Do the POCSAG calibration in a different way.

fix proper PDU reception and processing;

.gitignore

@@ -0,0 +1,5 @@
+*.o
+obj/
+bin/
+GitVersion.h
+build/

.gitmodules

@@ -0,0 +1,6 @@
+[submodule "STM32F4XX_Lib"]
+	path = STM32F4XX_Lib
+	url = https://github.com/juribeparada/STM32F4XX_Lib.git
+[submodule "STM32F7XX_Lib"]
+	path = STM32F7XX_Lib
+	url = https://github.com/juribeparada/STM32F7XX_Lib.git

CWIdTX.cpp

@@ -22,12 +22,12 @@
 #include "CWIdTX.h"
 
 q15_t TONE[] = {
-    0, 261, 518, 765, 1000, 1218, 1414, 1587, 1732, 1848, 1932, 1983, 2000, 1983, 1932, 1848, 1732, 1587, 1414, 1218, 1000, 765, 518, 261, 0, -261, -518, -765, -1000, -1218, -1414,
+    0, 518, 1000, 1414, 1732, 1932, 2000, 1932, 1732, 1414, 1000, 518, 0, -518, -1000, -1414, -1732, -1932, -2000, -1932, -1732, -1414, -1000, -518};
-    -1587, -1732, -1848, -1932, -1983, -2000, -1983, -1932, -1848, -1732, -1587, -1414, -1218, -1000, -765, -518, -261};
-q15_t SILENCE[] = {
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
-const uint8_t CYCLE_LENGTH = 48U;
+q15_t SILENCE[] = {
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+const uint8_t CYCLE_LENGTH = 24U;
 
 const uint8_t DOT_LENGTH = 50U;
 

CalDStarRX.cpp

@@ -24,7 +24,7 @@
 const unsigned int BUFFER_LENGTH = 200U;
 
 const uint32_t PLLMAX = 0x10000U;
-const uint32_t PLLINC = PLLMAX / DSTAR_RADIO_SYMBOL_LENGTH;
+const uint32_t PLLINC = PLLMAX / DSTAR_RADIO_BIT_LENGTH;
 const uint32_t INC    = PLLINC / 32U;
 
 // D-Star bit order version of 0x55 0x2D 0x16

CalPOCSAG.cpp

@@ -0,0 +1,49 @@
+/*
+ *   Copyright (C) 2019 by Florian Wolters DF2ET
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "Config.h"
+#include "Globals.h"
+#include "CalPOCSAG.h"
+
+
+CCalPOCSAG::CCalPOCSAG() :
+m_state(POCSAGCAL_IDLE)
+{
+}
+
+void CCalPOCSAG::process()
+{
+  if (m_state == POCSAGCAL_IDLE)
+    return;
+
+  uint16_t space = io.getSpace();
+  if (space <= 165U)
+    return;
+
+  pocsagTX.writeByte(0xAAU);
+}
+
+uint8_t CCalPOCSAG::write(const uint8_t* data, uint8_t length)
+{
+  if (length != 1U)
+    return 4U;
+
+  m_state = data[0U] == 1U ? POCSAGCAL_TX : POCSAGCAL_IDLE;
+
+  return 0U;
+}

CalPOCSAG.h

@@ -0,0 +1,41 @@
+/*
+ *   Copyright (C) 2019 by Florian Wolters DF2ET
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if !defined(CALPOCSAG_H)
+#define  CALPOCSAG_H
+
+#include "Config.h"
+
+enum POCSAGCAL {
+  POCSAGCAL_IDLE,
+  POCSAGCAL_TX
+};
+
+class CCalPOCSAG {
+public:
+  CCalPOCSAG();
+
+  void process();
+
+  uint8_t write(const uint8_t* data, uint8_t length);
+
+private:
+  POCSAGCAL m_state;
+};
+
+#endif

Config.h

@@ -45,7 +45,7 @@
 // #define ARDUINO_DUE_PAPA
 
 // For the ZUM V1.0 and V1.0.1 boards pin layout
-// #define ARDUINO_DUE_ZUM_V10
+#define ARDUINO_DUE_ZUM_V10
 
 // For the SQ6POG board
 // #define STM32F1_POG
@@ -55,7 +55,7 @@
 
 // For ST Nucleo-64 STM32F446RE board
 // #define STM32F4_NUCLEO_MORPHO_HEADER
-#define STM32F4_NUCLEO_ARDUINO_HEADER
+// #define STM32F4_NUCLEO_ARDUINO_HEADER
 
 // Use separate mode pins to switch external channel/filters/bandwidth for example
 // #define MODE_PINS
@@ -64,13 +64,13 @@
 // #define VK6MST_TEENSY_PI3_SHIELD_I2C
 
 // Pass RSSI information to the host
-#define SEND_RSSI_DATA
+// #define SEND_RSSI_DATA
 
 // Use the modem as a serial repeater for Nextion displays
 // #define SERIAL_REPEATER
 
 // To reduce CPU load, you can remove the DC blocker by commenting out the next line
-// #define USE_DCBLOCKER
+#define USE_DCBLOCKER
 
 // Constant Service LED once repeater is running 
 // Do not use if employing an external hardware watchdog 
@@ -82,7 +82,5 @@
 // Use the D-Star and DMR LEDs for POCSAG
 // #define USE_ALTERNATE_POCSAG_LEDS
 
-// Select BOXCAR Filter into D-Star
-// #define DSTARBOXCAR
-
 #endif
+

DMRDMORX.h

@@ -22,7 +22,7 @@
 #include "Config.h"
 #include "DMRDefines.h"
 
-const uint16_t DMO_BUFFER_LENGTH_SAMPLES = 2880U;   // 60ms at 48 kHz
+const uint16_t DMO_BUFFER_LENGTH_SAMPLES = 1440U;   // 60ms at 24 kHz
 
 enum DMORX_STATE {
   DMORXS_NONE,

DMRDMOTX.cpp

@@ -22,16 +22,10 @@
 #include "Globals.h"
 #include "DMRSlotType.h"
 
-// Generated using rcosdesign(0.2, 8, 10, 'sqrt') in MATLAB
+// Generated using rcosdesign(0.2, 8, 5, 'sqrt') in MATLAB
-static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 850, 592, 219, -234, -720, -1179,
+static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 850, 219, -720, -1548, -1795, -1172, 237, 1927, 3120, 3073, 1447, -1431, -4544, -6442,
-                                -1548, -1769, -1795, -1597, -1172, -544, 237, 1092, 1927, 2637,
+                                 -5735, -1633, 5651, 14822, 23810, 30367, 32767, 30367, 23810, 14822, 5651, -1633, -5735, -6442,
-                                3120, 3286, 3073, 2454, 1447, 116, -1431, -3043, -4544, -5739,
+                                 -4544, -1431, 1447, 3073, 3120, 1927, 237, -1172, -1795, -1548, -720, 219, 850}; // numTaps = 45, L = 5
-                                -6442, -6483, -5735, -4121, -1633, 1669, 5651, 10118, 14822,
-                                19484, 23810, 27520, 30367, 32156, 32767, 32156, 30367, 27520,
-                                23810, 19484, 14822, 10118, 5651, 1669, -1633, -4121, -5735,
-                                -6483, -6442, -5739, -4544, -3043, -1431, 116, 1447, 2454,
-                                3073, 3286, 3120, 2637, 1927, 1092, 237, -544, -1172, -1597,
-                                -1795, -1769, -1548, -1179, -720, -234, 219, 592, 850}; // numTaps = 90, L = 10
 const uint16_t RRC_0_2_FILTER_PHASE_LEN = 9U; // phaseLength = numTaps/L
 
 const q15_t DMR_LEVELA =  1362;
@@ -166,3 +160,4 @@ void CDMRDMOTX::setTXDelay(uint8_t delay)
   if (m_txDelay > 1200U)
     m_txDelay = 1200U;
 }
+

DMRDefines.h

@@ -1,5 +1,5 @@
 /*
- *   Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
+ *   Copyright (C) 2009-2016 by Jonathan Naylor G4KLX
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -19,7 +19,7 @@
 #if !defined(DMRDEFINES_H)
 #define  DMRDEFINES_H
 
-const unsigned int DMR_RADIO_SYMBOL_LENGTH = 10U;      // At 48 kHz sample rate
+const unsigned int DMR_RADIO_SYMBOL_LENGTH = 5U;      // At 24 kHz sample rate
 
 const unsigned int DMR_FRAME_LENGTH_BYTES   = 33U;
 const unsigned int DMR_FRAME_LENGTH_BITS    = DMR_FRAME_LENGTH_BYTES * 8U;

DMRIdleRX.cpp

@@ -24,8 +24,8 @@
 
 const q15_t SCALING_FACTOR = 19505;      // Q15(0.60)
 
-const uint8_t MAX_SYNC_SYMBOLS_ERRS = 4U;
+const uint8_t MAX_SYNC_SYMBOLS_ERRS = 2U;
-const uint8_t MAX_SYNC_BYTES_ERRS   = 6U;
+const uint8_t MAX_SYNC_BYTES_ERRS   = 3U;
 
 const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02U, 0x01U};
 

DMRSlotRX.cpp

@@ -22,15 +22,15 @@
 #include "DMRSlotType.h"
 #include "Utils.h"
 
-const uint16_t SCAN_START = 790U;
+const uint16_t SCAN_START = 400U;
-const uint16_t SCAN_END   = 920U;
+const uint16_t SCAN_END   = 490U;
 
 const q15_t SCALING_FACTOR = 19505;      // Q15(0.60)
 
-const uint8_t MAX_SYNC_SYMBOLS_ERRS = 4U;
+const uint8_t MAX_SYNC_SYMBOLS_ERRS = 2U;
-const uint8_t MAX_SYNC_BYTES_ERRS   = 6U;
+const uint8_t MAX_SYNC_BYTES_ERRS   = 3U;
 
-const uint8_t MAX_SYNC_LOST_FRAMES  = 26U;
+const uint8_t MAX_SYNC_LOST_FRAMES  = 13U;
 
 const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02U, 0x01U};
 
@@ -97,7 +97,7 @@ bool CDMRSlotRX::processSample(q15_t sample, uint16_t rssi)
     return m_state != DMRRXS_NONE;
 
   // Ensure that the buffer doesn't overflow
-  if (m_dataPtr > m_endPtr || m_dataPtr >= 1900U)
+  if (m_dataPtr > m_endPtr || m_dataPtr >= 900U)
     return m_state != DMRRXS_NONE;
 
   m_buffer[m_dataPtr] = sample;

DMRSlotRX.h

@@ -44,7 +44,7 @@ public:
 private:
   bool        m_slot;
   uint32_t    m_bitBuffer[DMR_RADIO_SYMBOL_LENGTH];
-  q15_t       m_buffer[1900U];
+  q15_t       m_buffer[900U];
   uint16_t    m_bitPtr;
   uint16_t    m_dataPtr;
   uint16_t    m_syncPtr;
@@ -62,7 +62,7 @@ private:
   DMRRX_STATE m_state;
   uint8_t     m_n;
   uint8_t     m_type;
-  uint16_t    m_rssi[1900U];
+  uint16_t    m_rssi[900U];
 
   void correlateSync(bool first);
   void samplesToBits(uint16_t start, uint8_t count, uint8_t* buffer, uint16_t offset, q15_t centre, q15_t threshold);

DMRTX.cpp

@@ -22,16 +22,10 @@
 #include "Globals.h"
 #include "DMRSlotType.h"
 
-// Generated using rcosdesign(0.2, 8, 10, 'sqrt') in MATLAB
+// Generated using rcosdesign(0.2, 8, 5, 'sqrt') in MATLAB
-static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 850, 592, 219, -234, -720, -1179,
+static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 850, 219, -720, -1548, -1795, -1172, 237, 1927, 3120, 3073, 1447, -1431, -4544, -6442,
-                                -1548, -1769, -1795, -1597, -1172, -544, 237, 1092, 1927, 2637,
+                                 -5735, -1633, 5651, 14822, 23810, 30367, 32767, 30367, 23810, 14822, 5651, -1633, -5735, -6442,
-                                3120, 3286, 3073, 2454, 1447, 116, -1431, -3043, -4544, -5739,
+                                 -4544, -1431, 1447, 3073, 3120, 1927, 237, -1172, -1795, -1548, -720, 219, 850}; // numTaps = 45, L = 5
-                                -6442, -6483, -5735, -4121, -1633, 1669, 5651, 10118, 14822,
-                                19484, 23810, 27520, 30367, 32156, 32767, 32156, 30367, 27520,
-                                23810, 19484, 14822, 10118, 5651, 1669, -1633, -4121, -5735,
-                                -6483, -6442, -5739, -4544, -3043, -1431, 116, 1447, 2454,
-                                3073, 3286, 3120, 2637, 1927, 1092, 237, -544, -1172, -1597,
-                                -1795, -1769, -1548, -1179, -720, -234, 219, 592, 850}; // numTaps = 90, L = 10
 const uint16_t RRC_0_2_FILTER_PHASE_LEN = 9U; // phaseLength = numTaps/L
 
 const q15_t DMR_LEVELA =  1362;

DStarDefines.h

@@ -1,5 +1,5 @@
 /*
- *   Copyright (C) 2009-2015,2017 by Jonathan Naylor G4KLX
+ *   Copyright (C) 2009-2015 by Jonathan Naylor G4KLX
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -19,50 +19,30 @@
 #if !defined(DSTARDEFINES_H)
 #define  DSTARDEFINES_H
 
-const unsigned int DSTAR_RADIO_SYMBOL_LENGTH = 10U;      // At 48 kHz sample rate
+const unsigned int DSTAR_RADIO_BIT_LENGTH = 5U;      // At 24 kHz sample rate
 
-const unsigned int DSTAR_HEADER_LENGTH_BYTES   = 41U;
+const unsigned int DSTAR_HEADER_LENGTH_BYTES = 41U;
+const unsigned int DSTAR_HEADER_LENGTH_BITS  = DSTAR_HEADER_LENGTH_BYTES * 8U;
 
-const unsigned int DSTAR_FEC_SECTION_LENGTH_BYTES   = 83U;
+const unsigned int DSTAR_FEC_SECTION_LENGTH_BYTES = 83U;
-const unsigned int DSTAR_FEC_SECTION_LENGTH_SYMBOLS = 660U;
+const unsigned int DSTAR_FEC_SECTION_LENGTH_BITS  = 660U;
-const unsigned int DSTAR_FEC_SECTION_LENGTH_SAMPLES = DSTAR_FEC_SECTION_LENGTH_SYMBOLS * DSTAR_RADIO_SYMBOL_LENGTH;
 
-const unsigned int DSTAR_DATA_LENGTH_BYTES   = 12U;
+const unsigned int DSTAR_DATA_LENGTH_BYTES = 12U;
-const unsigned int DSTAR_DATA_LENGTH_SYMBOLS = DSTAR_DATA_LENGTH_BYTES * 8U;
+const unsigned int DSTAR_DATA_LENGTH_BITS  = DSTAR_DATA_LENGTH_BYTES * 8U;
-const unsigned int DSTAR_DATA_LENGTH_SAMPLES = DSTAR_DATA_LENGTH_SYMBOLS * DSTAR_RADIO_SYMBOL_LENGTH;
 
-const unsigned int DSTAR_END_SYNC_LENGTH_BYTES = 6U;
+const uint8_t      DSTAR_EOT_BYTES[] = {0x55, 0x55, 0x55, 0x55, 0xC8, 0x7A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-const unsigned int DSTAR_END_SYNC_LENGTH_BITS  = DSTAR_END_SYNC_LENGTH_BYTES * 8U;
+const unsigned int DSTAR_EOT_LENGTH_BYTES = 6U;
+const unsigned int DSTAR_EOT_LENGTH_BITS  = DSTAR_EOT_LENGTH_BYTES * 8U;
 
-const unsigned int DSTAR_FRAME_SYNC_LENGTH_BYTES   = 3U;
+const uint8_t      DSTAR_DATA_SYNC_LENGTH_BYTES = 3U;
-const unsigned int DSTAR_FRAME_SYNC_LENGTH_SYMBOLS = DSTAR_FRAME_SYNC_LENGTH_BYTES * 8U;
+const uint8_t      DSTAR_DATA_SYNC_LENGTH_BITS  = DSTAR_DATA_SYNC_LENGTH_BYTES * 8U;
-const unsigned int DSTAR_FRAME_SYNC_LENGTH_SAMPLES = DSTAR_FRAME_SYNC_LENGTH_SYMBOLS * DSTAR_RADIO_SYMBOL_LENGTH;
 
-const unsigned int DSTAR_DATA_SYNC_LENGTH_BYTES   = 3U;
+const uint8_t      DSTAR_DATA_SYNC_BYTES[] = {0x9E, 0x8D, 0x32, 0x88, 0x26, 0x1A, 0x3F, 0x61, 0xE8, 0x55, 0x2D, 0x16};
-const unsigned int DSTAR_DATA_SYNC_LENGTH_SYMBOLS = DSTAR_DATA_SYNC_LENGTH_BYTES * 8U;
-const unsigned int DSTAR_DATA_SYNC_LENGTH_SAMPLES = DSTAR_DATA_SYNC_LENGTH_SYMBOLS * DSTAR_RADIO_SYMBOL_LENGTH;
 
-const uint8_t DSTAR_DATA_SYNC_BYTES[] = {0x9E, 0x8D, 0x32, 0x88, 0x26, 0x1A, 0x3F, 0x61, 0xE8, 0x55, 0x2D, 0x16};
+const uint8_t      DSTAR_SLOW_DATA_TYPE_TEXT   = 0x40U;
+const uint8_t      DSTAR_SLOW_DATA_TYPE_HEADER = 0x50U;
 
-// D-Star bit order version of 0x55 0x6E 0x0A
+const uint8_t      DSTAR_SCRAMBLER_BYTES[] = {0x70U, 0x4FU, 0x93U};
-const uint32_t DSTAR_FRAME_SYNC_DATA = 0x00557650U;
-const uint32_t DSTAR_FRAME_SYNC_MASK = 0x00FFFFFFU;
-const bool     DSTAR_FRAME_SYNC_SYMBOLS[] = {false, true, false, true, false, true, false, true, false, true, true, true, false, true, true, false, false, true, false, true, false, false, false, false};
-
-// D-Star bit order version of 0x55 0x2D 0x16
-const uint32_t DSTAR_DATA_SYNC_DATA = 0x00AAB468U;
-const uint32_t DSTAR_DATA_SYNC_MASK = 0x00FFFFFFU;
-const bool     DSTAR_DATA_SYNC_SYMBOLS[] = {true, false, true, false, true, false, true, false, true, false, true, true, false, true, false, false, false, true, true, false, true, false, false, false};
-
-// D-Star bit order version of 0x55 0x55 0xC8 0x7A
-const uint32_t DSTAR_END_SYNC_DATA = 0xAAAA135EU;
-const uint32_t DSTAR_END_SYNC_MASK = 0xFFFFFFFFU;
-const uint8_t  DSTAR_END_SYNC_BYTES[] = {0x55, 0x55, 0x55, 0x55, 0xC8, 0x7A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-
-const uint8_t  DSTAR_SLOW_DATA_TYPE_TEXT   = 0x40U;
-const uint8_t  DSTAR_SLOW_DATA_TYPE_HEADER = 0x50U;
-
-const uint8_t  DSTAR_SCRAMBLER_BYTES[] = {0x70U, 0x4FU, 0x93U};
 
 #endif
 

DStarRX.cpp

@@ -1,4 +1,3 @@
-
 /*
  *   Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
  *   Copyright (C) 2017 by Andy Uribe CA6JAU
@@ -23,12 +22,18 @@
 #include "DStarRX.h"
 #include "Utils.h"
 
-const unsigned int MAX_FRAMES = 150U;
+const unsigned int BUFFER_LENGTH = 200U;
+
+const uint32_t PLLMAX = 0x10000U;
+const uint32_t PLLINC = PLLMAX / DSTAR_RADIO_BIT_LENGTH;
+const uint32_t INC    = PLLINC / 32U;
+
+const unsigned int MAX_SYNC_BITS = 100U * DSTAR_DATA_LENGTH_BITS;
 
 // D-Star bit order version of 0x55 0x55 0x6E 0x0A
 const uint32_t FRAME_SYNC_DATA = 0x00557650U;
 const uint32_t FRAME_SYNC_MASK = 0x00FFFFFFU;
-const uint8_t  FRAME_SYNC_ERRS = 1U;
+const uint8_t  FRAME_SYNC_ERRS = 2U;
 
 // D-Star bit order version of 0x55 0x2D 0x16
 const uint32_t DATA_SYNC_DATA = 0x00AAB468U;
@@ -232,24 +237,14 @@ const uint16_t CCITT_TABLE[] = {
   0xf78fU, 0xe606U, 0xd49dU, 0xc514U, 0xb1abU, 0xa022U, 0x92b9U, 0x8330U,
   0x7bc7U, 0x6a4eU, 0x58d5U, 0x495cU, 0x3de3U, 0x2c6aU, 0x1ef1U, 0x0f78U};
 
-const uint16_t NOENDPTR = 9999U;
-
 CDStarRX::CDStarRX() :
+m_pll(0U),
+m_prev(false),
 m_rxState(DSRXS_NONE),
-m_bitBuffer(),
+m_patternBuffer(0x00U),
-m_headerBuffer(),
+m_rxBuffer(),
-m_dataBuffer(),
+m_rxBufferBits(0U),
-m_bitPtr(0U),
+m_dataBits(0U),
-m_headerPtr(0U),
-m_dataPtr(0U),
-m_startPtr(NOENDPTR),
-m_syncPtr(NOENDPTR),
-m_minSyncPtr(NOENDPTR),
-m_maxSyncPtr(NOENDPTR),
-m_maxFrameCorr(0),
-m_maxDataCorr(0),
-m_frameCount(0U),
-m_countdown(0U),
 m_mar(0U),
 m_pathMetric(),
 m_pathMemory0(),
@@ -264,20 +259,14 @@ m_rssiCount(0U)
 
 void CDStarRX::reset()
 {
-  m_rxState      = DSRXS_NONE;
+  m_pll           = 0U;
-  m_headerPtr    = 0U;
+  m_prev          = false;
-  m_dataPtr      = 0U;
+  m_rxState       = DSRXS_NONE;
-  m_bitPtr       = 0U;
+  m_patternBuffer = 0x00U;
-  m_maxFrameCorr = 0;
+  m_rxBufferBits  = 0U;
-  m_maxDataCorr  = 0;
+  m_dataBits      = 0U;
-  m_startPtr     = NOENDPTR;
+  m_rssiAccum     = 0U;
-  m_syncPtr      = NOENDPTR;
+  m_rssiCount     = 0U;
-  m_minSyncPtr   = NOENDPTR;
-  m_maxSyncPtr   = NOENDPTR;
-  m_frameCount   = 0U;
-  m_countdown    = 0U;
-  m_rssiAccum    = 0U;
-  m_rssiCount    = 0U;
 }
 
 void CDStarRX::samples(const q15_t* samples, const uint16_t* rssi, uint8_t length)
@@ -286,117 +275,125 @@ void CDStarRX::samples(const q15_t* samples, const uint16_t* rssi, uint8_t lengt
     m_rssiAccum += rssi[i];
     m_rssiCount++;
 
-    q15_t sample = samples[i];
+    bool bit = samples[i] < 0;
 
-    m_bitBuffer[m_bitPtr] <<= 1;
+    if (bit != m_prev) {
-    if (sample < 0)
+      if (m_pll < (PLLMAX / 2U))
-      m_bitBuffer[m_bitPtr] |= 0x01U;
+        m_pll += INC;
-
+      else
-    m_dataBuffer[m_dataPtr] = sample;
+        m_pll -= INC;
-
-    switch (m_rxState) {
-      case DSRXS_HEADER:
-        processHeader(sample);
-        break;
-      case DSRXS_DATA:
-        processData();
-        break;
-      default:
-        processNone(sample);
-        break;
     }
 
-    m_dataPtr++;
+    m_prev = bit;
-    if (m_dataPtr >= DSTAR_DATA_LENGTH_SAMPLES)
-      m_dataPtr = 0U;
 
-    m_bitPtr++;
+    m_pll += PLLINC;
-    if (m_bitPtr >= DSTAR_RADIO_SYMBOL_LENGTH)
+
-      m_bitPtr = 0U;
+    if (m_pll >= PLLMAX) {
+      m_pll -= PLLMAX;
+
+      switch (m_rxState) {
+        case DSRXS_NONE:
+          processNone(bit);
+          break;
+        case DSRXS_HEADER:
+          processHeader(bit);
+          break;
+        case DSRXS_DATA:
+          processData(bit);
+          break;
+        default:
+          break;
+      }
+    }
   }
 }
 
-void CDStarRX::processNone(q15_t sample)
+void CDStarRX::processNone(bool bit)
 {
+  m_patternBuffer <<= 1;
+  if (bit)
+    m_patternBuffer |= 0x01U;
+
   // Fuzzy matching of the frame sync sequence
-  bool ret = correlateFrameSync();
+  if (countBits32((m_patternBuffer & FRAME_SYNC_MASK) ^ FRAME_SYNC_DATA) <= FRAME_SYNC_ERRS) {
-  if (ret) {
+    DEBUG1("DStarRX: found frame sync in None");
-    m_countdown = 5U;
+
-	
+    ::memset(m_rxBuffer, 0x00U, DSTAR_FEC_SECTION_LENGTH_BYTES);
-    m_headerBuffer[m_headerPtr] = sample;
+    m_rxBufferBits = 0U;
-    m_headerPtr++;
 
     m_rssiAccum = 0U;
     m_rssiCount = 0U;
 
     m_rxState = DSRXS_HEADER;
-
     return;
   }
 
-  // Fuzzy matching of the data sync bit sequence
+  // Exact matching of the data sync bit sequence
-  ret = correlateDataSync();
+  if (countBits32((m_patternBuffer & DATA_SYNC_MASK) ^ DATA_SYNC_DATA) == 0U) {
-  if (ret) {
     DEBUG1("DStarRX: found data sync in None");
 
     io.setDecode(true);
     io.setADCDetection(true);
 
-    m_rxState = DSRXS_DATA;
+    // Suppress RSSI on the dummy sync message
+    m_rssiAccum = 0U;
+    m_rssiCount = 0U;
+
+    ::memcpy(m_rxBuffer, DSTAR_DATA_SYNC_BYTES, DSTAR_DATA_LENGTH_BYTES);
+    writeRSSIData(m_rxBuffer);
+
+    ::memset(m_rxBuffer, 0x00U, DSTAR_DATA_LENGTH_BYTES + 2U);
+    m_rxBufferBits = 0U;
+
+    m_dataBits  = MAX_SYNC_BITS;
+    m_rxState   = DSRXS_DATA;
+    return;
   }
 }
 
-void CDStarRX::processHeader(q15_t sample)
+void CDStarRX::processHeader(bool bit)
 {
-  if (m_countdown > 0U) {
+  m_patternBuffer <<= 1;
-    correlateFrameSync();
+  if (bit)
-    m_countdown--;
+    m_patternBuffer |= 0x01U;
-  }
 
-  m_headerBuffer[m_headerPtr] = sample;
+  WRITE_BIT2(m_rxBuffer, m_rxBufferBits, bit);
-  m_headerPtr++;
+  m_rxBufferBits++;
 
   // A full FEC header
-  if (m_headerPtr == (DSTAR_FEC_SECTION_LENGTH_SAMPLES + DSTAR_RADIO_SYMBOL_LENGTH)) {
+  if (m_rxBufferBits == DSTAR_FEC_SECTION_LENGTH_BITS) {
-    uint8_t buffer[DSTAR_FEC_SECTION_LENGTH_BYTES];
+    // Process the scrambling, interleaving and FEC, then return if the chcksum was correct
-    samplesToBits(m_headerBuffer, DSTAR_RADIO_SYMBOL_LENGTH, DSTAR_FEC_SECTION_LENGTH_SYMBOLS, buffer, DSTAR_FEC_SECTION_LENGTH_SAMPLES);
+    unsigned char header[DSTAR_HEADER_LENGTH_BYTES];
-
+    bool ok = rxHeader(m_rxBuffer, header);
-    // Process the scrambling, interleaving and FEC, then return true if the chcksum was correct
+    if (ok) {
-    uint8_t header[DSTAR_HEADER_LENGTH_BYTES];
-    bool ok = rxHeader(buffer, header);
-    if (!ok) {
-      // The checksum failed, return to looking for syncs
-      m_rxState = DSRXS_NONE;
-      m_maxFrameCorr = 0;
-      m_maxDataCorr  = 0;
-    } else {
       io.setDecode(true);
       io.setADCDetection(true);
 
       writeRSSIHeader(header);
+
+      ::memset(m_rxBuffer, 0x00U, DSTAR_DATA_LENGTH_BYTES + 2U);
+      m_rxBufferBits = 0U;
+
+      m_rxState  = DSRXS_DATA;
+      m_dataBits = MAX_SYNC_BITS;
+    } else {
+      // The checksum failed, return to looking for syncs
+      m_rxState = DSRXS_NONE;
     }
   }
-
-  // Ready to start the first data section
-  if (m_headerPtr == (DSTAR_FEC_SECTION_LENGTH_SAMPLES + 2U * DSTAR_RADIO_SYMBOL_LENGTH)) {
-    m_frameCount = 0U;
-    m_dataPtr    = 0U;
-
-    m_startPtr   = 952U;
-    m_syncPtr    = 942U;
-    m_maxSyncPtr = 944U;
-    m_minSyncPtr = 940U;
-
-    DEBUG5("DStarRX: calc start/sync/max/min", m_startPtr, m_syncPtr, m_maxSyncPtr, m_minSyncPtr);
-
-    m_rxState = DSRXS_DATA;
-  }
 }
 
-void CDStarRX::processData()
+void CDStarRX::processData(bool bit)
 {
+  m_patternBuffer <<= 1;
+  if (bit)
+    m_patternBuffer |= 0x01U;
+
+  WRITE_BIT2(m_rxBuffer, m_rxBufferBits, bit);
+  m_rxBufferBits++;
+
   // Fuzzy matching of the end frame sequences
-  if (countBits32((m_bitBuffer[m_bitPtr] & DSTAR_END_SYNC_MASK) ^ DSTAR_END_SYNC_DATA) <= END_SYNC_ERRS) {
+  if (countBits32((m_patternBuffer & END_SYNC_MASK) ^ END_SYNC_DATA) <= END_SYNC_ERRS) {
     DEBUG1("DStarRX: Found end sync in Data");
 
     io.setDecode(false);
@@ -404,24 +401,35 @@ void CDStarRX::processData()
 
     serial.writeDStarEOT();
 
-    m_maxFrameCorr = 0;
-    m_maxDataCorr  = 0;
-
     m_rxState = DSRXS_NONE;
     return;
   }
 
   // Fuzzy matching of the data sync bit sequence
-  if (m_minSyncPtr < m_maxSyncPtr) {
+  bool syncSeen = false;
-    if (m_dataPtr >= m_minSyncPtr && m_dataPtr <= m_maxSyncPtr)
+  if (m_rxBufferBits >= (DSTAR_DATA_LENGTH_BITS - 3U)) {
-      correlateDataSync();
+    if (countBits32((m_patternBuffer & DATA_SYNC_MASK) ^ DATA_SYNC_DATA) <= DATA_SYNC_ERRS) {
-  } else {
+      m_rxBufferBits = DSTAR_DATA_LENGTH_BITS;
-    if (m_dataPtr >= m_minSyncPtr || m_dataPtr <= m_maxSyncPtr)
+      m_dataBits     = MAX_SYNC_BITS;
-      correlateDataSync();
+      syncSeen       = true;
+    }
   }
 
-  // We've not seen a data sync for too long, signal RXLOST and change to RX_NONE
+  // Check to see if the sync is arriving late
-  if (m_frameCount >= MAX_FRAMES) {
+  if (m_rxBufferBits == DSTAR_DATA_LENGTH_BITS && !syncSeen) {
+    for (uint8_t i = 1U; i <= 3U; i++) {
+      uint32_t syncMask = DATA_SYNC_MASK >> i;
+      uint32_t syncData = DATA_SYNC_DATA >> i;
+      if (countBits32((m_patternBuffer & syncMask) ^ syncData) <= DATA_SYNC_ERRS) {
+        m_rxBufferBits -= i;
+        break;
+      }
+    }
+  }
+
+  m_dataBits--;
+
+  if (m_dataBits == 0U) {
     DEBUG1("DStarRX: data sync timed out, lost lock");
 
     io.setDecode(false);
@@ -429,35 +437,24 @@ void CDStarRX::processData()
 
     serial.writeDStarLost();
 
-    m_maxFrameCorr = 0;
-    m_maxDataCorr  = 0;
-
     m_rxState = DSRXS_NONE;
     return;
   }
 
-  // Send a data frame to the host if the required number of bits have been received
+  // Send a data frame to the host if the required number of bits have been received, or if a data sync has been seen
-  if (m_dataPtr == m_maxSyncPtr) {
+  if (m_rxBufferBits == DSTAR_DATA_LENGTH_BITS) {
-    uint8_t buffer[DSTAR_DATA_LENGTH_BYTES + 2U];
+    if (syncSeen) {
-    samplesToBits(m_dataBuffer, m_startPtr, DSTAR_DATA_LENGTH_SYMBOLS, buffer, DSTAR_DATA_LENGTH_SAMPLES);
+      m_rxBuffer[9U]  = DSTAR_DATA_SYNC_BYTES[9U];
-
+      m_rxBuffer[10U] = DSTAR_DATA_SYNC_BYTES[10U];
-    if ((m_frameCount % 21U) == 0U) {
+      m_rxBuffer[11U] = DSTAR_DATA_SYNC_BYTES[11U];
-      if (m_frameCount == 0U) {
+	    writeRSSIData(m_rxBuffer);
-        buffer[9U]  = DSTAR_DATA_SYNC_BYTES[9U];
-        buffer[10U] = DSTAR_DATA_SYNC_BYTES[10U];
-        buffer[11U] = DSTAR_DATA_SYNC_BYTES[11U];
-        DEBUG5("DStarRX: found start/sync/max/min", m_startPtr, m_syncPtr, m_maxSyncPtr, m_minSyncPtr);
-      }
-
-      writeRSSIData(buffer);
     } else {
-      serial.writeDStarData(buffer, DSTAR_DATA_LENGTH_BYTES);
+	    serial.writeDStarData(m_rxBuffer, DSTAR_DATA_LENGTH_BYTES);
-    }
+	  }
 
-    m_frameCount++;
+    // Start the next frame
-
+    ::memset(m_rxBuffer, 0x00U, DSTAR_DATA_LENGTH_BYTES + 2U);
-    m_maxFrameCorr = 0;
+    m_rxBufferBits = 0U;
-    m_maxDataCorr  = 0;
   }
 }
 
@@ -503,105 +500,6 @@ void CDStarRX::writeRSSIData(unsigned char* data)
   m_rssiCount = 0U;
 }
 
-bool CDStarRX::correlateFrameSync()
-{
-  if (countBits32((m_bitBuffer[m_bitPtr] & DSTAR_FRAME_SYNC_MASK) ^ DSTAR_FRAME_SYNC_DATA) <= FRAME_SYNC_ERRS) {
-    uint16_t ptr = m_dataPtr + DSTAR_DATA_LENGTH_SAMPLES - DSTAR_FRAME_SYNC_LENGTH_SAMPLES + DSTAR_RADIO_SYMBOL_LENGTH;
-    if (ptr >= DSTAR_DATA_LENGTH_SAMPLES)
-      ptr -= DSTAR_DATA_LENGTH_SAMPLES;
-
-    q31_t corr = 0;
-
-    for (uint8_t i = 0U; i < DSTAR_FRAME_SYNC_LENGTH_SYMBOLS; i++) {
-      q15_t val = m_dataBuffer[ptr];
-
-      if (DSTAR_FRAME_SYNC_SYMBOLS[i])
-        corr -= val;
-      else
-        corr += val;
-
-      ptr += DSTAR_RADIO_SYMBOL_LENGTH;
-      if (ptr >= DSTAR_DATA_LENGTH_SAMPLES)
-        ptr -= DSTAR_DATA_LENGTH_SAMPLES;
-    }
-
-    if (corr > m_maxFrameCorr) {
-      m_maxFrameCorr = corr;
-      m_headerPtr    = 0U;
-      return true;
-    }
-  }
-
-  return false;
-}
-
-bool CDStarRX::correlateDataSync()
-{
-  uint8_t maxErrs = 0U;
-  if (m_rxState == DSRXS_DATA)
-    maxErrs = DATA_SYNC_ERRS;
-
-  if (countBits32((m_bitBuffer[m_bitPtr] & DSTAR_DATA_SYNC_MASK) ^ DSTAR_DATA_SYNC_DATA) <= maxErrs) {
-    uint16_t ptr = m_dataPtr + DSTAR_DATA_LENGTH_SAMPLES - DSTAR_DATA_SYNC_LENGTH_SAMPLES + DSTAR_RADIO_SYMBOL_LENGTH;
-    if (ptr >= DSTAR_DATA_LENGTH_SAMPLES)
-      ptr -= DSTAR_DATA_LENGTH_SAMPLES;
-
-    q31_t corr = 0;
-
-    for (uint8_t i = 0U; i < DSTAR_DATA_SYNC_LENGTH_SYMBOLS; i++) {
-      q15_t val = m_dataBuffer[ptr];
-
-      if (DSTAR_DATA_SYNC_SYMBOLS[i])
-        corr -= val;
-      else
-        corr += val;
-
-      ptr += DSTAR_RADIO_SYMBOL_LENGTH;
-      if (ptr >= DSTAR_DATA_LENGTH_SAMPLES)
-        ptr -= DSTAR_DATA_LENGTH_SAMPLES;
-    }
-
-    if (corr > m_maxDataCorr) {
-      m_maxDataCorr = corr;
-      m_frameCount  = 0U;
-
-      m_syncPtr    = m_dataPtr;
-
-      m_startPtr   = m_dataPtr + DSTAR_RADIO_SYMBOL_LENGTH;
-      if (m_startPtr >= DSTAR_DATA_LENGTH_SAMPLES)
-        m_startPtr -= DSTAR_DATA_LENGTH_SAMPLES;
-
-      m_maxSyncPtr = m_syncPtr + 1U;
-      if (m_maxSyncPtr >= DSTAR_DATA_LENGTH_SAMPLES)
-        m_maxSyncPtr -= DSTAR_DATA_LENGTH_SAMPLES;
-
-      m_minSyncPtr = m_syncPtr + DSTAR_DATA_LENGTH_SAMPLES - 1U;
-      if (m_minSyncPtr >= DSTAR_DATA_LENGTH_SAMPLES)
-        m_minSyncPtr -= DSTAR_DATA_LENGTH_SAMPLES;
-
-      return true;
-    }
-  }
-
-  return false;
-}
-
-void CDStarRX::samplesToBits(const q15_t* inBuffer, uint16_t start, uint16_t count, uint8_t* outBuffer, uint16_t limit)
-{
-  for (uint16_t i = 0U; i < count; i++) {
-    q15_t sample = inBuffer[start];
-
-    if (sample < 0)
-      WRITE_BIT2(outBuffer, i, true);
-    else
-      WRITE_BIT2(outBuffer, i, false);
-
-    start += DSTAR_RADIO_SYMBOL_LENGTH;
-    if (start >= limit)
-      start -= limit;
-  }
-}
-
 bool CDStarRX::rxHeader(uint8_t* in, uint8_t* out)
 {
   int i;

DStarRX.h

@@ -37,21 +37,13 @@ public:
   void reset();
 
 private:
+  uint32_t     m_pll;
+  bool         m_prev;
   DSRX_STATE   m_rxState;
-  uint32_t     m_bitBuffer[DSTAR_RADIO_SYMBOL_LENGTH];
+  uint32_t     m_patternBuffer;
-  q15_t        m_headerBuffer[DSTAR_FEC_SECTION_LENGTH_SAMPLES + 2U * DSTAR_RADIO_SYMBOL_LENGTH];
+  uint8_t      m_rxBuffer[100U];
-  q15_t        m_dataBuffer[DSTAR_DATA_LENGTH_SAMPLES];
+  unsigned int m_rxBufferBits;
-  uint16_t     m_bitPtr;
+  unsigned int m_dataBits;
-  uint16_t     m_headerPtr;
-  uint16_t     m_dataPtr;
-  uint16_t     m_startPtr;
-  uint16_t     m_syncPtr;
-  uint16_t     m_minSyncPtr;
-  uint16_t     m_maxSyncPtr;
-  q31_t        m_maxFrameCorr;
-  q31_t        m_maxDataCorr;
-  uint16_t     m_frameCount;
-  uint8_t      m_countdown;
   unsigned int m_mar;
   int          m_pathMetric[4U];
   unsigned int m_pathMemory0[42U];
@@ -62,12 +54,9 @@ private:
   uint32_t     m_rssiAccum;
   uint16_t     m_rssiCount;
   
-  void    processNone(q15_t sample);
+  void    processNone(bool bit);
-  void    processHeader(q15_t sample);
+  void    processHeader(bool bit);
-  void    processData();
+  void    processData(bool bit);
-  bool    correlateFrameSync();
-  bool    correlateDataSync();
-  void    samplesToBits(const q15_t* inBuffer, uint16_t start, uint16_t count, uint8_t* outBuffer, uint16_t limit);
   void    writeRSSIHeader(unsigned char* header);
   void    writeRSSIData(unsigned char* data);
   bool    rxHeader(uint8_t* in, uint8_t* out);

DStarTX.cpp

@@ -27,10 +27,8 @@ const uint8_t BIT_SYNC = 0xAAU;
 
 const uint8_t FRAME_SYNC[] = {0xEAU, 0xA6U, 0x00U};
 
-// Generated using gaussfir(0.35, 1, 10) in MATLAB
+// Generated using gaussfir(0.35, 1, 5) in MATLAB
-static q15_t GAUSSIAN_0_35_FILTER[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1001, 1942, 3514, 5930,
+static q15_t GAUSSIAN_0_35_FILTER[] = {0, 0, 0, 0, 1001, 3514, 9333, 18751, 28499, 32767, 28499, 18751, 9333, 3514, 1001}; // numTaps = 15, L = 5
-                                      9333, 13699, 18751, 23938, 28499, 31644, 32767, 31644,
-                                      28499, 23938, 18751, 13699, 9333, 5930, 3514, 1942, 1001}; // numTaps = 30, L = 10
 const uint16_t GAUSSIAN_0_35_FILTER_PHASE_LEN = 3U; // phaseLength = numTaps/L
 
 const q15_t DSTAR_LEVEL0 = -841;
@@ -198,9 +196,9 @@ m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(60U)       // 100ms
 {
-  ::memset(m_modState, 0x00U, 15U * sizeof(q15_t));
+  ::memset(m_modState, 0x00U, 20U * sizeof(q15_t));
 
-  m_modFilter.L           = DSTAR_RADIO_SYMBOL_LENGTH;
+  m_modFilter.L           = DSTAR_RADIO_BIT_LENGTH;
   m_modFilter.phaseLength = GAUSSIAN_0_35_FILTER_PHASE_LEN;
   m_modFilter.pCoeffs     = GAUSSIAN_0_35_FILTER;
   m_modFilter.pState      = m_modState;
@@ -254,8 +252,8 @@ void CDStarTX::process()
     m_buffer.get();
 
     for (uint8_t j = 0U; j < 3U; j++) {
-      for (uint8_t i = 0U; i < DSTAR_END_SYNC_LENGTH_BYTES; i++)
+      for (uint8_t i = 0U; i < DSTAR_EOT_LENGTH_BYTES; i++)
-        m_poBuffer[m_poLen++] = DSTAR_END_SYNC_BYTES[i];
+        m_poBuffer[m_poLen++] = DSTAR_EOT_BYTES[i];
     }
      
     m_poPtr = 0U;
@@ -264,11 +262,11 @@ void CDStarTX::process()
   if (m_poLen > 0U) {
     uint16_t space = io.getSpace();
     
-    while (space > (8U * DSTAR_RADIO_SYMBOL_LENGTH)) {
+    while (space > (8U * DSTAR_RADIO_BIT_LENGTH)) {
       uint8_t c = m_poBuffer[m_poPtr++];
       writeByte(c);
 
-      space -= 8U * DSTAR_RADIO_SYMBOL_LENGTH;
+      space -= 8U * DSTAR_RADIO_BIT_LENGTH;
       
       if (m_poPtr >= m_poLen) {
         m_poPtr = 0U;
@@ -390,7 +388,7 @@ void CDStarTX::txHeader(const uint8_t* in, uint8_t* out) const
     if (i < 660U) {
       if (d & 0x08U)
         out[INTERLEAVE_TABLE_TX[i * 2U]] |= (0x01U << INTERLEAVE_TABLE_TX[i * 2U + 1U]);
-        i++;
+      i++;
 
       if (d & 0x04U)
         out[INTERLEAVE_TABLE_TX[i * 2U]] |= (0x01U << INTERLEAVE_TABLE_TX[i * 2U + 1U]);
@@ -414,7 +412,7 @@ void CDStarTX::txHeader(const uint8_t* in, uint8_t* out) const
 void CDStarTX::writeByte(uint8_t c)
 {
   q15_t inBuffer[8U];
-  q15_t outBuffer[DSTAR_RADIO_SYMBOL_LENGTH * 8U];
+  q15_t outBuffer[DSTAR_RADIO_BIT_LENGTH * 8U];
 
   uint8_t mask = 0x01U;
 
@@ -429,7 +427,7 @@ void CDStarTX::writeByte(uint8_t c)
 
   ::arm_fir_interpolate_q15(&m_modFilter, inBuffer, outBuffer, 8U);
   
-  io.write(STATE_DSTAR, outBuffer, DSTAR_RADIO_SYMBOL_LENGTH * 8U);
+  io.write(STATE_DSTAR, outBuffer, DSTAR_RADIO_BIT_LENGTH * 8U);
 }
 
 void CDStarTX::setTXDelay(uint8_t delay)

DStarTX.h

@@ -40,7 +40,7 @@ public:
 private:
   CSerialRB                        m_buffer;
   arm_fir_interpolate_instance_q15 m_modFilter;
-  q15_t                            m_modState[15U];    // blockSize + phaseLength - 1, 8 + 3 - 1 plus some spare
+  q15_t                            m_modState[20U];    // blockSize + phaseLength - 1, 8 + 9 - 1 plus some spare
   uint8_t                          m_poBuffer[600U];
   uint16_t                         m_poLen;
   uint16_t                         m_poPtr;

GitVersion.h

@@ -1 +0,0 @@
-#define GITVERSION "0000000"

Globals.h

@@ -60,7 +60,9 @@ enum MMDVM_STATE {
   STATE_RSSICAL   = 96,
   STATE_CWID      = 97,
   STATE_DMRCAL    = 98,
-  STATE_DSTARCAL  = 99
+  STATE_DSTARCAL  = 99,
+  STATE_INTCAL    = 100,
+  STATE_POCSAGCAL = 101
 };
 
 #include "SerialPort.h"
@@ -83,6 +85,7 @@ enum MMDVM_STATE {
 #include "CalDMR.h"
 #include "CalP25.h"
 #include "CalNXDN.h"
+#include "CalPOCSAG.h"
 #include "CalRSSI.h"
 #include "CWIdTX.h"
 #include "Debug.h"
@@ -94,8 +97,8 @@ const uint8_t  MARK_NONE  = 0x00U;
 
 const uint16_t RX_BLOCK_SIZE = 2U;
 
-const uint16_t TX_RINGBUFFER_SIZE = 1000U;
+const uint16_t TX_RINGBUFFER_SIZE = 500U;
-const uint16_t RX_RINGBUFFER_SIZE = 1200U;
+const uint16_t RX_RINGBUFFER_SIZE = 600U;
 
 #if defined(STM32F105xC) || defined(__MK20DX256__)
 const uint16_t TX_BUFFER_LEN = 2000U;
@@ -146,6 +149,7 @@ extern CCalDStarTX calDStarTX;
 extern CCalDMR     calDMR;
 extern CCalP25     calP25;
 extern CCalNXDN    calNXDN;
+extern CCalPOCSAG  calPOCSAG;
 extern CCalRSSI    calRSSI;
 
 extern CCWIdTX cwIdTX;

IO.cpp

@@ -22,41 +22,35 @@
 #include "Globals.h"
 #include "IO.h"
 
-// Generated using [b, a] = butter(1, 0.0005) in MATLAB
+// Generated using [b, a] = butter(1, 0.001) in MATLAB
-static q31_t   DC_FILTER[] = {1685306, 0, 1685306, 0, 2144113034, 0}; // {b0, 0, b1, b2, -a1, -a2}
+static q31_t   DC_FILTER[] = {3367972, 0, 3367972, 0, 2140747704, 0}; // {b0, 0, b1, b2, -a1, -a2}
 const uint32_t DC_FILTER_STAGES = 1U; // One Biquad stage
 
+// Generated using rcosdesign(0.2, 8, 5, 'sqrt') in MATLAB
+static q15_t RRC_0_2_FILTER[] = {401, 104, -340, -731, -847, -553, 112, 909, 1472, 1450, 683, -675, -2144, -3040, -2706, -770, 2667, 6995,
+                                 11237, 14331, 15464, 14331, 11237, 6995, 2667, -770, -2706, -3040, -2144, -675, 683, 1450, 1472, 909, 112,
+                                 -553, -847, -731, -340, 104, 401, 0};
+const uint16_t RRC_0_2_FILTER_LEN = 42U;
+
 // Generated using rcosdesign(0.2, 8, 10, 'sqrt') in MATLAB
-static q15_t RRC_0_2_FILTER[] = {284, 198, 73, -78, -240, -393, -517, -590, -599, -533, -391, -181, 79, 364, 643, 880, 1041, 1097, 1026, 819,
+static q15_t NXDN_0_2_FILTER[] = {284, 198, 73, -78, -240, -393, -517, -590, -599, -533, -391, -181, 79, 364, 643, 880, 1041, 1097, 1026, 819,
                                   483, 39, -477, -1016, -1516, -1915, -2150, -2164, -1914, -1375, -545, 557, 1886, 3376, 4946, 6502, 7946, 9184,
                                   10134, 10731, 10935, 10731, 10134, 9184, 7946, 6502, 4946, 3376, 1886, 557, -545, -1375, -1914, -2164, -2150,
                                   -1915, -1516, -1016, -477, 39, 483, 819, 1026, 1097, 1041, 880, 643, 364, 79, -181, -391, -533, -599, -590,
                                   -517, -393, -240, -78, 73, 198, 284, 0};
-const uint16_t RRC_0_2_FILTER_LEN = 82U;
+const uint16_t NXDN_0_2_FILTER_LEN = 82U;
 
-// Generated using rcosdesign(0.2, 8, 20, 'sqrt') in MATLAB
+static q15_t NXDN_ISINC_FILTER[] = {790, -1085, -1073, -553, 747, 2341, 3156, 2152, -893, -4915, -7834, -7536, -3102, 4441, 12354, 17394, 17394,
-static q15_t NXDN_0_2_FILTER[] = {201, 174, 140, 99, 52, 0, -55, -112, -170, -226, -278, -325, -365, -397, -417, -427, -424, -407, -377, -333, -277, -208,
+                                   12354, 4441, -3102, -7536, -7834, -4915, -893, 2152, 3156, 2341, 747, -553, -1073, -1085, 790};
-								  -128, -40, 56, 156, 258, 358, 455, 544, 622, 687, 736, 766, 775, 762, 725, 664, 579, 471, 342, 193, 27, -151, -338, -528,
-								  -718, -901, -1072, -1225, -1354, -1454, -1520, -1547, -1530, -1466, -1353, -1189, -972, -704, -385, -18, 394, 846, 1333,
-								  1850, 2388, 2940, 3498, 4053, 4598, 5122, 5619, 6079, 6494, 6859, 7166, 7410, 7588, 7696, 7732, 7696, 7588, 7410, 7166,
-								  6859, 6494, 6079, 5619, 5122, 4598, 4053, 3498, 2940, 2388, 1850, 1333, 846, 394, -18, -385, -704, -972, -1189, -1353,
-								  -1466, -1530, -1547, -1520, -1454, -1354, -1225, -1072, -901, -718, -528, -338, -151, 27, 193, 342, 471, 579, 664, 725,
-								  762, 775, 766, 736, 687, 622, 544, 455, 358, 258, 156, 56, -40, -128, -208, -277, -333, -377, -407, -424, -427, -417, -397,
-								  -365, -325, -278, -226, -170, -112, -55, 0, 52, 99, 140, 174, 201, 0};
-const uint16_t NXDN_0_2_FILTER_LEN = 162U;
-
-static q15_t NXDN_ISINC_FILTER[] = {7616, -1333, -1856, -2611, -3399, -4006, -4230, -3918, -2988, -1458, 561, 2867, 5200, 7276, 8832, 9665,
-                                    9665, 8832, 7276, 5200, 2867, 561, -1458, -2988, -3918, -4230, -4006, -3399, -2611, -1856, -1333, 7616};
 const uint16_t NXDN_ISINC_FILTER_LEN = 32U;
 
-#if !defined (DSTARBOXCAR)
+// Generated using gaussfir(0.5, 4, 5) in MATLAB
-// Generated using gaussfir(0.5, 4, 10) in MATLAB
+static q15_t   GAUSSIAN_0_5_FILTER[] = {8, 104, 760, 3158, 7421, 9866, 7421, 3158, 760, 104, 8, 0};
-static q15_t   GAUSSIAN_0_5_FILTER[] = {1, 4, 15, 52, 151, 380, 832, 1579, 2599, 3710, 4594, 4933, 4594, 3710, 2599, 1579, 832, 380, 151, 52, 15, 4, 1, 0};
+const uint16_t GAUSSIAN_0_5_FILTER_LEN = 12U;
-const uint16_t GAUSSIAN_0_5_FILTER_LEN = 24U;
+
-#endif
 // One symbol boxcar filter
-static q15_t   BOXCAR_FILTER[] = {6000, 6000, 6000, 6000, 6000, 6000, 6000, 6000, 6000, 6000, 0, 0};
+static q15_t   BOXCAR_FILTER[] = {12000, 12000, 12000, 12000, 12000, 0};
-const uint16_t BOXCAR_FILTER_LEN = 12U;
+const uint16_t BOXCAR_FILTER_LEN = 6U;
 
 const uint16_t DC_OFFSET = 2048U;
 
@@ -68,16 +62,12 @@ m_rssiBuffer(RX_RINGBUFFER_SIZE),
 m_dcFilter(),
 m_dcState(),
 m_rrcFilter(),
-#if !defined (DSTARBOXCAR)
 m_gaussianFilter(),
-#endif
 m_boxcarFilter(),
 m_nxdnFilter(),
 m_nxdnISincFilter(),
 m_rrcState(),
-#if !defined (DSTARBOXCAR)
 m_gaussianState(),
-#endif
 m_boxcarState(),
 m_nxdnState(),
 m_nxdnISincState(),
@@ -100,14 +90,12 @@ m_dacOverflow(0U),
 m_watchdog(0U),
 m_lockout(false)
 {
-  ::memset(m_rrcState,      	0x00U,  140U * sizeof(q15_t));
+  ::memset(m_rrcState,      0x00U,  70U * sizeof(q15_t));
-#if !defined (DSTARBOXCAR)
+  ::memset(m_gaussianState, 0x00U,  40U * sizeof(q15_t));
-  ::memset(m_gaussianState, 	0x00U,   80U * sizeof(q15_t));
+  ::memset(m_boxcarState,   0x00U,  30U * sizeof(q15_t));
-#endif
+  ::memset(m_nxdnState,     0x00U, 110U * sizeof(q15_t));
-  ::memset(m_boxcarState,   	0x00U,   60U * sizeof(q15_t));
+  ::memset(m_nxdnISincState, 0x00U, 60U * sizeof(q15_t));
-  ::memset(m_nxdnState,     	0x00U, 	220U * sizeof(q15_t));
+  ::memset(m_dcState,       0x00U,   4U * sizeof(q31_t));
-  ::memset(m_nxdnISincState, 	0x00U, 	 60U * sizeof(q15_t));
-  ::memset(m_dcState,       	0x00U,    4U * sizeof(q31_t));
 
   m_dcFilter.numStages = DC_FILTER_STAGES;
   m_dcFilter.pState    = m_dcState;
@@ -117,11 +105,11 @@ m_lockout(false)
   m_rrcFilter.numTaps = RRC_0_2_FILTER_LEN;
   m_rrcFilter.pState  = m_rrcState;
   m_rrcFilter.pCoeffs = RRC_0_2_FILTER;
-#if !defined (DSTARBOXCAR)
+
   m_gaussianFilter.numTaps = GAUSSIAN_0_5_FILTER_LEN;
   m_gaussianFilter.pState  = m_gaussianState;
   m_gaussianFilter.pCoeffs = GAUSSIAN_0_5_FILTER;
-#endif
+
   m_boxcarFilter.numTaps = BOXCAR_FILTER_LEN;
   m_boxcarFilter.pState  = m_boxcarState;
   m_boxcarFilter.pCoeffs = BOXCAR_FILTER;
@@ -149,7 +137,7 @@ void CIO::selfTest()
     // We exclude PTT to avoid trigger the transmitter
     setLEDInt(ledValue);
     setCOSInt(ledValue);
-#if defined(MODE_PINS)
+#if defined(MODE_LEDS)
     setDStarInt(ledValue);
     setDMRInt(ledValue);
     setYSFInt(ledValue);
@@ -160,7 +148,7 @@ void CIO::selfTest()
     delayInt(250);
   }
 
-#if defined(MODE_PINS)
+#if defined(MODE_LEDS)
   setDStarInt(true);
   setDMRInt(false);
   setYSFInt(false);
@@ -286,8 +274,8 @@ void CIO::process()
   m_ledCount++;
   if (m_started) {
     // Two seconds timeout
-    if (m_watchdog >= 96000U) {
+    if (m_watchdog >= 48000U) {
-      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF || m_modemState == STATE_P25 || m_modemState == STATE_NXDN) {
+      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF || m_modemState == STATE_P25 || m_modemState == STATE_NXDN || m_modemState == STATE_POCSAG) {
         if (m_modemState == STATE_DMR && m_tx)
           dmrTX.setStart(false);
         m_modemState = STATE_IDLE;
@@ -300,14 +288,14 @@ void CIO::process()
 #if defined(CONSTANT_SRV_LED)
     setLEDInt(true);
 #else
-    if (m_ledCount >= 48000U) {
+    if (m_ledCount >= 24000U) {
       m_ledCount = 0U;
       m_ledValue = !m_ledValue;
       setLEDInt(m_ledValue);
     }
 #endif
   } else {
-    if (m_ledCount >= 480000U) {
+    if (m_ledCount >= 240000U) {
       m_ledCount = 0U;
       m_ledValue = !m_ledValue;
       setLEDInt(m_ledValue);
@@ -370,17 +358,9 @@ void CIO::process()
       if (m_dstarEnable) {
         q15_t GMSKVals[RX_BLOCK_SIZE];
 #if defined(USE_DCBLOCKER)
-	#if !defined (DSTARBOXCAR)
         ::arm_fir_fast_q15(&m_gaussianFilter, dcSamples, GMSKVals, RX_BLOCK_SIZE);
-    #else
-        ::arm_fir_fast_q15(&m_boxcarFilter, dcSamples, GMSKVals, RX_BLOCK_SIZE);
-	#endif
 #else
-	#if !defined (DSTARBOXCAR)
+        ::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-    	::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-	#else
-    	::arm_fir_fast_q15(&m_boxcarFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-	#endif
 #endif
         dstarRX.samples(GMSKVals, rssi, RX_BLOCK_SIZE);
       }
@@ -426,17 +406,9 @@ void CIO::process()
       if (m_dstarEnable) {
         q15_t GMSKVals[RX_BLOCK_SIZE];
 #if defined(USE_DCBLOCKER)
-	#if !defined (DSTARBOXCAR)
         ::arm_fir_fast_q15(&m_gaussianFilter, dcSamples, GMSKVals, RX_BLOCK_SIZE);
-	#else
-        ::arm_fir_fast_q15(&m_boxcarFilter, dcSamples, GMSKVals, RX_BLOCK_SIZE);
-	#endif
 #else
-	#if !defined (DSTARBOXCAR)
+        ::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-		::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-	#else
-		::arm_fir_fast_q15(&m_boxcarFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-	#endif
 #endif
         dstarRX.samples(GMSKVals, rssi, RX_BLOCK_SIZE);
       }
@@ -490,11 +462,8 @@ void CIO::process()
       }
     } else if (m_modemState == STATE_DSTARCAL) {
       q15_t GMSKVals[RX_BLOCK_SIZE];
-#if !defined (DSTARBOXCAR)
+      ::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-    	::arm_fir_fast_q15(&m_gaussianFilter, samples, GMSKVals, RX_BLOCK_SIZE);
+
-#else
-    	::arm_fir_fast_q15(&m_boxcarFilter, samples, GMSKVals, RX_BLOCK_SIZE);
-#endif
       calDStarRX.samples(GMSKVals, RX_BLOCK_SIZE);
     } else if (m_modemState == STATE_RSSICAL) {
       calRSSI.samples(rssi, RX_BLOCK_SIZE);
@@ -577,7 +546,7 @@ void CIO::setADCDetection(bool detect)
 
 void CIO::setMode()
 {
-#if defined(MODE_PINS)
+#if defined(MODE_LEDS)
   setDStarInt(m_modemState == STATE_DSTAR);
   setDMRInt(m_modemState   == STATE_DMR);
   setYSFInt(m_modemState   == STATE_YSF);

IO.h

@@ -67,18 +67,14 @@ private:
   q31_t                        m_dcState[4];
 
   arm_fir_instance_q15 m_rrcFilter;
-#if !defined (DSTARBOXCAR)
   arm_fir_instance_q15 m_gaussianFilter;
-#endif
   arm_fir_instance_q15 m_boxcarFilter;
   arm_fir_instance_q15 m_nxdnFilter;
   arm_fir_instance_q15 m_nxdnISincFilter;
-  q15_t                m_rrcState[140U];          // NoTaps + BlockSize - 1, 82 + 20 - 1 plus some spare
+  q15_t                m_rrcState[70U];           // NoTaps + BlockSize - 1, 42 + 20 - 1 plus some spare
-#if !defined (DSTARBOXCAR)
+  q15_t                m_gaussianState[40U];      // NoTaps + BlockSize - 1, 12 + 20 - 1 plus some spare
-  q15_t                m_gaussianState[80U];      // NoTaps + BlockSize - 1, 24 + 20 - 1 plus some spare
+  q15_t                m_boxcarState[30U];        // NoTaps + BlockSize - 1, 6 + 20 - 1 plus some spare
-#endif
+  q15_t                m_nxdnState[110U];         // NoTaps + BlockSize - 1, 82 + 20 - 1 plus some spare
-  q15_t                m_boxcarState[60U];        // NoTaps + BlockSize - 1, 12 + 20 - 1 plus some spare
-  q15_t                m_nxdnState[220U];         // NoTaps + BlockSize - 1, 162 + 20 - 1 plus some spare
   q15_t                m_nxdnISincState[60U];     // NoTaps + BlockSize - 1, 32 + 20 - 1 plus some spare
 
   bool                 m_pttInvert;

IODue.cpp

@@ -152,11 +152,11 @@ void CIO::startInt()
     TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR |
     TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_CLEAR;
 #if defined(EXTERNAL_OSC)
-  t->TC_RC  = EXTERNAL_OSC / 48000;           // Counter resets on RC, so sets period in terms of the external clock
+  t->TC_RC  = EXTERNAL_OSC / 24000;           // Counter resets on RC, so sets period in terms of the external clock
-  t->TC_RA  = EXTERNAL_OSC / 96000;           // Roughly square wave
+  t->TC_RA  = EXTERNAL_OSC / 48000;           // Roughly square wave
 #else
-  t->TC_RC  = 875;                            // Counter resets on RC, so sets period in terms of 42MHz internal clock
+  t->TC_RC  = 1750;                           // Counter resets on RC, so sets period in terms of 42MHz internal clock
-  t->TC_RA  = 438;                            // Roughly square wave
+  t->TC_RA  = 880;                            // Roughly square wave
 #endif
   t->TC_CMR = (t->TC_CMR & 0xFFF0FFFF) | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET;  // Set clear and set from RA and RC compares
   t->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;    // re-enable local clocking and switch to hardware trigger source.

IOSTM.cpp

@@ -24,7 +24,120 @@
 
 #if defined(STM32F4XX) || defined(STM32F7XX)
 
-#if defined(STM32F4_DISCOVERY)
+#if defined(STM32F4_RPT_HAT_TGO)
+/*
+Pin definitions for MMDVM_RPT_Hat Pi-Hat BG4TGO  board::
+
+PTT      PB13   output           CN10 Pin30
+COSLED   PB14   output           CN10 Pin28
+LED      PA5    output           CN10 Pin11
+COS      PB15   input            CN10 Pin26
+
+DSTAR    PB10   output           CN10 Pin25
+DMR      PB4    output           CN10 Pin27
+YSF      PB5    output           CN10 Pin29
+P25      PB3    output           CN10 Pin31
+NXDN     PA10   output           CN10 Pin33
+POCSAG   PB12   output           CN10 Pin16
+
+MDSTAR   PC4    output           CN10 Pin34
+MDMR     PC5    output           CN10 Pin6
+MYSF     PC2    output           CN7 Pin35
+MP25     PC3    output           CN7 Pin37
+MNXDN    PC6    output           CN10 Pin4
+MPOCSAG  PC8    output           CN10 Pin2
+
+RX       PA0    analog input     CN7 Pin28
+RSSI     PA1    analog input     CN7 Pin30
+TX       PA4    analog output    CN7 Pin32
+
+EXT_CLK  PA15   input            CN7 Pin17
+*/
+
+#define PIN_COS           GPIO_Pin_15
+#define PORT_COS          GPIOB
+#define RCC_Per_COS       RCC_AHB1Periph_GPIOB
+
+#define PIN_PTT           GPIO_Pin_13
+#define PORT_PTT          GPIOB
+#define RCC_Per_PTT       RCC_AHB1Periph_GPIOB
+
+#define PIN_COSLED        GPIO_Pin_14
+#define PORT_COSLED       GPIOB
+#define RCC_Per_COSLED    RCC_AHB1Periph_GPIOB
+
+#define PIN_LED           GPIO_Pin_5
+#define PORT_LED          GPIOA
+#define RCC_Per_LED       RCC_AHB1Periph_GPIOA
+
+#define PIN_P25           GPIO_Pin_3
+#define PORT_P25          GPIOB
+#define RCC_Per_P25       RCC_AHB1Periph_GPIOB
+
+#define PIN_NXDN          GPIO_Pin_10
+#define PORT_NXDN         GPIOA
+#define RCC_Per_NXDN      RCC_AHB1Periph_GPIOA
+
+#define PIN_POCSAG        GPIO_Pin_12
+#define PORT_POCSAG       GPIOB
+#define RCC_Per_POCSAG    RCC_AHB1Periph_GPIOB
+
+#define PIN_DSTAR         GPIO_Pin_10
+#define PORT_DSTAR        GPIOB
+#define RCC_Per_DSTAR     RCC_AHB1Periph_GPIOB
+
+#define PIN_DMR           GPIO_Pin_4
+#define PORT_DMR          GPIOB
+#define RCC_Per_DMR       RCC_AHB1Periph_GPIOB
+
+#define PIN_YSF           GPIO_Pin_5
+#define PORT_YSF          GPIOB
+#define RCC_Per_YSF       RCC_AHB1Periph_GPIOB
+
+#if defined(MODE_PINS)
+#define PIN_MP25          GPIO_Pin_3
+#define PORT_MP25         GPIOC
+#define RCC_Per_MP25      RCC_AHB1Periph_GPIOC
+
+#define PIN_MNXDN         GPIO_Pin_6
+#define PORT_MNXDN        GPIOC
+#define RCC_Per_MNXDN     RCC_AHB1Periph_GPIOC
+
+#define PIN_MDSTAR        GPIO_Pin_4
+#define PORT_MDSTAR       GPIOC
+#define RCC_Per_MDSTAR    RCC_AHB1Periph_GPIOC
+
+#define PIN_MDMR          GPIO_Pin_5
+#define PORT_MDMR         GPIOC
+#define RCC_Per_MDMR      RCC_AHB1Periph_GPIOC
+
+#define PIN_MYSF          GPIO_Pin_2
+#define PORT_MYSF         GPIOC
+#define RCC_Per_MYSF      RCC_AHB1Periph_GPIOC
+
+#define PIN_MPOCSAG       GPIO_Pin_8
+#define PORT_MPOCSAG      GPIOC
+#define RCC_Per_MPOCSAG   RCC_AHB1Periph_GPIOC
+#endif
+
+#define PIN_EXT_CLK       GPIO_Pin_15
+#define SRC_EXT_CLK       GPIO_PinSource15
+#define PORT_EXT_CLK      GPIOA
+
+#define PIN_RX            GPIO_Pin_0
+#define PIN_RX_CH         ADC_Channel_0
+#define PORT_RX           GPIOA
+#define RCC_Per_RX        RCC_AHB1Periph_GPIOA
+
+#define PIN_RSSI          GPIO_Pin_1
+#define PIN_RSSI_CH       ADC_Channel_1
+#define PORT_RSSI         GPIOA
+#define RCC_Per_RSSI      RCC_AHB1Periph_GPIOA
+
+#define PIN_TX            GPIO_Pin_4
+#define PIN_TX_CH         DAC_Channel_1
+
+#elif defined(STM32F4_DISCOVERY)
 /*
 Pin definitions for STM32F4 Discovery Board:
 
@@ -419,9 +532,9 @@ EXT_CLK  PA15   input
 #define PIN_TX            GPIO_Pin_4
 #define PIN_TX_CH         DAC_Channel_1
 
-#elif defined(STM32F722_F7HAT)
+#elif defined(STM32F722_RPT_HAT)
 /*
-Pin definitions for MMDVM-F7Hat Pi-Hat F0DEI DB9MAT DF2ET board:
+Pin definitions for MMDVM_RPT_Hat Pi-Hat F0DEI DB9MAT DF2ET board:
 
 PTT      PB14   output
 COSLED   PB13   output
@@ -435,6 +548,13 @@ P25      PC8    output
 NXDN     PC9    output
 POCSAG   PA8    output
 
+MDSTAR   PC1    output
+MDMR     PC2    output
+MYSF     PC3    output
+MP25     PC4    output
+MNXDN    PC10   output
+MPOCSAG  PC11   output
+
 RX       PA0    analog input
 RSSI     PA7    analog input
 TX       PA4    analog output
@@ -482,6 +602,32 @@ EXT_CLK  PA15   input
 #define PORT_YSF          GPIOC
 #define RCC_Per_YSF       RCC_AHB1Periph_GPIOC
 
+#if defined(MODE_PINS)
+#define PIN_MP25          GPIO_Pin_4
+#define PORT_MP25         GPIOC
+#define RCC_Per_MP25      RCC_AHB1Periph_GPIOC
+
+#define PIN_MNXDN         GPIO_Pin_10
+#define PORT_MNXDN        GPIOC
+#define RCC_Per_MNXDN     RCC_AHB1Periph_GPIOC
+
+#define PIN_MDSTAR        GPIO_Pin_1
+#define PORT_MDSTAR       GPIOC
+#define RCC_Per_MDSTAR    RCC_AHB1Periph_GPIOC
+
+#define PIN_MDMR          GPIO_Pin_2
+#define PORT_MDMR         GPIOC
+#define RCC_Per_MDMR      RCC_AHB1Periph_GPIOC
+
+#define PIN_MYSF          GPIO_Pin_3
+#define PORT_MYSF         GPIOC
+#define RCC_Per_MYSF      RCC_AHB1Periph_GPIOC
+
+#define PIN_MPOCSAG       GPIO_Pin_11
+#define PORT_MPOCSAG      GPIOC
+#define RCC_Per_MPOCSAG   RCC_AHB1Periph_GPIOC
+#endif
+
 #define PIN_EXT_CLK       GPIO_Pin_15
 #define SRC_EXT_CLK       GPIO_PinSource15
 #define PORT_EXT_CLK      GPIOA
@@ -894,7 +1040,7 @@ EXT_CLK  PA15   input
 const uint16_t DC_OFFSET = 2048U;
 
 // Sampling frequency
-#define SAMP_FREQ   48000
+#define SAMP_FREQ   24000
 
 extern "C" {
    void TIM2_IRQHandler() {
@@ -979,7 +1125,7 @@ void CIO::initInt()
 #endif
 #endif
 
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    // DSTAR mode pin
    RCC_AHB1PeriphClockCmd(RCC_Per_MDSTAR, ENABLE);
    GPIO_InitStruct.GPIO_Pin   = PIN_MDSTAR;
@@ -1229,7 +1375,7 @@ void CIO::setCOSInt(bool on)
 void CIO::setDStarInt(bool on)
 {
    GPIO_WriteBit(PORT_DSTAR, PIN_DSTAR, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MDSTAR, PIN_MDSTAR, on ? Bit_SET : Bit_RESET);
 #endif
 }
@@ -1237,7 +1383,7 @@ void CIO::setDStarInt(bool on)
 void CIO::setDMRInt(bool on)
 {
    GPIO_WriteBit(PORT_DMR, PIN_DMR, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MDMR, PIN_MDMR, on ? Bit_SET : Bit_RESET);
 #endif
 }
@@ -1245,7 +1391,7 @@ void CIO::setDMRInt(bool on)
 void CIO::setYSFInt(bool on)
 {
    GPIO_WriteBit(PORT_YSF, PIN_YSF, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MYSF, PIN_MYSF, on ? Bit_SET : Bit_RESET);
 #endif
 }
@@ -1253,7 +1399,7 @@ void CIO::setYSFInt(bool on)
 void CIO::setP25Int(bool on)
 {
    GPIO_WriteBit(PORT_P25, PIN_P25, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MP25, PIN_MP25, on ? Bit_SET : Bit_RESET);
 #endif
 }
@@ -1263,13 +1409,13 @@ void CIO::setNXDNInt(bool on)
 #if defined(USE_ALTERNATE_NXDN_LEDS)
    GPIO_WriteBit(PORT_YSF, PIN_YSF, on ? Bit_SET : Bit_RESET);
    GPIO_WriteBit(PORT_P25, PIN_P25, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MYSF, PIN_MYSF, on ? Bit_SET : Bit_RESET);
    GPIO_WriteBit(PORT_MP25, PIN_MP25, on ? Bit_SET : Bit_RESET);
 #endif
 #else
    GPIO_WriteBit(PORT_NXDN, PIN_NXDN, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MNXDN, PIN_MNXDN, on ? Bit_SET : Bit_RESET);
 #endif
 #endif
@@ -1280,13 +1426,13 @@ void CIO::setPOCSAGInt(bool on)
 #if defined(USE_ALTERNATE_POCSAG_LEDS)
    GPIO_WriteBit(PORT_DSTAR, PIN_DSTAR, on ? Bit_SET : Bit_RESET);
    GPIO_WriteBit(PORT_DMR,   PIN_DMR,   on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MDSTAR, PIN_MDSTAR, on ? Bit_SET : Bit_RESET);
    GPIO_WriteBit(PORT_MDMR,   PIN_MDMR,   on ? Bit_SET : Bit_RESET);
 #endif
 #else
    GPIO_WriteBit(PORT_POCSAG,  PIN_POCSAG, on ? Bit_SET : Bit_RESET);
-#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && defined(STM32F4_NUCLEO)
+#if defined(MODE_PINS) && defined(STM32F4_NUCLEO_MORPHO_HEADER) && (defined(STM32F4_NUCLEO) || defined(STM32F722_RPT_HAT))
    GPIO_WriteBit(PORT_MPOCSAG, PIN_MPOCSAG, on ? Bit_SET : Bit_RESET);
 #endif
 #endif

IOSTM_CMSIS.cpp

@@ -111,7 +111,7 @@ USART1_RXD PA10  input (AF)
 const uint16_t DC_OFFSET = 2048U;
 
 // Sampling frequency
-#define SAMP_FREQ   48000
+#define SAMP_FREQ   24000
 
 extern "C" {
   void TIM2_IRQHandler() {
@@ -369,7 +369,9 @@ void CIO::interrupt()
 {
   uint8_t control  = MARK_NONE;
   uint16_t sample  = DC_OFFSET;
+#if defined(SEND_RSSI_DATA)
   uint16_t rawRSSI = 0U;
+#endif
   bitband_t eoc = (bitband_t)BITBAND_PERIPH(&ADC1->SR, ADC_SR_EOS_Pos);
   bitband_t adon = (bitband_t)BITBAND_PERIPH(&ADC1->CR2, ADC_CR2_ADON_Pos);
 #if defined(SEND_RSSI_DATA)

IOTeensy.cpp

@@ -125,7 +125,7 @@ void CIO::startInt()
 #endif
 
 #if defined(EXTERNAL_OSC)
-  // Set ADC0 to trigger from the LPTMR at 48 kHz
+  // Set ADC0 to trigger from the LPTMR at 24 kHz
   SIM_SOPT7   = SIM_SOPT7_ADC0ALTTRGEN |                              // Enable ADC0 alternate trigger
                 SIM_SOPT7_ADC0TRGSEL(14);                             // Trigger ADC0 by LPTMR0
 
@@ -134,14 +134,14 @@ void CIO::startInt()
   SIM_SCGC5  |= SIM_SCGC5_LPTIMER;                                    // Enable Low Power Timer Access
   LPTMR0_CSR  = 0;                                                    // Disable
   LPTMR0_PSR  = LPTMR_PSR_PBYP;                                       // Bypass prescaler/filter
-  LPTMR0_CMR  = (EXTERNAL_OSC / 48000) - 1;                           // Frequency divided by CMR + 1
+  LPTMR0_CMR  = (EXTERNAL_OSC / 24000) - 1;                           // Frequency divided by CMR + 1
   LPTMR0_CSR  = LPTMR_CSR_TPS(2) |                                    // Pin: 0=CMP0, 1=xtal, 2=pin13
                 LPTMR_CSR_TMS;                                        // Mode Select, 0=timer, 1=counter
   LPTMR0_CSR |= LPTMR_CSR_TEN;                                        // Enable
 #else
-  // Setup PDB for ADC0 at 48 kHz
+  // Setup PDB for ADC0 at 24 kHz
   SIM_SCGC6  |= SIM_SCGC6_PDB;                                        // Enable PDB clock
-  PDB0_MOD    = (F_BUS / 48000) - 1;                                  // Timer period - 1
+  PDB0_MOD    = (F_BUS / 24000) - 1;                                  // Timer period - 1
   PDB0_IDLY   = 0;                                                    // Interrupt delay
   PDB0_CH0C1  = PDB_CHnC1_TOS | PDB_CHnC1_EN;                         // Enable pre-trigger for ADC0
   PDB0_SC     = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN |                    // SW trigger, enable interrupts, continuous mode

MMDVM.cpp

@@ -64,6 +64,7 @@ CCalDStarTX calDStarTX;
 CCalDMR     calDMR;
 CCalP25     calP25;
 CCalNXDN    calNXDN;
+CCalPOCSAG  calPOCSAG;
 CCalRSSI    calRSSI;
 
 CCWIdTX cwIdTX;
@@ -117,6 +118,9 @@ void loop()
   if (m_modemState == STATE_NXDNCAL1K)
     calNXDN.process();
 
+  if (m_modemState == STATE_POCSAGCAL)
+    calPOCSAG.process();
+
   if (m_modemState == STATE_IDLE)
     cwIdTX.process();
 }

MMDVM.ino

@@ -61,6 +61,7 @@ CCalDStarTX calDStarTX;
 CCalDMR     calDMR;
 CCalP25     calP25;
 CCalNXDN    calNXDN;
+CCalPOCSAG  calPOCSAG;
 CCalRSSI    calRSSI;
 
 CCWIdTX cwIdTX;
@@ -114,6 +115,9 @@ void loop()
   if (m_modemState == STATE_NXDNCAL1K)
     calNXDN.process();
 
+  if (m_modemState == STATE_POCSAGCAL)
+    calPOCSAG.process();
+
   if (m_modemState == STATE_IDLE)
     cwIdTX.process();
 }

MMDVM_STM32F4xx.coproj

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<Project version="2G - 2.0.5" name="MMDVM_STM32F4xx">
+<Project version="2G - 1.7.8" name="MMDVM_STM32F4xx">
-  <Target name="MMDVM_Discovery_407" isCurrent="0">
+  <Target name="MMDVM_Discovery_407" isCurrent="1">
-    <Device manufacturerId="9" manufacturerName="ST" chipId="261" chipName="STM32F407VG" boardId="" boardName="" boardUrl="" coreId="" coreName=""/>
+    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName=""/>
     <BuildOption>
       <Compile>
         <Option name="OptimizationLevel" value="4"/>
@@ -9,8 +9,6 @@
         <Option name="UserEditCompiler" value=""/>
         <Option name="SupportCPlusplus" value="1"/>
         <Option name="FPU" value="2"/>
-        <Option name="DEBUG" value="2"/>
-        <Option name="WARNING" value="1"/>
         <Includepaths>
           <Includepath path="."/>
         </Includepaths>
@@ -79,7 +77,7 @@
     <ExcludeFile/>
   </Target>
   <Target name="MMDVM_Pi_446" isCurrent="0">
-    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName="" boardUrl="" coreId="" coreName=""/>
+    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName=""/>
     <BuildOption>
       <Compile>
         <Option name="OptimizationLevel" value="4"/>
@@ -99,7 +97,7 @@
           <Define name="STM32F446xx"/>
           <Define name="HSE_VALUE=12000000"/>
           <Define name="STM32F4_PI"/>
-          <Define name="ARDUINO_MODE_PINS"/>
+          <Define name="MODE_LEDS"/>
         </DefinedSymbols>
       </Compile>
       <Link useDefault="0">
@@ -155,8 +153,8 @@
     </DebugOption>
     <ExcludeFile/>
   </Target>
-  <Target name="MMDVM_Nucleo_446" isCurrent="1">
+  <Target name="MMDVM_Nucleo_446" isCurrent="0">
-    <Device manufacturerId="9" manufacturerName="ST" chipId="261" chipName="STM32F407VG" boardId="" boardName="" boardUrl="" coreId="" coreName=""/>
+    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName=""/>
     <BuildOption>
       <Compile>
         <Option name="OptimizationLevel" value="4"/>
@@ -164,8 +162,6 @@
         <Option name="UserEditCompiler" value=""/>
         <Option name="SupportCPlusplus" value="1"/>
         <Option name="FPU" value="2"/>
-        <Option name="DEBUG" value="2"/>
-        <Option name="WARNING" value="0"/>
         <Includepaths>
           <Includepath path="."/>
         </Includepaths>
@@ -233,26 +229,23 @@
     </DebugOption>
     <ExcludeFile/>
   </Target>
-  <Components path="./"/>
+  <Components path="./">
-  <LocalComponents/>
+  </Components>
   <Files>
     <File name="DMRIdleRX.h" path="DMRIdleRX.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c" type="1"/>
     <File name="DMRDMOTX.cpp" path="DMRDMOTX.cpp" type="1"/>
     <File name="DMRRX.cpp" path="DMRRX.cpp" type="1"/>
     <File name="YSFRX.cpp" path="YSFRX.cpp" type="1"/>
+    <File name="CalRSSI.cpp" path="CalRSSI.cpp" type="1"/>
     <File name="STM32F4XX_Lib/Device/stm32f4xx.h" path="STM32F4XX_Lib/Device/stm32f4xx.h" type="1"/>
     <File name="SampleRB.cpp" path="SampleRB.cpp" type="1"/>
     <File name="CalDStarTX.h" path="CalDStarTX.h" type="1"/>
-    <File name="CalNXDN.cpp" path="CalNXDN.cpp" type="1"/>
-    <File name="NXDNTX.cpp" path="NXDNTX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/Include/core_cm4.h" path="STM32F4XX_Lib/CMSIS/Include/core_cm4.h" type="1"/>
-    <File name="I2CTeensy.cpp" path="I2CTeensy.cpp" type="1"/>
     <File name="DMRSlotRX.h" path="DMRSlotRX.h" type="1"/>
-    <File name="YSFRX.h" path="YSFRX.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c" type="1"/>
+    <File name="YSFRX.h" path="YSFRX.h" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/Include" path="" type="2"/>
-    <File name="NXDNRX.cpp" path="NXDNRX.cpp" type="1"/>
     <File name="IO.cpp" path="IO.cpp" type="1"/>
     <File name="DMRDMORX.cpp" path="DMRDMORX.cpp" type="1"/>
     <File name="P25RX.h" path="P25RX.h" type="1"/>
@@ -260,35 +253,29 @@
     <File name="STM32F4XX_Lib/CMSIS" path="" type="2"/>
     <File name="SerialArduino.cpp" path="SerialArduino.cpp" type="1"/>
     <File name="SerialPort.cpp" path="SerialPort.cpp" type="1"/>
-    <File name="CalP25.cpp" path="CalP25.cpp" type="1"/>
     <File name="STM32F4XX_Lib/Device/stm32f4xx_conf.h" path="STM32F4XX_Lib/Device/stm32f4xx_conf.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c" type="1"/>
-    <File name="IOSTM_CMSIS.cpp" path="IOSTM_CMSIS.cpp" type="1"/>
     <File name="DStarTX.cpp" path="DStarTX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c" type="1"/>
-    <File name="YSFTX.h" path="YSFTX.h" type="1"/>
     <File name="SampleRB.h" path="SampleRB.h" type="1"/>
-    <File name="SerialSTM_CMSIS.cpp" path="SerialSTM_CMSIS.cpp" type="1"/>
+    <File name="YSFTX.h" path="YSFTX.h" type="1"/>
     <File name="DMRRX.h" path="DMRRX.h" type="1"/>
+    <File name="CalRSSI.h" path="CalRSSI.h" type="1"/>
     <File name="IOTeensy.cpp" path="IOTeensy.cpp" type="1"/>
     <File name="MMDVM.cpp" path="MMDVM.cpp" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h" path="STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h" type="1"/>
-    <File name="POCSAGTX.cpp" path="POCSAGTX.cpp" type="1"/>
     <File name="DMRDMORX.h" path="DMRDMORX.h" type="1"/>
-    <File name="GitVersion.h" path="GitVersion.h" type="1"/>
     <File name="SerialPort.h" path="SerialPort.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h" type="1"/>
-    <File name="STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h" path="STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h" type="1"/>
-    <File name="STM32F4XX_Lib/Device/system_stm32f4xx.h" path="STM32F4XX_Lib/Device/system_stm32f4xx.h" type="1"/>
     <File name="CWIdTX.h" path="CWIdTX.h" type="1"/>
+    <File name="STM32F4XX_Lib/Device/system_stm32f4xx.h" path="STM32F4XX_Lib/Device/system_stm32f4xx.h" type="1"/>
+    <File name="STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h" path="STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h" type="1"/>
     <File name="CalDStarTX.cpp" path="CalDStarTX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source" path="" type="2"/>
-    <File name="POCSAGTX.h" path="POCSAGTX.h" type="1"/>
-    <File name="DMRDMOTX.h" path="DMRDMOTX.h" type="1"/>
     <File name="CalDMR.h" path="CalDMR.h" type="1"/>
+    <File name="DMRDMOTX.h" path="DMRDMOTX.h" type="1"/>
     <File name="IODue.cpp" path="IODue.cpp" type="1"/>
     <File name="DMRTX.cpp" path="DMRTX.cpp" type="1"/>
-    <File name="CalRSSI.h" path="CalRSSI.h" type="1"/>
     <File name="P25RX.cpp" path="P25RX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/Lib/GCC" path="" type="2"/>
     <File name="STM32F4XX_Lib" path="" type="2"/>
@@ -299,9 +286,7 @@
     <File name="STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c" path="STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c" type="1"/>
     <File name="STM32F4XX_Lib/Device/startup" path="" type="2"/>
     <File name="SerialRB.h" path="SerialRB.h" type="1"/>
-    <File name="NXDNDefines.h" path="NXDNDefines.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h" type="1"/>
-    <File name="NXDNTX.h" path="NXDNTX.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver" path="" type="2"/>
     <File name="DMRDefines.h" path="DMRDefines.h" type="1"/>
     <File name="CalDMR.cpp" path="CalDMR.cpp" type="1"/>
@@ -310,22 +295,18 @@
     <File name="STM32F4XX_Lib/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a" path="STM32F4XX_Lib/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a" type="1"/>
     <File name="DStarDefines.h" path="DStarDefines.h" type="1"/>
     <File name="DStarRX.h" path="DStarRX.h" type="1"/>
-    <File name="NXDNRX.h" path="NXDNRX.h" type="1"/>
     <File name="Config.h" path="Config.h" type="1"/>
-    <File name="RingBuff.h" path="RingBuff.h" type="1"/>
     <File name="DMRSlotType.cpp" path="DMRSlotType.cpp" type="1"/>
     <File name="Globals.h" path="Globals.h" type="1"/>
     <File name="STM32F4XX_Lib/Device" path="" type="2"/>
     <File name="CalDStarRX.cpp" path="CalDStarRX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h" type="1"/>
-    <File name="CalNXDN.h" path="CalNXDN.h" type="1"/>
     <File name="CalDStarRX.h" path="CalDStarRX.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include" path="" type="2"/>
-    <File name="CalRSSI.cpp" path="CalRSSI.cpp" type="1"/>
     <File name="IO.h" path="IO.h" type="1"/>
     <File name="Utils.cpp" path="Utils.cpp" type="1"/>
-    <File name="STM32F4XX_Lib/CMSIS/Lib/.DS_Store" path="STM32F4XX_Lib/CMSIS/Lib/.DS_Store" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/.DS_Store" path="STM32F4XX_Lib/CMSIS/.DS_Store" type="1"/>
+    <File name="STM32F4XX_Lib/CMSIS/Lib/.DS_Store" path="STM32F4XX_Lib/CMSIS/Lib/.DS_Store" type="1"/>
     <File name="Utils.h" path="Utils.h" type="1"/>
     <File name="STM32F4XX_Lib/CMSIS/Lib" path="" type="2"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/.DS_Store" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/.DS_Store" type="1"/>
@@ -334,7 +315,6 @@
     <File name="YSFDefines.h" path="YSFDefines.h" type="1"/>
     <File name="DStarTX.h" path="DStarTX.h" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c" type="1"/>
-    <File name="CalP25.h" path="CalP25.h" type="1"/>
     <File name="STM32F4XX_Lib/Device/.DS_Store" path="STM32F4XX_Lib/Device/.DS_Store" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h" type="1"/>
     <File name="P25Defines.h" path="P25Defines.h" type="1"/>
@@ -344,17 +324,15 @@
     <File name="P25TX.h" path="P25TX.h" type="1"/>
     <File name="RSSIRB.cpp" path="RSSIRB.cpp" type="1"/>
     <File name="DStarRX.cpp" path="DStarRX.cpp" type="1"/>
-    <File name="IOSTM.cpp" path="IOSTM.cpp" type="1"/>
     <File name="DMRSlotRX.cpp" path="DMRSlotRX.cpp" type="1"/>
+    <File name="IOSTM.cpp" path="IOSTM.cpp" type="1"/>
     <File name="P25TX.cpp" path="P25TX.cpp" type="1"/>
     <File name="SerialRB.cpp" path="SerialRB.cpp" type="1"/>
     <File name="CWIdTX.cpp" path="CWIdTX.cpp" type="1"/>
     <File name="DMRIdleRX.cpp" path="DMRIdleRX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h" type="1"/>
-    <File name="STM32Utils.h" path="STM32Utils.h" type="1"/>
     <File name="STM32F4XX_Lib/.DS_Store" path="STM32F4XX_Lib/.DS_Store" type="1"/>
     <File name="YSFTX.cpp" path="YSFTX.cpp" type="1"/>
     <File name="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c" path="STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c" type="1"/>
   </Files>
-  <Bookmarks/>
 </Project>

Makefile

@@ -128,10 +128,12 @@ DEFS_NUCLEO_F767=-DUSE_HAL_DRIVER -DSTM32F767xx -DSTM32F7XX -DSTM32F7_NUCLEO -DH
 DEFS_PI_F722=-DUSE_HAL_DRIVER -DSTM32F722xx -DSTM32F7XX -DSTM32F722_PI -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
 # MMDVM-F7M F0DEI board:
 DEFS_F7M=-DUSE_HAL_DRIVER -DSTM32F722xx -DSTM32F7XX -DSTM32F722_F7M -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
-# MMDVM-F7-Hat F0DEI, DB9MAT, DF2ET board:
+# MMDVM_RPT_Hat F0DEI, DB9MAT, DF2ET board:
-DEFS_F7HAT=-DUSE_HAL_DRIVER -DSTM32F722xx -DSTM32F7XX -DSTM32F722_F7HAT -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
+DEFS_RPT_HAT=-DUSE_HAL_DRIVER -DSTM32F722xx -DSTM32F7XX -DSTM32F722_RPT_HAT -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
 # STM32F4 DVM board:
 DEFS_DVM=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F446xx -DSTM32F4_DVM -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
+# MMDVM_RPT_Hat BG4TGO, BG5HHP board:
+DEFS_RPT_HAT_TGO=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F40_41xxx -DSTM32F4_RPT_HAT_TGO -DHSE_VALUE=$(OSC) -DMADEBYMAKEFILE
 
 # Build compiler flags
 CFLAGS_F4=-c $(MCFLAGS_F4) $(INCLUDES_F4)
@@ -179,11 +181,17 @@ f7m: CXXFLAGS+=$(CXXFLAGS_F7) $(DEFS_F7M)
 f7m: LDFLAGS+=$(LDFLAGS_F722)
 f7m: release_f7
 
-f7hat: GitVersion.h
+rpt_hat: GitVersion.h
-f7hat: CFLAGS+=$(CFLAGS_F7) $(DEFS_F7HAT)
+rpt_hat: CFLAGS+=$(CFLAGS_F7) $(DEFS_RPT_HAT)
-f7hat: CXXFLAGS+=$(CXXFLAGS_F7) $(DEFS_F7HAT)
+rpt_hat: CXXFLAGS+=$(CXXFLAGS_F7) $(DEFS_RPT_HAT)
-f7hat: LDFLAGS+=$(LDFLAGS_F722)
+rpt_hat: LDFLAGS+=$(LDFLAGS_F722)
-f7hat: release_f7
+rpt_hat: release_f7
+
+rpt_hat_tgo: GitVersion.h
+rpt_hat_tgo: CFLAGS+=$(CFLAGS_F4) $(DEFS_RPT_HAT_TGO)
+rpt_hat_tgo: CXXFLAGS+=$(CXXFLAGS_F4) $(DEFS_RPT_HAT_TGO)
+rpt_hat_tgo: LDFLAGS+=$(LDFLAGS_F4)
+rpt_hat_tgo: release_f4
 
 nucleo: GitVersion.h
 nucleo: CFLAGS+=$(CFLAGS_F4) $(DEFS_NUCLEO)
@@ -345,7 +353,7 @@ ifneq ($(wildcard /usr/bin/stm32flash),)
 endif
 
 deploy-f7m:   deploy-pi-f7
-deploy-f7hat: deploy-pi-f7
+deploy-rpt_hat: deploy-pi-f7
 
 # Export the current git version if the index file exists, else 000...
 GitVersion.h:

Makefile.CMSIS

@@ -65,7 +65,7 @@ COMMON_FLAGS =-mthumb -mlittle-endian -mcpu=$(MCPU)
 COMMON_FLAGS+= -Wall
 COMMON_FLAGS+= -I. -I$(CMSISDIR)/Include -I$(CMSISDIR)/Device/ST/STM32F1xx/Include -I$(SYSDIR)
 COMMON_FLAGS+=  $(addprefix -I,$(INCDIR))
-COMMON_FLAGS+= -D$(MCU)
+COMMON_FLAGS+= -D$(MCU) -DMADEBYMAKEFILE
 COMMON_FLAGS+= -Os -flto -ffunction-sections -fdata-sections
 COMMON_FLAGS+= -g
 # Assembler flags
@@ -91,7 +91,7 @@ DEPENDS:=$(CSRC:%.c=$(OBJDIR)/%.d) $(CXXSRC:%.cpp=$(OBJDIR)/%.d)
 
 # Targets
 .PHONY: all
-all: $(DIS) $(HEX)
+all: GitVersion.h $(DIS) $(HEX)
 	$(SIZE) $(ELF)
 
 .PHONY: program
@@ -116,7 +116,7 @@ debug: $(ELF)
 
 .PHONY: clean
 clean:
-	$(RM) $(OBJ) $(HEX) $(ELF) $(DIS) $(MAP) $(DEPENDS)
+	$(RM) $(OBJ) $(HEX) $(ELF) $(DIS) $(MAP) $(DEPENDS) GitVersion.h
 
 # implicit rules
 .elf.hex:
@@ -149,3 +149,17 @@ $(DIS): $(ELF)
 
 # include dependecies
 -include $(DEPENDS)
+
+# Export the current git version if the index file exists, else 000...
+GitVersion.h:
+ifdef SYSTEMROOT
+	echo #define GITVERSION "0000000" > $@
+else ifdef SystemRoot
+	echo #define GITVERSION "0000000" > $@
+else
+ifneq ("$(wildcard .git/index)","")
+	echo "#define GITVERSION \"$(shell git rev-parse --short HEAD)\"" > $@
+else
+	echo "#define GITVERSION \"0000000\"" > $@
+endif
+endif

NXDNDefines.h

@@ -19,7 +19,7 @@
 #if !defined(NXDNDEFINES_H)
 #define  NXDNDEFINES_H
 
-const unsigned int NXDN_RADIO_SYMBOL_LENGTH = 20U;      // At 48 kHz sample rate
+const unsigned int NXDN_RADIO_SYMBOL_LENGTH = 10U;      // At 24 kHz sample rate
 
 const unsigned int NXDN_FRAME_LENGTH_BITS    = 384U;
 const unsigned int NXDN_FRAME_LENGTH_BYTES   = NXDN_FRAME_LENGTH_BITS / 8U;

NXDNTX.cpp

@@ -23,21 +23,19 @@
 
 #include "NXDNDefines.h"
 
-// NXDN RRC filter + SINC filter
+// Generated using rcosdesign(0.2, 8, 10, 'sqrt') in MATLAB
-static q15_t RRC_0_2_FILTER[] = {51, 71, 92, 112, 129, 141, 144, 138, 120, 87, 39, -26, -107, -204, -314, -437, -567, -702, -835,
+static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 850, 592, 219, -234, -720, -1179, -1548, -1769, -1795, -1597, -1172,
-                               -932,-1066, -1176, -1257, -1304, -1314, -1284, -1213, -1099, -944, -749, -519, -257, 30, 335, 651,
+                                 -544, 237, 1092, 1927, 2637, 3120, 3286, 3073, 2454, 1447, 116, -1431, -3043, -4544, -5739, -6442,
-                               968, 1277, 1569, 1832, 2058, 2237, 2360, 2420, 2412, 2329, 2170, 1935, 1623, 1239, 790, 283, -271,
+                                 -6483, -5735, -4121, -1633, 1669, 5651, 10118, 14822, 19484, 23810, 27520, 30367, 32156, 32767,
-                               -858, -1466, -2076, -2671, -3233, -3742, -4178, -4521, -4754, -4857, -4815, -4614, -4242, -3690,
+                                 32156, 30367, 27520, 23810, 19484, 14822, 10118, 5651, 1669, -1633, -4121, -5735, -6483, -6442,
-                               -2952, -2025, -912, 385, 1855, 3488, 5266, 7172, 9183, 11274, 13418, 15585, 17746, 19869, 21923,
+                                 -5739, -4544, -3043, -1431, 116, 1447, 2454, 3073, 3286, 3120, 2637, 1927, 1092, 237, -544, -1172,
-                               23876, 25700, 27364, 28844, 30116, 31159, 31956, 32495, 32767, 32767, 32495, 31956, 31159, 30116,
+                                 -1597, -1795, -1769, -1548, -1179, -720, -234, 219, 592, 850}; // numTaps = 90, L = 10
-                               28844, 27364, 25700, 23876, 21923, 19869, 17746, 15585, 13418, 11274, 9183, 7172, 5266, 3488, 1855,
-                               385, -912, -2025, -2952, -3690, -4242, -4614, -4815, -4857, -4754, -4521, -4178, -3742, -3233, -2671,
-                               -2076, -1466, -858, -271, 283, 790, 1239, 1623, 1935, 2170, 2329, 2412, 2420, 2360, 2237, 2058, 1832,
-                               1569, 1277, 968, 651, 335, 30, -257, -519, -749, -944, -1099, -1213, -1284, -1314, -1304, -1257, 
-                               -1176, -1066, -932, -835, -702, -567, -437, -314, -204, -107, -26, 39, 87, 120, 138, 144, 141, 129,
-                               112, 92, 71, 51}; // numTaps = 180, L = 20
 const uint16_t RRC_0_2_FILTER_PHASE_LEN = 9U; // phaseLength = numTaps/L
 
+static q15_t NXDN_SINC_FILTER[] = {572, -1003, -253, 254, 740, 1290, 1902, 2527, 3090, 3517, 3747, 3747, 3517, 3090, 2527, 1902,
+                                   1290, 740, 254, -253, -1003, 572};
+const uint16_t NXDN_SINC_FILTER_LEN = 22U;
+
 const q15_t NXDN_LEVELA =  735;
 const q15_t NXDN_LEVELB =  245;
 const q15_t NXDN_LEVELC = -245;
@@ -49,18 +47,25 @@ const uint8_t NXDN_SYNC = 0x5FU;
 CNXDNTX::CNXDNTX() :
 m_buffer(TX_BUFFER_LEN),
 m_modFilter(),
+m_sincFilter(),
 m_modState(),
+m_sincState(),
 m_poBuffer(),
 m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(240U)      // 200ms
 {
   ::memset(m_modState, 0x00U, 16U * sizeof(q15_t));
+  ::memset(m_sincState,  0x00U, 70U * sizeof(q15_t));
 
   m_modFilter.L           = NXDN_RADIO_SYMBOL_LENGTH;
   m_modFilter.phaseLength = RRC_0_2_FILTER_PHASE_LEN;
   m_modFilter.pCoeffs     = RRC_0_2_FILTER;
   m_modFilter.pState      = m_modState;
+
+  m_sincFilter.numTaps = NXDN_SINC_FILTER_LEN;
+  m_sincFilter.pState  = m_sincState;
+  m_sincFilter.pCoeffs = NXDN_SINC_FILTER;
 }
 
 void CNXDNTX::process()
@@ -121,6 +126,7 @@ uint8_t CNXDNTX::writeData(const uint8_t* data, uint8_t length)
 void CNXDNTX::writeByte(uint8_t c)
 {
   q15_t inBuffer[4U];
+  q15_t intBuffer[NXDN_RADIO_SYMBOL_LENGTH * 4U];
   q15_t outBuffer[NXDN_RADIO_SYMBOL_LENGTH * 4U];
 
   const uint8_t MASK = 0xC0U;
@@ -142,7 +148,9 @@ void CNXDNTX::writeByte(uint8_t c)
     }
   }
 
-  ::arm_fir_interpolate_q15(&m_modFilter, inBuffer, outBuffer, 4U);
+  ::arm_fir_interpolate_q15(&m_modFilter, inBuffer, intBuffer, 4U);
+
+  ::arm_fir_fast_q15(&m_sincFilter, intBuffer, outBuffer, NXDN_RADIO_SYMBOL_LENGTH * 4U);
 
   io.write(STATE_NXDN, outBuffer, NXDN_RADIO_SYMBOL_LENGTH * 4U);
 }

NXDNTX.h

@@ -38,7 +38,9 @@ public:
 private:
   CSerialRB                        m_buffer;
   arm_fir_interpolate_instance_q15 m_modFilter;
+  arm_fir_instance_q15             m_sincFilter;
   q15_t                            m_modState[16U];    // blockSize + phaseLength - 1, 4 + 9 - 1 plus some spare
+  q15_t                            m_sincState[70U];   // NoTaps + BlockSize - 1, 22 + 40 - 1 plus some spare
   uint8_t                          m_poBuffer[1200U];
   uint16_t                         m_poLen;
   uint16_t                         m_poPtr;

P25Defines.h

@@ -20,7 +20,7 @@
 #if !defined(P25DEFINES_H)
 #define  P25DEFINES_H
 
-const unsigned int P25_RADIO_SYMBOL_LENGTH = 10U;      // At 48 kHz sample rate
+const unsigned int P25_RADIO_SYMBOL_LENGTH = 5U;      // At 24 kHz sample rate
 
 const unsigned int P25_HDR_FRAME_LENGTH_BYTES      = 99U;
 const unsigned int P25_HDR_FRAME_LENGTH_BITS       = P25_HDR_FRAME_LENGTH_BYTES * 8U;
@@ -47,6 +47,11 @@ const unsigned int P25_TSDU_FRAME_LENGTH_BITS      = P25_TSDU_FRAME_LENGTH_BYTES
 const unsigned int P25_TSDU_FRAME_LENGTH_SYMBOLS   = P25_TSDU_FRAME_LENGTH_BYTES * 4U; 
 const unsigned int P25_TSDU_FRAME_LENGTH_SAMPLES   = P25_TSDU_FRAME_LENGTH_SYMBOLS * P25_RADIO_SYMBOL_LENGTH;
 
+const unsigned int P25_PDU_HDR_FRAME_LENGTH_BYTES = 45U;
+const unsigned int P25_PDU_HDR_FRAME_LENGTH_BITS = P25_PDU_HDR_FRAME_LENGTH_BYTES * 8U;
+const unsigned int P25_PDU_HDR_FRAME_LENGTH_SYMBOLS = P25_PDU_HDR_FRAME_LENGTH_BYTES * 4U;
+const unsigned int P25_PDU_HDR_FRAME_LENGTH_SAMPLES = P25_PDU_HDR_FRAME_LENGTH_SYMBOLS * P25_RADIO_SYMBOL_LENGTH;
+
 const unsigned int P25_SYNC_LENGTH_BYTES   = 6U;
 const unsigned int P25_SYNC_LENGTH_BITS    = P25_SYNC_LENGTH_BYTES * 8U;
 const unsigned int P25_SYNC_LENGTH_SYMBOLS = P25_SYNC_LENGTH_BYTES * 4U;

P25RX.cpp

@@ -199,7 +199,19 @@ void CP25RX::processHdr(q15_t sample)
                 serial.writeP25Hdr(frame, P25_HDR_FRAME_LENGTH_BYTES + 1U);
             }
             break;
-        case P25_DUID_TSDU: {
+		case P25_DUID_PDU: {
+				calculateLevels(m_hdrSyncPtr, P25_PDU_HDR_FRAME_LENGTH_SYMBOLS);
+
+				DEBUG4("P25RX: sync found in PDU pos/centre/threshold", m_hdrSyncPtr, m_centreVal, m_thresholdVal);
+
+				uint8_t frame[P25_PDU_HDR_FRAME_LENGTH_BYTES + 1U];
+				samplesToBits(m_hdrSyncPtr, P25_PDU_HDR_FRAME_LENGTH_SYMBOLS, frame, 8U, m_centreVal, m_thresholdVal);
+
+				frame[0U] = 0x01U;
+				serial.writeP25Hdr(frame, P25_PDU_HDR_FRAME_LENGTH_BYTES + 1U);
+			}
+			break;
+		case P25_DUID_TSDU: {
                 calculateLevels(m_hdrStartPtr, P25_TSDU_FRAME_LENGTH_SYMBOLS);
 
                 DEBUG4("P25RX: sync found in TSDU pos/centre/threshold", m_hdrSyncPtr, m_centreVal, m_thresholdVal);

P25TX.cpp

@@ -23,23 +23,17 @@
 
 #include "P25Defines.h"
 
-// Generated using rcosdesign(0.2, 8, 10, 'normal') in MATLAB
+// Generated using rcosdesign(0.2, 8, 5, 'normal') in MATLAB
-static q15_t RC_0_2_FILTER[] = {-444, -897, -1311, -1636, -1825, -1840, -1659, -1278, -712, 0,
+// numTaps = 40, L = 5
-                               800, 1613, 2354, 2936, 3277, 3310, 2994, 2315, 1296, 0, -1478,
+static q15_t RC_0_2_FILTER[] = {-897, -1636, -1840, -1278, 0, 1613, 2936, 3310, 2315, 0, -3011, -5627, -6580, -4839,
-                               -3011, -4448, -5627, -6386, -6580, -6090, -4839, -2800, 0, 3474,
+                                0, 7482, 16311, 24651, 30607, 32767, 30607, 24651, 16311, 7482, 0, -4839, -6580, -5627,
-                               7482, 11835, 16311, 20666, 24651, 28032, 30607, 32219, 32767,
+                               -3011, 0, 2315, 3310, 2936, 1613, 0, -1278, -1840, -1636, -897, 0}; // numTaps = 40, L = 5
-                               32219, 30607, 28032, 24651, 20666, 16311, 11835, 7482, 3474, 0,
-                               -2800, -4839, -6090, -6580, -6386, -5627, -4448, -3011, -1478,
-                               0, 1296, 2315, 2994, 3310, 3277, 2936, 2354, 1613, 800, 0, -712,
-                               -1278, -1659, -1840, -1825, -1636, -1311, -897, -444, 0}; // numTaps = 80, L = 10
 const uint16_t RC_0_2_FILTER_PHASE_LEN = 8U; // phaseLength = numTaps/L
 
-// Generated in MATLAB using the following commands, and then normalised for unity gain
+static q15_t LOWPASS_FILTER[] = {124, -188, -682, 1262, 556, -621, -1912, -911, 2058, 3855, 1234, -4592, -7692, -2799,
-// shape2 = 'Inverse-sinc Lowpass';
+                                8556, 18133, 18133, 8556, -2799, -7692, -4592, 1234, 3855, 2058, -911, -1912, -621,
-// d2 = fdesign.interpolator(1, shape2);  
+                                556, 1262, -682, -188, 124};
-// h2 = design(d2, 'SystemObject', true);
+const uint16_t LOWPASS_FILTER_LEN = 32U;
-static q15_t LOWPASS_FILTER[] = {1294, -2251, 4312, -8402, 20999, 20999, -8402, 4312, -2251, 1294};
-const uint16_t LOWPASS_FILTER_LEN = 10U;
 
 const q15_t P25_LEVELA =  1260;
 const q15_t P25_LEVELB =   420;

POCSAGTX.cpp

@@ -24,18 +24,18 @@ const uint16_t POCSAG_FRAME_LENGTH_BYTES = 17U * sizeof(uint32_t);
 
 const uint16_t POCSAG_PREAMBLE_LENGTH_BYTES = 18U * sizeof(uint32_t);
 
-const uint16_t POCSAG_RADIO_SYMBOL_LENGTH = 40U; 					// at 48Khz
+const uint16_t POCSAG_RADIO_SYMBOL_LENGTH = 20U;
 
-const q15_t POCSAG_LEVEL1[] = { 1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700};
+const q15_t POCSAG_LEVEL1[] = { 1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700,  1700};
-const q15_t POCSAG_LEVEL0[] = {-1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700};
+const q15_t POCSAG_LEVEL0[] = {-1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700, -1700};
 
-static q15_t SHAPING_FILTER[] = {2730, 2730, 2730, 2730, 2730, 2730, 2730, 2730, 2730, 2730, 2730, 2730};
+static q15_t SHAPING_FILTER[] = {5461, 5461, 5461, 5461, 5461, 5461};
-const uint16_t SHAPING_FILTER_LEN = 12U;
+const uint16_t SHAPING_FILTER_LEN = 6U;
 
 const uint8_t POCSAG_SYNC = 0xAAU;
 
 CPOCSAGTX::CPOCSAGTX() :
-m_buffer(TX_BUFFER_LEN),
+m_buffer(4000U),
 m_modFilter(),
 m_modState(),
 m_poBuffer(),
@@ -43,7 +43,7 @@ m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(POCSAG_PREAMBLE_LENGTH_BYTES)
 {
-  ::memset(m_modState, 0x00U, 180U * sizeof(q15_t));
+  ::memset(m_modState, 0x00U, 170U * sizeof(q15_t));
 
   m_modFilter.numTaps = SHAPING_FILTER_LEN;
   m_modFilter.pState  = m_modState;

POCSAGTX.h

@@ -1,5 +1,5 @@
 /*
- *   Copyright (C) 2015,2016,2017,2018 by Jonathan Naylor G4KLX
+ *   Copyright (C) 2015-2019 by Jonathan Naylor G4KLX
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -29,6 +29,8 @@ public:
 
   uint8_t writeData(const uint8_t* data, uint8_t length);
 
+  void writeByte(uint8_t c);
+
   void process();
 
   void setTXDelay(uint8_t delay);
@@ -40,13 +42,11 @@ public:
 private:
   CSerialRB            m_buffer;
   arm_fir_instance_q15 m_modFilter;
-  q15_t                m_modState[180U];     // NoTaps + BlockSize - 1, 12 + 160 - 1 plus some spare
+  q15_t                m_modState[170U];     // NoTaps + BlockSize - 1, 6 + 160 - 1 plus some spare
   uint8_t              m_poBuffer[200U];
   uint16_t             m_poLen;
   uint16_t             m_poPtr;
   uint16_t             m_txDelay;
-
-  void writeByte(uint8_t c);
 };
 
 #endif

STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h

@@ -1,664 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-    or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-	or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */

STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h

@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-  return(result);
-}
-#endif
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-#endif
-  return(result);
-}
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h

@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */

STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c

@@ -1,436 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f4xx.s
-  * @author    Coocox
-  * @version   V1.0
-  * @date      03/05/2012
-  * @brief     STM32F4xx Devices vector table for RIDE7 toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM324xG-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  */
-  
-/* Some modifications by Andy Uribe CA6JAU :
-- Added C++ global constructors support
-- Changed initial stack pointer
-*/
-
-/*----------Macro definition--------------------------------------------------*/
-#define WEAK __attribute__ ((weak))
-
-/*----------Declaration of the default fault handlers-------------------------*/
-/* System exception vector handler */
-__attribute__ ((used))
-void WEAK  Reset_Handler(void);
-void WEAK  NMI_Handler(void);
-void WEAK  HardFault_Handler(void);
-void WEAK  MemManage_Handler(void);
-void WEAK  BusFault_Handler(void);
-void WEAK  UsageFault_Handler(void);
-void WEAK  SVC_Handler(void);
-void WEAK  DebugMon_Handler(void);
-void WEAK  PendSV_Handler(void);
-void WEAK  SysTick_Handler(void);
-
-void WEAK  WWDG_IRQHandler(void);
-void WEAK  PVD_IRQHandler(void);
-void WEAK  TAMP_STAMP_IRQHandler(void);
-void WEAK  RTC_WKUP_IRQHandler(void);
-void WEAK  FLASH_IRQHandler(void);
-void WEAK  RCC_IRQHandler(void);
-void WEAK  EXTI0_IRQHandler(void);
-void WEAK  EXTI1_IRQHandler(void);
-void WEAK  EXTI2_IRQHandler(void);
-void WEAK  EXTI3_IRQHandler(void);
-void WEAK  EXTI4_IRQHandler(void);
-void WEAK  DMA1_Stream0_IRQHandler(void);
-void WEAK  DMA1_Stream1_IRQHandler(void);
-void WEAK  DMA1_Stream2_IRQHandler(void);
-void WEAK  DMA1_Stream3_IRQHandler(void);
-void WEAK  DMA1_Stream4_IRQHandler(void);
-void WEAK  DMA1_Stream5_IRQHandler(void);
-void WEAK  DMA1_Stream6_IRQHandler(void);
-void WEAK  ADC_IRQHandler(void);
-void WEAK  CAN1_TX_IRQHandler(void);
-void WEAK  CAN1_RX0_IRQHandler(void);
-void WEAK  CAN1_RX1_IRQHandler(void);
-void WEAK  CAN1_SCE_IRQHandler(void);
-void WEAK  EXTI9_5_IRQHandler(void);
-void WEAK  TIM1_BRK_TIM9_IRQHandler(void);
-void WEAK  TIM1_UP_TIM10_IRQHandler(void);
-void WEAK  TIM1_TRG_COM_TIM11_IRQHandler(void);
-void WEAK  TIM1_CC_IRQHandler(void);
-void WEAK  TIM2_IRQHandler(void);
-void WEAK  TIM3_IRQHandler(void);
-void WEAK  TIM4_IRQHandler(void);
-void WEAK  I2C1_EV_IRQHandler(void);
-void WEAK  I2C1_ER_IRQHandler(void);
-void WEAK  I2C2_EV_IRQHandler(void);
-void WEAK  I2C2_ER_IRQHandler(void);
-void WEAK  SPI1_IRQHandler(void);
-void WEAK  SPI2_IRQHandler(void);
-void WEAK  USART1_IRQHandler(void);
-void WEAK  USART2_IRQHandler(void);
-void WEAK  USART3_IRQHandler(void);
-void WEAK  EXTI15_10_IRQHandler(void);
-void WEAK  RTC_Alarm_IRQHandler(void);
-void WEAK  OTG_FS_WKUP_IRQHandler(void);
-void WEAK  TIM8_BRK_TIM12_IRQHandler(void);
-void WEAK  TIM8_UP_TIM13_IRQHandler(void);
-void WEAK  TIM8_TRG_COM_TIM14_IRQHandler(void);
-void WEAK  TIM8_CC_IRQHandler(void);
-void WEAK  DMA1_Stream7_IRQHandler(void);
-void WEAK  FSMC_IRQHandler(void);
-void WEAK  SDIO_IRQHandler(void);
-void WEAK  TIM5_IRQHandler(void);
-void WEAK  SPI3_IRQHandler(void);
-void WEAK  UART4_IRQHandler(void);
-void WEAK  UART5_IRQHandler(void);
-void WEAK  TIM6_DAC_IRQHandler(void);
-void WEAK  TIM7_IRQHandler(void);
-void WEAK  DMA2_Stream0_IRQHandler(void);
-void WEAK  DMA2_Stream1_IRQHandler(void);
-void WEAK  DMA2_Stream2_IRQHandler(void);
-void WEAK  DMA2_Stream3_IRQHandler(void);
-void WEAK  DMA2_Stream4_IRQHandler(void);
-void WEAK  ETH_IRQHandler(void);
-void WEAK  ETH_WKUP_IRQHandler(void);
-void WEAK  CAN2_TX_IRQHandler(void);
-void WEAK  CAN2_RX0_IRQHandler(void);
-void WEAK  CAN2_RX1_IRQHandler(void);
-void WEAK  CAN2_SCE_IRQHandler(void);
-void WEAK  OTG_FS_IRQHandler(void);
-void WEAK  DMA2_Stream5_IRQHandler(void);
-void WEAK  DMA2_Stream6_IRQHandler(void);
-void WEAK  DMA2_Stream7_IRQHandler(void);
-void WEAK  USART6_IRQHandler(void);
-void WEAK  I2C3_EV_IRQHandler(void);
-void WEAK  I2C3_ER_IRQHandler(void);
-void WEAK  OTG_HS_EP1_OUT_IRQHandler(void);
-void WEAK  OTG_HS_EP1_IN_IRQHandler(void);
-void WEAK  OTG_HS_WKUP_IRQHandler(void);
-void WEAK  OTG_HS_IRQHandler(void);
-void WEAK  DCMI_IRQHandler(void);
-void WEAK  CRYP_IRQHandler(void);
-void WEAK  HASH_RNG_IRQHandler(void);
-void WEAK  FPU_IRQHandler(void);
-
-/*----------Symbols defined in linker script----------------------------------*/
-extern unsigned long _estack;    /*!< The initial stack pointer               */
-extern unsigned long _sidata;    /*!< Start address for the initialization
-                                      values of the .data section.            */
-extern unsigned long _sdata;     /*!< Start address for the .data section     */
-extern unsigned long _edata;     /*!< End address for the .data section       */
-extern unsigned long _sbss;      /*!< Start address for the .bss section      */
-extern unsigned long _ebss;      /*!< End address for the .bss section        */
-
-/* C++ global constructors support */
-extern unsigned long __preinit_array_start;
-extern unsigned long __preinit_array_end;
-extern unsigned long __init_array_start;
-extern unsigned long __init_array_end;
-
-/*----------Function prototypes-----------------------------------------------*/
-extern int main(void);           /*!< The entry point for the application.    */
-//extern void SystemInit(void);    /*!< Setup the microcontroller system(CMSIS) */
-void Default_Reset_Handler(void);   /*!< Default reset handler                */
-static void Default_Handler(void);  /*!< Default exception handler            */
-static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline));
-
-/**
-  *@brief The minimal vector table for a Cortex M3.  Note that the proper constructs
-  *       must be placed on this to ensure that it ends up at physical address
-  *       0x00000000.
-  */
-__attribute__ ((used,section(".isr_vector")))
-void (* const g_pfnVectors[])(void) =
-{
-  /*----------Core Exceptions------------------------------------------------ */
-  (void *) &_estack,		 /*!< The initial stack pointer         		  */
-  Reset_Handler,             /*!< Reset Handler                               */
-  NMI_Handler,               /*!< NMI Handler                                 */
-  HardFault_Handler,         /*!< Hard Fault Handler                          */
-  MemManage_Handler,         /*!< MPU Fault Handler                           */
-  BusFault_Handler,          /*!< Bus Fault Handler                           */
-  UsageFault_Handler,        /*!< Usage Fault Handler                         */
-  0,0,0,0,                   /*!< Reserved                                    */
-  SVC_Handler,               /*!< SVCall Handler                              */
-  DebugMon_Handler,          /*!< Debug Monitor Handler                       */
-  0,                         /*!< Reserved                                    */
-  PendSV_Handler,            /*!< PendSV Handler                              */
-  SysTick_Handler,           /*!< SysTick Handler                             */
-  
-  /*----------External Exceptions---------------------------------------------*/
-  WWDG_IRQHandler,           /*!<  0: Window WatchDog                         */
-  PVD_IRQHandler,            /*!<  1: PVD through EXTI Line detection         */
-  TAMP_STAMP_IRQHandler,     /*!<  2: Tamper and TimeStamps through the EXTI line*/
-  RTC_WKUP_IRQHandler,       /*!<  3: RTC Wakeup through the EXTI line        */
-  FLASH_IRQHandler,          /*!<  4: FLASH                                   */
-  RCC_IRQHandler  ,          /*!<  5: RCC                                     */
-  EXTI0_IRQHandler,          /*!<  6: EXTI Line0                              */
-  EXTI1_IRQHandler,          /*!<  7: EXTI Line1                              */
-  EXTI2_IRQHandler,          /*!<  8: EXTI Line2                              */
-  EXTI3_IRQHandler,          /*!<  9: EXTI Line3                              */
-  EXTI4_IRQHandler,          /*!< 10: EXTI Line4                              */
-  DMA1_Stream0_IRQHandler,   /*!< 11: DMA1 Stream 0                           */
-  DMA1_Stream1_IRQHandler,   /*!< 12: DMA1 Stream 1                           */
-  DMA1_Stream2_IRQHandler,   /*!< 13: DMA1 Stream 2                           */
-  DMA1_Stream3_IRQHandler,   /*!< 14: DMA1 Stream 3                           */
-  DMA1_Stream4_IRQHandler,   /*!< 15: DMA1 Stream 4                           */
-  DMA1_Stream5_IRQHandler,   /*!< 16: DMA1 Stream 5                           */
-  DMA1_Stream6_IRQHandler,   /*!< 17: DMA1 Stream 6                           */
-  ADC_IRQHandler,            /*!< 18: ADC1, ADC2 and ADC3s                    */
-  CAN1_TX_IRQHandler,        /*!< 19: CAN1 TX                                 */
-  CAN1_RX0_IRQHandler,       /*!< 20: CAN1 RX0                                */
-  CAN1_RX1_IRQHandler,       /*!< 21: CAN1 RX1                                */
-  CAN1_SCE_IRQHandler,       /*!< 22: CAN1 SCE                                */
-  EXTI9_5_IRQHandler,        /*!< 23: External Line[9:5]s                     */
-  TIM1_BRK_TIM9_IRQHandler,  /*!< 24: TIM1 Break and TIM9                     */
-  TIM1_UP_TIM10_IRQHandler,  /*!< 25: TIM1 Update and TIM10                   */
-  TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/
-  TIM1_CC_IRQHandler,        /*!< 27: TIM1 Capture Compare                    */
-  TIM2_IRQHandler,           /*!< 28: TIM2                                    */
-  TIM3_IRQHandler,           /*!< 29: TIM3                                    */
-  TIM4_IRQHandler,           /*!< 30: TIM4                                    */
-  I2C1_EV_IRQHandler,        /*!< 31: I2C1 Event                              */
-  I2C1_ER_IRQHandler,        /*!< 32: I2C1 Error                              */
-  I2C2_EV_IRQHandler,        /*!< 33: I2C2 Event                              */
-  I2C2_ER_IRQHandler,        /*!< 34: I2C2 Error                              */
-  SPI1_IRQHandler,           /*!< 35: SPI1                                    */
-  SPI2_IRQHandler,           /*!< 36: SPI2                                    */
-  USART1_IRQHandler,         /*!< 37: USART1                                  */
-  USART2_IRQHandler,         /*!< 38: USART2                                  */
-  USART3_IRQHandler,         /*!< 39: USART3                                  */
-  EXTI15_10_IRQHandler,      /*!< 40: External Line[15:10]s                   */
-  RTC_Alarm_IRQHandler,      /*!< 41: RTC Alarm (A and B) through EXTI Line   */
-  OTG_FS_WKUP_IRQHandler,    /*!< 42: USB OTG FS Wakeup through EXTI line     */
-  TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12                    */
-  TIM8_UP_TIM13_IRQHandler,  /*!< 44: TIM8 Update and TIM13                   */
-  TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/
-  TIM8_CC_IRQHandler,        /*!< 46: TIM8 Capture Compare                    */
-  DMA1_Stream7_IRQHandler,   /*!< 47: DMA1 Stream7                            */
-  FSMC_IRQHandler,           /*!< 48: FSMC                                    */
-  SDIO_IRQHandler,           /*!< 49: SDIO                                    */
-  TIM5_IRQHandler,           /*!< 50: TIM5                                    */
-  SPI3_IRQHandler,           /*!< 51: SPI3                                    */
-  UART4_IRQHandler,          /*!< 52: UART4                                   */
-  UART5_IRQHandler,          /*!< 53: UART5                                   */
-  TIM6_DAC_IRQHandler,       /*!< 54: TIM6 and DAC1&2 underrun errors         */
-  TIM7_IRQHandler,           /*!< 55: TIM7                                    */
-  DMA2_Stream0_IRQHandler,   /*!< 56: DMA2 Stream 0                           */
-  DMA2_Stream1_IRQHandler,   /*!< 57: DMA2 Stream 1                           */
-  DMA2_Stream2_IRQHandler,   /*!< 58: DMA2 Stream 2                           */
-  DMA2_Stream3_IRQHandler,   /*!< 59: DMA2 Stream 3                           */
-  DMA2_Stream4_IRQHandler,   /*!< 60: DMA2 Stream 4                           */
-  ETH_IRQHandler,            /*!< 61: Ethernet                                */
-  ETH_WKUP_IRQHandler,       /*!< 62: Ethernet Wakeup through EXTI line       */
-  CAN2_TX_IRQHandler,        /*!< 63: CAN2 TX                                 */
-  CAN2_RX0_IRQHandler,       /*!< 64: CAN2 RX0                                */
-  CAN2_RX1_IRQHandler,       /*!< 65: CAN2 RX1                                */
-  CAN2_SCE_IRQHandler,       /*!< 66: CAN2 SCE                                */
-  OTG_FS_IRQHandler,         /*!< 67: USB OTG FS                              */
-  DMA2_Stream5_IRQHandler,   /*!< 68: DMA2 Stream 5                           */
-  DMA2_Stream6_IRQHandler,   /*!< 69: DMA2 Stream 6                           */
-  DMA2_Stream7_IRQHandler,   /*!< 70: DMA2 Stream 7                           */
-  USART6_IRQHandler,         /*!< 71: USART6                                  */
-  I2C3_EV_IRQHandler,        /*!< 72: I2C3 event                              */
-  I2C3_ER_IRQHandler,        /*!< 73: I2C3 error                              */
-  OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out              */
-  OTG_HS_EP1_IN_IRQHandler,  /*!< 75: USB OTG HS End Point 1 In               */
-  OTG_HS_WKUP_IRQHandler,    /*!< 76: USB OTG HS Wakeup through EXTI          */
-  OTG_HS_IRQHandler,         /*!< 77: USB OTG HS                              */
-  DCMI_IRQHandler,           /*!< 53: DCMI                                    */
-  CRYP_IRQHandler,           /*!< 53: CRYP crypto                             */
-  HASH_RNG_IRQHandler,       /*!< 53: Hash and Rng                            */
-  FPU_IRQHandler             /*!< 53: FPU                                     */
-  
-};
-
-/* C++ global constructors support */
-static void call_constructors(unsigned long *start, unsigned long *end)
-{
-   unsigned long *i;
-   void (*funcptr)();
-   for ( i = start; i < end; i++)
-   {
-     funcptr=(void (*)())(*i);
-     funcptr();
-   }
-}
-
-
-/**
-  * @brief  This is the code that gets called when the processor first
-  *         starts execution following a reset event. Only the absolutely
-  *         necessary set is performed, after which the application
-  *         supplied main() routine is called.
-  * @param  None
-  * @retval None
-  */
-void Default_Reset_Handler(void)
-{
-  /* Initialize data and bss */
-  unsigned long *pulSrc, *pulDest;
-
-  /* Copy the data segment initializers from flash to SRAM */
-  pulSrc = &_sidata;
-
-  for(pulDest = &_sdata; pulDest < &_edata; )
-  {
-    *(pulDest++) = *(pulSrc++);
-  }
-  
-  /* Zero fill the bss segment.  This is done with inline assembly since this
-     will clear the value of pulDest if it is not kept in a register. */
-  __asm("  ldr     r0, =_sbss\n"
-        "  ldr     r1, =_ebss\n"
-        "  mov     r2, #0\n"
-        "  .thumb_func\n"
-        "zero_loop:\n"
-        "    cmp     r0, r1\n"
-        "    it      lt\n"
-        "    strlt   r2, [r0], #4\n"
-        "    blt     zero_loop");
-#ifdef __FPU_USED
-  /* Enable FPU.*/ 
-  __asm("  LDR.W R0, =0xE000ED88\n"
-        "  LDR R1, [R0]\n"
-        "  ORR R1, R1, #(0xF << 20)\n"
-        "  STR R1, [R0]");
-#endif	
-
-  SystemInit();
- 
-  //Call C++ global constructors
-  call_constructors(&__preinit_array_start, &__preinit_array_end);
-  call_constructors(&__init_array_start, &__init_array_end);
-
-  /* Call the application's entry point.*/
-  main();
-}
-
-
-/**
-  *@brief Provide weak aliases for each Exception handler to the Default_Handler.
-  *       As they are weak aliases, any function with the same name will override
-  *       this definition.
-  */
-#pragma weak Reset_Handler = Default_Reset_Handler
-#pragma weak NMI_Handler = Default_Handler
-#pragma weak HardFault_Handler = Default_Handler
-#pragma weak MemManage_Handler = Default_Handler
-#pragma weak BusFault_Handler = Default_Handler
-#pragma weak UsageFault_Handler = Default_Handler
-#pragma weak SVC_Handler = Default_Handler
-#pragma weak DebugMon_Handler = Default_Handler
-#pragma weak PendSV_Handler = Default_Handler
-#pragma weak SysTick_Handler = Default_Handler
-
-#pragma weak WWDG_IRQHandler = Default_Handler
-#pragma weak PVD_IRQHandler = Default_Handler
-#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
-#pragma weak RTC_WKUP_IRQHandler = Default_Handler
-#pragma weak FLASH_IRQHandler = Default_Handler
-#pragma weak RCC_IRQHandler = Default_Handler
-#pragma weak EXTI0_IRQHandler = Default_Handler
-#pragma weak EXTI1_IRQHandler = Default_Handler
-#pragma weak EXTI2_IRQHandler = Default_Handler
-#pragma weak EXTI3_IRQHandler = Default_Handler
-#pragma weak EXTI4_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
-#pragma weak ADC_IRQHandler = Default_Handler
-#pragma weak CAN1_TX_IRQHandler = Default_Handler
-#pragma weak CAN1_RX0_IRQHandler = Default_Handler
-#pragma weak CAN1_RX1_IRQHandler = Default_Handler
-#pragma weak CAN1_SCE_IRQHandler = Default_Handler
-#pragma weak EXTI9_5_IRQHandler = Default_Handler
-#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
-#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
-#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
-#pragma weak TIM1_CC_IRQHandler = Default_Handler
-#pragma weak TIM2_IRQHandler = Default_Handler
-#pragma weak TIM3_IRQHandler = Default_Handler
-#pragma weak TIM4_IRQHandler = Default_Handler
-#pragma weak I2C1_EV_IRQHandler = Default_Handler
-#pragma weak I2C1_ER_IRQHandler = Default_Handler
-#pragma weak I2C2_EV_IRQHandler = Default_Handler
-#pragma weak I2C2_ER_IRQHandler = Default_Handler
-#pragma weak SPI1_IRQHandler = Default_Handler
-#pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_IRQHandler = Default_Handler
-#pragma weak EXTI15_10_IRQHandler = Default_Handler
-#pragma weak RTC_Alarm_IRQHandler = Default_Handler
-#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
-#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
-#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
-#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
-#pragma weak TIM8_CC_IRQHandler = Default_Handler
-#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
-#pragma weak FSMC_IRQHandler = Default_Handler
-#pragma weak SDIO_IRQHandler = Default_Handler
-#pragma weak TIM5_IRQHandler = Default_Handler
-#pragma weak SPI3_IRQHandler = Default_Handler
-#pragma weak UART4_IRQHandler = Default_Handler
-#pragma weak UART5_IRQHandler = Default_Handler
-#pragma weak TIM6_DAC_IRQHandler = Default_Handler
-#pragma weak TIM7_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
-#pragma weak ETH_IRQHandler = Default_Handler
-#pragma weak ETH_WKUP_IRQHandler = Default_Handler
-#pragma weak CAN2_TX_IRQHandler = Default_Handler
-#pragma weak CAN2_RX0_IRQHandler = Default_Handler
-#pragma weak CAN2_RX1_IRQHandler = Default_Handler
-#pragma weak CAN2_SCE_IRQHandler = Default_Handler
-#pragma weak OTG_FS_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
-#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
-#pragma weak USART6_IRQHandler = Default_Handler
-#pragma weak I2C3_EV_IRQHandler = Default_Handler
-#pragma weak I2C3_ER_IRQHandler = Default_Handler
-#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
-#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
-#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
-#pragma weak OTG_HS_IRQHandler = Default_Handler
-#pragma weak DCMI_IRQHandler = Default_Handler
-#pragma weak CRYP_IRQHandler = Default_Handler
-#pragma weak HASH_RNG_IRQHandler = Default_Handler
-#pragma weak FPU_IRQHandler = Default_Handler
-
-/**
-  * @brief  This is the code that gets called when the processor receives an
-  *         unexpected interrupt.  This simply enters an infinite loop,
-  *         preserving the system state for examination by a debugger.
-  * @param  None
-  * @retval None
-  */
-static void Default_Handler(void)
-{
-	/* Go into an infinite loop. */
-	while (1)
-	{
-	}
-}
-
-/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/

STM32F4XX_Lib/Device/stm32f4xx_conf.h

@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h  
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* If an external clock source is used, then the value of the following define 
-   should be set to the value of the external clock source, else, if no external 
-   clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *   which reports the name of the source file and the source
-  *   line number of the call that failed. 
-  *   If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/Device/system_stm32f4xx.h

@@ -1,105 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f4xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    22-April-2016
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F4xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
-  * @{
-  */
-
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/README.txt

@@ -1,21 +0,0 @@
-STM32F4XX library for MMDVM project
-
-This is the STM32F4XX_Lib directory structure with just the needed code for MMDVM.
-Copy this STM32F4XX_Lib directory inside the MMDVM source code project. You have to
-conserve the STM32F4XX_Lib folder name: MMDVM/STM32F4XX_Lib
-
-The source of this package can be found here:
-http://www.st.com/en/embedded-software/stsw-stm32065.html
-
-In order to run the MMDVM firmware correctly, there are the following modifications
-already done in this package:
-
-1) STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c :
-- Added C++ global constructors support
-- Changed initial stack pointer
-
-2) STM32F4XX_Lib/Device/system_stm32f4xx.c :
-- Changed PLL_M definition (support "integer" only crystal frequencies: 8, 12, 16 MHz, etc)
-
-3) STM32F4XX_Lib/Device/stm32f4xx_conf.h :
-- Peripheral header file inclusions

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/misc.h

@@ -1,178 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the miscellaneous
-  *          firmware library functions (add-on to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  NVIC Init Structure definition  
-  */
-
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be an enumerator of @ref IRQn_Type 
-                                                   enumeration (For the complete STM32 Devices IRQ Channels
-                                                   list, please refer to stm32f4xx.h file) */
-
-  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
-                                                   specified in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
-                                                   in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled. 
-                                                   This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
- 
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup MISC_Vector_Table_Base 
-  * @{
-  */
-
-#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
-                                  ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_System_Low_Power 
-  * @{
-  */
-
-#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Preemption_Priority_Group 
-  * @{
-  */
-
-#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
-                                                            4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
-                                                            3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
-                                                            2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
-                                                            1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
-                                                            0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
-                                       ((GROUP) == NVIC_PriorityGroup_1) || \
-                                       ((GROUP) == NVIC_PriorityGroup_2) || \
-                                       ((GROUP) == NVIC_PriorityGroup_3) || \
-                                       ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_SysTick_clock_source 
-  * @{
-  */
-
-#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
-                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_adc.h

@@ -1,656 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_adc.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the ADC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_H
-#define __STM32F4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief   ADC Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
-                                               This parameter can be a value of @ref ADC_resolution */                                   
-  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
-                                               is performed in Scan (multichannels) 
-                                               or Single (one channel) mode.
-                                               This parameter can be set to ENABLE or DISABLE */ 
-  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
-                                               is performed in Continuous or Single mode.
-                                               This parameter can be set to ENABLE or DISABLE. */
-  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
-                                               enable the trigger of a regular group. 
-                                               This parameter can be a value of 
-                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
-  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
-                                               the start of conversion of a regular group.
-                                               This parameter can be a value of 
-                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
-  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
-                                               is left or right. This parameter can be 
-                                               a value of @ref ADC_data_align */
-  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
-                                               that will be done using the sequencer for
-                                               regular channel group.
-                                               This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-  
-/** 
-  * @brief   ADC Common Init structure definition  
-  */ 
-typedef struct 
-{
-  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
-                                               independent or multi mode. 
-                                               This parameter can be a value of @ref ADC_Common_mode */                                              
-  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
-                                               to the ADC. The clock is common for all the ADCs.
-                                               This parameter can be a value of @ref ADC_Prescaler */
-  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
-                                              mode for multi ADC mode.
-                                               This parameter can be a value of 
-                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
-  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
-                                               This parameter can be a value of 
-                                               @ref ADC_delay_between_2_sampling_phases */
-  
-}ADC_CommonInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
-  * @{
-  */ 
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
-                                   ((PERIPH) == ADC2) || \
-                                   ((PERIPH) == ADC3))  
-
-/** @defgroup ADC_Common_mode 
-  * @{
-  */ 
-#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
-#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
-#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
-#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
-#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
-#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
-#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
-#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
-#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
-#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
-#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
-#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
-#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
-                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_DualMode_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult) || \
-                           ((MODE) == ADC_DualMode_Interl) || \
-                           ((MODE) == ADC_DualMode_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult) || \
-                           ((MODE) == ADC_TripleMode_Interl) || \
-                           ((MODE) == ADC_TripleMode_AlterTrig))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Prescaler 
-  * @{
-  */ 
-#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
-#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
-#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
-#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div8))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
-  * @{
-  */ 
-#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
-#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
-                                      ((MODE) == ADC_DMAAccessMode_1) || \
-                                      ((MODE) == ADC_DMAAccessMode_2) || \
-                                      ((MODE) == ADC_DMAAccessMode_3))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_delay_between_2_sampling_phases 
-  * @{
-  */ 
-#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
-#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
-#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
-#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
-#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
-#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
-#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
-#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
-#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
-#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
-#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
-#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
-#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
-#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
-#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
-#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_resolution 
-  * @{
-  */ 
-#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
-#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
-#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
-#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
-                                       ((RESOLUTION) == ADC_Resolution_10b) || \
-                                       ((RESOLUTION) == ADC_Resolution_8b) || \
-                                       ((RESOLUTION) == ADC_Resolution_6b))
-                                      
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
-#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
-#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
-#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
-#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
-#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
-#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
-#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
-#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
-#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
-#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
-#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
-#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
-#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
-#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
-#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_data_align 
-  * @{
-  */ 
-#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
-                                  ((ALIGN) == ADC_DataAlign_Left))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_channels 
-  * @{
-  */ 
-#define ADC_Channel_0                               ((uint8_t)0x00)
-#define ADC_Channel_1                               ((uint8_t)0x01)
-#define ADC_Channel_2                               ((uint8_t)0x02)
-#define ADC_Channel_3                               ((uint8_t)0x03)
-#define ADC_Channel_4                               ((uint8_t)0x04)
-#define ADC_Channel_5                               ((uint8_t)0x05)
-#define ADC_Channel_6                               ((uint8_t)0x06)
-#define ADC_Channel_7                               ((uint8_t)0x07)
-#define ADC_Channel_8                               ((uint8_t)0x08)
-#define ADC_Channel_9                               ((uint8_t)0x09)
-#define ADC_Channel_10                              ((uint8_t)0x0A)
-#define ADC_Channel_11                              ((uint8_t)0x0B)
-#define ADC_Channel_12                              ((uint8_t)0x0C)
-#define ADC_Channel_13                              ((uint8_t)0x0D)
-#define ADC_Channel_14                              ((uint8_t)0x0E)
-#define ADC_Channel_15                              ((uint8_t)0x0F)
-#define ADC_Channel_16                              ((uint8_t)0x10)
-#define ADC_Channel_17                              ((uint8_t)0x11)
-#define ADC_Channel_18                              ((uint8_t)0x12)
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG)
-#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
-#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_18)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
-
-#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
-#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
-                                 ((CHANNEL) == ADC_Channel_1) || \
-                                 ((CHANNEL) == ADC_Channel_2) || \
-                                 ((CHANNEL) == ADC_Channel_3) || \
-                                 ((CHANNEL) == ADC_Channel_4) || \
-                                 ((CHANNEL) == ADC_Channel_5) || \
-                                 ((CHANNEL) == ADC_Channel_6) || \
-                                 ((CHANNEL) == ADC_Channel_7) || \
-                                 ((CHANNEL) == ADC_Channel_8) || \
-                                 ((CHANNEL) == ADC_Channel_9) || \
-                                 ((CHANNEL) == ADC_Channel_10) || \
-                                 ((CHANNEL) == ADC_Channel_11) || \
-                                 ((CHANNEL) == ADC_Channel_12) || \
-                                 ((CHANNEL) == ADC_Channel_13) || \
-                                 ((CHANNEL) == ADC_Channel_14) || \
-                                 ((CHANNEL) == ADC_Channel_15) || \
-                                 ((CHANNEL) == ADC_Channel_16) || \
-                                 ((CHANNEL) == ADC_Channel_17) || \
-                                 ((CHANNEL) == ADC_Channel_18))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_sampling_times 
-  * @{
-  */ 
-#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
-#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
-#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
-#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
-#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
-#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
-#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
-#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
-                                  ((TIME) == ADC_SampleTime_15Cycles) || \
-                                  ((TIME) == ADC_SampleTime_28Cycles) || \
-                                  ((TIME) == ADC_SampleTime_56Cycles) || \
-                                  ((TIME) == ADC_SampleTime_84Cycles) || \
-                                  ((TIME) == ADC_SampleTime_112Cycles) || \
-                                  ((TIME) == ADC_SampleTime_144Cycles) || \
-                                  ((TIME) == ADC_SampleTime_480Cycles))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
-#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
-                                            
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
-#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
-#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
-#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
-#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
-#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
-#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
-#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
-#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
-#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
-#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
-#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
-#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_channel_selection 
-  * @{
-  */ 
-#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
-#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
-#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_analog_watchdog_selection 
-  * @{
-  */ 
-#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_interrupts_definition 
-  * @{
-  */ 
-#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
-#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
-#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
-#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
-                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_flags_definition 
-  * @{
-  */ 
-#define ADC_FLAG_AWD                               ((uint8_t)0x01)
-#define ADC_FLAG_EOC                               ((uint8_t)0x02)
-#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
-#define ADC_FLAG_STRT                              ((uint8_t)0x10)
-#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
-  
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
-                               ((FLAG) == ADC_FLAG_EOC) || \
-                               ((FLAG) == ADC_FLAG_JEOC) || \
-                               ((FLAG)== ADC_FLAG_JSTRT) || \
-                               ((FLAG) == ADC_FLAG_STRT) || \
-                               ((FLAG)== ADC_FLAG_OVR))     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_thresholds 
-  * @{
-  */ 
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_offset 
-  * @{
-  */ 
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_length 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_rank 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_length 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_rank 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_discontinuous_mode_number 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the ADC configuration to the default reset state *****/  
-void ADC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and VBAT management functions ******************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-void ADC_VBATCmd(FunctionalState NewState);
-
-/* Regular Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetMultiModeConversionValue(void);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h

@@ -1,304 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dac.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the DAC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DAC_H
-#define __STM32F4xx_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DAC Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
-                                                  This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
-                                                  are generated, or whether no wave is generated.
-                                                  This parameter can be a value of @ref DAC_wave_generation */
-
-  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
-                                                  the maximum amplitude triangle generation for the DAC channel. 
-                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
-  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                                  This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup DAC_trigger_selection 
-  * @{
-  */
-
-#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-
-#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
-                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
-                                 ((TRIGGER) == DAC_Trigger_Software))
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
-                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
-                                    ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
-  * @{
-  */
-
-#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer 
-  * @{
-  */
-
-#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
-                                           ((STATE) == DAC_OutputBuffer_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection 
-  * @{
-  */
-
-#define DAC_Channel_1                      ((uint32_t)0x00000000)
-#define DAC_Channel_2                      ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
-                                 ((CHANNEL) == DAC_Channel_2))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement 
-  * @{
-  */
-
-#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
-#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
-#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
-                             ((ALIGN) == DAC_Align_12b_L) || \
-                             ((ALIGN) == DAC_Align_8b_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
-                           ((WAVE) == DAC_Wave_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data 
-  * @{
-  */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_interrupts_definition 
-  * @{
-  */   
-#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup DAC_flags_definition 
-  * @{
-  */ 
-  
-#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the DAC configuration to the default reset state *****/  
-void DAC_DeInit(void);
-
-/*  DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DAC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h

@@ -1,564 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_gpio.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the GPIO firmware
-  *          library.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_GPIO_H
-#define __STM32F4xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
-                                    ((PERIPH) == GPIOB) || \
-                                    ((PERIPH) == GPIOC) || \
-                                    ((PERIPH) == GPIOD) || \
-                                    ((PERIPH) == GPIOE) || \
-                                    ((PERIPH) == GPIOF) || \
-                                    ((PERIPH) == GPIOG) || \
-                                    ((PERIPH) == GPIOH) || \
-                                    ((PERIPH) == GPIOI) || \
-                                    ((PERIPH) == GPIOJ) || \
-                                    ((PERIPH) == GPIOK))
-
-/** 
-  * @brief  GPIO Configuration Mode enumeration 
-  */   
-typedef enum
-{ 
-  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
-  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
-  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
-  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
-                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-
-/** 
-  * @brief  GPIO Output type enumeration 
-  */  
-typedef enum
-{ 
-  GPIO_OType_PP = 0x00,
-  GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-
-/** 
-  * @brief  GPIO Output Maximum frequency enumeration 
-  */  
-typedef enum
-{ 
-  GPIO_Low_Speed     = 0x00, /*!< Low speed    */
-  GPIO_Medium_Speed  = 0x01, /*!< Medium speed */
-  GPIO_Fast_Speed    = 0x02, /*!< Fast speed   */
-  GPIO_High_Speed    = 0x03  /*!< High speed   */
-}GPIOSpeed_TypeDef;
-
-/* Add legacy definition */
-#define  GPIO_Speed_2MHz    GPIO_Low_Speed    
-#define  GPIO_Speed_25MHz   GPIO_Medium_Speed 
-#define  GPIO_Speed_50MHz   GPIO_Fast_Speed 
-#define  GPIO_Speed_100MHz  GPIO_High_Speed  
-  
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
-                              ((SPEED) == GPIO_Fast_Speed)||  ((SPEED) == GPIO_High_Speed)) 
-
-/** 
-  * @brief  GPIO Configuration PullUp PullDown enumeration 
-  */ 
-typedef enum
-{ 
-  GPIO_PuPd_NOPULL = 0x00,
-  GPIO_PuPd_UP     = 0x01,
-  GPIO_PuPd_DOWN   = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
-                            ((PUPD) == GPIO_PuPd_DOWN))
-
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */ 
-typedef enum
-{ 
-  Bit_RESET = 0,
-  Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-
-/** 
-  * @brief   GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
-                                       This parameter can be any value of @ref GPIO_pins_define */
-
-  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
-                                       This parameter can be a value of @ref GPIOMode_TypeDef */
-
-  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
-                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
-  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
-                                       This parameter can be a value of @ref GPIOOType_TypeDef */
-
-  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define 
-  * @{
-  */ 
-#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
-#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
-#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
-#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
-#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
-#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
-#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
-#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
-#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
-#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
-#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
-#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
-#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
-#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
-#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
-#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
-#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
-                              ((PIN) == GPIO_Pin_1) || \
-                              ((PIN) == GPIO_Pin_2) || \
-                              ((PIN) == GPIO_Pin_3) || \
-                              ((PIN) == GPIO_Pin_4) || \
-                              ((PIN) == GPIO_Pin_5) || \
-                              ((PIN) == GPIO_Pin_6) || \
-                              ((PIN) == GPIO_Pin_7) || \
-                              ((PIN) == GPIO_Pin_8) || \
-                              ((PIN) == GPIO_Pin_9) || \
-                              ((PIN) == GPIO_Pin_10) || \
-                              ((PIN) == GPIO_Pin_11) || \
-                              ((PIN) == GPIO_Pin_12) || \
-                              ((PIN) == GPIO_Pin_13) || \
-                              ((PIN) == GPIO_Pin_14) || \
-                              ((PIN) == GPIO_Pin_15))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup GPIO_Pin_sources 
-  * @{
-  */ 
-#define GPIO_PinSource0            ((uint8_t)0x00)
-#define GPIO_PinSource1            ((uint8_t)0x01)
-#define GPIO_PinSource2            ((uint8_t)0x02)
-#define GPIO_PinSource3            ((uint8_t)0x03)
-#define GPIO_PinSource4            ((uint8_t)0x04)
-#define GPIO_PinSource5            ((uint8_t)0x05)
-#define GPIO_PinSource6            ((uint8_t)0x06)
-#define GPIO_PinSource7            ((uint8_t)0x07)
-#define GPIO_PinSource8            ((uint8_t)0x08)
-#define GPIO_PinSource9            ((uint8_t)0x09)
-#define GPIO_PinSource10           ((uint8_t)0x0A)
-#define GPIO_PinSource11           ((uint8_t)0x0B)
-#define GPIO_PinSource12           ((uint8_t)0x0C)
-#define GPIO_PinSource13           ((uint8_t)0x0D)
-#define GPIO_PinSource14           ((uint8_t)0x0E)
-#define GPIO_PinSource15           ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
-                                       ((PINSOURCE) == GPIO_PinSource1) || \
-                                       ((PINSOURCE) == GPIO_PinSource2) || \
-                                       ((PINSOURCE) == GPIO_PinSource3) || \
-                                       ((PINSOURCE) == GPIO_PinSource4) || \
-                                       ((PINSOURCE) == GPIO_PinSource5) || \
-                                       ((PINSOURCE) == GPIO_PinSource6) || \
-                                       ((PINSOURCE) == GPIO_PinSource7) || \
-                                       ((PINSOURCE) == GPIO_PinSource8) || \
-                                       ((PINSOURCE) == GPIO_PinSource9) || \
-                                       ((PINSOURCE) == GPIO_PinSource10) || \
-                                       ((PINSOURCE) == GPIO_PinSource11) || \
-                                       ((PINSOURCE) == GPIO_PinSource12) || \
-                                       ((PINSOURCE) == GPIO_PinSource13) || \
-                                       ((PINSOURCE) == GPIO_PinSource14) || \
-                                       ((PINSOURCE) == GPIO_PinSource15))
-/**
-  * @}
-  */ 
-
-/** @defgroup GPIO_Alternat_function_selection_define 
-  * @{
-  */ 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF0_TIM2         ((uint8_t)0x00)  /* TIM2 Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-#if defined(STM32F410xx)
-#define GPIO_AF_LPTIM         ((uint8_t)0x01)  /* LPTIM Alternate Function mapping */
-#endif /* STM32F410xx */
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
-#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF3_CEC          ((uint8_t)0x03)  /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF4_CEC          ((uint8_t)0x04)  /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
-#define GPIO_AF_FMPI2C        ((uint8_t)0x04)  /* FMPI2C Alternate Function mapping */
-#endif /* STM32F410xx || STM32F446xx */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3         ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
-#define GPIO_AF_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping */
-#define GPIO_AF_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping      */
-#define GPIO_AF_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping      */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_SPI1         ((uint8_t)0x06)  /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
-#define GPIO_AF6_SPI2         ((uint8_t)0x06)  /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF6_SPI4         ((uint8_t)0x06)  /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
-#define GPIO_AF6_SPI5         ((uint8_t)0x06)  /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping      */
-#define GPIO_AF_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG Devices) */
-#if defined(STM32F412xG)
-#define GPIO_AF6_DFSDM1       ((uint8_t)0x06)  /* DFSDM Alternate Function mapping */
-#endif /* STM32F412xG */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF_USART1         ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
-#define GPIO_AF_USART2         ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
-#define GPIO_AF_USART3         ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3ext Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection Legacy 
-  */ 
-#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-#if defined(STM32F412xG)
-#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
-#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM Alternate Function mapping  */
-#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
-#endif /* STM32F412xG */
-#if defined(STM32F446xx)
-#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping */
-#define GPIO_AF_SPDIF         ((uint8_t)0x08)   /* SPDIF Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2         ((uint8_t)0x09)  /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG Devices) */
-#define GPIO_AF9_I2C3         ((uint8_t)0x09)  /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG Devices) */
-#if defined(STM32F446xx)
-#define GPIO_AF9_SAI2         ((uint8_t)0x09)  /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#define GPIO_AF9_LTDC         ((uint8_t)0x09)  /* LTDC Alternate Function mapping */
-#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF9_QUADSPI      ((uint8_t)0x09)  /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F410xx) || defined(STM32F412xG)
-#define GPIO_AF9_FMPI2C       ((uint8_t)0x09)  /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
-#endif /* STM32F410xx || STM32F412xG */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF10_SAI2         ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F412xG)
-#define GPIO_AF10_FMC           ((uint8_t)0xA)  /* FMC Alternate Function mapping    */
-#define GPIO_AF10_DFSDM         ((uint8_t)0xA)  /* DFSDM Alternate Function mapping  */
-#endif /* STM32F412xG */
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#if defined(STM32F40_41xxx) || defined(STM32F412xG)
-#define GPIO_AF_FSMC             ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF_FMC              ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define GPIO_AF_OTG_HS_FS        ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF_SDIO             ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-#if defined(STM32F469_479xx)
-#define GPIO_AF_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping */
-#endif /* STM32F469_479xx */
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-#if defined(STM32F40_41xxx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
-                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_FSMC))
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F401xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4))
-#endif /* STM32F401xx */
-
-#if defined(STM32F411xE)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
-#endif /* STM32F411xE */
-
-#if defined(STM32F410xx)
-#define IS_GPIO_AF(AF)   (((AF) < 10) || ((AF) == 15))
-#endif /* STM32F410xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
-                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4)      || \
-                          ((AF) == GPIO_AF_SPI5)      || ((AF) == GPIO_AF_SPI6)      || \
-                          ((AF) == GPIO_AF_UART7)     || ((AF) == GPIO_AF_UART8)     || \
-                          ((AF) == GPIO_AF_FMC)       ||  ((AF) == GPIO_AF_SAI1)     || \
-                          ((AF) == GPIO_AF_LTDC))
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-#if defined(STM32F412xG)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F412xG */
-
-#if defined(STM32F446xx)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F446xx */
-
-#if defined(STM32F469_479xx)
-#define IS_GPIO_AF(AF)   ((AF) < 16)
-#endif /* STM32F469_479xx */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup GPIO_Legacy 
-  * @{
-  */
-    
-#define GPIO_Mode_AIN           GPIO_Mode_AN
-
-#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
-#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
-#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/*  Function used to set the GPIO configuration to the default reset state ****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Alternate functions configuration function ****************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_GPIO_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h

@@ -1,982 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_rcc.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the RCC firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RCC_H
-#define __STM32F4xx_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct
-{
-  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
-  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz   */
-  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz  */
-  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz  */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
-  * @{
-  */
-  
-/** @defgroup RCC_HSE_configuration 
-  * @{
-  */
-#define RCC_HSE_OFF                      ((uint8_t)0x00)
-#define RCC_HSE_ON                       ((uint8_t)0x01)
-#define RCC_HSE_Bypass                   ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_Bypass))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_LSE_Dual_Mode_Selection
-  * @{
-  */
-#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
-#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
-#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
-                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLSAIDivR_Factor
-  * @{
-  */
-#define RCC_PLLSAIDivR_Div2                ((uint32_t)0x00000000)
-#define RCC_PLLSAIDivR_Div4                ((uint32_t)0x00010000)
-#define RCC_PLLSAIDivR_Div8                ((uint32_t)0x00020000)
-#define RCC_PLLSAIDivR_Div16               ((uint32_t)0x00030000)
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
-                                        ((VALUE) == RCC_PLLSAIDivR_Div4)  ||\
-                                        ((VALUE) == RCC_PLLSAIDivR_Div8)  ||\
-                                        ((VALUE) == RCC_PLLSAIDivR_Div16))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source 
-  * @{
-  */
-#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
-                                   ((SOURCE) == RCC_PLLSource_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#if defined(STM32F446xx) 
-#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
-#elif  defined(STM32F412xG)
-#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#else
-#endif /* STM32F446xx */
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#endif /* STM32F446xx || STM32F469_479xx */
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_System_Clock_Source 
-  * @{
-  */
-
-#if  defined(STM32F412xG) || defined(STM32F446xx)
-#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLPCLK         ((uint32_t)0x00000002)
-#define RCC_SYSCLKSource_PLLRCLK         ((uint32_t)0x00000003)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
-/* Add legacy definition */
-#define  RCC_SYSCLKSource_PLLCLK    RCC_SYSCLKSource_PLLPCLK  
-#endif /* STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_AHB_Clock_Source
-  * @{
-  */
-#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
-#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
-#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
-#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
-                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
-                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
-                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
-                           ((HCLK) == RCC_SYSCLK_Div512))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_APB1_APB2_Clock_Source
-  * @{
-  */
-#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
-#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
-#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
-#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
-                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
-                           ((PCLK) == RCC_HCLK_Div16))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_Interrupt_Source 
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20) 
-#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40)
-#define RCC_IT_CSS                       ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
-                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
-                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
-                           ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
-#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_LSE_Configuration 
-  * @{
-  */
-#define RCC_LSE_OFF                      ((uint8_t)0x00)
-#define RCC_LSE_ON                       ((uint8_t)0x01)
-#define RCC_LSE_Bypass                   ((uint8_t)0x04)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_Bypass))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_RTC_Clock_Source
-  * @{
-  */
-#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
-#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
-#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
-#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
-#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
-#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
-#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
-#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
-#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
-#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
-#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
-#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
-#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
-#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
-#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
-#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
-#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
-#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
-#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
-#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
-#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
-#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
-#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
-#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
-#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
-#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
-#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
-#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
-#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
-#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
-#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
-/**
-  * @}
-  */ 
-
-#if defined(STM32F410xx)
-/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK            ((uint32_t)0x00000000)
-#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
-#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
-#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-
-#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
-                                           ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-/* Legacy Defines */
-#define IS_RCC_LPTIM1_SOURCE           IS_RCC_LPTIM1_CLOCKSOURCE
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
-  * @{
-  */
-#define RCC_I2SAPBCLKSOURCE_PLLR            ((uint32_t)0x00000000)
-#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
-#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
-                                      ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 
-/**
-  * @}
-  */
-
-#endif /* STM32F410xx */
-
-#if defined(STM32F412xG) || defined(STM32F446xx)
-/** @defgroup RCC_I2S_Clock_Source
-  * @{
-  */
-#define RCC_I2SCLKSource_PLLI2S             ((uint32_t)0x00)
-#define RCC_I2SCLKSource_Ext                ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SCLKSource_PLL                ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SCLKSource_HSI_HSE            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
-                                      ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))                                
-/**
-  * @}
-  */
-
-/** @defgroup RCC_I2S_APBBus
-  * @{
-  */
-#define RCC_I2SBus_APB1             ((uint8_t)0x00)
-#define RCC_I2SBus_APB2             ((uint8_t)0x01)
-#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))                                
-/**
-  * @}
-  */
-#if defined(STM32F446xx)    
-/** @defgroup RCC_SAI_Clock_Source
-  * @{
-  */
-#define RCC_SAICLKSource_PLLSAI             ((uint32_t)0x00)
-#define RCC_SAICLKSource_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
-#define RCC_SAICLKSource_PLL                ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
-#define RCC_SAICLKSource_HSI_HSE            ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
-
-#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
-                                      ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))                                
-/**
-  * @}
-  */    
-    
-/** @defgroup RCC_SAI_Instance
-  * @{
-  */
-#define RCC_SAIInstance_SAI1             ((uint8_t)0x00)
-#define RCC_SAIInstance_SAI2             ((uint8_t)0x01)
-#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))                                
-/**
-  * @}
-  */
-#endif /* STM32F446xx */
-#endif /* STM32F412xG || STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-/** @defgroup RCC_I2S_Clock_Source
-  * @{
-  */
-#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_SAI_BlockA_Clock_Source
-  * @{
-  */
-#define RCC_SAIACLKSource_PLLSAI             ((uint32_t)0x00000000)
-#define RCC_SAIACLKSource_PLLI2S             ((uint32_t)0x00100000)
-#define RCC_SAIACLKSource_Ext                ((uint32_t)0x00200000)
-
-#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
-                                       ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
-                                       ((SOURCE) == RCC_SAIACLKSource_Ext))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_SAI_BlockB_Clock_Source
-  * @{
-  */
-#define RCC_SAIBCLKSource_PLLSAI             ((uint32_t)0x00000000)
-#define RCC_SAIBCLKSource_PLLI2S             ((uint32_t)0x00400000)
-#define RCC_SAIBCLKSource_Ext                ((uint32_t)0x00800000)
-
-#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
-                                       ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
-                                       ((SOURCE) == RCC_SAIBCLKSource_Ext))
-/**
-  * @}
-  */ 
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-
-/** @defgroup RCC_TIM_PRescaler_Selection
-  * @{
-  */
-#define RCC_TIMPrescDesactivated             ((uint8_t)0x00)
-#define RCC_TIMPrescActivated                ((uint8_t)0x01)
-
-#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
-/**
-  * @}
-  */
-
-#if defined(STM32F469_479xx)
-/** @defgroup RCC_DSI_Clock_Source_Selection
-  * @{
-  */
-#define RCC_DSICLKSource_PHY                ((uint8_t)0x00)
-#define RCC_DSICLKSource_PLLR               ((uint8_t)0x01)
-#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
-                                             ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
-/**
-  * @}
-  */
-#endif /* STM32F469_479xx */
-
-#if  defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/** @defgroup RCC_SDIO_Clock_Source_Selection
-  * @{
-  */
-#define RCC_SDIOCLKSource_48MHZ              ((uint8_t)0x00)
-#define RCC_SDIOCLKSource_SYSCLK             ((uint8_t)0x01)
-#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
-                                              ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_48MHZ_Clock_Source_Selection
-  * @{
-  */
-#if  defined(STM32F446xx) || defined(STM32F469_479xx)
-#define RCC_48MHZCLKSource_PLL                ((uint8_t)0x00)
-#define RCC_48MHZCLKSource_PLLSAI             ((uint8_t)0x01)
-#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
-                                               ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
-#endif /* STM32F446xx || STM32F469_479xx */
-#if defined(STM32F412xG)
-#define RCC_CK48CLKSOURCE_PLLQ                ((uint8_t)0x00)
-#define RCC_CK48CLKSOURCE_PLLI2SQ             ((uint8_t)0x01) /* Only for STM32F412xG Devices */    
-#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
-                                               ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
-#endif /* STM32F412xG */
-/**
-  * @}
-  */
-#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx) 
-/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
-  * @{
-  */
-#define RCC_SPDIFRXCLKSource_PLLR                 ((uint8_t)0x00)
-#define RCC_SPDIFRXCLKSource_PLLI2SP              ((uint8_t)0x01)
-#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
-                                                   ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_CEC_Clock_Source_Selection
-  * @{
-  */
-#define RCC_CECCLKSource_HSIDiv488            ((uint8_t)0x00)
-#define RCC_CECCLKSource_LSE                  ((uint8_t)0x01)
-#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
-                                               ((CLKSOURCE) == RCC_CECCLKSource_LSE))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_ClockGating
-  * @{
-  */ 
-#define RCC_AHB1ClockGating_APB1Bridge         ((uint32_t)0x00000001)
-#define RCC_AHB1ClockGating_APB2Bridge         ((uint32_t)0x00000002)
-#define RCC_AHB1ClockGating_CM4DBG             ((uint32_t)0x00000004)
-#define RCC_AHB1ClockGating_SPARE              ((uint32_t)0x00000008)
-#define RCC_AHB1ClockGating_SRAM               ((uint32_t)0x00000010)
-#define RCC_AHB1ClockGating_FLITF              ((uint32_t)0x00000020)
-#define RCC_AHB1ClockGating_RCC                ((uint32_t)0x00000040)
-
-#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */
-#endif /* STM32F446xx */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
-/** @defgroup RCC_FMPI2C1_Clock_Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSource_APB1            ((uint32_t)0x00)
-#define RCC_FMPI2C1CLKSource_SYSCLK          ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSource_HSI             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-    
-#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
-                                            ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
-/**
-  * @}
-  */
-#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
-
-#if defined(STM32F412xG)
-/** @defgroup RCC_DFSDM_Clock_Source
- * @{
- */
-#define RCC_DFSDM1CLKSource_APB             ((uint8_t)0x00)
-#define RCC_DFSDM1CLKSource_SYS             ((uint8_t)0x01)
-#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_DFSDM_Audio_Clock_Source  RCC DFSDM Audio Clock Source
-  * @{
-  */
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1          ((uint32_t)0x00000000)
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2          ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
-#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
-/**
-  * @}
-  */
-#endif /* STM32F412xG */
-
-/** @defgroup RCC_AHB1_Peripherals 
-  * @{
-  */ 
-#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
-#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
-#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
-#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
-#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
-#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
-#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
-#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
-#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100) 
-#define RCC_AHB1Periph_GPIOJ             ((uint32_t)0x00000200)
-#define RCC_AHB1Periph_GPIOK             ((uint32_t)0x00000400)
-#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
-#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
-#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
-#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
-#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
-#define RCC_AHB1Periph_SRAM3             ((uint32_t)0x00080000)
-#define RCC_AHB1Periph_CCMDATARAMEN      ((uint32_t)0x00100000)
-#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
-#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
-#define RCC_AHB1Periph_DMA2D             ((uint32_t)0x00800000)
-#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
-#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
-#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
-#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
-#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
-#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
-#if defined(STM32F410xx)
-#define RCC_AHB1Periph_RNG               ((uint32_t)0x80000000)
-#endif /* STM32F410xx */
-#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_AHB2_Peripherals 
-  * @{
-  */  
-#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
-#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
-#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)    
-#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
-#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_AHB3_Peripherals 
-  * @{
-  */ 
-#if defined(STM32F40_41xxx)
-#define RCC_AHB3Periph_FSMC                ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define RCC_AHB3Periph_FMC                 ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx) 
-#define RCC_AHB3Periph_FMC                 ((uint32_t)0x00000001)
-#define RCC_AHB3Periph_QSPI                ((uint32_t)0x00000002)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F446xx ||  STM32F469_479xx */
-
-#if defined(STM32F412xG)
-#define RCC_AHB3Periph_FSMC                 ((uint32_t)0x00000001)
-#define RCC_AHB3Periph_QSPI                 ((uint32_t)0x00000002)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F412xG */
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_APB1_Peripherals 
-  * @{
-  */ 
-#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
-#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
-#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
-#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
-#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
-#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
-#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
-#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
-#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
-#if defined(STM32F410xx)
-#define RCC_APB1Periph_LPTIM1            ((uint32_t)0x00000200)
-#endif /* STM32F410xx */
-#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
-#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
-#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
-#if defined(STM32F446xx)
-#define RCC_APB1Periph_SPDIFRX           ((uint32_t)0x00010000)
-#endif /* STM32F446xx */ 
-#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
-#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
-#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
-#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
-#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
-#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
-#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
-#define RCC_APB1Periph_FMPI2C1           ((uint32_t)0x01000000)
-#endif /* STM32F410xx || STM32F446xx */ 
-#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
-#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
-#if defined(STM32F446xx)
-#define RCC_APB1Periph_CEC               ((uint32_t)0x08000000)
-#endif /* STM32F446xx */ 
-#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
-#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
-#define RCC_APB1Periph_UART7             ((uint32_t)0x40000000)
-#define RCC_APB1Periph_UART8             ((uint32_t)0x80000000)
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_APB2_Peripherals 
-  * @{
-  */ 
-#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
-#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
-#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
-#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
-#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
-#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
-#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
-#define RCC_APB2Periph_SPI4              ((uint32_t)0x00002000)
-#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
-#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
-#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
-#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
-#define RCC_APB2Periph_SPI5              ((uint32_t)0x00100000)
-#define RCC_APB2Periph_SPI6              ((uint32_t)0x00200000)
-#define RCC_APB2Periph_SAI1              ((uint32_t)0x00400000)
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define RCC_APB2Periph_SAI2              ((uint32_t)0x00800000)
-#endif /* STM32F446xx || STM32F469_479xx */
-#define RCC_APB2Periph_LTDC              ((uint32_t)0x04000000)
-#if defined(STM32F469_479xx)
-#define RCC_APB2Periph_DSI               ((uint32_t)0x08000000)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG)
-#define RCC_APB2Periph_DFSDM             ((uint32_t)0x01000000)
-#endif /* STM32F412xG */
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_MCO1_Clock_Source_Prescaler
-  * @{
-  */
-#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
-#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
-#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
-#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
-#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
-#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
-#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
-#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
-#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
-                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
-                                   
-#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
-                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
-                             ((DIV) == RCC_MCO1Div_5)) 
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_MCO2_Clock_Source_Prescaler
-  * @{
-  */
-#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
-#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
-#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
-#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
-#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
-#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
-#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
-#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
-#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
-                                   
-#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
-                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
-                             ((DIV) == RCC_MCO2Div_5))                             
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_Flag 
-  * @{
-  */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
-#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3D)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)   || ((FLAG) == RCC_FLAG_HSERDY) || \
-                           ((FLAG) == RCC_FLAG_PLLRDY)   || ((FLAG) == RCC_FLAG_LSERDY) || \
-                           ((FLAG) == RCC_FLAG_LSIRDY)   || ((FLAG) == RCC_FLAG_BORRST) || \
-                           ((FLAG) == RCC_FLAG_PINRST)   || ((FLAG) == RCC_FLAG_PORRST) || \
-                           ((FLAG) == RCC_FLAG_SFTRST)   || ((FLAG) == RCC_FLAG_IWDGRST)|| \
-                           ((FLAG) == RCC_FLAG_WWDGRST)  || ((FLAG) == RCC_FLAG_LPWRRST)|| \
-                           ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void        RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void        RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void        RCC_HSICmd(FunctionalState NewState);
-void        RCC_LSEConfig(uint8_t RCC_LSE);
-void        RCC_LSICmd(FunctionalState NewState);
-
-void        RCC_PLLCmd(FunctionalState NewState);
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
-#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-void        RCC_PLLI2SCmd(FunctionalState NewState);
-
-#if defined(STM32F40_41xxx) || defined(STM32F401xx)
-void        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
-#endif /* STM32F40_41xxx || STM32F401xx */
-#if defined(STM32F411xE)
-void        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
-#endif /* STM32F411xE */
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-void        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F446xx)
-void        RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
-#endif /* STM32F412xG || STM32F446xx */
-
-void        RCC_PLLSAICmd(FunctionalState NewState);
-#if defined(STM32F469_479xx)
-void        RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
-#endif /* STM32F469_479xx */
-#if defined(STM32F446xx)
-void        RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
-#endif /* STM32F446xx */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void        RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-void        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void        RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
-void        RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void        RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t     RCC_GetSYSCLKSource(void);
-void        RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void        RCC_PCLK1Config(uint32_t RCC_HCLK);
-void        RCC_PCLK2Config(uint32_t RCC_HCLK);
-void        RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void        RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void        RCC_RTCCLKCmd(FunctionalState NewState);
-void        RCC_BackupResetCmd(FunctionalState NewState);
-
-#if defined(STM32F412xG) || defined(STM32F446xx)  
-void        RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
-#if defined(STM32F446xx)
-void        RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
-#endif /* STM32F446xx */
-#endif /* STM32F412xG || STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-void        RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-void        RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
-void        RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-void        RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
-void        RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
-
-void        RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
-void        RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
-
-void        RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void        RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void        RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void        RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void        RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void        RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void        RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void        RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void        RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void        RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void        RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void        RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void        RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void        RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void        RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
-void        RCC_LSEModeConfig(uint8_t RCC_Mode);
-
-/* Features available only for STM32F469_479xx devices */
-#if defined(STM32F469_479xx)
-void        RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /*  STM32F469_479xx */
-
-/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
-#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
-void        RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
-void        RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-/* Features available only for STM32F446xx devices */
-#if defined(STM32F446xx)
-void        RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
-void        RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
-void        RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /* STM32F446xx */
-
-/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
-void        RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
-#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
-
-/* Features available only for STM32F410xx devices */
-#if defined(STM32F410xx)
-void        RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
-
-void        RCC_MCO1Cmd(FunctionalState NewState);
-void        RCC_MCO2Cmd(FunctionalState NewState);
-#endif /* STM32F410xx */
-
-#if defined(STM32F412xG)
-void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
-void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
-#endif /* STM32F412xG */
-/* Interrupts and flags management functions **********************************/
-void        RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus  RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void        RCC_ClearFlag(void);
-ITStatus    RCC_GetITStatus(uint8_t RCC_IT);
-void        RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_RCC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h

@@ -1,431 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_usart.h
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file contains all the functions prototypes for the USART 
-  *          firmware library.    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_USART_H
-#define __STM32F4xx_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** 
-  * @brief  USART Init Structure definition  
-  */ 
-  
-typedef struct
-{
-  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
-                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
-                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
-  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint16_t USART_Parity;              /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint16_t USART_Mode;                /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/** 
-  * @brief  USART Clock Init Structure definition  
-  */ 
-  
-typedef struct
-{
-
-  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
-                               This parameter can be a value of @ref USART_Clock */
-
-  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
-                               This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
-                               This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                               This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
-  * @{
-  */ 
-  
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                     ((PERIPH) == USART2) || \
-                                     ((PERIPH) == USART3) || \
-                                     ((PERIPH) == UART4)  || \
-                                     ((PERIPH) == UART5)  || \
-                                     ((PERIPH) == USART6) || \
-                                     ((PERIPH) == UART7)  || \
-                                     ((PERIPH) == UART8))
-
-#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                      ((PERIPH) == USART2) || \
-                                      ((PERIPH) == USART3) || \
-                                      ((PERIPH) == USART6))
-
-/** @defgroup USART_Word_Length 
-  * @{
-  */ 
-  
-#define USART_WordLength_8b                  ((uint16_t)0x0000)
-#define USART_WordLength_9b                  ((uint16_t)0x1000)
-                                    
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
-                                      ((LENGTH) == USART_WordLength_9b))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Stop_Bits 
-  * @{
-  */ 
-  
-#define USART_StopBits_1                     ((uint16_t)0x0000)
-#define USART_StopBits_0_5                   ((uint16_t)0x1000)
-#define USART_StopBits_2                     ((uint16_t)0x2000)
-#define USART_StopBits_1_5                   ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
-                                     ((STOPBITS) == USART_StopBits_0_5) || \
-                                     ((STOPBITS) == USART_StopBits_2) || \
-                                     ((STOPBITS) == USART_StopBits_1_5))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Parity 
-  * @{
-  */ 
-  
-#define USART_Parity_No                      ((uint16_t)0x0000)
-#define USART_Parity_Even                    ((uint16_t)0x0400)
-#define USART_Parity_Odd                     ((uint16_t)0x0600) 
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
-                                 ((PARITY) == USART_Parity_Even) || \
-                                 ((PARITY) == USART_Parity_Odd))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Mode 
-  * @{
-  */ 
-  
-#define USART_Mode_Rx                        ((uint16_t)0x0004)
-#define USART_Mode_Tx                        ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Hardware_Flow_Control 
-  * @{
-  */ 
-#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == USART_HardwareFlowControl_None) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock 
-  * @{
-  */ 
-#define USART_Clock_Disable                  ((uint16_t)0x0000)
-#define USART_Clock_Enable                   ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
-                               ((CLOCK) == USART_Clock_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Polarity 
-  * @{
-  */
-  
-#define USART_CPOL_Low                       ((uint16_t)0x0000)
-#define USART_CPOL_High                      ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Phase
-  * @{
-  */
-
-#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
-#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit
-  * @{
-  */
-
-#define USART_LastBit_Disable                ((uint16_t)0x0000)
-#define USART_LastBit_Enable                 ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
-                                   ((LASTBIT) == USART_LastBit_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Interrupt_definition 
-  * @{
-  */
-  
-#define USART_IT_PE                          ((uint16_t)0x0028)
-#define USART_IT_TXE                         ((uint16_t)0x0727)
-#define USART_IT_TC                          ((uint16_t)0x0626)
-#define USART_IT_RXNE                        ((uint16_t)0x0525)
-#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
-#define USART_IT_IDLE                        ((uint16_t)0x0424)
-#define USART_IT_LBD                         ((uint16_t)0x0846)
-#define USART_IT_CTS                         ((uint16_t)0x096A)
-#define USART_IT_ERR                         ((uint16_t)0x0060)
-#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
-#define USART_IT_NE                          ((uint16_t)0x0260)
-#define USART_IT_FE                          ((uint16_t)0x0160)
-
-/** @defgroup USART_Legacy 
-  * @{
-  */
-#define USART_IT_ORE                          USART_IT_ORE_ER               
-/**
-  * @}
-  */
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
-                             ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
-                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
-  * @}
-  */
-
-/** @defgroup USART_DMA_Requests 
-  * @{
-  */
-
-#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
-#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_WakeUp_methods
-  * @{
-  */
-
-#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
-                                 ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
-  * @}
-  */
-
-/** @defgroup USART_LIN_Break_Detection_Length 
-  * @{
-  */
-  
-#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
-                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
-                                ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
-  * @}
-  */
-
-/** @defgroup USART_IrDA_Low_Power 
-  * @{
-  */
-
-#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
-                                  ((MODE) == USART_IrDAMode_Normal))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Flags 
-  * @{
-  */
-
-#define USART_FLAG_CTS                       ((uint16_t)0x0200)
-#define USART_FLAG_LBD                       ((uint16_t)0x0100)
-#define USART_FLAG_TXE                       ((uint16_t)0x0080)
-#define USART_FLAG_TC                        ((uint16_t)0x0040)
-#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
-#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
-#define USART_FLAG_ORE                       ((uint16_t)0x0008)
-#define USART_FLAG_NE                        ((uint16_t)0x0004)
-#define USART_FLAG_FE                        ((uint16_t)0x0002)
-#define USART_FLAG_PE                        ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
-                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
-                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
-                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
-                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-                              
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the USART configuration to the default reset state ***/ 
-void USART_DeInit(USART_TypeDef* USARTx);
-
-/* Initialization and Configuration functions *********************************/
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/ 
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendBreak(USART_TypeDef* USARTx);
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_USART_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/misc.c

@@ -1,249 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.c
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file provides all the miscellaneous firmware functions (add-on
-  *          to CMSIS functions).
-  *          
-  *  @verbatim   
-  *                               
-  *          ===================================================================      
-  *                        How to configure Interrupts using driver 
-  *          ===================================================================      
-  * 
-  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
-  *            The Cortex-M4 exceptions are managed by CMSIS functions.
-  *
-  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
-  *                function according to the following table.
- 
-  *  The table below gives the allowed values of the pre-emption priority and subpriority according
-  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
-  *    ==========================================================================================================================
-  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-  *    ==========================================================================================================================
-  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
-  *                           |                                   |                             | 4 bits for subpriority
-  *    --------------------------------------------------------------------------------------------------------------------------
-  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
-  *                           |                                   |                             | 3 bits for subpriority
-  *    --------------------------------------------------------------------------------------------------------------------------    
-  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-  *                           |                                   |                             | 2 bits for subpriority
-  *    --------------------------------------------------------------------------------------------------------------------------    
-  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-  *                           |                                   |                             | 1 bits for subpriority
-  *    --------------------------------------------------------------------------------------------------------------------------    
-  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
-  *                           |                                   |                             | 0 bits for subpriority                       
-  *    ==========================================================================================================================     
-  *
-  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
-  *
-  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
-  *        The pending IRQ priority will be managed only by the subpriority.
-  *
-  * @note  IRQ priority order (sorted by highest to lowest priority):
-  *         - Lowest pre-emption priority
-  *         - Lowest subpriority
-  *         - Lowest hardware priority (IRQ number)
-  *
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup MISC 
-  * @brief MISC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
-  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
-  *                                4 bits for subpriority
-  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
-  *                                3 bits for subpriority
-  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
-  *                                2 bits for subpriority
-  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
-  *                                1 bits for subpriority
-  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
-  *                                0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
-  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
-  * @brief  Initializes the NVIC peripheral according to the specified
-  *         parameters in the NVIC_InitStruct.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
-  *         the configuration information for the specified NVIC peripheral.
-  * @retval None
-  */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
-  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
-  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-    
-  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
-  {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/    
-    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
-    tmppre = (0x4 - tmppriority);
-    tmpsub = tmpsub >> tmppriority;
-
-    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
-    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
-        
-    tmppriority = tmppriority << 0x04;
-        
-    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-    
-    /* Enable the Selected IRQ Channels --------------------------------------*/
-    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-  else
-  {
-    /* Disable the Selected IRQ Channels -------------------------------------*/
-    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-}
-
-/**
-  * @brief  Sets the vector table location and Offset.
-  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
-  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
-  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
-  * @retval None
-  */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{ 
-  /* Check the parameters */
-  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
-  assert_param(IS_NVIC_OFFSET(Offset));  
-   
-  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
-  * @brief  Selects the condition for the system to enter low power mode.
-  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
-  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
-  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
-  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_LP(LowPowerMode));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if (NewState != DISABLE)
-  {
-    SCB->SCR |= LowPowerMode;
-  }
-  else
-  {
-    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
-  }
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  SysTick_CLKSource: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
-  {
-    SysTick->CTRL |= SysTick_CLKSource_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c

@@ -1,714 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dac.c
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-   * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
-  *           + DAC channels configuration: trigger, output buffer, data format
-  *           + DMA management      
-  *           + Interrupts and flags management
-  *
- @verbatim      
- ===============================================================================
-                      ##### DAC Peripheral features #####
- ===============================================================================
-    [..]        
-      *** DAC Channels ***
-      ====================  
-    [..]  
-    The device integrates two 12-bit Digital Analog Converters that can 
-    be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output
-  
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
-    using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
-    [..] 
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
-          The used pin (GPIOx_Pin9) must be configured in input mode.
-  
-      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
-          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
-          The timer TRGO event should be selected using TIM_SelectOutputTrigger()
-  
-      (#) Software using DAC_Trigger_Software
-  
-      *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use  
-      DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-      [..]           
-      (@) Refer to the device datasheet for more details about output 
-          impedance value with and without output buffer.
-            
-       *** DAC wave generation feature ***
-       =================================== 
-       [..]     
-       Both DAC channels can be used to generate
-         (#) Noise wave using DAC_WaveGeneration_Noise
-         (#) Triangle wave using DAC_WaveGeneration_Triangle
-          
-          -@-  Wave generation can be disabled using DAC_WaveGeneration_None
-  
-       *** DAC data format ***
-       =======================
-       [..]   
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_Align_8b_R
-         (#) 12-bit left alignment using DAC_Align_12b_L
-         (#) 12-bit right alignment using DAC_Align_12b_R
-  
-       *** DAC data value to voltage correspondence ***  
-       ================================================ 
-       [..] 
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
-       DAC_OUTx = VREF+ * DOR / 4095
-       with  DOR is the Data Output Register
-          VEF+ is the input voltage reference (refer to the device datasheet)
-        e.g. To set DAC_OUT1 to 0.7V, use
-          DAC_SetChannel1Data(DAC_Align_12b_R, 868);
-          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-       *** DMA requests  ***
-       =====================
-       [..]    
-       A DMA1 request can be generated when an external trigger (but not
-       a software trigger) occurs if DMA1 requests are enabled using
-       DAC_DMACmd()
-       [..]
-       DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
-             already configured
-         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
-             already configured
-  
-      
-                      ##### How to use this driver #####
- ===============================================================================
-    [..]          
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using
-          RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using DAC_Init() function
-      (+) Enable the DAC channel using DAC_Cmd() function
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DAC 
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CR register Mask */
-#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
-#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
-#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
-
-/* DOR register offset */
-#define DOR_OFFSET                 ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
-  * @{
-  */
-
-/** @defgroup DAC_Group1 DAC channels configuration
- *  @brief   DAC channels configuration: trigger, output buffer, data format 
- *
-@verbatim   
- ===============================================================================
-   ##### DAC channels configuration: trigger, output buffer, data format #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void DAC_DeInit(void)
-{
-  /* Enable DAC reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
-  /* Release DAC from reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
-  * @brief  Initializes the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
-  *         the configuration information for the  specified DAC channel.
-  * @retval None
-  */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
-  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
-  /* Get the DAC CR value */
-  tmpreg1 = DAC->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
-  /* Configure for the selected DAC channel: buffer output, trigger, 
-     wave generation, mask/amplitude for wave generation */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set WAVEx bits according to DAC_WaveGeneration value */
-  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
-  /* Set BOFFx bit according to DAC_OutputBuffer value */   
-  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
-             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
-             DAC_InitStruct->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << DAC_Channel;
-  /* Write to DAC CR */
-  DAC->CR = tmpreg1;
-}
-
-/**
-  * @brief  Fills each DAC_InitStruct member with its default value.
-  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
-  /* Initialize the DAC_Trigger member */
-  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
-  /* Initialize the DAC_WaveGeneration member */
-  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
-  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
-  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
-  /* Initialize the DAC_OutputBuffer member */
-  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
-  * @brief  Enables or disables the specified DAC channel.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  NewState: new state of the DAC channel. 
-  *          This parameter can be: ENABLE or DISABLE.
-  * @note   When the DAC channel is enabled the trigger source can no more be modified.
-  * @retval None
-  */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC channel */
-    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC channel */
-    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
-  }
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel software trigger.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  NewState: new state of the selected DAC channel software trigger.
-  *          This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable software trigger for the selected DAC channel */
-    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
-  }
-  else
-  {
-    /* Disable software trigger for the selected DAC channel */
-    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
-  }
-}
-
-/**
-  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
-  * @param  NewState: new state of the DAC channels software triggers.
-  *          This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable software trigger for both DAC channels */
-    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
-  }
-  else
-  {
-    /* Disable software trigger for both DAC channels */
-    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
-  }
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_Wave: specifies the wave type to enable or disable.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Wave_Noise: noise wave generation
-  *            @arg DAC_Wave_Triangle: triangle wave generation
-  * @param  NewState: new state of the selected DAC channel wave generation.
-  *          This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_WAVE(DAC_Wave)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected wave generation for the selected DAC channel */
-    DAC->CR |= DAC_Wave << DAC_Channel;
-  }
-  else
-  {
-    /* Disable the selected wave generation for the selected DAC channel */
-    DAC->CR &= ~(DAC_Wave << DAC_Channel);
-  }
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel1.
-  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
-  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
-  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval None
-  */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{  
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(DAC_Align));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)DAC_BASE; 
-  tmp += DHR12R1_OFFSET + DAC_Align;
-
-  /* Set the DAC channel1 selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel2.
-  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
-  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
-  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval None
-  */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(DAC_Align));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)DAC_BASE;
-  tmp += DHR12R2_OFFSET + DAC_Align;
-
-  /* Set the DAC channel2 selected data holding register */
-  *(__IO uint32_t *)tmp = Data;
-}
-
-/**
-  * @brief  Set the specified data holding register value for dual channel DAC.
-  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
-  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
-  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
-  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval None
-  */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
-  uint32_t data = 0, tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(DAC_Align));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-  
-  /* Calculate and set dual DAC data holding register value */
-  if (DAC_Align == DAC_Align_8b_R)
-  {
-    data = ((uint32_t)Data2 << 8) | Data1; 
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16) | Data1;
-  }
-  
-  tmp = (uint32_t)DAC_BASE;
-  tmp += DHR12RD_OFFSET + DAC_Align;
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  
-  tmp = (uint32_t) DAC_BASE ;
-  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-  
-  /* Returns the DAC channel data output register value */
-  return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Group2 DMA management functions
- *  @brief   DMA management functions
- *
-@verbatim   
- ===============================================================================
-                       ##### DMA management functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified DAC channel DMA request.
-  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
-  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  NewState: new state of the selected DAC channel DMA request.
-  *          This parameter can be: ENABLE or DISABLE.
-  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
-  *          already configured.
-  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
-  *          already configured.    
-  * @retval None
-  */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC channel DMA request */
-    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC channel DMA request */
-    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
-  }
-}
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions
- *
-@verbatim   
- ===============================================================================
-             ##### Interrupts and flags management functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified DAC interrupts.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
-  *          This parameter can be the following values:
-  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
-  * @note   The DMA underrun occurs when a second external trigger arrives before the 
-  *         acknowledgement for the first external trigger is received (first request).
-  * @param  NewState: new state of the specified DAC interrupts.
-  *          This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */ 
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_DAC_IT(DAC_IT)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC interrupts */
-    DAC->CR |=  (DAC_IT << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC interrupts */
-    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
-  }
-}
-
-/**
-  * @brief  Checks whether the specified DAC flag is set or not.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_FLAG: specifies the flag to check. 
-  *          This parameter can be only of the following value:
-  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
-  * @note   The DMA underrun occurs when a second external trigger arrives before the 
-  *         acknowledgement for the first external trigger is received (first request).
-  * @retval The new state of DAC_FLAG (SET or RESET).
-  */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_FLAG(DAC_FLAG));
-
-  /* Check the status of the specified DAC flag */
-  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
-  {
-    /* DAC_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DAC_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DAC_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DAC channel's pending flags.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_FLAG: specifies the flag to clear. 
-  *          This parameter can be of the following value:
-  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
-  * @note   The DMA underrun occurs when a second external trigger arrives before the 
-  *         acknowledgement for the first external trigger is received (first request).                           
-  * @retval None
-  */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_FLAG(DAC_FLAG));
-
-  /* Clear the selected DAC flags */
-  DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
-  * @brief  Checks whether the specified DAC interrupt has occurred or not.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_IT: specifies the DAC interrupt source to check. 
-  *          This parameter can be the following values:
-  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
-  * @note   The DMA underrun occurs when a second external trigger arrives before the 
-  *         acknowledgement for the first external trigger is received (first request).
-  * @retval The new state of DAC_IT (SET or RESET).
-  */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_IT(DAC_IT));
-
-  /* Get the DAC_IT enable bit status */
-  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-  
-  /* Check the status of the specified DAC interrupt */
-  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
-  {
-    /* DAC_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DAC_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DAC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DAC channel's interrupt pending bits.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_Channel_1: DAC Channel1 selected
-  *            @arg DAC_Channel_2: DAC Channel2 selected
-  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
-  *          This parameter can be the following values:
-  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
-  * @note   The DMA underrun occurs when a second external trigger arrives before the 
-  *         acknowledgement for the first external trigger is received (first request).                           
-  * @retval None
-  */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_IT(DAC_IT)); 
-
-  /* Clear the selected DAC interrupt pending bits */
-  DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c

@@ -1,611 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_gpio.c
-  * @author  MCD Application Team
-  * @version V1.7.1
-  * @date    20-May-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the GPIO peripheral:           
-  *           + Initialization and Configuration
-  *           + GPIO Read and Write
-  *           + GPIO Alternate functions configuration
-  * 
-@verbatim  
- ===============================================================================
-                      ##### How to use this driver #####
- ===============================================================================       
- [..]             
-   (#) Enable the GPIO AHB clock using the following function
-       RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-               
-   (#) Configure the GPIO pin(s) using GPIO_Init()
-       Four possible configuration are available for each pin:
-       (++) Input: Floating, Pull-up, Pull-down.
-       (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
-            Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed 
-            is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
-       (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open 
-            Drain (Pull-up, Pull-down or no Pull).
-       (++) Analog: required mode when a pin is to be used as ADC channel or DAC 
-            output.
-   
-   (#) Peripherals alternate function:
-       (++) For ADC and DAC, configure the desired pin in analog mode using 
-            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
-            (+++) For other peripherals (TIM, USART...):
-            (+++) Connect the pin to the desired peripherals' Alternate 
-                     Function (AF) using GPIO_PinAFConfig() function
-            (+++) Configure the desired pin in alternate function mode using
-                     GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
-            (+++) Select the type, pull-up/pull-down and output speed via 
-                     GPIO_PuPd, GPIO_OType and GPIO_Speed members
-            (+++) Call GPIO_Init() function
-          
-   (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
-            
-   (#) To set/reset the level of a pin configured in output mode use 
-       GPIO_SetBits()/GPIO_ResetBits()
-                 
-   (#) During and just after reset, the alternate functions are not 
-       active and the GPIO pins are configured in input floating mode (except JTAG
-       pins).
-  
-   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
-       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
-       priority over the GPIO function.
-  
-   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
-       general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
-       The HSE has priority over the GPIO function.
-               
-@endverbatim        
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup GPIO 
-  * @brief GPIO driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
-  * @{
-  */ 
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- *  @brief   Initialization and Configuration
- *
-@verbatim   
- ===============================================================================
-                 ##### Initialization and Configuration #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @note   By default, The GPIO pins are configured in input floating mode (except JTAG pins).
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.  
-  * @retval None
-  */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  if (GPIOx == GPIOA)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
-  }
-  else if (GPIOx == GPIOD)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
-  }
-  else if (GPIOx == GPIOE)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
-  }
-  else if (GPIOx == GPIOF)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
-  }
-  else if (GPIOx == GPIOG)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
-  }
-  else if (GPIOx == GPIOH)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
-  }
-
-  else if (GPIOx == GPIOI)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
-  }
-  else if (GPIOx == GPIOJ)
-  {
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
-    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
-  }
-  else
-  {
-    if (GPIOx == GPIOK)
-    {
-      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
-      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.   
-  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
-  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
-  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
-  /* ------------------------- Configure the port pins ---------------- */
-  /*-- GPIO Mode Configuration --*/
-  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
-  {
-    pos = ((uint32_t)0x01) << pinpos;
-    /* Get the port pins position */
-    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
-    if (currentpin == pos)
-    {
-      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
-      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
-      {
-        /* Check Speed mode parameters */
-        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
-        /* Speed mode configuration */
-        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
-        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
-        /* Check Output mode parameters */
-        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
-        /* Output mode configuration*/
-        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
-        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
-      }
-
-      /* Pull-up Pull down resistor configuration*/
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
-      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
-    }
-  }
-}
-
-/**
-  * @brief  Fills each GPIO_InitStruct member with its default value.
-  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
-  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
-  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bit to be locked.
-  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = 0x00010000;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  tmp |= GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKK bit */
-  GPIOx->LCKR =  GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- *  @brief   GPIO Read and Write
- *
-@verbatim   
- ===============================================================================
-                         ##### GPIO Read and Write #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO input data port.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @retval GPIO input data port value.
-  */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  return ((uint16_t)GPIOx->IDR);
-}
-
-/**
-  * @brief  Reads the specified output data port bit.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *          This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The output port pin value.
-  */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
-  if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO output data port.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @retval GPIO output data port value.
-  */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  return ((uint16_t)GPIOx->ODR);
-}
-
-/**
-  * @brief  Sets the selected data port bits.
-  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
-  * @brief  Clears the selected data port bits.
-  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_Pin_x where x can be (0..15).
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *          This parameter can be one of the BitAction enum values:
-  *            @arg Bit_RESET: to clear the port pin
-  *            @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
-  if (BitVal != Bit_RESET)
-  {
-    GPIOx->BSRRL = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRRH = GPIO_Pin ;
-  }
-}
-
-/**
-  * @brief  Writes data to the specified GPIO data port.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  PortVal: specifies the value to be written to the port output data register.
-  * @retval None
-  */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  GPIOx->ODR = PortVal;
-}
-
-/**
-  * @brief  Toggles the specified GPIO pins..
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_Pin: Specifies the pins to be toggled.
-  * @retval None
-  */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- *  @brief   GPIO Alternate functions configuration function
- *
-@verbatim   
- ===============================================================================
-           ##### GPIO Alternate functions configuration function #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Changes the mapping of the specified pin.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
-  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
-  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
-  *         This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @param  GPIO_AFSelection: selects the pin to used as Alternate function.
-  *          This parameter can be one of the following values:
-  *            @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) 
-  *            @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) 
-  *            @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) 
-  *            @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) 
-  *            @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
-  *            @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
-  *            @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
-  *            @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
-  *            @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
-  *            @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
-  *            @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
-  *            @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
-  *            @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
-  *            @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
-  *            @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
-  *            @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
-  *            @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
-  *            @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
-  *            @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
-  *            @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 
-  *            @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 
-  *            @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
-  *            @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.       
-  *            @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
-  *            @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
-  *            @arg GPIO_AF_USART1: Connect USART1 pins to AF7
-  *            @arg GPIO_AF_USART2: Connect USART2 pins to AF7
-  *            @arg GPIO_AF_USART3: Connect USART3 pins to AF7
-  *            @arg GPIO_AF_UART4: Connect UART4 pins to AF8
-  *            @arg GPIO_AF_UART5: Connect UART5 pins to AF8
-  *            @arg GPIO_AF_USART6: Connect USART6 pins to AF8
-  *            @arg GPIO_AF_UART7: Connect UART7 pins to AF8
-  *            @arg GPIO_AF_UART8: Connect UART8 pins to AF8
-  *            @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
-  *            @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
-  *            @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
-  *            @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
-  *            @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
-  *            @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
-  *            @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
-  *            @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
-  *            @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 
-  *            @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.   
-  *            @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
-  *            @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
-  *            @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
-  *            @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. 
-  *            @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
-  * @retval None
-  */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
-  uint32_t temp = 0x00;
-  uint32_t temp_2 = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-  assert_param(IS_GPIO_AF(GPIO_AF));
-  
-  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
-  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
-  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
-  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F7XX_Lib/CMSIS/Include/arm_common_tables.h

@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. October 2015
-* $Revision: 	V.1.4.5 a
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
-*
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-/* extern const q31_t realCoefAQ31[1024]; */
-/* extern const q31_t realCoefBQ31[1024]; */
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */

STM32F7XX_Lib/CMSIS/Include/arm_const_structs.h

@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
-*
-* Description:	This file has constant structs that are initialized for
-*              user convenience.  For example, some can be given as
-*              arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif

STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h

@@ -1,734 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS Cortex-M Core Function/Instruction Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
-
-
-#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    value  Value to rotate
-  \param [in]    value  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#endif /* (__CORTEX_M >= 0x04) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */

STM32F7XX_Lib/CMSIS/Include/core_cm0.h

@@ -1,798 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h

@@ -1,914 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h

@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */

STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h

@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h

@@ -1,96 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */

STM32F7XX_Lib/CMSIS/Include/core_sc000.h

@@ -1,926 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC000_REV
-    #define __SC000_REV             0x0000U
-    #warning "__SC000_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-        uint32_t RESERVED1[154U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of SC000 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

STM32F7XX_Lib/Device/startup/startup_stm32f7xx.c

@@ -1,519 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f4xx.s
-  * @author    Coocox
-  * @version   V1.0
-  * @date      03/05/2012
-  * @brief     STM32F4xx Devices vector table for RIDE7 toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM324xG-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  */
-  
-/* Some modifications by Andy Uribe CA6JAU :
-- Added C++ global constructors support
-- Changed initial stack pointer
-- Changed support for STM32F767
-*/
-
-/*----------Macro definition--------------------------------------------------*/
-#define WEAK __attribute__ ((weak))
-
-/*----------Declaration of the default fault handlers-------------------------*/
-/* System exception vector handler */
-__attribute__ ((used))
-void WEAK  Reset_Handler(void);
-
-void WEAK  NMI_Handler(void);
-void WEAK  HardFault_Handler(void);
-void WEAK  MemManage_Handler(void);
-void WEAK  BusFault_Handler(void);
-void WEAK  UsageFault_Handler(void);
-void WEAK  SVC_Handler(void);
-void WEAK  DebugMon_Handler(void);
-void WEAK  PendSV_Handler(void);
-void WEAK  SysTick_Handler(void);
-  
-  /* External Interrupts */
-void WEAK  WWDG_IRQHandler(void);                   /* Window WatchDog              */
-void WEAK  PVD_IRQHandler(void);                    /* PVD through EXTI Line detection */
-void WEAK  TAMP_STAMP_IRQHandler(void);             /* Tamper and TimeStamps through the EXTI line */
-void WEAK  RTC_WKUP_IRQHandler(void);               /* RTC Wakeup through the EXTI line */
-void WEAK  FLASH_IRQHandler(void);                  /* FLASH                        */
-void WEAK  RCC_IRQHandler(void);                    /* RCC                          */
-void WEAK  EXTI0_IRQHandler(void);                  /* EXTI Line0                   */
-void WEAK  EXTI1_IRQHandler(void);                  /* EXTI Line1                   */
-void WEAK  EXTI2_IRQHandler(void);                  /* EXTI Line2                   */
-void WEAK  EXTI3_IRQHandler(void);                  /* EXTI Line3                   */
-void WEAK  EXTI4_IRQHandler(void);                  /* EXTI Line4                   */
-void WEAK  DMA1_Stream0_IRQHandler(void);           /* DMA1 Stream 0                */
-void WEAK  DMA1_Stream1_IRQHandler(void);           /* DMA1 Stream 1                */
-void WEAK  DMA1_Stream2_IRQHandler(void);           /* DMA1 Stream 2                */
-void WEAK  DMA1_Stream3_IRQHandler(void);           /* DMA1 Stream 3                */
-void WEAK  DMA1_Stream4_IRQHandler(void);           /* DMA1 Stream 4                */
-void WEAK  DMA1_Stream5_IRQHandler(void);           /* DMA1 Stream 5                */
-void WEAK  DMA1_Stream6_IRQHandler(void);           /* DMA1 Stream 6                */
-void WEAK  ADC_IRQHandler(void);                    /* ADC1, ADC2 and ADC3s         */
-void WEAK  CAN1_TX_IRQHandler(void);                /* CAN1 TX                      */
-void WEAK  CAN1_RX0_IRQHandler(void);               /* CAN1 RX0                     */
-void WEAK  CAN1_RX1_IRQHandler(void);               /* CAN1 RX1                     */
-void WEAK  CAN1_SCE_IRQHandler(void);               /* CAN1 SCE                     */
-void WEAK  EXTI9_5_IRQHandler(void);                /* External Line[9:5]s          */
-void WEAK  TIM1_BRK_TIM9_IRQHandler(void);          /* TIM1 Break and TIM9          */
-void WEAK  TIM1_UP_TIM10_IRQHandler(void);          /* TIM1 Update and TIM10        */
-void WEAK  TIM1_TRG_COM_TIM11_IRQHandler(void);     /* TIM1 Trigger and Commutation and TIM11 */
-void WEAK  TIM1_CC_IRQHandler(void);                /* TIM1 Capture Compare         */
-void WEAK  TIM2_IRQHandler(void);                   /* TIM2                         */
-void WEAK  TIM3_IRQHandler(void);                   /* TIM3                         */
-void WEAK  TIM4_IRQHandler(void);                   /* TIM4                         */
-void WEAK  I2C1_EV_IRQHandler(void);                /* I2C1 Event                   */
-void WEAK  I2C1_ER_IRQHandler(void);                /* I2C1 Error                   */
-void WEAK  I2C2_EV_IRQHandler(void);                /* I2C2 Event                   */
-void WEAK  I2C2_ER_IRQHandler(void);                /* I2C2 Error                   */
-void WEAK  SPI1_IRQHandler(void);                   /* SPI1                         */
-void WEAK  SPI2_IRQHandler(void);                   /* SPI2                         */
-void WEAK  USART1_IRQHandler(void);                 /* USART1                       */
-void WEAK  USART2_IRQHandler(void);                 /* USART2                       */
-void WEAK  USART3_IRQHandler(void);                 /* USART3                       */
-void WEAK  EXTI15_10_IRQHandler(void);              /* External Line[15:10]s        */
-void WEAK  RTC_Alarm_IRQHandler(void);              /* RTC Alarm (A and B) through EXTI Line */
-void WEAK  OTG_FS_WKUP_IRQHandler(void);            /* USB OTG FS Wakeup through EXTI line */
-void WEAK  TIM8_BRK_TIM12_IRQHandler(void);         /* TIM8 Break and TIM12         */
-void WEAK  TIM8_UP_TIM13_IRQHandler(void);          /* TIM8 Update and TIM13        */
-void WEAK  TIM8_TRG_COM_TIM14_IRQHandler(void);     /* TIM8 Trigger and Commutation and TIM14 */
-void WEAK  TIM8_CC_IRQHandler(void);                /* TIM8 Capture Compare         */
-void WEAK  DMA1_Stream7_IRQHandler(void);           /* DMA1 Stream7                 */
-void WEAK  FMC_IRQHandler(void);                    /* FMC                          */
-void WEAK  SDMMC1_IRQHandler(void);                 /* SDMMC1                       */
-void WEAK  TIM5_IRQHandler(void);                   /* TIM5                         */
-void WEAK  SPI3_IRQHandler(void);                   /* SPI3                         */
-void WEAK  UART4_IRQHandler(void);                  /* UART4                        */
-void WEAK  UART5_IRQHandler(void);                  /* UART5                        */
-void WEAK  TIM6_DAC_IRQHandler(void);               /* TIM6 and DAC1&2 underrun errors */
-void WEAK  TIM7_IRQHandler(void);                   /* TIM7                         */
-void WEAK  DMA2_Stream0_IRQHandler(void);           /* DMA2 Stream 0                */
-void WEAK  DMA2_Stream1_IRQHandler(void);           /* DMA2 Stream 1                */
-void WEAK  DMA2_Stream2_IRQHandler(void);           /* DMA2 Stream 2                */
-void WEAK  DMA2_Stream3_IRQHandler(void);           /* DMA2 Stream 3                */
-void WEAK  DMA2_Stream4_IRQHandler(void);           /* DMA2 Stream 4                */
-void WEAK  ETH_IRQHandler(void);                    /* Ethernet                     */
-void WEAK  ETH_WKUP_IRQHandler(void);               /* Ethernet Wakeup through EXTI line */
-void WEAK  CAN2_TX_IRQHandler(void);                /* CAN2 TX                      */
-void WEAK  CAN2_RX0_IRQHandler(void);               /* CAN2 RX0                     */
-void WEAK  CAN2_RX1_IRQHandler(void);               /* CAN2 RX1                     */
-void WEAK  CAN2_SCE_IRQHandler(void);               /* CAN2 SCE                     */
-void WEAK  OTG_FS_IRQHandler(void);                 /* USB OTG FS                   */
-void WEAK  DMA2_Stream5_IRQHandler(void);           /* DMA2 Stream 5                */
-void WEAK  DMA2_Stream6_IRQHandler(void);           /* DMA2 Stream 6                */
-void WEAK  DMA2_Stream7_IRQHandler(void);           /* DMA2 Stream 7                */
-void WEAK  USART6_IRQHandler(void);                 /* USART6                       */
-void WEAK  I2C3_EV_IRQHandler(void);                /* I2C3 event                   */
-void WEAK  I2C3_ER_IRQHandler(void);                /* I2C3 error                   */
-void WEAK  OTG_HS_EP1_OUT_IRQHandler(void);         /* USB OTG HS End Point 1 Out   */
-void WEAK  OTG_HS_EP1_IN_IRQHandler(void);          /* USB OTG HS End Point 1 In    */
-void WEAK  OTG_HS_WKUP_IRQHandler(void);            /* USB OTG HS Wakeup through EXTI */
-void WEAK  OTG_HS_IRQHandler(void);                 /* USB OTG HS                   */
-void WEAK  DCMI_IRQHandler(void);                   /* DCMI                         */
-void WEAK  RNG_IRQHandler(void);                    /* RNG                          */
-void WEAK  FPU_IRQHandler(void);                    /* FPU                          */
-void WEAK  UART7_IRQHandler(void);                  /* UART7                        */
-void WEAK  UART8_IRQHandler(void);                  /* UART8                        */
-void WEAK  SPI4_IRQHandler(void);                   /* SPI4                         */
-void WEAK  SPI5_IRQHandler(void);                   /* SPI5                         */
-void WEAK  SPI6_IRQHandler(void);                   /* SPI6                         */
-void WEAK  SAI1_IRQHandler(void);                   /* SAI1                         */
-void WEAK  LTDC_IRQHandler(void);                   /* LTDC                         */
-void WEAK  LTDC_ER_IRQHandler(void);                /* LTDC error                   */
-void WEAK  DMA2D_IRQHandler(void);                  /* DMA2D                        */
-void WEAK  SAI2_IRQHandler(void);                   /* SAI2                         */
-void WEAK  QUADSPI_IRQHandler(void);                /* QUADSPI                      */
-void WEAK  LPTIM1_IRQHandler(void);                 /* LPTIM1                       */
-void WEAK  CEC_IRQHandler(void);                    /* HDMI_CEC                     */
-void WEAK  I2C4_EV_IRQHandler(void);                /* I2C4 Event                   */
-void WEAK  I2C4_ER_IRQHandler(void);                /* I2C4 Error                   */
-void WEAK  SPDIF_RX_IRQHandler(void);               /* SPDIF_RX                     */
-void WEAK  DFSDM1_FLT0_IRQHandler(void);            /* DFSDM1 Filter 0 global Interrupt */
-void WEAK  DFSDM1_FLT1_IRQHandler(void);            /* DFSDM1 Filter 1 global Interrupt */
-void WEAK  DFSDM1_FLT2_IRQHandler(void);            /* DFSDM1 Filter 2 global Interrupt */
-void WEAK  DFSDM1_FLT3_IRQHandler(void);            /* DFSDM1 Filter 3 global Interrupt */
-void WEAK  SDMMC2_IRQHandler(void);                 /* SDMMC2                       */
-void WEAK  CAN3_TX_IRQHandler(void);                /* CAN3 TX                      */
-void WEAK  CAN3_RX0_IRQHandler(void);               /* CAN3 RX0                     */
-void WEAK  CAN3_RX1_IRQHandler(void);               /* CAN3 RX1                     */
-void WEAK  CAN3_SCE_IRQHandler(void);               /* CAN3 SCE                     */
-void WEAK  JPEG_IRQHandler(void);                   /* JPEG                         */
-void WEAK  MDIOS_IRQHandler(void);                  /* MDIOS                        */
-  
-/*----------Symbols defined in linker script----------------------------------*/
-extern unsigned long _estack;    /*!< The initial stack pointer               */
-extern unsigned long _sidata;    /*!< Start address for the initialization
-                                      values of the .data section.            */
-extern unsigned long _sdata;     /*!< Start address for the .data section     */
-extern unsigned long _edata;     /*!< End address for the .data section       */
-extern unsigned long _sbss;      /*!< Start address for the .bss section      */
-extern unsigned long _ebss;      /*!< End address for the .bss section        */
-
-/* C++ global constructors support */
-extern unsigned long __preinit_array_start;
-extern unsigned long __preinit_array_end;
-extern unsigned long __init_array_start;
-extern unsigned long __init_array_end;
-
-/*----------Function prototypes-----------------------------------------------*/
-extern int main(void);           /*!< The entry point for the application.    */
-//extern void SystemInit(void);    /*!< Setup the microcontroller system(CMSIS) */
-void Default_Reset_Handler(void);   /*!< Default reset handler                */
-static void Default_Handler(void);  /*!< Default exception handler            */
-static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline));
-
-/**
-  *@brief The minimal vector table for a Cortex M3.  Note that the proper constructs
-  *       must be placed on this to ensure that it ends up at physical address
-  *       0x00000000.
-  */
-__attribute__ ((used,section(".isr_vector")))
-void (* const g_pfnVectors[])(void) =
-{
-  /*----------Core Exceptions------------------------------------------------ */
-  (void *) &_estack,         /*!< The initial stack pointer                   */
-  Reset_Handler,             /*!< Reset Handler                               */
-  NMI_Handler,               /*!< NMI Handler                                 */
-  HardFault_Handler,         /*!< Hard Fault Handler                          */
-  MemManage_Handler,         /*!< MPU Fault Handler                           */
-  BusFault_Handler,          /*!< Bus Fault Handler                           */
-  UsageFault_Handler,        /*!< Usage Fault Handler                         */
-  0,0,0,0,                   /*!< Reserved                                    */
-  SVC_Handler,               /*!< SVCall Handler                              */
-  DebugMon_Handler,          /*!< Debug Monitor Handler                       */
-  0,                         /*!< Reserved                                    */
-  PendSV_Handler,            /*!< PendSV Handler                              */
-  SysTick_Handler,           /*!< SysTick Handler                             */
-  
-  /*----------External Exceptions---------------------------------------------*/
-  WWDG_IRQHandler,           /*!<  0: Window WatchDog                         */
-  PVD_IRQHandler,            /*!<  1: PVD through EXTI Line detection         */
-  TAMP_STAMP_IRQHandler,     /*!<  2: Tamper and TimeStamps through the EXTI line*/
-  RTC_WKUP_IRQHandler,       /*!<  3: RTC Wakeup through the EXTI line        */
-  FLASH_IRQHandler,          /*!<  4: FLASH                                   */
-  RCC_IRQHandler  ,          /*!<  5: RCC                                     */
-  EXTI0_IRQHandler,          /*!<  6: EXTI Line0                              */
-  EXTI1_IRQHandler,          /*!<  7: EXTI Line1                              */
-  EXTI2_IRQHandler,          /*!<  8: EXTI Line2                              */
-  EXTI3_IRQHandler,          /*!<  9: EXTI Line3                              */
-  EXTI4_IRQHandler,          /*!< 10: EXTI Line4                              */
-  DMA1_Stream0_IRQHandler,   /*!< 11: DMA1 Stream 0                           */
-  DMA1_Stream1_IRQHandler,   /*!< 12: DMA1 Stream 1                           */
-  DMA1_Stream2_IRQHandler,   /*!< 13: DMA1 Stream 2                           */
-  DMA1_Stream3_IRQHandler,   /*!< 14: DMA1 Stream 3                           */
-  DMA1_Stream4_IRQHandler,   /*!< 15: DMA1 Stream 4                           */
-  DMA1_Stream5_IRQHandler,   /*!< 16: DMA1 Stream 5                           */
-  DMA1_Stream6_IRQHandler,   /*!< 17: DMA1 Stream 6                           */
-  ADC_IRQHandler,            /*!< 18: ADC1, ADC2 and ADC3s                    */
-  CAN1_TX_IRQHandler,        /*!< 19: CAN1 TX                                 */
-  CAN1_RX0_IRQHandler,       /*!< 20: CAN1 RX0                                */
-  CAN1_RX1_IRQHandler,       /*!< 21: CAN1 RX1                                */
-  CAN1_SCE_IRQHandler,       /*!< 22: CAN1 SCE                                */
-  EXTI9_5_IRQHandler,        /*!< 23: External Line[9:5]s                     */
-  TIM1_BRK_TIM9_IRQHandler,  /*!< 24: TIM1 Break and TIM9                     */
-  TIM1_UP_TIM10_IRQHandler,  /*!< 25: TIM1 Update and TIM10                   */
-  TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/
-  TIM1_CC_IRQHandler,        /*!< 27: TIM1 Capture Compare                    */
-  TIM2_IRQHandler,           /*!< 28: TIM2                                    */
-  TIM3_IRQHandler,           /*!< 29: TIM3                                    */
-  TIM4_IRQHandler,           /*!< 30: TIM4                                    */
-  I2C1_EV_IRQHandler,        /*!< 31: I2C1 Event                              */
-  I2C1_ER_IRQHandler,        /*!< 32: I2C1 Error                              */
-  I2C2_EV_IRQHandler,        /*!< 33: I2C2 Event                              */
-  I2C2_ER_IRQHandler,        /*!< 34: I2C2 Error                              */
-  SPI1_IRQHandler,           /*!< 35: SPI1                                    */
-  SPI2_IRQHandler,           /*!< 36: SPI2                                    */
-  USART1_IRQHandler,         /*!< 37: USART1                                  */
-  USART2_IRQHandler,         /*!< 38: USART2                                  */
-  USART3_IRQHandler,         /*!< 39: USART3                                  */
-  EXTI15_10_IRQHandler,      /*!< 40: External Line[15:10]s                   */
-  RTC_Alarm_IRQHandler,      /*!< 41: RTC Alarm (A and B) through EXTI Line   */
-  OTG_FS_WKUP_IRQHandler,    /*!< 42: USB OTG FS Wakeup through EXTI line     */
-  TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12                    */
-  TIM8_UP_TIM13_IRQHandler,  /*!< 44: TIM8 Update and TIM13                   */
-  TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/
-  TIM8_CC_IRQHandler,        /*!< 46: TIM8 Capture Compare                    */
-  DMA1_Stream7_IRQHandler,   /*!< 47: DMA1 Stream7                            */
-  FMC_IRQHandler,            /*!< 48: FSMC                                    */
-  SDMMC1_IRQHandler,         /*!< 49: SDIO                                    */
-  TIM5_IRQHandler,           /*!< 50: TIM5                                    */
-  SPI3_IRQHandler,           /*!< 51: SPI3                                    */
-  UART4_IRQHandler,          /*!< 52: UART4                                   */
-  UART5_IRQHandler,          /*!< 53: UART5                                   */
-  TIM6_DAC_IRQHandler,       /*!< 54: TIM6 and DAC1&2 underrun errors         */
-  TIM7_IRQHandler,           /*!< 55: TIM7                                    */
-  DMA2_Stream0_IRQHandler,   /*!< 56: DMA2 Stream 0                           */
-  DMA2_Stream1_IRQHandler,   /*!< 57: DMA2 Stream 1                           */
-  DMA2_Stream2_IRQHandler,   /*!< 58: DMA2 Stream 2                           */
-  DMA2_Stream3_IRQHandler,   /*!< 59: DMA2 Stream 3                           */
-  DMA2_Stream4_IRQHandler,   /*!< 60: DMA2 Stream 4                           */
-  ETH_IRQHandler,            /*!< 61: Ethernet                                */
-  ETH_WKUP_IRQHandler,       /*!< 62: Ethernet Wakeup through EXTI line       */
-  CAN2_TX_IRQHandler,        /*!< 63: CAN2 TX                                 */
-  CAN2_RX0_IRQHandler,       /*!< 64: CAN2 RX0                                */
-  CAN2_RX1_IRQHandler,       /*!< 65: CAN2 RX1                                */
-  CAN2_SCE_IRQHandler,       /*!< 66: CAN2 SCE                                */
-  OTG_FS_IRQHandler,         /*!< 67: USB OTG FS                              */
-  DMA2_Stream5_IRQHandler,   /*!< 68: DMA2 Stream 5                           */
-  DMA2_Stream6_IRQHandler,   /*!< 69: DMA2 Stream 6                           */
-  DMA2_Stream7_IRQHandler,   /*!< 70: DMA2 Stream 7                           */
-  USART6_IRQHandler,         /*!< 71: USART6                                  */
-  I2C3_EV_IRQHandler,        /*!< 72: I2C3 event                              */
-  I2C3_ER_IRQHandler,        /*!< 73: I2C3 error                              */
-  OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out              */
-  OTG_HS_EP1_IN_IRQHandler,  /*!< 75: USB OTG HS End Point 1 In               */
-  OTG_HS_WKUP_IRQHandler,    /*!< 76: USB OTG HS Wakeup through EXTI          */
-  OTG_HS_IRQHandler,         /*!< 77: USB OTG HS                              */
-  DCMI_IRQHandler,           /*!< 53: DCMI                                    */
-  0,                         /*!< Reserved                                    */
-  RNG_IRQHandler,            /*!< 53: Rng                                     */
-  FPU_IRQHandler,            /*!< 53: FPU                                     */
-  UART7_IRQHandler,          /* UART7                                         */
-  UART8_IRQHandler,          /* UART8                                         */
-  SPI4_IRQHandler,           /* SPI4                                          */
-  SPI5_IRQHandler,           /* SPI5                                          */
-  SPI6_IRQHandler,           /* SPI6                                          */
-  SAI1_IRQHandler,           /* SAI1                                          */
-  LTDC_IRQHandler,           /* LTDC                                          */
-  LTDC_ER_IRQHandler,        /* LTDC error                                    */
-  DMA2D_IRQHandler,          /* DMA2D                                         */
-  SAI2_IRQHandler,           /* SAI2                                          */
-  QUADSPI_IRQHandler,        /* QUADSPI                                       */
-  LPTIM1_IRQHandler,         /* LPTIM1                                        */
-  CEC_IRQHandler,            /* HDMI_CEC                                      */
-  I2C4_EV_IRQHandler,        /* I2C4 Event                                    */
-  I2C4_ER_IRQHandler,        /* I2C4 Error                                    */
-  SPDIF_RX_IRQHandler,       /* SPDIF_RX                                      */
-  0,                         /* Reserved                                      */
-  DFSDM1_FLT0_IRQHandler,    /* DFSDM1 Filter 0 global Interrupt              */
-  DFSDM1_FLT1_IRQHandler,    /* DFSDM1 Filter 1 global Interrupt              */
-  DFSDM1_FLT2_IRQHandler,    /* DFSDM1 Filter 2 global Interrupt              */
-  DFSDM1_FLT3_IRQHandler,    /* DFSDM1 Filter 3 global Interrupt              */
-  SDMMC2_IRQHandler,         /* SDMMC2                                        */
-  CAN3_TX_IRQHandler,        /* CAN3 TX                                       */
-  CAN3_RX0_IRQHandler,       /* CAN3 RX0                                      */
-  CAN3_RX1_IRQHandler,       /* CAN3 RX1                                      */
-  CAN3_SCE_IRQHandler,       /* CAN3 SCE                                      */
-  JPEG_IRQHandler,           /* JPEG                                          */
-  MDIOS_IRQHandler           /* MDIOS                                         */
-};
-
-/* C++ global constructors support */
-static void call_constructors(unsigned long *start, unsigned long *end)
-{
-   unsigned long *i;
-   void (*funcptr)();
-   for ( i = start; i < end; i++)
-   {
-     funcptr=(void (*)())(*i);
-     funcptr();
-   }
-}
-
-
-/**
-  * @brief  This is the code that gets called when the processor first
-  *         starts execution following a reset event. Only the absolutely
-  *         necessary set is performed, after which the application
-  *         supplied main() routine is called.
-  * @param  None
-  * @retval None
-  */
-void Default_Reset_Handler(void)
-{
-  /* Initialize data and bss */
-  unsigned long *pulSrc, *pulDest;
-
-  /* Copy the data segment initializers from flash to SRAM */
-  pulSrc = &_sidata;
-
-  for(pulDest = &_sdata; pulDest < &_edata; )
-  {
-    *(pulDest++) = *(pulSrc++);
-  }
-  
-  /* Zero fill the bss segment.  This is done with inline assembly since this
-     will clear the value of pulDest if it is not kept in a register. */
-  __asm("  ldr     r0, =_sbss\n"
-        "  ldr     r1, =_ebss\n"
-        "  mov     r2, #0\n"
-        "  .thumb_func\n"
-        "zero_loop:\n"
-        "    cmp     r0, r1\n"
-        "    it      lt\n"
-        "    strlt   r2, [r0], #4\n"
-        "    blt     zero_loop");
-#ifdef __FPU_USED
-  /* Enable FPU.*/ 
-  __asm("  LDR.W R0, =0xE000ED88\n"
-        "  LDR R1, [R0]\n"
-        "  ORR R1, R1, #(0xF << 20)\n"
-        "  STR R1, [R0]");
-#endif
-
-  SystemInit();
- 
-  //Call C++ global constructors
-  call_constructors(&__preinit_array_start, &__preinit_array_end);
-  call_constructors(&__init_array_start, &__init_array_end);
-
-  /* Call the application's entry point.*/
-  main();
-}
-
-
-/**
-  *@brief Provide weak aliases for each Exception handler to the Default_Handler.
-  *       As they are weak aliases, any function with the same name will override
-  *       this definition.
-  */
-#pragma weak Reset_Handler = Default_Reset_Handler
-#pragma weak NMI_Handler = Default_Reset_Handler
-#pragma weak HardFault_Handler = Default_Reset_Handler
-#pragma weak MemManage_Handler = Default_Reset_Handler
-#pragma weak BusFault_Handler = Default_Reset_Handler
-#pragma weak UsageFault_Handler = Default_Reset_Handler
-#pragma weak SVC_Handler = Default_Reset_Handler
-#pragma weak DebugMon_Handler = Default_Reset_Handler
-#pragma weak PendSV_Handler = Default_Reset_Handler
-#pragma weak SysTick_Handler = Default_Reset_Handler
-  
-  /* External Interrupts */
-#pragma weak WWDG_IRQHandler = Default_Reset_Handler                   /* Window WatchDog              */
-#pragma weak PVD_IRQHandler = Default_Reset_Handler                    /* PVD through EXTI Line detection */
-#pragma weak TAMP_STAMP_IRQHandler = Default_Reset_Handler             /* Tamper and TimeStamps through the EXTI line */
-#pragma weak RTC_WKUP_IRQHandler = Default_Reset_Handler               /* RTC Wakeup through the EXTI line */
-#pragma weak FLASH_IRQHandler = Default_Reset_Handler                  /* FLASH                        */
-#pragma weak RCC_IRQHandler = Default_Reset_Handler                    /* RCC                          */
-#pragma weak EXTI0_IRQHandler = Default_Reset_Handler                  /* EXTI Line0                   */
-#pragma weak EXTI1_IRQHandler = Default_Reset_Handler                  /* EXTI Line1                   */
-#pragma weak EXTI2_IRQHandler = Default_Reset_Handler                  /* EXTI Line2                   */
-#pragma weak EXTI3_IRQHandler = Default_Reset_Handler                  /* EXTI Line3                   */
-#pragma weak EXTI4_IRQHandler = Default_Reset_Handler                  /* EXTI Line4                   */
-#pragma weak DMA1_Stream0_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 0                */
-#pragma weak DMA1_Stream1_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 1                */
-#pragma weak DMA1_Stream2_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 2                */
-#pragma weak DMA1_Stream3_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 3                */
-#pragma weak DMA1_Stream4_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 4                */
-#pragma weak DMA1_Stream5_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 5                */
-#pragma weak DMA1_Stream6_IRQHandler = Default_Reset_Handler           /* DMA1 Stream 6                */
-#pragma weak ADC_IRQHandler = Default_Reset_Handler                    /* ADC1, ADC2 and ADC3s         */
-#pragma weak CAN1_TX_IRQHandler = Default_Reset_Handler                /* CAN1 TX                      */
-#pragma weak CAN1_RX0_IRQHandler = Default_Reset_Handler               /* CAN1 RX0                     */
-#pragma weak CAN1_RX1_IRQHandler = Default_Reset_Handler               /* CAN1 RX1                     */
-#pragma weak CAN1_SCE_IRQHandler = Default_Reset_Handler               /* CAN1 SCE                     */
-#pragma weak EXTI9_5_IRQHandler = Default_Reset_Handler                /* External Line[9:5]s          */
-#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Reset_Handler          /* TIM1 Break and TIM9          */
-#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Reset_Handler          /* TIM1 Update and TIM10        */
-#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Reset_Handler     /* TIM1 Trigger and Commutation and TIM11 */
-#pragma weak TIM1_CC_IRQHandler = Default_Reset_Handler                /* TIM1 Capture Compare         */
-#pragma weak TIM2_IRQHandler = Default_Reset_Handler                   /* TIM2                         */
-#pragma weak TIM3_IRQHandler = Default_Reset_Handler                   /* TIM3                         */
-#pragma weak TIM4_IRQHandler = Default_Reset_Handler                   /* TIM4                         */
-#pragma weak I2C1_EV_IRQHandler = Default_Reset_Handler                /* I2C1 Event                   */
-#pragma weak I2C1_ER_IRQHandler = Default_Reset_Handler                /* I2C1 Error                   */
-#pragma weak I2C2_EV_IRQHandler = Default_Reset_Handler                /* I2C2 Event                   */
-#pragma weak I2C2_ER_IRQHandler = Default_Reset_Handler                /* I2C2 Error                   */
-#pragma weak SPI1_IRQHandler = Default_Reset_Handler                   /* SPI1                         */
-#pragma weak SPI2_IRQHandler = Default_Reset_Handler                   /* SPI2                         */
-#pragma weak USART1_IRQHandler = Default_Reset_Handler                 /* USART1                       */
-#pragma weak USART2_IRQHandler = Default_Reset_Handler                 /* USART2                       */
-#pragma weak USART3_IRQHandler = Default_Reset_Handler                 /* USART3                       */
-#pragma weak EXTI15_10_IRQHandler = Default_Reset_Handler              /* External Line[15:10]s        */
-#pragma weak RTC_Alarm_IRQHandler = Default_Reset_Handler              /* RTC Alarm (A and B) through EXTI Line */
-#pragma weak OTG_FS_WKUP_IRQHandler = Default_Reset_Handler            /* USB OTG FS Wakeup through EXTI line */
-#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Reset_Handler         /* TIM8 Break and TIM12         */
-#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Reset_Handler          /* TIM8 Update and TIM13        */
-#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Reset_Handler     /* TIM8 Trigger and Commutation and TIM14 */
-#pragma weak TIM8_CC_IRQHandler = Default_Reset_Handler                /* TIM8 Capture Compare         */
-#pragma weak DMA1_Stream7_IRQHandler = Default_Reset_Handler           /* DMA1 Stream7                 */
-#pragma weak FMC_IRQHandler = Default_Reset_Handler                    /* FMC                          */
-#pragma weak SDMMC1_IRQHandler = Default_Reset_Handler                 /* SDMMC1                       */
-#pragma weak TIM5_IRQHandler = Default_Reset_Handler                   /* TIM5                         */
-#pragma weak SPI3_IRQHandler = Default_Reset_Handler                   /* SPI3                         */
-#pragma weak UART4_IRQHandler = Default_Reset_Handler                  /* UART4                        */
-#pragma weak UART5_IRQHandler = Default_Reset_Handler                  /* UART5                        */
-#pragma weak TIM6_DAC_IRQHandler = Default_Reset_Handler               /* TIM6 and DAC1&2 underrun errors */
-#pragma weak TIM7_IRQHandler = Default_Reset_Handler                   /* TIM7                         */
-#pragma weak DMA2_Stream0_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 0                */
-#pragma weak DMA2_Stream1_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 1                */
-#pragma weak DMA2_Stream2_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 2                */
-#pragma weak DMA2_Stream3_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 3                */
-#pragma weak DMA2_Stream4_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 4                */
-#pragma weak ETH_IRQHandler = Default_Reset_Handler                    /* Ethernet                     */
-#pragma weak ETH_WKUP_IRQHandler = Default_Reset_Handler               /* Ethernet Wakeup through EXTI line */
-#pragma weak CAN2_TX_IRQHandler = Default_Reset_Handler                /* CAN2 TX                      */
-#pragma weak CAN2_RX0_IRQHandler = Default_Reset_Handler               /* CAN2 RX0                     */
-#pragma weak CAN2_RX1_IRQHandler = Default_Reset_Handler               /* CAN2 RX1                     */
-#pragma weak CAN2_SCE_IRQHandler = Default_Reset_Handler               /* CAN2 SCE                     */
-#pragma weak OTG_FS_IRQHandler = Default_Reset_Handler                 /* USB OTG FS                   */
-#pragma weak DMA2_Stream5_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 5                */
-#pragma weak DMA2_Stream6_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 6                */
-#pragma weak DMA2_Stream7_IRQHandler = Default_Reset_Handler           /* DMA2 Stream 7                */
-#pragma weak USART6_IRQHandler = Default_Reset_Handler                 /* USART6                       */
-#pragma weak I2C3_EV_IRQHandler = Default_Reset_Handler                /* I2C3 event                   */
-#pragma weak I2C3_ER_IRQHandler = Default_Reset_Handler                /* I2C3 error                   */
-#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Reset_Handler         /* USB OTG HS End Point 1 Out   */
-#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Reset_Handler          /* USB OTG HS End Point 1 In    */
-#pragma weak OTG_HS_WKUP_IRQHandler = Default_Reset_Handler            /* USB OTG HS Wakeup through EXTI */
-#pragma weak OTG_HS_IRQHandler = Default_Reset_Handler                 /* USB OTG HS                   */
-#pragma weak DCMI_IRQHandler = Default_Reset_Handler                   /* DCMI                         */
-#pragma weak RNG_IRQHandler = Default_Reset_Handler                    /* RNG                          */
-#pragma weak FPU_IRQHandler = Default_Reset_Handler                    /* FPU                          */
-#pragma weak UART7_IRQHandler = Default_Reset_Handler                  /* UART7                        */
-#pragma weak UART8_IRQHandler = Default_Reset_Handler                  /* UART8                        */
-#pragma weak SPI4_IRQHandler = Default_Reset_Handler                   /* SPI4                         */
-#pragma weak SPI5_IRQHandler = Default_Reset_Handler                   /* SPI5                         */
-#pragma weak SPI6_IRQHandler = Default_Reset_Handler                   /* SPI6                         */
-#pragma weak SAI1_IRQHandler = Default_Reset_Handler                   /* SAI1                         */
-#pragma weak LTDC_IRQHandler = Default_Reset_Handler                   /* LTDC                         */
-#pragma weak LTDC_ER_IRQHandler = Default_Reset_Handler                /* LTDC error                   */
-#pragma weak DMA2D_IRQHandler = Default_Reset_Handler                  /* DMA2D                        */
-#pragma weak SAI2_IRQHandler = Default_Reset_Handler                   /* SAI2                         */
-#pragma weak QUADSPI_IRQHandler = Default_Reset_Handler                /* QUADSPI                      */
-#pragma weak LPTIM1_IRQHandler = Default_Reset_Handler                 /* LPTIM1                       */
-#pragma weak CEC_IRQHandler = Default_Reset_Handler                    /* HDMI_CEC                     */
-#pragma weak I2C4_EV_IRQHandler = Default_Reset_Handler                /* I2C4 Event                   */
-#pragma weak I2C4_ER_IRQHandler = Default_Reset_Handler                /* I2C4 Error                   */
-#pragma weak SPDIF_RX_IRQHandler = Default_Reset_Handler               /* SPDIF_RX                     */
-#pragma weak DFSDM1_FLT0_IRQHandler = Default_Reset_Handler            /* DFSDM1 Filter 0 global Interrupt */
-#pragma weak DFSDM1_FLT1_IRQHandler = Default_Reset_Handler            /* DFSDM1 Filter 1 global Interrupt */
-#pragma weak DFSDM1_FLT2_IRQHandler = Default_Reset_Handler            /* DFSDM1 Filter 2 global Interrupt */
-#pragma weak DFSDM1_FLT3_IRQHandler = Default_Reset_Handler            /* DFSDM1 Filter 3 global Interrupt */
-#pragma weak SDMMC2_IRQHandler = Default_Reset_Handler                 /* SDMMC2                       */
-#pragma weak CAN3_TX_IRQHandler = Default_Reset_Handler                /* CAN3 TX                      */
-#pragma weak CAN3_RX0_IRQHandler = Default_Reset_Handler               /* CAN3 RX0                     */
-#pragma weak CAN3_RX1_IRQHandler = Default_Reset_Handler               /* CAN3 RX1                     */
-#pragma weak CAN3_SCE_IRQHandler = Default_Reset_Handler               /* CAN3 SCE                     */
-#pragma weak JPEG_IRQHandler = Default_Reset_Handler                   /* JPEG                         */
-#pragma weak MDIOS_IRQHandler = Default_Reset_Handler                  /* MDIOS                        */
-
-/**
-  * @brief  This is the code that gets called when the processor receives an
-  *         unexpected interrupt.  This simply enters an infinite loop,
-  *         preserving the system state for examination by a debugger.
-  * @param  None
-  * @retval None
-  */
-static void Default_Handler(void)
-{
-  /* Go into an infinite loop. */
-  while (1)
-  {
-  }
-}
-
-/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/

STM32F7XX_Lib/Device/stm32f7xx.h

@@ -1,230 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32F7xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx
-  * @{
-  */
-    
-#ifndef __STM32F7xx_H
-#define __STM32F7xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined  (STM32F7)
-#define STM32F7
-#endif /* STM32F7 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
-    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
-	!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
-  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
-                                   STM32F756NG Devices */
-  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
-                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
-  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
-  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
-                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
-  /* #define STM32F767xx */        /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
-                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
-  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
-                                   STM32F769NG, STM32F769NI, STM32F768AI Devices */
-  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
-  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
-  /* #define STM32F722xx */   /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
-                                   STM32F722VC, STM32F722RC Devices */
-  /* #define STM32F723xx */   /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
-  /* #define STM32F732xx */   /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
-  /* #define STM32F733xx */   /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  //#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.2.0
-  */
-#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
-                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32F7_CMSIS_VERSION))
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-#if defined(STM32F722xx)
-  #include "stm32f722xx.h"
-#elif defined(STM32F723xx)
-  #include "stm32f723xx.h"
-#elif defined(STM32F732xx)
-  #include "stm32f732xx.h"
-#elif defined(STM32F733xx)
-  #include "stm32f733xx.h"    
-#elif defined(STM32F756xx)
-  #include "stm32f756xx.h"
-#elif defined(STM32F746xx)
-  #include "stm32f746xx.h"
-#elif defined(STM32F745xx)
-  #include "stm32f745xx.h"
-#elif defined(STM32F765xx)
-  #include "stm32f765xx.h"
-#elif defined(STM32F767xx)
-  #include "stm32f767xx.h"
-#elif defined(STM32F769xx)
-  #include "stm32f769xx.h"
-#elif defined(STM32F777xx)
-  #include "stm32f777xx.h"
-#elif defined(STM32F779xx)
-  #include "stm32f779xx.h"  
-#else
- #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-/**
-  * @}
-  */
-
-#ifdef USE_HAL_DRIVER
-  #include "stm32f7xx_hal_conf.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F7xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F7XX_Lib/Device/stm32f7xx_hal_conf.h

@@ -1,228 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    25-June-2015
-  * @brief   HAL configuration file. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  ART_ACCLERATOR_ENABLE        1 /* To enable instruction cache and prefetch */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-#define USE_FULL_ASSERT    1 
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-   
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "misc.h"
-#include "stm32f7xx_adc.h"
-#include "stm32f7xx_dac.h"
-#include "stm32f7xx_flash.h"
-#include "stm32f7xx_gpio.h"
-#include "stm32f7xx_pwr.h"
-#include "stm32f7xx_rcc.h"
-#include "stm32f7xx_tim.h"
-#include "stm32f7xx_usart.h"
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F7XX_Lib/Device/system_stm32f7xx.c

@@ -1,405 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/************************* PLL Parameters *************************************/
-/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#define PLL_M      (HSE_VALUE/1000000)
-
-static void CPU_CACHE_Enable(void);
-static void MPU_Config(void);
-static void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 216000000;
-  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-  
-  MPU_Config();
-  CPU_CACHE_Enable();
-  SetSysClock();
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow : 
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 216000000
-  *            HCLK(Hz)                       = 216000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 4
-  *            APB2 Prescaler                 = 2
-  *            HSE Frequency(Hz)              = 8000000
-  *            PLL_M                          = 8
-  *            PLL_N                          = 432
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 9
-  *            VDD(V)                         = 3.3
-  *            Main regulator output voltage  = Scale1 mode
-  *            Flash Latency(WS)              = 7
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  RCC_HSEConfig(RCC_HSE_ON);
-  
-  if ( RCC_WaitForHSEStartUp() != SUCCESS )
-  {
-    while(1);
-  }
-  
-  RCC_PLLConfig(RCC_PLLSource_HSE, PLL_M, 432, 2, 9);
-  RCC_PLLCmd(ENABLE);
-  
-  while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-  
-  /* Activate the OverDrive to reach the 216 MHz Frequency */  
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-  
-  PWR_OverDriveCmd(ENABLE);
-  
-  while(PWR_GetFlagStatus(PWR_FLAG_ODRDY) == RESET );
-  
-  while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
-  
-  PWR_OverDriveSWCmd(ENABLE);
-  
-  while(PWR_GetFlagStatus(PWR_FLAG_ODSWRDY) == RESET );
-  
-  FLASH_SetLatency(FLASH_Latency_7);
-  RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-  
-  RCC_HCLKConfig(RCC_SYSCLK_Div1);
-  RCC_PCLK1Config(RCC_HCLK_Div4);
-  RCC_PCLK2Config(RCC_HCLK_Div2);
-  
-  SystemCoreClockUpdate();
-}
-
-/**
-  * @brief  Configure the MPU attributes as Write Through for SRAM1/2.
-  * @note   The Base Address is 0x20020000 since this memory interface is the AXI.
-  *         The Region Size is 384KB, it is related to SRAM1 and SRAM2  memory size.
-  * @param  None
-  * @retval None
-  */
-static void MPU_Config(void)
-{
-  MPU_Region_InitTypeDef MPU_InitStruct;
-  
-  /* Disable the MPU */
-  MPU_Disable();
-
-  /* Configure the MPU attributes as WT for SRAM */
-  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
-  MPU_InitStruct.BaseAddress = 0x20020000;
-  MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
-  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
-  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
-  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
-  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
-  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
-  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
-  MPU_InitStruct.SubRegionDisable = 0x00;
-  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
-
-  MPU_ConfigRegion(&MPU_InitStruct);
-
-  /* Enable the MPU */
-  MPU_Enable(MPU_PRIVILEGED_DEFAULT);
-}
-
-/**
-  * @brief  CPU L1-Cache enable.
-  * @param  None
-  * @retval None
-  */
-static void CPU_CACHE_Enable(void)
-{
-  /* Enable branch prediction */
-  SCB->CCR |= (1 <<18); 
-  __DSB();
-
-  /* Enable I-Cache */
-  SCB_EnableICache();	
-	
-  /* Enable D-Cache */
-  SCB_EnableDCache();
-}
-
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F7XX_Lib/Device/system_stm32f7xx.h

@@ -1,125 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F7XX_H
-#define __SYSTEM_STM32F7XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F7xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F7xx_System_Exported_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-    */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F7XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32F7XX_Lib/README.txt

@@ -1,26 +0,0 @@
-STM32F7XX library for MMDVM project
-
-This is the STM32F7XX_Lib directory structure with just the needed code for MMDVM.
-Copy this STM32F7XX_Lib directory inside the MMDVM source code project. You have to
-conserve the STM32F7XX_Lib folder name: MMDVM/STM32F7XX_Lib
-
-The source of CMSIS library and some include files is from STM32Cube_FW_F7_V1.7.0:
-http://www.st.com/content/st_com/en/products/embedded-software/mcus-embedded-software/stm32-embedded-software/stm32cube-embedded-software/stm32cubef7.html
-
-The adaptation to STM32F7 Standard Peripheral Library (STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver) is from:
-https://gitlab.com/caesar-lab/stm32f7-legacy-library
-
-In order to run the MMDVM firmware correctly, there are the following modifications
-already done in this package:
-
-1) STM32F7XX_Lib/Device/startup/startup_stm32f7xx.c :
-- Added C++ global constructors support
-- Changed initial stack pointer
-- Changed support for STM32F767
-
-2) STM32F7XX_Lib/Device/system_stm32f7xx.c :
-- Changed PLL_M definition (support "integer" only crystal frequencies: 8, 12, 16 MHz, etc)
-- Added functions: SetSysClock(), MPU_Config(), CPU_CACHE_Enable() from examples in https://gitlab.com/caesar-lab/stm32f7-legacy-library
-
-3) STM32F7XX_Lib/Device/stm32f7xx_hal_conf.h :
-- Peripheral header file inclusions

STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/misc.h

@@ -1,378 +0,0 @@
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx.h"
-
-/** @addtogroup STM32F7xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-   
-/** 
-  * @brief  NVIC Init Structure definition  
-  */
-
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be an enumerator of @ref IRQn_Type 
-                                                   enumeration (For the complete STM32 Devices IRQ Channels
-                                                   list, please refer to stm32f7xx.h file) */
-
-  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
-                                                   specified in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
-                                                   in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled. 
-                                                   This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup MISC_Vector_Table_Base 
-  * @{
-  */
-
-#define NVIC_VectTab_RAM             ((uint32_t)SRAM1_BASE)
-#define NVIC_VectTab_FLASH           ((uint32_t)FLASH_BASE)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
-                                  ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_System_Low_Power 
-  * @{
-  */
-
-#define NVIC_LP_SEVONPEND            ((uint8_t)SCB_SCR_SEVONPEND_Msk)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)SCB_SCR_SLEEPDEEP_Msk)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)SCB_SCR_SLEEPONEXIT_Msk)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Preemption_Priority_Group 
-  * @{
-  */
-
-#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
-                                                            4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
-                                                            3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
-                                                            2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
-                                                            1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
-                                                            0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
-                                       ((GROUP) == NVIC_PriorityGroup_1) || \
-                                       ((GROUP) == NVIC_PriorityGroup_2) || \
-                                       ((GROUP) == NVIC_PriorityGroup_3) || \
-                                       ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
-
-/**
-  * @}
-  */
-
-
-/** @defgroup MISC_SysTick_clock_source 
-  * @{
-  */
-
-#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
-                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-/**                                
-  * @}
-  */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-#if (__MPU_PRESENT == 1)
-void MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-void MPU_Disable(void);
-void MPU_Enable(uint32_t MPU_Control);
-#endif /* __MPU_PRESENT */
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_adc.h

@@ -1,617 +0,0 @@
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_ADC_H
-#define __STM32F7xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx.h"
-
-/** @addtogroup STM32F7xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief   ADC Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
-                                               This parameter can be a value of @ref ADC_resolution */                                   
-  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
-                                               is performed in Scan (multichannels) 
-                                               or Single (one channel) mode.
-                                               This parameter can be set to ENABLE or DISABLE */ 
-  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
-                                               is performed in Continuous or Single mode.
-                                               This parameter can be set to ENABLE or DISABLE. */
-  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
-                                               enable the trigger of a regular group. 
-                                               This parameter can be a value of 
-                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
-  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
-                                               the start of conversion of a regular group.
-                                               This parameter can be a value of 
-                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
-  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
-                                               is left or right. This parameter can be 
-                                               a value of @ref ADC_data_align */
-  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
-                                               that will be done using the sequencer for
-                                               regular channel group.
-                                               This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-  
-/** 
-  * @brief   ADC Common Init structure definition  
-  */ 
-typedef struct 
-{
-  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
-                                               independent or multi mode. 
-                                               This parameter can be a value of @ref ADC_Common_mode */                                              
-  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
-                                               to the ADC. The clock is common for all the ADCs.
-                                               This parameter can be a value of @ref ADC_Prescaler */
-  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
-                                              mode for multi ADC mode.
-                                               This parameter can be a value of 
-                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
-  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
-                                               This parameter can be a value of 
-                                               @ref ADC_delay_between_2_sampling_phases */
-  
-}ADC_CommonInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
-  * @{
-  */ 
-#define IS_ADC_ALL_PERIPH(PERIPH) (IS_ADC_ALL_INSTANCE(PERIPH))
-
-/** @defgroup ADC_Common_mode 
-  * @{
-  */ 
-#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
-#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
-#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
-#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
-#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
-#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
-#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
-#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
-#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
-#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
-#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
-#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
-#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
-                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_DualMode_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult) || \
-                           ((MODE) == ADC_DualMode_Interl) || \
-                           ((MODE) == ADC_DualMode_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult) || \
-                           ((MODE) == ADC_TripleMode_Interl) || \
-                           ((MODE) == ADC_TripleMode_AlterTrig))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Prescaler 
-  * @{
-  */ 
-#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
-#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
-#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
-#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div8))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
-  * @{
-  */ 
-#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
-#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
-                                      ((MODE) == ADC_DMAAccessMode_1) || \
-                                      ((MODE) == ADC_DMAAccessMode_2) || \
-                                      ((MODE) == ADC_DMAAccessMode_3))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_delay_between_2_sampling_phases 
-  * @{
-  */ 
-#define ADC_TwoSamplingDelay_5Cycles    ((uint32_t)0x00000000)
-#define ADC_TwoSamplingDelay_6Cycles    ((uint32_t)ADC_CCR_DELAY_0)
-#define ADC_TwoSamplingDelay_7Cycles    ((uint32_t)ADC_CCR_DELAY_1)
-#define ADC_TwoSamplingDelay_8Cycles    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_9Cycles    ((uint32_t)ADC_CCR_DELAY_2)
-#define ADC_TwoSamplingDelay_10Cycles   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_11Cycles   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TwoSamplingDelay_12Cycles   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_13Cycles   ((uint32_t)ADC_CCR_DELAY_3)
-#define ADC_TwoSamplingDelay_14Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_15Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
-#define ADC_TwoSamplingDelay_16Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_17Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
-#define ADC_TwoSamplingDelay_18Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TwoSamplingDelay_19Cycles   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TwoSamplingDelay_20Cycles   ((uint32_t)ADC_CCR_DELAY)
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_resolution 
-  * @{
-  */ 
-#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
-#define ADC_Resolution_10b                         ((uint32_t)ADC_CR1_RES_0)
-#define ADC_Resolution_8b                          ((uint32_t)ADC_CR1_RES_1)
-#define ADC_Resolution_6b                          ((uint32_t)ADC_CR1_RES)
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
-                                       ((RESOLUTION) == ADC_Resolution_10b) || \
-                                       ((RESOLUTION) == ADC_Resolution_8b) || \
-                                       ((RESOLUTION) == ADC_Resolution_6b))
-                                      
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)ADC_CR2_EXTEN_0)
-#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)ADC_CR2_EXTEN)
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
-  * @{
-  */ 
-
-#define ADC_ExternalTrigConv_T1_CC1    ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
-#define ADC_ExternalTrigConv_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
-#define ADC_ExternalTrigConv_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_ExternalTrigConv_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_ExternalTrigConv_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_ExternalTrigConv_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_ExternalTrigConv_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_ExternalTrigConv_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)
-#define ADC_ExternalTrigConv_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
-#define ADC_ExternalTrigConv_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
-#define ADC_ExternalTrigConv_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_ExternalTrigConv_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
-#define ADC_ExternalTrigConv_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-
-#define ADC_ExternalTrigConv_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_Software_Start             ((uint32_t)ADC_CR2_EXTSEL + 1)
-
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)  || \
-                                  ((REGTRIG) == ADC_Software_Start))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_data_align 
-  * @{
-  */ 
-#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left                         ((uint32_t)ADC_CR2_ALIGN)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
-                                  ((ALIGN) == ADC_DataAlign_Left))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_channels 
-  * @{
-  */ 
-#define ADC_Channel_0           ((uint32_t)0x00000000)
-#define ADC_Channel_1           ((uint32_t)ADC_CR1_AWDCH_0)
-#define ADC_Channel_2           ((uint32_t)ADC_CR1_AWDCH_1)
-#define ADC_Channel_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_4           ((uint32_t)ADC_CR1_AWDCH_2)
-#define ADC_Channel_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_Channel_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_8           ((uint32_t)ADC_CR1_AWDCH_3)
-#define ADC_Channel_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
-#define ADC_Channel_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
-#define ADC_Channel_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_Channel_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_16          ((uint32_t)ADC_CR1_AWDCH_4)
-#define ADC_Channel_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
-#define ADC_Channel_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-
-#define ADC_Channel_Vrefint                         ((uint32_t)ADC_Channel_17)
-#define ADC_Channel_Vbat                            ((uint32_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
-                                 ((CHANNEL) == ADC_Channel_1) || \
-                                 ((CHANNEL) == ADC_Channel_2) || \
-                                 ((CHANNEL) == ADC_Channel_3) || \
-                                 ((CHANNEL) == ADC_Channel_4) || \
-                                 ((CHANNEL) == ADC_Channel_5) || \
-                                 ((CHANNEL) == ADC_Channel_6) || \
-                                 ((CHANNEL) == ADC_Channel_7) || \
-                                 ((CHANNEL) == ADC_Channel_8) || \
-                                 ((CHANNEL) == ADC_Channel_9) || \
-                                 ((CHANNEL) == ADC_Channel_10) || \
-                                 ((CHANNEL) == ADC_Channel_11) || \
-                                 ((CHANNEL) == ADC_Channel_12) || \
-                                 ((CHANNEL) == ADC_Channel_13) || \
-                                 ((CHANNEL) == ADC_Channel_14) || \
-                                 ((CHANNEL) == ADC_Channel_15) || \
-                                 ((CHANNEL) == ADC_Channel_16) || \
-                                 ((CHANNEL) == ADC_Channel_17) || \
-                                 ((CHANNEL) == ADC_Channel_18))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_sampling_times 
-  * @{
-  */ 
-#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
-#define ADC_SampleTime_15Cycles                   ((uint32_t)ADC_SMPR1_SMP10_0)
-#define ADC_SampleTime_28Cycles                   ((uint32_t)ADC_SMPR1_SMP10_1)
-#define ADC_SampleTime_56Cycles                   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
-#define ADC_SampleTime_84Cycles                   ((uint32_t)ADC_SMPR1_SMP10_2)
-#define ADC_SampleTime_112Cycles                  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
-#define ADC_SampleTime_144Cycles                  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
-#define ADC_SampleTime_480Cycles                  ((uint32_t)ADC_SMPR1_SMP10)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
-                                  ((TIME) == ADC_SampleTime_15Cycles) || \
-                                  ((TIME) == ADC_SampleTime_28Cycles) || \
-                                  ((TIME) == ADC_SampleTime_56Cycles) || \
-                                  ((TIME) == ADC_SampleTime_84Cycles) || \
-                                  ((TIME) == ADC_SampleTime_112Cycles) || \
-                                  ((TIME) == ADC_SampleTime_144Cycles) || \
-                                  ((TIME) == ADC_SampleTime_480Cycles))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
-#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
-                                            
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
-  * @{
-  */ 
-
-#define ADC_ExternalTrigInjecConv_T1_TRGO         ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)
-#define ADC_ExternalTrigInjecConv_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)
-#define ADC_ExternalTrigInjecConv_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_ExternalTrigInjecConv_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)
-#define ADC_ExternalTrigInjecConv_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-
-#define ADC_ExternalTrigInjecConv_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_ExternalTrigInjecConv_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)
-#define ADC_ExternalTrigInjecConv_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
-#define ADC_ExternalTrigInjecConv_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
-#define ADC_ExternalTrigInjecConv_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_ExternalTrigInjecConv_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
-#define ADC_ExternalTrigInjecConv_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_ExternalTrigInjecConv_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_TRGO2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC3) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_channel_selection 
-  * @{
-  */ 
-#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
-#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
-#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_analog_watchdog_selection 
-  * @{
-  */ 
-#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)ADC_CR1_AWDEN)
-#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)ADC_CR1_JAWDEN)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_interrupts_definition 
-  * @{
-  */ 
-#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
-#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
-#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
-#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
-                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_flags_definition 
-  * @{
-  */ 
-#define ADC_FLAG_AWD                               ((uint8_t)0x01)
-#define ADC_FLAG_EOC                               ((uint8_t)0x02)
-#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
-#define ADC_FLAG_STRT                              ((uint8_t)0x10)
-#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
-  
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
-                               ((FLAG) == ADC_FLAG_EOC) || \
-                               ((FLAG) == ADC_FLAG_JEOC) || \
-                               ((FLAG)== ADC_FLAG_JSTRT) || \
-                               ((FLAG) == ADC_FLAG_STRT) || \
-                               ((FLAG)== ADC_FLAG_OVR))     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_thresholds 
-  * @{
-  */ 
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_offset 
-  * @{
-  */ 
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_length 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_rank 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_length 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_rank 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_discontinuous_mode_number 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the ADC configuration to the default reset state *****/  
-void ADC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and VBAT management functions ******************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-void ADC_VBATCmd(FunctionalState NewState);
-
-/* Regular Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetMultiModeConversionValue(void);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_ADC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 

STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_dac.h

@@ -1,277 +0,0 @@
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_DAC_H
-#define __STM32F7xx_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx.h"
-
-/** @addtogroup STM32F7xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DAC Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
-                                                  This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
-                                                  are generated, or whether no wave is generated.
-                                                  This parameter can be a value of @ref DAC_wave_generation */
-
-  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
-                                                  the maximum amplitude triangle generation for the DAC channel. 
-                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
-  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                                  This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup DAC_trigger_selection 
-  * @{
-  */
-
-#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_Trigger_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-
-#define DAC_Trigger_Ext_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
-                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
-                                 ((TRIGGER) == DAC_Trigger_Software))
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
-                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
-                                    ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
-  * @{
-  */
-
-#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer 
-  * @{
-  */
-
-#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
-                                           ((STATE) == DAC_OutputBuffer_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection 
-  * @{
-  */
-
-#define DAC_Channel_1                      ((uint32_t)0x00000000)
-#define DAC_Channel_2                      ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
-                                 ((CHANNEL) == DAC_Channel_2))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement 
-  * @{
-  */
-
-#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
-#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
-#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
-                             ((ALIGN) == DAC_Align_12b_L) || \
-                             ((ALIGN) == DAC_Align_8b_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
-                           ((WAVE) == DAC_Wave_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data 
-  * @{
-  */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_interrupts_definition 
-  * @{
-  */   
-#define DAC_IT_DMAUDR1                     ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                     ((uint32_t)DAC_SR_DMAUDR2)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || ((IT) == DAC_IT_DMAUDR2) ) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup DAC_flags_definition 
-  * @{
-  */ 
-  
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || ((FLAG) == DAC_FLAG_DMAUDR2))  
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the DAC configuration to the default reset state *****/  
-void DAC_DeInit(void);
-
-/*  DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_DAC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_flash.h

@@ -1,366 +0,0 @@
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_FLASH_H
-#define __STM32F7xx_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx.h"
-
-/** @addtogroup STM32F7xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** 
-  * @brief FLASH Status  
-  */ 
-typedef enum
-{ 
-  FLASH_BUSY = 1,
-  FLASH_ERROR_ERS,
-  FLASH_ERROR_PGP,
-  FLASH_ERROR_PGA,
-  FLASH_ERROR_WRP,
-  FLASH_ERROR_PROGRAM,
-  FLASH_ERROR_OPERATION,
-  FLASH_COMPLETE
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
-  * @{
-  */  
-
-/** @defgroup Flash_Latency 
-  * @{
-  */ 
-#define FLASH_Latency_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_Latency_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_Latency_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_Latency_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_Latency_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_Latency_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_Latency_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_Latency_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#define FLASH_Latency_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
-#define FLASH_Latency_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
-#define FLASH_Latency_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
-#define FLASH_Latency_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
-#define FLASH_Latency_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
-#define FLASH_Latency_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
-#define FLASH_Latency_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
-#define FLASH_Latency_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0)  || \
-                                   ((LATENCY) == FLASH_Latency_1)  || \
-                                   ((LATENCY) == FLASH_Latency_2)  || \
-                                   ((LATENCY) == FLASH_Latency_3)  || \
-                                   ((LATENCY) == FLASH_Latency_4)  || \
-                                   ((LATENCY) == FLASH_Latency_5)  || \
-                                   ((LATENCY) == FLASH_Latency_6)  || \
-                                   ((LATENCY) == FLASH_Latency_7)  || \
-                                   ((LATENCY) == FLASH_Latency_8)  || \
-                                   ((LATENCY) == FLASH_Latency_9)  || \
-                                   ((LATENCY) == FLASH_Latency_10) || \
-                                   ((LATENCY) == FLASH_Latency_11) || \
-                                   ((LATENCY) == FLASH_Latency_12) || \
-                                   ((LATENCY) == FLASH_Latency_13) || \
-                                   ((LATENCY) == FLASH_Latency_14) || \
-                                   ((LATENCY) == FLASH_Latency_15))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Voltage_Range 
-  * @{
-  */ 
-#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
-#define VoltageRange_2        ((uint8_t)0x01)  /*!<Device operating range: 2.1V to 2.7V */
-#define VoltageRange_3        ((uint8_t)0x02)  /*!<Device operating range: 2.7V to 3.6V */
-#define VoltageRange_4        ((uint8_t)0x03)  /*!<Device operating range: 2.7V to 3.6V + External Vpp */
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
-                               ((RANGE) == VoltageRange_2) || \
-                               ((RANGE) == VoltageRange_3) || \
-                               ((RANGE) == VoltageRange_4))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Sectors FLASH Sectors
-  * @{
-  */
-#define FLASH_Sector_0     ((uint32_t)0) /*!< Sector Number 0   */
-#define FLASH_Sector_1     ((uint32_t)1) /*!< Sector Number 1   */
-#define FLASH_Sector_2     ((uint32_t)2) /*!< Sector Number 2   */
-#define FLASH_Sector_3     ((uint32_t)3) /*!< Sector Number 3   */
-#define FLASH_Sector_4     ((uint32_t)4) /*!< Sector Number 4   */
-#define FLASH_Sector_5     ((uint32_t)5) /*!< Sector Number 5   */
-#define FLASH_Sector_6     ((uint32_t)6) /*!< Sector Number 6   */
-#define FLASH_Sector_7     ((uint32_t)7) /*!< Sector Number 7   */
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0)   || ((SECTOR) == FLASH_Sector_1)   ||\
-                                 ((SECTOR) == FLASH_Sector_2)   || ((SECTOR) == FLASH_Sector_3)   ||\
-                                 ((SECTOR) == FLASH_Sector_4)   || ((SECTOR) == FLASH_Sector_5)   ||\
-                                 ((SECTOR) == FLASH_Sector_6)   || ((SECTOR) == FLASH_Sector_7))
-
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-#define OB_WRP_Sector_0       ((uint32_t)0x00010000) /*!< Write protection of Sector0     */
-#define OB_WRP_Sector_1       ((uint32_t)0x00020000) /*!< Write protection of Sector1     */
-#define OB_WRP_Sector_2       ((uint32_t)0x00040000) /*!< Write protection of Sector2     */
-#define OB_WRP_Sector_3       ((uint32_t)0x00080000) /*!< Write protection of Sector3     */
-#define OB_WRP_Sector_4       ((uint32_t)0x00100000) /*!< Write protection of Sector4     */
-#define OB_WRP_Sector_5       ((uint32_t)0x00200000) /*!< Write protection of Sector5     */
-#define OB_WRP_Sector_6       ((uint32_t)0x00400000) /*!< Write protection of Sector6     */
-#define OB_WRP_Sector_7       ((uint32_t)0x00800000) /*!< Write protection of Sector7     */
-#define OB_WRP_Sector_All     ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(SECTOR)  ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
-
-/**
-  * @}
-  */
-
-  /** @defgroup FLASH_Option_Bytes_Read_Protection 
-  * @{
-  */
-#define OB_RDP_Level_0   ((uint8_t)0xAA)
-#define OB_RDP_Level_1   ((uint8_t)0x55)
-#define OB_RDP_Level_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
-                                              it's no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
-                          ((LEVEL) == OB_RDP_Level_1))/*||\
-                          ((LEVEL) == OB_RDP_Level_2))*/
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
-  * @{
-  */ 
-#define OB_WWDG_SW                      ((uint32_t)0x10)  /*!< Software WWDG selected */
-#define OB_WWDG_HW                      ((uint32_t)0x00)  /*!< Hardware WWDG selected */
-#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog 
-  * @{
-  */ 
-#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP 
-  * @{
-  */ 
-#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
-  * @{
-  */ 
-#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
-  * @{
-  */
-#define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
-#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */
-#define IS_OB_IWDG_STOP_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_STOP_FREEZE) || ((SOURCE) == OB_IWDG_STOP_ACTIVE))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
-  * @{
-  */
-#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */
-#define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */
-#define IS_OB_IWDG_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_STDBY_FREEZE) || ((SOURCE) == OB_IWDG_STDBY_ACTIVE))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
-  * @{
-  */
-#define OB_BOR_LEVEL3          ((uint32_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2          ((uint32_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1          ((uint32_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF             ((uint32_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
-                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
-  * @{
-  */
-#define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10)  /*!< Boot 0 Address configuration   */
-#define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20)  /*!< Boot 1 Address configuration   */
-#define IS_OB_BOOT_OPTION(BOOT)       (((BOOT) == OPTIONBYTE_BOOTADDR_0)   || \
-                                     ((BOOT) == OPTIONBYTE_BOOTADDR_1))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
-  * @{
-  */
-#define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000)  /*!< Boot from ITCM RAM (0x00000000)                 */
-#define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040)  /*!< Boot from System memory bootloader (0x00100000) */
-#define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080)  /*!< Boot from Flash on ITCM interface (0x00200000)  */
-#define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
-#define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000)  /*!< Boot from DTCM RAM (0x20000000)                 */
-#define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004)  /*!< Boot from SRAM1 (0x20010000)                    */
-#define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013)  /*!< Boot from SRAM2 (0x2004C000)                    */
-#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM)   || \
-                                     ((ADDRESS) == OB_BOOTADDR_SYSTEM)     || \
-                                     ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \
-                                     ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \
-                                     ((ADDRESS) == OB_BOOTADDR_DTCM_RAM)   || \
-                                     ((ADDRESS) == OB_BOOTADDR_SRAM1)      || \
-                                     ((ADDRESS) == OB_BOOTADDR_SRAM2))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupts 
-  * @{
-  */ 
-#define FLASH_IT_EOP                   ((uint32_t)FLASH_CR_EOPIE)  /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   ((uint32_t)FLASH_CR_ERRIE)  /*!< Error Interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Flags 
-  * @{
-  */ 
-#define FLASH_FLAG_EOP                 ((uint32_t)FLASH_SR_EOP)  /*!< FLASH End of Operation flag               */
-#define FLASH_FLAG_OPERR               ((uint32_t)FLASH_SR_OPERR)  /*!< FLASH operation Error flag                */
-#define FLASH_FLAG_WRPERR              ((uint32_t)FLASH_SR_WRPERR)  /*!< FLASH Write protected error flag          */
-#define FLASH_FLAG_PGAERR              ((uint32_t)FLASH_SR_PGAERR)  /*!< FLASH Programming Alignment error flag    */
-#define FLASH_FLAG_PGPERR              ((uint32_t)FLASH_SR_PGPERR)  /*!< FLASH Programming Parallelism error flag  */
-#define FLASH_FLAG_ERSERR              ((uint32_t)FLASH_SR_ERSERR)  /*!< FLASH Erasing Sequence error flag         */
-#define FLASH_FLAG_BSY                 ((uint32_t)FLASH_SR_BSY)  /*!< FLASH Busy flag                           */ 
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP)    || ((FLAG) == FLASH_FLAG_OPERR)  || \
-                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
-                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_ERSERR) || \
-                                  ((FLAG) == FLASH_FLAG_BSY))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
-  * @{
-  */
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)
-#define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */ 
-#define FLASH_KEY1               ((uint32_t)0x45670123)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
-#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
-#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
- 
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-void FLASH_AdaptiveRealTimeCmd(FunctionalState NewState);
-void FLASH_AdaptiveRealTimeReset(void);
-
-/* FLASH Memory Programming functions *****************************************/   
-void         FLASH_Unlock(void);
-void         FLASH_Lock(void);
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
-
-/* Option Bytes Programming functions *****************************************/ 
-void         FLASH_OB_Unlock(void);
-void         FLASH_OB_Lock(void);
-void         FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
-void         FLASH_OB_RDPConfig(uint8_t OB_RDP);
-void         FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby );
-void         FLASH_OB_BORConfig(uint8_t OB_BOR);
-FLASH_Status FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
-FLASH_Status FLASH_OB_Launch(void);
-uint32_t     FLASH_OB_GetUser(void);
-uint32_t     FLASH_OB_GetWRP(void);
-uint8_t      FLASH_OB_GetRDP(void);
-uint32_t     FLASH_OB_GetBOR(void);
-
-/* Interrupts and flags management functions **********************************/
-void         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void         FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_FLASH_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */