78 lines
5.4 KiB
Markdown
78 lines
5.4 KiB
Markdown
# CH32V003F4P6 — IR Remote / Badge Project Pinout
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Last updated: 2026-06-18
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## MCU
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- **Part:** CH32V003F4P6
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- **Package:** TSSOP20
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- **Core:** QingKe RISC-V2A, 48 MHz
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- **VDD:** 3.3V nominal (2.7–3.6V tolerance), supplied via TLV61070A boost from CR2032
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- **Ports available:** PA1–PA2, PC0–PC7, PD0–PD7 (18 GPIOs total; PD7 shared with NRST)
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## Pin Assignment
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| Pin | Function | Notes |
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|------|------------------------|------------------------------------------------------------------------|
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| PA1 | Indicator LED | Activity/status LED. No documented alternate-function conflicts. |
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| PC0 | OK Button | Input, pull-up, active-low. Also TIM1 CH3 (default remap) — not used as PWM here, fine as plain GPIO. |
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| PC1 | OLED SDA | I2C1 |
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| PC2 | OLED SCL | I2C1 |
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| PC4 | IR Receiver VCC (switched) | GPIO output, drives power gate (high-side) for IR receiver module. Switch off when IR not in use to save current (~200–500 µA continuous draw when powered). |
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| PD1 | SWDIO | Reserved — debug/programming. Do not repurpose. |
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| PD2 | Buzzer (PWM tone) | TIM2-driven PWM, passive piezo. Confirmed working pattern on this chip; caution that heavy use can interfere with programming since PD1 (SWDIO) is adjacent/shared in function. |
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| PD3 | IR Receiver DATA | Input, pull-up. EXTI-capable — use falling-edge interrupt to catch IR bursts rather than polling. Note: TIM1 default-remap CH2 also lives here, unused as PWM in this design. |
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| PD4 | IR TX (PWM, 38 kHz carrier) | TIM1 CH1 (default remap). Drives transistor stage → IR333C-A LED, current-limited per design. |
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| PD5 | Right Button | Input, pull-up. Also candidate wake-from-sleep EXTI source. |
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| PD6 | Left Button | Input, pull-up. |
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| PD7 | NRST | Reserved (shared reset pad). Reconfigure deliberately only if using as deep-sleep wake source — confirm wake mode requirements before repurposing. |
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### Free / unused pins
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PA2, PC3, PC5, PC6, PC7, PD0
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- PC3 was earlier considered for TLV61070A EN, but EN is wired per the power architecture below (see note).
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- PC5/PC7 carry TIM1 full-remap alternate functions (CH1/ETR, CH2) — keep in mind if a second PWM channel is needed later.
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- PA2 has no documented alternate-function entanglement found so far — good candidate for future expansion, similar to PA1.
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## Power Architecture
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- **Cell:** CR2032 coin cell
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- **Boost converter:** TLV61070A (synchronous boost, SOT-23-6, DBV)
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- VIN: direct from CR2032
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- VOUT: 3.3V, set via FB divider **R1 = 560 kΩ, R2 = 100 kΩ** (Vref ≈ 0.5V typical — confirm tolerance in datasheet if accuracy-critical)
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- EN: tie to VIN for always-on main MCU rail (no GPIO needed), OR to a GPIO if this specific converter instance needs to be software-gateable. **Confirm which role this converter instance plays in the final design** — if it's the main MCU supply, EN→VIN is correct; if it's a switchable secondary rail, EN needs a GPIO instead.
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- True load disconnect on EN-low (no body-diode leakage path), unlike most boost converters — useful if this rail ever needs clean shutdown.
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- Light-load power-save mode, ~20 µA Iq from VOUT.
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- **OLED power gating:** No dedicated pin assigned in this pinout. The module has no always-on indicator LED, so the software `0xAE` display-off command may be sufficient on its own. Hardware gating was discussed as an option but not assigned a pin — confirm before layout freeze if hardware gating is still wanted for the OLED, separate from the IR receiver gating on PC4.
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- **IR Receiver power gating:** PC4 drives the IR receiver module's VCC, switched off when not listening for IR, to avoid the ~200–500 µA continuous draw typical of TSOP-style demodulating receivers (exact figure for XL-IRM0038D not independently confirmed — estimated from sibling parts in the same family).
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## Display
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- **Module:** SSD1306, 128×64 (or 128×32 — confirm)
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- **Interface:** I2C1, SDA = PC1, SCL = PC2
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- **Power:** confirm whether gated or tied to main 3.3V rail (see Power Architecture note above)
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## IR Subsystem
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- **TX LED:** Everlight IR333C-A, 940 nm, 5mm through-hole (LCSC C5130)
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- Driven via PD4 (TIM1 CH1 PWM, 38 kHz carrier) through a transistor stage (reservoir capacitor topology / AC-coupled gate protection, per existing design pattern)
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- Current heavily limited per design intent — confirm final resistor/transistor values against IR333C-A datasheet forward voltage/current specs
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- **RX Module:** Xinglight XL-IRM0038D, 38 kHz, SIP-3 through-hole
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- VCC: PC4 (switched)
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- DATA (OUT): PD3, input pull-up, EXTI falling-edge
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- GND: common ground
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- **Pin order not independently verified in this conversation — confirm against XL-IRM0038D datasheet/silkscreen before finalizing layout (SIP-3 IR receiver modules vary in pin order between manufacturers).**
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## Audio
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- **Buzzer:** Passive piezo, PWM tone generation via PD2 (TIM2)
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## Inputs
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- 3x tactile buttons: PC0 (OK), PD5 (Right), PD6 (Left) — all input, internal or external pull-up, active-low, software debounce
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- One of these (suggest PD5) intended as deep-sleep wake-from-EXTI source — confirm in firmware before relying on it for wake behavior, and confirm sleep mode (standby vs. lighter retained-state sleep) since wake mechanism differs between modes on this chip.
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