CH32V003F4P6 — IR Remote / Badge Project Pinout

Last updated: 2026-06-18

MCU

Part: CH32V003F4P6
Package: TSSOP20
Core: QingKe RISC-V2A, 48 MHz
VDD: 3.3V nominal (2.7–3.6V tolerance), supplied via TLV61070A boost from CR2032
Ports available: PA1–PA2, PC0–PC7, PD0–PD7 (18 GPIOs total; PD7 shared with NRST)

Pin	Function	Notes
PA1	Indicator LED	Activity/status LED. No documented alternate-function conflicts.
PC0	OK Button	Input, pull-up, active-low. Also TIM1 CH3 (default remap) — not used as PWM here, fine as plain GPIO.
PC1	OLED SDA	I2C1
PC2	OLED SCL	I2C1
PC4	IR Receiver VCC (switched)	GPIO output, drives power gate (high-side) for IR receiver module. Switch off when IR not in use to save current (~200–500 µA continuous draw when powered).
PD1	SWDIO	Reserved — debug/programming. Do not repurpose.
PD2	Buzzer (PWM tone)	TIM2-driven PWM, passive piezo. Confirmed working pattern on this chip; caution that heavy use can interfere with programming since PD1 (SWDIO) is adjacent/shared in function.
PD3	IR Receiver DATA	Input, pull-up. EXTI-capable — use falling-edge interrupt to catch IR bursts rather than polling. Note: TIM1 default-remap CH2 also lives here, unused as PWM in this design.
PD4	IR TX (PWM, 38 kHz carrier)	TIM1 CH1 (default remap). Drives transistor stage → IR333C-A LED, current-limited per design.
PD5	Right Button	Input, pull-up. Also candidate wake-from-sleep EXTI source.
PD6	Left Button	Input, pull-up.
PD7	NRST	Reserved (shared reset pad). Reconfigure deliberately only if using as deep-sleep wake source — confirm wake mode requirements before repurposing.

PA2, PC3, PC5, PC6, PC7, PD0

PC3 was earlier considered for TLV61070A EN, but EN is wired per the power architecture below (see note).
PC5/PC7 carry TIM1 full-remap alternate functions (CH1/ETR, CH2) — keep in mind if a second PWM channel is needed later.
PA2 has no documented alternate-function entanglement found so far — good candidate for future expansion, similar to PA1.

Cell: CR2032 coin cell
Boost converter: TLV61070A (synchronous boost, SOT-23-6, DBV)
- VIN: direct from CR2032
- VOUT: 3.3V, set via FB divider R1 = 560 kΩ, R2 = 100 kΩ (Vref ≈ 0.5V typical — confirm tolerance in datasheet if accuracy-critical)
- EN: tie to VIN for always-on main MCU rail (no GPIO needed), OR to a GPIO if this specific converter instance needs to be software-gateable. Confirm which role this converter instance plays in the final design — if it's the main MCU supply, EN→VIN is correct; if it's a switchable secondary rail, EN needs a GPIO instead.
- True load disconnect on EN-low (no body-diode leakage path), unlike most boost converters — useful if this rail ever needs clean shutdown.
- Light-load power-save mode, ~20 µA Iq from VOUT.
OLED power gating: No dedicated pin assigned in this pinout. The module has no always-on indicator LED, so the software 0xAE display-off command may be sufficient on its own. Hardware gating was discussed as an option but not assigned a pin — confirm before layout freeze if hardware gating is still wanted for the OLED, separate from the IR receiver gating on PC4.
IR Receiver power gating: PC4 drives the IR receiver module's VCC, switched off when not listening for IR, to avoid the ~200–500 µA continuous draw typical of TSOP-style demodulating receivers (exact figure for XL-IRM0038D not independently confirmed — estimated from sibling parts in the same family).

Module: SSD1306, 128×64 (or 128×32 — confirm)
Interface: I2C1, SDA = PC1, SCL = PC2
Power: confirm whether gated or tied to main 3.3V rail (see Power Architecture note above)

TX LED: Everlight IR333C-A, 940 nm, 5mm through-hole (LCSC C5130)
- Driven via PD4 (TIM1 CH1 PWM, 38 kHz carrier) through a transistor stage (reservoir capacitor topology / AC-coupled gate protection, per existing design pattern)
- Current heavily limited per design intent — confirm final resistor/transistor values against IR333C-A datasheet forward voltage/current specs
RX Module: Xinglight XL-IRM0038D, 38 kHz, SIP-3 through-hole
- VCC: PC4 (switched)
- DATA (OUT): PD3, input pull-up, EXTI falling-edge
- GND: common ground
- Pin order not independently verified in this conversation — confirm against XL-IRM0038D datasheet/silkscreen before finalizing layout (SIP-3 IR receiver modules vary in pin order between manufacturers).

3x tactile buttons: PC0 (OK), PD5 (Right), PD6 (Left) — all input, internal or external pull-up, active-low, software debounce
One of these (suggest PD5) intended as deep-sleep wake-from-EXTI source — confirm in firmware before relying on it for wake behavior, and confirm sleep mode (standby vs. lighter retained-state sleep) since wake mechanism differs between modes on this chip.