mirror of https://github.com/g4klx/MMDVM.git
Use the LPTMR to triger the ADC from an external oscillator.
This commit is contained in:
Jonathan Naylor
parent
cd2042aa9b
commit
df202e19df
58
IOTeensy.cpp
58
IOTeensy.cpp
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@ -22,7 +22,11 @@
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#if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
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#if defined(EXTERNAL_OSC)
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#define PIN_LED 3
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#else
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#define PIN_LED 13
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#endif
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#define PIN_COS 4
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#define PIN_PTT 5
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#define PIN_COSLED 6
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@ -50,21 +54,6 @@ extern "C" {
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io.interrupt(1U);
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}
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#endif
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#if defined(EXTERNAL_OSC)
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void ftm0_isr()
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{
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FTM0_CNT = 0; // Reset count value
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if ((FTM0_SC & FTM_SC_TOF) == FTM_SC_TOF) // Read the timer overflow flag (TOF in FTM0_SC)
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FTM0_SC &= ~FTM_SC_TOF; // If set, clear overflow flag
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// Kick off the ADCs with interrupt at the end of conversion
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ADC0_SC1A = ADC_SC1_AIEN | PIN_ADC;
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#if defined(SEND_RSSI_DATA)
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ADC1_SC1A = ADC_SC1_AIEN | PIN_RSSI;
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#endif
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}
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#endif
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}
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void CIO::initInt()
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@ -99,11 +88,7 @@ void CIO::startInt()
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ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | ADC_CFG1_MODE(1) |
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ADC_CFG1_ADLSMP; // Single-ended 12 bits, long sample time
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ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
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#if defined(EXTERNAL_OSC)
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ADC0_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger
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#else
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ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger
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#endif
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ADC0_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
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while ((ADC0_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration
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@ -113,10 +98,7 @@ void CIO::startInt()
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sum0 = (sum0 / 2U) | 0x8000U;
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ADC0_PG = sum0;
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#if !defined(EXTERNAL_OSC)
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ADC0_SC1A = ADC_SC1_AIEN | PIN_ADC; // Enable ADC interrupt, use A0
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#endif
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NVIC_ENABLE_IRQ(IRQ_ADC0);
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#if defined(SEND_RSSI_DATA)
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@ -125,11 +107,7 @@ void CIO::startInt()
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ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | ADC_CFG1_MODE(1) |
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ADC_CFG1_ADLSMP; // Single-ended 12 bits, long sample time
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ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
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#if defined(EXTERNAL_OSC)
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ADC1_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger
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#else
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ADC1_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger
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#endif
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ADC1_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
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while ((ADC1_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration
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@ -139,21 +117,27 @@ void CIO::startInt()
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sum1 = (sum1 / 2U) | 0x8000U;
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ADC1_PG = sum1;
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#if !defined(EXTERNAL_OSC)
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ADC1_SC1A = ADC_SC1_AIEN | PIN_RSSI; // Enable ADC interrupt, use A2
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#endif
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NVIC_ENABLE_IRQ(IRQ_ADC1);
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#endif
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#if defined(EXTERNAL_OSC)
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// Set up for an external oscillator input
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SIM_SCGC6 |= SIM_SCGC6_FTM0;
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FTM0_MODE = FTM_MODE_WPDIS | FTM_MODE_FTMEN;
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FTM0_MOD = EXTERNAL_OSC / 24000;
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FTM0_CNTIN = 0;
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FTM0_SC = FTM_SC_TOIE | FTM_SC_CLKS(3); // External clock, overflow interrupts, no prescaling
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NVIC_ENABLE_IRQ(IRQ_FTM0);
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SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
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LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
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LPTMR0_CMR = EXTERNAL_OSC / 24000;
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LPTMR0_CSR = LPTMR_CSR_TIE | LPTMR_CSR_TPS(2) | // Interrupt, counter, input=Alt2, free running mode, enable
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LPTMR_CSR_TFC | LPTMR_CSR_TMS |
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LPTMR_CSR_TEN;
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CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
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// Set ADC0 to trigger from the LPTMR
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SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | SIM_SOPT7_ADC0TRGSEL(14);
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#if defined(SEND_RSSI_DATA)
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// Set ADC1 to trigger from the LPTMR
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SIM_SOPT7 |= SIM_SOPT7_ADC1ALTTRGEN | SIM_SOPT7_ADC1TRGSEL(14);
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#endif
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NVIC_ENABLE_IRQ(IRQ_LPTMR);
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#else
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// Setup PDB for ADC0 (and ADC1) at 24 kHz
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SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock
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@ -161,7 +145,7 @@ void CIO::startInt()
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PDB0_IDLY = 0; // Interrupt delay
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PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0
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#if defined(SEND_RSSI_DATA)
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PDB0_CH1C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-t9rigger for ADC1
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PDB0_CH1C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC1
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#endif
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PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode
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PDB_SC_PDBIE | PDB_SC_CONT | PDB_SC_LDOK; // No prescaling
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