mirror of https://github.com/g4klx/MMDVM.git
Fix RX interrupt flag being cleared on the wrong USART in STMUART.
handleIRQ() hardcoded USART1 when clearing the RXNE pending bit, so on boards where the repeater/display UART is not USART1 (Nucleo, Discovery, F767, UART5-based boards) the flag was cleared on the wrong peripheral. Use the m_usart member, matching the TXE handling below. Also fix flush(): it passed a flag constant to USART_GetITStatus and span while TXE was set, which returns immediately since TXE indicates the data register is already empty. Wait for the software TX FIFO to drain and then for the TC flag, which indicates the shift register has actually emptied.
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57e692ad8c
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10
STMUART.cpp
10
STMUART.cpp
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@ -61,7 +61,7 @@ void CSTMUART::handleIRQ()
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if (USART_GetITStatus(m_usart, USART_IT_RXNE)) {
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if (USART_GetITStatus(m_usart, USART_IT_RXNE)) {
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if(!m_rxFifo.isFull())
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if(!m_rxFifo.isFull())
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m_rxFifo.put((uint8_t) USART_ReceiveData(m_usart));
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m_rxFifo.put((uint8_t) USART_ReceiveData(m_usart));
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USART_ClearITPendingBit(USART1, USART_IT_RXNE);
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USART_ClearITPendingBit(m_usart, USART_IT_RXNE);
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}
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}
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if (USART_GetITStatus(m_usart, USART_IT_TXE)) {
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if (USART_GetITStatus(m_usart, USART_IT_TXE)) {
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@ -82,8 +82,12 @@ void CSTMUART::flush()
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if(m_usart == NULL)
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if(m_usart == NULL)
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return;
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return;
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// wait until the TXE shows the shift register is empty
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// wait until the TX FIFO has drained
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while (USART_GetITStatus(m_usart, USART_FLAG_TXE))
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while (!m_txFifo.isEmpty())
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;
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// wait until the TC flag shows the shift register is empty
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while (USART_GetFlagStatus(m_usart, USART_FLAG_TC) == RESET)
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;
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;
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}
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}
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