Superminaren
/
MMDVM
mirror of https://github.com/g4klx/MMDVM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Reorganise the code slightly.

This commit is contained in:
Jonathan Naylor 2016-11-30 09:42:10 +00:00 committed by GitHub
parent 79440ca32d
commit 6d383332e1
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
IOTeensy.cpp
View File

@ -75,6 +75,10 @@ void CIO::initInt()
void CIO::startInt() void CIO::startInt()
{ {
// Initialise the DAC
SIM_SCGC2 |= SIM_SCGC2_DAC0;
DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 1.2V VDDA is DACREF_2
// Initialise ADC0 // Initialise ADC0
SIM_SCGC6 |= SIM_SCGC6_ADC0; SIM_SCGC6 |= SIM_SCGC6_ADC0;
ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
@ -118,18 +122,18 @@ void CIO::startInt()
#endif #endif
#if defined(EXTERNAL_OSC) #if defined(EXTERNAL_OSC)
// Set ADC0 to trigger from the LPTMR at 24 kHz
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN |
SIM_SOPT7_ADC0TRGSEL(14);
CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
SIM_SCGC5 |= SIM_SCGC5_LPTIMER; SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = EXTERNAL_OSC / 24000; LPTMR0_CMR = EXTERNAL_OSC / 24000;
LPTMR0_CSR = LPTMR_CSR_TIE | LPTMR_CSR_TPS(2) | // Interrupt, counter, input=Alt2, free running mode, enable LPTMR0_CSR = LPTMR_CSR_TIE | LPTMR_CSR_TPS(2) | // Interrupt, counter, input=Alt2, free running mode, enable
LPTMR_CSR_TFC | LPTMR_CSR_TMS | LPTMR_CSR_TFC | LPTMR_CSR_TMS |
LPTMR_CSR_TEN; LPTMR_CSR_TEN;
CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
// Set ADC0 to trigger from the LPTMR
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN |
SIM_SOPT7_ADC0TRGSEL(14);
#else #else
// Setup PDB for ADC0 at 24 kHz // Setup PDB for ADC0 at 24 kHz
SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock
@ -141,10 +145,6 @@ void CIO::startInt()
PDB0_SC |= PDB_SC_SWTRIG; // Software trigger (reset and restart counter) PDB0_SC |= PDB_SC_SWTRIG; // Software trigger (reset and restart counter)
#endif #endif
// Initialise the DAC
SIM_SCGC2 |= SIM_SCGC2_DAC0;
DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 1.2V VDDA is DACREF_2
digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW); digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW);
digitalWrite(PIN_COSLED, LOW); digitalWrite(PIN_COSLED, LOW);
digitalWrite(PIN_LED, HIGH); digitalWrite(PIN_LED, HIGH);