From 6d383332e1f6ed2aa9a7ed3c2990aa4e522c88ed Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 30 Nov 2016 09:42:10 +0000 Subject: [PATCH] Reorganise the code slightly. --- IOTeensy.cpp | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 6f629a6..ae143a7 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -75,6 +75,10 @@ void CIO::initInt() void CIO::startInt() { + // Initialise the DAC + SIM_SCGC2 |= SIM_SCGC2_DAC0; + DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 1.2V VDDA is DACREF_2 + // Initialise ADC0 SIM_SCGC6 |= SIM_SCGC6_ADC0; ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time @@ -118,18 +122,18 @@ void CIO::startInt() #endif #if defined(EXTERNAL_OSC) + // Set ADC0 to trigger from the LPTMR at 24 kHz + SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | + SIM_SOPT7_ADC0TRGSEL(14); + + CORE_PIN13_CONFIG = PORT_PCR_MUX(3); + SIM_SCGC5 |= SIM_SCGC5_LPTIMER; LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter LPTMR0_CMR = EXTERNAL_OSC / 24000; LPTMR0_CSR = LPTMR_CSR_TIE | LPTMR_CSR_TPS(2) | // Interrupt, counter, input=Alt2, free running mode, enable LPTMR_CSR_TFC | LPTMR_CSR_TMS | LPTMR_CSR_TEN; - - CORE_PIN13_CONFIG = PORT_PCR_MUX(3); - - // Set ADC0 to trigger from the LPTMR - SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | - SIM_SOPT7_ADC0TRGSEL(14); #else // Setup PDB for ADC0 at 24 kHz SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock @@ -141,10 +145,6 @@ void CIO::startInt() PDB0_SC |= PDB_SC_SWTRIG; // Software trigger (reset and restart counter) #endif - // Initialise the DAC - SIM_SCGC2 |= SIM_SCGC2_DAC0; - DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 1.2V VDDA is DACREF_2 - digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW); digitalWrite(PIN_COSLED, LOW); digitalWrite(PIN_LED, HIGH);