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Add submodules for F4/F7 libs

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Luca Marchesano
2018-06-29 09:31:01 +02:00
committed by GitHub
parent 047229d6d3
commit 0833dba9bd
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STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/misc.h
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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/* Exported types ------------------------------------------------------------*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be an enumerator of @ref IRQn_Type
enumeration (For the complete STM32 Devices IRQ Channels
list, please refer to stm32f7xx.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
A lower priority value indicates a higher priority */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
A lower priority value indicates a higher priority */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup MISC_Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)SRAM1_BASE)
#define NVIC_VectTab_FLASH ((uint32_t)FLASH_BASE)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup MISC_System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)SCB_SCR_SEVONPEND_Msk)
#define NVIC_LP_SLEEPDEEP ((uint8_t)SCB_SCR_SLEEPDEEP_Msk)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)SCB_SCR_SLEEPONEXIT_Msk)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup MISC_Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @defgroup MISC_SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
#if (__MPU_PRESENT == 1)
void MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
void MPU_Disable(void);
void MPU_Enable(uint32_t MPU_Control);
#endif /* __MPU_PRESENT */
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_adc.h
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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_ADC_H
#define __STM32F7xx_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
This parameter can be a value of @ref ADC_resolution */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
is performed in Scan (multichannels)
or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
is performed in Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
enable the trigger of a regular group.
This parameter can be a value of
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
the start of conversion of a regular group.
This parameter can be a value of
@ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
is left or right. This parameter can be
a value of @ref ADC_data_align */
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
that will be done using the sequencer for
regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @brief ADC Common Init structure definition
*/
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
independent or multi mode.
This parameter can be a value of @ref ADC_Common_mode */
uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
to the ADC. The clock is common for all the ADCs.
This parameter can be a value of @ref ADC_Prescaler */
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
mode for multi ADC mode.
This parameter can be a value of
@ref ADC_Direct_memory_access_mode_for_multi_mode */
uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of
@ref ADC_delay_between_2_sampling_phases */
}ADC_CommonInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (IS_ADC_ALL_INSTANCE(PERIPH))
/** @defgroup ADC_Common_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
#define ADC_DualMode_Interl ((uint32_t)0x00000007)
#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
((MODE) == ADC_DualMode_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult) || \
((MODE) == ADC_DualMode_Interl) || \
((MODE) == ADC_DualMode_AlterTrig) || \
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
((MODE) == ADC_TripleMode_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult) || \
((MODE) == ADC_TripleMode_Interl) || \
((MODE) == ADC_TripleMode_AlterTrig))
/**
* @}
*/
/** @defgroup ADC_Prescaler
* @{
*/
#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
((PRESCALER) == ADC_Prescaler_Div4) || \
((PRESCALER) == ADC_Prescaler_Div6) || \
((PRESCALER) == ADC_Prescaler_Div8))
/**
* @}
*/
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
* @{
*/
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
((MODE) == ADC_DMAAccessMode_1) || \
((MODE) == ADC_DMAAccessMode_2) || \
((MODE) == ADC_DMAAccessMode_3))
/**
* @}
*/
/** @defgroup ADC_delay_between_2_sampling_phases
* @{
*/
#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)ADC_CCR_DELAY_2)
#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)ADC_CCR_DELAY_3)
#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)ADC_CCR_DELAY)
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
/**
* @}
*/
/** @defgroup ADC_resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000)
#define ADC_Resolution_10b ((uint32_t)ADC_CR1_RES_0)
#define ADC_Resolution_8b ((uint32_t)ADC_CR1_RES_1)
#define ADC_Resolution_6b ((uint32_t)ADC_CR1_RES)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)ADC_CR2_EXTEN)
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define ADC_Software_Start ((uint32_t)ADC_CR2_EXTSEL + 1)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11) || \
((REGTRIG) == ADC_Software_Start))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)ADC_CR2_ALIGN)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint32_t)0x00000000)
#define ADC_Channel_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_Channel_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define ADC_Channel_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define ADC_Channel_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define ADC_Channel_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define ADC_Channel_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define ADC_Channel_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define ADC_Channel_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define ADC_Channel_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
#define ADC_Channel_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
#define ADC_Channel_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define ADC_Channel_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
#define ADC_Channel_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define ADC_Channel_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define ADC_Channel_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define ADC_Channel_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define ADC_Channel_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define ADC_Channel_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || \
((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || \
((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || \
((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || \
((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || \
((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || \
((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || \
((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || \
((CHANNEL) == ADC_Channel_17) || \
((CHANNEL) == ADC_Channel_18))
/**
* @}
*/
/** @defgroup ADC_sampling_times
* @{
*/
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_15Cycles ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SampleTime_28Cycles ((uint32_t)ADC_SMPR1_SMP10_1)
#define ADC_SampleTime_56Cycles ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
#define ADC_SampleTime_84Cycles ((uint32_t)ADC_SMPR1_SMP10_2)
#define ADC_SampleTime_112Cycles ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define ADC_SampleTime_144Cycles ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define ADC_SampleTime_480Cycles ((uint32_t)ADC_SMPR1_SMP10)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
((TIME) == ADC_SampleTime_15Cycles) || \
((TIME) == ADC_SampleTime_28Cycles) || \
((TIME) == ADC_SampleTime_56Cycles) || \
((TIME) == ADC_SampleTime_84Cycles) || \
((TIME) == ADC_SampleTime_112Cycles) || \
((TIME) == ADC_SampleTime_144Cycles) || \
((TIME) == ADC_SampleTime_480Cycles))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)
#define ADC_ExternalTrigInjecConv_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
#define ADC_ExternalTrigInjecConv_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define ADC_ExternalTrigInjecConv_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_ExternalTrigInjecConv_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_TRGO2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO))
/**
* @}
*/
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)ADC_CR1_AWDEN)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0205)
#define ADC_IT_AWD ((uint16_t)0x0106)
#define ADC_IT_JEOC ((uint16_t)0x0407)
#define ADC_IT_OVR ((uint16_t)0x201A)
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
#define ADC_FLAG_OVR ((uint8_t)0x20)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || \
((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT) || \
((FLAG)== ADC_FLAG_OVR))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
/* Temperature Sensor, Vrefint and VBAT management functions ******************/
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
void ADC_VBATCmd(FunctionalState NewState);
/* Regular Channels Configuration functions ***********************************/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetMultiModeConversionValue(void);
/* Regular Channels DMA Configuration functions *******************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
/* Injected channels Configuration functions **********************************/
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F7xx_ADC_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_dac.h
+277
View File
@@ -0,0 +1,277 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_DAC_H
#define __STM32F7xx_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignement
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || ((IT) == DAC_IT_DMAUDR2) )
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || ((FLAG) == DAC_FLAG_DMAUDR2))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the DAC configuration to the default reset state *****/
void DAC_DeInit(void);
/* DAC channels configuration: trigger, output buffer, data format functions */
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
/* DMA management functions ***************************************************/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F7xx_DAC_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_flash.h
+366
View File
@@ -0,0 +1,366 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_FLASH_H
#define __STM32F7xx_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_ERS,
FLASH_ERROR_PGP,
FLASH_ERROR_PGA,
FLASH_ERROR_WRP,
FLASH_ERROR_PROGRAM,
FLASH_ERROR_OPERATION,
FLASH_COMPLETE
}FLASH_Status;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
#define FLASH_Latency_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
#define FLASH_Latency_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
#define FLASH_Latency_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
#define FLASH_Latency_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
#define FLASH_Latency_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
#define FLASH_Latency_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
#define FLASH_Latency_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
#define FLASH_Latency_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
#define FLASH_Latency_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
#define FLASH_Latency_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
#define FLASH_Latency_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2) || \
((LATENCY) == FLASH_Latency_3) || \
((LATENCY) == FLASH_Latency_4) || \
((LATENCY) == FLASH_Latency_5) || \
((LATENCY) == FLASH_Latency_6) || \
((LATENCY) == FLASH_Latency_7) || \
((LATENCY) == FLASH_Latency_8) || \
((LATENCY) == FLASH_Latency_9) || \
((LATENCY) == FLASH_Latency_10) || \
((LATENCY) == FLASH_Latency_11) || \
((LATENCY) == FLASH_Latency_12) || \
((LATENCY) == FLASH_Latency_13) || \
((LATENCY) == FLASH_Latency_14) || \
((LATENCY) == FLASH_Latency_15))
/**
* @}
*/
/** @defgroup FLASH_Voltage_Range
* @{
*/
#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
((RANGE) == VoltageRange_2) || \
((RANGE) == VoltageRange_3) || \
((RANGE) == VoltageRange_4))
/**
* @}
*/
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
#define FLASH_Sector_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_Sector_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_Sector_2 ((uint32_t)2) /*!< Sector Number 2 */
#define FLASH_Sector_3 ((uint32_t)3) /*!< Sector Number 3 */
#define FLASH_Sector_4 ((uint32_t)4) /*!< Sector Number 4 */
#define FLASH_Sector_5 ((uint32_t)5) /*!< Sector Number 5 */
#define FLASH_Sector_6 ((uint32_t)6) /*!< Sector Number 6 */
#define FLASH_Sector_7 ((uint32_t)7) /*!< Sector Number 7 */
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_Sector_0 ((uint32_t)0x00010000) /*!< Write protection of Sector0 */
#define OB_WRP_Sector_1 ((uint32_t)0x00020000) /*!< Write protection of Sector1 */
#define OB_WRP_Sector_2 ((uint32_t)0x00040000) /*!< Write protection of Sector2 */
#define OB_WRP_Sector_3 ((uint32_t)0x00080000) /*!< Write protection of Sector3 */
#define OB_WRP_Sector_4 ((uint32_t)0x00100000) /*!< Write protection of Sector4 */
#define OB_WRP_Sector_5 ((uint32_t)0x00200000) /*!< Write protection of Sector5 */
#define OB_WRP_Sector_6 ((uint32_t)0x00400000) /*!< Write protection of Sector6 */
#define OB_WRP_Sector_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */
#define OB_WRP_Sector_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
#define IS_OB_WRP(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_Read_Protection
* @{
*/
#define OB_RDP_Level_0 ((uint8_t)0xAA)
#define OB_RDP_Level_1 ((uint8_t)0x55)
#define OB_RDP_Level_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
((LEVEL) == OB_RDP_Level_1))/*||\
((LEVEL) == OB_RDP_Level_2))*/
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
* @{
*/
#define OB_WWDG_SW ((uint32_t)0x10) /*!< Software WWDG selected */
#define OB_WWDG_HW ((uint32_t)0x00) /*!< Hardware WWDG selected */
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
* @{
*/
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */
#define IS_OB_IWDG_STOP_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_STOP_FREEZE) || ((SOURCE) == OB_IWDG_STOP_ACTIVE))
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
* @{
*/
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */
#define IS_OB_IWDG_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_STDBY_FREEZE) || ((SOURCE) == OB_IWDG_STDBY_ACTIVE))
/**
* @}
*/
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL3 ((uint32_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint32_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint32_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint32_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
/**
* @}
*/
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10) /*!< Boot 0 Address configuration */
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20) /*!< Boot 1 Address configuration */
#define IS_OB_BOOT_OPTION(BOOT) (((BOOT) == OPTIONBYTE_BOOTADDR_0) || \
((BOOT) == OPTIONBYTE_BOOTADDR_1))
/**
* @}
*/
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000) /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040) /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080) /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000) /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */
#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM) || \
((ADDRESS) == OB_BOOTADDR_SYSTEM) || \
((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \
((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \
((ADDRESS) == OB_BOOTADDR_DTCM_RAM) || \
((ADDRESS) == OB_BOOTADDR_SRAM1) || \
((ADDRESS) == OB_BOOTADDR_SRAM2))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_EOP ((uint32_t)FLASH_CR_EOPIE) /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)FLASH_CR_ERRIE) /*!< Error Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_EOP ((uint32_t)FLASH_SR_EOP) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_OPERR ((uint32_t)FLASH_SR_OPERR) /*!< FLASH operation Error flag */
#define FLASH_FLAG_WRPERR ((uint32_t)FLASH_SR_WRPERR) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR ((uint32_t)FLASH_SR_PGAERR) /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR ((uint32_t)FLASH_SR_PGPERR) /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_ERSERR ((uint32_t)FLASH_SR_ERSERR) /*!< FLASH Erasing Sequence error flag */
#define FLASH_FLAG_BSY ((uint32_t)FLASH_SR_BSY) /*!< FLASH Busy flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_ERSERR) || \
((FLAG) == FLASH_FLAG_BSY))
/**
* @}
*/
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* FLASH Interface configuration functions ************************************/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
void FLASH_AdaptiveRealTimeCmd(FunctionalState NewState);
void FLASH_AdaptiveRealTimeReset(void);
/* FLASH Memory Programming functions *****************************************/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
/* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
void FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby );
void FLASH_OB_BORConfig(uint8_t OB_BOR);
FLASH_Status FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
FLASH_Status FLASH_OB_Launch(void);
uint32_t FLASH_OB_GetUser(void);
uint32_t FLASH_OB_GetWRP(void);
uint8_t FLASH_OB_GetRDP(void);
uint32_t FLASH_OB_GetBOR(void);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_FLASH_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_gpio.h
+491
View File
@@ -0,0 +1,491 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_GPIO_H
#define __STM32F7xx_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
#if defined(STM32F767xx)
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG) || \
((PERIPH) == GPIOH) || \
((PERIPH) == GPIOI) || \
((PERIPH) == GPIOJ) || \
((PERIPH) == GPIOK))
#elif defined(STM32F722xx)
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG) || \
((PERIPH) == GPIOH) || \
((PERIPH) == GPIOI))
#endif
/**
* @brief GPIO Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
/**
* @brief GPIO Output type enumeration
*/
typedef enum
{
GPIO_OType_PP = 0x00,
GPIO_OType_OD = 0x01
}GPIOOType_TypeDef;
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
/**
* @brief GPIO Output Maximum frequency enumeration
*/
typedef enum
{
GPIO_Low_Speed = 0x00, /*!< Low speed */
GPIO_Medium_Speed = 0x01, /*!< Medium speed */
GPIO_Fast_Speed = 0x02, /*!< Fast speed */
GPIO_High_Speed = 0x03 /*!< High speed */
}GPIOSpeed_TypeDef;
/* Add legacy definition */
//#define GPIO_Speed_2MHz GPIO_Low_Speed
//#define GPIO_Speed_25MHz GPIO_Medium_Speed
//#define GPIO_Speed_50MHz GPIO_Fast_Speed
//#define GPIO_Speed_100MHz GPIO_High_Speed
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
/**
* @brief GPIO Configuration PullUp PullDown enumeration
*/
typedef enum
{
GPIO_PuPd_NOPULL = 0x00,
GPIO_PuPd_UP = 0x01,
GPIO_PuPd_DOWN = 0x02
}GPIOPuPd_TypeDef;
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
((PUPD) == GPIO_PuPd_DOWN))
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIOOType_TypeDef */
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIOPuPd_TypeDef */
}GPIO_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/**
* @}
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF_TIM2 GPIO_AF1_TIM2
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF_USART1 GPIO_AF7_USART1
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF_USART2 GPIO_AF7_USART2
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF_USART3 GPIO_AF7_USART3
#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF_UART5 GPIO_AF8_UART5
#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F767xx)
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F756xx || STM32F746xx */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F767xx)
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F756xx || STM32F746xx */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
/**
* @}
*/
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
* @{
*/
#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F767xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))
#elif defined(STM32F745xx) || defined(STM32F722xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F756xx || STM32F746xx */
/**
* @}
*/
/** @defgroup GPIO_Legacy
* @{
*/
#define GPIO_Mode_AIN GPIO_Mode_AN
#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the GPIO configuration to the default reset state ****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
/* Initialization and Configuration functions *********************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/* GPIO Read and Write functions **********************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/* GPIO Alternate functions configuration function ****************************/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F7xx_GPIO_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_pwr.h
+247
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@@ -0,0 +1,247 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_PWR_H
#define __STM32F7xx_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level
* @{
*/
#define PWR_PVDLevel_0 PWR_CR1_PLS_LEV0
#define PWR_PVDLevel_1 PWR_CR1_PLS_LEV1
#define PWR_PVDLevel_2 PWR_CR1_PLS_LEV2
#define PWR_PVDLevel_3 PWR_CR1_PLS_LEV3
#define PWR_PVDLevel_4 PWR_CR1_PLS_LEV4
#define PWR_PVDLevel_5 PWR_CR1_PLS_LEV5
#define PWR_PVDLevel_6 PWR_CR1_PLS_LEV6
#define PWR_PVDLevel_7 PWR_CR1_PLS_LEV7
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_STOP_mode
* @{
*/
#define PWR_MainRegulator_ON ((uint32_t)0x00000000)
#define PWR_LowPowerRegulator_ON PWR_CR1_LPDS
/* --- PWR_Legacy ---*/
#define PWR_Regulator_ON PWR_MainRegulator_ON
#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_ON))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_UnderDrive_mode
* @{
*/
#define PWR_MainRegulator_UnderDrive_ON PWR_CR1_MRUDS
#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
/**
* @}
*/
/** @defgroup PWR_Wake_Up_Pin
* @{
*/
#define PWR_WakeUp_Pin1 PWR_CSR2_EWUP1 /*!< Wakeup Pin PA0 */
#define PWR_WakeUp_Pin2 PWR_CSR2_EWUP2 /*!< Wakeup Pin PA2 */
#define PWR_WakeUp_Pin3 PWR_CSR2_EWUP3 /*!< Wakeup Pin PC1 */
#define PWR_WakeUp_Pin4 PWR_CSR2_EWUP4 /*!< Wakeup Pin PC13 */
#define PWR_WakeUp_Pin5 PWR_CSR2_EWUP5 /*!< Wakeup Pin PI8 */
#define PWR_WakeUp_Pin6 PWR_CSR2_EWUP6 /*!< Wakeup Pin PI11 */
#define PWR_WakeUp_Pin1_RisingEdge PWR_CSR2_EWUP1 /*!< Wakeup Pin PA0 with risig edge */
#define PWR_WakeUp_Pin2_RisingEdge PWR_CSR2_EWUP2 /*!< Wakeup Pin PA2 with risig edge */
#define PWR_WakeUp_Pin3_RisingEdge PWR_CSR2_EWUP3 /*!< Wakeup Pin PC1 with risig edge */
#define PWR_WakeUp_Pin4_RisingEdge PWR_CSR2_EWUP4 /*!< Wakeup Pin PC13 with risig edge */
#define PWR_WakeUp_Pin5_RisingEdge PWR_CSR2_EWUP5 /*!< Wakeup Pin PI8 with risig edge */
#define PWR_WakeUp_Pin6_RisingEdge PWR_CSR2_EWUP6 /*!< Wakeup Pin PI11 with risig edge */
#define PWR_WakeUp_Pin1_FallingEdge (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) /*!< Wakeup Pin PA0 with falling edge */
#define PWR_WakeUp_Pin2_FallingEdge (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) /*!< Wakeup Pin PA2 with falling edge */
#define PWR_WakeUp_Pin3_FallingEdge (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) /*!< Wakeup Pin PC1 with falling edge */
#define PWR_WakeUp_Pin4_FallingEdge (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) /*!< Wakeup Pin PC13 with falling edge */
#define PWR_WakeUp_Pin5_FallingEdge (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) /*!< Wakeup Pin PI8 with falling edge */
#define PWR_WakeUp_Pin6_FallingEdge (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) /*!< Wakeup Pin PI11 with falling edge */
#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WakeUp_Pin1) || \
((__PIN__) == PWR_WakeUp_Pin2) || \
((__PIN__) == PWR_WakeUp_Pin3) || \
((__PIN__) == PWR_WakeUp_Pin4) || \
((__PIN__) == PWR_WakeUp_Pin5) || \
((__PIN__) == PWR_WakeUp_Pin6) || \
((__PIN__) == PWR_WakeUp_Pin1_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin2_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin3_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin4_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin5_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin6_RisingEdge) || \
((__PIN__) == PWR_WakeUp_Pin1_FallingEdge) || \
((__PIN__) == PWR_WakeUp_Pin2_FallingEdge) || \
((__PIN__) == PWR_WakeUp_Pin3_FallingEdge) || \
((__PIN__) == PWR_WakeUp_Pin4_FallingEdge) || \
((__PIN__) == PWR_WakeUp_Pin5_FallingEdge) || \
((__PIN__) == PWR_WakeUp_Pin6_FallingEdge))
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)PWR_CR1_VOS)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)PWR_CR1_VOS_1)
#define PWR_Regulator_Voltage_Scale3 ((uint32_t)PWR_CR1_VOS_0)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU1 (PWR_CSR2_WUPF1 | 0x80000000)
#define PWR_FLAG_WU2 (PWR_CSR2_WUPF2 | 0x80000000)
#define PWR_FLAG_WU3 (PWR_CSR2_WUPF3 | 0x80000000)
#define PWR_FLAG_WU4 (PWR_CSR2_WUPF4 | 0x80000000)
#define PWR_FLAG_WU5 (PWR_CSR2_WUPF5 | 0x80000000)
#define PWR_FLAG_WU6 (PWR_CSR2_WUPF6 | 0x80000000)
#define PWR_FLAG_SB PWR_CSR1_SBF
#define PWR_FLAG_PVDO PWR_CSR1_PVDO
#define PWR_FLAG_BRR PWR_CSR1_BRR
#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY
#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY
/* --- FLAG Legacy ---*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU1) || \
((FLAG) == PWR_FLAG_WU2) || \
((FLAG) == PWR_FLAG_WU3) || \
((FLAG) == PWR_FLAG_WU4) || \
((FLAG) == PWR_FLAG_WU5) || \
((FLAG) == PWR_FLAG_WU6) || \
((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU1) || \
((FLAG) == PWR_FLAG_WU2) || \
((FLAG) == PWR_FLAG_WU3) || \
((FLAG) == PWR_FLAG_WU4) || \
((FLAG) == PWR_FLAG_WU5) || \
((FLAG) == PWR_FLAG_WU6) || \
((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_UDRDY))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the PWR configuration to the default reset state ******/
void PWR_DeInit(void);
/* Backup Domain Access function **********************************************/
void PWR_BackupAccessCmd(FunctionalState NewState);
/* PVD configuration functions ************************************************/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_PVDCmd(FunctionalState NewState);
/* WakeUp pins configuration functions ****************************************/
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
void PWR_OverDriveCmd(FunctionalState NewState);
void PWR_OverDriveSWCmd(FunctionalState NewState);
void PWR_UnderDriveCmd(FunctionalState NewState);
void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
/* Flags management functions *************************************************/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_PWR_H */
/**
* @}
*/
/**
* @}
*/
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_rcc.h
+721
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@@ -0,0 +1,721 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_RCC_H
#define __STM32F7xx_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_Bypass ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_LSE_Dual_Mode_Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint32_t)0x00000000)
#define RCC_LSE_MEDIUMLOW_MODE RCC_BDCR_LSEDRV_1
#define RCC_LSE_MEDIUMHIGH_MODE RCC_BDCR_LSEDRV_0
#define RCC_LSE_HIGHDRIVE_MODE RCC_BDCR_LSEDRV
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
((MODE) == RCC_LSE_MEDIUMLOW_MODE) || \
((MODE) == RCC_LSE_MEDIUMHIGH_MODE) || \
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
/** @defgroup RCC_PLLSAIDivR_Factor
* @{
*/
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
((SOURCE) == RCC_PLLSource_HSE))
#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
/**
* @}
*/
#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source
* @{
*/
#define RCC_SYSCLKSource_HSI ((uint32_t)RCC_CFGR_SW_HSI)
#define RCC_SYSCLKSource_HSE ((uint32_t)RCC_CFGR_SW_HSE)
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)RCC_CFGR_SW_PLL)
/* Add legacy definition */
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLPCLK))
/**
* @}
*/
/** @defgroup RCC_AHB_Clock_Source
* @{
*/
#define RCC_SYSCLK_Div1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
#define RCC_SYSCLK_Div2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
#define RCC_SYSCLK_Div4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
#define RCC_SYSCLK_Div8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
#define RCC_SYSCLK_Div16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
#define RCC_SYSCLK_Div64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
#define RCC_SYSCLK_Div128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
#define RCC_SYSCLK_Div256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
#define RCC_SYSCLK_Div512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup RCC_APB1_APB2_Clock_Source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)RCC_CFGR_PPRE1_DIV1)
#define RCC_HCLK_Div2 ((uint32_t)RCC_CFGR_PPRE1_DIV2)
#define RCC_HCLK_Div4 ((uint32_t)RCC_CFGR_PPRE1_DIV4)
#define RCC_HCLK_Div8 ((uint32_t)RCC_CFGR_PPRE1_DIV8)
#define RCC_HCLK_Div16 ((uint32_t)RCC_CFGR_PPRE1_DIV16)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
/**
* @}
*/
/** @defgroup RCC_LSE_Config RCC LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/** @defgroup RCC_RTC_Clock_Source
* @{
*/
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
/**
* @}
*/
/** @defgroup RCC_I2S_Clock_Source
* @{
*/
#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_CFGR_I2SSRC)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_SAI_Clock_Source
* @{
*/
#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR1_SAI2SEL_0)
#define RCC_SAICLKSource_CKIN ((uint32_t)RCC_DCKCFGR1_SAI2SEL_1)
#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
((SOURCE) == RCC_SAICLKSource_CKIN))
/**
* @}
*/
/** @defgroup RCC_SAI_Instance
* @{
*/
#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
/**
* @}
*/
/** @defgroup RCC_TIM_PRescaler_Selection
* @{
*/
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
#define RCC_TIMPrescActivated ((uint8_t)0x01)
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
/**
* @}
*/
/** @defgroup RCC_SDIO_Clock_Source_Selection
* @{
*/
#define RCC_SDMMCCLKSource_48MHZ ((uint8_t)0x00)
#define RCC_SDMMCCLKSource_SYSCLK ((uint8_t)0x01)
#define IS_RCC_SDMMC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDMMCCLKSource_48MHZ) || \
((CLKSOURCE) == RCC_SDMMCCLKSource_SYSCLK))
/**
* @}
*/
/** @defgroup RCC_48MHZ_Clock_Source_Selection
* @{
*/
#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
/**
* @}
*/
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
* @{
*/
#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
/**
* @}
*/
/** @defgroup RCC_CEC_Clock_Source_Selection
* @{
*/
#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
((CLKSOURCE) == RCC_CECCLKSource_LSE))
/**
* @}
*/
/** @defgroup RCC_I2C_Clock_Source
* @{
*/
#define RCC_I2CCLKSource_APB ((uint32_t)0x00)
#define RCC_I2CCLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_I2C1SEL_0)
#define RCC_I2CCLKSource_HSI ((uint32_t)RCC_DCKCFGR2_I2C1SEL_1)
#define IS_RCC_I2C_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_I2CCLKSource_APB) || ((SOURCE) == RCC_I2CCLKSource_SYSCLK) || \
((SOURCE) == RCC_I2CCLKSource_HSI))
/**
* @}
*/
/** @defgroup RCC_USART_UART_Clock_Source
* @{
*/
#define RCC_USARTCLKSource_APB ((uint32_t)0x00)
#define RCC_USARTCLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_USART1SEL_0)
#define RCC_USARTCLKSource_HSI ((uint32_t)RCC_DCKCFGR2_USART1SEL_1)
#define RCC_USARTCLKSource_LSE ((uint32_t)RCC_DCKCFGR2_USART1SEL)
#define IS_RCC_USART_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_USARTCLKSource_APB) || ((SOURCE) == RCC_USARTCLKSource_SYSCLK) || \
((SOURCE) == RCC_USARTCLKSource_HSI)) || ((SOURCE) == RCC_USARTCLKSource_LSE)
/**
* @}
*/
/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIMCLKSource_APB ((uint32_t)0x00000000)
#define RCC_LPTIMCLKSource_LSI RCC_DCKCFGR2_LPTIM1SEL_0
#define RCC_LPTIMCLKSource_HSI RCC_DCKCFGR2_LPTIM1SEL_1
#define RCC_LPTIMCLKSource_LSE RCC_DCKCFGR2_LPTIM1SEL
#define IS_RCC_LPTIM_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIMCLKSource_APB) || ((SOURCE) == RCC_LPTIMCLKSource_LSI) || \
((SOURCE) == RCC_LPTIMCLKSource_HSI) || ((SOURCE) == RCC_LPTIMCLKSource_LSE))
/**
* @}
*/
/** @defgroup RCC_AHB1_Peripherals
* @{
*/
#define RCC_AHB1Periph_GPIOA ((uint32_t)RCC_AHB1ENR_GPIOAEN)
#define RCC_AHB1Periph_GPIOB ((uint32_t)RCC_AHB1ENR_GPIOBEN)
#define RCC_AHB1Periph_GPIOC ((uint32_t)RCC_AHB1ENR_GPIOCEN)
#define RCC_AHB1Periph_GPIOD ((uint32_t)RCC_AHB1ENR_GPIODEN)
#define RCC_AHB1Periph_GPIOE ((uint32_t)RCC_AHB1ENR_GPIOEEN)
#define RCC_AHB1Periph_GPIOF ((uint32_t)RCC_AHB1ENR_GPIOFEN)
#define RCC_AHB1Periph_GPIOG ((uint32_t)RCC_AHB1ENR_GPIOGEN)
#define RCC_AHB1Periph_GPIOH ((uint32_t)RCC_AHB1ENR_GPIOHEN)
#define RCC_AHB1Periph_GPIOI ((uint32_t)RCC_AHB1ENR_GPIOIEN)
#if defined(STM32F767xx)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)RCC_AHB1ENR_GPIOJEN)
#define RCC_AHB1Periph_GPIOK ((uint32_t)RCC_AHB1ENR_GPIOKEN)
#endif
#define RCC_AHB1Periph_CRC ((uint32_t)RCC_AHB1ENR_CRCEN)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)RCC_AHB1ENR_BKPSRAMEN)
#define RCC_AHB1Periph_DTCMRAM ((uint32_t)RCC_AHB1ENR_DTCMRAMEN)
#define RCC_AHB1Periph_DMA1 ((uint32_t)RCC_AHB1ENR_DMA1EN)
#define RCC_AHB1Periph_DMA2 ((uint32_t)RCC_AHB1ENR_DMA2EN)
#define RCC_AHB1Periph_DMA2D ((uint32_t)RCC_AHB1ENR_DMA2DEN)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)RCC_AHB1ENR_ETHMACEN)
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)RCC_AHB1ENR_ETHMACTXEN)
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)RCC_AHB1ENR_ETHMACRXEN)
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)RCC_AHB1ENR_ETHMACPTPEN)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)RCC_AHB1ENR_OTGHSEN)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)RCC_AHB1ENR_OTGHSULPIEN)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_AHB2_Peripherals
* @{
*/
#define RCC_AHB2Periph_DCMI ((uint32_t)RCC_AHB2ENR_DCMIEN)
#define RCC_AHB2Periph_RNG ((uint32_t)RCC_AHB2ENR_RNGEN)
#define RCC_AHB2Periph_OTG_FS ((uint32_t)RCC_AHB2ENR_OTGFSEN)
#if defined (STM32F756xx)
#define RCC_AHB2Periph_CRYP ((uint32_t)RCC_AHB2ENR_CRYPEN)
#define RCC_AHB2Periph_HASH ((uint32_t)RCC_AHB2ENR_HASHEN)
#endif /* STM32F756xx */
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_AHB3_Peripherals
* @{
*/
#define RCC_AHB3Periph_FMC ((uint32_t)RCC_AHB3ENR_FMCEN)
#define RCC_AHB3Periph_QSPI ((uint32_t)RCC_AHB3ENR_QSPIEN)
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB1_Peripherals
* @{
*/
#define RCC_APB1Periph_TIM2 ((uint32_t)RCC_APB1ENR_TIM2EN)
#define RCC_APB1Periph_TIM3 ((uint32_t)RCC_APB1ENR_TIM3EN)
#define RCC_APB1Periph_TIM4 ((uint32_t)RCC_APB1ENR_TIM4EN)
#define RCC_APB1Periph_TIM5 ((uint32_t)RCC_APB1ENR_TIM5EN)
#define RCC_APB1Periph_TIM6 ((uint32_t)RCC_APB1ENR_TIM6EN)
#define RCC_APB1Periph_TIM7 ((uint32_t)RCC_APB1ENR_TIM7EN)
#define RCC_APB1Periph_TIM12 ((uint32_t)RCC_APB1ENR_TIM12EN)
#define RCC_APB1Periph_TIM13 ((uint32_t)RCC_APB1ENR_TIM13EN)
#define RCC_APB1Periph_TIM14 ((uint32_t)RCC_APB1ENR_TIM14EN)
#define RCC_APB1Periph_LPTIM1 ((uint32_t)RCC_APB1ENR_LPTIM1EN)
#define RCC_APB1Periph_WWDG ((uint32_t)RCC_APB1ENR_WWDGEN)
#define RCC_APB1Periph_SPI2 ((uint32_t)RCC_APB1ENR_SPI2EN)
#define RCC_APB1Periph_SPI3 ((uint32_t)RCC_APB1ENR_SPI3EN)
#define RCC_APB1Periph_SPDIFRX ((uint32_t)RCC_APB1ENR_SPDIFRXEN)
#define RCC_APB1Periph_USART2 ((uint32_t)RCC_APB1ENR_USART2EN)
#define RCC_APB1Periph_USART3 ((uint32_t)RCC_APB1ENR_USART3EN)
#define RCC_APB1Periph_UART4 ((uint32_t)RCC_APB1ENR_UART4EN)
#define RCC_APB1Periph_UART5 ((uint32_t)RCC_APB1ENR_UART5EN)
#define RCC_APB1Periph_I2C1 ((uint32_t)RCC_APB1ENR_I2C1EN)
#define RCC_APB1Periph_I2C2 ((uint32_t)RCC_APB1ENR_I2C2EN)
#define RCC_APB1Periph_I2C3 ((uint32_t)RCC_APB1ENR_I2C3EN)
#define RCC_APB1Periph_I2C4 ((uint32_t)RCC_APB1ENR_I2C4EN)
#define RCC_APB1Periph_CAN1 ((uint32_t)RCC_APB1ENR_CAN1EN)
#define RCC_APB1Periph_CAN2 ((uint32_t)RCC_APB1ENR_CAN2EN)
#define RCC_APB1Periph_CEC ((uint32_t)RCC_APB1ENR_CECEN)
#define RCC_APB1Periph_PWR ((uint32_t)RCC_APB1ENR_PWREN)
#define RCC_APB1Periph_DAC ((uint32_t)RCC_APB1ENR_DACEN)
#define RCC_APB1Periph_UART7 ((uint32_t)RCC_APB1ENR_UART7EN)
#define RCC_APB1Periph_UART8 ((uint32_t)RCC_APB1ENR_UART8EN)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB2_Peripherals
* @{
*/
#define RCC_APB2Periph_TIM1 ((uint32_t)RCC_APB2ENR_TIM1EN)
#define RCC_APB2Periph_TIM8 ((uint32_t)RCC_APB2ENR_TIM8EN)
#define RCC_APB2Periph_USART1 ((uint32_t)RCC_APB2ENR_USART1EN)
#define RCC_APB2Periph_USART6 ((uint32_t)RCC_APB2ENR_USART6EN)
#define RCC_APB2Periph_ADC ((uint32_t)RCC_APB2ENR_ADC1EN)
#define RCC_APB2Periph_ADC1 ((uint32_t)RCC_APB2ENR_ADC1EN)
#define RCC_APB2Periph_ADC2 ((uint32_t)RCC_APB2ENR_ADC2EN)
#define RCC_APB2Periph_ADC3 ((uint32_t)RCC_APB2ENR_ADC3EN)
#define RCC_APB2Periph_SDMMC1 ((uint32_t)RCC_APB2ENR_SDMMC1EN)
#define RCC_APB2Periph_SPI1 ((uint32_t)RCC_APB2ENR_SPI1EN)
#define RCC_APB2Periph_SPI4 ((uint32_t)RCC_APB2ENR_SPI4EN)
#define RCC_APB2Periph_SYSCFG ((uint32_t)RCC_APB2ENR_SYSCFGEN)
#define RCC_APB2Periph_TIM9 ((uint32_t)RCC_APB2ENR_TIM9EN)
#define RCC_APB2Periph_TIM10 ((uint32_t)RCC_APB2ENR_TIM10EN)
#define RCC_APB2Periph_TIM11 ((uint32_t)RCC_APB2ENR_TIM11EN)
#define RCC_APB2Periph_SPI5 ((uint32_t)RCC_APB2ENR_SPI5EN)
#define RCC_APB2Periph_SPI6 ((uint32_t)RCC_APB2ENR_SPI6EN)
#define RCC_APB2Periph_SAI1 ((uint32_t)RCC_APB2ENR_SAI1EN)
#define RCC_APB2Periph_SAI2 ((uint32_t)RCC_APB2ENR_SAI2EN)
#define RCC_APB2Periph_LTDC ((uint32_t)RCC_APB2ENR_LTDCEN)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
* @{
*/
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
#define RCC_MCO1Source_LSE ((uint32_t)RCC_CFGR_MCO1_0)
#define RCC_MCO1Source_HSE ((uint32_t)RCC_CFGR_MCO1_1)
#define RCC_MCO1Source_PLLCLK ((uint32_t)RCC_CFGR_MCO1)
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
#define RCC_MCO1Div_2 ((uint32_t)RCC_CFGR_MCO1PRE_2)
#define RCC_MCO1Div_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCO1Div_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCO1Div_5 ((uint32_t)RCC_CFGR_MCO1PRE)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
((DIV) == RCC_MCO1Div_5))
/**
* @}
*/
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
* @{
*/
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)RCC_CFGR_MCO2_0)
#define RCC_MCO2Source_HSE ((uint32_t)RCC_CFGR_MCO2_1)
#define RCC_MCO2Source_PLLCLK ((uint32_t)RCC_CFGR_MCO2)
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
#define RCC_MCO2Div_2 ((uint32_t)RCC_CFGR_MCO2PRE_2)
#define RCC_MCO2Div_3 ((uint32_t)RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
#define RCC_MCO2Div_4 ((uint32_t)RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
#define RCC_MCO2Div_5 ((uint32_t)RCC_CFGR_MCO2PRE)
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
((DIV) == RCC_MCO2Div_5))
/**
* @}
*/
/** @defgroup RCC_Flag RCC Flags
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
* - 0XX : Register index
* - 01: CR register
* - 10: BDCR register
* - 11: CSR register
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLI2SCmd(FunctionalState NewState);
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
void RCC_PLLSAICmd(FunctionalState NewState);
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_LSEModeConfig(uint32_t RCC_Mode);
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
void RCC_SDMMCClockSourceConfig(uint8_t RCC_ClockSource);
void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
void RCC_I2CClockSourceConfig(I2C_TypeDef * I2Cx, uint32_t RCC_ClockSource);
void RCC_USARTClockSourceConfig(USART_TypeDef * USARTx, uint32_t RCC_ClockSource);
void RCC_LPTIMClockSourceConfig(LPTIM_TypeDef * LPTIMx, uint32_t RCC_ClockSource);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_RCC_H */
STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_tim.h
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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_USART_H
#define __STM32F7xx_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
/** @addtogroup STM32F7xx_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
} USART_InitTypeDef;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/**
* @brief USART clock sources definitions
*/
typedef enum
{
USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
}USART_ClockSourceTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) IS_UART_INSTANCE(PERIPH)
#define IS_USART_PERIPH(PERIPH) IS_USART_INSTANCE(PERIPH)
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint32_t)0x00000000)
#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */
#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b) || \
((LENGTH) == USART_WordLength_7b))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint32_t)0x00000000)
#define USART_StopBits_2 USART_CR2_STOP_1
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint32_t)0x00000000)
#define USART_Parity_Even USART_CR1_PCE
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx USART_CR1_RE
#define USART_Mode_Tx USART_CR1_TE
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
((MODE) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint32_t)0x00000000)
#define USART_Clock_Enable USART_CR2_CLKEN
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint32_t)0x00000000)
#define USART_CPOL_High USART_CR2_CPOL
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
#define USART_CPHA_2Edge USART_CR2_CPHA
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint32_t)0x00000000)
#define USART_LastBit_Enable USART_CR2_LBCL
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAReq_Tx USART_CR3_DMAT
#define USART_DMAReq_Rx USART_CR3_DMAR
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
((DMAREQ) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_DMA_Recception_Error
* @{
*/
#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
#define USART_DMAOnError_Disable USART_CR3_DDRE
#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
((DMAERROR) == USART_DMAOnError_Enable))
/**
* @}
*/
/** @defgroup USART_MuteMode_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
#define USART_WakeUp_AddressMark USART_CR1_WAKE
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_Address_Detection
* @{
*/
#define USART_AddressLength_4b ((uint32_t)0x00000000)
#define USART_AddressLength_7b USART_CR2_ADDM7
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
((ADDRESS) == USART_AddressLength_7b))
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower USART_CR3_IRLP
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_DE_Polarity
* @{
*/
#define USART_DEPolarity_High ((uint32_t)0x00000000)
#define USART_DEPolarity_Low USART_CR3_DEP
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
((POLARITY) == USART_DEPolarity_High))
/**
* @}
*/
/** @defgroup USART_Inversion_Pins
* @{
*/
#define USART_InvPin_Tx USART_CR2_TXINV
#define USART_InvPin_Rx USART_CR2_RXINV
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
((PIN) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_AutoBaudRate_Mode
* @{
*/
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
((MODE) == USART_AutoBaudRate_FallingEdge))
/**
* @}
*/
/** @defgroup USART_OVR_DETECTION
* @{
*/
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
((OVR) == USART_OVRDetection_Disable))
/**
* @}
*/
/** @defgroup USART_Request
* @{
*/
#define USART_Request_ABRRQ USART_RQR_ABRRQ
#define USART_Request_SBKRQ USART_RQR_SBKRQ
#define USART_Request_MMRQ USART_RQR_MMRQ
#define USART_Request_RXFRQ USART_RQR_RXFRQ
#define USART_Request_TXFRQ USART_RQR_TXFRQ
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
((REQUEST) == USART_Request_RXFRQ) || \
((REQUEST) == USART_Request_MMRQ) || \
((REQUEST) == USART_Request_SBKRQ) || \
((REQUEST) == USART_Request_ABRRQ))
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_REACK USART_ISR_REACK
#define USART_FLAG_TEACK USART_ISR_TEACK
#define USART_FLAG_WU USART_ISR_WUF
#define USART_FLAG_RWU USART_ISR_RWU
#define USART_FLAG_SBK USART_ISR_SBKF
#define USART_FLAG_CM USART_ISR_CMF
#define USART_FLAG_BUSY USART_ISR_BUSY
#define USART_FLAG_ABRF USART_ISR_ABRF
#define USART_FLAG_ABRE USART_ISR_ABRE
#define USART_FLAG_EOB USART_ISR_EOBF
#define USART_FLAG_RTO USART_ISR_RTOF
#define USART_FLAG_nCTSS USART_ISR_CTS
#define USART_FLAG_CTS USART_ISR_CTSIF
#define USART_FLAG_LBD USART_ISR_LBD
#define USART_FLAG_TXE USART_ISR_TXE
#define USART_FLAG_TC USART_ISR_TC
#define USART_FLAG_RXNE USART_ISR_RXNE
#define USART_FLAG_IDLE USART_ISR_IDLE
#define USART_FLAG_ORE USART_ISR_ORE
#define USART_FLAG_NE USART_ISR_NE
#define USART_FLAG_FE USART_ISR_FE
#define USART_FLAG_PE USART_ISR_PE
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @brief USART Interrupt definition
* USART_IT possible values
* Elements values convention: 0xZZZZYYXX
* XX: Position of the corresponding Interrupt
* YY: Register index
* ZZZZ: Flag position
* @{
*/
#define USART_IT_WU ((uint32_t)0x00140316)
#define USART_IT_CM ((uint32_t)0x0011010E)
#define USART_IT_EOB ((uint32_t)0x000C011B)
#define USART_IT_RTO ((uint32_t)0x000B011A)
#define USART_IT_PE ((uint32_t)0x00000108)
#define USART_IT_TXE ((uint32_t)0x00070107)
#define USART_IT_TC ((uint32_t)0x00060106)
#define USART_IT_RXNE ((uint32_t)0x00050105)
#define USART_IT_IDLE ((uint32_t)0x00040104)
#define USART_IT_LBD ((uint32_t)0x00080206)
#define USART_IT_CTS ((uint32_t)0x0009030A)
#define USART_IT_ERR ((uint32_t)0x00000300)
#define USART_IT_ORE ((uint32_t)0x00030300)
#define USART_IT_NE ((uint32_t)0x00020300)
#define USART_IT_FE ((uint32_t)0x00010300)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
/**
* @}
*/
#define IS_USART1_CLKSOURCE_PCLK2() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_0 ))
#define IS_USART1_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_0 ))
#define IS_USART1_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_0 ))
#define IS_USART1_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART1SEL_0 ))
#define IS_USART2_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_0 ))
#define IS_USART2_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_0 ))
#define IS_USART2_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_0 ))
#define IS_USART2_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART2SEL_0 ))
#define IS_USART3_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_0 ))
#define IS_USART3_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_0 ))
#define IS_USART3_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_0 ))
#define IS_USART3_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART3SEL_0 ))
#define IS_UART4_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_0 ))
#define IS_UART4_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_0 ))
#define IS_UART4_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_0 ))
#define IS_UART4_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART4SEL_0 ))
#define IS_UART5_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_0 ))
#define IS_UART5_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_0 ))
#define IS_UART5_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_0 ))
#define IS_UART5_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART5SEL_0 ))
#define IS_USART6_CLKSOURCE_PCLK2() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_0 ))
#define IS_USART6_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_0 ))
#define IS_USART6_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_0 ))
#define IS_USART6_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_USART6SEL_0 ))
#define IS_UART7_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_0 ))
#define IS_UART7_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_0 ))
#define IS_UART7_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_0 ))
#define IS_UART7_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART7SEL_0 ))
#define IS_UART8_CLKSOURCE_PCLK1() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_0 ))
#define IS_UART8_CLKSOURCE_SYSCLK() ( !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_0 ))
#define IS_UART8_CLKSOURCE_HSI() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_1 ) && !( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_0 ))
#define IS_UART8_CLKSOURCE_LSE() ( ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_1 ) && ( RCC->DCKCFGR2 & RCC_DCKCFGR2_UART8SEL_0 ))
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
#define IS_USART_DATA(DATA) ((DATA) <= USART_TDR_TDR)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and Configuration functions *********************************/
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
USART_ClockSourceTypeDef USART_GetClockSource(USART_TypeDef* USARTx);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
/* AutoBaudRate functions *****************************************************/
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
/* Data transfers functions ***************************************************/
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
/* Multi-Processor Communication functions ************************************/
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
/* LIN mode functions *********************************************************/
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Half-duplex mode function **************************************************/
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Smartcard mode functions ***************************************************/
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
/* IrDA mode functions ********************************************************/
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* RS485 mode functions *******************************************************/
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
/* DMA transfers management functions *****************************************/
void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
/* Interrupts and flags management functions **********************************/
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_USART_H */
/**
* @}
*/
/**
* @}
*/