From 0833dba9bd0522eaad32889606be74d297a0f04d Mon Sep 17 00:00:00 2001 From: Luca Marchesano Date: Fri, 29 Jun 2018 09:31:01 +0200 Subject: [PATCH] Add submodules for F4/F7 libs --- .../CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 0 -> 172641 bytes STM32F4XX_Lib/CMSIS/Include/arm_math.h | 7556 +++++++ STM32F4XX_Lib/CMSIS/Include/core_cm4.h | 1858 ++ STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h | 664 + STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h | 916 + STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h | 697 + .../CMSIS/Lib/GCC/libarm_cortexM4lf_math.a | Bin 0 -> 3194948 bytes .../Device/startup/startup_stm32f4xx.c | 436 + STM32F4XX_Lib/Device/stm32f4xx.h | 11849 ++++++++++ STM32F4XX_Lib/Device/stm32f4xx_conf.h | 78 + STM32F4XX_Lib/Device/system_stm32f4xx.c | 1212 + STM32F4XX_Lib/Device/system_stm32f4xx.h | 105 + ...MCD-ST Liberty SW License Agreement V2.pdf | Bin 0 -> 17797 bytes STM32F4XX_Lib/README.txt | 21 + .../STM32F4xx_StdPeriph_Driver/include/misc.h | 178 + .../include/stm32f4xx_adc.h | 656 + .../include/stm32f4xx_dac.h | 304 + .../include/stm32f4xx_gpio.h | 564 + .../include/stm32f4xx_rcc.h | 982 + .../include/stm32f4xx_tim.h | 1150 + .../include/stm32f4xx_usart.h | 431 + .../STM32F4xx_StdPeriph_Driver/source/misc.c | 249 + .../source/stm32f4xx_adc.c | 1745 ++ .../source/stm32f4xx_dac.c | 714 + .../source/stm32f4xx_gpio.c | 611 + .../source/stm32f4xx_rcc.c | 3022 +++ .../source/stm32f4xx_tim.c | 3365 +++ .../source/stm32f4xx_usart.c | 1486 ++ .../CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 0 -> 179946 bytes .../CMSIS/Include/arm_common_tables.h | 136 + .../CMSIS/Include/arm_const_structs.h | 79 + STM32F7XX_Lib/CMSIS/Include/arm_math.h | 7154 ++++++ STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h | 734 + STM32F7XX_Lib/CMSIS/Include/cmsis_armcc_V6.h | 1800 ++ STM32F7XX_Lib/CMSIS/Include/cmsis_gcc.h | 1373 ++ STM32F7XX_Lib/CMSIS/Include/core_cm0.h | 798 + STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h | 914 + STM32F7XX_Lib/CMSIS/Include/core_cm3.h | 1763 ++ STM32F7XX_Lib/CMSIS/Include/core_cm4.h | 1937 ++ STM32F7XX_Lib/CMSIS/Include/core_cm7.h | 2512 +++ STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h | 87 + STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h | 87 + STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h | 96 + STM32F7XX_Lib/CMSIS/Include/core_sc000.h | 926 + STM32F7XX_Lib/CMSIS/Include/core_sc300.h | 1745 ++ .../CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a | Bin 0 -> 3136980 bytes .../Device/startup/startup_stm32f7xx.c | 519 + STM32F7XX_Lib/Device/stm32f722xx.h | 15173 +++++++++++++ STM32F7XX_Lib/Device/stm32f767xx.h | 18607 ++++++++++++++++ STM32F7XX_Lib/Device/stm32f7xx.h | 230 + STM32F7XX_Lib/Device/stm32f7xx_hal_conf.h | 228 + STM32F7XX_Lib/Device/system_stm32f7xx.c | 405 + STM32F7XX_Lib/Device/system_stm32f7xx.h | 125 + STM32F7XX_Lib/README.txt | 26 + .../STM32F7xx_StdPeriph_Driver/inc/misc.h | 378 + .../inc/stm32f7xx_adc.h | 617 + .../inc/stm32f7xx_dac.h | 277 + .../inc/stm32f7xx_flash.h | 366 + .../inc/stm32f7xx_gpio.h | 491 + .../inc/stm32f7xx_pwr.h | 247 + .../inc/stm32f7xx_rcc.h | 721 + .../inc/stm32f7xx_tim.h | 1279 ++ .../inc/stm32f7xx_usart.h | 592 + .../STM32F7xx_StdPeriph_Driver/src/misc.c | 254 + .../src/stm32f7xx_adc.c | 1640 ++ .../src/stm32f7xx_dac.c | 584 + .../src/stm32f7xx_flash.c | 1109 + .../src/stm32f7xx_gpio.c | 541 + .../src/stm32f7xx_pwr.c | 965 + .../src/stm32f7xx_rcc.c | 2370 ++ .../src/stm32f7xx_tim.c | 3890 ++++ .../src/stm32f7xx_usart.c | 2064 ++ 72 files changed, 116688 insertions(+) create mode 100644 STM32F4XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf create mode 100644 STM32F4XX_Lib/CMSIS/Include/arm_math.h create mode 100644 STM32F4XX_Lib/CMSIS/Include/core_cm4.h create mode 100644 STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h create mode 100644 STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h create mode 100644 STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h create mode 100644 STM32F4XX_Lib/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a create mode 100644 STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c create mode 100644 STM32F4XX_Lib/Device/stm32f4xx.h create mode 100644 STM32F4XX_Lib/Device/stm32f4xx_conf.h create mode 100644 STM32F4XX_Lib/Device/system_stm32f4xx.c create mode 100644 STM32F4XX_Lib/Device/system_stm32f4xx.h create mode 100644 STM32F4XX_Lib/MCD-ST Liberty SW License Agreement V2.pdf create mode 100644 STM32F4XX_Lib/README.txt create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/misc.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_adc.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/misc.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c create mode 100644 STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c create mode 100644 STM32F7XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf create mode 100644 STM32F7XX_Lib/CMSIS/Include/arm_common_tables.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/arm_const_structs.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/arm_math.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/cmsis_armcc_V6.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/cmsis_gcc.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cm0.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cm3.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cm4.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cm7.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_sc000.h create mode 100644 STM32F7XX_Lib/CMSIS/Include/core_sc300.h create mode 100644 STM32F7XX_Lib/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a create mode 100644 STM32F7XX_Lib/Device/startup/startup_stm32f7xx.c create mode 100644 STM32F7XX_Lib/Device/stm32f722xx.h create mode 100644 STM32F7XX_Lib/Device/stm32f767xx.h create mode 100644 STM32F7XX_Lib/Device/stm32f7xx.h create mode 100644 STM32F7XX_Lib/Device/stm32f7xx_hal_conf.h create mode 100644 STM32F7XX_Lib/Device/system_stm32f7xx.c create mode 100644 STM32F7XX_Lib/Device/system_stm32f7xx.h create mode 100644 STM32F7XX_Lib/README.txt create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/misc.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_adc.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_dac.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_flash.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_gpio.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_pwr.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_rcc.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_tim.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/inc/stm32f7xx_usart.h create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/misc.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_adc.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_dac.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_flash.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_gpio.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_pwr.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_rcc.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_tim.c create mode 100644 STM32F7XX_Lib/STM32F7xx_StdPeriph_Driver/src/stm32f7xx_usart.c diff --git a/STM32F4XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/STM32F4XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..b374366930b2d1b5689ff5044caba49eace6aa68 GIT binary patch literal 172641 zcmdR#Ral%$x1b?7!6mr6Htz23?(XjH?hZkNyL)hVcZUGMEw~TKKKuOppEGBkxtNQY zzNxCOYgw(T?tc1RMIt98LPJl>3=2)t`0;{;rpKqlw>7YUh34V{D7o7i0|fP*^sQ`7 z0do4L#*X+5A8#uFr1Wh}$&GDjLtNZ>{+B zEPpj@zZ-4*e=7Su@4qPf@Y=!nL)l+$D;PW4Iy)E|JAODNVr%2{yP?Nt{;dlj!hp~E zSBDXw{db3l2O#HQYp7`KqzU*~B!H5!n-f6X`ePLY{%QpOYQ%rL0gyH}GS?Tdb<_M1 zrNd`tXQpLjz-MEkr)6i*#{Y=O#_7WiNBlog07M;Zo$dZ!-#-I@B0$MO-^S7Ix4VY! z06|57kgUm-c-)BQ90--`c^Uc}tW$=CrPVx{k7EM#nG zYh(=&KtZxkq?Uq@ot?9VVQs?8E{0>4T%czN&-V%rZBdJV; zh+<|i-kB-FwYkDu&dJ`%K%Ik#z3uHDVxxrx%7J{Sv2g|l!i)(sx*BT(_G!W4+R4+= z{!!`Wvafu9Zf;=zVo7!2S=IC&{@usiG#!7cmsy$s#ehB*PBCXgsMx+(C?_aYxru3xjfZ=NhdqT> zk)Abyk%2?AbyM)`76wu$Re)ELGEd%EFomyyy;P60wop5pisGaWcRri-8zw|~Hp<(m zUo?5SiCOnRGfo)>#_`_Gb_U$yC?dblntP*#T}f{ovb4R+qmPPm-NKf`db&Lb)YPnA zsECvFBL`lNyMs1miLljyd%>HI@GlwHz4!b=BzAnjU$_vDeg) z1R}u>L8dLPNwkSmm(I9)Px$LCv`by!cM9OiGTV`)xnSU;r|){DmjU#0ZBefZUrq+e zQ6ai2B2+=>B=|2xR=Z^cH-2q*5;$K%2 z+EStG<1Ks|a+XJy!Oh*_r3u)}!Z>I!!rO%hz#nCblDSO6<@_#W4=D>xBy zKg1&P&D0bPoo&*EZvmi_#-$qrx<5p2`mf1&^s9ZIkCm? z`t^kOSdr3P?5c%qYYHyr{$SRwX}dA=^*aw+*3ui+6SQb~;BK=6vewN z5ac>^%IB-&HM@Pi)?8n6ag5X4DxMDqIx4Vi5kj(>Iv8XW))ri-hb0?#bfAXL8@s8# z*xt!7S4usq-6tG_rJyavOH})&MQ)A(sLPcnn(^C9E861~UKph7m0vgAuP#njqTJkC zRl^m-PxRWyivawC{LkbJ_4i|>LZx%cn!DSQT5W}>y*~Ca^@c8+C;7LJ*k=Q8JsCs~ z&yx~|PObMp^|-&oF*L&kBukNGTFD=96i+78pH2vQ+lch{T(Tt$_gO5>e5X6sdWrZ& zSEiM=zZVV;kVo?Y?ciUiWGM6Gd4_`lEWBQH!(iFxVJ{6JIdvaF%W3`?>a~KU7jVA- z3gu-?C+5?hI0)SRp?isTbEV37(=+q6_Lg^L!a3sQ*GilNvqoP^*ld!6TDpZ$Ix3aB zV8h8FdXX_1q$4vmF3tsB2j}X$^P>p_=|%Pr-2N%9wQ@3|=LaB`*!T+!EhWj0zS@q(JLI!Tmoosz#qT&auDhMPU@G=P>}yd>LgkW!3g+!(Af7liR=Ax5x-aV> z-*;F+^3Rcn4-j}FDMS5?*w+?ME6hCw;j2yZ%j-xWyCNLvzR`U*S5GDwr&O27M)Jwg z8$FsOf6dlDxFxqv$+y-*0f`H8G2a`&L=4^oe{-9 z2>Yo*g#)G)*nHJytuGz4QsEFnHI$TTRIN6t7e2^_8YNTO2Fex=j1d!?#)vfA5?@Bt zU*F6Iox|>>-TJ@Ojme@)T&d9p0m+&2VVE^^UOsNm zuI#9NM5T!vbrx>q6PRIHyLa*Dk1+g z#_eR*qz5|X-?I0;!crpUoE8BY{c!=w`kEgh=2l=5JUL$lh;wcoA)E1&4!ebRQ$PHX zUaD09CQ(u&H``VpUP1a%Ddc7EvEPAIMa$fI1@Fl>IO?+xG3WV_vU=E?)6q;tJn>#1iX4{jt1 z2NQR)UR&Lxh6rk)OsSDg1rM+OT+ig@7F_5L@_b0A4l=6&k_@95gNVppPoSX;J$iB& z1Qsn2?uAmO56e~|b`e^(imYrrZ_$(XXt2DE`eHram;9<3z5%xMGxw^5awYv8@0=F% zTD!^xZT6+|wkn|d>|CIGY1J#`uD)VpOK^>;!MtWH+i6eJO@+O#DmoW9f05d$C&$pU zF_LSHduj9bGi(7%^uu|c3t7xUH`!66H@F6jFOUK24Msk!TO zwOdEM=adE@byZLM7mMVm5iG5^l!_r6t#|+S5;Me+1ZC1kdyTYY&;?a)%|~xfd(Hr) zBoHA(elM%Z+Na|90)3=ClBSW!+V4rQxeWcphStqTBM!IqJsV4q83!iYCQsdiVG%B? z-RY@~_|md7+F)@yXk&@_OLS*H3_44!Cr_cd0ea+BU)5=gM9~@Clq6Wf3FO0V6i+BS z*8rorw@BMjmb2#A%8w{Ym6|#hEU3!O=LX=6mXHhCC{OJ*Wk+|v*m@D|f_qFhKV4!j zQo`E_UP{ta59mU4Lv~W!k@0E--2-8iu=Kc?LCpAhN56^}?v_0y`Y+9+^vf3<$2H$5 zLGL53I-{-3nX56*WQgjCs(ld}`qt|HU@rd?l^J%!zvHUJkZMXt`+}hkdU8_BnegSyk#cCv7t9j;kzvX2As890(rtwdF|Zqq^`HGBK$%W~ACP8& z?{|(WWe0uf@S1=eD%GGGp~bjod(QpFmv+{W*%E12VyA9kuHOe>y#`D(KCN=S!VR08 zbf^G%-8C0my1i@>%rhlcvKgBq=&zL-;VdSCtbo9U2L1@D;x3Lg;fa|VYt0x0e+<$c z^`CLuNP^AJj~2{L0}cL(uTTmZ>`=~A@_orZJ#|N);f#%36C%cZ&3jl1cLs6>s9_XZ zMs@8VrF=wB!HM&}fz=R%cu_N6$JJ$JqIdAsz!?>_pS(oz^ao;$27D8byrwfhYF8_> z^yP`L%Dr}pP&#Ze4aMozhz;-Do?V!4pie8LZml@2vXih0+#0MMLK4^ny=KB z%(NZLD*mF9t2{6qpRnP23at0Qh3`G}oI%!b$gU8*GYQfgX`Q9bbzmEQgR^1{FbA(?kEmTCm(w;qgJ6{$s1QZk~YMW5V*TvyiK9mSW&SF zBDc<9+dQFZSB?To2~H_!K7=YcpB1P^4q4n2On2`4*V9%T6IglO-a!=B`rvl`P*_O# z?rDMkK<|m1BlSgxu@PJ>&}LiVb-atXlKyIYAB}=DY@7o;Fkh-CHjcIECyV}rdY;4_ zVOtivPFdsKsR#0mDm?W>^wGuoPIX{{!(Rk)-nHRr8XCKo2zu1DAixh0`k+u+!JV~3 z#W8>{n8k1j=7$J-J$*|h(-t7JaQ(s@*7E+!hJFGjDKKn`Q$t)o1MVD$370* zdS#w`swtQT=JpXwM3=Tr%n}P}pcbGp;95+eEF+ZHxOw^F7DsxDLKd#{$>k>krd+x_Qr|EPB+_lH)Wty% z-AxFC03n+vnYeQ|*c7E7psh*0i|Ux4r|CGxdWh2F!>+K!)+QR8UGYLaYMYiUAxqdz zJDOUMFOU@5^wu%f4)eD42hPX)M+22k?|`Ib{WB(+D7O>UE~Spu-Bv z+6M~k+AX6Z;SI?tdaP=L76Af4apj)a0pT7dyDhyFJ%eLh;TY2FpA%ZyS)uma1GC4B zApu@649^MJD$=$fr=wo|KL^Z9pwvL*N{z1KZZ_h6p>yp-$rw$)n^#mPHQ^{d4?al< zT0h${Cwxjp-HfSGin++)12@C1r01v7J4h!LI$T-Agk33$$9l%6k6Y6BJ~wnVZGxCU zWfkQtrAX}HpG~JAxV7??vq7T#1zBr(JR^z~rE!&^YJ?VyEwR0QD=Xm2*3h@pBD2Z^ z-sZZ~VS|?4bL5|NK7{?5(X=I>+4@C8pdq~h*3#Y_2kQE)UiW8JZM3?#VH8T?^{d_* z=IJrh+xEGdXvzWObWR$Luyh~|28iaRQVX+G48Ui9TONrbv|IW;4bmt-CynP2Cgivs ztRslUL50G@y9v5cOhDIW2d5z<3fPu=-ZJ23)je0859iVkVhNa(NO+GIec#nA-CWs4NQC(49INc8u8<%@NTf@K%nG1rmy*h9+Vrz)j zfD>h$?*-6_SVFCD=uy@|kWx~*#A6Z1Kj&x#p=nVvKMmWdVd0laWqqge2ph`Hbn*>ZWfAFH(!EhHP-$DvQJ+OXZU-f9BiYyLdI$qM%& zB!`mFgZT+X6aI?L{y^m1NBr5G_TgnE@kGQSlg?UTluIfzvb;tyo+zyjCFnR%bXOXW zpIE%gy2^VFOLA~b0c0cB%ttvQU4lX+>Vk_>C@{Gy)rfm+!_WfVRd|F6XZbW>(fZTK z1a3FNb6BMoF=9S}CPi{k0R@KXPy|HOnQ66|g45)I31&|F^`#N8ht>=}UP=DgHW*M5 zzQw>08)8<`x67gTfCw%j+Dsb{tfPh;@%bgoDRxVRYKSb;Q}XYdNsD6ISX$K=Sx?#H3Qp4O)eD7k{7CF5-euMj1(TJ1j*R0M z=xYz>k1Hkw61$YNPv^|8l9)YLN#uzua3`!PMqtm`yi;IIdTvbv`&|)2Lncaft!N%w3arWP)58|CW%zUt+egrD4`Z- z%jVp-fPyCqlO)B2An)X9#`i&QMI!$5NrzMLF&4I-l>=%JFA@gvX|U6UE%5N`RZz&M zUG`!;@OD{Kyw_h7%2iV*6l%n%LWl_n>MZaa4nFXh>h+_cm`pR9ahq`AQDqaMn3(}B zr22K2V5Vs!o8THmy`E<+oZK3M!Pn4jtr*sM5^B3B^Ls~(-1r`p^zKNBn6W;DGq@+K zri$&Lthspuu~Oi0GbyKs2iHr1%*l&3g;eYf$8jSGnN6@&Suy7uEt6rGnft_>K0C&K zZ`t%%R0u{o`6V_i`sowLZtA*h;w zO+%LKoCB#B^tQ8_?es{ki55dPQm6wrRQliXZ*`6+Sc1cyf{Xl+wc1NOhv>0ZpAg0s zSUr59MyECTa{|eGJs{G$ZhNv@`~t7sc8TlYOm~5+)=8jvyCV4c9=|R?nOEB?WbrMh zsbozb?T4Uxxc0PADckKlp0T%M+UO$Tda$?CK&UQm7h(wn2K{KUpQ*Qxl*z`;m2y>X zt^vG2ayTLz9&})HUu2utoUDRiX`tEeZl}6714|&VZ0x?C47ECDR7`lH*K}6BK3cun zynA)-cD_Lk1s)Kevf)ag8F&s>Rd2VRun$t^XN6NKB#*0Q!oT&!in{=iGmg3%h+KV# ztcf-)Amu#qOrj+20*WZhiv;(-y7$%+IHJMwA2~~gV(0jrd*C9|v` z$F8(BOzF|PD#m^#QAiS7w`HPKj!~S_9yiqR^B~z1)g2H%jNZf9_GnL-3f^x>4K(iV zw^J5(`js$3Qxz8>bzFnlo@+FAmeCMbS}3gTIr}9elt-LUNtOzHEcIYbpeAH-nR9id zky;_Qb6-PcyH;_9r$>s9T#5WU6N)KTy0tkI6!iV4-p{(9lVQg#6;$_fU4ghV7IUDS zn?psn5CU;8yT@e~t+cKLG)HoI0vbrJGKvyU8Mc`Fp9D6FoG}asL@|pGH;ge{%amb@IB^io ztRtwpwBMu1oE6qvI|^u7us*x%t8{6ul|gJcab^@FNZGAK3BxQ|dh8z7!>=yyydeu@ z^6<}~S%qyAhkuo;pMmY8p%8poB`%<(sOq{SNloNNeCx^75i zm?yFY_lKri$l=7=CqMY!jHHW!d1RfTGAV33QL3syNX+@7e6d|tZ{xKlVBy2jCT)WX z)8%mNnR1NyzP?c+lcJybb=}1-6}-4(sTg+!Udp^eBW&Dh>tLzq7K0vSn{nP6Grl1^ zKh{Jb;p1oj!~p=eWrp7&yg(FhLm=-R3!8(FM5rrb`mmpLl^Fax)T8LLy|8(! zGTClsTzKJIvh%HhcewTCAcR7|*SugX&ZZ0DJ@ynRFHFq`(&sYr!5v!BI;(k-L&cE+ z7~=BWFJW@w;VUw=vxdB|$3K~z3E9OGB>0GbVIYrmYRfX$z(Xb%N0%2nvfK`;Q0Tak z)PHqK$0GGCH;0ju@`67eKDkw!>n%@8tV~w1QP39O$3)2{F%9o8L{D}8@;?4GvhbxP zKL(b0%M%T(*~y8|LmBq9r%oQW<{lQu8mv>^s}+$fILNz>{c;aGkR<4|38`;@Z$-$r z|FqmM3b!E(acCgEPyHU#USOY;w7;YM^(+)ZO<&8|X;DCWoak1bhSIysIaukggI}Td zS*b`?%D5xpJ1`@QbxsL=bpZ=m>c~&IaBP5y$kl>*h1D9O%3xE4(x$j`dnOsP;ZL#n zW>tE@8Tk%cD-wuE)>MEQ%+=(J~xu*OQKeEXsiGbK(yZLGF=bMwaJ)LimO-%#-c?c9s8x(PXK;ZPf4MDs4wU)pD5 zAM^8at1V7Y?48T;vLun41vDIX%9=S0q+^~s+U=+-B=3UF4|NWAa@H<2D^6;Ua6Rw{ zHs!@8n^k?*v_m9d9p>-M<9h*BRFG1~z%z7rlS@;zNtDkivl>Kj5Rdn8eEG!J08(WH zZE0~Ch6I8{dIr6WTTx>$fRY%57f#@pxdcP&MPY0F+k{!1;vPqn9<{=~ws|2#SP?55?|s#TbYi(gDsufbM2S0*QES*?EMlRlM41e;I-VyE(ltsY zyR;)U=B*Z@j5{zae?so5*4bCP;fR#;qwMwL-VkwqGZj!Yr^t6)I7~NI%1`skl*n0# zJOqhBu&?PeAS6nv#s+oX+9Qt$%u49RWdiU_r3S}MN~Jo-7JCnyKcl)-$0JfR$$yfY zG_3eG=hB=+#63NYalRrthCsXxa0o+SZ>_W67+ro*me{Kw%51Y6hp!I)rA}>%*d0_# zsk*S?Da}7eT6-AhS+{2Db-r@#hY}b0mB&3RP@5L(VaOgb*@)L-h*dbjNPu8TbS%GD zKF+F&^l=C#f2;}PfFtxMPvvq^vG?}a@Up^V33|MHl9feT%`1&<-;mm<53V9ak}xQ^ zU%ke!Jkgv~;G5q8v!JWxFpKZx2+H>*sb6t=G80h5QLooXL@p9opoBf`=oiprFVY&` z2Z}IPpZHoJl9QV9PmrnZ1z23PURLU09!!VQgQo5qB-p+?Vup%Wj}M^EAh*{lljbfT z&_7RoZcvlT`NhUFbIJ>tHfSLvVTc&#z`CZ};LMBysz2Y7M8~2#iHB}4M}i3Aw7!&h z8oSqo)^b|J3RaD!6Mz%HC4c3`Bt|9p0}}s6S${Ld-!$)U5cY>({sw&jMP~!2-!N0@ zgF*gzDx+_0`~m*}0{V`|e`fGInCn{sgl#@>nYoQAK-Jua-^S7WKgYl42pKyXI+)uz z**f6=!H@tEa|cH!K{I^^d`5;3Ci)+JdIp9MaU&-)M|^s^KXCD%pzgQifAQ~Mn*VUg zKhFK-&9cn*KBAk8MqS`rq{hALRaDMF4-E{O#HQbR7Rawu0h9zs>zVxeR|*CHx)&J{~LC zii!(K>)QeT_7NbY`r*UJmi~BC(cST51OKi<_*kYte*PBwSCaAR|Eg8^E%ArU|C`tU ztWJ=1Ffw-dI27c6oB61FP%t(%|M>KAC+GjDW-$I;2;ppJXJu^t`(XYXoBw0w?+E|% zGwEM${7KyZZ)g7BcH5t2{I|vXXFbB7kbjqU{J&O>LH}3j$N!yj4EleI|DRt&|9w3M zD;)#FZ?V6>#6IdVxYum3*y}EUf5Ar&0LL_haZX6;wjiU&8M7~T%X1}gxB1t@;|__p zXVkXGFnIpFfG>BWYFbX>LZ&8Fsb3i|s8w@y(3Qbub;YZ;Wf>?}1(0P-+)f;gv3_***Vyd79gJz5Qw9?dzt7jUyZR&gHwvWK5(sqpYkx60o4Gj+U96MU88l z!~6WK8~J=NWyMN+y%9s3&Fksj3$3i><@FYYn*4@GrJ8WE|R!&@F9dpUJ- zFjXaD<%KUY5W5>_b7Ng0a)0R-Y3;QhL-`P_z4wqaFc3SHGjW5?`zjulcCO+oh>m(C zW}C_K$RINNnq(jAwPa=0;q;Xmr9>3phMd)7 z*8U#o8Vl6Gj@kS{|7>HDIPCIk0>t}J5$omclG6P*MZuAAIo^CG-xm%ZGZEKa5Oxht z`uFBfZ>X2DP(Lc3vc=SO(D^Jf&|pw>=)kQ~r*$jio!P|(PA3}N*uMqGE@n(TEp0@! zl#Zqxsau#=T;Z7r9}b0nhb=+xkkdk~d|R@LEl0%5d&K)x&72n2jkbmCRUXWT!RK_#VhSMbUZdxZ|CC1qSOGCOZQ8BHo&YqgXLM;toy?TEaem1c&PC-~b{M)w zO?Mo7oFSnGAOjq)OtFG2Hbd-hMpWkWDUM};R>0ArnXJnR ziW)l=Ql4^@SY1j98d)cKoG5QVE>(Y>G7t)F+YLeKC*I5w1|B*4lXg9{M1yVa8OV!J zV>qqh18bld@C#F=FiVw;BnGqLGO@VCo?}8y|kQbulPdhRl|xIBhry?L~~y6SXVa}`eEXC zV;*dWdh-@Jw!!M*a(P%X`Y{06ab#3)`@&U!ngyMClkOssyRr=OIB7d%Hb>+!t`Ey7 zi?LIb0k4ChGH0=(Ama`SemYJekMji~6yBx&O7iuQ8>imm225=b5TOmapDOQaxG7@T zTG^+Nm(1+ZgtCS692+k7E3)&Vs?sk)(XP6zjDy2S;5~V+@1tx;@ik|<>#I*maVX8p zPAK%7Qz*prLRZQx({T8s=F*pxv%|N#UBSV_&;|L2W!Pa(ziw(`oA;&;z{z5Jh3-uC zDVuZP;V4hG2CZt|;=6Ka=E*_+;JETVubB=>h-=G2^3gYfpTo5E(5jGUWlb}boj{ui z>7Gd|0CMid;rnhzo!Lv7i&e{Q_GOe7SvfteXPie{w-*beBz?J;QeI-5ckZS-eGnT# zVYg@3_x;sCrm1BJ1fefv-aH9sm+V$YH$K)%AR1P(S2?q#E>kQLBzLE~tCC#HzO{U_ zOmqx`qiDv$oyc(>pLne9dWI%(&(7aI%@K2Q4%2p(sw043ME`Q*1^@IGw^blsIHg&W z)kj^;B!;qppX@ljS^(w$lPCBmu_~O>DBLzPKwXkA9>2fO@JptI|J+X&Q$#jU=Zr=U zMH66K3#P3R>{mkWx1Z?QmkzO8wwYBPc4x6ILHzNyuIvve=vql^69xHrjie$z!sDPYnpDM(S|5c zm$PL45QHB&YE5&i+ddwa=cNVHhKlVC9g&O?F51$KV!r< zhI-7v;tbys-6IJaC0?C3qByA2s0@W!JCkj_4wi&OiA3}~?AxBbIF#Z@Mx8Q!Qr=}` z&Q=peJY^&I^c`txXu_{@Oq#Uv!3&`5+e@LrT8jpJ<#@vZ`L-RDRL0Bd!n^8Xv~Ebp zGo!H?&56a&m;JXnKOC6nv@wPjkzb&*F6Y!)AmfnCv}}#k6{B2&krW7{EM?^z>60kH zAvVqKSnA{>2Uk|G?OxrRGNT3#hYJK%R%R4_Nt(^F65`T~84;317UxVc14w7ggqVCX|3VundG&ZN=ibij?vk~Lnd zk&Ra6K3D;W=Z?=G?jmF3Oy?6_#~j>VoS*{zm?GX>!;2ego!1 z8qjAjXpV#JWR3D2u^FSfb7ytx?Cu6hXtc_yf=Vscxeta{I1;RdMakK=J#XD_aZnHP zW*KfT?IOv(CZI{HZU4J-6(-V4uyg8mIWrg{jjhEuEl@^tM9p&EX}{&;lV|Go0;VeZ zY`h*pH3)S%@%ReWCPS2YRQ;i7*1TVdGU2*as-5tUXa~|;&)o@yS3{gpfSpaHs+kZk zIgPy#*)eNn7eZVf+3ciNB2d8ECh@eC7Q~&`&0EQpLn*8&HX>=;j41M4J>xSVsD#JU zka-wy?b&0@l%*1)qnoIq%KNe>!`mmnx}H%c-J~qU%!X;#6N&A_IxOl?4|XJSk0exz z0)vdbVPHi>MQ&PaFfI13oMf~3a+N;GXE#4cYB-y8+E#G*x*QRovc#{3%*Q?;!sj@T z^U|}Mop8AUzq1dd9O)Z5M4m`}`4pw=r@I*r&^MLYRSk*;hmK_bN&KEDQ% zucebBK=OJ)Xcz^mca60s?Hyt;CLDdE%?_yC`qHYIM80_Mo1aI>rc?96_ZotazrGT- zR$A#3!OQL{%2`;8BA_Dm%Si;j;DR9j41A5(HGf= zIxTj`m1{KQsCC-R<>L*hODwzAqw!aF1~a^L>>E4}qd7>fF#3Dg_#Hx5OB4l^@>S~~ zMP$qyXm=8$XXZ!T@^JI4^W)!Az!Fe+DgvOPp^2x)#aH?Y#8)Bkd2TFJ3!9xWk&f$y zT3zhhCs<#pE`^Q!I2|WE5TF+}$!z8NbB*?J0Cwq}t$6lJHiE_C;u13>3IpZRf!-A> zYw)X*Ud$tY`I`l++=XmzjODWJ%Sa>W%})1A5rXz+%dcgl{kQ2!Va@|zR=ee9-rytH zP)2=VM0``wDO$@0D3hq;{HsKGjdBYLP|K%3MSR;sBc+gOn4gDJ0xcv<)6dxJCIy2D zwa7xZ!j+hfUfR_5jqqshrHwiz>vq_!An>xTl(Ka6fsVh%hNf8QQ-UCsjOEeaqQYEk zzbynJefap>Q>pu9m9rPN(X^K5 z{Go?Ucu8FUqW-(b{O_fw zyD(qlFLg7hM`qiS!_iwlznjl_1<%#<^Tn(BL<|Bsx)FC=H&L{)3=;8XBvGSkE05wP zWtS?b1F+8Kz7?3&)Zig!#&uIilYLjqoUz_)TcXj;tZ1axmq`l=}Z983iU1Ip{ffb))1g37IFuy)kc%bhG>yl8vejz|01 zEFt&v~S?m8Idi?fj1 zP{P0|Z%%Jr(scvz zelAj|_vEhD#iUXc!A}hD|4L%cv|D9en>HRjwj}k`j1W2ZI-6vz|JDy@KVYTvItKhS zz_U&E%bR*zN3R?b@gj>MRTQkO&eT+#(+a@uaiH?fF-W@%9~M?3kiF^V0gu?_OF)rF z!}SD?xhmcu6d`q=j$p*M4`$N%>g5-EOi=}hHnO!ijZLL;tL7vNowUyNUihkJ<2q4XU?>W;nR*5`XW*1 zAf`@BDklZJa{TMXi<<6dO+UV1_VLI=F3|UZ?rY>T1*O!wB!ejr_T&})I+3k#IqubM zR~@r2_njKZ`GK!a0gl{(V#IeAkU^wBoNLVSa+*lglcl=qFp+wVBxF|;T_~0E8NZ;W zo6t*GEA>#48-&xX($^a0B|{A(3+wgzLnb-ny&U5&_PA5nXg^lg&IHEe&Esc}&`|+} zyGhr)<7jg4QrgwC6^~n&YR_p5un`G4MCeO8=0zssP?GQ&ja{NIya~x9V@Y&GQVKUK z$t2WLDmp?k*D4n@8R6y_X_eBHlLml+$yM~_6>1wvs9WLym|qS2Ag!*N(C{UJq{0!v zNV*Wa%V)M~6@2ToEWp#LY3ukBA&9@C*cpQkAW0mywqovRt8CZpv9p_4MmGP<%Bkb+ z`$7+e?P+n(-8#Kb*l z$cve?)M&A)Pl&vST>k4Si=gn}gG%)sgC^lb!a=SO$@Vt~rkfZH;=UQ>P|wr={?ngx zE1&8ihf)fBfz281*``!|d&)#O`Nepbm+O4YODq!LvsdZlVHN<~{#Ms88SlW6Zk?Hx zH)-XJFmLTxOo>z`H_3)Y72V?5(GKGUBjkD8*H>Q5+!^EiM_*q81{L6$((%9?11b%3kteG}$;@x5G$@Ap&M1 zdpZg)t98f8M94idUhZw#nNX4g>XrgqqC=ajAKQKW(dgWf)KDOrm;EUk0I(`WhOt24 z*U0E~d0D|*E}jH6<*xOYg9PGjG`oQ+x=4AXNr$nujBG4)Y9~D1{bU^D;dUutXk67I zusMRqDr26IegYON%7t!#LIaG|2*@Xnt!5XQ(P#=cAh;eFK}wksha{%$Xdhe1uH+l# zgS!NUt)$c~|31BL_)B%U4aoiR9NE)QOh zAjyu57pIyg7FseH9}@V;;VX2hqSx11KFa+=6`m7pmskVmlvmG8xtx~I+zicFfv3#R-5Ex{qz|sO29$$yn~x! zvODLiY>XUpI^Yr#fp!qCNoIt(2$aqsXfnnUR)O_LcYLXdt#UG#?a#3BwYnH3<#ukl zH>m(zXTq*pjSgDXLr*V8$^vEVbS!9JUB z6^^2eLM{q`R_T)0x2Of&Ks*^gl9S*PG?x($tLCG*(}}10jVZ9ur{QR2jY|OoTt0e< z5=BLz5D+Avke%}CCoIPzztv3-a~+nzR-cJiWx@s*b2W0iw@!08bJb@mOWL+Aq_9VG zmwST}Wuny|sd2;`Xz<;X46`uiglZS#sicbX=6&Kb$>iv(Jc5k;0THqv9lG;V|1@`T z^2VtJn@gu25_DO& z#7x5S#SiM*Rc{a%KqYkW+Fx^4^yi#IN^NslVL^fa9N}v18op&OWzH4r5gK!*yueha2;=-kV3_I=%xR9 z0z9~Q+P%{0pR|X_GqkJ?5`RatEACiDkIg*wQ#_*z!}OaplwIYKsc>9&;&=HqV7S6Q;{rbAVeUy1a#)(1GJ>Fwls zDt2PzguQSq6ML0zM7_W@A%5a5(DJ&wl*`K6gwOtc&v2DJg}Fx6Z0^c%-Oc`UkUl;V zBZh%C5=hdldFy$MKJ8eQ0?^MKMpZ8hzTbz!r%Gr6_6%5`ZBE9I`1S6oopXED!w|;(Lzi5(0+rbgqyQy$ujlhYE$R0XNFnHD0B9S~M zJ4J-FI!h)=Tv2~23v1uwVs(;I0l^8o6f(n!Q12~8@a2{vx26v+czsq?peDSOh~kM1 zszWeT%>F8(ktYP5l5}?4L!$diAvPyNNl;0!w0!jN3sr-E&S~$V$^A|g$~!B>T$kj? z^JFKpJ2^%(YK_>f6z*QIA9Ssg3?ZRd8z-K29SqWSpBblvs5-`W-SSk}gYx^}RC_s= z!`!zntEtUZSA&d=eSeyOxSbhz`7!jUh>%6Y5h6#yZ*OkT+NPVWW6&EozPOk1Y^RE5 zC#yEOmmJokS~q5&(ygOCB<{SH^7yQpVjeK+y-dir1C)W z880)|>bWC^?kW_wz9g%@q@*V|Sv*XHSO5(>Lv04m44t&-8;88``SXnd0nCv4z?3uq^i7>*%nkovdP z&OT11;?UWS7%-Z<8ipA}nBcMbVadU$iiTdd)NaJAfHrAz-m|&~hFlFh!{GV{58RHp zjYAX=#d@Ly8ahB!Ig?Sc#i2D!M!~HLkKzj5L8E2~@-8vPV!* zmJ3i0^unb=t8gp~aajub_BYTP^v6=xD7ABRn2~fzKByz6bXiM`s5O&@OnwLF02x32 zNn=g0f=5rolcEJF5Dd|ktFPY94EO!%xm#2<+1og8KWe-5JK35)+bFnBFFViI*I!XR zbluI+E|2;c&-OBYg6K=iBcV0OCY44ttLt5!2MapgSe*oVY_f#1ZIClC5VN5R26sxo zxu`1pr3O-goK}V|e6rR=TkOS=lb!z9keddUV-ZPEz$}XPy;+Y1wXbOMTJ@0x@VG1LDB%AXHGz>vE%rCieC!Q7`xSPzX5{SC0gVX#RSyRwu`U z_FbnG1GjdP#^mz5Sy1{IN_y{f!j}PLqi%+@yRQWJzZ!wK@(5x5RhRj%?Mg$=8RW|7 zq29X?(Cvb%OcZa4J>B&@89pY&y!#>Np$j6P@^&Gey@n3z32#ZLhW7f2*`Q)s( z%B^WO{+TGIwVZ*iODj7T9_224?DLOpPuQLj$W)wT)`WNZRtEl!SQk#e7?UbjiaTjniI}PA zjE@5^>E!UBF_Fer=E+8NPPc)Tdo~~z3)IqV_hV!+6z$k(-jo2*BWu)R-}i#U2`VS! zaqCML2%1*X&isgLALy_We{$JLQ{JCNNZ?N|NNpktuUG@Jv zb_#Xuz&n`ea>KQlFY4AYXzR5eMd{W{>+o{%;|33)J3fy6{=y%Xc2u;=6BXe^ z%86krJtD+_F&0lTXDeFJGFxc&6vyFaTVj7>;={&?DXYfJfy2m>F1uwdxBrZYpp`7( zi>xfPk>p$lmNy{}_8d<0`b$l`RAOO_`{DyyLSQL9#6wxit2l23CFXD{bJHz^?yksY zRV0H1y|kWKWNel~gUHMe9PK}rlo^%#{%nu1&qwME56rr=OmC`K6`=fSGUu%FI^*M! zuZss^* zLN=>_d1IFO#shZ?tn<9;&mD3HVfS2fhjzZFt4^EOU$wA^=qvG`@?+{j;%+0C@cfS6 z+0yX7BpaUc=hVcT_?&m=(&W6;o1B^1cww7+XO_C}O>VgRGO3s>ijP?x-2c2KZdyx$ zA3DV6U&~;>>1|4kH9UQQ<_MozyEh~dd1p8di#73`j2Y^U=1I$r-aj;QG1JL#VdCas zs{W}ic{s5)vqrC&kJ0O8IruopJJ^mX4R7kQyn^^pAKHnt4PFp4u0~%cCIg?xctFSL z?F(Z#5}+4%CIgkdk|A=bASNn}zF*T{I|Podxauy|m9a>{(|eHqSha1u+WKZ`<+6?1 z1lIYds93+XHYW*nVev^RBhgt}=zCD9cT~J=TN}E{KjIG3?Ox)O!%vq=z1( zapn=q&6WR7NUOGvwO)p{NG6s9uXza!u@4r;Zof}x^^oF=mHM!Oy_q~mJ#2SnylZcR{9HQtaKtOSC4c_71k@Mv@94yospaO39Zj??zZkgd{VK5Ti<2L>f!n5Ob$&beuijt=*icf zcn8y9I`z!3=`s5X%4OodnX_EbHF*^6<~c|~=<Z0!4w)aGb_n^oGki13kXALVZ77=+(z2)lgO^c(qKWudW)6_KUSgv z%4g9;hwFP7AQ>lbSCYYArhZEfJZ8a?FzkXsP;sb&Yx(f1U3GT@JU?tc)%+3pYr=T5 z0CQ@v+UIAA>uepeZbX8bxCS^^=ULYK4oMg=vMu* zh{`1heE@~a!++i3E~xi8v;H&UAP1u<^&zzX&NeC}l?yZ{oR`Ku@-C`Lrrwa;qbC*NK!@HGs?%f~NS+g@$ z#$Z#U*3*P>aNz4{oujTm<2I*4C!7y9rWQ!F(rNL{aXw)Tw8p%wO(5&!?jz)kIvN55 zYYRcQcDevT{1&WM%ks}>91_Q%dI@r_{KO0`V5VF~Ymj?@v9csGE zFAzFkWhFna-uT{uRC7PvewwC}T10@O*+#t|n;zt?QoT21eaCF>Hu%EwRvTFo*z&zj z>^soItW34&fG!^fwncN5n&5Mmbcn^hg*hZ~;{$bW@rr%cDQiRfb+tY?2j1Ws$gg}x z%}TY;q$H;|EQt#HNxFr6&gUkI=vaDeMPuKKu$SNn6B}hG%Y@`M%d8#<2j;P2ql+Hp zk#f|?V0_^e()LfW8Sm1=QS$W($6(@<2dQc4=>-)glz5YqZ6taWC_zr>jHdbf9g51W z>C8ywrf62q16UfzExS3F676b`XC6%2{5{$}2gHu{TcB78dpqKc;|=2=%3k-+x-#y8 z2U|F^%M`iCgj{c0TCW)l-~}@T{14jR0xGg*$sdHq8*SXBad&rz!rk573Td=)hsNC- zckRX<8h3YhFWi>zn|W{EoBhw3vuAftmgKpWxANYI$cU(@$X^76qqZ}Nm1i~v)N~kA zSGJ@ww#ENkHnYsngvJ_xw9JxkI3&F@KzULoH>3VO@iT)IZjx|F-fix{hN6s+z+2lR z;l7zw2~RnI&ljOdksAL*)x);}o5`!}i`m?1S%~xSB)pUk#8treAG3G;x5aw~qOINK z2)c-p1aP`wL)ws9NOfN(N@di$BUC(KZLrZNN|Vw>)dk9uNGf~k?b}Fk$s#l4Dtmre zV`Se9uQZveeY#yGCqA##1J+%gw(C=5me+i$f7s|6o0y-O?TfoXfO@Pb7xbB8zDCfG|EI8{AI!13FlYFhimAYh6B9*}GM z%wU-5TGuerObkEJHR78|hG+bSDj88?`gK( z4t--%5E5Tw@C8xksHp*2zy0)g^NR--kz$tf@%}vSRlQEapr#l$@Haql2ae*JI~Gwn z)H;2&@O|yc;}PSfTFglBz9d&HqT21zY#}c zeAZ!hbrp?80@lB95QHJzg5{5r<1Oa*WwXy;*!UzFmw5v}N>`=XoZx34o61CN9ZI!s zDE3qJyn&tDa`oN*z{>59xCqte2p4RG3^_>Naj!c**%Y~LZoj+viRA~&G1eG};@_lz z*ix9yfz_vyuhuFVp*6VXpId^(3aeKwaC^5+v&n{vzUUF5;v;>+WwbT;rcE-utn$1* zD7`N4b>@pj7x;=D*zhBjjB07HOVOzO&rd56W=8#@m9b$@n@70>5ur8pIxFNaH+^)i zQcRjo+ZU)zIDNZKf^1uw~Bb$-q3eh_br@;umrF$OOIG%9TPFcz7KKiWTz3P zNHYbW;>$kKcqr*9T1lWzYws@vV+qnWm1uGhucDmR!P|c z5&1~bAfa}FB^e@5W0CtaKJt6sd*&}vu%`N~S*DUPpb%`Rl%t)+>~Bc*QsrMG$&R}W z3F>Zj=d9v`@YGy^KHTcrW|@cDLoYl?S^2HIYV_Etl(d%Vr&6*(A_ql)W`Ry7u2#N)+(F7BJBkjhK z-qq7u2x%~rr$?-w^@ZOwAh3vbAG)pXsEvc{9j129smo!~99xODO>ZZtloI z@dZ5r`Hrf?;M8!gT>KHpg^7i?8g^cPTNT`{0sp z(+PFtM1E2et)xk4TVdhA_PSoJhi538?xiS5v_=hKwKq-!7X7W)OzwN9cD|iqcjp6!H`0>!LCdEj zUy|8qbz{*X!_SsWLyz8o%ygYZ_4Xu5RW+9OI8cWcHzuNPzDwwG1mq~k&wN-e4pQ(1 z30tSVW=46r7g9eFu2M8X^`Y}_*BUk@!9pFhRogwNmWiGw+?Zh0I*_)BNmz@IyTqv7 z7wH89$l7MObRY5gHX}7Y;qV=>h9tecr`>}KF7Dy!-z3XRaevB&;T@D#<;n0$&uD(t zrdYaI&@hC=D6vw1r0e||H{F`p+MGj$CL1|)hU%F&8M6+DIY$p3-*U6qJ>ksvaxdJ| z!|qg5Ycx>1HmrU{^phid)FU`$2Jh_87GC2!g})iieOP~~zNg?SS)18UVX1C>UF*_l z=Jd}4q`kvFdvZe=3){m zy`_&HTSF%ErLGg%QOk(oDEV|y%@ zZ2%p-L;Vt_eM&8*n~oAHtWa7TOI?fdwQvDtwZ^gKha@=}f7|dh_=TBc)Am_o(mime zEuSEXm*Q=NjP6uY`%A~AG#b+w*t!BI_cHUhC(t_-6@KL;~mg=&=Ho+%FthQ`i*J>tEZ`owkk_)8&*3#lO8T_$ipRm=zDr%+l$dpf99+0-crq-$#_+vg zE(vTz}KR!XeOTjP}Ory!N#DvQ%u z6{}LG79**~3HP9K=q(L`Kao~$BSvB8^>Yj@t5mr=@AcD;w zCfj5@tDb?T*s+Z7;7qWUMdn3n?})4_-~VY$HRBUeM_QumLMoV9T}EqB$SQl0ci6$< zoXUQsJME3V7SCwgMu=gN%UF2PkgF%AX~e08er{%sHMZPm@w_bvgk2F2%Q z8PzPs%=L{URYObdaiizBAM8{^hbtA%lo(AGe<;v?-^HmffNx31%(=lr?d;BuV+6OT z6se0%oN#~;_N4Io&XgP|d?#CR?bsDr>1g2ANw%nrS3@57beMHb;@JJ0<+PnWtAk~5 z38*qCC0$FXzhMLf#%MR)Dx`NPZ*YiV#jby(M>xPS+7X8TMi8pl3yAd#<`aqM8=e&? z)Oss_sO?=cr)rjvR3;AJs4`WCYbrplc6Jjv#8uXWduz&Qsz$oT^%BY;CHeB&Za3-*^i$rslTj@6I^sM zQ7&BE?Byw%<;ImO$9|>2->i{=`!Dc@fgj*-!`3er;GT6Vad$d`(`CvkL_61PF zK(}s&75|R#Ak08Xz192z=pn;CoUS2Ft;Sbwi04B)C)b^GX1d~CHz6!(+^h8e@u03V zd`x+sZdUC4#GFaB2-tzoVPz!DO{}|^X2@F!1`o{521|^FWJvf4Q`^u*f|x3WO2X)8_25ffn_Cxe>^G%DMdxp^eOy+xEq*oKqDeIhd+0dP-zq zLB`m#)w$1j)OP& z->=k%A+}CS$C=NJxN00c!STP(I_f%el-Qke1z^Hsizk~Cg7gxj1wp;E+6kL^NAgA0 zDLWW}AAc9q30`snexn{41c!zClv2t^yr}##D_=0SWOK|4k#;_8Zp!yd!)D4rlkB2` zX~Ny&x!yO<)YTdx?#v&xRQe>pP|z7Ijp&Sb?ja9pjA!p*3mZr{S*AqJ=cVJyd47qv z#h!K87oHnpi<9aS8RQCR?uf2NlRirfrI4kh{bOv!e)B>0ySTd>vFA!+yfd38jfCe3M`LlJZ~D`k%M}1|A$!i|80}o|NB_BxCc;D z1^9t1`hj06slxKtHo(7kR(%Z;Q`PZ#+|8vBfg`JJ_ z-y`0Q+I9}B9H?*hUGM%x8saIm@$pnm!eE^o4Ds`oKJG;E+cmWd((>N0HMOT(j$Gd6`)N}QNN#ga=HJxfG^#OS)Ee8K8d@kWuu@h+1u;_$2-PER z_Rc)(E9O_mP8N1AAHrUmJ2lW7P@)p805efFe1+UwQOP(@oA|3NmY{U4B+(T=I0f7Bu}dcx}`C3@bY@B+zc<^5qro7dnRj$kyvf% z`BRDNPdOWlG1#gl@3Bo7tGA0=X5!zrUDD%W1{8_g_CAi-t0CCBzC8~`+N+yG#CR{c zB(bz$fV<`sr)XSQSfwW&li!cwgeG3nK`!7Z4aXOe4>_w}6h#;UfP1P63?YWW>eBs8 z>OAYIz0@jsYfestGEN4KHr@HHAyv;AO~cSlPsQW=t%Iieqw_<28FqH*@BW*`UC0qf zbUxAr)^uV~$0psDTS3f0dbvf?2`3?JaS85{re8`&Ls!a{*JH5`z81!JQYmh&^8(-$_`gZtqQ(oImu`G@v)2bEp!W5>Pl%gM@r$O~ zQ^|ijHx?d7!Nlh#M2j38OeOhUhX(Z{CJ>$tG_;K`{C<9Tn);Ky24^4w67$oe&S$B8 zlz|%R)S=SN<qVB9vwkWz&R7g@KY|pVSwB2BsWkDOk+Fyl5V`l?l?y=7g~4Y#-n%pAzhAzqSsN zoZNKnBbssm`eUm#;2Xq|&!qt_1ws7I|pGZOHJ zM5pWm5_DUJa1HX=)Xe4IC`!>gPLsH8?7SKwcU-ycd8=$1fYHWyJE%290nfuW$QxZ7 zzXn`u&c|n+Jzi*ynhRt$;F_DB+z-Lpzcq^MwYnhI9%<6ZhfNY6F+mmHQc1M9h84l<+#XdxxxrP&t)>X z)q}Diam2Kr2*6=A;&Au%*CdOTvlL+Wn|G{aj_8hxtFi4-9US^x`?3*KypMcObw3Fi zIt20M&*ub~?gdzM2^4biAKccrm8vmy@f1ta$u0oX^8Mx@TLhBX(R9M%bfBOl(+k z>l^F7Cp-OciX*9vz?lh5!TqkGPYhA_Fl|rRr2(k#F<^zRQNQDcb4R+S-eTFvDTFnuzs_3G(`R4A=hGY7JXnEQ3DULX|HY48Fk*fXVuC;(E`9JqmFaC6hU+HGt zn(lZ;R^2+N%RrVTn6)F=JktjrVFXEpV$gy2Cs81A2%(pNrLeMZI)f_?%{D+pu$>IK z`NW_LUZ7#h7^^oimV%7R*)t2y)r`?~6*G03z22l`<&=||5gRmd0+rJS84HPmY>8q0 zDXx-xt0|!JTFvQT^_FUhfo52P%gGZ>^w!koZMST;y>qBg99-43cnjrlp|qYjm25cE z)*8S)_FDFe*Drl?7LZ0d#?i%cDx~wTV8TndL3TOI;CXZV$*Bc)z2C~xQwKHKilgLi zN>L^q;SKHxP<^{NM)0?PH*hp!$PronYE%gb`PK*#s#lR|7Iku$yEebac|{!G!tbad zM`e)*o=UKG>An0A8V*igT7)h!(yiw*H4tp>9r?yG;kKB2Y=Kx2>vnv(#4~;MKL2UI z8_>9ekkt!xx4`sHO&gzZ-`rLOZXlJ5AS>X{7!)3nc&+Iz;sHc>;-&>%60J<~%{y$f zDr7THN0lx{ZP501BPk%&?W`-)4Vf%njd%7+o%RzJI;((3{(`&fVa3)mcmp1YmM$8f zDbHNgH$PoaATh>V!BjowWUOX#r(wQ#e4zBOKFy*}q+hesEXbvD#%7p5EkHku(%~kG zsULiE$HPrIRu{A~jmv0Zlu}>Rmy_xi|K`tn)wxisSfxS|yM#v+G zvYS}TBAOSKOrRsm>ri1)Rdr<1WO`TZogzq=PtmmNVrS|9$?7UqP~&q}F-gT*Yl+g$i#VcZXybwq4fnF(;k}@S`{xT(>Rwq+>enCN0T*ndkgCf1 z4|OJ>%;M$_eRsKv4ktr4<%c>SjfNqkrG2E7r-5}g51pi_WIEqdfn$+sa=K$@ahXTk z+2(TV*|nG&(W=)ChSLqThiK-&Hqw#WBz{}$KP{0Wmi+Dpfrkj(Nb|aZ<5PSXl}Cr% zt4o@LPYK;uRN-jbDl5+$E62qeMoOdyGOUdWj!)F?-7o1>=EFW$)^^k4L9NS*%cR{AY2goWP@`)_j_w<@#WQnn1{?IR?iXW!V*o z!W5a*&t&HXPqPOfv6YI0p$0tP>Eqeevd58jh0QZgcsd=&^F2Rl`%BH(KGoUjyCbj4 zQc2IBdwey4Z%NExtyxTKR@&JN(XO3)Nv__f(*&z$jI(o;%saASDO{E=M~Q{J=L??p zcJ(SVS?PJ23!J{TRlGq?p&%+sFSZPjetLjd1wnNu>QR~?eqG)I#XMZa&!q-2)btom zg90l0_v<5saFujagWs;nF~2Abx2OESo+T>$-_H71OafIa zpsg8|thgw>qOv$W6B8R3H?c3VxSFgmvH1r?iKv{4ve4C+6h(4_pvp4knI|-v3k+ftii#zh$!Q zY1%lTYaqPF^!Z&1re66Nz>zdUsrHF}5#AQ<4<%2d_%g(x&4K!O&rdkPfX9|Gq**AZ z26xGKUh8w_GU4HrrhQG{56BLOPjKIDqkM59k4OGJyz8V^L#70)8BeWBM~x1luL_8v zZb+=7Y#YBs$KS)H_MoYS3Zqdsae`tX+vZUFoR(T2$Y>0+p!uijD;C+dP2pjf=rB6J zlk=DEFxHpBFfpBq&>Ura@rP2l-y&6V(s$d~D_x`qmrTrVeZNz(wtRZ#14LWEIbeE7 zu?Vs)76ZHl4XPlqJ$}p2hZ-r5v|(zO!0)*D>UUl^8J8lxRzA z@!iF!wpXY9`~#jLLPeBT+NA*50Y>@!alv#nT^6dpa^IRMM6BBSQY2Knw>rKK(ew}A zL@2Xd$D^`x7(gs{W&cD*$_R?w#5tJ~h?P?Xl5riu(Z%m!W<`huViFdjQURn6n{F%t zk#;bezb`Vj6bX&Mny`NUQRYVPC2^KuW*NTRm3ASM*Y;e%=ad|K&S2DYY11;uvCTGc z(-$LmV4XGE0VJ7$vBDN^G51U~;cmiVT*Uu2HaP4J6N{(z!=>a6ZOnorF zNED~KP!F-m5MT%_SaE3(d?G`F@;nrUGDQvv$&js6o)XeLg9CpHv(y>!{^+#bWKu=_ z1ZNjS7{-7;B`T%CoJm4udE|WEC$J z)ssiV+9ccmy>29xM3d3`dg%UIX*qm=j)(=F3$$sw!X@b9haa+!kx((g0)BwVv$gjr3Jum-dNPEdak zT(Kt1xbqKbm2v!e|6g=yWwOQH&JA3t&M}zrE^N0f+JD-|7{|gJ1XspH&O>-*W-oZG zg=1-}yJ!64W;Ta(B07uD@29LqgZN#4H7vgIe{aG2WIvdqmFtU*?Pw-{Yv#?gIZXw< zLEGQ<=IZLn+S2T#+uGmG$E3J*%QdYaPFEDR<=DrCQJem?sQ1f_s+heT$;j3ZR~9lI zk@-8rKLi{4vHQ!cHkS93fq6`#bCCm4eJ|-_s`KcfOSBIMKKN>CHKbj4yR=a7iMR0l4AI8jesy3Sc zY}Tl1?W(t5I~8Z^X!<56+o3xQ+}B#?tY_ME^xPaU4NQ^Z)eEN9>ilR;;`rhiF4#Qp z@9ggFZpvEon11_$8;r~q*{lx>PNWoXIINo-70>sJ)zfS2Qmc)0e=^pe1Fs8mCsIF|$Wbq!7^|Nfy2Wrl&hh5IXo+^d9osf- zUv7Or!+$?t6KvJgts1{0#5d5-bn~)dM@r7B#L^gxjI2L#ME zr%X_suy|x{rF}V1Ts3Q=JQOsqfLXV;hwr!Rof(Lx9+_Y=l5MDD7pZ+o<*W5b`V|bpLpvvltoh%`j&9R51VrR}#+Y6uVBlg=QorXyF{4aKqxR&@ z2d@Jj^_zrrX?6B>4>F8&t;dqC_yNTJ{Q?{+uK1o>>bU?XNXk19K&owl)=B6x^yMed z?3_a>U50hj0aUh`!WI09Hd`Ybqv)Ndu}St=#CcpYIrO7IzJ?fY?9fx`+qKwkLZS%ydr{1t!_pxw!s4e0Q1! z=Z$9eG??RV?z~|&(;&S}_EWB~kiJ1khMK$`tTK~+@v9WPs<8NEz%R`O@mj*)Rgn=@ zB`4jUMNmrt=RKYqzt>x6F!@1#s-g|&o+@u3|!k@$% z@w;^A7h2>rFa7#Fs4v6@N>b4t=aL&mgN}35r5W~hI^O;^7G1PAMwU26d2OpX>wSlM zV9Z*D@r=C!BX6TWtL$ZeXp4&LBrq^a9;uTu%-w+dW~X+Xk~vjJcG4KG6SfxSIg=yx zjgHOAW|-*P-4%CJ9pkP39?O@tCRSca>70)HqtK3Th7;0m(;2naiYv6lb4eFjVrp(r z`~D8&jVcOq_z9xawQSQ=sB@qEPgR9jFKad;cWA=40dDM8Qq@`o)ICUTwW=@hSyWuN zxZOXKAfZY#oOdgMZb`@BB{`ZHxv)^5j?z=^<;}!foab>!C`MTB2QNp|CZ?~ zA&mT7Jp%_wn*~T-+$8D&Sc6-Sy!-Ex^3K*YtA$#$mN3tXdz*TP4OtDdJ(k2YSu5nV zBv<5yn?R(N=6}4{SS=g(rFp)%v0nd@=C#UlL#OX~I$N}l6jQBe=K}YufQCX714%kP2`uR zT}rsNE0F|X?L4H=?A085@PIFvLLCnpx5`!+M76>ATE;CK3NI=N?n4|1Ld34Q10qiJ zVeqPVuNE_x4c<1L{PH_v#y*1D_(%r_$U2k`=MF?j7}58|JG7y_TOi7)-7(M9tcTx2 ze-HUM^w-FLzDe^99~eHbz^ zKuWp!J2MBW;)3E`SVf-5F!9I%>+kuGFy3hTx#PpgSfHY*SioI!RmX~pDnSnIvYyi; zUPD6A-;i;JVAR+?J-x>svxU?p6;~TYsO<6TTLOQ3Asac*|g+h8@cno@4^i4i}+- zsD^`(ikR3W=X8gY-^E1_sVuY09upzxb9E0DhXauUeWimFk?He49XjIDyeCMM@Wh7* zN0!2Bi}dcj=P8vXPs1Kss*PBZ0TD1nM@k`ik|l=Tb77N2Xf4?q;)iq9CK*f82ZU@& z@OfeehFh)p#B3CYR+7DzgK>MklyWk*QJ6cpRdqgJl6EM{;J^)IQ2Y zS@O>f=S%_9VYBj%o!H=(g%b7@O5=)zEJOqgcC2Ww>r0S$GLG{oOL#(yM*NB?(!uSD zc5+?v{0hF!!e%M3=FtQBKw|0Sej=2mE#J*Wv8Lg!2Z1c?Bz_TP#mcO}FJt15R&2;E znselA25({V#h8aUK-31cxxxmaw;#zKE?m?-i0DXwQ zkWB8#5%AHcMRAV9I#^#!Ca*Ks>{`Ahbv)=zc@6`Z+!n}?SD%+M%{`d}WB{@7DEP)M zA9)|{0l@)P-#a8VrkxMffFwW+J;-+4Wx39L1EK1?$h^)XgW;7UZ8bkp+T8LZjgToCrFK3)Uzg9ux|JsHUFy;A(;hD}Ml#>UOH!&@7=mLT{ zyqSga@#hf!Rr>VRF61qkFr-7wFVUbVC69567DRbi-T?K4YnSvcQeFN8&Hu?KfiSp3 zJXZLZSiG=%V2Ra^v{reH1%d_DE&G1O{92mRohpy*G{iEJm`|yMPPUijARHeiCXL?dcc2rsX0BMRvW~QH0vU}| z7JAgc)2@WoTAi0X+Z3-(3yUjEG-5(2aa#!@jY-}tcD&^9QFVc42%TaFhTj->b<0w} zo_+dTIkxv$#AK2NanF5U1SBSYGgYuHJRu>}IRZfk>RT{{X^SJ)vS(4hrI`>==OxRl zrrU@o)MW*+M++Am?euoOf8il-LPcILinSi^+GB!N@Y!y|c7)xZeRK2wO9N->Z?Q^_ zf9cs~{;K+goxe5-vLm)K5!Fy}67P!+Nj?j9EjEgY7VsEZzqB@q;bYpnesxr1+AM}I z?~ezy7zdr3OfAr{l`;4M{WBX3e{1v^TJQZo+#-uCvao7wxMqaZG!CrNxYE=2HH=Lx z>9P`mLsZ96o(WU7Y#E6U!{%ZA>Yfpeb0c+J6ICqhi2>c)UP6ER7w-kZ>rUS+-sj?g@bWJQjo|uJ) za#O_kjcILvF*X7Ep4Fkro8pnyLj*;++Ph53eT8dao>rj#wnLtUvEk&QE+t&hS}0{7 zU%5ArhFd9d<712Q-ZR^=2ryX`Y;sPOwXP(&OB1#&8c+x5m!~9NnBbsZbtL(3S`aDt zi+N8(-qde?&{^egI>!kA*HxR)j(_<|Z7XhDI7fXWWo2M%cKpFdEjsn`e%pG>Xv~DM z04N(wnfU&S`Sd@QAC%HgP>M&0C(ufmFJZ<_q@o39$dD>NIida$_KfE2i-|w5X(gYD z1%X6Dz4}km^EGYbljw50?I9iWe2|`+Xlv%ULE8oSDx*ZFf+I-9t$f~;owvfRe9fF) zhn}Hat&%+fXDd-FQc;!#;I^knPw51W@1&7HKJN`oxgH&gpgoG?4jrjHLhUNraB#k<>tE7o7RU13gdM!JS ztg)gw?MCWhH|X+pb7_&TB(M}aNWo{=Y!BQ1qu>wmiuqf-+DV`PAqBw`_}r3VplS3z zb!gJ1smdscK6Q!q^>tCcCIG;>IX=@qWjxu`y>(UE9t#l95+6US&AW8Q(a^Z!%2UoD zw=`}!vqH}h*`E%Ua`rKk$7izb`mhhzBb3>Lg8VNcCh9N$JHI}~sj^_pQaI=9P~X3@ zrXoOFeDF)@x32v!TJABsn$}Ex_jFps?xYnA$L3jWN^X3&(B4DGW1w5s!jU7FtXtsB ze$z7QRVfW+_k@7``M3$KJR|3Ye`PbJM@wiR4=hd;7ZrYMw>k$_lTeTC-4_)Xnv7*& z%Da>|G63Ajo8xQK#((_0p=J|WST8cn2(dC0XkX~fKWtpD$;Yp0%=vWl94Oq$$ZF~K%&*lg z>qjvk@aF9oqJ2UVJ9u`b$xm1?Wrsk!vb2gB%Ns`gv3|W^eQ}Z3Lq0T{{$atvse!i-#qPl-9p)Yoa@T-muL>)JyI$nj}o?)SS*`d}Wj z2NK{fa<2VR`LD(0w;k>hM5V_Qbb3dYaxLhYaP6gbN7l+e8Ms!}G(0{&G=#Lbw>Vu7 z0mc1o=^Jd7bDd0mkG0+RPyWCLL`b@1gb^mQ)}KHxVxJnux8Mp=neQJA6a1UlWpC-p%jS2BQ%6Od=6am zA^U3k`=yOqiAn6RcJ+0(O~Oq|!*0}p@pS=E{tuzhv2Fm$tcXVdP15zWc7+xJi| zlwvp(JS@-6^`Ei|Vy@kFL`rJm9T_^4mnrrh$2>$Y3scoUqnc9PD#xzAs^3tZ}A0pCX+|I%S5H2)ML z7qP$Y75n7;^q<=K?JrAUtgeChjW3%RBTwh?RgAE6P-Qld(v3BO*@Wh!6sv3rXg8L+ ztTL0yTx2g*Daj;;k*HuEQ%On5S1HcjL#eKu_}f##)Xae@_4y~%v{_oB*Mpfd2V&mm2CFw=yd1g_US!REqh`JL z0ry|tSZ5v0&%f3d`h5-|iVCwsWKm$(Uvr?j$fZSjz7`D0n%47XN)J_`yIZFZp2)<$ z?mC&Pb3K=Ib2p1#U&DtW(bC}x7@Il`l}t~WS=*7TEkxl7ZXKFf$7XR^T_={#93K}? za8>0w?O)ZKzb~Y`2#KljTE0RrFG|j6+>g9>`T)PG&79DFH5nO9jAkHEQ|2@FP}-`= zgL?cX>g)ndlteH-jDYwV`UU4mpqi3?E^8Yg@62<`@!`L);DUH6B~YOxM6E@3(mzc( zs;GYc$eaA5GA}wtWw~CRON}cu^&4VE3_{MjzRRDU)biW*yA@7&V-%>t^iBvTX%7)@ zHt5sTLAj_u1BZ(>#I=TcC@#d*#O#Y0yI*7aFJdAD<3J&~U>?ByOp~*ldcWxEdfYzc0QQ~$ed2#-{<8({y674Hu8uK}} ziCFoxWkr=UL}chI3 z)gs-Sm&uoXEkvc-W+m;UPRA^#E* zRUGX}UuQHzTm`ShqAavikjK}IUHj`<$mJ6}k?uoHhmzXn<%Kxevzc+N989>M1eyt) zKYP!^^cIoI>9d)2?j{;Qv!&dP&GF?~^Dbs-+e(L)z%WZgeXwk{AV+!fh=xSP=QdO} zh-d^I@q?W&TG;HW?2RijNzP`^B@`ospBwz755e;$1o&%ya_i@h)%i&S)Q>3n^$>5L zucua5E#+gT#er%bvRfw2EdpO1{-o)NP&M=s3I&WvsyNzZ;K{%{J_ZW!fp@ggin!FG z+GQ-G=paw(I#7y#cE&3ZNl>nLHHfxpQJ!h4F0!~OLh-zYzLh?YIPT^5HewIN`(e}9nXsFsuQCr-ysjK6T zDpAAxX*a4&TudKL(axb_Vq-OO%7s}KFk|!eMYrs(4XayUznVL778EwaRK*GyzJlG4 zo_)nn?h&zj9ldkg0e3yLu7w~ZP?+2)?I6J}iI@iRvDRNMkUP*TRZQVUZ^o-pBTl{> zi(kz_;Ck*nO5}pZ+emhpCL4dn!b1%-ayD|h581hhf_s(tBwU7FN5r0{%V~T zz%rmZ$9cNpHCt?ILO4ZHh83$#B!AoaP{WnlVidsjo0W5|Q+gD0hF9{LRL|J5eMZf) z{0|xgm$`o#_@VJ4L=AoZH4TsCs8BP3CrJh39hfcrsW|pNzG5Ky0zJmfv-0@UgXvt?Rt4tLv*%bS-duR#V#tSfOQAu~f5FyZth(na)p^%v1k)C2`i0 zdR05_Ytbf|%H{(q6&fKap2=>pju@7>Q9wy_ikR5J)2QRtGJU?7EV`J)%@CslhE{RE zlBN;5sSy_U5TiGPH)i=40UZZd^r}iOiA7=LuBI+ABbem-p!-9SJe}tK$=aI68u}W$ z8a<}U$!Ig)WcOhAA&NFpsG8c3TlwoFJ*KQnq*;cx$|!|0n#WouVGlfOthb1nC)!zx zw%}Er9v#QCz42|O;EY*Wdtttvi3p3;b&r8Gl% z!sv~Gxv}0huTy5RS>VS>XQ6S)hj8?~M`-Nr3HCE8yQY3*y1_`;ie$Px(Ao%OirS zTcEkcdpg@beY_s%2W5WUQkf8wkGp(Hh*Kfsb3t;B2%=mdg*igCe-kxt>h!p#rc*RR z8}Cu$f!8>q(=Du*LLFDee9~6-Zmngdgwe2-BXf6*>9k|D@k(u!`=|$9+k`pal-a1) zw>+%50#`ww()g&U18oyo(-f)+#~_XuY0G8ks!EpB$ltqsZemwiK|i`&r>R3>17EW( zm4b50*CHinJ!|R{eEn0DrwG3wRt|PM0($Bo5F4#Y=vTL?D}8{3zi{n<6%K&M(r0{e z(bLyzYdZq2r(p3?i4P%m+ATE*=1>V(AX%FrSqp&&q_ah`rM1P94Y8W?M8P*GEJM@= z!-LO&_>gw^BDJ+8C^So_)qWV&!Oz?B3hMJglC=musOSN4z}AUun;hb*Yi1qjj7$;> z*#2Q3=}@pdVIi2kXm^&Yu3N0tC4B znCN__5fN>X%Ht>4>!Tzf*JF^^4@|cwb3;}g3y&~A)_NKpJCNU**T#EzwT#f6$%g3L z0)!sw38*t7-izbO;7V`buO(L|Ha@gh4`FEk`!X=0y3cQe)p{mUv9@TYQ&*bfiSaV} zK4)8nR@)eZvcZ_%_(lPK0;JIOR_5dK8mE5hQs7r{0qLhzF$Zgw5&f3uNWz&s=3gJ^ zb1W>1bBt7sBSmpI*a#`w4%hwy}9VGg5UhE_sn2+{S#8RASy<;d&cPbX?6lYXUsw1N zf;qIbtTPfhJSFUIWC0n|6xvlBSC5lqy~P|xgx95V-lGK^X;(f80Uik>p6R+pgwm!P zzpnb1HCyf*Yk>uF=Xul0X&EE)vG$pqGH@;FBJA`vMTdJ93{ufeV~CJE`|JY+wT?5Z z-{2D)n#q^3txIFZ;niSxBqpBXj z5HYS=6SW}TN#TzRv zkB;fLZ4xaOwMuXXOilZkQK%s9-_`bbqbJh@=P%AEQq!soBZPSL5(&JGY+EH=(^;Ys zYEOK{v88V0h?t66_5>Fd_TdX!ifT^0zMfnTL$ft&u5jHD*tS2|SGLVcbXm8MN$GdF zvZ-au9%$;LsC;ISMjq}TK5I6XsTG~JEn-WRbipc=Hriu7xR$JmO#)tsJem~hO9yuv z<(@>~P4TqE(*Jz6gy-*ZGbx8bfwd(z`>ZO*IrRvn*NaGLOrvU!Dl(eNebG*)aLE1C zg28C}Yx>603!lDtEU`yelWEy+x-pbxuqJ-$7W#$C5r@tM>{du$Hg{CeuV%4-E zZg6@(h|)7&-<0Ie!l-tjf_her?O?cCkp;2f=<<%i_L1Znpc%6#@&U7)sVl9nn_@t% zkwI8|pBjo$Gh`dWq^U`_N|!C{iSLA+{Mdl9@a%c|ss}8H4$xYpc$06Dd{WQo_@&dd z{RM6&8l>~YTE8g^QIYf-&_3YyS*-_uOTsABqY~tGM6Sm={sgHlrZLSA!f>fWLVg}&qSiu0jUg}v>e?qP89_h@;LEJc;cnx)aJXclv6zT0U>^!h-zPiZ$8 z3ce<1!+72L>hX@(f@9GX-ZYh=*))SxWJF=!k7_8)k(Cu{#@!mfHZWhiQIE(q9BB*l z49O^MQ0D;EHvL(p6#F5CJ;+}w1R?g=^l;|OvxRd^k?)7?^e-7l{#NCa z)TNi`Kj?GsBiQcjyQujS|9=5iK&ih`@=JrHu#_u}m*z;zq?@IWq>nVSG|y^2&>FRi zw3leRv|nIWQ?8q$o2r|wTcz8mdqv-b-uWm!NPpP>f5fa?yhyAOAEc{*0Ghs1#E+msX1FaS{ThH(QYY>YyE_GO_uIP zQYJl0pGgnn++M(*&(@mRa$%R&Or4k`jlwY>7l%r@;wTj{Tok-6Dt!d>DN z^nyQ1<(dWxiZ{{y;_2)HdQhk#GJdPS0{wUryBp&|Ju77Y7G+F>C!rS=i#zFJIz@Pc zKEv~PC0)nnODEA)RK(7wkLXT3D+X&$)8=Sh>}g@4)Gj2k4J1gv$JvcynM~9q(=XX< zagBDD@Fp#zZIY4R74L=j+l2eYiPCP(G`0ZGfD7mnI$geq&e1eTFR_zIWHTsB>c;4H zzE~&)kzR;VWfsP?jd*r%#yC(RPDDv6dd{)v7t=99tif_U#t8{MXd#~C$6*wEfi`IC zg)TZtV`Uh1h@@xtPNSLfopghI5}hVrLwOhvE|t&69@o(aw2IcT6?@O4B?u+o#B=*t z%{XD3W}KWSvFdJ3}JdN`9ijFAg2s*MLm^ssT0debh5eQ?hF5!WQNnfTl8cL-yZ7E{~@9%k^#_suWthd9b)`n3l zkk)8=Ry34qN~AI>K|8Tb5CV*`XN^YFMZsII$IN$<{hzbTCfYxou5|FngK3tnq(2`xf{ps35tM96|`ElUeIabR>U2ll?ak)s?t%BW>$zkqHLPg_CO#ull}+>2 zv9%GSB^9ZyPwOOXw2ZD#lW;&1~P{J~I9=TtD18 z9vicNKmX0|w*t}JYTu~rYTxyH{qQroK6d)G_F3r`BRH(8vZ|s=kOLW?-|J^`OM1*? z+Bh7V5y4TDNxcD0bJf_%G@WW0+f>~!nKU+xw6btJ8w}O?M?;s-Tk87wlPEvHpxXIvW>0t^Ua?c3(3kFm0N@?ORVJ=C=p>|4|XFnt$iionLsi$-~Vx z`B}@V`Xk;4mVE1)I!uaZf?`&4YsuJQA_-JF$cV5aMb}YA=gX+~=8-(GxsN*f?I`z} zQCy`1fBReEAUtJR;hSuZw2zo%oUK*+A@2?-s%du9#!m9EPlcmxDG&QDB7!NT1VMP( zdT=d&aQ~4$^9Vd0&)LB>wo89;j@AYqkOXPKD`OzS&f{tRRhp{O75mp>GBE(?A$#0DWdZ7s}}RMi2?8QFU{3%eLMr z7c}IWh2Gxw+cIq>7heePJ&ks=`D`Iz&Ir3?5nCj%HrfWStRyThErJdu;-c@P-R;kt z2S{C8-{^YM4wD>{4xh$qX!q8ws3|?rtcKAGq{@yl9BivI#Ak@O0q$=Q`6!R%xwbfi z>gh#HrkJO&9LPr?=j|ZE!24T5IR;2(r$V_O3X};C3(p8lxSG%qZdahtPZK^S>|>DI zCV08nxip40cDT=UWUyKqmCavo?nPN-vtimu>85ps=_S&izX+iZm^$z$(UNw9K9n)P z?e!am@%5>GL)X7PRqh`6*tYOois89pVq1z=b)=kLaDLd1c)eernvk*e8`vr)w$Cy2 zf3_A+ic%=)^+v&Ie9UzT3A+T9$zu@%uaJmgKx^PNQU{9E3r#QZ2RT&gc+!)fbQqo_ z37Uzia zYPLpSR&D2 ztK4J09D9eoA-|!&>yHl(7e|Yn1md$UWLp%yYzUbYUE;CRl}+^?N<1d_tA}|H&Y}eN z@T@DhxLhnB-mp}>Xe}Y=V^Z+d6v34)-h-&vgYX_?T@syyc?2d69spV-^X;50GJ)pX zAtmI0`#|9{q#y)2de96sH#S5f0We#+vZ6W@G$V}-&6b&|tWe~s3-)ceddpQ`pTF;s z*RNf_W7D!_n>O9B?5sT7M@2gB>Diryfp-dp!Y?-8yPZB*_~Bm;LC!V*;I~(ymVW@M zcMP;nBk$N}XwJxatMM5U-fGS)cq?FZu|QnT?qK(+;?pAa5Lse^N1_I!uV|bV8gh|P zL^<&H9J_${)V8>KCAfO|xO#!i?GjWTS3|hA#0?1y0OOzCwhx~r(G=veOe)cPXe+&$ zIELTu@R9$(3C1}Pf<<%G!k8vc@{W7UX493HEGuIGY8u(GuG99N|HD7lT_s-kwPoc$ z{l+V^VU(?4uL^J>$znT*0+xXsP!VpqxuLBf!LM+m0@di`cI8-u$1=UKU{IdwMV+xM zP8_s7rU_IsBqdRUqSzss#JkCa5AGxloNcn3?X(T1MWd;5(}Ezg9PqL3^2xh_k3vUfgqcj4B<6=_7-@wGXaLW{%4zW{;S@G7K!h} zxAB+R&8JGI$~&d!<(dOgbqA|lb-?zZH#J4oCGOA?$M+QjF6u^IK7eM&GZEJY#}bH#78fnCDxA)=fClk!r?P^3E-*>( zVc_*;MO2QruxQnf@Bhoj`>wn30lFi2^tbzt{MQqE9-Woky!o`&xw~)J`_a4wcRg@x z@YT0J-8}utU5~A~cr;qzw1ER+1avP;yS5224)Wba4Md`I2z=`$F&l*!OAv~-ku~6i z)>LZXE&NGMs|hC)VzMS7)p#qtMyv#)iIj=fmQphOnb18`hv3^=hyO?*H-0?$dF*L#n41j9g5pkal0ymU6myn4%-<@GG>OsOb>6zZ)MhvjCIqoTT1p(Oa}-sOdrJP zbtAgzoki`ym>l$@h{uPs`9WCj-;Z|D=S1g@t^l%tb^y50_8AB-!IlU@F;@zuWsr3B z0~JKUmQ+?`rgfFyyk6zz+b||1P>0UMe+iOEz=}&+9y;l~@yX3}og^%BOVSwHg zyKnWgH!gc5^bq^r^>c4rxiYo&rOUQlGW&s1$)DZ6yYROI7%jvBu}p}8HQ?{|9mE*; z!hRb0v7G3wcEoyV<<$lBC&XIJ7}{txhAS<>qU@gjmF&U0UVO2uFow>4T-bK}tj7zF0F>R`zW{Lp3LGr(J&g9Z;$bfivzh#f^L$fLsmZ-tl}&~PJiIw2M0!D4{7dW_2(J8@y3 zj6ypI1#Wwhy)@y|lHqV7fG$k;i()e2^--e4z}fTQk`o-U(77PupjClM_3s6gL6E5l za3|>J?WFj%Ww(~y6MQ203*!yr-BQ&PjQMKgf~Q`p*L%RB2!J$ZPzwiw!B>3#kS`d5 zd>G)y4&p#;-v-Eme11Dji-X$k7wJBPB5*IZg~PLEo0!VqVT$Je15{!hRAQ9G%ovNg zpb}e`3hbg|h@ajKmN#~bZ|hfqOZmy*auU4cF&6?r;e5zj@WBewYIRgr0+l1&1##~~ z+aXW*(gM&>yaA92ro(9gfQE!a3PgsPsXq(fcg2leo7Y~jcKD{-+1vfwC$C(;o2plR z|M0K+X@`01ZF?WRf6L_Y5%$-o3s=u79Qo}_>$iM}h|&i76$U?4MrxU`1H$h^oHtf? zkx04RQeC3jRiny5HA*}A32%K|nRsuG92lu+PD)~&@M-0KT25zEftC(W+Ft7QLKIUf zRU|`RElEk0iQnSsiJ6R=s8dny(V{#(i57E--q(B0U%I-L?=$!2QMX1eD4}O4cKD2v zGg31H=cg73mnfI0^8=Tpu2R37xLIA5ctd?XVks#UY_)?KGEN5E8B%F}L%|!>smfFu zZ&*0WDP9KSET#J}cI-x%=8l=7!y#L%TozTinpHKZSyf9+u33=ln*eYy!9&|I_BGdy z0Aw3$2b0{YlN^|n9AcB*G-p?gkIs%>8C@O~qdfhKaxO+A_}yp(M;h&B!#cBrnTF%X zhN@nl zrkytRTkN!5mv!}D^V-V)DeQmnmX9~T*WWVv_H!0L_ULs>pA^sY&985(|JuPn%$-yC z`|ob;yMa!k%jl*THtsq8UjE4$-4EUS%rn5zi@~==q$h}%EV6xjy;Ou>rivbL9tbq` zjEWw^yF?HeGIBDH`2-gCt4lophfD@#n$3jqaJZ5#hXkm^S2RYf(Y3d>9qv2FJc8K* z=H(a*=B%6(_<_M;{XiyytW-7!0xcH{Th|u)CN=wa2seIyi}=OnwRaZ+g=5|CZl<5o zmma{1=y_l@C15pCQc3EC2|Gx_P1WNZhLu>+c8XUk_<0>~N4jxd%^-GXPITv)eFe9q z#Nc_HpVzpCHZnnHbW)avCj;IjMijhoaCjT98)W^65onu!H_w|phIy@WxV7KVil z>>lP%40D?fpQsOGkA#x=g%EZPynY-}Nqy z-bQYvYsFRS3Vo%q%KQE3e_JmG0~G)tTN0@_9#W|~Jd8|b5K~HOQU*!JhylacFp3W0 zvoPY=6{WQ(1$Zl~-Z)?}CX?G#{*pAx_6XZ~)w-Y#i~ae#?& zfQfN{i7k0nph7ph%nlFZH;3_?!}!f%OTum)=!!2H1v0~PUtUf%6rQ*px!RHH+DU|X=(ra4sREqIY1?J!= zyuI0c1NRaQTz;VZXpJU%+V_4rScn)hh!YW?UCTp0iyQU7c;I4<%~WOGC~rREZuRb#YR z3APnWr{vV|nS5aq6omAmFs?pArqduWd6#oIcv8E@QOO%bk@vsxz*<0y}rGBS4++jv}4k<`gxO{O@4Fc^e)jas7lYk zAza2stDQj?x99(*uY;dT+DI#fv=B@SnQB=PSmSTm^!J|X|Is6F)4$#~p(4>J^?Wgb z?kb$YX3~3hT=V_gF!HHb2$HJ76&6vPP&ut~UgZ+cN{{^Q_;;m6 z99*cq5`rP_%~uM zP@?Cty_ki>GO~do9=NCjb`|;oIe_h~~jq$73^pH`JI z68JPj!)F+%fz|i~BR&GgGbB0Euy-=W7aCHO z6Kdt*R&63x{tfT6&;{XXC6`MJ%B~CC7Pw!y&v$=fBYli*w0`dkk`RfTAu}%GqUe_4 zIUYxxIXq|j2^C8ri4{tdqQ}hm&mtMzHxn<9a?wS(=%QS7(M(FE0B=|(FmRM=NpkKi zXV*$L&qV;zz>O77=4wTq%_@0ZD}yj`F^$S%WyLUHYG7DngNQp6z|paAD1fd`?AkM~ z@QaW73UB`C8G8DjKhP1UKHs?Ku1)_tYvF-aKmH?QqyKX31^S)eeMF}|_u;QcZn*Q& z!e7?!EPQh7F7#{<0e;T}`|^`AT4D!M<@9vbu?Ndc`iUBKHF)Ss;t{)|I57_`=e2qd zS4@w_*IHxz3Rh?jsqykMlk>ymF}=xS2J_!m=)b!PebiOxPS^OWcuAq6; z_-G^=34}uo^t~$GP+TIZ1}%Sx{^O~cH_W(d$vI2c_ugE1j^@@sKKjhIA6{|J=E8qV zJ>jymzg2j3?-PZ>ri&XkH;+E^lb;;;doBL8-lKqRxIr$aSikQ2jJlG{0o#YPQ9?GlSQ_+xj>O`JG}o( z$S}Gdm=aDGKaYyTjz1)1kN;j+DfMhFjDNb|-3%jw6hpijX6PZ0+T-{P?@;LABw>ON zq*zL4EUy25%?eWx#@#=kO5sa$(oUWAFXy!1sf%Fb`Oov&D7<(4Blc|n6r9T`oBQV> z{wxIi*#Y=dMbEM0rJ>R=n^R3MQiC)g3>!w$fhemYNyY&pjN_nGjwXEqWVs$nGu2hY zTuU0}TGBAIBwpVdmJ$TuMD-kA)!)x&%A=HGdH)?QKOUtt;9MORTYtl$ud(q@)BX<^FWEsadg~3kr0cToAJi}EX#3{M$!i|oTR7Tr zaSOFjmX87IRiNcj0~bAZ+mT?nNfeSEZG-lj#x#jBT?NE&MW(tUQ&D6d4&^CDk#Vtx z#{qC3lUSg5-B!keM=g&BD31s79bW2XIv1GE1*UU>>8axWf!($SL-;q8T`em65LAp5 z4LIecDen~T9Pc8pc~DjSJ`e0$0h|+PgjypCgF4i z-oou;T}Z&~V>aglf&s&w5S?Sk@f{JJjZMyRWW947UgI1qtDIw5(mBTB&JK!Nui2E6 z)=AGuU`h~k-$6EzXNg!xY%+y>Kn@Wpkb;Zrh#)!ZXvo%Bk==iG*?rJuHyS1n*g3l& z72lXK#N(VkYx4@SMXz{Wkd`-A*^eh-GVz`2%zKM5D}NcJP!yp&xg zU&X#Fuko(2WDiG;E*(Lmo5mqw_j^39>Umt%^9-t*TC9i~`sjh*3?-|*y6r(q!z4?)&$HOZ#WYEn&~ z+2lb=Gr{hPe_u7@g!1D`vE``%W{xPyiTJ4~&4J;)zbyh}Bqt-U^*~Oo2<1dOltbQc ztpYNf8!{ukT0;hO~a7!>Dr)ScV$u9G%E;v&TO-Mh`#UfYe^ zK(bj!q{Q72S*~zElzA)gR^+Y3TLdG!5-G-mGKd&3TJfEztZ2Md+``#s-kuc|Xi&3T)B zli4KU48>O4ykGZe_p%?pG$4Zn5ud- z9UPC(XQG_u1UdpN(8D$oFCD!_N~zs+G$67^d=dI!@*C9 zTd3u}ikIR^%D>2@W;dI*JtfVNIwbIPY-6W|p+E`lQO>u<`Z-Qx4G7NSLr(YSNetrQ zlQ#0l%|2cmT75k)4Z#6${X_}qXT%sd23q1@z=-3h#wwHp>;g~o}?Tz54x+k-wagk z z2tpc+10}~aAx^V1+&=Otou>3D`W$_c-l0pnI+*GhJk{Ybpce-9@8vw=m&3rpoM%X= zlFesZxsdbihyOY53*e$vF1K3b5_a)k82E5Iz`UA*hHy;BxE*BJrP>p6Fz?;lCgfDR z!66%R3V=KoN4Av!+2D|PwbI!~u2<$1UkE-yJU_fG2xOT*qA7;- zs9q{=if;40=o6yRSSd@D+1BLX|ajF$Pi z7xHsm@bicJGpGU1zG|My5qSv0l_ch#NNL^TQGQU`ZU4O2I-hS3nk3yIV(Ee>SuG}M zY#>$>%T!j7xpWO}{xzNOR99i!^RE_qHvWp1z4vz zoNPbfvh<{#klXl{tPIbrEWVe97erOF=ui&ZBXQuLPuvxI+!cF#u%sT(1Y;DX?J!I(k)>W|5!hL5aI-;&07Lv^XCU4L$3vYJ)lC+jmsK~J#iPG?g!^xG zmSvp#(BCW`@xDC~h$`P%iL+AY>9Z0G6N^3H`@f8R349dg-Typu-^X6FSF)RAcXMnY zKoTG!no&7K%x@>NJCk{S&+qvDj?u3(Zk2B{9@L&Rb{mKEPYn~> zf@#YLS(afLsuW1jW$}p22S}zr7nP)l9gmgT;10W3bFUL7vuN8?SviQ2C}tR4EcKbH zIBCT5k4tmZrb`kWxwFwqDIg!KTlP983j2%wE(gOZOF`lERqt!!kPl4miKg>y?Lq{e3^R?cGP3T-79R^1-dD+u$D zInMY*)+cg4QRx#EF#YbqE|K+#oKI8|CY(s9DlM0xGfZW6w9!y8K0BdqUiyNH+1aJa zVr_|jMQB0vI^}xpdSk7*DzhTHp1DK0UAx1$+q^Y%bM`*%0po#ispoPHE6W8Exww?8 zMmdVAjtAILBXiUOEC;k<*ClRG(1~nB8&+DGMOiMw5gF-*uuF$YrKJ%DjDb9sXYDSq zOE&G0<6n2!{g-ftWiz^_aAnDo(u64REJO1sn<>Zpc&;=tEbb6izZdJ?!x3s2AlzWx znkbECpboSQbt4|_M%x^H7&#?5HNN6=BtPk-7{l@syQCadjjD-xr0X=v)jQ^-$ahx9 zN0q5XG97YC@Et(805P)3!2y361_t8lf%C~~jg9oM?)Iq%0G{$fYrequ;%jDKd!Cdc z=Z}%QfY%ubca!kuTmoBl4lXlP{00_Xa7-y(Kgx^zWT0@^t$*-ha^a92VQpAcL_Or% zp3^S*{n~4unl+380Rn<{3Q4rx9I8vgZ(b z7I~QUAx8oED0;&2s1J|)&6koVeW_S*-E#7c;;x5_krF5+?>o?b(1iNgRu76E_#x#3 zBql=#3nlCwg#@QP^UR5Vl1v+H`4bF3gj7e)8FSb<;;SMX+3lhE4eU5^B72Uw+StM! zG6a>PEm9`NOCeu#gnX_H`N(M~NBf=}J>bdFrWbqp*clGUMteGf(vcYvx+AhI(iLGM z-(!$M9L9Gu<+NAg;i?hY=U;h1jmWHrZ@6ki9#A84dziR$gKEUZ_okZd9`rh3@PkR3 zr`l1yj${<+%6d2OZD{C<8$T7`>eO0EgWqa4ckslSB^DT-^t6njgGr z)z@Q2YK3g)gp;Y`Pz_bZWaT<_gxaCrF5WJ6tG((GRY|KeRGOs~k@k`eC8R2ph`+M6 z6_Q}^r)5b>i(E()ISTVV&4p;1lkllNOUslfEfCQHT7-Z?RnrU+b&1^~evgo&(N0y< zB{aI1-bm9l*<+=-85})=>)^V%UhW9Tal7f;b}AiDxbRFTDfJ|;sOc6{$76@1Zb7w| zn?q7_T=*q4bKaaCl!5u=|L%|ih-}0V0SMjPQ-Z`);loA)5<@|sUGN7_$$u}BY-On4 z#aikSeMaB!|A^KOPn8ctcfHd06854@C)#9cf0vJn4x$Vc^zaC76d;7BdvNLbIU3WpL+~nr(nC_?HXh*L-1+K7;rZNrbxC+7w^F?!Y;a)$Lk2`F;b`Er)>hyv8#E|kk5Y!^IGPtQd&v0D zl{DQj)KD-GAPxJY*lTLp$x+cX*{T7HY@K;wQA$%B>9c}m7owt^D3*q!p>Q}FP$j7} z9KdA2QVk<*S|QW40+K35!<=E6Scu_E;+Uvu7?LE4G`^;2AYfUP7`N@Xd4_~$QfW%X zV;H|2ibFGZrAb~&EVdinx!pBL+vBmReeq~tUp&?qoi<^?_=5vhsE_;+1JvuA;^%@* zEye+dZZP|7(9OMj@zAo@r-}#6js|8&i*Ri~CJ9w8k7n`Cnn51*utgp3*{M35GuCC> zSMR$zcb7Te$kyh1V+u zJ5+cTOTN|z@BbpheApK+eEH8idzfFHn8>!@m0mFE+s%|G0ViYr4l?QIDbqt)4M16; z8Xl4j^?}4hx8jV5Ls#Z;ZsH>B)drHDg98<5PW_<4ip`oBiYRn-pgK4fjbX-$W2LcL zv)&jO6O;o%61)nKLH8n7nzt>EWI0PoC@bv;yRJpoDs+ym7OIpQJr@|wHjB*)`Np%w z^VxQ>O_`^kAGi`NU>A!^ltuc2z$*57k(i>_2CfaRXYUa1knd-Ai_ZmKVP6&h#Qu-? zp8js&Q}&Q}NIw{;<)OY^wXp3MA)_La5zC*icM`%|T8c`ALuORAcsDUzCzQ!kw1!1B zO#}Ey*b2|8yNcTJ0+J*|9-qKqlOky7nubhMvjV}Of@g%*6h;lo3gS&VD9OQKnvy~k zB{8(7rBx=Rstgv>3`5gFO;c4$tP7(sUJz;3QE7EIy5zaE+%5OYjJzA|e)bYiBJXx& zzQ-|VnEOn|#0NQYnu>+OFO?CAoS$}#ER*)=C$Yorhubj$E2VwNQrW-_Srw$J4gVMh zSqLrS-r|kB5cbXmY3rg#11t?rn?k_SSQ8=+TQt!WAo*sArl7lFNuf!iNi0t^kv>Q} zk_0;MbyCTuAa?E;{L=J@-4YB$?9)W-L$@$2rW69e4iDh(3^XZfN!e+LDk*DGWJ1w| zQiC?$7qsy{LeZESy2y%G9ri9yHHhocpw{r0pG1!-sGlNvR>jD(P~}^FeRTdv;oel) z$Z(;XK1u&q;kH$+GcH88_Dwzc4Xq4ooKadpq&2K(cc?V&U{{2QdKE@6Qndji6;je6 z(^rKN71<#tT#duBo;h;TH%CtR&c{)=evdK0p#&RQ{T@r%%|Mo#8Fn20(5E{CHd$() zIyxrU7#6WEpchHgojdbkvbl={!g7l4;D# z&*EF9sA-BhZ#sQ1@bt5egjGt&hbZ^p5`+o0fuseSc$l)y#u7V85`sllQrSKI$0(-%807JTJB0wJ zkRTL{Uzm|U+#Vwk#N6*?GT-JO>g+)L7Awkj3=|99K z+0&^iY7G5^Q!8mwO-zf|RBJUgP1@-2m_&2U(>I=4~Zs(+<3`as&eu6mu5KKFYm9dpV^e-0f=WOSaC(C9g`igbvI>3Wi}chgTf zS`>`^=>4H&QlJJdotjW7k4iF1^`+*e#WBaP{Y7_@blM<63gEG9S%!E}9;EW6>p^8$ z!gd*w*hb3WGOot}z~o|A+3_RC4rW@BE-fzFkk6Y~U_v{b z!vp>sL>BU&d_sJ-1Nqj&efa}!SCWCxcDg`~--v+%><`MMsm?4U(h$^P4E$?ssB|l& zPp1Kfh=fVEvWgtT3p(wV!r+6Lmif;w-ul9%6=ydtdH+gOKjF5Ut}EFVy?X!cw>>q( zlfPFpuEq-*g^R=#@JX>&WHop(-gEVMnp$^u$3@dmyOyk`^>{Urc&ka3pjVw65T_a$u92I-ajmIsDLR!ZPu3^T zOfE}xr}*YzOQa=!Zsgo}yV$PHG1?;+#}|uBwS~sjk*njqsrS_P?e}AU3w~*T8T)(5 z$Ep5QEX~y!b)gYltKo3x8Z)>nxc5u`#hx%#Gpw^bO(l|8^~m9*u0(xwG3t8?B$MCC z0&{2fE67wFr9f#^}xDeT7W(3U7v<=TMK1rx)-5tvHl1{`e|-Y-@opie(!553SSl8{TX`T#o2eh`TG7>px@Yx{zJ@REOq1PpU+cv{}HDg z(j4FpN-!EQn(jRni~Rit{U!q$3L*)8%dn_t14%`QCRqjPVL>D}On@6EKt&$u9)?F) zSZ}`lii`a1Z68Hm1QwVisVJ2^D|nVYD>%#U2zJ;%rGLu&M0?zPJg$mbOkPYcVit3& z)MZ+iwncqb+9f}$su6X)`gfYq%P%pmF>W##0}OY)yz)Kk=pTY_qdvK1P$7YHHCXoY{&uB1Q z9N-8C*x_tof;ce2=RH*XccHdhp4nnJ|=*665Kv&aI`Qo(Xe*_ zq;nahD3x@%_b40akui2I{_XN(B!afwPb0RP>df{7_&)%un3a6c0oiVKeFHT58URfR zPcbdqOTPNm`-T5q{@Lx%{3W$DcGJAuo_hS2#rL3F?dSHP5+py3=yh8kO)OdZ+qd3* z>4#Y6OvJqOky{&tUUY7hX;#Z>4cd5(YYa6eFQm_x&kM~;UP;gA7D$(eI+DGqx4CzM zAH+TheiHi1{v!4X$d*Vdm5&pFG$l@?lQ5jlXu~7TbfY$fo}f((O-^1YU!Yy7eZqel zIf0JpCJHmUVj5WHD1t>{p~DOjI$u8rLZ_b0=h5e27PFS&A25^&DuD^Irn%ojrsY^2 zR+ok465(7|I#~fC5-d>1L{3>e;d2Y5l?4zbnMX?}^Jw|$QI?+uMF^(@7ShUq+s4N2 zr~=#&$Or(fxxMpV6!r-p3H<^~_+z@j2&J%oK<^2q?z#e=0YgHF1JA@t8)g(q8sZ)R zAUPmhV5gfIiX~3V0S~JruR&2ma(>DhiDJW=&E*V|=~r9^J$Av~o8DQq`0blJ9;n;d zmwtNH>i>M=hBc3_|M^|tZr+HPJ7%6i>nA4Cfj3_J?^oV`V=vK2Q?N!V#gZnBx#Q=K zouZOqY+<)^?b2*z0ked=Mp~eVVYkO5+^Pf4d4wuSLZghpd)$f8@i;p&&>S0?JR>kQ zenxU;pe=S@^3uRn@k^6y_%-3<^zo=kMUbJ{_KXODgPBOu=r%W*v}v-5q%2T-=%>gk z@g;k&15;(<1$}=Iiv`>7J2IqEADA_^gMGZe08p&?O@TB&As5^~sj{YFn})P_ie#{6 za}8ws95I7ZC>0^Pp$+P)>s?{$)!+ahm>I#z)HL{W?XG%P0;G%PJqh#f%8De+IOLj> zc^|4_+Vc?IJb?FM9ykteq7O}z1Zl6tx23PM#Vd&QYRMqK(-#YFW=cpX1JoLoL2C}4 zxp+_QKc4@r@D&RElZWITw_bi%-~04Tb?gPV-}ofDz~0=0QdozosH*T`;Tto( zbCk7!S7VqB}zw#9m5Y>eDi zC!T635j93Nk}?X@`B0E$cuL+FLZSX3+{2*5dIer^Gi}v1FT;!qUZVRls!}-JQu0u!q!8KWKO-IPIcuC+zZ1ONOuR7g zGkIdiWp|yt0nyQx+fT{gP9wRWO1v1~&1`DN!zG_JX~+}Gld2pE z*JtaCo9!L->y^KDDk1QYjYjv|$g~~1!|t-#T0AB6>{^hV>-4p z+)k+=s|{GAMx5}9Q4S4AlH|;8e<=fGvk}YJt}G+sIX`W1nRa@CP_tMry_Vsh3y7t!Uv95mThDvFncr>c7^R&gDqOB6=FC<8A(nE zDYEM8T-Bd$D6*{q@F*)e^`jg5CDbdS2q@f$10{@AFowv)O2mV;pqLS?c_~hglRPMx z$48NghL|>VQX=J#@c#HNNO+zG!N}@{(GA-oM@)W5KL(ZCO?#Q zGeAvzRYyo)-ZbXkk4bB8%rqXHbHcGfTCjd0P*EP}3D*yxXb=xHxE<5NlV(JV4Y$s` zUj@{eKQ@#B{OVuV2Oy{q$O)a-g{;o238aZwLQn*(Sx4nb&(V6^8QS{g~x@*&{4Xv1xWce#f$| zt4EVFd(+Rt^s_QKKMRV2^%Vu{2ioB}Wx@*VH1Sj>SPm`n$yDcyyW_VnF9vsq{y;|v zJm0tV^z^V_?A!Nkn9Y6rKI#APSYak=hS?0Dan5o#kmtsIRW~56ySUU~P|tOSRTwpQ zzv~#osKThh$Z}b399z$==QvyBIDutpmJ3oyQ)ninvKFTZa7%OkEme3SX&K#EQ`G2|9{r4is*D}d=JrQq$WG zTc(*LBG5^-P9?5$9ttK0Zm3mXzrhsU0%Tn@jhtx82_)%4f^rwpDJfm#4kNd*CJEb< zE_dsD3Jc3er^bx#sXybv$?Ru;_`^3hJgiT?k8S&Q)847`iHyW+iTN7prC!;^_+j?J zD7?Q~jyfY@VHNeu^m}K5ImchX&yyHK`zLptXC%MJftwj9`-J2ZjMq<#pFNwoR;B}d zItU>6k)44`0*W8$!P@`_J0Mnd#JL6U;aQer`7zQYJgfXLd5(N7vr2xS`8zLc;ZX&j z6S86xKUQkhrfYNAx%?bquC$iDj(b>oh5sY_E`NakO!!~^8!;S^WsYH3niOYAB7P%@ zV%9CmVpulomTAd&v9TnO&vGO84|MV^i9z$O7(D z+`f}p%4KSoNnIAEvj}0Uu9cdO1sW-&8wr9L*otxs2Vs2@L(M4jqr#ad*D z=J2Xdi}b`0-Qc#XE7k-o%%zj;N~7ET6L{3K8J1j3i@x)Q$bIp zm__;fE@AmZiGTZ&K9TT=xKEV$&4H3Wk?@JQPpE#Pk>(S+PZ&NC^sRT(CjvfU`9#n+ z0!^O?_=M#XnxA1V`UDB>Ia3v_AOn zKzv0!X3G1ss5`qUOJ}j}(X-tavRD9bAi>>&Xb6BeA!r!pH50`Y4G<2f9t+|imS3Py z1mvK0r!*=Sr6~imMzh@slz-OROX z!_`L|{+*dax)eh`rwwiSz^(q_^kx6iGiUy}>zdiz z{nIYFY|fsoyZS2WpDn$l`TocI9;A1ySu^7&Kk9qW^Jfm?l@vkSogl~XLHY@ExA}MG z)8G;2c#vm_o-D^Kcb$nIGWSP6j`l~{v>4JukpT8*5FgQGO;>fFX?1_a>0a(ErZQ3R zVWQyADB#H`;K?Who{R!wL@9?Oyd)NE=71-oKDc~$A2>(~6MTyv| zC0Zx#p?-V$N`UGNPmh> zqC|l)yZ~DfS8RA})dwAq&M@Vknk8qi_ywDLaO;F+Q%9}sTS2eC`l>VTd!r9}?2PX} z#8%>&*QgkJaaTC%6|)?IrA>N>ItvIDgI@#$Ii^nH&lWG>=ZaVIi$t-(Yz{O>8lw}; zDS;`G3DGvLO*+qP541ZC zh7kgy1XDe(2`~nowI~SXP)XnpfFV8k z0n(C!_63xKPe%k3O#y)EJ(vU%u&9x70#tgBBq`9;~3L_dhXReB(Fp!DN( ze>zgZ=FNP#k!?07vgerd%ukdrN(!c8=}aU^0;PN;sVkHo^BE%MGepcQ$Hr71EUU45(e>D|{KZCwL zh=fDXVzSa=ie`Mn&$~$_(Hdu|Lg(q4=s0=`eVxj;hFfD(V%?>i zO1Xw$L!z~Gd~keXR&ZA0^5Er(j?%8uxA}Jh2l>y`&!c8FU9RTCO?0C=nVzW5qZiTd zseg|CJ@Q%XVB#cgAXW>-lZv48p(KkZ+t%wTf4++&jUMbtksy?TOv5ocj4p#M1=zC` zX50YS(-?p~4S+ojfIW@fZU!)UPiDh#>-Tu~@OF@JE4?QO6+crb^PPB8ar`j@@&@ot z0q{*B;`(TA^r58mRAkcwHj7YAAJaV6^4+PWI+5iCB1d~b=8$MpZOwzTe^dDCnzw%N za_3`xWlyhJv1RM(RhtWoXmQ*$G#m+=3O8@L=fqjeGjG26+uyzY?(c}Dd@G*ZSMa=A z)Q8U0x*#%HRKYf|XR))`E7+ARFIl1_N?Op8G>Q?C0t=CnrK)ZbiRI}a3ex369=PP* zu78gU4tNM(J64e@rd#o%UTKSJYVknBOzYB`SQP+$YL>B2E6(n*if050y7d=Sbr- z7nCn3zfrnJx+SwE_{-Xt7)`R{QG3Lc+IMX(LC>aXa}<)JZDO0$CbubVYMZuLTr4e? z7b}a^#ad6Ur_vyWKAGy#nR)VDWqxjc)yj&MnXb%_N1#?!els|+uRlMqLF ztQG>qvDVo1*d?*8v3)V#h^1oJ#6F6#so1?SI`$jP0b$IK5PNh&()_45|d!S?SngpJou+FS2>(+Y#2S}I|XmH_pnT&AX|4Bx8HE%n#SypUwL@?8DndH zG;8f|=2_d+6^m|M9EsE=Zh7&+3l_bycHevGwB(ZI3&x*T5zUU8yl&d0>#9=uvv0UE zdS2UkV=9s*K{-=@#*J7x1n(0vv<%BN zz|&)AVWKOBD5PpKVyK8IUSYq$L(2!R_roz@Rw#plWF*&9^9ZjS#0lU%VlERCia@WP)$BS0!XA1t6-A@B zUvUa*1J9RqV>btgMmtREg%Czvv0^|Z8wjCgm0}e@YEfs0i(_MxhQS z@jl|j0-=U{5M{(*L`A`ff)$vB?;lkk@%_?>Z)8LU{L)A^Y7+-C4&JE^eyJUR(CI*q zs13@?9`H!*kQYStVrw?Q6}HnlhEWRneE#4nz<8Bzi z4MDh}1~n@UC{pt5!?d(t`dDHmUy(`!iqwnt$q?g%rS?87qcv&%(IS2~agALV~ z)*Iisc=L2q=~1k!XU@E5T+bstXJ0kFaRq%}-_E;7PMSIE-rMM=Z{No=8Ygj7Jfku_ zn)H-9>h;ssJwx!+qC7g{fu949!8!8(*!vdnD2ifshz= z#E5{rXEG@6-TS})|M%Vh_c1l6>U4G0sZ-~is_s7B)g4hof%{UP#Y@w4a_ClO zO)kCbq27O!o0GZ%Pc6XPJ49oY%PVDA{{lBdgvqtVBZGBb5ZubaJF_dLo* zq%I!pSv~WpBO+|Q6IqenKaawQyskc!ZSUnMpdpTtbfse|o64u_)9mG}oLB0V_NCOw z8hMkx)ZXa$Ir}+ZC2q8>*4NnYrrYedI3A)cj^EK<+oO(y^qk`zdeiXTIIQ$v{tWLrb+6^AY~!*)D?)7ipu4h z=5oqseE*sQ*#KV7c{zu2lM58{9X4I>X?KL|b_WU0dm8J)G>3y6#v(7P&0!bBv|JZ+ zW$BSf#P}dK%h(;!R%%=W7O{tUgk?F8zb?)4)6VHy@z4!KD9E-YB6tLh{>FCk>yR&3Ja+YFaJ!ihMudSNndmwFw!%g?yQVevamZ?kbM^2^V=yzG1H zW#1d>Rd42UMr8ttLw*M4yAZq3(#OF^`)B%Z@(X|1_#&P8?I=qEkzdV<*fYE5`MPv9 zZv92}X7VP|xw?(GXjqevzkG zTxpHi#_Cr&FZW*QA03$KofueTE7cbSnykxg_4?!1{oXx+FRiET*-n2pWxIQOvc0_n zxuIc{A86E9>9>hrxgKEK`F7_v*KXQl-S2t9@|N{4_Kz(edyfWATEDS(ajKVoxK!-3 z8jB%}vpMB;Gskv@!{fCC$gkVC1_Z$k0qfZ_~pze;|;f*+QCT^FYr%-JX!!?a^_O zp5xF%s4kb8n$rn!W(!z!uixcyEA|37j>(u)@^l@fAssxP+^AW=@*6%N=%wc}x6#T=y;1SiM{V*WBgp7J>8hQB)kDmB{QXC5VIwzSzS~Z|MCH{zxC#Jm z%mlAC+XhIA%`}YfH(E*(Pu5FQ_5AVoA9I8)VH##GUo~IJ^2VM(0rd^2S13IiY+nIo z+=G+DPrdi#`pD*A`-ZSW=TF#8PCYkpjb*xRx^tT6SL`;&ZO*-XpX&wZi=LN!?}#_; zuelHTK5_&C?aNC8es3qYFR{E-VqUep)ZyUP?=LScw_1gEY9eZ%AOh$k#o@T~C=_9*}I1LhZc)qxquW#31>lb?QXIcfi#*{0FYHouZ6SCgtG zqz8-`iA^mlEi!Fum#0(L0=3f9*|orxl~y1Ca=W>Efls}GqC)}8>Rw=vbV~?rm3#&tOTN`666TcQPJqGgcm`>j4#eE#|G)laXA*<*#nMs@P?e zFm3{*JQZY|wg-~N=t?!lu8xpbI7OFqZ@}ub1|tD)*cow!O`}ZD&FTEt&YfQFobHo} z@@J{TT*hPGE^;Bpdy&Om3bI2}y^lCV#2ta=!`TD!d@{1R?17H%PJ!Oe-mc#6p{}9s zA)ed)&g?*TaAe2nf$72N9V!Er!O9Lz)+O#H|FY1s4nK3R@vjZ64c-{K&9U9t;(Nls zKXlx2H1wtWjPL7Eyi2!)>2?e{yJT3r#oimd!keCC-|)8ul5Z8r_j+AE%OwRbn zEOl-S#oybLU*O2fFYw4$bap84n=h%FE-$6zn}1C^O*uWy3HCOgN6lAn05DHa@&AF{ABqO zzUcG|j|`taN!oHYX2myP%O3X39+rG-sPT|UU>`rI^8g!UtOkB1Vh6%5>8752dNwi| zNFSbU&-E3s0>>yef{)Ng*~j~4vB`Y0KEpo2SHFJ1Z`4e9Apme_iBuau$`rSX}7=ybJgSRR_+YxYVZn90X` zGYaf_$Bc{Rxn^@(f$=`6js-jf=-jb=f|HLD4Pn*`x@m3WMd_Jm zYMK_Z|JWdO>xRZNbADvMQ?4NXmc3}Hfv^O1i+I@(xq?`|Qp)n!GPQ_!cIql(i=~de zc*`yFZq6j}cRoXFB`2lP+mTuKq(73*Kev4zoarpY-?zOVImm4DU zKv+!wjZJ0@U=SduBE~%4A{XS<+nsg^jy6(U?gq|95kX|VNxmRup^_F3(dIYOq^OSg z6b}2AGCK2VB0XDJNjXL3x6{~c`6Oq^W_&tra0-6SGnqLv`wkr<-cBHvuOOg{uI_VX z$7?6GV{#s<635uZN>=reUahtdZTwN&?``}Go!zS6r}H}fdYw|m zKfg;oe9YqeSx>f|waTgLcf|SU#Q1+;OrCgDW4S)*bc1p*0kG|D0rnZ|`7jxEw2c3{ zj+XJwJz7b79Y#M?=cD#^sBJ$R(OyUY7wYKrkNtW|9pArD$48&<_a*A6=dYm!FHLxy zIF42QbyuFpYVTt4l9joI)!maK6v-QwN0APl^1PHud_1Oio+)o8`hDsf$?_6};ix|L z%z`c|(No;`_2gxIp9&{MniwJ$TefRC)=JwA`j73ub$sC*iF2zLJg2-<+Jo-ctPd|0m(i;y15YID!x+{*S_~=fnAMKAaE#t?=9bC*cq0!};*PFdQCn`pORH z!})MNoDb*2`EWj*59h=Aa6X(5=fi(HOg|sahx6fl_}>#q-o+%o0&xXfNme>Rf_lW) zBhHT>LR^G6M4@;E^&o-#9>|w?fr<;`yAT&Cd^$?@pcyKjrQ$uv??c{rSHyl5OUk*R zvkS4LldI_Df{u)fR6I-V-Gh>YQSuOCZ`)Uh{VMK(GD8$^Lr_=7g({YO=Bx7gs>OWr zfkM7&H=nwyxSNV4g?t*MN*1e}5h@<3;xTAFpC&4Nio&NVe44^%D4Men7oe45#6E@l z72XwP3ebv-Wh(`sFXNG_%owy-0Ll`dqRLEDvFvXlsI5orLzzNQlXzE!cT;f>Ri;?Q zBUR2AXs!^{BtAvO(^Nbw{uvc1ITR_m6@g|kV!y(>f^rdP{s^(;ut;%O1e&sp?0XSt zN_>*apRDj{s@8PGqi7T;kD@))lcp%1rzmcxAZH9sM@|J|KjIl`?+mqfmdc-{^7kn1 z?}1bgA>M;n{tEe%h=sxzs#qw?bf_(fbMnw}6BjgxUNUh@N*Rqh(KjY;B@esM#BDS$ zSw^P;pk&~7TEm8!xSQ`_&&si&enTu(CeBE++-KsPY?i|&E-2UXx`|s-%4p=W95Zn% z*)(S2HX4{Lqf;kKor&A&3Qae0H=Cl31!ZOtav{HUi^4VFK5MhWtt$Unh1*pAD+<>Y z{+`0^rVI_-kfDJaGBj{Qh6Zj)DPzdczzrE1xFJIWH)Lqwh71kdkfFpKDf~MXZ=WgL zm6GpKc$>m~k~f<{GYC9j>!R>bO8E|oj)8Yf$xl~x`zt&{l`&{`O(~O^g7;A6ixhsL z!bdB-pTeg}TuC8SqNfm1QecnG!&~qF0JCi;>1? z5%OxN{QroT@0Kh)t4+z#0%`y*+bN`}in}_qb{Mm8f5>0}uxwDOr1{uegZ+}5dd&Xq zw8nzB?{hUdi4`lp8d16$Erw}4D3mLTa&JGyOARctQnfoy?WsVHwSa~}chga`0ozi3O-LJ*+@)kIOgWb;Uh7p}4dPOjU#r?{QhJbd z!^nv#o@B}SW}Px~yF^i{Rjn^Zsd}|f)|#hi)SKF>GW%Jb^FJ%I2ATpPP2||Df;f)Jv1P zkEwBx&}G6_&((uO>)+?=q7)s;o)~?pSM4Q6fuwKrwG=sxs^>LoWc@QsC^<{(WlB3W zW^DAzz#FhttKzWYc1hBj4LY)96-xXw8|wdHc+h}>1H+Rm%EDu7s%z?-YRkfx*TiaT zVkPyJHP!vYmsM4TCsr<~sILo8EUPPvEh#JQe_5=uq$*rl7cL3c$4W}e7MH{pg=@-x zm`WnE(5N}FY(Ya+Nvv>cS*#Ab!$bNH91zYPTRA^gQ&&@7-$#`iJ2^>evW$vjC5@HU z3&P{e%PZ%Xh5Lmk*37G{4v(vxUr|$4Qr9;;p`<=mIlrZ5w*y76i`m)mS zye3pD3s<4dYDoe+B#oHLt&P=`Hq5UNgOA1vFp|;&(#q=jRSl((S2)2$O?6dMIJ>e> zxNPw}&`v2`{ZCt0#Y<)HV`X)+mr|n<ut90M8bZXN8t}OFi%gOB3*AmSwtH{_&Dn%;FGOWfKRnv1ALlw z8u01XnZRdR>wz~|8-OpdHUeL2{TXrVD(laIueRO@e2r}@G28vN`$^cg*>(fpqhCf` zAFeMaq5oJ%@AT{RyMW)Ve+K+>{Uq=&?P$e5-QGyTzSN1cQK!S{CgJorvw`<<;tJ21 z=X?P8cIP9&cRHT|{;cx=@aLR=1pboqW#Z0PoH(a;9(R6<{Lh?!2Y%9d3iv;q{{a4# z6Owm+?feG#X(&&)nCtgALp$L51MnAIUjYBR>m+g4mu??1x8I#k!rj>o-f-?~=$un` zC3!>UhO|vNqmL8OqscntrccvROP`_70bZidM_jJgB3`05AzlV)NICoj@%8%k$oZ-M zQ{Xq~tAPJpzY+Kv{TIM*hODHNzA$CNA&ng1eVw>Ib`Ee3Q2qT6;GZ}@QGIz1@$;_d z(W5`0U$Pe+5vRG+(3ei`PQcS;zs&wPXcKE8tt3`5kHYhtVpVj>f>_xi8dp&^FGh2! zO6sdI`W?ikOe_xL3ZF0*IHch;F<57vdwTk;7M*Xj66^pGkIi~I+`W8 z{Q8TD3+(lge^FVinkrOWt>StWFOvr(TB+jID!y68n^e3*#jmLNgT;#$FQQW_Zj&*y zs@S9AjwO2ai#I(4QD>Ox(q z8)f3ieC~SZ%H#4gJ!hp}(Ep*d56*&TVLq(FthbzQptZD-?xL;q5bdHCI)H1oH|SkD zLZ8q{`j%Oki*;t%Y$z*cW7uRii^bRmb_d(ScCco)pFPW7WUqrVt}xjuw2rIMzyR=w zv}*-8MH(g}?S8}<3t2Z9>CiSK&41NM3;G*rpVzq-Fh$bU{Z|&QjUGa(Ly`%7y0E+m)Xz zq=g}4YvEf9k1uRn6fm|Htz5Km(e_0xM*XT4M!I;RkyaP0QhH6dnn5)qYv$C{*Q}|z zw`PyZb=TfiyR-H{?c24VL@64IW=D&n6QZTjrO~wpx3OU|Mmoo!7ArT>x`>h1?=sSc z<3_p0Ic8d}tc^9^M9f>OBveW7GAr~ph(*{OR?DtuFLBQEc#JRSYxqXMX1}XM14fHlu|&KeUdJ(_vt^nkW?607VtGg#q}?lC&|b8LtqZNS)@{~zg~w*Kg-`>* zHrzJNHpfF7(rYK_ zO21$?MZZFM1f@SvdIO~|P!klrdjH(Y`)5!oR(?O}^^;VjKTZ1k zq_@w>D!Z@y^*TMA?3}Rrljy0W`snqq!&;2OnUI7 z|E|5QVw2Ni<+GC>JL#{J-a4+lb<$TSRLine>8In$A1A$WJekjExAON2)!ReLGpF%> z@wt2`U<}~ucnhB#Z^3x*#xqeT6K6u5`3`VX0Uj&BV+H7} zxo9snMU@8X@1c1D_kv@0MSAAz3D<9*^Ih=cBHXzex3@Y0H5ss9o`R#{q>G)vu> zC`Df6K7;z}!Q)X#;3)V!3OOv*eu1LFKUI=5~1@Q@x&U)SxdA+HHXQNyn$OSgRoY)Oq~8pR&7jx}{+l87zo1kzB;Jft&5(FA&I!QR z|8=_xfKnsc-vw%o(8LZDx_wGN|})Z$^3K8(_bQTjD#>`$n17&Q(!N*4Im11Bzpl8r~0zEo4)C zB}SgX*M8F?TVcf`)!3KzJR@P*at4tj2Ul&FQBv%v#gy`X=&seY0;#{jrd`c7=Yg%T zKBX7fenQ*hQOmHp7HBn1@}|bQ9M>*WliN&N-I_8+)|s@WRc$r3cMMlnC2Ec^=Bp@r z;)S+fQ)RA2&Rjr=vTs>ljZ@iQUajoCMa?MnfJVhZEBR0xBMcztpLPmzMte>1DJ8Zj z*``4$3hMRd+~i2iO`z0j^3iHiXhm(wL#ryuQKwanQM=hX7&apeJD8?B?r?E)SqF_ zh3z%cR1HH*M=@rMnoMDWL5aoL! z`TUA}e=5m4zkLt{wq)-DF`l_PBU=LH%mUr zK)Z1b<)Z@#0hYu1QIO@bTJ`B>Fi7P59-XmW?xfRcAA~0ZX74ql*u)& zQFm_R4$9&#?xtSc%e|D%(|8*7;pse`F60@!3+3=k-W`_PgZH2Tych3919>0bhX(N+ zo(R>13&L`nmJep7C(`XEz0s9}%OL;k6 z!z-Yb8GIqHrJ1~r*Wv7Q313R{`6|AO%K2)(nilZ2d@WTFvzA(S$h+M19_10$-UZk~ zEcPza?SO}Ye}HrsU_an#6P^dWWWwu2(F&w*1KtB1L7k709tWHNoC17{G8~`-Jb)0O zGawA;1?Y=9pCKIt7^e2I*h#gY#lAs$37{A-8ZZGcl~^6r9-Rf4N7S$l@DQMxSi?S~ zPXZ3GlG-h?!kDFQMeWnEiRE)*rM1UnwFAX5u^pn_f!0OuV zu}JO1fL*c3f&sBe^p(2Fwbs~(+WoN+$ue)prXeqayof=6!OhXFu{qHlu{pKR$0n-% zFCl#oX?wfNQ}8*pCy)Z79Q8aXdkXMv>|Si&8x6;{DZXU-cI+Xv@g%liO{S+}Zz=dT z_O62Cu@3+rM|;KIjrIi$i+uq281+AhPN=ggD2{!Tz!QBhpHtUOLUdW(g$h>H4Tan$ zM%TvfkbQ{m1fN^L-<~>(w$v3#StMi-{iJRNV6N=DDPxoeeF@>%HwpPA0P-3mWtfng zqV+~Qz1r8&|05}Kdpb5v>Fs&&@b-dD$^7r`Pmv>JQY!)aos%N#>r-|A17(&(L+H0B zb`xMD@QqR*!0%A`3FvI-N9rjRl+JWRZ{VrfO!t}k+Xr3`d{=+bLC}-b*Co)=C8n+< z?5w*%K^QWhfK&qV>(^7YNW`27x{sN-K(@h zrQcw?6VjWI1`_$vYS_n0*oK5uyuKZW4fTNi3{bEZ@_akCFuDPOORFpV$m;RpGCi_TN-UM zQ$r8UkpGLSU+v@MGr&n{_mJmE$Zee5ui&m&o*I+V4!Eh~7od}8F%HbM_UXD6%Knv2 zs&SC8*=cA`rdg6lBOhsEZb-FR(*~tILPxdI=9EpDW550@Nds^KWBf$y+pv#@ECngHlIWMR1>MlQ+ScVZ=qI*$T|feKI3gzYa{h>ADc~vd7kJ0f#i{O`lDcQAtGlIkbx+fy?q>Sbeaw)$gPEc3 zU3OP@EiX`a411~jef>e@_xy8?K4t^%cJrzomZS5%CE17mtcZDOWru9-{$b zx7bYs#a^+O28qYT<1|=2A)cT-@jLN58X}$&Ptj2EjCh9f#dG308YT{k*Qh|WiZ^Mv z__O#6T_FyMLo`zSRUD>K;zRKvjT0Y)TqtV=Fw8ER4b(>tz4_1W!gfmihitBYqhjei)r=rQ*DX1 zlvZiWwB>Z8wnAG$YqgcyN?NB~uU$_!X*Xy$(0Xl^wu)}nR%@&27Hy5ThBjzxwY7As zc9V7!ZPaeoZl+&q8?+6yN!zGxq+e;9v`uuIhCsJ#cW8Ie9ok*mU390mS=&r^Y4>XP z(%sq?Z3}JIwrX4H9&MYpjqcU9Yuo8QZHKmlwrCG&57Do+hqZ@ktF}|yN%w2bS~LA8 zdEW!nMt0`;T9%rBZNd=3FbpPyV1_V+Arxo<6HK9A$Fw9u9B4^B4ucs66UOm+eXajO zY6;=!W-u=VgiGunx;Q9>#G9aU9|h!V=;*3?W{^I`_RN zwGbLSPEvcRtJ-??d*7$m@6Y#r?|a{S-AMGHYD6`H{!(>a^?%Ti>TgwlhlW*OSA7Hh zwd$LyzegjgZ>jzP{cqJjs=kfJRPU+YLw~D!U-dp3SA9qI9rSmq@2b9wCRE>3eGh$I z^?lX%(M{D4R6ju9Q2kK#Lv%~^Bh`=4H&s7Y{TNNEexmvb`g_$+RX;_yRsW>=C-g1V z&s0A{Q>veL=i;P^|u!YCOfmCDczO})xQGtpEU z6U)R>d+>j~q|%vqCZ75vlfWcU8B8LRNPUV)Vv?v#CYed5KFy>sDO47d%A`_znKUMi z%4X7;4C*x|lgXlTnQSJT`Ye;fYa`)5tVZMy82rqD)LP z(@Y6W3)4!y$+R(TR0DI2IYzz39A}PGjfhf|DBN4;=Xc;d`c4y~j>0+m9XJ!ea~${q zpd!Elkb*b`I1@wV@hxe9OoZB60LK6)5!Ge`>IV4HtEdDW zK(%mZgulIGLq2o{^`d^bR~rBC1eU`flCxxgcRWz z!vA=%Rfrdk1D7lu5|n}wI7X;5Z3qHz3ZcUEL|~D^^i-%cEeZ#Kdo1Ld9tZ`%EeLt0 z8KDrkn{f5EkOthSP;MF*(vi~iP~f0OE!5ymv(SeUat=ysp_Df*3x}b0m+7IY+XVWz zUNy~|PPJbDSKAX+k{1kD9=b zn!t~mz>k{1kDBI#0AFfa2?BiS?bAR($|mrix50nj2LE{*{O9dt0Qk<^;5%=F@4lT6 z0RMlx3{VL;0MG#r0gPeg4S;4q8{h=M0&oF*2pxrc%A;^Uc@*v^kHUTA(FK%e$}!~w ziU4It<4p%lI#aSK&6H`HGBukjO>L$_CZp+u$zp0SxghtMPD46tI%m3I>W7j+(-lb9 zOryY$n{FNDj@BOKF^9iJ2KEOH6>ExLA%)`CFc(TP7c`lRC^8oe%ta~8$iC2wyaY4y zC6q#c8RjL8%*!5Hpat|vn3pRkBW@UGXK&nZ;{FA_7WZ42quf8@NEE6>BAM%a6#dcj z1o0x;C>k9`$#}|m#@J&#--5rL60P_^@c}UFigiS(%2Z`YK_8+IpXCf%XJB zLF5PP7Xd(1ZzbSBsQ#8r5c^w?10e3VI!GT_X3{1&E^38+p!F1~r|{~6WoP~X!2Z#C zJ`Avjv|b|iP&7$M@z$vjQ0wJDSrZ=nDv^!IM?PPFE&|tYV5;~5-({Wf^os}04$mOp zYajJo5o^rxo@-*AecUrD*4S^sRRK!I#YV_)i7oai&y;vfw0Z85l2P%b{jTS}XtUq< zJP;f051p6&KWX2Pvcw_FV<}hcb0Dce9ELjS;)u0HQj24d zmx~jmWYV@GRf*FMS~@7sI2b6Ig*=6ybRktNlM3yxe#fbvAB zx$G#A8pS8jwgvb^;Fle0=@>ujD3?x(>y9c3L4FYA2fIl&ann)b88s^$b)H-1Xoui= z1bidt*y|X^T7>1pjuFB`ZmuOISi3$b9|OHUl$&|Sgd~^`J0?Nj7RR(S0Qrn(ieGok zO6le%$3y7nIk`CDSdfNDj%z|L4v>5p+Gd&K9W9bu6dcDu+E&N1G;BT&$D;&L2ubCx%hUc8453I*I21t(iQ?^y`w_)pqG%JpYL()U@8E3S_ zn0uV@Qlt4ij4}cmjY$i{->wn8CSWdxq{M)PVvXYocpWaEG+%Tkc^>fV&QxjHTF>*ni!8$(b!}@-xmnu-;|No3CP?pRtd772>9|5d0I*-K_b#v&0*1zTr@N z7>o1+T(9=d6Xc^G;r>GA}w0gGM8K z7v{lNXT?c#5AYn=^A^+}lTzO8#k_gN*#z>eI$L2)4Lgs+oNhW5ARF%#y{YCT!asFP zdo#fDHQsD~)9H{F%+Ktj-aL!aDR~Pmu`mmRz@PG#SQ2obmSpD{DJ#H>6V4v+1l+d5 zlIA=QZ3BEJ=J{UdMb9-$j`PxyyOwx#DGET`xh@nsF3(S#vZ<^2ky| zq8jOh9fqLXR;k1s#PDscn{`;U5RHbZLu^es@<()|-cUZm)jzAs)W^YIbRniB z!g+PUetV=j{VsY&cf?^m?6O=6y?G@D2*{dWq$r#0Vv?zBly4zPwHgn7 zOjSX;<{khd^r{DJAB1FoCxVeuj16Ic6trAQN6w!=?u5dh9^}d^0J3U{cnvX(``c^lCi@1i|@ol*I9i?-Z+~95vLeQrN z0HqUmGcuT@?`#tr&6URn zxaV;CpLjq2`9b}sSHZwrs}G-GZ{M~X3797u!vX!@V9ENfW6P$i9O)vVwEG4(no4x* z7fBtV*po4s&KlziJ^-#+A^q(?W#hK+hN&RK2M7_!02skX25YF(d+Cp$PpwOg{PV;m z^OYJ{#%HTv>stQhRfD-e-OKcPerH_>8nRfJOrua}>U5Ml z{9`|(pyx-d*X3L0^(nm7u70y%YodqSUbzP-~r39qcF5A5QwnD{t+p*UPor9cPI%j{- z8EGO{fy<^)3dF;>k%xso*cr8oWr&_Pi6uDjpU=)}Uk~(w8DrjS$`HCUUXfJsBGH)c z-_V}sAIu5azJA#|&xu``)gyXxJ%lMosa;XknHuDQwte$P;?NZNZZ+P-TK2Ulgar+j zI-3_DP3wnPt|VZMw$$9;$cyGHh*1t_=878q2rCw}{EFe65P!mdE&_Y=!IbVjVoMGU z4HX+}NDTN(YQF!HQEUrZ)-5q{syC&$`%=KAZenh}h$|S?yY5ribc)dIn3UN0D7!9S9zyjAu^19n+Qxj&-+y)`Vt~ zdqB(F1u-@mXT_J(Ia zTD^F?9e<>?Bc1V&o?oM^sa$vpSgo885+Mr*ds6nqUctXGp*XdW6dVbtux=+SJ~6st z9Nr|XCXd&N0l4)p6~5C1ISwb+6#vL;adab{5aZjOs>sh}6R)}Q4R zTEv6-EfMa){)kTrk^^GU!$MIMtytUox(L@yt%yBUd$@Ft{Rc!e2#yr)s4H5_C#Y@l zwj>!5_I9uEyCXqIYc%|CtzQuo)MT7!K=FD4ea>E+!0ZhBxB(Z&Li5JE3q;tqP_!wC z5b{Si*(-J0av`zHvfpc<(R~p;G+5vD=qygWhC>j6c(5cL=FZj?h>ou!@jzpDbJ4_l75*kaLizM*H`2T^pyW9bcGDCV80Bq94bod`fH2V6 zk)!q_I&_xLcup|)6AtDuvk=$=g!)gySVA-aPP|OA2RuWZBD`r^t|?k$iO%X1h&}8E zymugL9W#s)TJQGrj511uuT!1<4%y_)qzJ$ac8E>;iNk&)oV$C^?hGhpIRlR{fhm)- zJ&Y|YC66@!VUe`f`Qq4@t?^K~mzB;ho-_dk5meGQ|H&Lzhov8Ua}0}u77o24FW8A< zLRhlaQqUu98|id>Vp+%7;Ca`)7)?n1ID6y-+kc|?{&`LKwAdkD&EG4(*&g=H`4D(w zo(r7Lzv_W23+W?b?r1~VT8!9ifW1;5)vxRZ3AMc&a5?eVu((dY9-XION_=*`2l)>5 zS}k{IzB4?EU6y^Q183hcb&>_FiJ)X>c;3+_Z zR>~AKxlDfsC14bi2@3uDHl636UElpL1$2X_DIyv+ZtKobsu$eJ#9skvOH}5Q zi4og+j@2y-hYLo;$0ezK!QJQ!#->-nQDM!U6Y-ts;P+D8S@ik z$i~C^v^To|+A52e3x9mSCF);?{xZbIrv>tBKhi$9e9a$K389YxN;C^PJWAZj%4~i*f5#zmg*nhD-Au7rk zw?*XlI7z3!cwVN${%t#t29$kTu_8%CUJJ$ zRt`}4)p5M7s=t8emVR2=6Z(Pk@XZF&ztB!K0OeiMTjn|QxNVGJtWFh}Ha`Zgz&%L0 zwOo)Jb6;dW#i(RlG&r4i!|@MYlT(^8EQ`D6Id=R7<)0gn=#%>4fT_@pfratF{$N=2 zC|;_XStN{g@Eg`tkgW`}GOIW0MEN}7xsDA7lV#+sEsG&W)AYk~BJJNp7TEMlG$!g< zbfWWLEL(51f{Gv3XQ|9AIt~e#EnI||?b3XxqMc-ziEfIOCM!0^;7}8Y72|jr;0~^e z0efDpzFQA~-Mq4~L~21$S758~m11j`5KYiqXKugo;t_D)mCT z_#%tjlDye})kBD>qw9$2XvK)1Ib6n9!&k*u)=_w}jBHbDRckHDwU?utLpP~E=|A~xl4A1v%t#K` zBy6l!j`@l>cesLO(~4eekb2XB9hUEZW8YWtTNAKWBwNFUhV#wr83_-$2y~+t`cDvm ziYg|w_OPlr>ywWk6(JYjNIimxLTm^7;_FS%p@9>Mjq}&m5dd?NMx-aOyYlC^>g=w` z>6_1Av_EP3Y{!#`{CZ-ZIE}WtKT#?nKR-}k$aNyrU` z`J)r%?F&|JRcljg>tN;ZZ<}25)4MtQZH?0-x8*!3W~Pk{tC&PgWw7$|D;e4hT|rsN zU5TA8xhVA|USED#ZqbaUJhA3*yY2LgIp$|MGjUQF?FYh)+7H<4v!F@+aQE3aC{e*) z`JiXY4;g*>UPWQc>s$}2RZ<5B;2C5Y-dhxbV2t>vbM>x(;`_7NbZ@z9FBaobNdCi z8qh9(xtH?WdL5TN{)^hAvF8T;WxSx_)5yR9&h*BukTE6VRFAuPNuP_b&ex`02Rz~Q z-r=zt%^xsw#!?A>jhn}8uCqH@h=Je)Pz^U@RXD($R^u~AE_v50bk8{z3okjP-c!6%&b&Ym+HXktH|{Ee49)T5+#mQN zo?kczg-izZ_Gk@_2#*$rb^SV=5l7s6#=J7qh&Z>7Y~#?RyZNJ{c?~3|*jAF1f#xD!yq2UB^*4B0dU0&`=E_~>8|xV&Yp?r4 zRD!4?iIOjxW`QnzTO&CGZ}w&FS1Z2*`KZT^zIg*cw!-`qnNC9Iu_yiS9VW52+QH8m z*6=KIcYF;Vxh#>Y-kX1=s*6GIEQ}f7{Rgb9wiBad){pP@YvSuI|9buIW_K}+FBuv9 zr_Y;yB%ZMB4e9%t{bY&i-F@SLF>n?H&b8_p|9cJciZ5JGi$dp*9Dg76H+}X|p!>}g zH-aESGJd8cOaQl@`h@Zdy=^IrR^zLOdWKrp`$Y!{sk)S4d1ci5mPF^d&L0=0?85jj zQUPXtO8f~wA)12PUB9`ai+M|JC@~xLyYRG{YNmZmo5izL4C4SXhZy(Yf;NwgrnX9!Ap z#|ldE{ZyLSE}TlHp*Xy z+A0&PBtS%c3=1hQX)ke|QvL=+HOy*;VGNlInTt1+`Y?K$mOlc%%_%(CKM*|#x%(w6 z36OM(nKnHG=(&U44qqj z8hlEGm;@bRw=m4va#dD)?7tbyewIzq8!~V2-*y!J z3#dgtveAjBchjTtENt&Bs_|2a=hc5O2|tUsxcv11I2Fii@X5c=fq0Mn?g{lmW*w;i zY;l8W+20M4iHEB2ina~Ps6_;D!+>GltS`?ACb8`MrZFa5C-n%LHA95K*R+&?Dg&73 z@AVs`LmMAkG2B+}8F%U|F3-PSp_UE(>wZQmcR{~byM%6}pYpkDJP>-u6V&9h7!C`C zUCYPA7YgGb35~eym4J0O)EXN6Qsf|N*o>M&sN4@Hd;XOwJfpyVRK(yeu zFkv0>7Cho+529Si)S&39oGrcdd&cy+8l$%8uQ^?7k0nu6GJ_`gZbdcJa%#!9P|k)EsNLD}j|R3l@a-{5FdJeN2-q z)6u*69P|+SR||_SS1K))C8K}gXzsJ?`9~i3cFtHMgg@_MVq`C58uN|J{F8g+*HKzA zgaf<$bPOv*3YVP;Uc?rs?_ zuYP2{`ZL0_wYEGBk64!DJmx^nx?@bpF|3m!_nS^ieR=~4m(`wtV_&h%;NRoSPG`4n z;a@?(4c^S&_Pz5vZj%iIbJ(E-LIX-@wXZ%*(4sSp!?{4G4v~@{EeL}pCmg~D#mgsmC#9=Ur!Pr`$p6V(iX))zHya zXKZoJhw#Lp|NA%prXGdQD1o3oGEh6BYe88}WqaSj54SC7z<-+B8zfP~UIF)V8!-OV z`QEkPC8uXamg-J;+TXr7sg_x}qV*04P}XX5(sJ%|7^k#Sbya^A*V5HhRPt%*X{)NL zYEmrhYt(7vg|5o>vEi6-iL|DZq^Elx7fdVMhnMJsr zApBJFPIDB+B&GYLq$Hr^DUp;8kk)^mf8I>;Av^ea8oB^u4Kep0r5-o3HS`>A3BNQ( z67?O;O<-GG07GZ;8_u+dgdqe_V{l+A{N9Pba5l5w$Jywpt}u}zM%zRqT72J8zmy`1 zo&}B{w%JD0_{8aix?lRgERt{X&>~7ue?kv9f>w>5#p~_JivSZM$SNIv)KMp_0qk*x z@Fx7ymV>pUTBrsE$Y-{c(&k}j6sp?8pbw7}I=xmW!8&`&`dXzB)7r=r=5eks5n$Gz zThihQBIpsxte{3F=ye6Sku-Y_3=QV#UGc1hTy&4L6L~HF?12_`i7flUx>0rrrdZUu zCssU3@?m0xsWSON^8)0V#uB2n#B_)G21cwTNYEDZ5w||Md3>`NWjrB=%a_F4Wm6++ z<2!ci3+?!8RD;Kyh)RU?3#%RR{>?$7G=86zK zAjvhY*7?}u)(0#ZOOGVO%ibc+W{)u~2%Pn{&9 zR-FB#Z>|_28`CC9wGbMRN}(?zaOTrcN$(B??9!%kZ5O4l-yudz*ZtK^Gk?~8 zP^)^|3prkS6Qd-?@7fBbjJbXY^1l*xS-s&5Z2``4Is!b_J`KeOO=c7B!Py1Z0R>H# zm%JZ}Zq#;ftU!W&?*ZGL03)JvUkEQ~UZTG$5Wnv#Hw-QbUT^p2YPbZoJKy~n>qMUI z2<;O0c(!OBYwSmVEE%{My@!L_9E;tKnmp^bUDP`Li6sBh@?odXm#$BXa|FBVP1&7j z=HnjX^!pspp$B|#_VixLU=q8-?tygz+|Mbzb<^Btz}!0?8Kj;Le}00D5u-^XirHuZz6#BxXuojn457;5GnxV+ zcz@XAe$|-^2^E5t`m~@&M4-qkCt40VUEe#tf*Q!u=>K&SF9 z1JQthVkx6QF#|G36d8&uq*bw=y?)iV#1+#Rw5(iI`Rzh*Yy-~yYG0+Gj?`ZOUH9S$;5D@BIS51$! ze%5PV3WT)x;ujWmVx8shS)F_D5<&8du-fhHfdJ(jx9F{cgZLI9hL>erj9;oihF_{L zkGG{fqPLPfzPH!}@vTD^@-1qX{Ox0=-R*ED;cZ6dbP^c2{~>ag`E$_9?9B0p?-bel zR)M?v=dB0#j=I|N);5Q$#T4Ht0s;;C90VB&C#iT2`P>h> z5`1*kAF|1krI_gGY!c$)%*${UMGq>?=t)HqvZ8eKhNV#pMdT_H%`x!hxalk%@VMxz zw#AfJI=w=KgBKU;iM|D2z~s;8f|g|i-;0*z^HmPZlqS8iijCF{<6>bxH?HAe;9q~) zKM$6hB3XW57;rrusspM6H_q|7HT`^GX3we~h-GPiEFU=#=?|;A2>HWTjct6BCjQFd zyRP?wH4DCdA1m=iCxMjb`y!3RI~Rqj!%NEyh--8M&>^sXfTO^eGsoPkU*@5|j*`sO zrmuYoyzm*_YTJCifHg7w-4lHFvG(55+&!jGmBMw2zt?%T;Xdq2;z@!t9l)~nG*@O% zE$KM-x2a6t=Y`{+VMd;_C*Qi42hT)vhJ3!Y{0O=SOXr>3mJ3VH-S)V-XN+P_zeH%v z7wHAPPiJAZRTXhBd#jbcakZ822(yGhTER!&a*I{sDJBX-rK+~F`z&NSPM5A5G(bbb zU7|SV^r5`76DOX@rZC|cTY=VwF-Of#@oIsILDwB~t5CM>`n*}u|pcbeEviMFTfIQU;30>K;!{+|$C-B=sH1l<|o6sACG%gqn6+*3WDdB%ZKW>eaR| z;Dk+h9jHg{vD@Q{RWTv*qT#^6>rF1d7d);nEFfXO6N)s3GfWMB)wBx#4xWP>{a?s`o6m9(-PJl#@G>o}LMYVp{R+V7Ib=YbR6t%Gf z*%z!+w<+w-hl8W;r5$oZ#@@ccP^=|PZ!5F1x0p5=C0stA-4eL7l-ubV{L*fxXvqxh z&?dP%t4V|rE8V&upc+Hs!DeQmr6Z&)y{HL1)jihiXf~kAs9KJ$Ed5B+WjsuifT6;4OB)4^8%zt06Sfn*t*H4`$cFcb{}Q?_@zT-TP!Yznlru2}xNL8%j$8*-2)FYYygf zKJp#nH1qSId$-a13hHliYj9#DelOSRZ`%L8bf>h&CT~V8C#-J# ze3U)*l`}J5CH@8gy?mYlQH8q59Ydn^CmrGn~ zul{wy)EzsFDE88M?B$C11kt`JNj~?+hMRI{Wol#Xp9GRj<7KSD9jT3GWO8s?icd-R zv)x)#Hr^B-sDH@;a45I3@u@ylchPTHjA^91TDEJp)Z?bs#Jo3m&u8eYWrLLE{>*=P zy=uRH?`01tz4unpYh(;i)#KP9>EX_Hk289jw0NXl&CKmzl`|J0(M#rMR=2(E>D@UC2)=YRNR}Jl2dhjMl6wS%_3*ZB%L# z_woyW7+x4R8a%>s@OqO!Ti?do@d#vW(hEraO7vcZS*5z3J0}it@bLB!NyakMw9rH# z$q@>%kFz>7Pt2?l+-O#0GVt^NeF0@v>9#Xkdk<_GC`bocKDI7;;ME++=s0A!P%{A`)ad1RB$w-fTug8z`M zb5e)4wKej{xD<^d#*b>5N@}0e+&vU!AI-NvKJfD0GCRk`_l!L|ChQX16G3A>r9c&% zTK8pHJMK;b1vQhq>gWz#s-MnabeiBy$IU*F#f!)5)9}Vu_qv1W=?(j>CrNG_044QumiGae zn*zB2{GQ$ZA!}z8*DM3bV)<(J=UX|<@QtM;JHsdZEOPeeQ#j0MC{GjgVs*w6vV3YK znap1&jGs9lk+a_g=6_p)Jd$+%r<3dj_H>NQb0_bZhC4aHR{XUQe5=NaORMb>3|n~0 z@k&osBn`@+08N5$7EEcLH@J%BTQ}kiLi{rP0ODF}nvZyRnW`4HX90Y=+QU}; zvv_+t)dU~2uh|+?PCmTaFZLAgoajScbu2si4WljrOWcANpWK-2(!)I7zj4vs*-cI;u ztIu9^nxjru@2{{lQM!g5$AJj5`9h{U6($G^`0{VjJ&sp=U`T0IC|px%*>(|?Vf(=_<}vb5C^31LaB6cbGe1SC%!HP8@>O- zscauayKS{;(LF$J(oFhKCpETCC`NI1!fKes&(0s)-GbzC6E_njRCeU9$id=f z-RGH-`<2Aczr6SH_IVgyG{uRrwn{d#YmZTW-{VNbzV>FC>wZ^&dqc-=HEP12_`yyj z(EF1HWkMrP!}x;K>VoAV!)CkR&?n_$%OMaTDM@w78VI}=OE&4JQTvxB=|=RzB~gdd zCH@d4E1m3RX#|D zcvj|&?02=Uf)GZUbd>De`JGQk!r&u-MIpUGu*1>K^Po91OBg=o;Z#~=eH1st2(@Q4 zk<8K1vE`rlIid3BsJa*|>TV$Lpm*h(=U+SgTV~dl=BRWpgU%CY@ah`YM!4^+AFTF| z`I~3?-;4vB2_dzLKxbl<(c+O*54ee1v)qJvAsC$1d>&bGnK;6)=IDGNDI_z$;l zuRHe8wY_xILNV3qVOMS6A4GLD0Ut(Ow-^idKW_6)?xLm9qEAT!i*|H`z};uK$+_1a zgnq<+6-CGLlt&UAw=qS)I34}ued`KOXaL=BGokD*gW@m?sL_jlBGU!~Ky2MxQm8TeqAllGM!om};D6w^ZA!KZ_ zd(l0yx1&G%)x+jR`(e5(taQ4(ak}pm??nHSa)#uE%PU_I#23asukz^1*Rtr!i?p(Z z6WWv@gw?X0)a$1jaTmH1h?l(6xxmq?qjdquEHRAni&GKMZbEC2*TI14Bw>GZATvT> z?4aLg{&t1PT`ymRI1Fhk>OqC~gqCGI)-%?;HQKVa+OtIW+&Nyjf&@{@h-|ay)E%qxF z5>mQ#l4T2PQf1f%u?IToS&}b}D0XJ0n^xV6Pwnp~a-X0Atd@*I9oo_w9b1w>VyMVS zJ-NuLKY9vTrZ<*&Jxue&2rTAPWh`qM)p*qXI29u7kuo1ySEt8!ljF+8fe5zpEWf(r zb4U7e-H2@sDBMYm4JI>I)fhRQ-63p~IqCUJGtPVrG@1yS)jCvdW@}d})W^DiFjawd z^udUy^14MXZTJ9KyM&*XX=)MlxX@j|T}dfn`1BO${Qkbq z?;-2{cM`z{FFzOsLg6kpgl|#+<}P`kbky-fZ|O5vo%{idhqhDD($&;!NLA^iSaxiu z^zl@NZkl29c?Z?E^v^x^I)$%&c%5=u)Og2+UvN=#si2Z_wKY(+pP(-~hTX8coT4ay zyuGBq`=ru-d7|8XLWPj5Pwuts8L~;x#lf>QVX04hRKVrEa)HpyMOMn}a0(RK4yEkKlO2 zo2ld9K=vh8i(*t$WE~~~~LE2%tK*X4AYHut+`xA;2d{B+y5D7=hKs%2QmMN} z^XN}vh+97z7S$jLj3K$>-R`4xU)fHLmzDcHAj(!OL1c^Onr8HK@A@by5F!xf4Xd0Z zefM%&{MwLW#!v4emr&;!*MYoP^yPc9FgH=uSX3TA=0$P-S&J^E;5P*NzQn$=zR|+k z%ed26&1#Z2$$b$hM@SZkz=;P>gr{mf7|Fjrh&_e4eC4?J8gBhjkdERXK4gmXic(OUs>bV-7?C2J*#2ng!(cA0SK_FnWaq*Qchslv zDSSIt^+>#gga~sZAa^el|5xg6U#JpJi}z2a(&a&(c?VxFtf-?c$m(>84t2J8wiphB zh6Yj>NA$<5enp=BZ%NaImoDe$kXPbA-~5LMghV&>WJ!hxhSF+Bpj>)s{1CeE1(7qz zXvA{rW&|as5eKx|Ia0J4n$od8*sW56+uc; zfru+%kqGrcbE#GVB*btv2MjZ13vyDoe5ISoU5WeOo=mTi?>YLd3z67;+y6gYLfoWR zLO5FE!HL(x@5EzjhDjullSuz3*jZAL8@r^o4IT+RqrtO3d^!kM$PwC_F@H&XtwfKMi2TUI>3+C|M{eml3SoXnXMmZN?Jzf`US9W)+=WdS70)b_T`$nXForF8KQDc6`E zzJ|ZzEf{nf9J9{VK8rWzpFQ3SY_FEvS!&hpU+E>GoS1H>pYpA`{fXB(e`%h_ToRq8 zgDd?VWOVoX5!acqw@U7#x=AP_2C=%+@6B;?svhz|P2f18=x-cBdCodM|4lD*AU=3` z@qOQi{E(9`S=j!AiwDg-2Q>2JW)cp2&u<1|zC+j0)blOs%#^jeps!5;9xQxnvY>f_ zIr=M%v}v~`^01C5v>^**Hf;KQ@&&Iqi$(|xldnfT<{2+vGUqN;B&E)TNqmH(ffBaH znOj6bgIH84tyt+@gr`>~-0R^Axr?bYdWeRyiE6|Y)URqBw@kjDA>j=>p*!5U@x~u4 zR6LUGV;;~nvz{i3%r%yJf7t$MUl*7dS9Jr$dlUVsL&NoagtCzdmG)^=ZG$GUbFp^$ zzT*UxEg^bM?M%sfLh$G9{CEcPS#Wuykv(hsw5p4 zTv5Ec61k3ci4M0 znS!nkbC<}Uj&{^!BZHMG8Ttr9P(#A~M0BG{p!5I!WJ-~ha7Es5bl-8;BCzaThZ%o5 z1e386AfbS^za2$x3!LGb@@%u?(7y1k=@JCVre0~JmYF-zjEoYst0Ubq)(Wth@= zI--G__c{Hx@wvFD!|L?9QkFC1Mm*OS`UqPfb;buFKdvF8fferaXyutKOVaO8GL4A2 zhl(&GEe;a6cz%5u?-ljkLiRAvr#n%V$n{r8oPZ-v(6=A?8XcQ-H55FL7^(3#Bk$(C zy(eJt0%)G9cPHuzOIX$CpN8Al&lvVZMyT3IQ-y{+d!HWv<`MbsY8?AqlimmcrGNL; zhotk1wxjm-DNl^}QapAPxaHoJzHsaN@K0tFv2Q~XHAzu7!=JYBCU1ylv)39WPiTJ!%rc#2K|LFCtVl6M5hy~tN4O&}Mytp<<2 z4y*5MpWM8w%*vC-_v&*<2uDWs_yH8$BLnk&N3`8>IuudQ9XpUO52QzOzLb`sS3x*z zXli{#UJQ(`sGZ9}W%c!|YYmpzT|qhp12`(SLEYH2l2?8BcYe*oFQ%5(oL3Sqgj05m zvr8(q@XEEaAM;uUr=HXW0cb0v7 zD~2I$)4C29LAlmv_?+W>dlsQw#vhuj{5}TTmDqF4n#2WFf=d`~)|u+!T>_RER}0V8 ze~ZTJS=00;Lq+hX&|(y`o`mxNn902c4VW%96@FFN zj5#snLUD_`{mV1L^LKjkH9jXn{nCg}REy}b-H)H!3V=oNl;96LyUV@J&GLuUNByrH zjuXb$yWimf*R7CNSXYHzlU8t@jDqoN2_mCvyUTX#lFp6;CLOT5g4jOz|Gh*PVDh2sN58=1k}Ww~&Yi4EO}t&|7Bw z!#-;gn)f!?zfrS6w0h9YxbsWXR zhC&vN*}q&5(xNSL*1Fxa%!5ZW8Kjy%h6|!|-R9TKa*^LD8?$D6b>y<-Q#twmr28%L zD75@7$tn(vM|W9<9##d0MxZgyd=CBerewTR$lyDxtP0>9oq)cAJ_K{7bi>c)D-Fr~{a^hOF0h-@M>AecPaj(ahn${xSKWxtK*^^qyEt>|0|EK|mwd zVEQ9JJXab~C`&j`oarcu}N*m31C2BD@DkBc70JJCqXEX_f??8+5i zZH&XecK#R45w6)XzS?+UQ$0S145ccGSM7wVB3<6v1mO{91viGT1tL+8UrCr->v*f) zK4*0|f|12p9KPCUhog4xmlUhI=pM#`rI<&OuN`{^oZau$6KsnFcx&T(sMl;i<;3qr zQk6J3K7U7@mmDz^*F`3;Vo6$f;${mOn{6d|Xh?1&@7-zOW_BCvZK3X|;7INRSjn#< z(7jpWKs~JFuhF1jR&uz(C_+Sv+W_3;L1Xcc)F?s(id#|K+FdIv<|oJ_h;Rf0Fx3#>0O2l84jAX2M7mcR1{S*y5&- zjQx7x_gv`XkCHQ^?2coIQR zt~oSs8efnRPsmCAGwTd!*2;;OX55sd%&13?Hvd|pvl{i6or}DI@oTB=SD*WuvZwey z{)X=urQW#~7wtbJNu6Oyfni&QhhgiuhjI4bFpWr@(g-WF;bQ(U;y^oQ zgfkuDo(kb`X=?nq2vPE0MO0cC`U#Cn#uRFvcC_4)WVXV zTjS$C92FjN8D{i4zEe(!`+LjR!d@su)1`W;=aBv3zv-N~$NAeske$1N)#x3)S#M0f zj`20%3Db|-$|cLq^g{aM<15CU_*pkM>c(@xP8>P`&!J=SKxYxr!EobIS=y;4cU7X} z!?QT&Taocts+PUFiBGkfi;HlUE<`75gj;i?0Nv=GvlaUX7orx*7ctk9P3rpH)N`CX={?a9nG4S!(w1s5*HP{$eQM+rfRXs8qnoup&LsSf z%`?_}l}bn(BDhMNIPH#q7`xL=d{xgcFstMmJXOv&F@0Hv9{YbU*EX%s7)+m$Ipc zwH}(e@}4!X1gQrfOZtu}m#|zD5uGbSGLnS{CXhxo7ey4#9L*!rOso;Kwa6%G}cY`}8G z?U>;i>6yv14jg&S=Gg{L1Gjb0nI1BH6TK3>tGc+h9J@xkx4o6Tr+osiTYc-i>b!y7 zZC##S?^~}XXYJtMo&y3Wo;Pyuj?eG!j;}aR=^qfECcR@M|Hs=~23OYWih@a}!_;AB z++k*BPKTM9lMZvz=`b@hGcz+YGcz+Mlm5;<_nxVm_iBE;ney_oEo(`#0zB0Zge^`A`ead{&csKA4b`DnFAHLkagMJ8n0((by zF6r#>?p0o?yjZ;7e;|Fteq6qrydA!wy(PY>yf40KeWZS@ez%3_FKn4@$FU%r7LUe$Y@Vnqwv$eL>{)y|sc!cM{*@Tad z5e8QQXDy|Z*umo|*dzTtxK5~4h+&#EI`JrpTqcgVg}8-O0!c?UE%7M*D78pTGpUJ< zo{gS~o=YwrJsCY6J$33+{n~=|;5a5XcTsL2yLNH8331<=0q)S{aOmyI@$z)wapHD@ z(f85da**_7{bJo(AMu@2YV9@n5h?cIJ@65abiH-8b(PqV$;+6b&6VMIxuN0(V=@E7 zV=C1p|0VzI%4_^1W$Yd911`%lgM4HXHb(j2m>PqAsT3AQJ##^M*qV)0McBsf0VTul zPDWRT5ZPoWhM38e2Zj`HI-EANb~NdZN72j3g50n(ivm6o=SDyrg4ZbWFnOmzh*93- zsO3Y)W5;vJqwk|H;5x!}P|5`38D1LglIW7izTvU@vHF-oZK~fPR*IZC-%F>nl6~;< z@R4!-9jdd(W1M%BcQa1hNin5TG605-`_1=*&%VM?BK{b#%+QxchQT;?7gL6z*FlhM z-wa4R!!UA_1PiD4e6#ytyOs9-y*7P!PxgW|-uO2BVK_UPc_PdF{(k)7pg^$9-0Pvi zU|GPfQ**{*?`yb1r2trVDs2AAa6!Y!S7Y7KEXH6HfkD3P9NDbOP_>{ajyl1-87-A& z118QwL+3|AgqA`O6AzyxNz90roE?)MI_^v&n3$v&lMkPKDPB-P*Gr?#7Z7<{-I0@xh_yj}ip^u9?zh{3^qLQ&t<2|^ z@{AZ%;ew~XVT*;siIF^QnrZ+aPlHnu@FR;6!9WT|$)F<*_&}R6fMfh2(Su}w)aXGq zM0ohaJw#f7sK5_LJchR?F!HU7g76OnaA~j$A?{u$vnj3?<}$Ad6-MzAk$$Q1SIPD2#A%y zE&b|FexDNy%V!0Bg+uFxn@M8==Ok!f$U;Z7gm=k9I{q#prZR&P7ju!vxda;g@U4|# zo<|p+coqK4-{IBIGwKTH3ObML`%Qs!77k<`Y6FXo9DrCjK2{+orL{HjED{9utReB*rcutw=x?{gQ`Z zCZZnglt;uKp2j~xY!chC$MuTs1SIM39|+RXBkG2#Q@)8dr0LwLp%^e zJU&DG4~BR;hIj}D#NaUEkTBwaFye?XV&5?0ucm((ad;T9Ul?&{7!w?Z85ctgHp9$! zLtDBuDDkS0P9DN!(6L9irWn5_tyt*?79 z3>^|i7j#V}j4{F254DhXgnpi&HTED)9ia=^AWdGOQ%#{$E}>Hop;F!)N8lVsf*ePL z9A=*+JuUea3A1jNht<1uSVqEJX-ea(|>w2aTim8B^)UhA)K) zS`K*k762RH!7p3(ROnkRNe>-(_K}8VPgNKLP#z7;x=S_55LSrEG;fMlaMCS5@nrt=)L?#oBG*p zIb-_v8Lf^$^_|NFjT>shMx9WlZ`5@iCl7o16bUtqALfkO9xL$(XWdht(!rWA%+<7^;x*wutTQ`JgKYz(7ynZ$w#wv|U^XExthC@BHX~ z{Lu`|zHD#F#>gA)Lcb>@n1L}1aMz#gh||@)s(q)dT7a)@Y&GSiw{k>no)O_i6eXfIr|TUM+mw|;vg`J z7=$c=DGcUfn2fVw~GV-kq7|J(t}HxsX}x zq4K45?a>Lp+#svZ@~_LTf`m}Yb*)ee{QZ+dz$w{ySO{3CK?Fo)r2MwmS% zkd}XVZ;SGeG`nRW%wDi<3YbWSDy+K3=kR|_~XG& zx6R8*=O}SM>pSe-%0sN!pNfJD;;wZ4%OR_YiCMzo?AwefTUQg49nh-(u_h+0BCYhf z>d#}#>(FapV)^2G_GHN8H9?+1X zt;{Pny=8Z%0l9e0T93G)Is3@rXR)%=TQD@*rIY zR=rWuFUe<#a;UF&;ouP`c!)Bv>Y0ejb6C z4?mT*w2pffU)&`yGbVyDVPX(Tzv~_CGyw(39p}F(V-k5{#dnZM>whpmSSY{A+^bO< zMz|n{vBdX%zV3!o!cF|XY51N+D9pTAvSlxHooa3FXc}N`U|l*^A-giS-)(T}-zDrv5@KCH zlc!je@qGVf)8kwJNCjotK*M8&>&g8X^%D5XjYE}v-^`5H+6~zKcuXUJ1bDtRKOBTB z5Y_LLj4$&1_|aa6zat@?B51foTUa8Cg06GXOUyR9q2*0?|8Wz!z7Eaedx9_3a>Z4G89GZtWTH(^d0DVabsQaV>ovplP~ zkT0(!DLo_~jWEy7{aW7Z=RemAt6r8?d)9e>NogUTikV3ThEof}L3&hc@XbuLfe3BH zYZL*F`xZ?e*1z{p4*j1LdU|~?)QDl#c!|j;Z*~?rWHven3|z)`WAA0`*VysTV)utW zk`d;08U}PPBrXCgm2OiaPCu&T0!A*b%A9_|wt*7Kd#H_!k!numq%u9%Kvso)xvw?m zwcTm*B20E>hC$RcdX0SVY${588cMC(KL{*}8`aStCFT*t?EoT+ElXwFt?wC9 z(-Av_iMq8KF$=s}4ocU!j~&aGyL{9Uy3>XND=4cUj*!O2Ldeu`!T^vNr!3iwjG|_8v-6Z zoF?((KQ0C@o+a!|-oi;4OsChig8M`J8aUny>XqtqFDHBS;IGZfnT*b6422f`e-7|d- zvSztEs~@POTZjw64tJnqxVB(@mB7&mM zy>5=M%u2TqKS&J=1jWADi7JlOfYVwoS}$XeHHeuMX#Vuso;bzGP?&ooO1r(lFqCk? z!Qde6Bt3~Aa60ZL4Ng_lw`m@REP&;urL=;>*WN-|7Mb@;Juu-gd@-^LDgL?OXca;I z%cJV)cw`tfI@6;!->jRF;aGG4;cXKATOrZ)sg2ZGU=f@~`_S=gwtVI{ZL z-I-6kpFuCPdCw9Yg9BJGF-#jj;+O!oZ|@^fHZM%B7k-g6Zp@fl#3Eq$cMKnJiYm{l z>-g#SOiWG!O`E$Xs!OW=MAXw#=jV{M(aIWmQyliHOZoe4wGyc6-(@J#s>LazqeZ#X z*!8|)ceUlJnEZkpF65!o^?XLq)$Els6Pg*P-D{QqjIZT%_>~jE5ZDyru=2kb{ zrB?A!keo{PHaOfA`>~%5MLcs>sSA5KKJz=uX!(K)nzCBdlT~SI2z$?1T>U7;pYmMO-rd4Ysk9*|pj1EKR+Gq())rgSwe71Bh?wL?Q?UUM(u_l7g%RK7`#Rjnw)v8P3AkhCM%+un(N}< z&qE)J8_k={o!eS_WC>5EGg1#vV#mxkj2#Pk=Ueix3NE*>E-E5YRn4j`4}!*R)tuw? zh$3-kK3x>Oex+qSnyb0#1Q_2qSg&;~?gs#1S#t-*6`|J=_qO%vO1#KV`?Z~57v>yC ze{|9rrF+g#IIW)*osgRK&N0JM!bPysy-}ad^+6r7`|bC-ZDVY&U@=xsQp$ZgvE3^{ z$Tq^Xd8dCK(4TIvK}?dDJ`o&w zYvPO6V}wu3C(r1YJ+THE<2_%s(JtD_n+CFOLbNp9Sxka&)(>|h=WKD|P#z#TTN6gp z^p78w1Hhl}+SQ8z&D}e~k|q%*7q32MC!@?p=b)h$!pSff)Ugyb5Ow?KvXE`IREv6n z<;OUk>nW?$t>!_X4DOLZt(nwS6Q|G=*f8$P8XF3P*QA>VHCCZ8d(cAf10> zrrXhw#Fjc7&S1iwq4?t`r_}&vmUzk9D##N`}|n08OETG|%An-pGmLR;$gwtWsCd$)5j~ z;*yUvu^I={0y$gkz{)#6wNdX_!pl8w z#mmcPbZ79#S;cpp&rf{5BqGPt=)S##q4@ES#RMMLBh!7C1B=b>25v!*`0_fMXQT0^ z?Wt-lz)Cs}3S$MJIV$%0^cK`O%hX)cnt@TKG z3Q;H|$(wjo9JS5)+CaA5v@P2eV%L)D`rmoNld`gI%rdJp4WZMlMWw0Qrb^!JgST&K z^^xogv#+kDoAoz_)s(9*H|LIb9EWRTr5cIE=<6QY0-leXF@v414obQl@BO5RUiY-llywgcESqjZYQTv5u{l;Uh4N zzq3Agv{f3>rd}(bZU0vIAgLHneT2YSMDX9>B4g)*`>w0HPr zq-XU{)kfbO7K)yZ37-!CpQ;8vod!NDGo2PbKBERc11sBCg;@iik(v3c!m5GK%*^st zq5ndnXQ#(!WMurC|3bcyzOes+{4M|HFWmoE`M>bLs4%i<;Ipu>{*zf581Vn*f7>1!iLC5j ziv1rAvN3$Akbyx9Ukm>~O~d>@rui!p-CtXL-T$(s`%3>|hJV_BasCqhTmI(|{w?PJ zs{A+pUz-0)|34Vwzj^(8JpV1-|JR22PYwT7(JxvNOFai8AtM7DLnB%#BWn`})2|uHK+pPL4SIZf7Ir!YCLSJGsDHnP zE@@|;kREaK%^&QWXBrHU%Vcyq*oX;yJu<3)d@av3(4~L~Vhv-$4DA{8keGf$g%>r2 zs`q<#8!KPBis5xE5OzC{m??|uS zPDQUZWPVy*Rb{!|dT-3`sLeJLY`?w&g&R=5Fd0i)K)+h_yqib@3F<`LN5a&zU9r+S=Y_WcR{$@d9tP#DSgoK>)(?)`AOoQhG(?+r$6`cP>z zioxwdc9QEUWp&L8&S1m+jQlidFh*ZqUeCRDs&A6b%_-!nK|a-RAhSmHWp{#3||eePMmm z>vr6FR8&3BOT1B174ddSz<3G<%DzSbRhP<)Y@@XK==NDAE(Nv~#sJ~hkLn8&r-Ys{ zDe%qUKcEV3S9mFT<^{#`%u>J-X$iwi65n_ zH^BFgBr0R2e zd@$dDE5J3{ZOdoK*3fQrn-8W`p{gvoqb^siahdJ` zy*(UHXLMI~RWlR69>dr;o{h-lFuKXh2}T+~Lk+{GXQFkkI%IPek%(cO)~i(?BhBTn zRA9rBI{}m`6S>YKcxIR^ltmL>UiWTYniNG8(Z%DOBgvIAv)-G^(sG?fUf;zOHcrNJ z&KFyr3?Y~oi-vRQ?8v!4-So##9mcto%nk8NPcGK+$d0l_4G;6f)-&Z+3x!{q*E7jC zG*p+?wS2#Bv0BiVwd>;e_5HMA1>fptbaqCAHID=4;va@OhhL37V{q3iK{SnXI%sNj zO*M6W@v#c|%c|9=l=@T=Np-5`KkJgy%bg;Z7VC2dhs{fF&mA*3K1W7^CL$%YT4pLL ztfKSYhUjF)4VMNU8K?I74F447F~wZ+S2at%Xm=3>Xcmf|zocbfXZYdaSX~cN4QL)7 zN{LPPcjyT;&%sy;LQi+5VNWO2y0?{qC5s*INQ{)04WJlp^t_b>$x}-_496&Dk{`#B zc+Qt{v+I{glp1(1uow$*Sjr>YQFI|V@~fYEzYq(J%G1xk&rN1OHvYTAVO5~ zE-cPm$oXGAs^lW^)5C;P68UE|h=rJtvUg>LutO*-nk(tg69W1Xl(n!*Q2%*%2XrVKj{{3FI@uCH=LU>`Lr$UU}jbs;Mx|2=<+-GUzWWLYL3o z1<{SBQ*`xAKW8d^MM0VSFwsLF-p>{LRQt5UFpcTcYYn4m&^XapK=qhnllozpdr*tx zGkgk1{FwK&6ag=!1L~=p%_teop@}NywKy6il93~Ft_b^tRN(y#xyS~v3Hz;kb>`2% zs5cYS9i^@<)ykZbx$P-igluK0@D-~4rpydBEI*fphj*)(M{QeNN8WJfixV85-Q74X zT3XsSDjH@^28Ia(Oq{e53v+&zNLrl6jEq-=?*K^ApzIHLrGocBR`RKBofU>|}+KP!0o; zxQqZzsH%^!C08(yFp3awPS2XeSMEi|5Is>MrqtnLW>h7iF);y=x}O|oR+tpPb)C~w zQeilWZe^oSscPQ{S(9Z|mJ>roV|ZOdfk_;TLtS~FRn(x~Z+fa`1)9K-p0A9i_Kgkk z-W3>DS*0v0*!uXF6`Vz%ypPWlQC&HorMO^4aY+bf<$gmy_La3sUjXX}VjGaBBq$8V6R77m%sKZ@I70?5Sc*CMCpu?dHS%Uee2wF}oOKegI~^X;hAOh!3)({G5awk-tueIY3#m zS|S7~Ulq^~1xS#TBN5I=CKIccg33ge%rA=44@M5nS0(Nj0HBJ|>x8(<8_CB>$Po%xBQxeF5%{Zw9Lr0^?zjL7BPP{<)xzZ+mLtj&?)=T z0V0z05+MQrs62E)KLp?=ADyP34iF$gFBHNB_?3@NQ3K5Z^=Hj}HKoh^F?J z450!r?=_N?wBlylDH~<*}o7v;Z5?J63>=m>p@rM%0e8 zd>c)_h5Vax$fnqJ336w`4hld!VTS~u9k&At$Vl8_2V}(WU;w;G`e)_2Ncv;txd{5b z0Jw=e^Z?v={Y>OYvFj>ic=78jWOy;VPUJ`NX`=pi`8A^cb@?@ter-UGyn`e{^o|VR zB5KD8U>&O;iQFh*7mCa(X%~ykDq-h`yeMgxj=U&g7mnPT-=rQ=n)j5CtRi9OkDMr3 zEg3SJ*Q6LCnb)Km5}McaGXy%1O(!H>K8>uuSw4-Z9}X~)kRutQBUY^yVkMtO(w{6p zWC8!R)J;>#t*Pza)b?QOdcJ+L(z{N{u@NR1Rv~~U5zWM0ge-9jeg-?9M zqq*eO{6E<7KSDM1?ppoZocMw+7##DZuQ1eXS^j)$WPqb^#PP~X~G6<+#?>Jt$RvmiDCD3pz<-b+k;o;-l1GO@3c(R_#xDnz387LjA|(ffO^*rV z3o_Z$i^=8@o<1~tV? z{^*<|8_bhk(zGgp82(ze(f@NgNTFA=n}DA zaG)`GgU~JZ2=>=A&b~I88+D4;x1+}CJEN@4AMFwYI!NsTcMQ{#dpCsB(1sovN9;K! z!5IXJItbj-1BF2u#BRS$d8c>xp3(PlNmfMfAmX{D?tWn45xe;udF8wYxeeWFkE{zi zuuf|Ux#ybA@=u$tK>cKu`*S3d!x>~v))H{R1t-~8|@#`%TOtJ(io5_qBQow2SN(Av|F_R*3hD~Fr(=> z1^)c$IIFA}(-E_*9a9N1Q)8xP7$(0VNv3pDbtVkn&FAa5R7~lTZ_)%Q*wToS28eQU zOvTtt^eKvvDLs!^Vn>$BC%4YwSG4)pEDj}SJmEr!LvXD4mM@xK%5NrA zECdh&35qEeKvc4gp^ql_9pX16lf`mXA2uam_&bsJ%K_XKj~zQw%+=d%gA0lXpdL4B3lh1GTGvxsA{R>>~X>J9x7o;&gILqWI_|*rz_F!1(FEDB(%9|5e4#kf z`KBVE0@EPrE9n#J8|nk?3;pxbqi@wrYl~;HWy-UnzS}e69_$hBRQiI^ zvH610LHMG)ZK%C}@tD(7w(yc^(|EJko#oXswb`oH;&yGk&~l^pd3=1sFxN5GCigOq z8_N^REuU#K zDX$|ut-l$=9qI`kiu#1w#nWk8VY89Z+`%qf>rwkSb`y^l|12@>ns7d*T@B$ne^mfaNp4^^!Ne?`Nb!=u;%$~ZFe@1(8oBtw!8;zSl8`ilq_AErQOp@% zn+GDENqj7iXV-D0h=}B>uWysHBmKu+|2HQ;0$w{LhfU8>uu(8vqu^HyPAg>*I5dc@ zufx<#Eoa|E)Mfcez-`zvk$C;3~ zw`OkR21Dz;`=v2o zdm<1@3ZhnUGo&^XKPnr6<*S+=;~x{6S738Xffh%m=!g zo#Uw+s!vg*W?$t-BL95)x83@WLb4Bg)~!umN5*RsKaBPfj53*JC`(`&a1P&D9|hm> zF48SzU7{*rRroTHg>N`~=%(N@U@Jb#S)it1DL%|y;(R|$zhnBi;RDS9*Ym+{ftUEs zcTsE!>5^1^Q-xCmj_-o(V(0>=0;TXF>C)FlsQRG_GzNYEZ12n7WvPq$6D|%opAYgU z%-DBhAZ=X^I#@Q`Bq%9hQjl05LR~^SV08E}kb!RoKGR*~SwF~uM7|OEc<8dx!JtFI z0N?m%>e6iiM}YhSLa_z$^YP_l+4@%FBZUtl20r7Xh!2VmL<}PCgCzDH5eQrt+|mc7 z3dp$YJ325(R_1i5EKU{>wr*KO?*KeVpwFd`jjxSQrEjGVtuL+5r0=B9S5OOZ9#9_O z4=@iH?C(6^KA_$}pBS$QuE@4Pwj#S;yYPHAK`w#8eVl!reHwimeOP^2eKvtBK`Mbe zLA^lQpx!WDKwU6gAYBk#fL(B1;9O8$z@AX9n68koh_Aj^;kjVDe0^t@z`4G0!Ek-& zg5UyLgI@!`1A6@S^>G1l26p!)pMn+g;q>M7S@m7@;qEH$qV5{+lI{xcg6+ERa_p+_ zV(zluGT)-uO6-d7Lh0J?qS<2DlHWqy(%&N764?5-<)KSvi)%|`3s(ighIRDK3)m98 z0oVlCq^1QU9s4!Y;M4xhJK}w^`jh>EckttI>GOXLy#3+B=(7v6#RkGQ0Tl6nwEAxW zHV&6wvE4HbF73}eBibjcAK4#x2LA$iAKBk*GD^HIz}`{|!{$rT8MXSCwxJ_mQ11zy z5G_p7T_*GotDu*O&ZL!l8wAevTbIMnP*L?FYjmm?KjL*DdE2_D#?D&YlcQmE%N|oV z`~q#hyTL%dQ=t*E@>Swi-*LF}@(es&Z$rDM2fBw1kCn_jl2>-UzjSsso?N9+)jg{}&&LAzqD&P0X2iotkLO{iY8xU#Hu;iIX6TBuwuLiDbD zWw;*JfG(0-Q@u{8+1tW>_(Jhf>yd^^S>dVP=1k?l$`TvYWcgJdITJkL$bo@~KG_T3 zi&!MNbM?X}(ZWaWje#;duF3;eGG$%b&p~x>F`XW-U>p}%p8g^zM{1_xQs%E^TBXcO zYie(t){J$Z<|c84nBiYUchYCZXXhHrxK3CZL@k|!9e(Q-m-=!uy+cG*KpvHzvOhIR&{uq=&7)j4^->?nL7gC8Tgw{UMv zJAtjMxDnQtG(TB-So|TIgc3eIK80G}u&_YB?C;69jrU##V}lSfMvboN^Rp`jfC#zV z8EEKoPz($;?smKj$D8LZ*$2{rrR-}o_j63|rbSX!@f$cyt`+M>o!C-cbyu90LY$O8168g=woe8N) z3|(co$oXY?@Pa%ziE2RLXfwO;_}EYIB#|b}c{x8uDvxyEOrz0Xhej-9EnrKvV@|Q% zx;3fyu$$V3H7O2mvGYN`oAV}}c2BzQ3qKc~$&ReCnYd<+G3e+}petG)vo0jw#>RR_ zxK>Xyc>Gs2WBZDv5OW!ZkCE}vi^cUlNV$DF`RSFH-1%T^^(?ob4L~ZZxs4kkmCLkG zebN|K^9X1>du*?H`AxOe98yLH!CH7Q*KdNC6SW?B4f1<=P4%oJ0!J4Qr}x&4zCK zePeTWqsDvKm(*A>!O_#F^bDs5w5gr-t)y>V82kDCA>(^LKo00|D9YLN%*RP>h7-E3 zhkHXsL%q?Opn2bIX1IF?YF1iT25#H>mM|s595LR8wSr}MXz3dukldeCHVhANeD3$8 zdjg?|Mr$6fG%HEGWwiB6I5?GHgm3c1XRDJRb3a$egXp)a>3_U4-D|K^BZ$pARmwGs z)2oji-1+(`Fp7p}p3#%d3ec096c)ldr2I0G%3zv`W^~EYs@!c!spA(%4ed{pr?c6~ z4q7%|IK9s1?6s^tazIUWJ^d3y5X@0KZ!T_2Utnu-iS|a_OOY@VQ2nPBwz=YYf`RGr z9L;uW2=(|zpBmHljQ=J|+;Z>CPyvy((5*%*L(%>>iG9&3H&w6xF#3TL{CM3JT&-4J zkM+X3jcfx}*aPuvW9+XREtXVDUNRHIg7E})L<4WL%fu(FWng22MPvS>macWpA+J2d^yWPGe zeY6KNZ#aaJP%AB)I~0(SnGj>nmIK(2G1vj9UM{P04RWq6wT8}5q4GGmo^|8LbJl^2 zZ<8)hzn^YxZr`rGKXc1Mc(2Jm-l!%Wd2hI`?Rhvf-h%%^`ZAx8ymw^(pBuN{=hGjb zhS#l@wRK-!9%w0-TWal>w>T{$8}#bWV*6~Q-rzRr55=?QB&O`yC<$4!jL)m7;HNPL z>YI~;T?`IL`YTJ5*7_EX(E2N50T!JKDyGm1j;{tQC1)46jnzgij|M9f0jFexb%M=O zw4R8nvDd8~n|oXXbLg{a$x?}fbv;rCokN?;V=?15th}eM&*(|(IiY3-ysg2~)x-mJ z$@wYj1}i;j3GDP%`=KvyR#clcTm|P;^S_LxIG?yi_dPo$U4Gw#T(4H#CoHkW7TA$W z?@FZ%B-eFh!iO_{5#s#1W17q`P2`!SiO>EI#xrU`4ZS5YR=8~Z_+p1NhJJY&PLYY; zQb@f`_KdUKd)4=BbyZ*q<0?`v3XN|XAQnPutqIURAXnOInx!On`=DN^5L`Bcf zzQ%nevmP2z7J=o$l({ebb$p<2SI~q#V0#Pv{?{~0uNM}u4oDtK<>NR-T7{mC4g8@q zn4y>fqV{L$J%Yk`8uiX#b(d2i9b*eG>hPgDuhu4Fr~W0?I;Z(AwD-BFBt&&X<0<*# zp+|%0(OMn(7cZ_S5pgZAK>NQR%qVPB-eV=}shmejYCEL196Sz0hn5>a1l649HV*1OG}G7q7do@Req z!cFHeTOhEQ?oJ`3K7Z^|8;8B%O|8(r$lfB(DEsNU30heOJ=YO6(xY;R zX-~nFpQn;^Hi*1cvEa?qHm6ujBX&M~tSr4k*P*OtjmMKeA9B+@XS%ghHT?Qr&CG%; zN2(A0ekB2KaalI2oZ~W@(!m~OaO>$_NzhQS`qI`vl8<5I>&>UZdAlVy8end~0mI{{ z-uA29x)hZ+tPu8{ysuWq9jcDo@$MB$e;PWQ)s(V|-@*}#(9%aKOtpQ%pjtjMg5vys zg>^%4#Vz`}q>g8bVmWKvx^n$CV`PWu#O6O=O!l-$!}vrv-g5&N}+CQw;-0b=TAe0hT)r6)SaF4SmW` zeb74DYK4gNM)E=&cI5g#so?pavyTOr7D}VM!XL*54#X{7DDz9rs0%Av?sLyKlb(r% z!`0_0GdACaWQ%AWMn*D`vOADkWjJfq>uN_o{kZe(9`Kk8>UK2@GUq5~a8^c6r_2}3 zUUlwBr_e-QSj<`v291w&>S-g+f(6Q%_2H+6b+X2lur$0wIgICy=uh5st%~Z~>v_sh z8v|C<1wU-7>hr(WxaRU`AX%6KR_954ANWkIvMREcHj&F9LFaW_PgGJhPQPWN)~|2Q zROE1}RxZ4z`blHWIdH)6SZJ zE4>HyZX!Z9RS^XCj>Ux8#i>6hntL$jRsVTvXh&!Y3cIQIT0pJSeC};FRz6vVc1ZwETf_v7Eq0=iUqfN(xoiW0yKY+)7~O% zO(gQ42J6@}6)dkBEJgJ=M_l!sYeA3T3&jMyFNjb%t3^jP%A6~G7C)+i6CSoingTVZ zv+Hvty&Thd=cFzXdo@>&;Is97e|E?435v$@&ar~T?w2O&*-qg&dUW^Ei^96G?NvfE zy$V_g!3$YLjA?@mv`8meXiQ%x=w`L+YKxx#^nRtQr^!kPRM+SY-?m-d>*;YkT|i+P zbpy4fg|RWUu!4AA#biZZ2sqWy=sBlX$v%B|dB@yVnP2fGSk7{)1HbwTTZ&xjHO7ZO zhYb@5;%Gh&R<4%c;mY_EbA}-)vjr|C*fG3&Wx&g^yE|c}Ac8}&KWH9wbv5Pc8@;ks zHa@obHi{`ETG7pVId#%dcDJ5+RBE zbaLKRoW`D7Bd^fBUztKa1>h!oHcOnUsMfI)N=pq5wv_t%D#>_PI`cBUDc-oRXnj5v zUB-o$(+u7w&kr-uuw zypSI|og{VWMx&9}mzx>BSG0dVudj3S70FKb#9Cz1BT`{ooiAB5nwB3-4|CHOcbXw4ow!gz8u24w@(x7= z4Ks_Zw$~7$=Xhg;g=$or`#a!|F)x`npzBP)aZ95$#@*U^+IGVjCzcRcj++6fWwRqF zrP;LVg+0x`x7@fJF`Wt3tkzDJRN5;syPY#DGb)|7*+C-5hx&PCo;H$LDwYh#a{X57 zvRJ?yNiIg0606;hF0wgI&eKR*Tne70Zc%I3`_558&3-MT=G6=vbF*R@*m0g~R%3B? zvev8g#-uDRiZG@Jo!6Om#_Yj%nPb}Qp4Idb|R|0)NV4& zUNZN(pyTEJx)^wQnR%UgyGVuik~0IxCIxP5=ia!iy)u}1l?>ES?gt9{t-YM+dBIaN z7gIAC$0uFkd9JoV5||GT-EMEyZtY{ApIe@r$KTeL8D8HCWk+S-9CGr0gE=8PLG4yj ze12A7cyCI+R7MW(Fxjo0dw6(w-d;ObD?1J~rck4$X{?#ha>-t}Z@ad}K~JuB{@QlUyrkv2be?_()}rD1 zIs%DURU?zNuEho|A+@so%Ht#!8)^91i?H{}9orF?za)DBrh1`eUY%+~(W~%H26-i6 zWdpIBMQ0VSkvzDOV=@Oyc{4G%l!C#XJGm#7-489DLRH?Ky;-JGC zF`sKr3Tqu`KYhY>8 zS1c4IlUFR*Vj0U|t+_UulSi-1X;4mMpoy-=I7L*d*?adfWGkG29Jjm-!&H3S52+ z&YIhyWg^DPWfa;>?b^qb9yt*5#V~c=mm~C6wG6Df8KrfzH?8#SG8*Onl)WhUEMuj?{ClS{Uz~HW!QV}78TAYMK6HAg6S3p zln8f1#?WQ^woVIRAjNNGc|5WM+yk{{2oQVAWTc+F9l}~O{>#b88A3@8dTSjiH=sLu z`W&~cO$&$DB&XL+*bWy5yYXQf*Pa?(>+VHy%jL{rikDuWm+V&5C3^P0=7{r$;h-dB za*f2s3jM5~3VMcGoR*`3;+M>t^`?{AJ@{6dXN%dDS|_9U_MC$ z4BqP3E4wo_>g&%_IaDE4)2Z6MQE^bS(ozAt|Jr?Be5Bp%b{;h;skVm>@-dwh%`l#+ z>Na5-x_M(^1D)a0fzG!Y&k;Et6x1YHxEPz=vQw zF^U}W5C-FW{Or)eW8zjtYEC1+e7otu@z&ci`nGF+LhzAu*v5`L2|MXI>eOZ}Bx;Mq zC~8lTud%(rZgEX_yov$LU^?hpZMvEdZ+^GQVY4we z*KoGd@L)!F(-5vVmzM0@P~1)$M;X~S?}D6CH&Tx15{Mt*KEcL*XdC z!(?Q6N~!7)j%K}U+PrJqt~!Puq0;bq`mO9>tM%Q(_eiuJ0r^Z3`~sT-W79~bQi**& zP>N)Bma#+LS#rc;EGiEw6~D=k7X6#%h2y-*0x0LJAb=< zt_9n!rv*FBy4kc2IO;DejFZ*s7ds#-g(_^S^_!D}+T@Su5e<2@^dg?^+GbjDSK)Jt z-s&CdW{-_e&6q?Qs!OIH^R!F812my9A0BO_E1~YFF>A zasFfDNk{yn!;!b98FXg4@tqB!LB_lTWafvW!IVM#7KFjsAm1Qeh^HaH5+Qskry}5I z_cRxm9@nP#S_%NNFv{p)Vzi%S-UCg(rF53`oDEgjcmT_ZxRy6#R>rVfH>7T*}u z!>(3cCHQ6*wvL!ik`GCE#K4;^#NkeNI<*w|gR*CI6Z6f*{5RxALATBIA_2Dv_O19< z=UGhXHF~)sJ%JH6joUT?8*gvEQ9XY2k)(?|sq25uru;erC?$rXEZ5f|HF34{A^-e^ zW;q6Ti$Yf_t@ALg_1S}bwn+z)ERybuuPEg(9Z)H78#lg{=gWpQSpKum}?uM zauTYJiv9tw#E)dRJU|jCB={=21N-=$AiR7>&#F7@b?4QC(5KNQieE1X^{Y2j6VdA0 z4wkXU89l^ZC@$zYx@!7K+Y9I6PrKIoHSLm4Dz>xMLkBEvdMRspR+xAxZsuBoKO%m_ z#1Vachb{H?rR0iUwogj!iEYZ-$)^;Xz(!F2rFlV|p@&aYhq%w}B+1r5#{~lL z`Q5AdzECf|Oc1HnzNvv8ys3eYUS#dlk6wNfY_n|d9bHfY8^wG=@Hc-^sG~5vB_?~t zX)lN{+(CRCU%v=r?lCX$(<}&ZH+{+JxQOboLZ(jrlLnEE|E-E6kHh6Vw=`34fv5F} zv*9%MXe{mxwe-LT{NMvj@Bug23T=iv%#wI`T&pjktzYK4Glhk`_ zCHlUq3We{n>&tX@AxS1QuDi5z5Qm&qIkq1vx7cPrd|=y{%>sRDCtpzj1a#z;vFI+tA(Wl@oMe{NwiO zqGel#_%RdYGa?}}pmTyfOZZX1WpoH}wgKeat>JmXFiWIA!}usQ*gBdHx`-dI@-V9s z5*o;=$^VWt^Zw{0j$UGq&MpWG6g}-+&F`z~Rm~rxYV%`qv3fch+LE_971^W}Y9DOd zWs>*^q-HaYPY{n%?&5dFfp!=i^9nwfZ&y0zTpviBMn_nFL*iea`3$WC^NI-REh5!1 z3tbl*ZNQoW8mrXLyz!@&7A{#N#wG&Sha?`S9Ddy%+rS1K+; z+{{y#fDN+^xhP$?S!c1L+VU(6e}$J_3NIc56%pG2SNO_(i3d1hE5r&}MCQw!6CX(@ zItWdl-RR$v{g_{(7C&@}OknE)u@dIJ{~5_^y~PV>?C^+Ik9`&MVvlb94Q6M7%;Z{jxRpo~OPg=t%4Ofq7|Z>vri` zG>Pl_FG>V5zK@FhQ7_2&j(hziqt+(qLXdt@_Rta9KOK`kAWIXE_vx@M&CMFocC-8( znjE%Ci1~Ubw-#9O58GIZT~&W1GbB)?Q@NOY?daZ}46YKf=T55nY{$CG(sh@WPjRvKa*>~JQhYa-Ii|+YQM5+^(HczK+GdGKy1Zq z#$4Sc-R{ZliKraL9g#Dv2HcRuE*rKWCx@47)laS3yLp*RQse0y#Pl|-6Iq~@QO+i$ z2Sfa`aW&%|vpc|pvkGT-bpfH0G%~0hxOc`6=Zf3Xtg(}{<^Bgt@rWcN$b};mUoZHeUJ7ht*LiYy*{9G zmY^rxp~s#Etv5*wg=oMDmH3cBMbP&$dU{a7?U@81aRTF^EQEXHLUj9IN#NvD9R2NZ7&VEN}bAove1QXYeC# zHh%Gi)jpPzdP8G{^nR`~8%Jt30-(%`vP@q{k5ME?Lh|Cf5Qr=7=CtdbYQ@a@9jShd zeSX7j^1GNF4K;UYT)I=PiOzqL$%PZz?+2C5nOQBU0UTk;pC@Fpjj_053zEbJ->R($2hq1nr%ZNDO; zdAgvidGcOL48%rR@X00Qr>SbJDF1q8^$QKn_T!6p{>bxRU-sF)u7+QA%6sqe#+t@X zAZ+gQyxgiYR$UdcW03Xx$F#Gh&wtR4U-}5LyD0g#bVhJr?9j?F2cct>|EM-GI#1i6 zE&lM}iYv?I;abCO8^Y-q!b|WM)RG{}>0jq{ZV#mCOU%+~KFgj66ArSmxUccvKm#w> z6W^1(CSC6fBwHUbN8VLe=<(;ro2bl;f_GvpFvtr2z4<^WtwmT_9e`tsUO4ic|0B&d zirGkz(4NrBfLTDF=-Y7Mdag=9MOm)qx;wgs@P=I*t#ANd1H17stk&H9Su z;urog)q0z7Z^*qZjFDaRAz8y6Z|@fs-N;8%buQyukr&(&56r77a$3(=wjIua+auPaQ~y!ua=R)` zcy6aEO=I?sxPdyP*zdj3Fe!=tZ1H1MMt1QwV?>#=@h7F;OVDf)3`4qrB zg8TFNz2lfX%^#Hix7%vjUgLnIS77!{{fk!)Lvn3yR7=Byos?JJT#ps zc*{ald?0s1`{>iBFuCwT8!T zUZ#?N`XRlYLz2*=xR1_EVu_|^`_CP7l$ zoi#&WUqO0aFGRLV6HyAal=tfgz8VyoJ&fN&u5TH;69}(dD#ElX!QNnr(^}u!m%|3N zTG^FrqJYuj0DFi8uh+h03tFbVyVT16#kAjV(rd8K90hLVP3Dz8lut#C?lWCoJANtn zTE1=k80DBbq5gS#z}5=9D<*flbj53LJcJaTCflks7zN ztXONL^P+EdyiiA!USTW5Op&l8sx<4&`*+1=GUI@b(ii&q7dxz|?8~Yea{EMNQQy0G z9eHvDxua?Ln6|`b%>Ab75Wrl{PdN+WNy({~%e& zcL8j*c5_z(vN(YqHRk*NT)l=fh6L}8v2yL3IO$gVE+^jQj_2fF#huT|?=9X15cOuh zy3vr3m)iau#=ds@$_RQ%R4k1(gaUN>+@AIp=5i-ws0KGP`Tj_1TjzB%LzWBGSy|v> z+;Swki6`$`2O;^;m2Gzjhj1!v<=?ShP|+&*|8K-0YzIg03TTVKzg1|9Aipia?#dO* zkUQIfwblva`ecy#B9Q`sy!4J@K`XFUtj8DS7b}y(O|v0tw+fV`Tw{R$ppFP4-HGGu zV0^Bof)#O87IRm?zhi+MCq7C3Z-iR@^r%7=+oxXL3UlSd%*R+EqR@UjHe!l?v;QH5 zqMGhw2oC3`mBWb6){v`9j7PH7CDA+aPCc>zAd&EGNz8lNY;y6loKSC^(P)YrK&Lva z&xJYph^P}6s+F{6>=*53P3ABU$4YLRLPl)O|tL0BmVigdb-+vB_H6xC^Mo;!G#!h{$Vd zyHR3^>!xh<-?t2glBpiUW)T#ws^a+uLJMS2C@DlP8S0lpiB0U*7_Cz`X4uo6PD&!a z#eDh^Ku8xRCcyi^liAGch!--1m776(FSbJ?B?7n!8;_vueV?%h{ zR5P}NMcl+}c_^2)Bz)!G?S=kOx?|x;i)@8p^x1$~jaPKY7B~J*fDH^4wEw5X8fB8S zc14tZMgNe&w;)!o_hYItFv1lb>*#~N&?jxu&_XyDU5fO8PKU3qXjsD^R{3c6p+;9f zwY@EL-pXrEeZwE_CEAnj)|+jZHPoST0KVnO>dotkYm$#X8o!Tmq` zt{w*xmNfL@ml~#*em;RY=#K}}GxW2-20;h(dF0Es`{e+)<7beN-x&_P_NUy1^cT9n zWn`#IVwRF%oTKAX7V(i71F!ca+-Cbz(i5$8WNKObjI;;e^~Y7H;;C1y09{`~!_c7T zCtiE6(mmwJ>V$ts9~#~=p5%=sC%)3piL0Lr@cw%J`YR%{tti&J4yqBn*$+t7AMD-GVFQ!cE@w$Jh6CkXu@Yj=B`@XiNoPWvFA(r^kA#9DT z9{(`lkH~KMc_KP``->}7#z653g7{yG>aPZXe@wmAsYLL&*|!Mjy+Pp{P+4%4wkFM9 zU#!G8KV&xT(3SVtXat0+L*Y49tJ{KEIrb=V1|_Wg43R@fIaTf3zh%@7+eCDhH_Ev| z0lDZs!ETR&NbtXG*?hdGp7>`{~<^g1pj3F z7p(3?Ejedm12$yYsjmxrV(jK>+0O9h8F@PDg%Xl`@nT^A5-47pTZ@ z78|xm{XyaAj{)eXActJu zOVpvsW$i!dp%LbTe^^+bubHtr%fZ|H;Q z&>pk<%p++~g^XIS5Q6N)o4Mu-TT~AD=~STg4=T^CaVQ?WfIF&HNxv3cv3dK%*X$iC;S=IpevtXPloQxyI9y?o*T$K|hPTk?7I z{WqgOF-wX6B?8PxLsd+5#G_T*OW2XJBmHS}-t^OkCf{TbKi_@`fS4fIa6N!wM^(*8 zB1OkJ|1QC+;3xwW#6RHvUBr!I7;%abq5>pDzyIIl8BJs`Et~c;FtOf>bzFN7cm*aQ|llM4+Ot90s70i2JX_ zq|ti&Q^$1%Ur)+Eb{mavP;az_d^M9#qSP^wn|vH603NlZ3enr-MRN1x3=WwxnEY`1 z@`Eb;ES}Jau-Fc-WTn}YwDml&gsRHIjlX-k#K_4y6Z!=Q3aHPTEGvxPFQaO-=sVN| zH$KUGAI`an7_S;bJ*F8o>5Iv~%Ud5OHN&RTPKDip_{;cLS)JuwwmSlBa8{?I+~ki% zuyP_R5KoF?s%bzA<{2pQbm`R)&q>rVmO$>Hwugqq2$z2urXwiR;-wDdHqnPEPsc&Y zf1B)!l2ePQ^Nacl&Ho}Dqcc5TE>LcheYiyYDLEqKe~9_7SqYe1f1KYp*sAUHglt?7 z+`?G;+0EyoqoX&30z(Vy8(ZviH@WlHLLI`QvBV`y{V#%&lp6f&rrw@-83m%$-C1lT zWtW~ftVBJgw9~tMB5SWKt!~72=6E5T5Cj!6ym^|owh zNZ0>izHjH`{1G(rZV%^eG{aNAg~;Yn)G*gRS1{)(Ibj<&5jP5MKZq;3C373Of5s|V z@6%zIh0=ik+`-?2tA{bl!dIwT070E?Vfb0jShL?Pi#@1e_+D#>r^BMUQpJ1k0q&p` zoxGRhP^68y?3(W}k&>+ex!#!|>OI>Q6~^i`u(m%Vu)(x&R0wt2D)!=047idNnO%`Z^icA3KFN@+c z&Do05KTPT?GfBvja_s@C$f))J;6Dhar97bk5EVy-F9uZLz()Wo2;ilElS0MIKh!$K zA58Se+eGlv3Qzm|{UyP95ulvtoO5Dap^T`D6K7mOMwAXUm-Bm(M4|ilBFXbybC?7DZ0;on zx|pEdy6lI*2DEDUf*U#H%9lMu1tm(?&g`S>zeD&9p!1@}UeDbOA>QWX6vaq0;;;Dd z`mhaqUW3L2y1W6c_*mBGBuTupA zEV?0jR53fzY3Vi_m(ItHK2*@?xANRsdw?^PMvh#$+w*EY`P=iu1U?^~-D)Kk%L(($ zt%yPZa9v1Xg%mk5q??IXPuR_t8GFNsxE3VYC#qnz-Uk z=h@KN@S3xar9!2(wKYBFH5U_5xFA)WYG1@^l{xoTe+m@_@d^9F3HRqsS~c8XzdjHC zocYb;<5lqcH`-M`<%Hv>RrhICL;MLf-abuJE-iJ<8O@hf8C$0i|FEPZP6KRkm3TIv zI!0Mv%i$INgg%>Uwy(7 zM_q{nUJ3RlFN6=k6+PcgJf*%99WHz;o^hW&>|Oj|C*akZ*0LnGWTSQz9aTZrRWomP zSeJZTx+oO}Ak|k6A(#a2r*$uyJyG*yeI3!Is=LgSK>^ngRt0~yK&6AF5>kN9IPat zlx`op5!Z$Q^_9|k)9@QkosW6C3c5Bt7Un|kfdIEUgRemY3Q_uZQYW=Y8A_|l)G|`a zx2dR<(y)?*H9ua&=24o|F0J8>(ybGy!v-`3>%PM&tYbmog{1hB6pF3jtDbN-I6Lht zXZ^3IYj*yp*mg0)ZWnOLLq@Ps<>UZ z(XgD373P9y=-t6$>YrkN2ul)ye=mt zN29EYUS)$I@)-FLm&FcJ8)rB^;CP43tdKPBk`P)`pr=CMXvPtE`s}f*d=Nzjg#$#~ z58bBlT&=T)BaXB8$_0GJ&+DphO{Nyx^t6k+^e4=U$)rb@uW{1{4RSr;Ll>Joz&ajs z&Q9v4Tj`V$a@8KgH6Fu#WlkV;tX!}&nF@xqGFC4}@ghO`k{R#Hd& zXo=4ZMke0>IXtJ4F!R~rAaQO#k!L><>F5#Z$S3I%|1rOvP|*AH z8O!P(+~f(J z<%EnrqN(Pl?2IIqz2gI*7E;g~jGaOHRF=pv4l9DmJInH$QSx&eQHiySY)uX0$ zwX=6;|Ee{$jm6}+3$LX%xV&`5!s1F5dC7c5&Ejg3$ou@K_V+cV@&Vi7<3bw4`ds!N z`v`}b7~awGpLy4 z?urFXQoN6iE2>g-a`ujma~~KguUp$YxN;Y0S&aHqYBn}Qty!iI;2WF2)J@I)vF)RW z&TPm!yT$4(8Yb`*hVcM;#C5#fr}4cY%nVQsk?NehS%A_(fm-S5yGG-u_P%C1TUt}s z&eFwBIu<%x>f?M+$0*Xu0p@8VCTfj{&(6P?_t?UEo~rJZ+^&^%g(o#-RyP`5ubFj) z;}YaI1{(*bNKQFJc#gQ$93YdL4mI&=N8EZAZYS2K97}f)9+A_*Va>&+l&2jePX|Xm zPdP#^4_BL&+zzb`(rqHkgXUZ<6EGR=Yts${+G9N(oFr8P_&GuQ4og)~g(ZIQa`mT#TA z>)JdyULlJv+g{C!Q+v&FM_o6z%|yT&*9IX*wp}Xs!wG{}^^2y^#*dv$P=w)l3hREQ zG$Af!i{VG$%_rE@TWOA|eYseH!Q3i+tGYVQXj~y1D+g%a{l@H3X7DMeRSMyvK`J2! zW|lv->|4Dfv5nXb_v)G>zGO+t-Z@M+22Bf3mKj_(18u9wVvyZaIa6+1{P>rFozjg* z489Z91}Od1gVs7hCdd!?v$EB2zPQxhiq4(H8cICqZm=^KN}An!cuZ7Wmv}9KX9Ki@ z38XR^H;!8JfbEfy>k>C4s^(4Oi3ja-G^{xXK*sd|c`b--&WsgjBgnXJbf0@xML=vp z2uyyo0u*SM1~f3%hbYdHQWbpTNps?zBS5vqD+W4`(y)194Sd&OH%gG1nLH&0G7N&_ zqL!%EYWf{Z*>w_Rro_vSVh%LT&U75bWnzzF7JeGmG0&7n94?Bx9L3E1G^}O*Nf|$* zX%?-Xw-aOb(=ef|K#F;3FeYUEP<@Db_a~}5sC3yt^|(?|xiIEH0NYC}20e(I(iEnw zwQ2xh!IT)pPAkgr{5~#;iDT&acmvXNVN zhsM?WNq1%Ab%AWZFrti`z>vb+M9uIglJzkhCm)2Og%<|t(|b48b_rVLMd~wD3?m5| z!KW)qUZ_gqJvtcz&Z`xKnD%cdoyI>dR4ec>O~@j1jei`huGotHE`yAVU9}U9BaSRS z`VmmAfXxI*=4zcfbrw1tTXSwcfX)fHd(iMh7hDGCB)H2A*QDeR_pi}zAInC1XdA1p z&P^a4krksPhioAp4_0yM&Q>j_Tcr33nl}6`K9j1v!)rFhb^RQJ>3Z0z4-51cTo!}I zr86a5DTT%ylaRyK3s0I!ONr#cPgOIf+{A;%IWv}=DInvjQA_INL9r?gQ*Puzq$V~M#qbrzmmgCO5Q8DBs^WR-9p2nE|W8 zh;)0NVs}P*4`iFQVOJVPDPfXBDPey}z@8^t{4e#`1;mx1aJUXQ+~$r6B>G1G{<2Ik z!_A5UN${qvns|yy?H7xB1}BQ4U!lkE&EI(kk{iglzH?%NcDAK2&WmeF7 z3CbZ3=gD`PT@{?ludcFkdA(*vcFD{C@+vv4HG-?ccqjh&(@)%kLnru2 z?*M){v|UnCm0%=7Wy%O55?@_jj6VX(?j#^!SWs) zEEjN8!OKsOt>=h%lT9Ag^O_fvX2sC+wO+RyFS%Zun%(o3;PSPUE4(s9bl7}|>!GON zWw5DZA{nTyrXEeCt)4Z4XLxn6%Jr0SQIO%fxPsRW*}BWBp44SoZa%2d4*jsptDYR) z;|Nob$XMe%gkCkU3s+V>s5N`$95sq~bn^kv(#gt4Jyq&0h~Cha7OlgM;N|I8cJw9# z)m_IP4w7N}yBEw|MptOeJ)y@K!)~Elf}IXzt9(4islEdt|V2*FVj0SU}z8invC686IoBOy)Q}p+vu7VGq%6sz*K<05>8+=XaQKp z%cho^$RG#7rP-wB3HoV>tXWBDrI7Z{pxS_ezXFv$-jF8z$cZwr;bLywtn!W3QU1Ys z^;0d$@c33p-T0Di69&G=CYCndW}eTsCujFE|J}=}HR^ekTPCZhu}#`PsMk9=Ki}L#Vlech8 zMs%b%-g&rp6tNw)bvMhg^c_;&vZ^3CDPgm34KNj#)I_{TW7MN`n~{NkAbbd%T~)GO zQgDSl*4Xi~n7^$^uA&ILWH%6u&;bUUxgxf9ceuWcUgdE`;W*ZUbgm@^(Hy@^Z$Dxs zc3{OnJ@ya;U0;c+t9naK6yHr0*j(>KiP~Bd=sk4V%3def`kexS_SeU(*>@oXm=YtF zdQ#e06602SQl33_j#m!)G6nJz;<#Zq1@hT`yE=LFdSpge79Ay>{F;Vdjvw^{*1A`1 z;P|Yg+-W2w5vY2WHMK)BzA$zJ1{lm`VbQHdf)fwBvD1h2h7STHJPBD^BJuSkRQEw>QdGa{6r1f>qq@R? zhP&^2lwhL;<%#U<=XM#Afw0vcSC~Q56`SrI0i|~&rbuuEd54lG9T%D>-T8aoT%_w?Dq4XkEbV=nlJ=)0%xy zsajQVjs3Hzwn~D~wPPVG9ls+3|5IXCHpXIlWH-6zqXcYeB6%Em4%?dR(Ju{<@>ZV5%au=?9U;V z0%BFuQ2Ic(e`J2!IQvjm+gd!MF*s!ItXfr-oHn^%Vr;@C@TbMCT2+}0nzSr2HsB&I zo>3p{-tPmH!xeq~-~=nreiuJYXCa=mn!jojea6r#$2k!H@bf*AnR52k6cR^)MC}>! zg~lkO^m80q-xu%-na_}L-uu0vRd@!El==Q|CdM@y-Zfg@OHDdIRjJH4EYsZoELFZY zDgFlg%@l@Y2P=t4Ct_r0^s#|<5TO34fi#d}SLLtB-ccBJEHLF)<|L(0M#Gim$TpMU z91P7P9Oa};HWnL?G)>0*Z7y2HxTLHvP`lNA{+rAzxbo^@6!fEkc{(QcdL-Tv542YP zHxvQQ5!(Y~pBI?sXg(zoM#2Y8JMcP9dsH32XeCmBhjC_1!uL7EFOn#3WdL3!1;VPz z$m_l#b)j0O{)!RPPay1-y{RlI?Cbmj+g zm7Za~bYkj$d!mZ8ZExDS^Dp2{R zDcO~c{|zjBzfMd@uUyV1^rp|g6s%2A`O)i9H?R2X&Z~HD1MuYeAp7t(EyIA3Q9}u1 zLfi%ztgRY9&~LAy!TfhK_lFkUj;hqpxESmIQpPHMOic|(IDV72@>Zs&9A-;E?|>G^ z7gE%?S^OIV*@POLlo7^;qmhis-^4kjs-L2@R1+|KoM?-SG>Hzt3}I0XeN9Oc)gMS=b(!qxgZp(;r5 zaUVZWw<=P%g8gN2En`MQ`nNSyM6PKN9wT3k9=#sfq&>065Ax@VMe1Hi!G~ zG~&cR7y&+!uFRk>t4~Ea2qWs3(&xM36ZHnBH7(og4AI zmO{5H(H*sjB9GI;vI3T_Z#lg7IFeDTy@f$r#eV?5C%X(O+;@C#rR$sEyZMguZ%)m~l{e z_UBMA+eFlz>ujnh&}kl`et@CGONd016C65;VRxgJ-kN(>?9VnC3y|;J4O17wET++? zH)X{Ap5>3Gq}KU;L|uwDr#5sFuX2_`RjboHLfr~e=~E8v4*<>>?bC?no>n_$0M~g_ ztuD_co0XiWAj?shmozb^Zf=HC!x^hdB+X_vMxtE#JC2M){YOZKXX1N4xX)r>4v5JIk1Ld23FQysGqo?}^UoT2>v zp<&Ott&G50hX@}qNheUi!{uLuH|Xvw%jW)j^4j%?mtR)CEN>i zxqNc;xH6nE8g(;Dkkn(jwLXgl`-BPWT{LgU8mWmrYI|Ed0CXULE9+wuQNP4NlFv$__EG5=-|3>-ywgRl z+q>U#UyM^H=ic?ISUei>_;}O`y|n-s>DwiKD=>(a60YR*WEsUsmtSwH5#;O-FW#QW zZ_k*%ppo~MKGfddp-U&rP@i2m*pU>v7k4`&w9(!IAxO6#Twy}xz7C4K@$jj<6HM|{ zCs2LJp#?m=OS{v&N;u)^m^hgn?df;v?e)sm4T}z3qQ;ZZ(72(LIQ9@~E+mtE7hlAc z5G2w&hO2qR{WN+Dwa_ThxSNj!ezTIPCQvEfOX-LQ`$Wa8To=5c`vC}}H&g&In%h2e z4}u@{BOoElsXDG=Wx3(A?v$-3Z2iRoV|YrK+BNcd3QtI~1m1v8M%3fqW8r>!3zAZP z8(==M{GKFmk(a>B_HQu?FP7wrDatQ4UOYHEl2Fvu4Q)#Sqcxu3d zO@s@V-sS*QIdN<9g;x(1cg18`F>3PvJwqI0Wtn-JYXJFF-$cjJW@5^!<8G?#qYmd| zEw>hiSG<{=gMA^1h_$5`CL&TIcWL4(ky?l@90GBiYh{3Fj0EY{J`>8Dmsy-1b8fC_ z2p-)atNR9h@d!UC6uG@adsuaNdP=^IHxO4(qOY&ROd0jFnvRm&f3KzWujsskGu9;L15;qgcUZ0MO!c^RE6($N0(O6iSN)E)FV?WPg0y= zaPCmz9W^;zdBdkF(zCmz{{O+Ozhclf^3mT)$&wwM%`>)As;Vv2n48E_ntVbU>h91h zClk@@$cnupl^+x z+NtkE9!&~^AI%L*$R5XLkqk**GQloaR4f zU-`su0xGu1iQNu5-3j^-COgVE>s7PWxF36dCgs|Hdinh(b!*YKNdJSQuZ4|(*3)tW z{g0P*jswBsq7U~=<3_`U&OJ2eH%8aT5tgn;{e@togyM`iCj8#`(%dE5MeRF_?`32w z`%1Y-IJa&WyxcgCcx}PkqUl!^RaB!Gl>2Lo-?}yLChH$nZf z2&BiSn6^8c6sLkh%~KETE>s;ozefg({bPhQ1O&jHxdI(Ot?CmUu}8Az!8dCNe;ix43*4_kS8pyoDypu*v&Q=*v(ObK#Vq59Ks@m zoIX2#UImZYKy+dVFm>r3=mD#<71VY_Z;y@Z33NuRG@hY@+0Q!;gf`5Q$KK8AXT)+{6a zYWN~BgUI_g+%ky%j#-xsVHT8>@W-{!5i~P&JBk(qA5A8Xj&AO16P@@Zh~`YCJU?%L z(P^~n6g*x!MD8;_ZlbEXvQQ9Fxj`PxE|ungY5I>UjyuR3+9e6=rA*9hIIkG1Mr^073T zu{Ky71jj~t@C?YYA3k*JL=wbxr?5dmVYs7yROMRRAhqVoA>#W#3HDl^ymu3oYFLZt z0_>5%GZnYkANRoA)^*buNTauTMcTuby_&pDfLX2+*%ula5*CRN=7KEk1IVxUhL@+( zHmgI!zi|YZ+2Ht~mfNfn={lu(*7+@@oK0h`#ZAdSkhcP)h_wShR0G%e`UTsb9mjojl5VH`(t5rg_lhM=oevrUN`4n8uF-MYVx+6(UEYt92PZBfm%N6HmIrTu2`xc=4gTvC5-ZpK>U_o zqo%6Irr+Z(uc=zKi_r2lvGkGz1b7Ka&%e14oJ?4#q>*Rvf*Zvma_tU1oSN|0n(!Vp zZ)P%Y++2UXuy;KhdN@7ltTr1<6DV)yBzC#mDRf^BFcTykZAPT)=xbt) ztil$eJkEbco3vbR3O73!%L!=A$Co%lDzazKFEwXPUJAG_AUav8Dd)vGmpWQdnF5sx zkCc@+51egWJOo@Fl%i2-@U{wX<+w{=7nO_FXBR`AWCFFO_rl&y89h$puix&Q3=ox) z7S~9W9>}N$X`3leLivbE3lyy1PFu!(ClQgi*eYm*mz)LDv`s^k_QrxobUtgfNd`h3BOC#O4owhM?R-l!U3Ab*MGmh)EwQI{N@G07MwIkeFUo4 zw1SRy94&yz<1yXMd-!H`pGs=Y`v`PFRy>fS`>2yqVPSB3iS7-o^LbZvU49c>Cl@yM z_|2!@L)-EAF+SS#AVA`N=?vQ@1B3KTD!{Tgpyrr z{K*G&r={n5;+6M4#>OtjM}wAFG0#44lfJ~k_&|r`EKYv2|Hj|{i>Oy<=qF4Cx@=B( zoR>J3%N=M)NO%~P42oj>V;)D4M*#;Lef<|%LihJBA_7TiLQ02+Nk^W;ki$MI-S%&& z@BbHD?;M=T^Syz_=EmMlHnwfscCtw}w(VqN+qP}nw)rM`W8>!Y{oVWDt(sHMb1*$M zRZ}%xeNOi&W)opzd8EK-xYF>YpNF(T0`me0CQH$ zVVk0;N>WQn?bXXlL~E0$x;Jxj&(x?~-V4!-G%NH+BP*82{R>$(|0IK)IwDOHK~-+WB#NMSr|?06cWc+6WV@|5 zieczXKk*Fjj7~XLJ&x)O(G&IwT$uw5*xtW-65V=s#&n)}r9O2%k@$|i4QWq}cmQ|? z_^%6m5`9lB_3wZmfB1vHc4r=Z5BT3AK90QdddBsKQl2f}S-r}7ruAo1UhqDwy@GoN zcKTLcJ3hL+vU+xQX4qe$KLWiHd^KLZ8dR9#fN^6?X+&|9^$hGxy2T|rb8WX{f1nficX+p!6Z{1%yTa}Sg3PiLy z)uJ(;#_Sz3|I+Ix)%<%q5_#!%6Oc>J37d8Zc^A5m)gN2SZ^2f~$tNxxRw6fwj3=hpq~A+5YGQ@AK^p4WJXms!^V$ zJw4|A!9#d|%LVNn;InPqx6lVtTktgYT(x2jK6rmu2bE)j;^PICo$jyUu1L4Hc&R258He8jbfd0 zee8{6opgOD1NRd5a!)qmF}(X|D$ED-V_lmd3rqLHI-D-5`tecZiTsa;_>XZ?gj;EH z1WC6wUp7OBekWh2{uo&9_m!skv(J|H^6o+XeA{K$m$&<_S3#UP0w?jbLhiF^CQ;Wp z-9Ls~s{E7@r`@lbnp(*7fqzJOMfl070fruxmF4<#HKSY}oj%gbOSS;yKP0@O@(C&D z@((5T;n{g+qZRijua@pjpK@QswzECw`bSkB-Fg(-r=lKdRz>Qk*7a4}Wlv*ruYP>L zJI+adjS>DrZo9zn$V==R_=#|&Z0MjNf&{ZL;Ka!?i4ZYy(jRZ=&dF1Wt(I6YKxl}} zNp^w5M>!JWJz#cNvA1hinu*Ovgp`obkJXQL$h|jeSLns=Md_v4jTH^ApQ8N3-6;S4 zHzR3XX=Z{3OlL&4O~9WB=VPd_B4zWlR6DEI+CcH9n7UN(ExF{^2v+ghK=AKpH`e#{MgbL=M~4Q z^Bna#d-@Kx!*%O4LO9a)=YeLbg?FgbN7d6T{HZUqM5jm>kMDpS13kuqn-=9$VGls936cD|UrugJ)FP9du zPLQIV2)N*Ho9^c8W~yCsy0w>OhQEFXYsmFWe>y(hU_ILeE8JnST_v>c=DK1#n(i64 z2whs^Q9mXSw|Qr}ON@~HwDe_j#TWNE4SVU`TUL78lyhRXa_L}kC^XF^F_a|3=T6nqIfjk1zFCHbZWtl^yt!R zl5GE5CG63o%HdJ1P3hMoRj1aE`1)XMCL-~j^12%V(l!2JpEZA)!$o-Cv}y+LOYYz^ zY4XUCCOW4}VaZ85J67k;CnEjI!@nt^1b_BLV{PL7o!ty!JkZ#wk(qU35dHi!l1I`B zvPsBGiN_k_YI{bUNVVbI754+|R@{$|U|+&!VTai^fk8Ps{i{anG?2GR_?7tvpr5hU z`n5ASbG!fKkAL$ynkA^7U?PMyxWLCsR1ow<*!0PNE6*Q5ZhAAPWBF;ao?2{w#^`?g z1op4X;?vTHspnYYcrn0Z0c0?{$p0||#{)i{JG|JBK(63SWnzkIF^}GyZ>ebKFDq+a zQ{>!KC5ELaa$o)zyK`eRk8`~m4{twk@A6D>^#HyM?<=b&|H_L%U)=i{sypsgYa{dZ zj@OI+yNS??pvUt1G0W_?U^lyiAz~DXP~!fw!Js{boRiv=Bk3C3{!_13l{e?}FGpx+ z4EZSZzUy5@u7v0i=)m~#JBsB#qUr2!^|$1;i|I;BSIUY{7%XgwOjOB=Q-2HK+kp3< zeDk+&5jR-ioq}23G$312U=0whlpTrxPpV``;L7YRc%+-y2&k>BxzteEwvf~amNN}y z!BL+p-BBPEU9@upMO-`;C?rg*1NsFOm+3|k{xx_8#0#1)^HE@_7$8HPKx5U08Z>Q< z5r#M~r#Oc=Ke7OfF6kdro5D5JEz#<1U}H!TjCiYx20{RTvZjmATJE*2iuHNJ;^ z4IHbg`g|Iip|q{65t}F1ajn{#SXZemEo&dXog0-^ea+h1ftU5oP~3knVO&PnQ7>wn zNI2vpf0NlIX>in0#E@M{^YmV(_k)!%PMRZx4kHALGG^)p$;A}jNVsEkM-ns|nz8dtwfN}N^~)Q{lyraiuA-8!>0EU8J8(^qcW3sHhRPhP%J@}9e!3{2y*ADAVhU#6+ znWWfKj+t0!quinhx%8u}G!`HltV3^fD*8mc;(abS`Y!G)FfM%lYrnj}1G~vdDNEs& zwy805v*_I0XsH^x6yzY*%3m+ttw<`bQhCXjp1^ALcA%aq1tYs}OLRy{$ zwo*vN-rq48Rxrxb9Q39Sw4+G1f;h`a+`xN#3;c1Mnqgsw{PeKImc`$P-r8MJZ`aYU zAg;&44~*-as^VOAbwNPlw1& zNX}L2c%_x=rEGh0Hfq|Xo$KYz`NP&0(CeMjmjQ=1O?c{0rMwb56_5F(Z;RhEQUL;i zG3X`1L@x<~d=+O60)BRf+0!X+>{`W> z;ISW{Uj_8TFR5Aa#=QI4^yM%39x!8Dr4dC#c9g54|>?|~Hw1C%dI|UB>M1j5* zlpGPFU+<~8)&c`FC|_XM6n`=86hNR)Kp9WK^@B5dknxe=LIZ;dkTC5zu$?(H7WWL= z2l@~~1JjV8S*496(d$hsar)mhJcE#Hkzly%qha0}KGDHQYe=sYn7|UP0%!C81PG6X z36F_{hMRk#?T7^9BNcPt%N&Ki7)m+7q|)&0DZ_%WyhPu1+s6mZ&==TXa6>3R0RS1tiFM1%cqUbC#J|Mt##z3bKQ!XCY5^)ap zLQ@FvcSAVvDBBLx{x1$T)Jc(508yaYY_UP2t`v)7alw8OFF)kxmXZE$E&W1Xwq5B- zS&E+rakPi=lE$FE8a?=&o??x__I|D%M`{{4bnrkQ2nPqo4fdmVKA-rz^aGkugg0od zE$Tkz1044v^}YiAxk62;aF&M$*ZJM0p0 zOoktfjsIMt`K01bjps&CTq0Zwg8m{KC<`^3HIgf3NAgLchAQ(IO7z1I66_bAP4%Y# z>Cy$}qKDFtA!*M0(RiZnlsqZ_U^s$#Z5v7y%7cL<1(ii7<-(V==ZJ@bkQCe`max!Z zp@GARATT!!uZ5VG9;z!qkg8pc+pi^AGZg<7N1615ML=ZySAMEId!f>X4EjFA{Q6#^}rz z^k*hru!a{5sjvF8bj_Q0N3+)^48x0$M!R5?;K!yt(M4(a22xFQzht#pI#@XYOHL8e z8>u@N0c)|YHq#dj)RVTY@n#tNe_ARvZ#T`FzXqGQM!Z1R>FN(Mq8}5d>N^|KODrdR zAxnC74yGoqfWO%BKAU(i-ecX->NxGwXr}6U-CAB4sXv0wUk1)j$N6V2X;L-gh4*pT ziT<37r?jmS{gssq`nR)l;N5Mr>|xU9K;A95;E-tfm@3SHwAx1J$dR&Hw_NlYW9{ph z!yi2r$rU`ga;Us5RgOSF;|^Cu=vg6yq)nU6B{Ss;&W8VlyI&TA;Y&%cUg7ZAbujsr zoo2HgUV~hi#%S6ut!pCwlv(g3c@rAkJA4$)U+KI#n3qP7FzN7~g`Kj#zr4}i#|Zzn zzRA3TG{!_>Y2!jR9Kd;OhF=itQIuxc?R?fVtP!L=*L^goonCSTaLj6BTnngTjeoq!HsVOl%3nUovGtlg`LmFB!b8H4} z&Fo?`TG4=`czIh`8cx`@Y%vcU1=k7+8*S1%3|d6oq=gFeyK#mGp6aVe|C`5jSe{cG6m|= z1j1=BJ26h*tntZ>0A}ItMgTX%loMz8^0rNT zn!1eVV7EYx&rqY|^EHB4fx2CeS*qeOU1XK^C2sDUiSpEMW;QiPuf&X4<9JuPBUH@1u6zYl@lyh~K$tL|I(wzAY-qok234i@WLA|vWk0;mF zbxgXj#A6uJ@f zFy#WR(jLP0PcwSlv+{e1;haeXk6vbrN$rr&tH$=F@s_%bGFF-_p7PnbKH5~5KQSH7 z31O;yoQ}!kdbZ9k0an+r^t^MzeKp`|-EqHWX50lKX-hM1D1|fX>SRS7Pyow6xA4~A ztfsT!eOMoItY+re@0+8Oxrer$Sdsk+KK^ZEb+8Qt_hiJ#IxZmB`J39)T>b{6d!JwO z_Tjo7dCdU6u9BzhT{B-dl3uz1K3px>+z?-SQHns8Ne%S-=v&4+!V zkz{)XfsfP#_wn5|74s3vmv{fG8<@|&a-O~7z8e-G(IdIGoJ2Aw}0_l?%q zT-E59DbGz3dA%*`s`HuE#I}s%p6RZme+BB-3fuMPmiU(`ap-3Em$!DbEjM2f&zd6d zj%^WKQEWy>n4Bg(eV}IqThoG$aH&Bs;@!!j1_;B zNmcH1q(iqpzN)=G=NiU6(OsLC!rCKuIff=@gON>$uP6^`#q?`+bx$Mph-MD|#H2;U zhaRi>m}9Hn8u}PqWhH0)F%=RVMF9kzLFPX7jBDVbD$-;-uHR@fZ9USd56tMG5Uo!3YtrnC!S4;wSJzb{JJpQpUuL~fh?*`hyim*c zmNU6C-gLAsya(rYm+03{47+~+>48kNq#M1Mc}@QcT7L_0M{8b>xM?8L*($)F{@T6r z*Y)-uxnRoS_Fq+hyJ1Jz*YcVUUwM_c{z|B+yIZa&hOaXMOn)u9FacED<})ZqDutUv zgAQ;!mBzYz9J3;@O4e(6r8_z+`nc3O<_fX1tdH|T*S*6vEvAKi&BfOThaXzA{%zwl zl>Hl?*@>u8u^az1S}*Exj@;SXu42$-m>x3wDQmp&LmX`(SxMFkVfr?24snFExVx=y zu*Zr)KV#_18g|2&-9SbQwMD-|$%NfO%~@$Aduy~ump;QDW@nNw$HKZz$5u^;D2AoP zccD#X;w8LnxBBq?a*m`YHHgG>OX4NGZKcz8gkfRpzL_y`onO7F&b9Z7H~ewijIbBz z+nWUuwsm6H(1KUyJKUh-`TLRd1N{W!x22=&G7mca0f$wm7eG(HRwkP#V-pWFnViGg zVVwu&=|huwIRL7z zV{Pj`^G^DS$20Yz1l0-zPcEU-l`Gw%YhjKBkQL2Ww|#c1{K)whXL^m>N%qledB=61 z@E|Ad_yYM3_PXRzQsDj$w;hCejr9IYYmoa++??@y^ZdLLUv^AM(z`QXxZ2H_7o7DW z(Orx=^H-3339T1dj_Aeu0$d z@hAtf;~~%FcUpsDCh?8|i=)N?Hb1&_KE zO{QwUiF|#q*FW0Y?JbUm?X6a`t`7Sh57&e7Z}G>c9=Q<#tVES)^w{t$y*eKZRq3XZPg-yc+VA@u*J!htpv^?HHSP3&32IzAPx>wH$86}|~S5eppd-QF?~*SGIg_n@G1hxIf5p<{SNqsQ_+Dc5>7 zI;P<}v_fzsm&A9#L;t{53ux&T@X$R>4)qb>q5(lPD<#EfZx(L?uS4V4BC3$1#i6NmNPDDpEPf9pWo;DX}Z* zCx){`>QGRL(M9Xfl#9|u>ClynS4Xm-vJ$I{r~lK6%OGZta3p>b=L&0|o1eSQ_kXw| z!_@}b?85=7WOdBDn!=&0TG(z%AC}2Hv}~>O_4^-StA<40mauj@+M)&bo^Sk_I`HU2UZzZ@YhpnddVc|Hb)@QwQ{@bjs8nc4d zW$_=|_>Mf+$frTdc>y`|opNH(_H6Z!d|2ykyOage2^;i2-FH@TJFzGj6tJU(?LkV6}G zQ95WSMPzKS6vai55<8SvYGn1&Sf$4A{@*HwYCi?G0&DIc2se!!mh0KioY1>1-`?7= zv{Mvj*f4hzhpnJ46uSmUsm>@ZWfBW;1ZxC@OOWGhlt=h766fOndx}Tm#o+dWV?u#d zr=OL@2$=OE<4*c8SjJ<$o9DfoQW9m8RLY2I!CC(I<&{+XOMXK*ND-D`5gEjtP+?x- zcUb9tS|BNwoI2GZ8D(8Igi_swJQvx} zbyfn46%dP_@Mj1ES44v+nn-B}BXVz2pk8d~shX2eidnLWE z@koFP?n-*l$}hq_WP$g2f%hDgPlQeSGrOL`fe(jXZ&?fxnERU3*`9jgFDZd9CobVX zVF=|^Orm7ER^niTj6W1GA|aAc)G$?J;SWGn8xBAnme3whma!h}oAUmKU3=N{{b6AH zIk@VF{#Ny1a-|KJ*m_z@X#-Z!yY8sy|Fh4B&I0mYJ^TupGeRMC59~5@%4Xlh6D-?? z-~L;E5_O|joWD)I?Mpe3ap*0PhOJnvKnsvfwAio@#$B}!ZX{4gA$uEJT%|w6%1?K3 z%G1Ku^&#DxxjRub_wDA-iT`eN2X^}&{Aqh=yr>zONc#DskmeyJ{x;=hg5o;mZKABU zr(a(X)BaG-8`KQk;zr@K~=*IxXOW0u|Rq*|(*O_ze?oCJgt5KZb|0DLAn+i9-~km?@+R4w9Pj zmC%b!FcahT6nU96&@Z?3JcrbyZQr*$G& z+fdaE0bg4>L62Hus}$ZYZ;=+~wVFjaFAuvGCAP_la))mP*HBscXukJP-lD?Z$Ht7) zsfh5A5eZv%j9)#|@*W;gl$2bA|L_>oqsVKykcGX4eSxrWSK@+myg+%cCrwJv% z+6w}uY|SZxl-EFuoQrVnx7W%g6rC&c5&(fT8t3qvHMZc8V)L@jfu=v@h+1Xh)i0Q* z6-+9Xf}Ge(T1finHz%z7PBL(o^j7zUPRd8VJEkJx=+9vmammjQ5>AZxg+ub#%wPNi zOEX7UD$ocA)P*z24QDdfk({w#Vm^V1w%@P!F82vDmUAfocV^}mYjiTnajswgh^NuL zJ5zq?JB96cJ|67w>o%a^=ZaDrIw^g^M66|%PQ?837-H-W1-p<>$0lMLuLJVcuwEOM z^#(bzV#pDr6Pue%m|H%TNR#S6sUjmPS&SksDqW0{_VOSqS=K%WDn)QrP1QW=MVxY~ zCG{m0)N{j?G+n>Xy{2(YsR5nmJ&T4rJvfoM=LJWI?+!Fnwt#0nEQ3%!FX3gHSTVnP|=OjgtQ}CSHHa2g zB#apGr^hwdxd(|`V0EnwJf(padXo(NuT)GS2HGG4EtnPPjk5p)@mlbv3j~*Z{93wl zLrtuGGKNQAThTDO@LHGxgo)l#Z0uAaY!NUn@_;A{k^DG{eXjU02FidN_IP~BVy-x$ zIP}6oF{LuW-?Z^!X5w(-aLNM`aT1D!W+F_bF29-MC6`Esh=)+<2`Qtsq(r24Eyg4y z3;i~JA=!i`e*;8|FpNzo$|lmURstbA?x0;4n7&JtfdAJat~had3TD>y?>0^8^HfZ~AJLq|8&NR_9jY#QLWCSgy8`m4&{+fTV@9QV{Cv@5eY@{2Q{AghW z4Sb=aaW@_f{BIl0pF*_)K~v6-RC%^bElTEFLM^#MuWa6UN%OSM(o`kdXKE^HJJq)2 zdB9m$;%&8-U@z`1BqrChj-QS--B>qoPM%aXz?CQAW6+PEf4EMOT3=(YBuM*chy*>% zws6jNQ(!vIzn9d{u2giMW@D6bwv?X&{@8Be#mk?PD;n#6uqZ*Dnkh1IP*~vPhyKJb z&k3Al;KjEl%oESe#JZ0Ni&-T3#V-{j^iKNmV;sLq{NNm$H-ze}&Vxp^ZZe4~ur0cz z{8jaXO1Dyf!Iqd$P~LA+gcntPXW5p-OT0&V>E82|SI1l5*RMkPUfe0KoP`&W za<>Df&lT0Dx+fRzRhk!#so`E-MR8`i;nz#kCvKBhiLc1G{3})>EL-I53E%|=>oho4 zv(R^BX~=_dTr)p~xLbz4VBKJhT47zPE1pWTT86YQ$y4#B*7X@82{8x3KBYI~O{u9? zKg<&Y2?koB>^kilrw{=tRAI^PFGnI>vllMq?t;qHt+`Z#S9 z<3S|;r>ECR54qj{VB~wDG=JJR2KfH;Jnbug`ak&pwD`N71MV+g$^Y}~?7cs+*nfH| zWqoB=e2XvV7q9F$T4sJ_%P>4ZTpz~F`A4L;fuDsaC0o{a)9xqPz=fk}qN&L0s}H`cG-TvcQ+kTq6TvuJk_^EJ zU&M1;X4`>Rl{kLnfA6|VpjuwY?x-ry_Papl9rC0}*kke9#PaJFh2Wkbs!ll7=ZV~Y z_%JZl)_uN@Dv*zlALl@N|4$zbRSsEfC8PdXC>iW^KUiVp|LEeWzF5>JLD%Ny^b=ON|e@6+26#W;TdfA5lyB^UC7zRI+p*xUot0&g>dzWgC&qA|5S z2EMTW-qkN^{LBLs35(m0>ftZ=g(qy+cEA>_TAXCq#*Mz%J7ApCZ4;+HsXg(|S&k?| zKVrL}oztD~DLTe|MCKW9D3tpsG)fmX3#@{r@&dSI`Ns$E3uuP8hPeKQLqFuiwD+Jm z`=XwIiVcy8;x;Njx1ye#`x^wh~hl^dkw+=!!r03FkL-omosf;0kl8`x#&4^4HoXcO!35?!|Z=vE8 zTB;A(OMv4Zgt1)T4|;bNd@vU}O!$E)@SI-@|xwutUpjJ0O*U$$ORrgsd&dBg33NwZ(OC4<=N7Tj4AdVt-7;v7w_Om(W!@AzJQe7DrQ?f;RY0@2-NRwn9noQ0E6zoAy^6R-&p7jOB;y z0;D-X*1jPBi~O-Tp3&yJJKay{)BgdnT%y&6t$ItQGDcb&&t4!^y>BW&nvy5wgZjTa zr%L0g6-av`sa`m*Qa0%gzl+UKP2TZcBeVlB%VVS!h*I+Td;+zP)CBXCOmsrV-Iys3 zLUZLs#l|6d@L3~Iy(dR^30QP_V2(G>p={?AWCs643h?f7r#|7a?4 zGph2S(*Hf-CY3nZL;qhYobup4qi7}Qe}1Ckc6xr9;1@#xBR>t{-N3hH*-qal74B|e zpYeZ=o9~$ZcLt2(&>`dh*}H>Y3~P*hR>dZfJrVB)&KdbHoF|bjd*5qSCXtm5eO4<{ ziPU0V3=yA>LdzKVX)wM=-8E#3SF)p#kHwnHQMr}Bl@DMa-E$NG@K5o}N7Ffvp{)*^Kn{n$KL$iO=Z@($lj#$WC-TRsdla_t2?})Z8UHe=Q-t91ce& zVj&oT90pfr%Isbz0unin&a5zUVQ)He-~gqdZ3FCw4C!+k`JS#r-%KSqzcPf*y8z|2 z=`{mjcAyd*`HqXhnI16PRVn;*3)h-b{M{Hx&jkKC7SoBQs;+8w9(6--+*r1b%z#l1 zqIpouuc}VXK)ez>)pX9fm!=&tRrKkn=^SsErV}1Rgbg?s5u`^3ea%KAU4oaP?qxfD z!mabGGvR!Yq_dP0x0D@+d|*T_;j#HWgM1lx-vCeXm0E^CnexspHdk^eEsq=QW{Z zX-5GVPy`I%cmMG|#%^f4n8V}$`Fmf6P~0rO<}>=0yBAot1718`2$LmQ@M_za#sfZm z_+1%N!zTnco5mA3eW>X~Cb}#0NvIWF(Id}S!k5PfYWXSf0sgn-^YHFmc~|~+sbs0d z@J!Q=4DwX+-)sU)Ien=woOH<|R$dlYg4q&LDZd|U89AlWmykE)`WKd4yjfqu`;SL9 z=;_}CS(5%9dc4R$=?}?YuL(01z6DTGp=W;Xsp9Ds-DTa7v@Dbi%3Y;;0bEn?lf#|8 zGL!I=1OEdr^gD@#rLXEwSA%qd)RIpLL^u>Qhz5bwK(ImlK5@nj7J>x`qCTs6r%Ck5 zVVORjNwO(jq82{Fb@Oh6$JZzTyAZrA&SYO=pZH2irF?J^izNec15^W}B?I&~ESpu& z1QoH^GvJ{?Gc(#VSaz9rh4X~SUBKEIfjSw@5-r>6_F&+zv)Sp(=e~JhdaIK>SKA7B zue>rU`CS3l9y(TlAzZR_lf#Go;tXvJ$O-U{-+-3@pA@v_#65+)uU@q(=OY@{44Dgw z4MHpc*1DpH1K{W!_d_w@HbAe1uZ6B9vV*aMu)}8nO@+t=mjN{eY4GFhf2IE!<^tOH zS^}Dq=Yv)Yp#i!{QkVsK?Z+YT<0nQeDrd;!#n&M#eSOViKgB5Q{2Ij z^`rQ7T^Hyq!r!Pyaed7%RS08VI1bPUOG|6iO%NI}Knm!@-0Kz$*l#$bT&Uk*N+4%( z&fuD@eC8{lk#T@U8_ka6IA=$D-uWvKHxM5I4iBV(xF>jYkr`)b1B6=k_ICj%cYAb` zS*RRiZr&VaKW595ADky>e&5XR&M(4G+K<}Lz4zf1Q1zzAulL2aD|i1O<E2I82R#A;wE83Q4y{*H|P=)w_@&`#1v9pUD)vb{n z(oJ2S>pDA|X7_`)4Sd0gTEF5^LEc|}#bs-g!LIExxy^mI{82)l(P2&N!%hCESG9f7 z%&NoMhM=`L>$D7~6|+qIC0di+PMG_4y&VH)K z2VaYNUST@Xo9~h*4%WSP0Ht>x2aRdoF_Wj5P5?f!o|KJp-IaaG7elsufz!G%{TN9M z6xs%#Y*7atdANX1Ft;reO{N^IUxznjG zXIpcbCaecy)9c|lBfGntO=_S!16NyjvW=@ti`TBBSjE%~Eu1-eUJ`!r`Xo&z53m9eW4v#THK!w{a|qi+g9lv z+Jw^fr;5*%7JA#V3XIR73X-se4TPwP&A3aIu3+O;?(g|z$)S{N!Aqphf=_?B_JOim z7Et94r$VuM&WbT71;A>39N~t5`DaAyqjL#dJfB@ZK4YC;>%-D(3^zH0h3pQat;n-} zCI(-O5Q=Z51>CLN7QwC9mj2pm2Xwcs+rBN>hV}4F@06SCa7AP4u3qhcNk0W~i~UUw zg#IB*sQ4kNo4MYfjsVWG^H`f{#k&UBIhm$$SCzL1V;OL~QU7=UjgD9!EPB8Le>vf` z8l>cL3f$~o7kc`tgEYdaB9EZgHMe`JlS;a{vwNdA*xS`l`ZYJW89B;aj7DnBn(9fR z`gRcMa_ORRaJ;^3IYD3zeb|G^E|46tbu9sQ^Lz|++5Of(Dw|ldSR0XmL6fIQ_#k~N z-O^$7@LFZ`*A$<0KxdZ2Pie>5c$%1Wo@@()o)S62B3fZ_l1oKCE6D^`^Jq<`Bi`cL z68or7UhUlu@JnIxe6RU<5+M8Kb>lC<%DFKi+O=K`#3%)Mn0!879b~^lPI%wSuDBi%HBA*r(E@tt-Bof&SNHI_dy#-=XqK(Ib_iZ zlU?OWIgexuLHdeLv&zH?i#o0IZDQu`fFaJIG8PHp_tlf*Tym8Cho&=0%oBMHJw~ju+MpRSL zybW62Pz}bup4h8xRmZ27VS{rsbhaM*&fPY-a^+O}0BQI%1{P%GCG~eN{LG*+9PB z#G0JYZM9{dfyLQ6Y-YXTN53lOS7OcWPru;;uHSSC-fhZ#s=c&TOYlf-$Y0{^zV5Wa zxGOcGx$7|j$uTXuA-QWZzRFZ%T`%(n=j>`-!avoxh1|U4vYfKjw?_Aj)<~N?(H)P} zWWBB~1o-@89f7FTs5PO=Qv;*_*18?{w*xfONEpmwt#R{O)frv-oPVE*a!$P{i6)|3t7@bE!t%7V@hX?5sM0`Jh`L$INE~} zz7@7jbR2S73i6YsT=G4Q0ICf89`-M|uUsfa65{4*Y@w7viwas=-^Ys+;XRh~s8Uzv zHfntOp%WL{i!^t$G_8|bd}A-e$}=^W7-^u+W}Wm8Lmz)&L{GbM%%7Pjakyq-ekz63=5sYHC_WWy;DubpJ^!EEe}mHf@o|BR!7iscb& zma(J<8(S>CR%vx!AF4oH+qZ}(g4eg(Sc+?Z#dT6*9z)Y-*T=VLnZC(MnGH+;XOQR_rS>BQ5=z^~zyxVxXu@zLh}zAnCH) zqn%@M^6|!^ePQp=#W#?B$X_~ESMrK%d3%ZD(9XA!eaT%j({S<|UzA(_aQ$h<&Mc z&Dq@OFKAyNeIa%YT;0&0^Sbo-a^{@8vY!t;67&u{GAh_N z+HP8}toc81UqFM2@S74L+r4%@7JxQ=g6Jw2H0EGyEXQofL;fHcm+ctwF*VTgUGyRB zJ}6auAiuzZwrMO`r$^je%Bk1)cV%Bc+2hKr(}(7>?IATgqhGfTgu-jt@jqz$qYv4= zukb3~NFA-Q`qfGDD>lF9O5#y|ff_|(WyhgV^ws63wC_e7>|5KxXk5fYMfAIXP073> zIz<@8J)xLY`*LA43U1s(OAGNG&``BTqT#PEi%A@HPUJ>dCbQF` zClq!rTX8jJi@B@kaQf^?>>3<%jOScC?sAPeYZu*D?b&PR-6ti%p19<>+J52@Y}nr~ zH*+ircHcEJqly`~Fq2|q;lOgwa4iH%W?^M&_AO4EYdbR(+|@I)rxMJ8a3wT=9D`+= zaMjG)b2Ev%>N#RU-*MS;OaugHML0EI>bR)&S3(!4)rzoRR>CGbZ8zz`B?DZz0N!O# z`&MwpVkbv|)0q01{*D%9$#%Ghkb&!z^PF3hV^0X-axL^@vHOX8-ZfmpPM;3_*ncHl zqlG+^9aHGb3VPd44$}H#0h>gXOz0fQeRclHFu!sCWr@Ep++PGVg)p7mj7k7H{**e& z_4-(3CNRMFX5v{fENVwXW}NY0Sh2Ej&OkbcV4kSV{+;DA3&8Z)3P9S788NV%hWdb- zdX5k!UN zoAK*V=ij1XH+V>u0Ub>Af+9PI&FYm-`02mhIf?D@F>XQE%dt&J4-KpGQ-4R~?8IG$WIkHdg_PGy4R=}BBq>coxAU0HM z=~o#}FM)LKT7+m;ZZDl%4qN)bzqs6wZ#tcMk%o|_%&D7b*lT(rhIrD2cFqp9^Yn2C zboY?qQ>VTHgdYN$dSF+Vc8Fu(wtcFsPy#-n($Jb8BK9CO!~=>*KCbNQYa8@KiaOqe z_gD<|zaH(1?P`6|H)p#)b#Gnv?7p(?qD{@dd^9nmABf;i;K|=&f+B(zK1K$L7>wmc z-+~)H5&}1Z;6G0KG5VdpR9dTPRA7+AEVAx-=dPlZS zd)kTzu-;Pot@|Cm;1+?8J9s=~Kj`t6BQjHvGenx$>8vo&x+D!#Quk#MJ%^lZ#W=9- zbBncX+1#qb76j#gnY!QgZxGYTPX=R3(p+N(oCLJ-@fdOK(!$2TaBkmT%hj!FV{FqV zyIT&BDHG}{Gw)l+ZW$G|aCXw~H?)&?RS~_dg^i$F&Z;k`S1XU4ELC;AwXVQK>Pc2U zY4tLS@=Q~?O-k04`BEyFQay1Qe9`L3Kj)S{y!M&(VZab!B5vEMR9v8l0&6?<6Fa#N zHRmn~;EB*ofZNw&VMOS{+u(Z(`z}DYXPPC>J^207Cki(UyX8Ie!-;)5AZ#jYui$_e zD1NupT4*+xS5&w3vslm&@3yj?*jt~YDcVa%=ein9n7eTkUqOuLcsby$HMP98%49SN6*C3O zsE;$icTnnm>zy&rjuS))B< zBKjEG@uI)dcTFp!0;r`avdRRlZs!D%jwsOY4mDbLSF?RzXHU>XJ>JrdL2aVV1>#4C zlCH7SmE9$Q%;|V8!UK5VnC@EjO&`l{fo0|i7h~$0>M0j%>Vhhm_6@51is}^?bLx)j z5f{J4qAH-BLt}kux1B{}E=g)c{*YUDs+!uLluHXqjb!C4pxRwuNxcH_YG9l)?QCfm z(Y)%s!M~8G<72AW|wQA-rZ76!DETA=f;vU7gtM0|pL`b!CS8?B2HFei=--Pa6 zS9M>7R^1Aq;=Fwu?>@wJrhC}vV25xU0QBo#4loBPMTNTRlx5OBH=Pq)R>6`9UL z64>2$RL$K54GnaudL%@ub~$<=#G7QH@{~t9#xwSm4-I3?d$I~+CVSF@DT^}iTDUD` zTwukN>h!f8&fK2JLpSyTE-AFvl|E@vOlYiok|bJIp6ViCU{`pi2oDXnZ+GM|85d*( zQAKHQ>XZ(z9;=0(M|rps*N$cVkczBd%A%vk*1f7!NSFgm6CmIQUIi#b*k^Qb6tYIQ zP6$CA$hn$Guw1#U1pPkXbM+pT<==_5;wg0w6&fD6DxP&QPRASeI$&&JW5Ip7h$P<% znWZ~0Z#gAm%yyQ};~j>#VZUzFM!ICz3z0>}scCP4PH1GcvC|l~ywdIcf0+8l=t_dN z+t@ZHwr!kfq6sIqZTrNw?TIFy*w(~$a^hrSJGpt^@7{I4AJwR;?p3RLcRi(NZ=MYw zF{zm7i}%94VY5dvP)AouVWj=8Fh<7d;l_wrjm~)A+GM{Nx?i|I z9v}y%oif~Ud5rr}iOXyjcHa~(T%7xV^6t2U7hN_d;LZ?y9WyDzEcV zG&og)S7Q-BP%S}Hn>A1lv!>YQeSUD9ukFfEapET0RHBv9?X zbkMvAile+}y%NIzAU00R@TUrShHMbiJY>ElQ)VZrN7~WE9#4c_ajVLzGQnIyHWhj$ z&6e9;RdvT)?KS@spB!t8@`~k^@Q(A!bdyjdc}4=ylROyVjoVP4p(jFt@u}{;53GW+p%xS?>In` zN?)mGls%2^$~S6EC7{kTG3HNVWn#1LQo+JEaE_|C#2cxJ@*A4J{-#@fM{FMS7AYjG zm-I&|w-Y?6%c-CJXUZQ6&jRN8H>iL8O}fP|i%d|;xqoxBf6CtnTBq_2Rb}8N=Fj_vAkVaS+qN^$ zD!4ZQhY$puW@<3957jYi8A`~wKNDb!WJCS49p^=R==9K)ah7qkQq0CO9C2nEBV-Qi z!*EE*wyjidvK6~ptVwdanL!a1d-wU9o;d3Hl8px2iVc$up#E$AH4tl+4G^EHhBc%c z*;Ydv`JA5NuhKbTaXW$~|8_~@DR+I^in=GPI(Kv+@dsH`e(q#`I8~|`1nxztv#_{< z9;?P>(5|aSsx1+IT#oE|G7`=JWBDTs@Yy7r!2{S zgE^#&SFsM$`9bck6Z z=Av;?Mvyda!=SE_G9y~_5PSX4D)iGK>iX{sQ83C_RI^Nfjioo3X#3*$IvGqO~mCGla~0_-u*8{LHgGGDaqRCSgHunXrS$<)Zmo z+X2gz&{09ZM3s|lZzz=$1!>v#ZDKgrQ1H5!aIXJv#2`@m$IJZ{~=3Z_FSO zCrM`}n1(PCT^6Gr6IR&iq|buM&r|A|R3`NLnCMSrC*lG6jX}Y$&Hay_z%8IAarcVgr{dK#1Lln7%U0G}lJweD_; z7?Wo};Xl+liIiN+T0BAfOfS5-3PW)sQ)EP)0YBF##}1(OKKynYKiK<*d8;@$`j(PO zzPaKLjR)-a392hnD5txedgajL628BZ=wOn$kODWxajMWmSg*NLZCsU?+ zz$JWDuXrS8Qiv*<_$bazh*+TnE$;6S?LtvY9Bt@aLoCK1@hdnW86y&+KnR;rts~gq zR!3D{vK)*lxTDbMeyW`)Ru)}cd-#@6f&SmE@~Tnw#z7g3rIDG&aTzQ)ktN2^Dc1E0 zwpcA9R+#riGL2EpvkWkWF%beon|FYS->$#yGoX41mcyPASU&wvw`)ZsNA&Xox_luY zZemx)lk3s}5nY1#K3)h9H>zg`*>&k%07@TEpUiQix{FUzG>O*vO^ZOmP(~P_H!n@hbyJIrghgoZnLcB$+z%U+w79Me|oR9avF9n z`S8oOh^2(h+5SP_*D*pDO-b08*1r}|s??W7=k?Zw5CWwcgOWWFD#zV2x*s%i_JY*s z;H~Ktq*IbU@YHL+X6DFCKBzQqESkebz(~?ft=2S25{ZKD_-H z#c0x}qR1mI4AT01NCMUeBbvtwN9g(76@g?4kxjw)2$;_~pC-U?8h7OUdq1-kQv72) zDREP}v0r@SBa5h@Q7xL{Y9*j4{(UY`aVLTE!+-Ua__+MH&7}Z`M_2?adFfkZ;4l_j zSO8jrJtP?ibQq#O0$J>-UQ&%l7u;2Znt5Ep{2WbUFw|bRO(rrZ*QJ;Ty`IwH9QI*ZL|(| zMC4a9Gz;}~SxWWo?4Go8<4pgn0T@VkME%aMrTg6#{eZhDRsz?C(o-5|jMo6+8K3Lh2}5Jh$79DQ@@?zUfztHNpYVGPNAM zu!-D1QG+llsm@-hGn^aUF7_gN$i zX9VY1rIT!?))RAiS;YBTy(T$uVb?COaW}UU21*j^@^CGVO{Eid80#{6@u;_T7cx+0 z=w9$bMBy6!;d`&TZ;lPkI+Q$%Fj0n@FE?vTD^&qj3-sHN24vwbVW6d^@uxAeu|X0l zWVBW8!cs#oyS6_k0QT?b)bF}TJJ8meV{LDkqk+B$|MFTZ-@nGOU)6N=O#!ciHYSED zo?tJ{T!OsZ(=$hFiZ1bPnM;B(b~>JL;}8N?$Rsoo%Qg>}M5dUh?6n%2@h3v{O&PVM zQ6w?d;{?$j=+N%dEJnLr+|4z^v~>0kE+Bqe*EHIaBWztxcY}# zZ@lt+gMpCN12_Bpf~lc?Qd!oWlou3Pi#Hg`kyxg7S zyu!M1N8ME)mhT7(OaD9>N76@5Ed7QxI~Mk)t{sWuW^ubt5&v1SYIN{NxnE`QSJ>pn z)TZi^m~gRoQztQ>)uC)tkU&{rt&0g1!-{nj-^+Ej>^u*5n;YE0nW{DfjgTMC1Rh_n zd{C*92oW(NUrG@b`$-*3-!VR5sm=$j58wt-?PRUwk-7@51!WDN0xk(#mvZBpuL+3w z3A+faBe&o#P`8nqm=eS^a5KbsaPG2Ln2rUu8x4Ek^bui96iXL>2#))3*lmXhDcZ*O zH**sDIsmt!#as2Ad-xyS>-|<1*SYYp)(0$oP@9Kd>z^TUe%%5sK0weECez~i!@>T^ zJqa|N&ClXEF`+S!v21e>kseCRT?NgL9l@ME?wiYQ7?)o%nQjKS>&0#jJlXlo$3Gs; zJ0GLA{jc*FnlGc)O`Hs_8BZ;R+ZbACKZ6#M0k<>8s!v-Jhz+9d7j|348&}8o3GPUyghS^BevHPN2w=wvh z)c7GO*HLev6nUD85j$`4X7!}6Uy z=sZzQ-^X}x?|=j6CVu!^C;k}yf)sTx_hNj1h&16~)3#Z{M3sNY6xk;p=+`_Lp+~W+3kDiZLQyZox^j zKx2(~AFY5&C1v3@jC$VZ^@%PUJB3{GJ#{9coW!~MFl<;tywGWu_Avg2l9R5THw9A< z=g;?XeiJTtl!$8O!SGTkjd}%3byucw%C27=EIjEy<^Z2TH>h{GDe5OT=RJ_L=RX6p zewCJsFCuZNO#Y;qNLaL8EK;DzshCn;`>vvrvEaK{xq&5*{M*Pav0Xy1rbczS{B#k) zEn2(eBBNfmTHVItOyzW8z`EFaX^lWB*;`hALA$|Q-%gFCa(NM@0c3`jnN$@98p^se8qKl`b3ZwR9lF; zV{^=N#pMe3l@e217!R_sB>1|Fsx3TuBH%|d5a*yhBKU>=lcGua>w(DH!s2VLJ11Xc zA_hPD_wO&Iu8C{BzL&P@~#-&kwC()+hW2hLPoQ_>|>QD>a1XgB9$w7 zPTXyY+bj8nAcrD#U(BWxV7ZU7^Ksh0G+D*3e6GHj@66qi!ojtL9CY*k3__Lb#p@K4 z!#uN>JK4vNU$4&V6#J;yA7nv39Pc;~N)q$(Q*s_>x-p<+IdBko{z=1>B5ObLJ6iIL z|APOV|J2&4Nx9=+yJ#E_T~|u?UobP)EFC(fsFYAy_@wvYn1S!3al~e*|&jx#Sd`io3j_ne$-Zz93H= zqiqW2s(9mZyueLbO3TiFx00N{PW8#Krlz!&Wmay}xkT+@_t#mYW}GbR&m7kPm$;UA60^Kkt!k^eipx(I z7nNp^Hi$lotK@If)kW!9Kxk+UMs;dbscMIMt2%8{$bkn>$yC!+Q+#^NUle!WneYY*_tm`P1s6@@2lQOxgE7kdTE?fQ-{LOy~o_0LwS`6SD|p4 znT6(#>JAid7sDOHiG~`)qGyzL<~HVMdieEA`)(M5?a8S_rMp}v(MEegH%%+m30Y$c zo1aND3Y!lSRdkcGQS6*ctb0ePG0fGe$A6L{)4rd#Q(r2X^~2{no;v`X=PGmW&MVdNvhqiw2}qpd~s35IqE5O<}#Isn8yM>vD?CKDOuS}}Z zRPcQ>`5h}%sBrY8WP#3uTRf?Ry%NpXN@UeV_<=K(Y8h_clKrr7eE>~C)3 zeouYPwe^Bp1v52E_M+KB54#)o&>t1OAJ^SVn+3;<@>t^s&u0JBsiL(7u@G`gtDKEkwpg-zI+*t_jP*YplV+NFtz7RvSx zg?d`8i&)ttpN5XPF1^gXt?#!#8cJ%Mms=k@P?L_>Q*8gu^OwwSf`ld4Xex4***Cc& zM2M*lqwdR<2kX)|jv|<8S5pQKF5HvCH+h7-AMq7~!ne+4?kK%}3W^Ki@7wgyB=2n| zA7p~Y9yA5#d56auGF+zRxMGW##yLjxKx1Wx_fVv) z01HdORV6|pw@AshT{xxKry1M3+DG|^YZv(^{N=|o zwP7zVV}S5hy*$1T-({d%4$Zv4)a5>Ef9XsM;f!a@?X*s$9|h-?-DI)uon0bjzeq>dT5qGp263^lg~p zO{Ok`Z&&%+U5T!<(gsq21v{6@OY}pl!3!S6&5~$PBOGhB1$U*&QuWiST=_|@qpEBV z=Pj8dBkR~H$=GI3Qvn~y5=1qJ$6?*PB`05Vs8D(<FNn z+L(qI^fElmhfX2KD4AZmL*g9Wi=nX++=ou{Gq1~mycX0c#>c(Jn}A=Z#dq+=a!;2i zxh9mk^ODO>uDQ(H`5lXyw`!xtg{Ry_xdtK~&{~IZe>WeoPr#J@cw8kCsN|OS3}P97 z9D8dQHxM+z{S~07NxPT89&AC^>&j+SbM3l5Fs-2eP1TVkNnNDxfib)kdh_C52<{Jy zOieI{T;gGpZe@x~@VYoE3Y;cXWpHYwRAc^bj(UO2g_WQM!;;W5Kplx1%T znC-JKFGM7IwKnBbTuxTlmuiuCWUQ7*=jw7XNMuIS`xmBQ%`I@e_OUohKYxE{_vhF_ zrA&e3d@Y_f^MYyvs3EAO()5_!lT&3SL2==`m9!F?)J_I;N77R{=2z%Y_}2|EkVq?( zz~5A&R#xZX+)?;*IJkKEJuubhi?&R>iH}7ht&W`|Ga5`Dy*J zZ&9x>yj0iV1f&+=mRSM$aBH*Jb~OUsa?6-q7TQV&4=d!VVw<~*9GbzMrnk{d`g%O9 zZAjkNxiypRqKh{-m6qL}rFmQh?fqhPOav;J;@Ycfb59TaEpoq|b-FOgd2H!J?k#nE z4K7WytMsfk|L`?_D}FI5<{Fcf;FDVuH5qUJVmg=)zZGNR@Lo#sGhm>`O|JnV*^P1lH$Ovoo#z6(PP(0 zz3Pd~U%W_33|TGOe7@#lpdQ@5bbaA!>~~R0?6LKuRo+1Jw7V*=bVJ5taqLMu6JLX3 z?;n|~3TH0k4rI-&3LUVt6mho;d79_asx)rF6pP`(cDF6g>NUNhk>^j7ja$s2EB%Oi zMY)ChgV5`bbxgU*MQi-p&(lW!k!vZNJJmltsb{MdJt}nerAb{CSQaX))I%!^7}dbx ze+TY%4mj&P*qb%QUz+zKBtO1)N%XWY?J#q-x}aiK4hSkV4?WVBmZpse^@tHpYwoa| zwOQJ#EL;7#c1l@CcH2bc?;xA3)q8ZyRmG6{I@JrU`CB+Nk9!?`*!0{!bTa_s4;J#O zBX4DvH;UdGxOgxBGOV*%91)KXd-+K&6is=%DGWB92jM8P@tro>T#sn{W^iY^JWDZg zZzy>3ZJ>!FFjB<0wjx=Z6b>8BD^xBeT@Y=~FVUmfm=c|W7pQi7uyT5q^8OM++&*iR zT)&O%G(L|+|EHXKg&Ds}Oo?FAZ1wHo`x-BopFr-(*?6QnMzvEB&gwGeEdEq?Xt`{a zzg&58BTd~U>2I9-6@7-?lw~m=qFJLN$w>owiLybyKA`^7*cScWd87MEEv8$95b5%# zrk(o?0qB@6;@l{=aK-%&9q2JbypYJaJCR8LHhOz3J%159V;h6sv?1yv0eg;0r0Zh| zI4tnX2!2pQSySZ0+A#<>s5IdON=bJ}ei!7mWZ5qeN(f$p8~MF{J2#K$KoKz$CkF+H04TgwGNcw1SIUS??lZ8%w_BBy!CAFEr-UCT7d6Yy0!aKlVEQ zu3AnZ9remU_5OaYma0MuVOFUKsYtGfu?XI2*_Iq}ma`~R!X@G+vQt8|h;^2{h)UwW z)k3DNs4Cj{RVBql5{nW|5^i6NfCQ0Q5en#Bn7PYat1r;Y;}XkU#_uRHvI(Jrg*3_} z)ehBbsly2~U#$uo85&X4 zZ{KfRWF}!IQ5ms>VMn?q(U@wP?Y@cc5qok;y;i2jV>Nvq-Qgclo_7p4>r^x^Vc}q~ z3V>&lu=5|`I*hLDkN0OWLfN&-B5jU;wqA18X`ey9?#YeUGnpPa+cF{lS2D>nc6s9S z>OBos)HhdK-KHM?#j)DFXyq1+Q1yK&bP26-@pn^KPM7v14HoFqLSi7$3{^lWdvvtwWn&!o|f41RvvCY)$bUF>^oz;u(tL~di zM(O85=YD7JXJZelK3RSteldPIen~yx`&JV0{RNOxVRYC(TML?U*TE@5pt65PwQ?XBi6#;evVzj4ra#aCH7%)nsf<XL==hWr< zx3?po*>JN204k94X%;jRv1Q!~$4kO*dVBjxg-T(&B*}^7(G#w3^y>x_FCA6rk==n8 zUKreiO7NbV5?s(GbYJ)i^ZE=zvjbHq6OL2Ng3)y&grYAVDxWSscmoy4$S8vHEw&@G z^;P~^Msn}=c#PMQ9kAwz&)<*AU{sB>o7sj|^jZ*f+&dRr?Bs zL*LgE+M!b5kN9!|nua_LxD@#;(v{BQ-s?g4&)rjZVDFalg&lW$9`^2UVE-N@9O?Ee zdblLybEsUPRt63^vo0A*Zn%Nok*lu97ttf1;sa9h-Ri2Tm!dcQfKO1WG`iQ?5W5a( zWq8E|tji`QL)5a{baz{63>JXCqBB5mh@X&ujyeh1+5wrAoRA{&M`l9cHe|8)E1?c~ z^u=pNH>Qj-a9D$vzPBeP&jH#1a^ttm?*Ox2ZbR-^vz~e+<$bfkbw#jR(CQ+AI%H*l znMiXT!PXPsDc%yKf1I!ZIQM`8$D@|V?23pdw&&~<0V`AvtOO;V&X}10#Il3GCS+GLhwmv)gxJPApL{f|H<6J|GRm8hwGF&i_+HT?KN@8ViR4(?FI z^T(V2ZmCBX3=;Se_%>`a#Ok4ypbx@f?A7;Cz;~v0 z1R!!PX*-~}^d9Fvfy+%Ombf2QX;L=ueJA#OW=w?H7w*H#utXiw%5S!>yBoIngm$|7 zr0fit!n)$jG(W?g!{M*t)=bb!jYN(qxi{g}g8iNXP<<;-|5~r7{D`_HX8@0mCp$q! zew1P=F1)XHcoSe_!YJv#;rXC3^NIZygJ5E7^vU|O+8pbaYeV9+SQz1b3xq1tBT-4L zRt{;_$xjNqnb3pON%F+Hs2X*^#Uq87)S{MqT9QoE6cC(jBns<2$orL`Hmn_BC@&}G00@7xd-6ql!iqUyyiB>9 zH*Mag&4$W`u4a0dDmkcW($r%-{nwD6nESJTW`B&e5lSn-woar-<0%L;q z&IwyPz=Z%&9_OJ=l*AQpQV(J1!ilv;z~ats!k2okf$)j(FXpR0&vn))n{w>sgh-iV zn%`aBX+D;C!S&n4_h~*!2*To}U6mJTlJ7d1?!oOc$LmId(U!~c$%woo*9%Bnkf#=S zAF{3Lz$iw=Ucrkb>^Q~u%0ZsKwK9S~P0L0{PAd~BX8nqIbpK#vIvFTX@w|Ic9Y7W2 zhJ3~a-_0-W!b3ShEQTZC!a?;tFaX72ym!wp=T57Fcp=FSM&cp%ttJeAR4M4C0{Y5;?0iZY2dtsdm zmM5G$O5YUO$}{HO=8Q*!1WAyoASFt@jhVjnQ63r)ZUgaaFY?kQlY6u0xPIV@)IpyD zF`&{P=8YrBLLkJ4Oc5F-h!X!g_#MU;2w|fUnA+PCux_dkUebBRp{N%Kon~5?zsy-BW$r{$ zN=PE!d~?Q_>ebR_AV74bvy~oCVd2DYC@*uiKW*dyKr0K-1zj51k)E|c#zVI3tZMas z6YL(9n_?+90YW9``z|%`=$_ z2Gaa5m>2OK09+qZ9Rk&u#=wd{zNKy-XBu&m<@ShcP&as+i9DPN3m#{p0GdPL$g*PL zN{U~DKjx7=>v-ek88#;}-{0_;7I$Yz0b2(Ncrgp!mY1_g7-g$iBZM2P;u-bT12-adFgiA zSUU&0xpKe((7aj73OjsBD(Hk}GybUP_vpn=h^~?p^huiYSC|uL27RwikIEZF0hVK7 z&`#=`FcU)^)W#ZD{OY~m9x`??t4PhtV`1y8zwN(A8ezKss;q;t8~$))qhvACn1>N~ z4Uq3e4J7HC;xnXh1YatRuba9s=lnqNg?B{#Z6mN$Kyv#bPaLMVAw^(-Tm_K^zW&6V z-x-4o`V_Q$fDkr%!4-2NAAp~&llrfvW9men4E6j+l!o@ll;B5<3p%z--Lf87BZT-0 zK9136W-texd)-wy0^Np|60U^DtwXyj*1hZ!3i=GfcHOr z&2=bOa3|qZOtuHyUJV<~|CC{eIsO#-A+4jd=DFuDIgLwlVB1Vtl9M|5Qa_jhx~xf(f25H zAQAsyTTiS${=`okMYaAP%e(*P9pXdfpF3Sw$|Eu1B6&RBx7O7wze2_+N=#+^$x3qF zgYE&CyW%qZZvk9K^KZo8aP}^rI>^aR&-zq+dTIJ0&#&g_Ot77eShukwFi*XN>;Ez_ zvRxeHjV^)!kSr7mrpGMY`h$#c`}3!;zTQ+0j;fr0f6Va2X~Mq|-}$0mMA7qud)Bfg zD(ybAqi_nzznP~Il890IBl(I}mgss}EC0|Cw}8IemKc7=_Ht#Rx5lBrg1NeMhAwR_ zDvNn#V}UioEYlbu&_wB7W4&7R{V2g?-bNN}NMkc%k@5@*nO|Zt#NU?ljW9;xx!)W1h+|g!w^zK6zDnV9(z)t+LMrT>9Z-1YH(z`H7!J53F)+l z5)UHOZy)mk8>lQ-2oGR?d0@^@Jn)AO!$*E{HZJF3I=V;E>Lhp* znDHl?{y@sqAI3;duM9l#8uf>LHwSU_%9pwi6E}F31W&Q>IeQDjb(1)9R&9oSXy3Kb z)S@^Wd?-)>%;m)1SZj~E@pZf&4!TEkhju$7Jy*;HC!G47pE1wnCJh)X9f!Rjyo5rR zBZ%8FI#AhE6xkjAS)Ivy)S67L4bT`z>DR!o`nE_htEb85$g9?VS>0mhMKCYqCXm1! z>*%xy5awo@6af1yl`tLH6n~B5bfX=US`XhEzHMWBh@N>Rv{Z*lb1|v8x75)6vHj#L zuVzmy=!@)k*nS6<-z49acyBj);TN+%2D6YkGJ`oRxzUCDTIAz(Bz}M8vfpo0j_2C~ zrCF+m3j7E4Z`jB8f;tyD!9nCxxmJz^!yr}|Kn0L~0^lEDJ^8~*zR*l4VDV2|XEEZ( zxXfI7#oWC6N^*lL|A^+SDeNw|<8eL1UWv0G`teSg)skw%;8oycVq7h7ouL6IkDQ7P zN|Qr75xBS`EP_41X1ryA=^xpiCc=jYZaFX5F~=jkJKSUxrqaOSGG{NmmuI14gMPwU z1{1ocAzyADtRP%|a7{eKH{r{4%k5FEHmQs0QwZ-Tx?SCz(wyl-(3NLeBBnT{t+;X5mmNNND;xyksz_US)*YE&rR z`w$$pa34TeVO&b^TOoX6%%6|-3Ha-^EdAO_mewzMy{qsd;zwSsQHlE ztO9^OL2a)kT5tG!2hpS$pnWf$IhSJ*$Vp5qR#zuBdCFQ?ZB~yz5|5-W&Ktn#59K@Z zgz=B;*1SNClu^^D4*^l7U^T2^i#2U@fRqn>3?|cDH{9Z0JYd{O|ATpIe0zxQ3_j;l zf2RTCJH*Lp*UTH7!&&(Ik)tNz)b!s~P&z`0DV+|*f6Trkn!5W<%r&j#QTmChQHR@%Fdp20P#FqQ0IDDG4072CkEAB_ z9pc44dQ|ZRmMO11t*859T{e*ge?TE>7)}mXVn0UFqwZDS41~BGm{A%;L`B`Q=hi-7 zC=2`*-0qa`WwuO>ks`wQ(TxgyE00P3d?+85leBER@-Mz?D)+Qu__hb zps(Mem(%kJ+Ax4YKVJMS5DNCqi|DBP=sH!n*B2F2z3b?y<{I6zl{jk^q;}}@&DaJW zWh)a;z>(M&Vh^J}F;r`6xYHIY9}aP^@Rs32*wFFM=K7dM@Pz8JEp zAVl_hFCa#krav5D$Y-T5jF=6L!D+TQIkgXD1N0{>7p#Q#jy?Rcej zV z!fYVgz#Q*`=Lf!F#vTc)irwH)s`PI6tNh;~FBps1Jj@5bC*~6h2n@6u=emVo1ei(x zh^B(s$uu>@_~DAzbfE=;O~{8aKoo=^+UY72=$6MBj%YK~2cUnkU{IQa`%)`GbR%u7 z^>xg@_kS|Zz7u#tdwhb8pAH@OKH}zuE5N!EW0(Z~!tdfo{V3;7b1>0`zdIur?8u

s9Vmykq6efZoZ9j1SW;ibutI|Yl$zp_O8=#PL~VOMW zeS+H(4{Y)TUX{7R7k7jCB0q)eprQfe*d9Xm?XH4*%M6!F105u$bsRlNZ&lgoW!T|8 zq5}yXTOf!<8VMx>aWnGXi!dn8qbDL}63RiL)ZAVDH+VRuHaP0Y&zt z_V=2&qm{0utfY@_4q(v%Me4u6{lQ~Ih+zQu$5K$;V9(iW+P&AEXPi0~1Crme;Q`|ThN^(L7qkdS=V3U0^HyUl$FBRUy8ACD@ zhssSsleR(3Laen1+IAA&30@HfKitqu0$5?uu_3>OAO)W$ix^qnvj3#ee6@R!xQ&4) z_(O47+(S^UY6x@VNX|ayYltXqPKp{ngX@qRb$@I9&3N53>@P?)?2(?Lasv#21gN^2 z-PaE@l_!Y}TcyptH2JoaOZmi#;-1xs6+SoF>!931{D3!KA8r6A5E}}yZ8?_k=^pDP zP(r>nHrBu8Om~}B+%#E`5q#8h>UbGRM1T6rZfim-RDfO34t)`_CiBEIs9|wtmuAN5 zL4TuiH#5CWxQx0e1RuA7qOar}rPS@!#U<9r(rK*Qx@eZPY_(zZjKxZZ-*Uz}UYiSv z-=(e$9W1T>HLDFCxxvnFb9}OZY(52sph%sZ75tKB14?ogdNSg6eb}UPX%tTziM7WO zT?VF&fh35VNrn(f`+KK0=#16UfVJGm$dTXQ&>LK6ak3^z`u?ty4u;}VH7t*JApxMh@k+2B|oFPzUZd8Cl`832KlFklk%JjnI5Au_mFXtutYIpO=@Q=E40dXBE zLsZ1^f@J${Z%A!8Bi<$1lq{Zvah;K?;VQ4n>OAS$r@B=)^zor^>eHygVQ04a2^;Zf zGUJG0V87rdj^q{rvK;5AgUF#tpa;pVK|=4E@gES5AGJ}B zL)n^0@)VyuK6AWZ;=4&AiTiNI6Rzi97KkhrwS9IMEkVP>KZz~>z)lH&ox)@m7Q!@g zVL;1GVXYU;&+rU7HCPAa!H%uXpown2isVClnBt?dgdrbQ6>0y8F>~j2(_hGu8y7U2 z`ZG7FO}Zh}$M?xPA$|ff)bCF(;=kPg;Z=`7KVn-;g0G&Ykj%QD^Q&5D@9D zws+S1%nH1E-X5X~rPDBB8tjPBRSaZ7fW>_U=_o5!+Sb=gES(0kBx!{{Q!T<1wom8S z+oFQ>x4(cy3~J^WcUvslAxIz5#~pGy@RqN!NwhjDVFT*py#O~L z4=UdmwH?MM6Hp2DmSJg#NnzFZrO{cT$6I1RxiwKA6FH+Q60Q zus8V83Fvn$$}YT07*&|!!>o2?FC!Z9LoZ8Bh#2Tk;=6WA!3Ovnl42~E!L3N`p&1;T%VZ+Ximx@#|3`W zOg0e~F_6&3;dl16E|P9-!Q^C7(bTnh@^UeD0=yWIoOi3W7V4|Bf(Dn3&&R=v#4l8dhW!9edYBTsQfKH@0I=>t zeny(fh;%mq>0hyxB7F)>_DaS5No=wm3>HyuSqD!S6DDHg0K48hsN@sbCx^X_fDPO; zoBC0H8cR2v%k~p|5Q7KWxaOLcv`E9A3oo?Xu@1-=@c`DzH2Vl9Yd6Z_j0HfcveBkt ze?6$wpW-7C}JwFSX~QbOchf&+yT7?G=D=g13m0_~B;R6qd^ zWq2u}qJV%olE4#C0rm&JtIiB$zP*V|tEKiUygbzdlK5|a*oLd2IP&Zr^ zqA#@XT||S@@_aKsFWd@vD`FCS!7NL6D9$!i7tX^OOdjNsi=|DlHa1xs{M)N23z!hR z@H4S13kb`QZsChww1MoF^Eh5<4cis*iVDpSUKd6+(_rlK{#_s(O^xBDBy%y+U1(Dw%-^gZG z30xtM0}oKNo#;iJDeqz+kqzJ{7=2*sXzI{SJ8}G>y-nJYN*us;WS9eRI>2^>;N$#| znI6Em$6>zyv25H3FB)9lw!jRP7$;Lp%&l)DzE~Qh@$K&HS3f|uS6x*QSuKGL#CK$k zangnoti_FJ;Qk%)vis*oDzNr9vLI5X^$n4FX53q&k}`O?l7{}*OAkO2Dx zln6gl_wUXB=8U(5Vd58Z2wE@gE!+t``Q0(Bi(LOa+cA!0KF)i7d-xf$6VU*Q=k&b| zg3dJ1!BgM}o>^Tu(-Oi_pJg1FO{et;%|ZpV;aE?DAoboN>6<-=j~ctI7V z=CK}v)G2gr38!U(snee?m_MjIzIB zyBB+z4W2;_i@I2B!wdi{ha)QSeg&6zfbk-%)$Nff1kBHju27L5>NS-qX>;9#4#O=j zz2S|faD8(cYQWDbBP4`)3~K0~S)#qdq(GGSCGhfLlJ&^`x#_{dPiCnA1pv4L;a)Gt zre@qxLcUfZ)`2SHCsExw5dQQ_vEYQk2R^%G79 z*_%;TyDmh*`avdD%&;Qd!CiR_5N7wWfKPFy#KBkq8e?IO=%n?z%Q;Yn$D_qp3<&-B z5D4Q)F*>D*ZM>^5AyE2$;CX<+VpRF}DQ1*l?9{}p1b2_%p0JVsz1a_!l(LvyK^Ysu zaymS|UHS}Y>J$0#K^PoB0+4Kx#wdF>sAq_6!Q?g2s!Cw zT4;9IA^YkJvY`{6phw#3z3FY|b{6oJPCUO22p}0KzOJl`Ci27m!P}0~4a;bm03G|P zi=Rjt*#U1_^StmGb3ZWkYRkHZskrQ$Bz=B*h0-a;|LN{6gX(IweeV!L2p&QR?(Xg^ z2=4AqaCcp3a3{FCFWfD-ySprcySrY_-sjx9`w3O=r?+m^onPqrpDp9pJ?QS5Fh`q} z1{i#pz(pG92^v-vfDVzR613UfMGfGv5X?{n^XI`(#fTIcG%1e#pa-9OOa`k;kxp zoq!2u56!JDVbN>oHUe(m+00Rip%+68qph=hRQzt zTGIfdJ^1cgnDYzr8T%M|&(jkSh;isritai3f{?(Q$3VZL6$ojzo*%xZEw!YvjVJHlyx zIMAt@NOqDOVRO;$RTQ|Y3Sq`@jSS_%(hbgV3R?0Wtbp=KxkDGTZCS%I;VoDy72RF%C zi}R(KgycZ?mpI7CJAwp|CLh*z3eb-NABynfrh!8WLLmMzc?6JzR8d~t1A&>~(;fhr z#wq6v3>Cipwk$-8n&nm)JNxUq%!IvS%)T6xnGhmCl5XN1CjU_p6Nv)e1fbxRzk!Ubv05pj%6OlT zRRcx;Q5F66bA^0LE@Ju87=$?_%96wJ+fry*2vn6 z+Bw>L+T+x1CEOrwsBFk=yySOq(+-K+724t2nb)LryEFC498J?UKm259e{An;sz_0Q zSH(m}DtT7|U-GeJqGz`V(&CfFdv}C+#KaGWvw0dRqte#8ylZP^0U7VHp&mc5BeUbM zV>M(p;}RJ&*ihK8*!)*Z&Nql@OB~QY`@D_46TJ7@!;aI`oe@6Me+q;8_A&lL{J|=q z)gqIzg0q6Pf}jGUBD~k`C$TPL1)UB3YsB7?-t(WqubtugYW!AvEhftQl%HJQZa)LP z$-H-(ZcJtXHc&2*iKeo!x?g1-PbO-cU#tDl3nB3i?|r<)YnTGo zu!ehwPdkYZbUE!opGs#^f7JJtAZ=5g(QRmXVVpc!qhBO2AjUIB%vzcNZMbBf1Pof_ zw{jj|h#lF;v*rp2U#2U`Q6CB-dWyPvZEG&Y?<3Ff9=a!~Zh3n(y62*qmR8Qfn^)G(E}EuQO#0KnhAw7DiXw0HU{@+y ze0k{Mi0a^@?ayocGPh2;9Q9xW8@a;)L`<&B{++nR$uX+2#f}%X;l63P;}mi3oxbfR zre2>0jdIM5B-K{k+GJbsJWuMJzLUpwwG%#Kt4$c_9*(^;VwbwJE3^9a`hY5F&%7)(vgj#qV1Ij?tlIr?MTLvs>&fNLyM5&;FyU)1ScA%G^17jXq7Dv|{nw z<)dfYHZSf!c;$~t4tpP7RC{=5Pa_ddYO);$(^}jsI@5Lx37rRdCvQhDsyKwRG#jyZ zU^qtWci6#E8;|@E7ZT3t31c1_v8LJl77-V)&Vwq2i5uL;uBF&Jwf3oVjrL#h%Jbw* z$7kuC!ccgP8j6&E4z z3YlRQG%eN>xDxX-^ZUXw3(qoc0z}KPw@Yo+2%5X$j+?>IL(Z|}4AlosI;#_w^YBLM zgBGRuGmd5wLD%NXnGa@!HTbAO)QDN1^`uohW!;$mHbbXWQq$KD?s_6GY?P`Xw()I0P46Y{sw|VWAKts3vU5 z(q}kL&k}|wM?vYoF$291Nn6aLh-b%f6?GppR9tCBO;#u~P4-xbS#iAX)(>E>1 z5=8|XFk|E`%Lf%{ib<(V-NCR3jI0fs#V7a3fELVHRpjiau|35{6fSN}YroU1fy}bh z`)8)v_OU#LJ&Iem_RWITJI6qH(@2l0>iO|!7iM|t11!@r`($NBvxO|05~T_Uw@|g( zr8|peIg9;tpp2O@O%Y2ujfS$t{5o5}Rp`C{L9xzEd1|3kk=F9}BRRK*ti^(BTO!Br zIBN;hKO7Tvl+k8{tV+rXsUAbb6-<`}^NJm;Kvsp|#w5hm_>0wiHN|#F{kXl=CRsfT93F zC`AmV09cRfgUVCu1gOd%P$G@vLw_hCk1pCYYP@|h;& zQ9}|?o?fsHYBZB3Q8b@P#+9{H(x5ETRw-AYh|7&Gtl2MljoS$--WNwIGKiBzDozKH z#mTiOSpx;H6rRYn5o93?OE615DsZqUBIKQ$HDF4^nE7GyMS`Nth?Qh>W=w#R;d1(g z+4rg*l99zSGX;ub9{D^uWYZs5_;wD&%)S7M@(U>xg`^awb}6nJ?^Dy2nPwzGpjKHO zS(dB3`{;Bz`x#A8*>>^WWy!s|htyb+kQp+d{9AF4qJT$1YfkdM+ZA9&USdWb$X6;$ zRmge{4(<1HbU4uImTP&I_*+FL@yRq z9}bz-YcpXMw*W_6gpTISg;5+uakBGoh25DP)wJ@r_d!kKG}A1O;o3@bGmeLDt~V;* zNbu+4Co8v9M@qMoS7yy5;#<14`3Zla_7g^cz9yqi$@JfX6v zX{ms$ z*+@nlN9srJLa<+ld7|}cPxxL|2F7EB>Dyhpv0n$_`sk1CX0cy~;Fd)KYBgaa1}086 z=81qGA^KsIk@rST;?wwurmNtOh(*&#AO^0j;vrrQ%7 z?j1Vd1otWUBuU0&EbIbsk#v%D)@n?8i<`9TW)OW6MbRpfe~+8A?Pkz)5;f)#IeZCV z9J=X8YZWniz`dKi>DL4kUARXM-vFxGZ~9eQMSAz2og>rXBZs|3wjV=r)n2QKI*GD& zkEFf^oR^+Nk+h1m-so>ZgP9~e#;7j<)yp@-uwW)CkI2Vew@orIQL#s4$r+$(_NJc` zOmyH8X>kgunz-pF1rzbUwup&)hZt1_i!1ho2B_+}=~o65ExAWp+yKr)Poi`@A`dSC zRj>A0fr;GQBM&bCRp6U`2wr8x`}Dh!n_&VlQ=rEf_8Gu_`ljC&Oho1$nR*GZ8@%Z^ z1rw$GiNZPU*A^VC^qL?t_J~Zq0NAbG^h1G(&^#hFuK{+i%_)J2Oj||D?r_GARuM*zNP|1v;M>aRBUe(2vwJyU zDSG6n5fZ8a%Q=T!dfOmmJAGL}2j+5nb<tLcs;ZN ze6WlDM-PYW51!3ITGO;fX!R2FNQvpDp=J8cE6v&znL*vzwbJ7=WXSm|p3)r||UIUWUxk(oRR zR}8ux)Zfuwn@W!;<=ZS?ti9trp~j|1)vk4}L@_(2M>>_Gql=w1>dkwB6WRfKFNy~l zmykSM+YiIj51|wOKvGNxKtZ*tq^}8mi->>;IYQ1Kpmv)K(dnEJZ>}7(`q()Gb39MJ z%&r2aNX8xq?@!W6;$%q$6H2Kmj5YgYJ|@#|9(>h%5@|@=libNNaJy9Z$=~)5PZ4PH zt@pUp`N302oGR2gTQ#pCkRoeBJSUU%5lZtMW5o|lAuXp}H;or1HB6{1bB-=UM=9GT zr5A;oO_7fBJUIKXGkq_yaI(7`{37{F%3#W;lu_TbZI?smAfGD97LX{S(|K-Cj0 z;spl|zMcgsm(YgeG=sU+A+mLd`V!Mbyk<03#DES+7wOV|{`)}vUda)|QK17R!sNQxNTwI0My84x<|-1Sj$#T6In$l`85PckE5-?Bdt{kuV6p}38PSaP>@BM z&+yXqFe?|f?tmQj$Q4HvmW_Z_@5mjC)j-;<6z=fJ*=O8A{adE=ew_>c=K!>en@33N zEz93&UVm^NsZKVvey7}=YOnS^+`Yrw1mAwf+a_|K_UtUPc(y8TnOZeGsk@nXJMy^p zeDL-de;(m6z^jX#7dg_uwtevPnB+0cs2iI%KC-`deem&^Xf@EOE1y?6VtzrHC{mGT7uzfeBFgf@emac8E@I2yT1OzMr`dSTveUB+-#JiAwW%s zbns(UmIbj+G~H0|IqHHSYut!|{Q`e0rA`cuA=QHVi+S-&OWBL#FPtqbMlq-8G()rn zrB;gOfn!Fs>t6svx&@6^l80R{k1ejMj6*u;e&?<49HNNvCj$g_h1jHlLtpP&u?cv8 z5p4z9#bVR&M(b~?-c>#ddQ$ccjBUDb@JYwUY#ML~NyklXI@~p;66_4R+O@t$y^Piw z^0$k66sC;_51tHzJ>z)$^X!r|X;u2;&P5uY_vc!AnoQdmb=+x& zTP|NNU-3UCyuos=d?OHIV^;}ClYi#K z-T-t@HzyXi|4rZ}7yTwY*Vpp~B|(hB?&^5CZxSi^uS z{wP_e#7<>ZKMsq)G#h;CF1bIuHuQ%90)K2&{q6nrJDvUQ126payIi~OI-LVA0^$7N z0#0DiV8K|l*sXNfXsx`O#G1^S)SBFygxmz&4BQml9NZ+_EZj8QfJavsVHYD8<=fCx z3vQ3zRi5klhfoTBW7)%0nGJQI2e^lB|H=c2?N5G9q{eBn!@J@=>*cuSNrIO37Ky++ zqUWH93wB%)vWlvV?j}drgIUuO4dV){w5<~tn6xff+YZm=G6Q6%HGdQbALZXD8{Mjg zm3`W@Hq17IoJ1RjK8`RCM{_;`z9@d5M&X~yj}filSHEsm9IV1V993VMWe88iW`yjr zv_-VO$1GRzj^pGyAYHx@Eey}x{>eCIqDPL0YBzUq0XY5`{;(X5iPVttLfb5&z$+Kq zn%*zte}($p^kgrpdF*rr64T4cYpS6KP-2_nHZiT}8ZI0+W}@hf6+RvZRqEv?j8Zx_ zTa?**HQ16vj3%xpYd42OawjMMdi1LtA-Q^_`fuFkkj}^2T(WKy;%@tO4m~-A>DL&f zsEz|L5ik*1-)+QfUk*V3>b6R3YVxN z0TGJ{4!Nyn>*vgTL@clD>#FAl%FZlo5&Q&9jps&c3a0^ z%ucv6vqkHk53VJV1jfewAc!Rxz5Q^b3-Mv~_!+!2gUHpsen6JfR6~V|o0(zBMt@hW z*Gp|Qmulah3TY(w^%hLqwO;nH+WO>m;+CydV5H7$DA-_vD;od401%Q$Aq-d!0^bWu3QIOFL!mkK@Z{4YTl_%#DLERjGXO=#eM-W>SWVR zkcE;2d~vH1T*tR1T_Q0PqpAuOeynC*&&XL=ay5;*{NUQXU)7}B-D(K-VR(q}fF`vd z(SXTkJfx+M2~UvvV81}TpjZ(vm9WJJxnQxNX+oSrr-3+HrKbkN9Ag>#1Y2qVZAg}t za`^j@Td<#YpzOP~TGAn>AOTyUkE$Aioi8;4Qn*otT9-x_v{V1l=5>X}F}`y^i(RcI z0`w-X9TGdaHKFzU!0rcQ8`V|*)%Owo9$T$8imU3Ym=Oa@14|vYuF$T~>;y>h&|PA# zh1_4I2f8+Y*r=~+;3B++*+2i#P#A2=tGS-tVA3$$W9RXQaxPNB7fX{f0Wp$cbh`^B zteWc&LhpjJY^m;700x2(T@O8}Jco{JC`J~GoH=Xt&D8z3VPTaCF4`9SJ*AUl8hH&$0YaLFQ=c%i=GcFt1aQfmcI(&uWJT9} zkMAu?fONh~nc_o0#L`ZQY{k#62;)0!q00{9?!Gq6;>tgh7bMfRt90V|GnGM zbX0Y7zE~=X4EW=Zs6938WXLTF2~2xuj4btHE;NjQC;CsJ$ZlP^s8-d>0sLrTc+rm- z!u!9FRl{r@7`s2z@C7EWqq7if>q30%_9=@f3f-t>s_Z_)6n+hxu4T?CZ;6lmC74Ew zP66qo0A~?W(yw5BAa@v<(D#D z9Vr{86okl~hxx z82aQW;;Nf~O2L4z0$#>mTTR+1dz6L&!48`3_|G_27%GyN4HwH$di`4KWnYMnIi0Z@ zFKv1vyJ2(s(DkT_RIOd5{dck)GMxb!%N zG-wM+OriUtFBe1aUZEzc;kg(C`128%GY*}2By7G(LX7;P>w4fywhC1UXHC_C_I`S zF&-D;cJ7FjWuF9p>HkgVhT$_jVng1`l^gr})+sdYFtls`c_Mi;{rKz9uJ zXi}RkEuTc(MEFX}ay@c;uGWB`ahWdgf?17p6vnTo8r<~)IOc`*hAg+8z90>Er$=os z!yV%U3n4PZ6BB48N(K;ck&~*SKd}AULqDL4YMj1KDLSgx{m>>>Cyz8Q4AAAe@|NF+ z;3|YZ%*CyMBYI$}!peDotAZwSM_mX#(-e*%>SG|>iJDW5GVeD$8~_-Qz{*D)@+bUm zN4NIDct=QJBnk(tsV7m z$ez`oU`R*Wj`c<1fH#^i2RG=1f3|Jl&W4*Ce0MERP_tjwwUdp#nsBLrB%M3eOfKJI z+I&lHGd_L|{M18`$xfWbPMpWyEsq^7hdudvTfm+xW*d~lo}0;@o6Fv5PK*M*1Q~&F6)N)$b zdp_7)BIf}g+tb&tL94&D>yZaIR$w@_^RUB{Ra%$n@p60Hxgf-SdS(BBs;522(A!@TnquLFz}uOa9ti8@jS$xWmUnQvt=e2HXYE61Y; z*-eBD-`C_bA`^kgW3o`za ztHjF$3~MzL1~D7c$)j2d3oj==0@FQp14T2#ZPPnwpi8>w7ekjJ&fe7u;tAr+sNO)J zl@N8H9*}>>{n^y0j{}LT+Q+Y7veB-h`2gXmdIRlMf)YhXU#O%}qL7I*3z-F&EgFY7 zSQtk>;P@Qm$WttXK0WvDK&piO;*2jMfKO_oSWbpwHqUMot1w4WbA))Vy-A(6uSvK} z41F45A#yoz{!bxnpG!)RtrI(j0O>E&*P|0fL&RVfB5V)IIV8&TwqHKz^}kh=^6Vrio%>4*OQJOt)M)Cns)Vhm#HSl@<9O&J z7p-|}H6dy>32HT8gNnR2tM;EZ3N1uMQy8Mjiq{aQsh6w?)XcbUfH<-hSlnMI+2YGv@~b#XkSl-YoaEDZ3=X&@27hnLZzZtpP+j#`k5vsMf#Pz#*GE+q*Ti zEc00L-cUJvbM>p7!qff9;~pAvLC_v;*`aJiS{5k_Dc&~w`pGRs=c~e31=OjpQ>aW| znNVFr)I!2Tq(VkQXhKRuEJKb$7r$}K*RSrJAKhA`*|tVp&TtJplCO}H_bU6b-_z$`>3?A` zEBGN?V8FYR00Nfd`c zh0oJIyjkL~I}B=Jm_2MoioqEC{gHmDRghD+*Tdf-x035u@3AzqlXHG$GhFzJmgym4 zb|qJ0@39rLQ{ebKj<~+Fvk;5$5w18+*t8t8yz!(cAeyaR6o7fPEZ+GXBJ`3D^+Mxx zuSXDZO`6qGB=#T|d7VRXB%%RoB$`?FHCy#J!I! zM)z#*^|;C9@-h|G@#&Srr@?O>$WfNwlC)fDg;~=0T2oS2t|McSvO2M zH%tY$Rypxld{XDqn9I zCn@a4<-P-w^3qHA0BX+^q5f#6-+0`OAe+Jn^atnZouZvAn6ZX>t6>iDo#?sz>enrA zf$os25!T&Y=cB)qoi_k3GOZLRJ#0G~r>*W(tu%NYeW$kWIy}KL+tBB}cLeSqd42GD zj4w8BH9ZM=gEKm1HjGbQA1yo)c_Zo8LT~*a^*kxsQt7r;&dl$w9zS}bwE2U3Pu83- z-0q$pA)Y^b`SJEot3&~K6J zmGztEN%h~p*HU|zeT1u0#aglnycFn2trUe9^?7|au)UGiu-B9IBtG%rI(<)-^~%eK znCSDC?84_d-Rb)}^p`SKFAbi9n?2wj@-r9P8JRuG_p%?4mz}EMZ)#5T9*Bbp1sOpy z`~xI01MtJ1A^q}IuooGn255JvOqo-ggx4A0Pp+PeYj?mPuBWv7<_o+GBav8gqaar# zQ;O~P=m+qo*Z8X&?<%^ulRIAD;4d-hlGa^(cXzwt9{!C!|8A_Cti2O%SVeo%S@-wP z`uQ^N8)hTV_G^*CUMB>i)}MYqa(C^iiMr}O67jGob?82im`vQb?$RgfGXcYR>JZQc zEas5GV?S+YzAhPsq1KgR3@@W=oQ>e2>mOBEj?L>gBTs!=LJWgM2Aix0S&|96qsZ{Y zL>_SrV_S?FZtJLJ6bvJCRG91;#0+cQF`Sdnq3 zqVL@&n8&5$VF(#9s;*4yIwoAlig4CGFh@qMiC z_fnl-@3-*3bNu`E-O~#6zw~$ihqi^EQT8iK@&h>v#Gs%zBXZ{dJIT9q_h02Qa16oU zi)3!T#C#?g$}N_h;wi9{_Wx!=52Z%x*)S9cAxrf^3S%iKfu58anb1&^2t$;hm;rLq z2R|!xP1Zb8EviS93CPtK>Od%G@L5dwb2y3VE!pa-DXr=ZXQE=;k8se)?|0yZnBk2R z@&K}CnwbzTjbDaqCHZV)H zZBEB-PWRV*ctpbL5P#InW-NMgl`Juo<$rv~4Kg%ti}w-2p{Z4;DTG4nnCa;Oz_V#V zUCl}TnBMgosx^gyJ+t>0U#wKvDbs1Cy^AS_Q`6OI9_y|bF(g=C^NbjHkG}v~!j}|K3w^7Hvnri?$>{Ow}dAP1{9B52C@36L0AQjSai8nv9iO#T;oKLDuiit@^ zEx?1j>UXcuBFkkzxx3YtW@sxbE64bOY_}gK=}6R>%fkHa^e)2%6}nRogD74F{OljuxBb2p7QB4GodCs(BTi zd&Edf;I?Y61=iOb-JWyYJ+QinFl;1^QRV-{_eNvvOpp>yy?Ssj#D_9w<1B0DV=tY&g( zrqWFcPp;emsz9TGt)ToWS5Bp&8u1;6Gl{a`4A!0P;6G!Qa}9VnE5(oJWd@N>&7BS7 z^}bf4ZjKtOS!(t>IR%k%&Q;Pyzh(`;L2p{8f8~j|NsQkGRk|(=(n68lXg)2dmphzX zmB11BqZ*E(sRius4%5($ib-H6wmsYp0Vt3q%7`5;mOYgF!oHEM0R3k)P+#VmD{3u9 zJ~TJMIgrxWrCHk_uLR5{u?^;2kU}#XCvcWCsDt(Y?8o!*4yoaYJP1e`;tZ$87d88J ze;wmd=VltCb>7~rjNG;o3|kCASGt7CQQg4!Dk0?+DJSqu!>%iYg8%UNBr*TYD7n*n$Lv<-Tz+<4t zav8X86!G$3fKZ2hG7VV@X4Ox~Vos27WvwoCzm_k0F+?90YW!N21d*)J(Wu@}(1|LO z$63iq4(MldXQVmK6q{^5bydebXDv+8?C1nJrJ&5*@8A?$X(rEY9#vT>ksTv7?vw$) zJ?k1T6{Sf&GB>$xNA%CixI63`v{#fsh>W6NMjb?E)YTNoObPJBCy9-&yq?On1GEA+ z7l?sFBUYp=(iac`bHwA1N&q}*-Wo#kv9kKE?3Ak-{p&W(Dcw^v!KrTC zALc(*0!E(rOL11P?=csI40|%X9H+XN4zVh#Y~7rT%n!aEn}#Co;mxwCSI>F0)O~)0 zDftZg;0JpDg5Bl?Q^MmxtsaGm+!D>NbfYfo|DB|!6iP|k3jx&XwpnvR(D3NCJ7Xks zUzomMwaKJit&J%0XqykJhSca&G`279L_pCFOeNRSSNan3)zqo-v15ZxVely=O#P^| z#J$c=|28N|34(w*vj>S*0idxrETZVxrH(XnH)o}vYKw>JcY0F<*YByOv4K;gNfu2p?dZAa{4}GC z_W~=0%kg{tW%EZt+Hh@|3FaOsA=>-k92IL=xYX^~`;CHDhad=j0hmR8OX}%6qk?S} zg(4h(;f&tOBkPR@b2~<#4~w(}v;>@tG_zG(Yc;I{MKGoqU-Le6Oer1tWNz;JkZ+y4 zP6;hP%DkTS^pWL2-pvmSj)7~$_@=VvGA#}_c7FNN{d|Im4)>}&-L%kt12|PPL7I{Z zrGb4aC~*q+Jgg0N=rHN2|W=kykV!*a$pY~$yMntTa1h* ztmUe7KdJvG%jTuHSOo|+nRm_~h!!gH<=380aw-_~P&eziyIlPy@F-&JhMA5%9kYT7 zc3jVPgc(f;N1aiaJhaN=f=<|j1FWW{qboUX%AU;bk7{5R9@l)9&RyJNuHhMHA8&5& zaXYW%mr-+a(G^t|aGNz$X!n<%xRK!!ZaKYa)uAS{)<7HOnz849%7pHUulHKG7u2U4 zb0rbzM4L%sI}19_{an7%liWgL-1=SW!?kE)CJiDWPSj78&nNrawR-|I1-b1PHI&Uy zK*o_VH9rVZHJ~m$^y}-ebvcl95#-qPSehqOxlDE5{$`K%5*;UOuTER;m}uNLY#2gc zhKo}onl=cwR`z0<&|e>!PG%K6YT5>%q)u#&v&QdG8fsA%KRrWvLebc}KXW#CJh7u{ zX$X?QT6ENUmzIvJn<&A}bHAYKqCkg%3v!;LJQ%(MnN4}JJr8CgV>C(}7sgK*PPlbV zn?w3qpm~qRhtGV#;zCzZff4&qtRjKVqgbXh#q&#zU9;JF1ol=17E7AvwE6JjYj3TkA3`m;IWBjQ3vANV6UR;|2%Zi7#G>O#>%1Z=E3AN^WWkGXbwijBAG?f08p zEfJHRxcf<$Jb%P5OlwRr59_SLy0c}So%2!wPEU{JT=CSEZyn&O-r?KXh*Y2R zOTnW`mR;1<5_S+R&Zg~K<<%SqrTx}^CS8INB*JRgn+_CL^G897OLS&u% zqwkgOxFsc*r|mJKI%Y~2Fk{(vG(GYQnk;aX9+r30YQEV5}1b z|I<+Ji!YvdM%dhV*;-!WAa1E!_l(owazgpW2sY2NjaTYj&cjbQSm&h=IO(c;Ui=pZ z-TN`-?s-BdXk^miZR4kA2bnA!WGAc^N7I??1q$_LgIr$%k)B9pzI_bym=Q?SxZAi( zI>1vMc|2P&ouRtR&&(|&d5+nsCplW`-eau@)!@7s#aJl37CPypp0La*Ph#;Jp0W}s z{!!;@?8-WUtj@dQFp_^&=Mm9yp`rnAS%hoH`~s|=P=F&!LfBR}=T+V;_uZI<=wLZn zXmO)P)fsn#y6%tm@>>Oy1b{Q^r7bVNfdy#71|L4O=8(eWkb2^I!sVa|KQFB?Ns#I1 z{rK_VBSggozyGW*u=Vx9>*LkSm$;tR*`%aqHqFVwoWmajg9IuO#twU*%+n@6UQ5b@ zl(E5QUAZID##bSv#6p&ch7ljsL7ZchShMTOyLB@w#wjbzfvM}30y@tQ=VDCcZMFJe z`fyX{uV*jteXFFY@|PQVE5VIX%_mZB6!xR>+>br0vz%L9OOeh2qjr;^@rJmn6>^*7 zv8TrAy%e~V;b7-wu)o(=)MNd`o0z;Y8U&Pt87aktQb2FOjUQ(!kJo*b=PFh?jqS=D7bn;& zBh9`>qTjcXV(Lq1iUa!ttNxB%&JQ`Kv5@nlWdi}pY(!TL;+YX(8T(qrkstWJ`6R=@ zs-eZkH2Gn>{Rz_Ya=(D;catWKyuW0%<`HzdLF&vI?QfezPM zWwIw+R$#-C<5CWyFZj=SD7_G~NtL&J;^a7{28EY0h zf))dFINfq@y3u7ZSx7*ogf5X`eseOm64Ws}N-MDi2@8}itgl{MNbFMH!P9WyWN!Yw z5)KMbH+gsZYNbNb*GpmS)V?ov7FnjWdZ*7Y2y2nU*0n@r-5cc6sC z55s)G+Z+N*PCv7bXwaKw^iT3Mm*xwWmH-07cAhLHvbOyfGcbd&PltHLXM%)m>N**6 z0XKC$uU|VnIPN4}4G)27yQlBb@;C)Q(N^Fs{Bj_MAx_SXHsD0S5t$4kfg!~phN@q; z^&+mjj}Gg+C$fBT2+KFjCGIN_&c7U~c+{efGJ=p(T0V0QT5V{}^`i-`D*MeSuQ1^j zWVVfDNvJ{+F^*2e#kw0}zjXw`mTqXhTy?8PHC8IT(ZGfmf0ceqc{~5B^$r1`b)`J4 z_N;hdxzfC$-$2$&G*`pEGQQ-PHc_n6m%m-2zF^i%sEHRS z#dVEMXiYt9)#i}rUZ29;wB^?TId*XTyvDUXx_?@>h~(^l#1;1>@rNeVH@$jr48}0V zH?X%{XT+g-&Rys#b1=RdNXi?r9f;tP3!)6g=mnI9>@^7lpeNrjrj=NAN(4cZp3WY39Z=CTay7sO^H)$>5w zh{oBMl`jL)BGB&Gb%zW2$&&~BGczKRDRhZ@xTgl^-B~T8&0tUWtd48>2l_w4to6U| z1(vsG1a$hF(ZbA=V$6@KSWJA^*Y1@H$Z+82tzsC-6CEI`V?4mi*Voj{9P5Vv# zddw;F?rPfgnQ!klj?Ql;(AfRZ$cdS@mQot4NOrBmKGNP{vo}}qsy5JGUwC9qq}(X> zYwY56z)~?H5?7S1#Z|d0OI>51MLaUW_kK4!a?1j*gQ+Z1OoDJpJm;&?N3jWmj!dDn zMVcWTn+Y~91)E3qo)a-%o{CuU`2jnByV@3f!>Hy;bTFgu?BKL>{}KMNZ(2L~TNBR@T>0HYv- zprDW-2haa^j@Jf+O)VS@?dXIpemK0wGS{~@FrqboW9t5}ZL$2d5#eL8@w~{bA%y z(`y?xAgdmT2ntsonx7(@+=f|2ol^9{3%SVjqg@k$@uG;ra#7BP$V4xuwC!gqe3y_R zK2xe0w}z}OsCi8jf!&FW-39Te#ZiecXZ?}{f!2@($(aS$lm!jULgF4r(nj~@Lw}D4 z-$fDDP9E05F6oU&O7KqM^9N}D&jFtV2|gNs4m3^tsg~&Ls_HGI>SHL{&O!VGs;UB( zLbMChqMg&CgVaD5%dP^lxdPgi{5!IE1(IRm{7JdT!QwL8Vxq>1f&Gq(nWGEp9h5OC z)ytb>>SAYTgaAwbI(!_jKmPk-WWr}`edVi2qq1 zJ2M;eUm6SZtFQkf9~;MCws6oh|I=m$RtDyO_6q|mGyOlyGBR+m|D`c9vi-9xBQrb4 zKW$-T=3x0J2O|qT{a^h|PtVBw_gKD;+h60$$ohuH_J+p(hQ{%?#zg;y#_)#5_=fg| z|1rJ6@#>*}aWK8X@#c8yqZeaIn6?@j6HR)duSu z9IS6}u)e{;`UVH<8yu`}aIn6?@j5sCWgpuc9BglJu)V>-_6Eo69QJn`Z*Z`^!SOm5 z|6TSC4z@Qq*x%rIo!9=VkNph}_BS}#-{4?>gMwNkj+Uvs2`Z_oLZ_UB(hpC03 z9Rlp@7W2P1mK^`T?Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *


+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +//#define __CLZ __clz +//#endif + +//note: function can be removed when all toolchain support __CLZ for Cortex-M0 +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) // TASKING + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/STM32F4XX_Lib/CMSIS/Include/core_cm4.h b/STM32F4XX_Lib/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..544d414 --- /dev/null +++ b/STM32F4XX_Lib/CMSIS/Include/core_cm4.h @@ -0,0 +1,1858 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h b/STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..e3c057e --- /dev/null +++ b/STM32F4XX_Lib/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h b/STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..c8e045f --- /dev/null +++ b/STM32F4XX_Lib/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,916 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); +} + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h b/STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000..fd7214e --- /dev/null +++ b/STM32F4XX_Lib/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/STM32F4XX_Lib/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a b/STM32F4XX_Lib/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a new file mode 100644 index 0000000000000000000000000000000000000000..83c1dba3584276c2ee5f389759d8fdf34edfc47c GIT binary patch literal 3194948 zcmd?SdwgU?nLb{9Nz%DYrgQJfwR4%IbMM?cx30jTgnNKN0t`+vGnwhYT$)J+dYFM} z5iu&OQBfnp(!1W`f*M^{qRez_yl?dQ{(wKN*`4@lX>V!iY;A9EZF9T5vdH*C-mcm?huoVaXp_V#$y0X36IkSn~4^vE={y z1xx-*J4@L%&r&KLVkzxTmhzSnmU4X+OSzS?lrw`Y<-;>9<+E;<@??ai{P+M%`IU>M z{K?K7wy!Wp!EWYgc%3NjPWV9Eq#GyR!zsh z*M5a%-hP&4e&Sx{{Q6mz^`qBW&iWF|E%e5}Axf)nUfyYz*IdQ&2A5dgzUBD$`$H`6 z&BH9eZjR+&_bHZtYLewY;9>cnUuOB=T4(t$FR%iuhZPjv&k8ymtY9}?Z@rfl{M`$z z;9m}~g5^0@@YhA=DvL1J#jh~ebuTd2{%4u%wkhWN;1F{?HqTt&DrT<#{3hFx6J|TA z*4d70cC#HPzt47j?FCkt)W-_1e25i(Y>*ZHc%BuNT+WJan`K3hM_93AnH9Ib!ix8< zvEqlTSn&(9toV0sR+97(D{*D8lD=QCk}F?fB_r#sWWvcxKJpb-^4t(B&Dg_AOX=#p zh?QPwXQgAiS?On;tn`}ZIUMIK^h-|{ebrklBY!pwc+ z>&*R6^UVFktIYi!FLS@>W97+8pBum z$XsU??#o%ll?$xmeJiZuJHxEvm4{em*}bf?{UTO*iJev6Jk2WK_bjVCyTmI0`!QBk zcYsyxqU)pd{d0uv3|_=`KDN$w{-&7id}Ena9~xlQkLI%KZ`{vnI?uA2`@h0Gt_PUs z?Jnkdbe`4L{esnw9cHz+)AiG*S?#iy)&9DV)xI8Pb=#h0bzQlvZvPak3wv4J;%Qb# z^Q7*LVpd9efyV*%Fq zg$QeWGRzwPbCxx(eUmk1Rk5bVhgj34!>noSb=Gvo&YC_r!C3DYx>?iYkK)| z*7U}1)|~Y$Yo__q+%?RaukK^bM-Q{+sR7pf@GNWo>I!Rqeu_2!_5tR#JjT4m!_3=u zKl2U-n0L=K^WN@e-VYZu?-z1Mk005)|KP#Ny%X2$y{)BV@8Pkd?cVNAwn=`gx81i{ zev7xYeY5Wa zwkTEWYl~8~%(f`i-scvD=k2hz_RKYPQ)15Fs{dPce2X4$(bX;bxOwL`@0He_YsU7E z2jy$Mn&v3IPD2LGVB?fPPvx{WW}=%LGSSBknbg4zdDOcNdDOKHd7T^8k*UBEGq$B= zqcW|{)H9=;)@D?+ic21n@w40vndO0Hf3!v1#&7GJ0RzfF$0sw zn8vIzrZHWNY13ji86@LGms3OTan#JclgH$sW9QV9UB<$LhmVa;Y8kZALYn#}rBzZ% zYbk?tSAwvXqPHun%2Zrd-WkQ?8LCD+Lwnr8@xzB>EzuIXq%1K=!8YTe`;P@r#;Rxu zRYgl^Rph;1<@V9zu^RGTRlvP2GckD}CL`~a4DNNA<3}c9GV)%@;9i#r9=l^K{xp?R zaw?^@P)q35j*K6Tsh0PuioDk<;5H^cHfoTU3B7_$s2aGBRT&M%pMZP40`8SO-Rk1B zThdU+`>Ut*^5FP^y~oEU#wKG*4LN#$V=~5C<44C6D`^>qIx<7ABK^bTqX))A?fXt@ zmPJkjY|ZiP@uRno9iPzl_E@prMY9Su^G(??6~oQVjt3hY1XBb*z!KUM&s&83IAL#|`Ko?V4_2w&_PxQ;k`nS%%Z+&nkK0(VRgKLasplP}W=zl< zf*YpRvoTAlG-he9+>n#dstx%YHE8mitJ$Pk#w=qK^;L`~Dqk44<}ppkGc-n*+tB*N zf~{&8Tcy`9=8YdEV-P$>MTrBOkZ(|K%-_(YjfLl{xm7a~^9_a(L!>=3K`kWWZ%GOm zRV3JHsL(PDDvZ(xh!`Prnm8EoOhc_$=7wP~m26pO)8}qzZcN*TcE?L%HdMDp`UKp6 zES961VaU;qqArr~=(t?Ma}C+ChmzrrKM#r6qma;_VleLs(z@AAs1?iHq_(M<2EC@1 z8cU3g-Kbz=Mg84uwq+$uu?+$(vBB7^NDa*$_ynNwQbZAo8wxisCHtl1IH%!29F;zHz1y!@bp-Aq7w3Q zZZY*h%Sxy$v-FA+w;hjr^IAd)gPPI%A@2?OdTk?>Bk%PG5yhj+7+rUx+b-|5MQ-%o zCj#RJ9II0LqqQl@39(a)xwM5#Entc%6Dn6qe% z^eh8`8J9C;#vc*SG*#Els8OYsmsnZm8R}}>i;-T`HN;B{;s(Ac*7`U<;KPg8><+ zZ;N*;Av@kSW45_38_Uj9Z;KWfvJHLE+iD=L;w?2~#-A6@G-xz%PVwr7%y{*9rlESg zf9;!(6lKR%7^Sx!DaHPruih3dFk~k%5}ob(Xd&CM!x~<$xg_3dQ;F#zF~-OEh#2X! zG1F9C?H@)twT+mw%oX(wB0)~yCpKo9s_Q1(D5&Knc3d;sSY)QLG8Al9Bfgjt-h??@ zLqWzym{-15o#ad%P}bjARc!+1EJMY(8)qVnKwl+3<2<5UD`6Io)6p&7?B6Q*f2>@uzQjPYB*D^eBLmhKjY`2iD*i784U2l^~Hb(Cl zrdd2MKEq;pX8U0(*s6x%-NkB{@;1|Ko|UL;o-sy3$k2;~?0B<`+2$v1EIUsi*T*6zEVkUJu?O>c( zI_Ng$#b_PVAjR_&A0Nx#YXr68xWF#r2PqNKQ z&!fLZP5QXsyNLqxy4Xs@(B(};%mc8c$a$N4{%6DptMd$pCSzVt28URuu5=w6isB74 z7a3Y-DAI0?GcwM5sj^K~YGoUB8i=WlN{xjZv>FOGRlBJ=BM32aTZ!Wnqb4@!h?kh# z6D!%!7;>c~&z1NLE!V6?<{C8U3{QMc>pAh7ao$INf==$lYw0=hT5-xpuNCWoq1W-e zc+GfT%+AEJRMVTapFPERm92gk)#CMbc6PemEgh{sjc^%BJM)&y-)gZ~nEtUa4~wT5 zixkO{q;`4nu(z^ZjM;T*##U@}Z#AT;GX3x=_Q}AVLE${^9kF7zl1cZ53JcpAbH|IB zE3ug6qRb?3e!d$r>f@#BfS#bMkG_WLOt#O^A4keYd1L$6sJ@%N`UmYZ_Gf|WhxJ0b z261obKkA=PehKA<@mxS%L;K`-J0YZfFkWFjL03F)z>r3Nf0wGOv|Bops5$SVMn0z= zVznfHh~A;q;`mp}v7MqK%g#=!WwjQ!T4K zrJ4$?j-(o-94UWK8twKZ^1@K|2BmB+da$*l9vagi+u4uXpW*g`tE8%wZvW&&w0+jmN=;5lL+0lk zAD~QYB_q|8{3lstt+b~MQ-RTNVyLCF5E&*(o2x~ zyyF$R&~v`#crf;yCla4?Ru;vcb1v~YQNwd0Q2u==e+Hcsj@^_&%AaxkDW?28iORn# zi(<;3OH{sOQ2qv#uR!_TG?=#M9bZDmApZAh`d=D~JTy${pQf8KmhoRSDE77v%CT5d zU38HWm+BInWjsRn_V(*Fi5^|zur6_iex62(?HwmIi9Nc+`*n#oSw=o2IzORF+^tJ| ziEg%`9dBA#h6fGlifSSeUF7>Q5gW@WpoHD`Gfm`4UF1(OkrZkQW?{FT{!iU`Sr;j! zwDzFwEF*-r^wek~sdSM&?vIJkpmal|_fk!y0U~%^d+A0FTLH_chD85iP2wtD;vKp~ zGt2lYB>eB!ByQ6sKB-IWWf>393$pV$P2$74#8bM2U>P~dBr)*sn#8~8603A0dvk_{ z4Y~FU{-BBcr!JCC6HDu`m1R5uEf=~di^k+Hx=2$@B#9bJ3Hz>IO{9b_vcp%$MABKt z65h{6Z`VWybdkxJ2n`Bmk^L?2&_rN1(y*F7N;mqj<O zlqNB&OZ-Tepkez0o-+7LP2%5liPv=r8n){&^p~W<>{(J@(Iv_#9UC?>kMxt(22CWB zF0!c?>LPE_ussbemtCcawCEyZF%cTJKS1R2KYkq03H%kv$&k;9h5GHUP!5Bx}zIHybeR+pe*gH5rIy{<|8RF}x2dQwLh z&1v-bU@7I$pjhZ4pVFpFJjXJAMI&WDG@waT>Jo3G8#!!`(`@Ufggvld6M2g+a#9x& zBytsI_4s|7NI(~PNEb<=Mfy#M-10e1v5uz*Qj#+>)iq)O^F=J-fW5;x{-N3C7P93PE((#6Ic zhG$)7%()Y_t}^D7P|K38%b}*JW@bJOnH!8b*p-rQHs-ueJxm%k=2WBBm@x;QM$))3 z=O^gb5o69l$lPYknSkaK#++-R`OZv33txuJ-Nu{?G1&JQb3O~r_Zf4ZL#_83b4Jjw z_ZxGfsP!RZ&Owa)M~yjHI7ts0a+oE{vNJO$-IiID>7+ty6-!U|Q}|4yUVWyq#7fGfM^AmG56uP&J$on~ z;?VKYBX0Ty&)9_96Y_P|?m2YygnRPXvBMK?Ixu#R9oaW_;K0~{J?%|CcdNIh{kFC} zl;3#t*wL}ZvC)0wd&ZCMKYZfA*q$S!`vc=g$JqZ_wXCVBS^Mu2?K#NUbquH2@^@4d z&{~2`b=eGn!_sU;vU1<81r;6g0Cy@Bzv{pm?N-_R>YAt)KA3N^Vekv+| zuQm}lc6`zee2~x*I;f`~WUJpZ#`UUf{O+30aOwA_myaDiG#QB39jES(9z`sw7M5Uc zzj`zUCm4VDX8s}ERzJVnyY~dOlu9Sf)#dYyDowwo(}yC~6+-NW9-5nJYTqWm5Y&G+ znJ{YV{b6{FZHfKxlHM~77?aTq2@-gLhmRdSGpuF(8dZ(*zXyZKMTH}5k2e#$sz za&jBTOFc^djMLbi_^`*iX&!(5x1~mPYUR;@QLcIVs9BERdnPE|eD>0BO=+>nb|gp} zAE!@O^VGu3q{`YVHrF;cOZI*1=F$j~E}9YYHJb+$wkH1W;_IApX}si2+C;V4f~bDT z<)|;^P5Md0dhwOlxp%o~%V=tsn})ZmwZrY9-xG|DPK?#MZ@S=`E1LD4rLldluW=v! zW@UfCO~0`lpBO)O)ZNTbNM&E0tL=&?o$h8o{bB8SIEDYEDg zWga|nbpIqhuyJBcUMDE;!068TnF>AM{Ok=sZBW^^68= zFyGL)mku^!6DzJo(@jPos5LqMTWEb()EA3VA@>W@mftKVT|#)<{__kfrt!r1onvqh z5?&rgNxr>=<#N9FqwhrK@m8-7rf_RRxy7sBU_Z4n(jTRbU2MtH@Fesh9v{3#n>2%K zE|eCQk#+BJd$3q{ONZ~^vEy!9n(ntKr_Vif{Mi1niHT#!Cu;u>tY&rrc+^pNjm*+S zw@JISg?&XkOWu}pMXEI|IoqCV$+HyLT$UY{LQ9dY*ive(u&}0ylSe3Mk*<@+wQE4X zBg-(!ny_eD)4qub)@NX!3u9F6L-nB6j5qAw^X8=Nm>P4DbYpn zw{f zQ5%%=Jx7zkg52ssswwB`j*^h;bW1I2vXBMZQbf7?=WB~X>HPjCb!Tx zZ_@XyK_AXAb$u&zZydjSDZN>LU!Z(re_t@@!;!46&rZsW`X1OqAB2qhUNPvy^L2eV zD>3T()E4?^=SUpc z%MJR94f=2jLjT3uhxxPF{QI3r-yVa$QiHx7WLS*)a<|ZzM{>sbci5oMZP3?i(pR;G zzAlr#(*}JN27PZg>1*FY-;E}H_Z#$88T5rs`Y>-d8^6;geGeJ*RU7nu%A^m+%bV$o znDjkn(C0De`?g8nfi3jmMArB|&KmU98T9?yq;GNyeK@`~>U-9p4||KgJ~C-zBNegv zckdSZ(n!vz?*)TCIQY807L&dQw$RsT()Wr%pVy#ow@Kfpw$L|Z()YSSAN|BC*1nKQ z-&eNKH)+zB(G|CU?FM}hne=^g3w<*teZ>ZS)YMq}gh}7`x6t>5Nne9OAF!AHK7OY3 zQI`Dtg7p2t@FFQGKR+?)>mz+ZQgRWM_Rv??_unRcKcv%(&uJ>;|8;$Dn&j@GO&4}q z|LAhBnV$Ptujbd_xrlhtpPNZHdL8I^kn{~0GW6R*C5JhL&yTh-_5vId^?@9|J56$5 z&8NRUtqUm`$l;`)ni$lJY6=*`X|Vp$pPNM)Bp3UPker|D>K|PWS6Z5}&omjI2(|Am zlyf0{Q3dt}ugIv++sxRFy0c1Ux<0y1_!#r;?00V(3vH%awuF}8dB!IqZD)B#1+sPV z3>$gRiRFd{l9-J=)WmYbi;(4MrgC_C@eiHjn#$q1#XmNdX)1>&7XR32Bom*Hk&SluDu?F~|JYcm zsT`g_{9|KoQ@J}{NOv|?VJfdMmD8WRPROZBNZDAmsT@0L{9~io$i({C8RH)tt232j zr;C4Vtie={oh$yau_jYFcB1&l#=NF--707@Hr8q?$4(Ld*jT%%9F{-+v9V55IV^en zW25NF#QwuF$3He{S&iwwc!KV1(gMb_Y>dYfvV6dlzQB~eFlKWx^Rs9^>m#708`z+# zp{4C?Bq5#8?np>iu=gjVJ?zs7X*YW!A?;+(C!`(hmkH@irW+{j`PHmI889u~%9<0> z$?UBO={k0ELYfYj64E~Q-h^}&izK9r86wT_(Vo}NzMGKFU@s@6OW9u&(lo!6G1uy+ zv4(_n6Wf)LE@U?(q+RS-LOPqhOQrQTJ!ndQ&6NI*Dg7H$`md&Rk-@~H&Gn}Ag{CwD zH}ntWZ#AXErt~AG^p{QP=S=ArP3c!n=~TlWisvJ~PX8d?U`o?ptdD(Ajxap^gY+R& z`c6~&eWoApJd48liRi2jxi=!=ZnWMp&=@LAueDzTA`^F{SS|r9Wg! zf7Xf}5+#RLG+#N03+#M~~+#RJNah!}Su(5e6f5Y2R`5WGj$~SjMS7YjquEo?H zm2K*d$~ARISFthTK%Qe#U(9D^>Tpjs-FQ++ZQkna*Ki(atbx#&^M=;YoH5F8abk$< z1Ti&t%ng?>!6=By_cxj>=clob3R2j5Txfia@|z!fn>wa7goeUcQ;w%8PkVXhj+q{* zy?3(^MShtPl${XgS?53&F>L6Uh%GR4T zzQFo+mENn;BPuTAwRr-iY{-{dp&p)Qp zK_yQl15mK_xJuJOicIV6n^fr&s{D49CPy5ug*BwoCsq1RmDbyLN~KS$^1D>}Zk0Y` zsvkDVzeA<(QS$Fp>3dcBT`H}Q_kAk;ZdE>|()#n>qteuVxCT~&I6(1Mf->Mta0N!f zbqB6~#@s56Gd1J`_2CNM1y>T0*UQv(NL^_v$b5RW@=C8tUTLW1HLR}G1(}{!*H5VH zth#iV?0{y<%SrmlZf*CdOkKUZBV)%6l}eY?6IQPkrg*U0s0%j6A z)HQ=9BI-4(>ow|nLR~+mu3uBvAFJyd>Wc7r)ZeA92i5gG>iU?v!dHddn!0Aw1VXx9 zU9VTyJJt1JbzM-`m((>WMXOh%uHEW-le*ret`T*8Qe9tG*L8JGqlJp+7vQ>w&W2UG z3D=t#Yg6d~TyG>!Po=NH^#;bSSLp+|4l_2c(zoM!J!7X-dJ5OKG4^*V{UEN_G4_Z` zKZfgW#=fM|QCzQO>`9eg!u1-)exTAn$MtH)eyP&0;!2C=&nlfvWTTZL{nK%!{<(0y zlCYLa*Wr2vy>FH7!}W5;E>P(!aizt0txAvJdMRULDt#Q+OBlODrSHXckg@lu^ha^M zn6Xc&^enD#W$g1R{dHX5!kAF$XK}rVvFBC#MO=3=_L54k;d-I6H@(#E)|S|BeQ^`} zy>Dyczk{g%-nX@_)!QonCB(n|d*93Pqd9_k8Z+c!ml30aVRaHkOKhLb&BDZjg{@u| zw)j}sHpm8O=m#vrY``|c7Fd8SSc7cA5@HLsDdx6LGq+`ixoxv7Vx1$lVxC28i)_TY z#6~R3Y{a(8R;+7m#j;MnBz9PwR+q(T^H`>>Udyz_XPLGQT86B{mLXffvSbZfmMkI5 zl5NW3wa!?)wpq)Zb>1>(TeJkN%a)*R)v{(?x2)M*R)@`FowE9@Q?_C2peGN?hQDX~)4knqoZ&Y- zli!#1+8I8bc}d@;>u307SD)&8`PDQ0t51Kl@1?afeEip6?A!Iq89tZxbYIdh&+t=q zKkuvk*%|(|OJ3{y;*ZYo=JvGyneUz94NvCx|NNOV{MoB3`#_?`XV zzJ;#t_xAs4&l&!e1JnISt~|q&KKIf7-TVyy^D7VaKiqtV-|zio|0QK-_}3>s*FT(j zhKIlU#r~&XznlMP{a^YY{`KAb$)2;FOj`|i7&cir{l{<+}Yyy@)E`h7Rv%^&>BFZ(NZ-OX?J{ZIe#`n&nUiC6op za_;66U;azK?=N@px7@+}Us}0~TR&p+-~X+<_|Y#X`=5REE`Hy0ss5wWckxSK$?#83 z-o+nxIQ=hPe;5C^svQ4gJ$LbU4&?iPQhXO*xoL-g;;*Oqi?aQO6-*<0_-}vMS|N6Bd{_Jxh|ML|g{;40I@;iTb2mjg2cl#fY z-oY2v!~UndH93=lJ*n4 zqwK@}^uJ8kk~~PkrQ*{^0K8{E_TW z`>)A4&a*%88UG{C-^R<*XZ_cI;5Pov`#$Ht^YYuc#rmkO9Q%?0d>Tym~9I{lT~VuYLShe){4?f5v6E z@@v2LwEzCsZsA|3d&Yn2(OdZYKJl#ohd18Bf1Una|7TNg;s18(IsY#nALn(yS@M5y zY@Daw`0xHNWRLShi{JD2i2%Q#^9TO!TLb*#pZpL1Y<_^>>Rk4}`(F?7ubuv(fBDu! zJiPiN|HtzV@qfMc1^=_rgZyOlC;rULo0sg<751m*M8X2wyzqgWc>hB-ezM^v{+>ZQANuBv{N7jXJaW^GydjdrZ~6TV{GQ8_`RAu@ z;P?G8ncq@+1MmEY6#ftYJj_3InS)a3zu{DjU7DHaXJ6+zCynK#AWTTKKA0p{Fy(N@pp|}%s>2LH?RBoTlt@x%lYp8Z{@E&Q_gL_cnkmdp$gu8;4S=n z)=K_|moDO;d$^K!?Z1c@`l>kl`7XZm->dl5BfI!Bx9;S%FJ8#glB)T8Zn}`a^l&u~ zE?>ak)>*@Uw)+A;`rR7-qoo0!bkM{1Tt2`rc*DaFeVg;V2Wt827jPb~tK&sy{rsMV zI{s9LpBKHYp8xp^{ruA3)bsh8e!e~2z-^H}KAzjie^}7RZpT zr|&lLPo3`JpB`=IkNv)zzx=<={K7ytf8t$UKK2tIuPA8Y`PcY($!rV1?ps~_pM0&n zvZsqbz1Ygne7=+4Io!q%yF2;WU$*gIeyD?g;P!U@zxEFK#Xa&+1{uhr4(dV&bU`O{ z;~97so{49p4QLD6gtnoLXe-)`wxbW|3;Kkwgol@wgxr_wg)x{ zwg@%}wh1;0whA^2whJ~4whT56whcB8whlHAwhuNCwh%TEwh=ZGwh}fIwi7lKwiGrM zwiPxOwiY%Qwih-Swiq@Uwiz}Wwi-4Ywi`Aawj4GcwjDMewjMSgwjX-{_5$n)*c-4% zV6VWQfxQEJ2=)@}DcD=E$6&9)o`byydl2>_>`B<0ut#C9!k&e_3ws#$GVE#C+px!B zufv{)y$^dJ_CoB5*c-7&Vz0!WiMSrd?ENm@QvUj!B>LM z1m6ih6nrW8RPe3fW5L&g&jsHLJ{Wv4_+;?S;G@A;gU<%v4L%%vIrwz&?cn3V*MrXo z-w!?@d_nkx@D1T3!dHaP2;UJtBz#Hul<+O#W5U;j&k5fXJ}7)q_@wYn;iJM=h0hA# zRr;{x%fhFHZwnt6zAk)T_`dLg;S0kjhHnfX8NM=nX86wVq2Wuzr-pA09~-_ld~W#O z@WJ7W!zYJt4j&!9I(&Bc?(pH^%fqLKZx0_IzCL_@`2N5EzyiPozy`nwzzV<&zz)C= zz!Ja|z!tz5z#70Dz#hOLz#_mTz$U;bz$(Bjz%IZrz%sxzz&5}*z&gM@z&^l0z(T-8 zz(&AGz)HYOz)rwWz*4|ez*fLmz*@juz+S*$z+%8;z-GW`z-qv3z;3{Bz;eKJz;?iR zz2_(z>dI>z>>g}z?Q(6z?#6Ez@EUMz@osUz@`$T5>^Ff z1$G671(pS-1-5k&#s$^|<^}cz1_l-eCI&VJMg~>}W(IZ!h6a`frUteK#s<~~<_7i# z1_u@gCI>bLMh8|0W(Rf$h6k1hrU$kM#s}61<_Go%2SDj3kf!n{P)_n^Ay4(sqCV+6 z3w@;jEcDa!&fxI@&6zhl9Qxxlo)>jnki`H8d>y6f56zh-H zV-)L=)@Ky!lh$h#>y_4T6ziAPa}?{D)^`-^o7Q_2>z&qr6ziYtK@|3Y>_Zgxf$T*T z_JZt36!wGcNfh>k>`N5(h3rif_J-_F6!wSgQ55!w>{Ar>iR@Jr_KNIR6!wekSrqn+ z>{}G}jqF_%_Kxgd6!wqoVHEa|>|+%6k+6SMasYST6NUXGdm4p3CHoqMeI7C;J|SeJ6V#g}o>HABFv={UD0{fcA$d z_6OQ8qS!BJ|A=D$p#3C@{ezy{VinpSIB>f!ha!uCJKLs{F^BJ8}fIe@OQ}niNgOOe<%uni2S1{{3G(0qVSi< ze~Q9?B7Z6he~SF8DEuq(x1#X3$p4DM{~~`Z3V)3Jvnc#C^4Fs9*T{d1!ha)wE((8+ z{JSXpJM#CU@b}37i^BgSe=rJvko?0a{6q2=qwp8We~iL^B!4mrf0F#mDEv$EH>2=3 z$^VSP|0I7j3V)RR(d1?Rq|g2{8#d41^ij^Zw35Y@^=ONUGjeg{9p2i1^i+1 zj|Kc=@|OktW%8c|{Aco~1^j99uLb;T^0x*2ZSubb{BQEd1^jXH&jtK*^4A6Yb@JZ@ z{CD!_1^jvP?*;sO^7jS&ee(YW{C~m&0(gM%fdD=rydZ!V2tNpL0E8z5@C4xt0enGt zLjZ3O{t&<)ghvGM2;ma}d_s6d0Iv{!5x_5mX9VyJ;Tr*bLwH93?-2eGz(0hC1n>~y zBLRFwcu4>+5q=WDPlTrg@D$-I0enSxO8{>X{u01ngvSK%7~wMkd`5Up0Iv~#6TokT z=LGN^;X46*M|e*F?-BkJz<-1X1@Iu@Ljin9cu@c^5`GlGkAx=$@Fd|&0ene#Qvh!g z{uIEUghvJNDB)89d`fs#0Iw2$6~M2AX9e&q;adTGOL$iR?-KqMz`ult1@JK8V*z|j zcv%216Mh!J&xEH1@HF9T0enq(TL5np{uaRBgvSN&IN@^vd`@^>0Iw5%7r^g?=LPUQ z;d=pmPk3Jd?-TwP-~i}efCHd10S~6 zH~?y!00%&A72p7@hA=9T~lKyyui1E9GlzyZ))6yN}8 zZVGS!G*<;U0Ghi3901K_0SNY?}ZFK(g-~h-r3vd8rs|7d!vfTn40NHW@4uEXC00%&} zUVsB2+b_TY&|V;W0fP5hV4uE_k0S@hAd?x`8fP5(d4uE_s0S{;H~{jk1vmimwFNi;^1TH(0P@8JH~{j^1vmim)de^J^4$eE z0P^JpH~{kP1vmim^#wQp^8E!k0Kx(S8~|Yh0S{Z~%mT1ULY~LINBB zVIu(!fUuGP2SC_KfCC^bCBOj?wi4g~2x|#&0EE2+H~_+80vrHgGXV~Ou$lk|K-f)y z10XCXzyT1p6W{;{>j`iGg#83K0K$R-8~|ZM0S_6B!s-GX0AY6l z4uG({00%(WUVsB2tS`U;5cU^f08|>-ALUOdd0>Ck2lj_PV1MWb_Q&&p{qcNYf3yeK zAMHD<+6(ND_5=H)KfwOzAFx0A3+#{n1N&n?AM*{^AM@{=nvcN#n4iG@n6JS8n7_dOn9soenBTzunD4;;nE$~3SP#Jd zSRcUtSTDf-SUYSZ~1oSbxC&SdYN|Sf9ZDSg*kTSiivjSkJ)zSl__@ zSnt68SpUHOum`~Yun)lguouAouphwwuqVL&urI*=us6W|us^{5ut&iDuus7LuvftT zuwTIbuxG&juy4Truy?@zuz$e*u!q3@u#dq0u$RF8u%E#Gu&2QOu&==Wu(!beu)o0m zu*bmuu+PB$u-Cx;u;0M`u;;-3uZjR*bjjHu|EL&W4{3Q$NmBAkNpJL zANvciKlU47f9yZN{@9Oz{jom*`(wWX_Q(DO?2r8n*dO~Fus`-YV1Mj?!2Z||f&H;R z0{dgX1op@N3G9#k6xbj8E3iNITVQ|ezrg<3kAeNMKLh(?zXtZl{tfJp{T$dI`#Z2d z_IqG|?Ek?2@CShX;U56|!(RaQhyMWV4}SvKAN~cfKl}|~fA}B3{_sbD{o$Vg`@>%W z_J{uh><@ni*dP84us{4AV1M{O!2a-ufc@bg0sF&W0``ah1ndug3fLe16|g`2Ent86 zU%>wG$AJCep8@;BUjz1s{|4+2e-79m{vEJC{5@cQ_<|AL*dP8hus{53V1M}A!2a;Rf&Jl+1N*~22lj`*4(t#A9oQfKJg`6f zdtiU~`@sJ2|AGC12Y~&74}krF7l8eNAAtRVCxHEdFM$1lH-P=r-1!|uYmo5w}AbD zzkvOL$AJBT&w%}b*MR+j-+=vr=Yaiz?|}V*_kjI@|A7602Z8;84}txG7lHkOAA$XW zCxQKeFM<7mH-Y_uKY{&$M}hr;Pl5e`SAqS3UxEFBXMz2JZ-M=RcY*zZe}Vmhhk^Zp zkAeMxmx29(pMm{>r-A)}uYvu6w}JhEzk&UM$ASHU&w>4c*Ma?k-+}#s=Yjo!?}7b+ z_ksQ8SMdR|3^Ix@kaeL$@d;8lo}u^#`E0a7@e#6ZXrtmQWZTgP#b?OAp^u91kbTD( zC_Y4v4aP|EC35UAhKf&-V~a6Xe2W}=yaUC@$ajNxr1%>7?(hy3pCjKb-m&6)RptKdR8HzuYwgfgs@r%;dz~(6aQQ9KdB*jlkTLqh?_)BTaVAB-8DQz8W zp5i~HErd-}{HU~*u$hWK1@;G@Ds3xltm0dx?S&0ie5|z1u+fUIm9`r;T=BWmw!_9N zzE|3Q>;Z}omU{#C2*nr6y#srQ;*;gxf;~p@&2sO-9;Enaxi?{tQhc@CyRe60FT244(5 znL3}5z8ZWsb$%m#Irwzyd`J3v@cGpFkMsrM6RPte=_|r#ROd(1mxNEL&X=UG37=D) zKS^H{KB+pNlD;Z@R`{;chtw-ZSz=3IOm*HYu_rL7I**pvRAN-^yjo&cU|4mYEwL>yt~&3Q*cTXBorgFOO98?dr9sW9Ds@kliV;k02MDLxnpnu zDxM7ci{zMTzmc3XxM%D?DjrR8)8GJ9yqe^$!2zgvHpy*+15oj9lKTb+pyJ^qHx3R! z#mhu zpyC1L*#I~I6)z~y4!{AZctUx$01iOK8_Kf>Z~!VEQJzhJ15ojb^6UZ}fQo07XB*%E z$lsA?9xDD(o`rw|z}X1=Bl4HznTd*@lxHd6091UXJZk|5pyDs(SqwM;6`v{3YQO=g z_)U410}epNcf#M3XFe+a6aJt)6H@V^@~j9PfQlcLXG!1yRD7vCYXS$L;!ovS6gU8! zO~F6KSrz)z0jPLe zdG-blK*i(AvpH}8DqdHf-GKv8@x1bE4;+As_myXV-~d!SusjJfL}nY0XP7}9)N#9ECM(H z#3q2BK&%2d0K_hUzd$SlH~_>pfZsr@12_Q0K7ju~ECe_J#72N0L97Hg0K)z zzyTnZ1$-7_TfhMz)&+bQVqd@kAQlFE7-D0<0nl3E;L8v@0}cSOG~m+^TLTUNu{Pk_ z5PJg-0I@jW;}Dwz4gj$_;Oo@ycVsLN_&mh+fCE6R5BNUB{(u8OED-oW#0G%_Aneb< z7b12D8~|d8z$YTM2pj-njlee|_6QsRVv)c{A~p#e0AiISUrDh`-~b5wbMTpnZ2|{? zSSRqEhnBg9Rq(%dkF^z zfY>t0FKfRyld)&upAm}&4gj%f;HMF*1`YtRYv8XD%LWdB_BIX<0I_c101*2I{u{Ay z-~bRC2M&O+KL=lq*g0?jh@}Icj@UYI0Eo2%-;UTjZ~%n;IrwsntRc=D z5PJv?0I`TTk3ei9H~_>d;=BT}i{Jnd%ZT#~#5RHhK&&IqI}rN_4gj%`I1fQ=Bsc)X zO5(f(v6J8c5KD>k6vS4713;`L&RfX$k};Tw#RLa{*i3K$h}Fb-4PrOJ0U(wW=Q)V& z1P6dvPn`E4_7fZcVSgDDir7$a0EiXEc@bhq!2uwa6z55ZEd>XFSW}!gA@&p;0Af*b z9);LcZ~)}1a-3Hob`>0ejAbPbfP7ny^DV@>f&)P8E6%?V3kwbav9UNGL#!+~0L0GX z{EU2Q4h{gZwcr2<`*WPPA@&v=0Ag`*9*5XmZ~%za#d#fKcfkQ5mKW!Fi0uUjfLLFg z_mS_WxKcOv!~8~|dWaUP1;Xm9|CmBx7~VyD3YAeI{E zsfeux2S8X$##|%z8t1Qs#W*+s!u}lRvxL<+H~_?Ml_TT^rdvlz>6Bg&-00{eYoX-!KkZOOe_kS&{=`N52>rR20R0J!a7DQY+Jy> z8iN*A60)%Vu!YgzLSU8C7M3$(VQmo$OP{r{`Z)_Lnzyjt1q(}Aw6K~b3oBT*u&xyg z+rDaH&1)7`wr*kEVGX;T*09rM4SU_zu)|{wd%V`L%V!Py2CQNGpfy}IWDVyITf^-m z)^J9^8g2+$!^I(MxNpiDu9&ulvuCW~)`&HnHfs&n%~`{R^VV?Bf;F7HXbo2{S;P6u z)^O*FHJrI>4L7Y>!=>xiu-{<|mpg6YESD|Z;2seN*;_mfui}Of!>9rft1ChftsbHfr90vfv%OLf$ghF1I=qm17+(;1Kg3k;C3c2I9!;`$=@g^_0e8~&G!Q_Riq2z_!;pBz(k>rJpK=MLEFnOUkl)TV4mAp_foxG4e zlf2LxNnS{sO|%0j9qWuexavarLKvd}%4vaoX~Wg%}kWuapvWno(&WuY;cvQQFAS?Hfi zS*V;&S;(15S!j!-ETqq-EY#1XEELVBEc7m>EYvKeEEFuKEOf1;ENov*S!iBMStwgi zS>O(b+wF9?oi2yl>v6a}UWeP|bGUtj4tLd%!<{?qaJP>*+!+CfyCLXs7l$0~zA1;h zV%p)(o^iNaBMx`ktixS5=WrL!JKQ~s4tMpE!=1nEaCfda+?lHmchj1~UApdY`yHw7 za%ZYL%a!VG@ua$Iy{YaUzEpSjV5)oPP^vp`IMv-TlIq?TNOd;`Q{5$@RCoVWs=IPJ z)txhw>TZjqy3=P<-Su;+?xOirckg1VyJjiXU9g<$?pjH8Z(mJyH?O6-%hprf+>sV> zJJTXgS6amDNsD;AX%Uw%E#ezYi&PDzMRJGJBJCq-k&HlEq#>9VDGsGY`liw%71L>v z?3uJk>ug%2ZZ0iSIG+~jSxk#mFQrBDm(wDhD`}C;)wD>{T3V!ZJuTvQq({n~>5(i~ zdZfjZ9;x-FM|SwqBi)1Pk)1>7k-XvbNXJNeWLqFT(ilvSl!VeF{Zr|Y%IWk-&P;lw zZ8kkpKbIaUnop1PE~ZCnmeL~y%juD>mGsE=)$~a7T6&~xJw3u586$3I#)#9EG2-=P zjCi~mBQ9UYh;J}sq-rQ*BzHJtq&<)^(h$rTDGp_f^i5@qR7_`#WY1)bw9aOX)Xim# z6wYUi^ekqKR4-+W_9BRMnMM%re#jnvO=8!4LK zHqyJeZKP&t+epFkwvn!tZ6n)Pw~aKfZ5t_D-!{S>nJaE*=8Dsmx#IO?u6VqeD=uH= zif=G;rD`a1C3iS;r9F_j(h$sCDGp_>^i5^1R7_{CWY1)-w9aO()XinC6wYU^^ekqs zR4-+&l&)v4_#N9<%AMO+vRvC&T0GlVYQ5W6cKEihbPsM{**Ua* zC2x59N=IP(N@H;QN=az@O8?aMmCEVuD>*aUSK4N`uhh?NUn!d3zS6t6eWhk;`%1y` z_LZ*H?JLb|+gHlgx36%A)9H3OonDXA>G3+9E}zrs8+1CWhMdmaVW+b_;B+zwC5&t~#AfYffkBy3^@*WI4-S zSFJ?-*kPx}V5 zr>lmtr*nt1r`rSB(+$Dw>EclKbl+6=bj3{ebn9&PblqI`bm4sVbkAb;boEm9bpCSo zbmwaJbkkb)bm@BbwBM04UGB=6Zt>(y*LriNcldIqy9aZocMj!D=MCpfcLZ{#8-qF1 zC83<@{;8bl%9)($w%MHN`njCxqWPTZ-o>2hnx&lSg5{j)uGO6B=Cz#Zvh|#4?#LZ- zyK;xTp4=giH+RV8%N_C!<_=X2=MJ?8a)%m%xkJUF+@Zdy+@Xq@+@aRl+@ZR;+@Zqx z+@YSu+@b2F+@bvC+@a3Z+@Yqm+@aF-+#$asZ>ZdrH`L;o@4ejvd4RsIZ4ecDx z8|nz;4K)VyhDt(tL;X{ELzOdmLv6EpL-licLq+p>L%oZ6Lp4izLj}uuLtU$RL(OY> zLuKoEL)?+S-kH5N5N9Lt6-_cQ?OL)Em+#&D_H6t zELhq(T(Hy;C|GI?7A%#73YPk(3YIEo3YOYt3zq8V3YLoI3zm8p3zlk@3zoW83znMK z3YN;&3zoRU<#oGUUa!aH_4r&~-=ND|HSF@X2VCBUpvzkva(VlvT;7Tqm$!A+<*l1@ zc?;)V-kwF5w|d#-?Ob(vo7P<3(sh^D@7UojckS@Dcy@SeeLK9}gFC!Chj(~80z15o z!5!X`&<=0^)DCau%nonc><(}J+zxNi{0?vL;tp@k@(yp;>JD%7+755o`VKF56wbL_ zg>zm{;he`;IOiKIoU0lxoNEsh&NT!J=ZZsxbA3~Va}_g%bFH(5b9M8Db3KcNbJfd* zbDgV&b4_c7bEWHrbACtBT)C@guEkR{SL-X9>mDqc+c{h`*AXb1YYZ06m4u4s`lpKK zDrbu3+GdO9>gS8*dKZi4YL<)Ux>k$kn%9cv%GQhKxT84eb`=M`p5ma#R~+;W76+?_ zi-YZf;$TClIM_E;9ITir4z|t~2kYjGgFTDI!RqDWVCQOauxYJ0Sh`*u^gBv|<*t%o zi>D-5>njO%50(UX4wnQw0wux5P)V?Vsw7xBQxa^OEeY1omjrtkOM*4aCBd%Ml3?>% zNw93aB*-15Yi?KRn%7gh=JA!T`36hZs)kF~+5@F)4WZJtzNyl+ikZ^2*4fgvy7|(z zp2gC&>gCe4&ehVjruEV_zoTre+*P*L;wf9J^_8u450UK1(yB&U4xueBX?x^*ZJGuwU9Xp519UXyk zM`Nhm(LYu0sGKQxw9S?~>gUTHy^H0Jn&omw*J`<=dA;1hT@_PaPsNnSS25)qteC1A zu9#{MR7^F5DyI5oDyCXzE2iq^E2erDE2gTKE2cVEE2f&(E2jLe%BdDlIaNPjIn}#ZIaRY*lKldlst(tCy<=J6Ed)o7Sra{jQyZEuNi&wZ5H$ z-NQQvI|4fg8$&w>`)76zw$1Jwte@XG*t@uMux5GZVAtx-!RGaygWOfU==D@DdVJN3 zzTxV{_CWPwL#TSOZ>D;&b+&r3ZoYc4XSsT@bG3T0X}x;U@2XjB@zgBV`f3)thieu) z0yT?`p_;}1nVQA6*_y@r`I^Pv<(kE=)tbfT^_oTQ@_4*HkHLSs zw9a}wb@Lui&$7qUx$5yWt$RFvSFNYTSL^8>uJv>TYCVmiT2KE>t*33a)>A)U>*-yt z^>nS)dYad3J=|3{>-E*m`iARf+XHp84WYW(zL~n&*7>^Gp5?mP&egivruDj6zpH+> z#aBPuJzPKA5vZSS4Asx}&(zPh&DYQNF4xa?t=7*ruh-9VS3|(-YY6y;8v^a2hCts; zL!foOA<(nj5a?WO2sEuX1pKbXK#Q+2&^_E3=m<3i`ezygZS#$R-sQ$X*J@*+dA%{f zT}`WAU(>2@xM{UL)U?_+)3n+;-?ZAZ+_c)c-n8m>HLte#npeArn^!wR&8z)0&8uzm z&8xl3&8uDO&8yt!b@_(9uJ(}E)i>jHwa$B8Jx^%>b*4SkI@34bI@7bAeLU1N-?!c~ z?+^9P_pkTP^Yy-vf4x7%-+c4UGmJib?|bj+n_qYJeer_ZuXyS;@26&t-171(#TP$# z@}3*<#Xa&+1{uhr4(dY3lNYD_66r7Z*q=lBj+~d~A%F0`yFQKjHy!%WN1)@$q3C;{ zVr0*nm@iCYLU777!;Fh&0?(KK-kGmIUG5YI46{|w?BaSii~ zO)e1Mu*lfuOT;-WGj@1|c!yQS_N)>2u+G?NW?@!`ggLw#UM*@mg4` z&%%xmSXkPiggNu!SX0S=d{rEv$OR!VX3(EPvL* z-Zp1po%0rU`+|jKE?U@?OY|?j}wXnCZS(ty_!tQoh*#%B3D|cDhsN2f2 zJXUtK*UDOaR(9Kfm8A|^*(F0(Ry%BE<0DqKBVc7W1g)$)WM%&!Q)dG1Hd@_%-(7dt z-F0_mS9T>gi;~Ou$Qy3mAD7rLX>gq4Emy3oFSU1)isE_Ab47aA|s zg-)02Lg7kXXojngXncJ{6zU_ESRdh~`iLRdM`Wcw;%M~|POp#XMtwvw>m#;R9}(>O zi0RZv6t_O&M(ZP6V)c=^@%qU5M17<;Ssyu+s*kKn*GKMV>mzNs`pE8lePl_YK60&C z9~mjtM^2XOBa@Z-$P=z1vWahq%oZ9VXT^p{x6}|hAU8x-Dh-j_T0^8oZ;0$P8X}9# zhR7AGAu?n)M2PES=EoZ%7ZVMU{$xYsNU9;SCfyLZpKXYA zD*L*yCP7}>}-MrH|(kuzdrq)Tdy?3WuOE0o5_ zEv+%qtT#q>7>$vIW@F^C)fgGH8zaY@#>hIiG4e3l7}*+YjLeHSMlK{8BYnxn$l+9D zWOceRaxdE$Y0ouA_T(EQOAC#W>&3>%XsI!Bs@xcvsx(HPa!rxVd{bnO&=ff*Hbr`* zrpQ6LDKeonMeb-#kygDavdd_SEH;}WSFNVVu-z0n;WR}yxJ{AA(Wc1uSW{#{yeV=i z(G(d-Hbsu6nj&k{O_2xLrbuV5DY7r$6j@$qirg$VMaD}_k<;a-NVw7znc+B1<2g+f zIL#6{jh8shkU33OIL*;HO*c4AGC9q*I8CrQ&2%_TaXHP6a@v*{r_GIX+W7>h^(Hy( zP>R!5r8(_xmebmDoVGj9X-f*6cCE;1BPC8dS?09K3a35cnzc=Qvo>33*3OE}TDR1! z9gv%~l}fXATWi)@^k!|R(X1^po3$%evo>TmYsZ~tZN1y9J&HDK+hWby{CKl=G108` zC!4h+sb+0Wx>>uQZPq$+&D!34v$m|ztlcO!Yh$HmZMxj7sg-8!8P}q1)A7Md;EWvfLSv|F@ePK&nAZP6Y^TePjQ7HwXR(7hAN^Qj2z~+@eiYTC}HJtG1bM)#eDT z+BvaR>ycWugL11jp|omu^j2+`(W)&rTeYiJt2S)6YA2jlZG+pYJ&v|&+heWTf_STT zDbcD8BwMwksa9=mx>b9SZPhw+t=hhPtG2w*s@*KMYU8C=?R2?S3s+jT8Llm>@oiaA zXv- zqAlB-Y|9=>wPjbO+p>3aZQ0%Vw(OEZTlQM9EjvBfBTxkzHEo$X+jYWJgOK*;D0?>{O*A`;_a< zZst3)bA-<9Ik7X_BXwpE%AMH>r89d+@67HpI*d>mYy2R;nm#9{{#AjT$xRLJ`X9?Zn8L3;`FL#S8 zly32s-YxDhy2XWNw|Lp=76IO-Qu2nx45*>EnY8ni=(A(@l?56oT_w-Pq`j(Gv6c55qiXPQjd60?hz-H9`TOe zBknSK#KmThc-86=hwUEmgwrE#aC^kZ(H?PotVdiB?-4I0dc=Wbk9aiIBd$&Nh!1i- z;=X*3xV+FK-YoWr`fd>^(I!OdlPqay@}oV-o%nZZ{k|9 zH!)J`O`I(ECMGMri6>lNViVt&m@V`r&PsiW19D$trP7zUt@kB%8hwdHW?$lp)t4Bu z`x3{UzQlUBFYzeam)I8TOU#e=B`zlV68*`(#F12AVoka)aX;6W*qiT5EGzUSZWQ|x zW2L^tbh$5~R{9dpxc|UMx!zEJGG7SrIHp7cAWnEXfos+ZHU-5iG?OEH^4xTVjGWH!fJ`lY(_9 zC0MJ{f^|11SiAFrwWJ_e*NTEQQWC6_Wx<-P2-XvB(AvZgTC;^g>#Q_r9gqjDmCB%X zTOYJ`8iUp%bI`hC4O&C?pmp3CwAQqIceBBC=Xi`%CL1uAGUTG!`5PR*t%*DTPK`hYlAy% zJ&q1r+hfDlg7~m?DLHH%O$}RX)5F$-+_1GTKWr^83|lvg!`66d*g9Pvw!)QRYla&s zYWzsi@ADKbX{2b#BSl#mDLVQ{Q8z}4k~vbe?UADCj1(1jr07ORid$kM#kuj3;`!uA z@la}{xGFtTyqg;-?#_=CmlQ^d*GePBljV`(WM!oIgc~hx;zx_Kh0)?!X|#Ai9xbj^ zMvJ%g(c(^Hw7AF|Encxli^rYO;(B+q_$WGB+!h-x&X124FD6HeM^dB3HR;jf{oH7A zZ+^76tT0-R^C;$y`N$+6<$)L3zKdaQUaH&)z}A1f{`j1{k! z#)_xPW5ub;Sn(-0Ufj%&7v~7$#dFel@t{0joKVJ#cl7b%E@Qm7*c>ljwa1GmobloY zcf9yGI$qo!8!s-1j~6c`$BRc(3&%`MGhCKc5u&Ln)D8l@|HC zIg#I;7x^Uxk-t_F`IBXlpR9=d6K)p2iJ!&K7H08hrCIy|c^1D?nZ@7MXYo6YS^Oe% z7JtQ_#UFQO@$21L{G;eBep_r7KR-T;znGlGA4$#P*Q96h_j9xOz4=-EvcfF>Mrjs5 zU7p3Om0A2VZZ^MBn9ZM&X7l^y+58G+Hh)W>&F?T~^9#+{{AGJKf6ST9uXAVf52LgB zt+Cnsy!dSXLUJ~LI5nGJou19#%gyHZL@5W0o{GX2^46vNAX3=yPMbF*hce zb7QtWH)c9>V~RUB=0@knw#4Vg&L`)_4yESCR;B00?&jvkcIW5DmK5g3u9fD-PL}7! zCM$DePq=xpO~Sm`S!rJEfIKg@QkfUKt-?0K={&b-)qcV6sKbY5&* zY+h`Bd|vEga$f96YF=zjdS2{)ZeDC}eqL-@VP5P;XAKPKfk1aIk$1dCRW5=BNv32hJ*u&`j*w*;`*oEZ$*x}Ut*y{BB z*uC8R*q;3S*wVuM*!9x<*s1dT*i>bH>?yY(wpmyZJ0~rO9h4WuCX@xSJNkmyE@MG# zvAH02)m{)g;Vg)4a2LcLM;FAl#}~vdB^ShwrWVB3rWeE>GAv0l3|TV#o}A(6lA)WDVcU{nI+CHdlHo=rV@q5z&L<_~P)agZ zr6uETPBM1qC1XiJGOm>*<78PfCM%Nhgj;BA5*8X~rG>@;d7-gVS!mqW7aBW_g~lRt zp>f4tXdHJI8tdJK#-r#$V_SToaWT2jIFedutVu64?&lU7d-Ds8Wrc;tjnYD6y1dX( zD+`Th+#+M6u*f(gEi(4Yi;NY@BIB06$k<^nGA`STjAPCsW1YLmcoh86E+iKj zhf|A;)#*jXz1$*WPkxcHw6MsyURq?FDlamoDvOM#++t(1u-G^!EjA9yi;W3ov2jOV zZ0s@@8&~bc#tCP!vB6zzJdQ3lw#OG6my(N(qp8Kl+Vo=ML2j|JFTdDWURZ40EG;%p zmlqr1%3@=NTawp=C3#C)k~icfdB1;{cl0HB-CUBl?In5BS&~=WC3!cxB)=uTB!51+ zB!4KiB)=-XB!4%zB)_|`B!8{6B!9BJBtKbMl7GT2&2JKx=Fdt?^9SUm`IXAj{B3<{ zey6!Kf5l#!Kkh8euXmT`A4Qkux5by{FD94fkEE97*QA%`@8_20_vV-8mlc-gZPU6y|sU6$V( zUzWd+T$VqaT9#j(UY5U?TbAEbSeCzDT9!XmUY4J#EXzOTmghGM%k$@?<@tm1^8AFd zJby=Dp5J9I&tJ8d=TA7x^Bdgd`Nz@a`R(!L`Af;=`J<`j`L*fg`3Je>`F(}u`J1KX z`P1d)`EX@r9x5Zb;7n3XGBdHbgn)C|!er|=lx3EIKQCcBSmsiMYWrh5VTPbf8R?26j zmGXXNrF=_YDeo{>%9rhx@-b(nyv|)IKa8%Fx5ih>7m_RG!>N_>>hwzaUT&qlr?67K zURo)iDzB8MDl6ru+=RSYn2^s&6Y@c2LcXI<$h*u5`Kmo3pKvDR4eo^eI65J3k59;# zk`waL)P%e?Jt05HP00HS6Y|Z{gnYU@A%`my@(i~sr3tH2mb5BmD63MAzAB}gt5UYT zDrGvWQhr}Ix;4y9M6?&emdb{AHqu9a4$PL@}tCM&B_Pq@{oO~UHb zS!s3ZfU-JuTVI{pX|7IPu~(;#JF8Rc-PNf_(bcJK@ztq|$D8(Gxz(w? zh1IDWrPZnF^6HdYS)F>utx0VZ)}+ozYf}4_HK|+rn$!++P3p3}CUwkNlUnDlNj;3N zNo|d;NgYnFN!`n>N$n}DNnJ0kNu4UMNljJOq@HqXQ=5ggsdLiW)Inu!>W;oP zwaZ+ax@xaYop9EsHn?k3kE3f-+v96fmy&B!N7HLl4{~c$`wDAQH%n_%r^{sC zvZ6RoxOL7ZVV!eUTIU>4);YKJbJTH%jZA>GC>9t*mpNaqFFp!g}Y7wBFgTtaond>zy6udgrpe-Z|#3cOFL9 zJ6q%HoeRnJ&f)ZW=U#5Tv!}4$xn5fDoGPz(rYh^5r`!f-v#`NACv9*JDjS?T`UYp0 zxxu+=Z*Wey8=S|{4bJxX2Io?8gL5>!!FiC|;Or}GaBh}1IH$|L7qzm%nc*hOnlM?m zq{*_OOqLyevaFkvW!s)Co9<-UjZT)g#3#$=lau8`>B;il++=xoVX}O!G+91bnJhoy zrplXysq$HAs(e71D&N+p$~(=e@)dikeB7NXKZ;J3x5cN*7n4)vBk8H~{oGV}Z(*u@ zqcl~XE>D&H{(t!yr88OX2eAO1L~DXq+W!oS|r(qidXQYMgCroat(u8`Zciag95l z)VM=wjk}xExZMSfyH?V;lNF77!foU>2^+by(njupvXQ&3Z{&8G8@Vg?M(((~k$V)~ z$Zd;nV< zcN6z8x{2Ew-^5)=ZsHE7H*xoJo47rNP2Ba;Chk;a6Zcfu%$<`qa|e~p+#P*0x69nj zU9~rJC)~~4Mk$Zh8K6*hA>OPjgVmCf9YuqA3qTcU=tCFyYTH|)rn@ET#Z;f6|ZjByEZ;js1ZH?|NY>nP1ZH-P>wnm=`+oETr zZPES8w&*Q=TXcuHEqdAB7Cq)}i$08Ri(W`>iylsIi{8s^i|#3Gi(W5ni=L`%i#`>$ zN6$&yqX(7k(L4I~=q_`6^s2o*dcxfveH`B&y_DP@J(}JgeURH8-B;Kiy;<5GJzd!z zoe^~1l62irblov^-L`ezbama0>-zbmt{+P4`rVwa?=I;2wUVx%tmyg^VTXQJ+Myp% zcIdbD9r{jlhknK0p&xg5=#Sz%^oz+I`jPYw{eEtTzPGSLzfszuPgi#6&xD=&8EL1! zU)ibOGI#2i?Vb8Dcc=a^zEi)D+^HW<@6_+*cItZyJN4_Oo%*TDPW`E{OFt*=(hn-T z^gHG*{i?l7KjH4uAIEp;my)~mqv>7xgWN8CUtyPiv$RV;UD>722)lEZv^!@gyK|1Y zJ7?RwbEdmH=f-#E&L?;04yAYJ?iP0Eu9bG@PF8m3o(Ow#XQe&41InJ)lHQZMpWBn$TiBDkQQDK6uI$M@6ZYoLNPBbpmA$!J=HA?8dvETT zyEpeRzBhLvxi@z>y*GESus3(Tv^RIEvN!is*q1ve?aLih_T}!F`*K(9eYq3vzTD&Z zzTBnczTDCDzTAVtzTC~yzTD}`zTAvpNS0zqj%i4?ZAhkTNN(Ja&L<7&P}-3077XcH z$&gM~4C#rmUpg!8mkucVrQ7Cy>59EyI_~b59>w=d7nA#?BkBFp{lb3fMrpq^UD+=^ z6AnmclmpT&^MG{OJ|G=)4@eK=2c!$h1JdF20qI`hfONfdKsr@9AUzchO6Qb=(jD`l zbk#m6op29IkK+fWOUZ-M(ey#-LE)fuvvg28T{$St2#1oEawzGThmy8^C~3Nfl5YG^ z@_hPG@^0Z!@>=Oo@?_;u@`-Rbc~&``yloy%Ua=1+kGqGHkK%`u7n6sRN79Fr_X~%U zH%f<-)0M-?XTp)>8RbawmU$$3**=my<{n8tj2}r}NFPbwD;!B)FC9sqsvJo^6^1gtF>30+dO7pv5(ou-DCEn_%Zup`j~ycaLm3@I%ZE-j@i$I z&nYMDJLU=ds(ZqI96w=S zN}sSF6i(PTODF8pl@s=iaI$16CrgfbvShm_OK$vR>3sTR>2Bd<>00Gv>4|WvbXGZ4 zx^12+U2#v99>q_UE~ZbF?iWs#Zj?@yrYomP&xGmH8D+Y3%bYGFLtF z!gT3+WxDiKI9)oYoG#rlPnWK`r%R9Hr%RX8r%MkCr%N|0r%N-6B{-%f*sdkGaZ5O# zwuHL{OSo3CgeSro;jD5-xNV*huDEA}NAWYl#q=5Be&LL8qjE-grkoXSnP-K|?pfhs z{H$;xeO9EtDKKNQ7*)9n-}6&+zatX@eA>b=?n4ug$wZ;l?(A_%EkCC^J4t6dolhn zeKCHoa4~+paxwl?xfH)+UW#9JFU23HFU21eF2!$FF2!dQ+jLypbknwZw_uysDz^DV zxoqAxFPm4~%jTo>W%GXFvU#I&*?gv4F>kq7%!lbK=Dord^Lpiq`Bb@T-f^#*kJDGp z2ZgKV&B|4CM!8mS+-n6leXVe}a;@-0xn8*KUN1aKUoYG*Trb?HTrWIRZWM00Hwq8a zHwyPEHwsUcn}s{>&BEjK&BBAq&BBc9C~n$O?p7S-iE>N1?cP!zrEe+sE4P$q?rr5^ z`nGbfa$9-o-ccT>?Bp4^ z>6wb_K5-wqk17w{XO&0p)5>Fart-AnPiBR`B9LK#96Mw=fawUC7GPUKwg>XPkZ}Um zDP+CEkom&gV;J*)z`GexD$(PPu(9q=k6j!XWtb7e#+gqvX$Hd@-LfTVsTx zAv2T zv1;U+gg=L|SmV?rYuuVrO}eJ+Piuw0*t`T_C_)C(1jv2>0}`?zz=R9~8`9?`Kvo2J36LEDUIJuE zfGG*t5@1Y1)&!W7FfRcZl#oRMCM9H3fKdrq6<}6Eb_E!gkY$;IObf6rA>)F)gfOr# zAp?WF1jxn!BQto;ke2{i8enQdwgwoRkhKBkCS-4>AcKRv1jyz9qZ6_^Y+eV=??7Gx zWP5<|30WUtenR#K7@&{^0$u`SgH*@}`B@=ghC+4-7^09RQXx}>yadP^0do|xM=E5H zke2}2Bw&<6RtcD;kX-_XDP);|X$sjUV4OnM37DsleF9zrWTAkU0NE&Dqz3O7@)96R z1-t~vRsmxbvR1%ch3pkDSRsq0LM97&36RxNA+v?N1jup$(-pE^DrCHnmjKx>^&el% zO8_P;WW#_F3t2H>#zJ-s7_yKh16~5mO8{O1WX)8_oB?|lGHA$4fNUBtY9XtpLS_wl z36Nz2rY&UKRLHmi>lQL^$V-4M9Pkn#8>d1>j@A|AB|w%An7WXy1I8|7?NrFzAuj>4 zc)&}5Y##6uAgc$w1jz0I!xyrA!1RS|A25C)>j%tV$o>HX7_xxC1cq!NFoGc~=;spH zyaZqfLzWPj!jLTl#xP_JfjJD>LlrWJz#@iBBJvU-s|d_u$Swje0kVw1OMq-6FpeSX z2+U*1J^}+7vXH<;hHND85`y&=egBr4^z@!cXn;J5z$V&(VyBg;u0Mi<>ttw<(k(U73R~0g_$V-51EbtP7 zeFS+4kfjBtHe_pou?<;UU~WV978u-+#RVoeWOG%>=pruxvb(_WhAc1e5+K_PyadSl z0xtowzrX;8EHE&^AsZZqj4-gmAv27;1jrHtQyj9zVaON*YaHh#gdu|rEON*sBQF86 z%D^m#>@qOSA{51Dl2B|ugknDvld2ZlXl*@0;f*>>P1 zK-L|Y_mF)D27VZM36PBkUP4ee06QNt^vFwqY&|gcA!`rJeaPMegCDZ^VaVhIn;$az z$V-6iKJXGC%MVO{$o2y-0kZzU{DgPpk(a=} z3w$T!B>)?OeP`q)uxkO=1bGSUTER6#UIM$8a7~eyz^*l1bL1tkdja z0=t)RPm!0v?ls(VsuPiy0P_;qGlIMX_Uz!i1oliJFM&O4@XR4E0p=yJXA*e{>{*3p z7I_KmS%zmCc?mEtfj#rcOJMH;yc5VvVDAdNGssJTc?s;DLS6!U*WjH)UIKd;;hjWY z0()0|UIKe}ab5y@r;(QsMqUD|ouNiWUIJSiV2wat0$V#^4MAQ4TU%g_L0$q|dtePh zUIJU2V2wgv0$aOa4MSc6TialbLtX+~`(O=3UIJSiVU0vy0$V#_4Mko8%u8TvEUdM# z<{~eFt;Mh=BQJri)v#tGFM+M)u%;s~0oXXeOJHXRsLhd=0P_;q9)Y|Bn3urz5acDW zy#?nbusz3TC9*vTc?oQ9f;|d(32g6zJq&pXzye}>9P$#_-UoXi@)FqI2zw;#m9S?b zFM;i)u%{v~f$g=h=OQnG?ZvPsBQJsN)v#wHFM;jlu%{z0K}B9da2`Tl0;>(6MnGNy zs~w<*Kwbi?Euh9gUIMEyaaZJL|y_rTf!L=c?s<731?8`C9tz8 z&P!ltR^%nHvn-rxk(a>Ex^U)2UIIG{!z3V0m&ys=q{I4^#3vzM3GqvaXF_}v;++uxgm@^#N1^@}@l%MWLVOimKLY*=@mPq@LcA7Sj{=?x z@m+}b0%w2VzYq_G_%OtaA$|<;WQZ?Aycy!p5RZoVG{mbRehu+#h;Ku@8{*#(4~O_T z)Yl_^4)Jt|uS2{Y;_ncThxk0i>mhy*@qCEyL%bi{&jKD0@qvgJMEoE)`vXr1_sf7c zMEoJ*5fPt=ctyl7BAyZPjfi(d{3GHa5g&>AnZ!>bo)Vn>fv-foB{=&7e~EZZ#AhO2 z6Y-mf=R|xb;yqzK6Y!vj4@JBv;ztoriuh8*nJ~_;kdpBYqw6 z?1*niygTCG5f6{}c+|Hiejf4kh_6SyJ>u^XkB|6##Oot|AMyN%?}z8tfd5B4K;i=u zFOc|wcs>sJg2Wpn{vh!PiBCwpLgE(^&ye_r#5*MZA@LCLydUrqu^-?OPZ9eC9`+9c z{vz=hvELBz8nGV{@EoyU5%3H*bfPKlGrcth&M_6N#aowpOSc$ z*pCT#me{Wec$e7E33!;;@9{{dA$}(DG_hX<^Aey35b!s#zZCE}vHukCJF!0%@IA4A z74Sc?zZLL7vHunDLy0Gf{jz{JO8immuLXQk?7w-$FU9^`z&FMIUBExZ{$9XGC4Gwc zsn{P3_^Q}H4EU?qU-XF2iv7oc--`XofbWX^%Ygri{Y{Vfu-N|$__5d@^@uM^yjkMU zVt+N@(-N;1`>_Gf7W=gU?-u*HFfRdm03PviNtYvjF7b4+UmWmuv7a39c(LCc@OrTy z?Geux`_(Wn0eS!)@qdX2jQwtymjFG0fFF$gagX@I*gp^W!`NRB_{7+M5BSB{pAY!P z*uM|>$JpNw_{gM35FUW#TatpBeRsfZvSzM8J1O{UYE$qrMUFp;7+` z_|d431bk`KPXhil>MH@C8ub^Lm%#YdsLup^Yt(N7{x#}50Uw)mSmI}+J{0h^Q9la! z+o&&j#OFr+$s>L@@w`#5@=(7D_}{2+d8l^5A{!&mjFEg5B1T2FOT}Ehk9zjqes0p;MJoZ8}RH=uMK$jsOJVeeB$Gi z?v8qJz|%*)INhJ_phC8Hkq8KeT=Jq2qH8U7vXv@%;(WP^c>w3N^<=p}|Bb)Q}8?`ck1# zdpZ;v&4xmCxlpJl9}2Y=LZRVeDAZI6g$Bx@P-i6+8s};vJYN&xgqnyT)7?Zml*Jt<}0>wOVt$RvS#zY7NO+ ztuIxpwWn*f(QK_&m#fu!^0iuPp;j9%)@n_qT5X_Qt94dtwQ;U4%kyTYVqLag zs>}Aub=fwhE<2*vWxI{KY>Qc!9kS}OjdoqO->J)XxOLgFXkE4|R+nv#*JTG2b=ihw zUA8Y(mu*kiWk+*$*`9n|wzW`~9WK^on@V-rfpT58vr?BG=juhCuNOI?UKFHyu~)7a z+mw27M6VaSje4=gtQUu@da=>27yF%hvBRww$D;LOSFB!aj@OHWiF&aiSuggb>c#eS zy*Qey7kl#cVr!vZ94^+2O{IEqpj&f^radS?dgWZXs#jAlW$10 z78(-6#fC&vsUa~?Zb)=i8WQ7Nqs8-$7AG`Xg4AgB%8gc=(rAt7jaIkOXtkJ)){xz3 z^*fDLhudh4MH{WISfkY(Z?p!JjaFZ((P~dOTBEr}t0&)RwH6w!;bNoJRBE&a%8gcM zrO_JanuIenrkt7@-0Sdp~V<3 zwHO2C7NfJ$VvKXGd0uGE3sP&oS8mO>DXsYty*1x$w&sWI)_lLyn(uI1^JCH0d{?|R zKbUOI_oZ6%?djJ1Xs$KiQ)tZ(ms;}!<<@*>r8Pg!waGr4P!^;%xmRhENAxzi+ia7E z>^8aIX_GtLHhC=CCU?c#+$MKc+T?MrJ;e*{ zDM4ya^(yVD5xqUtZMLWUOn<81X-{>y?WwV7d#Wqmo*GQHr~1~Q+h9nNU3 z!|5q>IK!n5XQ15SbXGc?ajvt>3!P;_>MZvvo#hd|v)pZVmWS-la=+VI9*cICyW*YY z!DMH-FWp%l&2^T03Z3QQQfGOf(perCcutUbu2H&EfZaiJ?JNL|rhr7Jq3cSXC+uBe}jkM_G=(Xn_}bTHW! z?Mrt>M{`}#oGGty7gYATOTpI^&z`k?{~ZPv3R#WnC#a3(%t%K zu3PUZbnC;VZhfHAt&a;mIYH{l^(sBN5wj;ZWcTFy-JaZ7yeBu9?8)_|dvc?Np4@P$ zCpS>($&CxWlF#ImM$BGm$nKT;-Ck)d-YX3zd!@c~uQXcdm4-{b(m)wBM8Z7Ctv=*RiB@-?xo2;`f=6oH*)-g zla(J-eSg3G=u?v)`Cirk_u=3A@?`qkjN#0DfJ;B|y~)Mjtoi|Cuh&h5{*^JGnU;}$ z%ulU-t?Cbqwv0~wpD!>*G}AtQ9A7x~>MK>h;7{kTnOfvkeS`1#*ruuPe7x!({L_v5 zrrQ6g>Lc9!`4dy`cz@MTc=otG<-VutEByAi?oNIBrK-R1S~@ay{aMv#_^zM*^3>y7 zRlnhtO>die{an>|_#eOg&MEJ3)qmLXx!;`n(YC4&@e3V^skg1I`Vr*=AD(*4f~qfZ z@w@+M>YM#lf8r-!`{>l~HOvG)#jg(j)zm9Ltojw-=8qQK{dLClW?I$XzV~mYR(-ze zU;O2-er{^!6N~}Qw5{CeKTIwCFk^!=&FfcA6{e=%QS~)`=Dq(q^=FT({>JgByvzvHr_|1~wemNChh?{Uey{%2}>yy}1a_59DKKHd0?X>y>=Eo-b* zqu+g@)qy7R={XJRN59CJ=S<6M*vP5cUse5)KRnf{%I~ZCB!Bf$hx$uzs`@2geNUG< zb+PK3{OCt})nhxV{>iD&52%I3RUhTmZx5-TYOne!mHIKY?)z0=<%h;*sekeX#&TyG zHPB^V&DosiIf)XZHPMQa$)vRiEY#UQ@qwx9Znyn!j27kG)mj z=AI4PR9&k2Hw9yd+EMeEX}X~0Tsps7UH?yvjn6b+#oecVE>-n){>rZ&P+xva)!%8p z@31;DUG;hXUdmLzI#Km|UitJ1wZ6IP`%HduT7Ab?8LOZ9KTm%1jQWdzR`r4Y@{i7| zUwJcQ`!mgYcD=3s*3qgjba~HJ)mvEghyLNL8|uzCm`22WqVHOMOWp7)n;pP3@zUg7 z^_}mn`bIyz5%qswtNKcJe)1R8{U56O zOJ{4psP^2h`b_`eGjCQW)vDk0Yx*y%uQopje5WtJ`WE#wU#j{~4dYkTxxZWWp}zFR zm(P!7;;ce=l|AftAU><{&Cw@)+^G{cOs{B`D>c~rMb_4Sy zyleW`)$bZr->Ubucd82ps{YltS?^Z=?kj8t1oJk8zWyHd%kO8iA(-c(|4dxnak1)a z{e1B^)dh>H{?-N7Z>u-H%Vtb4?}YfZ_p0M5HhY43D$=Lkr>?tQ^}T-YUw&83OjP}^ zpFZ|}^^bnUW>_$9#>8tMQ0qTl^}~h_{hs>D-KsD4Tlo*EKboleW9RMpi2Bwauo)T5 z`|!+%|+N&S=Gxd^C_1Bu>pR33Jq3W~!$N0z8^siR^w*Sumh5CzIs=nJdNB>g& z#826*5axmT=+D#YsgG5CxHs;9LcM;q>c{#!rzq~uE{$OL(udBcOvO4$2Y^DkG?QU89*XrN=e$~I5OMXWE(n&T0g?W4aVfb%V zqw`we=RN!OSJVwJSAD$?LVu^e`*zje%isR2Iz6ZA^Ih_d&#CYJV%6{a*@J(tPX1!m z_xqi{{=9l%W!3-t(nMZ;t;lA$FmKWyeBl46ufDzN2iCj3sIHu>`hw5Td`WHkHk$>* zJWfA*{mbg^cUOJFJ;z^D>o!*X!XNzGg1YE+HdBUqrT%#3KdUdlhs~N{9;y}Z`xo`I zTGdCqtof_z*6+OVT7jncfjj@I%I{<|YnT`7ZD0MG`t}WMmJRc0eQ(>>)#-1r88^(k z^_f5YH#PB6)oihq;>Pwaf|5JVUm8w5^*0a~upSGV1e9Do3`>y(0s_IwXz3uzz{DW+! z5A&-1((jkm@BE0(`e7cng>64jXTRr#rwz1B<;D-y{2DeJhbt6b>6O1(8-Dw;s&BfowJw}~rRtx){)4*kajWX1e#iUj!}ls|HWTw4p556H zZjM!b)&KV24dMO;ReyEI`y0dWea>b)G4En&S5x@C2djSTn?G&}4}6==gkoOD_b0e; z>ocakG7sd;&gSsL?y3*F`A5y+b04nyv8R5gCH%^|sxNzFTWk0uud-QG%wzeX@3n?& zPgi}~uf3-&{7+>zyNY=-|6FYkFL_hdx2^npd-#p+!-0SM!rMB++ds%=U@>p!hE<*6 z&WS^TpF91}o#DfuuKK#a65+$b{)2(P`y=za!pFYGW^6I<=-{heVc~k!?=9cz4j=jn zo5{tzrr+!93G;8M`oE1&^n`czRDIy)bZ@xscdLHz`r5wmhDB9h_@NK=g@5!hHVce- zT(|4};l<&qPyB1&=?{N1$7Y8yPpt5^f$+$Is&D+imkHr7|1+C4#{A=V@(-#3pTj*Daw-KuZiODqoG_yL=>$NckuwR%bT z($%Vue#d8*gkS##o6W~O=QpR9hJSjZ>Z@P)gQem47dHg{diR%>gFPx}}DV0rj2*H(S^|2ip$f9a2_{`)7Nm&0G5y)N+K|MBS+;m`d>)sKIxydu20 zt?J8vC9*QSGg9^E|0zEa{@M@Oj6&wUUznH(*I%mo^;a!l6;A)t3y(f%_g{FvD*VQ- z)j{47{vQ4r`S{_#g+D`ne)w7NGtmdYei!^s^7q4MfzO1#0rpwpGn3yRz6*RO^ck@4 z3g4Oh|8OnfnxHR%T`Ra|lm~!o3D*>T4D4FNHK%+4+zYrTI9HL~E4XKr7l3;S_mpx2 zaIfK>Q+@!R1$ZXVSHYeYcxEV10M8OUQ#gl_J!|mHQN944MR+FBx51uOcxEYY0M9Z! z)9CYH&pJHwls|xX0p1Dpg|K%8-Wkdxz`F$R6#7Wmy9VzZB61))H7#DAxdM4Xionk6~*OtVy4JF&C1p zRj_7J-T~G!SkusF!`3=j^C=JYbyG9*jfu~F6AR&ErvB2 zeLrlihBce=60nxTnohY1SnFZUr~Cx$1+XWeuZZmxuxC)70`?NvQ_zRR_8Qo8C|?14 z5$s8nvw*z{_AJU8v2~rUI%*~Ds5PPHM1NiwYEh_3DQ5z;D%7l$H-TCfYFhO9v04{uUdo?9Eetg=`T|+4 z3^g<5QJ|KFni_qCtk#B_oAN18i$hJ0zC%{4vzoo}MGX(NJk<1*TY*|1YJSSK!&v~% z1e9ZevjUtMD9-|C2{=#jq);ZmV+}L zq|azoJTfu0Zgr&%uudP0;Vf?g5yjBx%c>m@-? ziE>5IYl5B=`mM>!?v)j`h={phTh2R%K?EkUmjdVa*QfL*&^va=UPI)Zor9)30=h(7dJM`Qsp9Q^m=*eU5g7xa5XHR)8 z=;cFCpK@E!>xZ5{<~NuY0Ga^hxIila%>eTrOiKVwfpT4-HGt-T`4FZ>fF?mXFVHGL zv%owF(=tHQpxhT|9iVw&{)A~Epovfp473u^OehZqS_)_?lnVo`1vD4Tw=gXRG#Sc? zfmQ>W4d!8(mIIm&<;Fnk0nG>VGfWEtO^9-2pcR2;gn1jLC4r_yxiZk2Ky$);4%4DQ zlcJm%XjPzDQQi!+EYP$lcLrJ)XkL^*11$_RG0LHVRtB0G<@bhSv^>!CD7QA_Yki>k5w`}kK+ps!#|Byjcdc=LIt@6f{xF!GTr^nknYBn3f8f zD(1MD)(V;{<>Nq$1x*&`3Nx)1G+WBcftCxJF6P9T)(e_1<>x>P22B{4GLWMKtr#?8 z%F}_C44N|L(3sW?nlt6=K#K-V8gpw*s|L*)^K4AZ22GoCcc68H=1uuK(856zryL$= z<)E2kUXE$$ps73F7?<=11fG403~bzk_+xp#A&LLokOL zpO;`hHE93-^AzL?@p%j8S%dcPKaatjYta7v=k+<|4e@yn=3;~P??3NB{t(}X=afSP z?caZ2o>LwX->2vJemw{6-+$kpQ$7*2fB$_9=5*ux`keBL_&z_U+#(O&upPu7-733XpJqzZN<9Zk5A8|c=j_YFv z*UMnOIj*M}%0+_q@2|JPJak--gE{G-{rl^6Fh3pF^9T9@3^03D0d0kzrWvQD1V9jVK7G?w10oU z4Cc$@ej3c32kqbAZ!?t7#Qiv!QxDp|zh7r4uZjD4FxMWme}BKvP<|8Zfeht1v0lhf zo)ffxzn;iYt`qBx4COmP`}gaSAm@qoN`~^DSkGiA_lfmRhVq|S4`nC^iuF>E2Lke9{tT!wP9p#A&jy$t1N@jRHJ94%=7 z{&_J&d0ISA2Dw_${{8c2kgvt_XohmOp#A&j)ePlr@jRQM+%0JT{&_b;`CB{>XDEjY z+P{BZ&QKl~&(j&o<%0I_pSLrV&&Bh2hH|=~{rl(j4CQt4JfET5E@=P$c|Sw>UF-*B zD94Naf(+$(LHqan2^q@uV!t8C_k#BC_aict^TmEekoN`c-|uH+DEEu~jtu30LHqan zAsNa6W4|Ord0^1~{eDV@a>3Yd$xuER`!N~H34`|U_iKW@F!pmYlp6-^-|zQiC_jw- zpbX`Rv0s#-JTdl@GL$O@?ceV=Whh^a{iqD(j6wVN`&Ajr8)H8!L%Cz@cV#GljQy}6 zhYZ@k-!IEx|15+3v<&vwGT3j+P(B&^aT&@fW4|s#d1dV9Whl3d{k{z4m$4t1p&T>z z3p12w2JPSPCuS(ujQz$8<(onK_xq6<$~j}dGDCT1(Ej~?W{`WverJaA&!GML{m=~d zM>E(j4f4>~Pt8y+8vCst<)g75>rqY`w12-}>rq}B`?((Fra}An`@J6Jr?DUGQH~n4 zf4^VsQJxz6$sXmZLHqan%^vojJ?uvZIcw1V{eE?jx5j?9N4aaz{{4QpNBL{)hX*-q z(Ej~?xkq_y?5BH_%LeV=@3#l}Z0yH-*q`@6`}h0xL0%jC`5xuAvET1eejD`wk8<3o z7kHHC2JPS16FkawgZA(14MDyew0~cZ@F?evdWA=MZ_xgIJ;S5iH|iZ8<-bAu_w^8u za^R?!c$5c6J;kG3IO;7P<-y-`Cqb%BQ0q=TS}_^*WF8>Zs>=lv_u=&!hZ0X#c(*=uwUx^+J#G z?4bSodZI_UcGMd^%D02|@9U8s<=j!P^eFER+P|-7dX#%dz0;%oJ81vD9_mpJ9`#a> z^6;Sj`+BNJxp>rDJ<7*}_V4Sl)tvkbz1E|=JZS&Ep6gL=9`#<2^7E(%dz7O`z1X8X zJ!t>Fo*d-rQE&DrUk}>9uSa{7vq!z!qr5$6|Gu8>QSKh~ZjbW!p#A%LxJNmB)XP1} z**fl@=iHh!_EGN-^84rq@F>TRet{s*kA4D= za{cHx2=e{tM+kEM=vVM4?~i^4k8=O$cL?(T=!fu#1Au;sfCqqn3Xiw|=(h;?0O-f? zh!cQ*jer+`evW_}fPN2;_yOn#@rWaUevyDDfPNB>xB}=m3HSo&NAZX=fPNK^cmwEX z@rXNseix7U1L%kGh(myWnSe)tej1Os1n9R3_yp+3@rYA^ew~0uadB_#@&@bi@PXYa89&r`W zZx-+s(2wR3X94|c9`P2?&lYeO(C_9Ee*yh)0fzzoavt#*&`%d|8PIR%5uXA5cmbyY z{dykp8qm)da2wF?=MldF{eT{E9MCW55zhhrgaOw9{e~X#9ng;$a30XF=n?M${fr)Q zAJFgU5&r@GkO2n*{gNK>Aka@4a3Rod=@B0S{g?qK0{xmE@gmUA8E_-e@97ag0{x%? zM*{t#9`Pj5Pa1F~&~NGyUjqH89&sknuj&zR0{yH3cLM#c9`Ps859<+!0{yZ9j{^O) z9&stqZyWF_(2wg8rvm-D0j~o6yaBfY{k{QL9{s=`aV*d;>=Dlb{lp$|EzoZq@Ga1f z>=EYz{mKFF0{zS$aWByC9PlsD5A6{L1O3tg4+H(w9&s_yZyoS4(2pH(GSIK>JYDhU)>|#2Kw0p?gskZ zy@0>*!Ve#CIM6Te5sw4?^Z}Ox{q`R5Ina+Ea5~Vh?-8#9{rmy91O5IU@jEaN;1S0I z^8z06JTOlXa6K?@;1S;g^9TXw1M>1aZE5TBQ|GvLNx-ZS9GU>-E!$Y5SH;K^W~G~mi$-qa($4CYY-&J5;N1KtegSv}&;VBR(0 z&tM+bBMuGbWve`z7kOHbxHOoz4fr&m{rj4nN1PhW>ju0U%=3E0t--vnNBkPh1AD}= z!Mt$5v%x&EM_e1s8wY$F%p-fmxxu`0z`Mabvq#(;%sU7C8_Yv{#KFP5bil*GJaxdu z!MwG1_r-h{5A)a_adI%P9q@86&+QR62lL+E@)z@CJj{a!939Myd&JYhJh?|)9n6~t zd>zcAd&Jqnyn4Xf!92T1+#Srjd&J+tJbb|6!MwajJRZ>geNEjXE)VAI13nMt@jc@7 zU|!!NUJvH^18xuI{XNqE$%jCG2=Zl+KZJZLes1!WlfRvO_T=}c+yTvdqB#gOPl4t#&|D~* z6G8JPXl@0bpMp6WG>?PkdeEFHnlnQ4N@(s0)?ZVICQZTj^E(-{5l!?ZsC`!UVU|GrH7^1naRp#1B>v>^Zb zFipn4UQ8SDuOHJW{OifI0{{B5o;@&2;TiC+KkH%p_k;D4{rkguy8iuQy;cAIu^y*? zKUuHQzrU>K=ihJEd-Lx<>w)>t1M5Zk&j;%X`OgdM&G^p`>yh}+6YEv@&ll?%_|F?V zyZg@{J45@Qg`H*n=aZc&{pXdP?fmDLow5AqnVog~=bN25{O6t3{{HjNYHa*Fk?1*Ylv?i|c*R|E4}X?hk=3f%`|G)8PIR=vKJ@1Ueq> zPaf`9fxe3SS)e!Lei!KP{oYSAg_-S*pP%8I zK0WhKO&_260QZrZE6u+#Gtu&vnKxSQ&HQ!i*_mH$+cR^pU6~o~m^Jf_j^>#^>?}XK z&42mXx~@+=tLgroXSwc~XK(L0{p@gW_}OsZ=(B(8`^nQ}|35yxK9G7kA-wdoBAk8t zd~n^daJ=&PE8~Cj_; z&wu=_+24Qk;W>Zt=+fM$kED5<9+l=bJW9^bJ-oEwrHAvSoe#eyH9!2|!dKigi{9*x zFV@_zEdI%Z_>zx3IK1@QgRW(B9=y8jpYFe9`P=VrlsDdgL;lgdkFWU9y&EeJ-K6>{(t4`nDv%2+e{hE*8`NW#jcW$n2x-(b#)7u5*@a?y*`^hbB{rhhHVEx8h zAKLJ5&XLJqbeg8-IO(aEZ`$hVn*-rDZv0L7JvZ)X@{L&=KYRW28_!;UwCVp|o45Jb zuH`q+z4mBJ`s&=RJFouz)~{T-x9$3sk?lXb{MXyxdik@o z=eA4l+x3Nu;oV0setq{>FZ{xua~EdqEuHuFUOPX%@B8Q8*mvvPZx}x~JF)-P+0XC) zuQQhq+&oiz@OA6A58Bqmp>Lf2?4jw?*5TKt|NF2p{nC+FPK_Q_Po<82?BphM;mI$V zzjNaJG5*94kG<*mn~wj`|GV?Ye&@uO{C~5_{MgBq|6h(CedW|kM-2Z@zcy_hp7wv* zH%?C+vi+a_x>bAdrvKai>&)l<-#oGZ2WNl7xaEJE@1L9Acg_EFrSr4)p7THLS1)|s z|K#D_U%2?bUEBO`^Zb&zbEW_7K5TdH81%pGTm5hSv&$pfulrZwD_8#Bzan$Drmy~g zp1uT}%C`HyWJpmYDN%`tl8_-OQc^O$gfy5#=FG!6&vTA>$Q;VpAY+E4G)N^$nNo>J zMM2+U&KykeyO+N=a~96Ye28_HcR+JS4VngwxD` zQ=Re@(XxS4zU@^9C(g4q98Q1GyKu{PxQ#rxl}Vq3&HLb%DvwF2^T4gy!0pxga;naU z+q8jOz34XpH!Q8Z4{o~_$Z}yV=oTC38Vb567rN*g zbkkGls;|tlg}l&Z63}hx&~=8;efH3W{?Lul(3P3cokh^4wa~41pljQqdwZaZUqd&) zhpzq#-8}|fJ_+4E4PF2LyI=L+Kg#3pG<9xzlIr_2MlJgDmD)4)o}wpTQ*{$P)aZCS zB|UzJI`q4iIx$v6wf@SaIDbV`nm_$1zaREg`FBI=%{O&Q?3)B-{*{+HKKhk;@5@u> z-_O^WYM*nNKA$LN=|>ypn-5w{@ekrm%lDIv)RAsR>$@rj&$~E=&agd$@pdz#?#)8R z&!M5PjYC($+y`UBN?u!s4Zo5NlYBKEYWuP&G;bg^wExASP|+9Cq5JzsL$dlVhdg`E z2oZU%6JpuR6_V9+Ke+cq8;S?crviG>r&vCNA7{j zk0b+wI(q|db|eOHc5DyOZ~y6^(pKo-+q%zRqLtI%_2EUoiw|u4rdsCv>9*ARCf~R5 z?Q7=om1(X#=6i47v4*BeAO5C1AM3l@eM%Y!y~po_d+Xhi^v=9}+iT>OjhDu)DbIw4 z49|g^8$A_oKJbXFxA%B{W5QkGMv{Bvbt(70Yjti)*Yw@uuJ#`ts`EIiSvT#PaV5d^ z>*ZyxdoQ1NDXLX+;jFE9w!5^;`BqKGkrg$TN0=91I1N-gIB8dpIG(O@cjT-Zb#STl zacHghZm(G3W1n&1o85G|mz`tzC)?IC7h9FGA)EZt!#49upB?ruF*!U~+lW8K5Gi98Xeb`teyTK^u zl!VdhQ!K;cldlanp42k9nw7U#Cu>T-Ez?SWf99nO@tmp!@rEjf z@fn+@;s%sU3q+dt>&=bH!w>Z;0++ z7aF~CoqDvL+*s6E+1jYLYyG37*Q!N1%S=WVOV>w^tYJs4U9%_BSxO-Cyku|0+tp_x zBv*Sx*hy$aXP;q%45vh|kVW3xqb+4al(+2c!% z*~&|0*&ZTX?BXSZtU=*htmVQ5tbL1VR-%wS>;58L*6c-ctj&T8S;qv%=(2?a^w5H4 zdijEjv>AUc9nTj>H_i{Dr{=lP%JZz~qrCd`nYml(ULHkSfJcVb<6c2iTubQ7oD1pC zb9iZ~Ib8Gs4h}kX_AI)EsJ~gX>OT(J<1ZI|Zkm_w`?HW<^k)gZXKDpaPs-4B6N>cc z_*PnaT%SJl+loFh=0dmr3ZglG#nGBSb7{XH7wPiv&GegZ1GLz;G1~m=Le}w7Io7=| zx~#vS?OAG{X_n8Y0#@nATdX%923g`CxY(BOW!b4C#_ZO2{%oFixon-`du+zruk5-v zV&OlBc86~q3J7-}EDSGs-5oysiYG$yl}3c^OOJ@Wfin^PFM1Sj3KEj< zk01Lw!UGb!n#;~OEJN-#|ceW*G-Y!TUxy6~HamzI& zp`jyX;HFBd;?3OD$a?Oy=Qq656mImTMPAoS@4Hr;u5?ZEMBLTX6GL?z8Jcyz85viG zGrnHlpSkyPTV_$MP8MhF)hxS98&BSF)rSF zw!WzQ?7AZRbJ^!d&+(mS6fz3=;NP;(+n-wpe^Xzy_pC8|=3ue<8UK<>`0BN%^Gi>| zcM~gUEz5-OE|foAo(!+HAWsoqxwV2n*QGKM-i<)c>8dn%cOuyX)j9BPSD#t|@BCKH z#*=oJuENvkWEIu6!PD)}{Cas9p4Jzhnj>SVE)`Be@`MtcNZ&QR^vLUda7x~ATHI-o z^|^3*DyaiEJK!{3;Z!+OMs5|rDQ`>GgA*UW69%U*o@9OZCftS{+zMBs@4ZsEC6nWQ z&Es%u1#o-%2~#aU;Wi84Rt@7N;D&o!OX0Sy;nwHJaY6;$?C^nVkd9S`%J}jq4XR`> zR0~&(Bvj6;C!tV9>d^Y@7BP=$M-8U-Rnp)&hloPjF! zfNIr%s^y6oe$@?CTnN=109Cyks#`3)?#)-I_IptExlsN7&;`cO4YJS`Tx@aZkT)N0 zLAMk@*U->C_RvMT&`omCRSQ|>U&o-!2B6!Tq3bR}_vJzt#z8j*L07s!cUnQ0>O;3~ zg|1bE?v;TqUIE>_1iE@5bT=<_ITv(02Xy@``X6vV&i_m7|4}guTV`3uOj9exQ)fRq zHc35`KET12fFC-_NzDmN|4I!@f1Y#e;d|=Pvdf%q&9A9Vvna0P(LGdHuO9a{zIJNo zSplAmeRrt51HC*K9crmlv(C)Dq*_GnNj}PZqdk+lF;{usk9E-$m&?>V%E+HmDQ}#g zq-swcejLwd^2U%#?K9*5WvNaL-C4fiQi=rS6g{+{F@={}CsVf2#_B6mui%)#y|+)9 z?O!(wZq~TQe6nQrqCfj`nVtgo7g=nkm{om=LTPVonAHLM7XP)>Vn)7PF8n@CoVj!H zpm0&vB!f$+cuC@sZpJ{bhsf{gD#pkW<)vCSaSYA6@uf|1_Kfcj>z93^H#620utk^Z zEM$x-=`F8r9|}9lo-ZaPb0w@Mp+oG&-q^6W#%bclTdl)ZJg`{tWlAcl2#t)@KE4IH~E$J{C!i+gDdG_Ju5X(Sk zsRLY$kVAZH*YpVJgw*Pethw-oDWz9jetL@~3A|ir5Zd$o+t+IBImr?(^n5&b4*QT=8zZAI?IHj>qzR$=# z(0-oa26-FFz!fg78)EkK2H5`>tx&iiF~GKY`$o;m?E!{OQyb^4|LK27zgDp$ve3WT z+*4_9{XYLYgVM^nk2(FLzYi#f-@oW*%+A>KDA&f%BH2)7(rmt8uPCQ#=f_%Kp;gyZ zrH|P7?#lC0>ulultxA(pKhITpEbVWPdc^vD$CO?qY~Br1(<6Cpjjr{1K3Bec*WjGH z-A8ss;g)+32fe+oS!n(Z3ip0`n`i4u0ZH#drMj(=X}7)B&v)5Y&0*tpWsiu~BAY4C z%uh{PIVBmM;@^F>_Y7_HJY^-ZeKG$7562bl+b3o0Jvz6C=uB;za96p#W`~$clKZDq zojYu0rQA*0LUwj8s&l(xA*CDiUEeK9rA^ndrT?gmi~p{3Ssq7+KZ)t-+fBP}xYMZT zE|uWwIPAK6)zC86FP01Uu=38kC<|ZOQ);Q?k}GDVe`8_2bEf;0{1~df{}}o@JQY;NT>}Eny@bJK}h5q`|0Rzq{km+{4C6N}~>j zPE*FMi+vmp|H(8dpZ(oFy;a%Nb<)S)^GUnuwprioJQunC=eF3(P9&1UY@_-o+flh} zvvzkETLy=+`SF?|8~u3?%xm}$+YD;k?u!k3cDU=@uYHGRn;b6L6lW2Z+k9x^i@2rg zf7=dObX8ftTy^Q7`3oJZ)_JlA6BazNG84=_km=~Sze7dfz@mX4`%eY4t?>i@9se8t z9exgeE`AMuEq)LDUidxnd*f^1YvF6+YvX&s_k!;U-y6P1e6RSP@x9|S;IrT};j@uv zglENP#%ISfz_Y+J!Lz|L!n49N!?VLP#IwXR#k0jT#zZ!dk+b!rHcLM%c|LTo~eLaai}LhM2eLo7o~Lu^BgL##v0 zL+nEgL@Y#1L~KNiM65*2MC?QiMJz>3MQlZkMXW{4MeIckMl425Mr=lmMyy86M(jom zM=VE7M{GxoN32K8N9;!qKrTQ|KyE;eK(0W}K<+>eK`uc~L2f~gL9Rj0LGD2gLM}p1 zLT*BiLasv2LheEiLoP#3LvBNkL#{*4L+(QkL@q>5L~cZmM6N{6MD9cmMJ`27MQ%lo zMXp88MeaooMlME9Ms7xqMy^KAM(#!qM=nQBM{Y-sN3KWCNA5=r5cE~`AO88(pvPbQ z`?bC2rt$N)KkfU2U%#w((I5PNXNLDo;rD;|kDkQW3zx2&z}LTiaC98skKH-xaeRMH z{|^1e_j}pv#2CK+9lu+D;qy#pa{j{Sdtj#d6QB3=dcPm|{2o%}-|;-ew!Zm>=W{AZ z>>HlflOFT0cz$&@$4Buz6&K$7g6F&L{ol`c-YKJMpYi;SrF=f&eHg`-e#H9;S@q@v z-q-by;vew-raoD|$NQ9!P94Gf6*<}Z4)42BkLMlUKmR73VXTMeHjKAe9|CQ4Z?IlY zz)vKwehhp!4q-isR=E#ieZ5vGd5!fJ!9Dy6>+h|k`Fl8VCAc zVEvlj6n%m9%nID!kM&&~lhudye&)xs=UD&x*F>IUKZFce_F{kV*=O}&zdYO3`waW1 zHc|8$_EYGVgWcF)e~t2B7RgcTpuEy zlz3fyfcPTwcB%#O=F>~v7Q~-xcFFe)4PNC`1oh$ZN$snmq%_Pe!2*0+(JAZpElNkl#+vaj8VU zb5m}uK>kZvr&xh}nDRN}0`lWX$aFdKrNC3ia^z3;bZZ&%Y3(nSGUQkBhWt|GTloX? zN|App9{QIcA9D*1788D!H!eoLE?Zq+g#7LMZCw%axl4BTdF1!c5`5>8?~g<=3X%U6 zAB>(u4N(5Y{v2umamxMh#%_ z{d56pfMW(?1*icO(=zi>19UbE<)a2j|CpSI8sPT71$n3eGPn|RQSX@j<*{A_}14Ob>19)iXoI(w-o^$mn)Brmhi%+5kc*Wd!5;eeD^{ZK^ z0d{=V$wCdVuedD}H2~9YeLr~!IU79^ksP*|*=fEs|S{AWCB00sMkc+>!4 zYKHNs0j{l|ibD->NvAXpHNeIY>p0W^zaGzzLk-Yqax)e+fb}<@SkwT4m!)G-13WJ1 zk3kI}Rh<@t8erAP-Wb#XfxEb3Py;+`ZHPt<@F_Gj8a2RSbMFQ3ITtWJjU~IJjv~Bx->E9DzvG09BiMBTxg_ z|2Y$Z8X(}OM+9mBZ*h$X)BqiUJQ1h?1Ub9IQ3F)nDGWyqu=-L!IBI~tp55W70gM#I z!chZ^)PH581`wj|u~7qP_~)`w1KcX`XQKv~%VEq$4d8Q9mW>*~%9)Fe8eob0APY6X z?BZK2)Bx_w3s|TDO777t)Btlz?OCV+?ltMMhz1aqW1$8pC|bxu4WQ{cMxzEW@Eo8~ z1I#OKrcnb_F26{l2JmjlrBMUW)p0ax0RAUIG-`kyiY_#20D~4Q8a04njy{bVz_oNM zjT+$g4@DX^z_B118Z|(=`U)B~fcB;(G-`ktw}mun0LB0>jT&IXaV{D)Kw%&UjT+#6 z?kpNL0Q`@}f8d`{1K{7I2Eflp4S-*d8UVi^Y5@HHr~&ZxPy^uWqXxkDgBk$eA8G)6 zzo-H5{i6oJ=RpmC&xaZSpBFU%K0j&zJP*_Wcs{5B@Vrn1;Q65j!1F{6uo=#mXaG2G z)Bt$?r~&XkPy^uopa#JELJffThZ+Fy6Ey(dFKPh1Z`1&I|EK}59#8{deV_)wdO;0< z^@AD!>j^ag))#63tT)sESbwMiupUtZV11$nzf6K)gZ?fcS+P0Pzep0OA{J0K_}g0EmC60T2&S10X)420*+-4S@KG8UXPWH2~r( zY5>Gr)BuRTr~wd@;hn(;t8RA*u znc~^v8RJ>wnd8~x9pGKyo#5Tz9pPQ!o#EZ#9pYW$o#Nf%9phc&o#WkO4PY%`O<-+c zjbN={&0y_d4Ph-|O<`?ejbW`}&0+0f4Pq@~O=4|gjbg20&0_6h4Pz~1O=E3ijbp82 z&13Cj4`44~Phf9gk6^E0&tUIh4`DB1PhoFik72K2&tdOj4`MH3PhxLkk7BQ4&tmUl z4`VN5Ph)Rmk7KW6&tvZ+1|Sw7CLlH-Mj%!oW*~MTh9H(8rXaQ;#vs-p<{Mj}=sW+HYXh9Z_CrXsc? z#v;}t<|6hY1|t?DCL=Z@Mk7`uW+QeZh9j0ErX#i^#v|4v<|Fna2Ot+9Cm=Tjz_LX&c~ks;0_M%!Qd_m?t|b?2JS`RZUSxx;qU12_vHAyYW#gM{>~PEZ;HRW zMD>8b!^7XB;qS8W_euCW9sIot{%!;0g%;|I|LytyZ{PO+_P)s9;phC{9-P+y_A&pr z7YTpY@PA*AyJ9#0x3BkqpO1e>vIX_b2uvKxH^Bpz9`IZvp8lntf(}Lo9NmX;bpoX}fQ^K%)p~u}#g>XNn%DFqK z0kTW=kka9~PxFdM>jZORQ6h7lP!#hJY_uc_1u}05c`?5WIWr|;%VpnUOJ?+9V`klA zJ?00pBc{eQ6yCt3gr%8PWM6DCQ)mevQ+LT6W&mu+6fgP4=v^|xm?!d*p$S_v9wKdw ze33>*r^q!12W-+PFD+s?F3n|REKO%Lll?N9A-61mabTG{BLOyU>X%tDMwb~eR*CLl zn8FqgTU3EjBPzvsBf5;S1U7T@mUA+KmQRG0EdLVrob03ZglUSkg?WhG3Ckn9X=P!v z#0$a{#nZ#=VXG%ioDp_c+$Zdp_>r(Ru<2v5!YC|yg-%%A3e~XpWPeROOn;?dSm;Ww zuyV4?_A!)y)yvRrtGYrxVM{1~)z#3>Rpp_xB=SQQVROh%A|f_nWZ%s= z)O@v0XvFGGp_j<++pltY$EONH!~77hu5Ev91WvEUx*cfmX|J;7?Q+2ky9 zH8@kIB)D1TWbhc-rwa+TSbH=$YOQr}E!nNp2o{!=3*ITaEZ7gWqRz@r1U;4=3F46J z2~vVhDLc8#K`C+FLV>r8_#kX^hDLG#y(2WhP53vz`mtE~0! z1MjbY7WjL8Q=l|#UhR`V6Br?%99SdI3>+l;de(tj8}tG_H>d>WlHEOlz^M&?17sCG z23Wz?RZz%4&Ziwb7gsdw(>InDrMXU{OZTIsn1Vi zQ?s87Y>;Ja%JaLsDc0}%CO^NGuvKQLqVE@~qT*MqvdXWU>>)<^tlZ+|W3a`_CkQs- z3b)AmJle9zXL`$|w;XK8S!h1=4%e*luGGx-?jyU3Zr;jU&Ae^5Zt+goihGOmyx(m7 z?j^A8xtAtv*12pe@k-m4?A5R>(CZ`FXWZqrLrdPvQ){u;DcHbk(i-&qrq$vpu3hQ5 z8@BR%wHcoI+76x%wDmp5$j+mPr@{7VkHGCi9%sn@W0l9m_6!dxoiGn$*ysz<+3iuN zBk$3vBjhnj_96$|O?KRM58YAXUPyK%{oJQ^>~~+YQ_I~1wgE$S^12u9{NmQJ^Re3` z*`3UBGtyDU0lTwm7~sDs^0F9Pg+K8Mj;@`o!e<{y4y@&3>R*-I@vq+=O=$l22NPy*ReU4H1P<;1}W%kG0KU>jA(D&?TF zmFK~DtGx#+$?hum!Evjh17iDc9nglYRmc6o2V(YH94Ozfe4vx;w0^P{v2L;6VqIu` z7}N|K{#girYJvayiR`*|!e^GlSH!?q;@+z^d?&H}LkGsKxM4F^7G7m9yqYJxY6{th zU18M??`GoQQ_JPBLAwp!r7gVMaCp~+WKVVip5zHUQ6)SX?#w#DlWM~gi(1r@{n<`9 zi845mNH`hXrPY9w65dw;r*?kl_!1UItQ z%m_Aoz2KIT;I^vZ);h@^t`6L!*nf&}tER9C>;t!)3b%a`ZoP}_=kl2fLNzEtRhU9` z_&}8;L$y>v)pU@(-6v2<Z{5AuZY3tBcsp}_nfEEV5f&228~S#xhm^M)s_K1Cu=fM#}+a!<}m#V7kR>alm>7WdAw= zn9v3oQBie_>|%EVQx*ebh5~cqUiL~AKVZ{XVAVXbqwNArs{xG5x9Ka{*RBF4W&+n9+yGO}c2EK4paxt(6@-#q zZ=sC^pcZOCHQXb6-&UX`WEK7fOl=SVX8`<;43vf^C=RU+)?^=i5R^y_D3SEl@-$pp0;rTnUsC zhujFLrU|lF?gvV0CnzdmSq-vdUJFVq3KW;c+7PmDJ_bsx85CJ2C^KhJXlkI;cx2vz zY8xYa=s}?5c7vi@Dy>X*((6F!#em|oTH{If(|>~!Yz9S`3Ca+6)zv^L@<=@f)%cq1 ztp|XT)CEN;EV&Gv71E$GH-XyJ0o7?t_St`c61@Y8G!>L7?zSs}Qk^AH4yyGk*>m>< zCA$q2E&r;IWaqsclx`>}Uj3Eg;NFl06|4$sSO-+G5!r=bv*HM-Wgk$@3{cOpprX@3 zO&5TwE+aegd7!jCKyhn|^^kq}=b*$(K#>Q5GRNKdCCitAT9*RVu0ZzaO+m@85;X!< zZ$)Udj1|coeR|q#Xkjx5b>F#INuT zCh-QC$dAKhj^2f}98)l@|Np5SeGE1*$>TIX^?%bnPWd?Pl*_b;M(_?sqjcF;+n}kChU?g~QlcN^vZo`u8iF zcrQ-nEEk_{pR^e+Cmz#=M{2RL>7L>iiF9;?L0eaflN5VMPsm zHzQt+kng*x-QRamOTKR{}CE4$a7_RSf8S3xS ziNECOFwHnO9Ki4$b|+pFfnh7g%eO|1inlw6@5JD(0%Q4GDaQLZ%ZLXh`VA+;;>|?Z znm1p<(2vqM)DxCE)D~tpbcc9T{tcFewGS4A>`-=*w@acJlZozT56HWBa3hyG=u*ZSv&#`aH#pbtj2|8>ZC-{X+` zeNDs@b~IT3nKkj&eCXB)zTPbt9N)c+_-xj9 zPXtXr9SLfC+7pDH8_%bggS4KW4-$BKg7|N$pZEr`pV$Ze_r#QVaehAD5Y+ToJSgKa zAMxd=J$@fJ_wlp9-mWI%(FyH36KK$t94Ow!Bz~P+kE{bz9_ad z1ByC72B42ezw=(e^3IxoPaOrs)05N@8erGq5}?#!PW(Mj+cyLhwJ#3{Zs#FhAF=jV z{$JW!{Tte@65o$QTZ+F*8^fQc&6Rk7%38PkGg{^Sja!!yKhTedU;UaM_W5N#Z1zKM z(3XdJe*6z({a!urBR-*s2l{@N4^;eQAFLvtq4t(B--4D`zP>FFebGO(w57oJDApRpPIW~KGAorh$m^oU0ENFyNi6DHcon@ zKPjy7p|?q6jki=|Ht{O8-f{EJzhma@duI#rEiJz@&wKRtcdy3V&%MyY8`w-ys`(}G)ro`Vf7o>v+wiO* zIB)p5Kfk`;z4E#i@k?1>=XKwB{fisd^~Y}LovOZ;;}(65<#zDe5#pnodriS@;Hr?@ zrK{sd(Nkr6_4ZNKtA$7TuEr97)zv!Fqe*otN1f`H9YwFzqPo|v@2}i-ZMafQd{^#Q zyj*u&F>_sZMU{B4nlDegtiT`3U;AGHa@jc-5pG(W~(%Uaql=n~$_# z6g_hO;vXmUby-|&aN2OOz=``Jn|QpgRO>n=RZBZLSMw0R*V5`1$FEhTjxAO3#QPOe zW$0*DCGWVdY601LH zWwFFtR#c{E%PNz$Jy6C;d}ab=cWgeC7T7eEQp9r>QmScVUMgy%P&#oK{bz4WY7aM* zq#Zt0;zPV>CMEKR*Okma%w6*S5c<;Uiwh5B6^9@4Ew&{dHM!#Dhq#L;4!$nxK8Sv` ztfG{Ienp-KO^Wss?;1}L_ram_LkAkp-#UOkw!rhj2h7e}98fr~OgwEPg`ceN7PeTQ zE-bXh-&a@{9=293++r-%Tmz*o#A9XH<_};Y6Y3~<1C$@j$?6?(r;4Yo5 zv`RS(KLI%FO#E=NXIEHppPjILbLOcfdgJoXBv^)>akjKRqeFahOU_JK{5<`{qU&^} z1$yQZPdiz-pVqd}KP^i9bKIvp_q{DB+t*kSNxXD)fyO?Y0^xmI3r5Y+S2vY^&b&9D zXB3?&v|Q7k<(y;UOlfIZxiF3JtiA- zRukXex9lgzUD@Tv7qcUYhtDrt)p%d_LSxnJcSh*v8$Xq0)O*U?=-R2>#M{R>HDPFT z>XD)LsS-o<`OP`C-|+28MZT`^jVjqmwSg|F`I*h{4aS(Y@VS_x7R} zFgweCFC)ufuWgnT@dd8Q>e8Q^RighPlSMp&RhbI!-m!Bm zt#Bv$5pSiL>^z^gW@mib)DH9}TBH^3*pe2yLn6(D_!K{-PU>`}cIsS7E!08JVtA^t zj%%uvj&bV5cJwcbrJmW&ks7#tB*lPu8EaF4ZV+Rk~O#SCkt%*mGovS`XKKnC2TEE zvfY}Vq)a@Kj!Au*21%8go07sc(I3f`B&Yc~ae7O4;-f9-l`KjO+LD}Tuq8NgCGkz_ zC*IRgPCTh0mgr7AlwXbuY4jW)-hBJ`)y?RqOh0b3nQ>fcv-5Fo;;qy;UZyT}oTndB)`^p^tM{oVJp3oS@RmxFJRKbdJYHDZYudQhXFENBo^-v27bOWAipf z#Cj92r%kNTMuXTl3Y%kV70~y&IMzyGcC4(zXw1|G^ngBy$=y&F-xcHjrEVB=M&FpMf8PrxzUVu3DHKx zKYBEJRBnItExA3>DRSr~m5El86N%=KNTUz+Lu8P2U*vA-*2tyAlUf;B zx27O6W=%?@74fI~MgEp@ifop$jLeimuc}6*n$-G89;p?P-IC~A<%kTB{28GuIUFHO zJgg5RF0HPQh*(_}VNU$4CnA1G#6;YY2#rXUKyRyUgrbC5#4L$j5uK~h=PDoJxoTC! zwpEKG_=)FrGQ51{m+;V)gW>wb|JoA%enowF-HPh)=oRRNJsG}cMPm3bad!A!arDKy zh1-kUge!`hhtDD&*{$JuVoKp2Vlv^H#4jrt{(L!ic**i9cF=P4&JMGeEbn8#5$$Bx zh@y}72HRA$n!QT2h&{RtJ+*1v749Lvon@ju^oxmR+r7ORFmB) zqQuS@LEr5vwx);(d!EPwcJC7O;QnC+EcwCGUGkA7MEtnDtSaG0EK2x3%aC|;>sTKa zSF!3A7qg-lqfa-BCAm16^<5~2bxR06yTPnOLO!f@LPuE>i_pJ&fR(YxoaMO4fTcvd zyxUkEf@-W>!Hq08LG<-XvgQhkvAPA8u+9mf$CsC-Ex^HAAn=ENu@L>fU+Lh5A85UW zZ)joS{q3Qv7j)6of;QTa_<--w@A+@gSNN~ck^JZhE~h2s)PmKJgiA&_z6Iv_H=#T8DU!73cx(^>jJ6EFHp){^K>Y zF!ySDh-(#H&4pfMG1`DjlosV$N{?`&FL^N?&bf#-5|1)JeQgdO9W!S>Z9)9X zbLnp!JahvGH+`G~y~~{RT8=sN*z7s<-P!14o=w}phdlV1r(hKTJL;Rqi}@PQiw zZQyjwh7VWxK-VMZzu9!x-`R8lxF9|L&Y`!!2k&1_`WZMQ&rNgF$EJB`?diGn0^*0B zPnZ1RqXYl&)4IePEl9tbT0~b&EvCc3Rk>$sDJ?Q3O23^HqieuvNl&h#jV4#qVv}p= z58%G6n~&MmTxN!~IiukIv>7T!M(06|8(aGT4JoMX$UiaIS zo*3IlH-nq=#MnXFVa%3R9CM`qfy1-)mpgsxmpAS5%a2wiK5Pcv^^-*x{EVVK!3nDQ zGl`z}Go9}Fkwu>ecc|ZwGqlc+B3j@_IXwW5(em$C=#cL>=-uD%&`XGKyN$m1t&66= z_0UGd!~KT-@bv>-_w_3s1#VOGuYc&(UpZLcMtNBc;6Ob-x`cILRE#A%D#`i{uGD*9 zHnP&csIlz7Y-4RCo^JzI+h=oD_U8jESK|LZ%Hsa)!+P>5m~{pmtv;V(SX!TwS^S@} zSpDE~E&W)`3i?>Z()(D)5+)w;`>cx}9Nfy}_;k7cS#%C)?m{AA9-RVfK4)=GMKLVn@H>4!3wC7`}%1(PhFL zhm^uohqi{>5pTMA_`gA$@b*Es@LX{9x(~9$w+tqR&l@}${v4dXC9kW)gI?E%>%DFX zUqbxrgW;_kB3xL;uf+YyBLNvEVx1-@hVKwts!(c%Me( zeQ+XY^;t%`^f^VU_xVN6CI0x7$fD;3k%7-EBlU<^zBTe)Z(rn<-Vc${;9|Dy<&Bc* zT^cpsBNKHWoXuH1yP{lrETYtVjzsYiKYe6W$+Htt!Ose#^oh5=De6P_)2Qp+!%^|z ziayxQ9lgF=BzpR(OmrJKrSqQdiS~TDKU(YQ(P#nUzfXv+ev%u_eo_(rAMxTpivIa{ zFuLjSkLV0=Svx;o5~KEbZOq)q8Zo`#ye{oJ6cgIz6=TrFiV-J%{lb`AkLqGl9zBS$ zC*J+h7|uttW4k*S#}?$k7A#; zzlkksACC1YeRLV3V-4#XkXl0+3J-j`ZaFmlGWBwSM2@>$Nl(EYU(&cKDXh^T$)wRSNs43@q$joBDNoA3 zb2rKN4(1m8N?Lx0KY8@_n&d`s)@R#MzG_X@_8*)-q8fsH`N#?;wO3h7<)R>!MsfS4ZfpIGLP1n@E z`tZ~$aP&vkUrDvD?@Cpu|CGu_auFobDsOB_i@0HtW=%2@;?p>9oKJgx{Z?8fqya=; zA4{{oE||XY`ucP(lAYj?UVV+39)0a(`azPT(3w8>+Nbn^t2`$zL6Sh+)omwiuUel_ zy&7L&hYi9bBJcfYG)tA#UCu*xQJ0ZcKsP;o9vvzKlMeUj_d6Ls$o7H!TkyUdk zJ1Y*74(u*O7<* zFfVGKvbbn-YQsgwDQ=SSaP8EU>fTdH)#Im}N#28M_R{Ko*6e`uDt5QCV+3t86O&0Hi{wlx-~#D6=W}P)ZjxK~hA1X=6c1>DvPHQts0V zB!5Ex^xG2m(+wqwr%yqmgnvobX_Jzlr`MG%Im1nIDXh=b7l)n6D$YOSOEN0noRKT$ zKFeJ!d-gS?QPdZCo`s(Pob@ZZbk>AqS4^DcDH1z3bYAOR1Ef}DpN~2hc)sME+4V5)Mr6Q0t>I6q@Lz>U)`bFmrWt%iAbcg}UNpdW8agj_j;Ck> zk})?q@;K?vE z;}kq;13dBD5`B`Np#Udg4kr=j~lN^RiOwvt?p18|ZoIME_FSMDxf+Np-Q}Itw#GI-%1hYSWr zg(MF~9F&LwD3VZ6CYTM=+ob_&Wi6JxdJ;%} zi~uMhEl@3vx|>MGj6Nu>U{G8o&mu|Q3@<1# zbx>q3pvm}{ZcQvG$!nk}KlBenvQjUo%!i;h>p^u^kvtndP@-Ewk$QkK z#cZ2)P^$k1%s{p7A~`oHpk!}@qW%7IG0D6!1Em`QinsRFAfz{Sg9>f|HCzv>xSC|) zJb!%>)N&%IW;Uqj08r6xpr&m=RhyHH96M0jsi3$Uhh#`z&KgkS7NE$ZL78KA&igmR zpw|09wRe&noeEI$FW**!sxKm$I=-Ov&w=89I!uv#9d(!lTwx-}hRFc4cBbFy!nB|X zQ-c!8-D!kL;@5}>Oce`Yy5M5R!lZExCXP?FpWHdspLM%<`ITTMGq#H zAedY*r>Fm87ECkAFxAA6%$_qa={))515?jYlHcPBlTbEHL~Wl9NS4n=n3U{cVoHa} z33GjZf02Y~N(`o|B_!jg0Vb_)qa3W&FnM9#PZUgIbuf{A`1*!q{}{ofM#IE*@mm|o z0a^l++-{iYLSVAPOrU}9U}F9GTbtwzS-~V5 z2NP}m_$HD$BmtAI8BDy9F!^Hs(1(dNFb%JUsdyF1BC3H&`R$}AOwCJ4E>Rdv(iJdK zznT&x8AZA$tzj_lejia0B|EOO(lx9Wt{G*1V9cQgC`bR+~`b_ST4(~ro!E9>Q#hkxXRfha* zN3p-uoaZ(qD*^qIX|MiJe{Js0UbyBDm2qZlcKg05>h+toBvS!>l_Fsil()-qj?+Hl z)VY!d4llFcl-q}IGx3v zQvs(2~@&i3c&ux+Ar6^dr^oJv$1sM}HV=g#B2K^0YPoqMIej?(M(BAFEEOa1e! zn#z)XGB@3?g3{Q_%^UWzlnV4zC)pL~U)2mb3tyMRD_ojS#dfswYTe7GMn26V85iht zO=wJ`{;qbKS9vapD%_GePx@FqRr+7cOkULDE;dyWDnCEokxAtrx0!D}6il_}rjX1G z^vzBedQ%VUe$9XK-i?ZFl;PtPb*7wK_w)TPU&>$W5arZU&v$u~73JSI%4fdBjEe4; zAQ>F!!!6C*O(pe2@;m76paLFW;ScNCN@=yepUI=@Y*eBSTrpg*Kun&>Euj`v+R9L8 zPgc+5RIR97PW2xXUihU>nEHD_Z=qD>Lh7DQFvf8 zJI1`;q)jqH&?hX^`<|&EbWT8J*AVlDVYk4&{C;M}s<|Xf1pUNnOFNi0H{Aq9)$TL3 zV{-+)bZ#?`ns&_OU~7Yxl;ebOwN`Zry8@=$58lX&IV@GEJ}FAYH6lmLKVqQLI1SQ_r*++ zlR`^mxAHN=MRk|t`^{leSpg(t1%1{!CEpl)alK2t&yO&UPtOzCl>CxGduWm@7W8AY zWWnX3lP|*G+sL?H)G4yb{~BXGF9*qNLErX%-y+8QTaHVupXM@TL^766Nv1QhU7Kg} zy=054&)?CoCaeQ_SUbTbNn0huB+>J7IOnc{90UGHqpHnh~?azu6Ro83rnf zvtOo%y>PN8SvKfr=PYD|9a6a~KK{WcOl!$6@$29=VSQgiGH=lLetC~k7+-Gmitjo) zVY}SwR&dIyhTYlpekPyn;&t&b=d1cF&0GY-Xur^vk7jd)HOQ6E87C^FqFb|+&|Lc&b)^17Nt>AQ-&m;AbzbRyLhZ@NY z!rTDQfZ`C5!b~aS1*bxk+M1GSUIg71Cgk?~sC z6Fk(cMly{s*WjGk)!=U)nKHuBCBa>4%`%MxCxcU`#%A){UhNABPVlx^YwmwE_^L$I z+68Ru;KJ70wg1a?vvtr2KD|&__OF^;@R_2WvL7dw1?z71BUwtAr_iW75oERJv21n6 zNKjofhuqYzo}gSUC6c*>xeLY9mxKD2r^pFxJs-4&z9l!{dLpRj#pp~vTur=hkX5A7 zx(3=lNTh?YZi|Cyki?=3Gr4i`UpE9zgwJ2^m@OW3^`gf5I%U3~^UqyL))VGE^uVs` zXW{$nOOHPb+${Th{p|jxz!NIcBohjAA$D&+6X>uxLVl}Na$xhu8u`Y9%)k{AgERSa zF|bP;|4C~@`;=Z_YP08tipwg2-r2b`xpaGf2?VCgPiPzQIX=$5s{w&93&%^PVoV?-O?f$2}n=8A!%lpSn zvXx)0UFIJ#S*85H{JcE3uYPfZe49qU_4!3V(AcDLq}eZ^)P-bpVNOTeQrIc_@9w7M zma%?C%f4^&3HS38>0L>(yfDvW+j)JzLt3FK^*JhjQp3e6CahI{g%RB<|I6XKwRp_; zO0lBq*~VACTQ=CJ7TG@ZJy@17lh3!>sleA7ejl6H8s{tbb+Ou>)&9OAdv!>L80Ltm zXYKKg7|Br!uT%EjDEB~(w^`g*+u`?2o?lPJw_^dE+p(7KHYB?Y^GjC7Z98`T=GDz&-7?1xWe!8YlHjpL z&O#*P40BE>lOdlIAKf*iEn0mn3r=ci>(}}$G`KgD7dS8-<)as~a*Ip7m(R7O23vgH ztbBM1f=Ff>=BBJjll2ivd$gsAZ;?;i-{~z=ev{rhc5)X5Q=gZMT;1+~Qp%l`xY>xaHwI@0DtAwr2Q! z_u^L)*mi;MxtFV?CdqWeT$fe6C0@qw)3!x;Bzv{iH*Bl973h@{^KmA>FkE?;*V5TL zwAP!+d(~BVYE{}T_DcHi)J(3S<=#Qh2Vvi|*wQVYtLBJnXML^oOrv&_EIG`RNi$`5 zUbfEHrbZk*Ew4V%cJkEsoZ=sw$w5@m6Y<<|(qQ}YQ_~(*9f8{g`-eP4|D2i0N0gPX z@`zEL*lwvL>&4npWXXd#x{ST16c@k19TPGv=I}$z{wQ%5kIfjC9-1vfR@8f^?6X9dY~0 ze|9FXagtVWbNlbN?ytW>ZeflRyWHK!kJh{GC7FGg+w)rZ_R&lG^LLGy79KsQ-Li|p zh&?JQ_G2dB(eAA2(Hj?c>0QlLIhy9-tydMj?C25kQ!}}b339JphYx(#3mLlW8u?+# z?xhLEt~{RFBr6c}f`ZDuTrT1t7Jd+c-Rc_ivHA{VutlcXY zr8c`g@1q-C2FBuM@*{tpi*=D(`(n@DY1#bN)ma)s*bqXY-5Oa!diVM38%x3A| zef-<`bYF@7o#5xruS>dS@+PmG$ak)nl-hfFKHJ%_!(i_%A4g{`FMpDGh`C1`3uK*D z6YlNZv2(t&Jn!h<(?>ra@eC0m*@&2r)EHfTacQ7gUOQ;MF;okwzW8mLsdJi6X_~ZEQS0=m6R#rl#^Gs1g(?DJ5Cf=GMXV2mB0|$Lg+U2( zWU?wq71WA=6=`k+#W)i2fk6~2pjJewsJtRP{h#0c=jivTg|^AfJ!kK|_FC(n{XpX# znR$yx4?4f)?{ha-?7d_350iesW6i3|N57rvx^vo~+|ehNUH|`QRf_YfzFid`_0Oh- zcTTEk9rdqox88Yb{lZa;ul@4xb2<-9=szm{cE!M(-nnel)?fM$e8ZGA>h1i;{yx8R z+wc$lRad<|a6sKl{uPzq4^$@2^_$AG^fNL!Co3YJ{W|@*@2-89UErV4JpC?5x6%LY z@O6Km_gUrNdC%&NC+;f!v-zI?s0D*=da~i3pLX}w&)nqPt%n-=+_UNBS%W4VcHVPS z*2Y1f_BuWCrF-IkpAY)%>sv>*ed!!r_T`e1LoA-b=2MT3e5uEM`Wc>_<5ltJWg~0; z`Rd^D$1_Gged&J&U-8iocTdkh{r7pI{r&6jHto26NNfI#yVpz|JLHA!{=472Y{B2> zjNW&!>E-w`1FYXo;*Ed%g+5Hei>h?pB>8iVOrgy5hc}QeZI}(N2rVD`&z%f zb;OSSul{{5>E?6HBVMfP_Km&x$nfkzuAyB$qQke0@#trfavs_86H|u2HY7N-T^l_7 ze|7-f)k&SKKpst}6GEd&<4#9&@j`=kmN&)`B%*ZCE4LiZzqxu(Fn{DQn9bv(~IR zXR~oW9D9L1!QNnxuvgeK^4wPT5_^ih#U5j?vFA9;jq~Q%i|k4ECVP~<%AS?yyt0?s z)9h{bID4HvFVBA^7KjOAgBT%Jh#7eu zWO6e(np{oJmgnG-%gO2Fc5*zqo}4ew$E6lf6Q~W;2x!^A1{9S4xHIdp#jigpmGv&Fw)KY3HwUru6 zt)=G5^LnYp)MRQiHJVyY&6el*Qp>67)OKn-wVs+U&-VojfC<0`U<9xNm_eTV3zh&= zfGxlnU=1*bJP#Nw0ww{QfKk9IU>42@hztn!>=uq>DsYzxK(>wk zFfrH|j0{!=Gs|<4!O~!Aur(MPtPSRt=Ou&1!Q^0bFgjQr%r4JS2Fru#!S-N$us)a{ z?9ch4^aAt*^ak_@^a}J0^4w*533>{83wjKC4SEiF9y7fNJqf)DJqo=FJ&Qc2nO=sT zhTeuAhhB%CN1oqIFGNp7Z$ytouSCxz&vmAkqNk#_qQ|1wqUVz5J=2TPlhK>eqtUC; zv&nOy>E-C@=X7 zr6;8~rAMV#rDvsgq+7p5nsH>O9XSEgr{=Tg&4(^J!1 z(__1MIdD2~J8(R3J#aqq zd~UcPI3c(pI3lIVlRVEGE(%TxZVHYHt_sddp7RZt1*ZkK z1;+)~1?MHt|Aq^L6N4LrBZDi0Gn40n!==Hg!L7lu!L`A;!M$-FGF%*-9NZin9b6rp zojgYzE)Px*ZV!$Rt`E*no-Ym;2qy?P2uBE42xka)$T`e#iExT=i*Sr^jc|_gJaV{5 zos$&YBpfANC7h)^ryMR5P7`hujuWmE&QqRW4i^e13O5Qz3Rene3U|sm(Qv77s&K1t ztZ=PxuJXKdxL7z@xLG(_xLP<{c@8>UE}SmhE*vjhFPtxDqjEkqTriw4+%Oz5Trr$6 z+%e}^!zIHh!!5%x!!^S>%k$LXqT!_Brs1gJs^P5VIqPuQaN2O&aNKa+aNhF#b+~Xi zakz0fa=3Chb9pX1TsoXO+&UaPTsxdQ+&kxS!^OkN!_C9d!_~vt%X8e}^5OL1_Tl*9 z`r-WL`R-@|XaZ;hXar~lXa@4!ceDgF1+)b;2DAn=2YDVmS_GN|+5{Q}S_PT~+6Cu| zqh+9JplzUWpmm^m$n)dTLeNCeM$kymO3+N?x$JE zgGPf^gJvVop-0O>(?Q!o<3Z~|^O5J%qXnS}p$(xCp%tMS$#d(`lF*dUme82cn$Vok zo;Yt^*P?_bg*Jsog;s@TCC|A>%Rq7IA=ij4+p^2f5p^>4Lp_$2Z@zK)I z)X>(@*wEV0+~j%rXmMzAXme>X&f?{~dbCJ1Nwi5cO0-HeOLf$38M|85u+8O8Oyl=Xvt{GXv=8KXw7KOa-INMG@3NpG#WKp zHJUYN3^Nx1EgMZ6Z5xdntsBi-&L2PvM-xXIMCgm3DDBf)X~<_*wNb2+|k~d zM}QWOCXY6cMvqpHW-sR$pyi|KqwS;dqxGZt3-`Z1-ynU*$A9r>cm1lr_fO~$`?y#WvG{gc-}dw%nuydUQ!^8P8!*Z#@%JaBi~pIl#Q$>;y$dgYvig)9F3 zKR(a!!Jhx|`IZ)B|Bufr=O;X{?8UR(kHW!|&vJkI7yauj_lt8HxqpFG9cQ?ob4R{% zhWp#++$YX(zvaAzog0hJupa9k{q_&mXF%2Kf3RM14nujY{~xU9;6<)KSl`EnA3M!@ zb3UZL{wHUhW~}f;!8c&cDdJ&L<>jY{ zkD|Q4ekWe!T!@sfR{l;r4ST2dcj9Z%%e{Ul-Z&4F_`74~-rtBv|G%4mBR(%5J^nZ1 zm2)$R->Ys;|BZN_)F<&P@g2VMg{AL`FLbdr3*Ih^E= zx(gpaNj{l-srMxLC3eP z^*!}G(fPpl)c1RrSA9>tm-9W&p56Byc%X3Gy6?aT#S;f=4dSF8LOGGW*9Lj)GU@oRB@6=Ntvke7Jh>QSeRr{PT~3 zcjWw#2@`i60S|3@WbqO3(an#HIs#sjb47Md{p&DzYIE?D!{DoPSFSk>-jef1p8Me1 z!{D*Ee@H(JKAWEP#W&zJ&b|!G`%W zJHUt6?HkwuUgR8I=9WyDeDZ7Xd!n zst$thN7}3h!TWN)%Clc?_=0|5^oNtbpg;IYyZH;qll0LqFJA+4LX!!$Uva z`5*d4IXA}q#BZO`Pu_IUTecADKI7#fR`Ea<0zFm#_U0KE?N4)`##bofmX`0N=uS-taHaMQ45h zA9JvH$OrH|!{Z(D$@}m*?|j<)KK#z}cTIR7zDLgISuai@fe+fB^J5Ht zXx5hY7<`eO+cULjObk9LzVGT7{F1iX8iQ|=^L*ys_{w|mQIDSA_#XU}E$6QH;H%`E zpC`|r-VL8MMfrF){8q25=H2jJa{kYa*WI)mKJ2;L;@$9LKZTFK3tuMZ0zH_&SasPM+KJSVY!#nVM z?Q8e#g71^_g<5}qVi$bi`LEXOf*(BfXpdd+g>vrDdwC!2girj>$!B)LFZvEn*a_dr zdF{+2>WG!>gpWM=@rk$LCzpS@>uvZ-Ij5+#aNOJQnO9!#c^iIn%;fyH;X671o%u!I z|G6UyAA0j0i=yzObuZr+g)fzJjjo=N9feQ*`s`s1esx^n4Gq3k&O7S2-mk&Ow%l~J z20v>&nWn+l$~j1%-v4?8K6gN6Fap2(ZR*_-_+B|5Y4ZE#2z+qETL;_Whqu4c+74eV z=O%so$*^|#U8WtuOfBgwKCo>-8r5{&z<*--Pd% z^PO(I{mnM?fN_f#wxJI^efYjM^a45esd$~e4L#xUf*;;MU+7+>y@B2!=RwtO8utcz z#Mpi}yn#Nk=GWpk&@1Ges1L@zw+%hx<15x~L*F9ddruzR%Cyh8}W#{Pb4z z5$Av6ThU9HQ@~uQbN-yZ6+LBSkHK5fS4sz8wiUfa&YQaa%Y$3cV>Va5z6E_I8k)BS zy@t65%%OUJ!ZlmabM~IHZ9(5zG^_J<^d32%>XzLrUPlk=U;oJK=tJlBy7_hVB00Be zz`j$P(UZ1r`(!ivQp&m)HlsJmc~%cTH+VC8)Z*9wu^D}8d)&Mky-LoxImfi+}K{*UPYga7cP7iy^gsN%+cyN>vj&^zV)uJ=By-h>`n zyT`E!ee{p7Pi{mnWljcjz04IGHln94xTkR=`l@r?@QvuL%+o-Bz4tELM)cTAqQ_oB zpS54}?n~&k%-vuP*uXmh#{+Qdf?n(K09@N6Z#^CWIrr@H=^w4b18}|P#dUZ99}Ik#>5zXQ#90KQ4Nrx_2xd(ZT3#sk1C7d!ypTh2U#2jJqp2cE$LaNWkX zXYc^XId6Z>o%9SIfYybBp1}if%et$c!2=-Yzj^;SxfTz=o7e7LiwEF>1+T5e1Heoe zJOF9K>ek``nEUyFwRixW_x42{`;{mWd{mN=Q0L+}h1F-eBM^@tj zSlm8fH6DOHeJfYv0g&_P9v}D1Dm(xuoqJc|0r)Dhc@-W2Ij63C#>7>400NH;T7?H- z>_fd);Q^5I>kcmJUWo_b(H-K+Uf}^~KDB)%9soJl?yIM#t;7THyWyUdcmUd_dRF2A zkn`>auTEWw2cY+j-#(28;Lw@fPvZfQbMPjtocA;yfJYj~J&gyTPksNV@c?ur=i`lB zW`7zFz>c?m3*!O!^OyZ$JOFZTp8C|PFdl$gew!A?1K@qoAI1Y9=jrvGeSR1Zz_piJ z!*~F$JA7;f9soIK@A2uaEARkpy?4n9JOJs#C#}E(Am{HD*7sR~2Vno&vK4p$cJ4E* zzyl!X@?Adh{pEN7+7E78jt5}Qz|e9$0L<#a1MvNXAiU&Z>30(HcrAzSutcm6>#RJf9 z*Qq6V0Ob6@=l+N;!2>Y3=L<{l07NIwUxEjKnL>B~-o1SA5-=>rYSN0r+Oz{-^K&$hnIPmTq_o4?y_( z&{KE-&NWPV3J(CYnD78-Tl+nQ2jIYqS3ZRYAn>Z|DLepjPGi%FpP$47aP*?YlXw6+ z9((&qJOFZj;~Up6eG(7A)4QfUi3i}k!DFAq10d%*s;#}n(W)D(5|ev8i3i}qJF=g| z1Hh~&JOHPv4llq1Fzx1#7T^JRZ|t@OcmU)a$ZcQETYv{()Rm7dzyt8r%6k^z0g&?{ zea~FA01v>3K4lB=0C;{(TYv{Z&W(I^`q%UE09-%jgZX#>-X6MjJ{|x$PjcZC^XKCM zINCC4J|2K8z8^Io4*)Z!@BqB~bk%%30JiKN^YH+TTADK-4}hFMS@!vN^Y8#HS+aK? z9)RM}k$HFkyrB4?v&gpU%}i0Ll55v)vo#;sKa@cEwyg0DFF#ITsHAGq3Of zTxPjvE*^l}dfqk{55SubTr(FBfSiXpw;+Em9)MqFr_99zuqFLO5D$QylX=H29|Z9L zTyAU&;sKZ}o*l*mAm?ZHdA>1-2Vm!hM}l|&-iX{C!~-DbYW{g%?;sw4LI17@;sLl& zJX?$hK+fB|`J-Rw-~m{5@8LOk03OTvbPgT>IfwJz)vwIK1K?>`GY1dAZ4(#F!2=-Y zbDp#O!8v#UPV5{y2M@py!!2|00LZzW#y2mVg9o60Wzifw0DZQb=imX5^E~s--_6DY zV2JITjR)YF)$h*610d&o{xWU-Y&-xP=PjF!2cYbwS+nr~$oZdr&bfa!9)M%@gJOY}KM!cmS9!h6mt{aT90Z0cic@zFBwx7R?v5>Bf`a&BOyB=aiPr`*0>6 zfLSNoXW{|)<>A(ucmU-5(gSOj&BOyRVkjf&cFkZ zbBB2b9)QHOGfj8^n8}6*;JV!Jn(zR8JNaM}9)Nwn#GCK{Fsls@z_VpLn(zQLe)d`u z9)Q-Am_Lij#<)#2cX}*bDQu0B}|`RYI;9)R*OpElwF*mow@hzCH@Bw2jDZ?U5$7Eg5TWMhzCHKF80qxJOHupD;x0uT;u%zdA8U1 z&uhd3@WGp|Mmzw=FDPup10d(zc3zv-hzDTT5kn&$fUBQ58_=J3P0qhPSko2217N@T zSO5>e;hLiXJOFYo?j6r00(by^IkGo^2cT!4j{|rBann0l1`aX#fv^Vc5a|9soIacfD(N z01v>#RgD2W06$(fEr16=&f`7skUxM2 zVAre>0XzV5e(#L(K><7f56!_vY!T1i;{lNKfxk~b zKY#}y@3nIScmTQ|EDzuTkaL57D0T(#0Q@)G8NdUe6*&UB2Ov35`0;!519$))X|V_J z0F)}Z0XzV5&hVyVSphr%3#MfT@Bm!cBO`zZK+YcyZL$XN0E~Rf62Jq{Il~;l10d%T zU;dIYfCr%Ki_`!ffN^E10XzV5Uh%3UDFHkHw~t8)-~nhqr3CN*$T`NJ`IG=2fX6RX z0(bxpr6~bC0G$5EfA}*V0KSh0fS<<$Am<+QdUybMeLMiXA07ZX51H%11Hkp+0pNP^ z0LVGXd>%Xid_Ft?d|o^Na(*)R0}lZA2M+-E3lD&ttIYkx1Hk>o1Hk>p10d%uvmST= zSRXt9tQQ^tIft3`!~?+k;sId2@c_vA%_`y!Z>{mPh>|Z

}Nax>~A~(>~}l>a{e>%fCqs1zymCv2Y`6T10d&1lMnC!kRR{>kT386 z$hp(x6FdOq7d!yu8$1ByA3Ol$BRl})Cp-Y;D?9*lPBr-q4*>ZM4*>ZN4}hFsO+Lf} zKz_snK)%ESAm>_>Pw@bdU-1BtZ}9+-fAIj2kMRJIpYZ^YukiqozwrQ&&+!0|-|+yD z@9_Z0`PkG0JOI=OJOI=SJOFZTHuVG#0QChA0QCkBfSjjIJ;DP(eZm7ky}|<^=WJ8Y z@BmQX@BmQn@Bqm9+tfom0Mti30Mtu70CFxj^%M^P^%V~Q^%f6+oYze~#sffo#sfgT z#seVdcvH{u08roY08sDo0Lb~?-~l`U-~&7W-~~JYa_%>H0uKQA0uKOq0}lZB0}lXr z1P=iC1P=gs1rGrD1rGpt1`h!E1`hyu2M>Up9}XVE0{}k40{~va10d&$gQxHSfUocX zfVc1f$a&-7F+2d^Gduv`H9P=v4mo%Z4*>WM4*+-%4*>WN4*+-&4*>WO4*+-(4*>WP z4*+-)4*>WQ4*+-*4}hF!4j#n=06xV70A5`sJOJQVJOJQXJOJQZJOJQbJOFb3Id~Wk z0QeXW0C*V>fSijCp2hB3U9>)U!KF0$9UdIC<=ct3{@c@AD@c@AL z@c@AT@c_^d-~pgNzymF4kO(BI(!px?s-Am_u=58?r!Kg0t-zlaAw&W)#^!~;Noi3fmw6Au9W zCmsO$Q9J0MH-f0ia*T13>?b2Y`MW z4*>l&9sv4n-2;%ES5H5V2Y~(@4*>l-9sv4xJOK3bcmU|{@c_{8;{lNK?coFP0KgC6 z0e~;S10d(#UoZFs-2))_1v~)o4R`?HAMgOcN8kZ~pTGkEUx5bz{sIpGd_zgS& z@Ev#n;6LyHz=z-gfFHpF0AGR!0R99I0DKA_0QeO=0Prn%0N`Kn0KmuK0f3*u0{~xx z2LS#C4*+})9su|qJOJ=LcmUvk@BqLE;Q@dj!UF(bga-ir2oC^!5*`5fB|HG|O?Uv{ zpYQ;{N9i5_!B610DpxC06q&30Q?pn0QfFE0PtUU0N}&$0Kkvo0e~;V0|0-9 z2LL_|4*>ic9su|@JOJ=-cmUwz@BqNi;Q@fJ!vg?+hX(*Y4-WwR9v%SrK0E;Me|P}k z1MvXB58?rUFT?`?e~1SFJ`oQ9{30Fz_(nVc@Q-)^;3M$>z)#`@0Dp-G06r5B z0Q@E%0QgQk0Pvr90N_LM0Kkvp0e~;X0|0-D2LL`54*>is9su}OJOJ>ocmUvI@c_Wj z;sJoK#RC9;iw6Kc7Y_jZE*=2*UOWKszjy%PgYf{s590xVFUA7^e~bqJJ{b=H{4yQ@ zli-{20Kh-v0f3Lj0{}mb2LQhM8{q+fzs3UqpN$6qej5(}d^a8d_-{M_@Zop>;K%U* zz?b6zfIr6r0H2Nr0Dc`00DLHD!UKSw zga-h92@e2z6CMEcCp-Y?QFs8*r|mC-DHF zSKb^lv-> z=;3$((8uurpqJwTKtIO=fS!&A0DT<~0D3zf0Q7e}0O;{}0MO_00HD|70YJaU1Av~7 z2LOE^4*+^U9su-z{^e`_j_>g^{4Br2@A4Y@Yl+w7wRsQTi}&QcxdyI z=GyrTd=@?vpN-GRXXP{V*|`VY3+@T`hI_=l;+}EuxQE0J>;d)ydxE{e9$~MrXV^RJA@&k`ioL}iW3RF2 z*n8|j_9ACD)R3$-U%YaxpoX+)R!pSCg~J-Q;j`IXRu&PL3znlk>^_ z)BtJ$HG$edji6RgGpHTZ5NZiEh1x=mq1I4ys6EsmY7sSw+C+__R#CI4UDPmY88waC zMvbG^QS+#M)Ie$>HIdp#jigpmGpU`_P--bPmD);;rPfk&slC)-YB4pL+Dwh6R#UU7 z-PCYuIW?WyPK~G5Q}e0)x(7gD0WbmB0E_@u05gCczz|>wFa_8Gi~-gFbAUa-AYc(N z3D^XT0#*UDfL*{aU>PtC*anOP)&cW?eZW9qAutix2#f?)0yBY~z))Z*-2))76&MSw z1?B>Kfx*CHU^1{77!9ljW&^u{;lOfWI zl3+@(B^VQ|3FZWQfPSr&@0e0&^ypW&`Z!$&|A=B&}-0h(0kB>(2LNM(3{Ys(5uk1(7VvX(96)% z(A&`C(Cg6i(EHE>(F@TN(Hqet(JRq2(L2#Y(M!=&(OcmGpx2`3qW7W)qZgwmqc@{R zqgSJ6qj#f+qnD$nqqn2Sqt~P7qxYi+q!*+oq&K8Tq*tV8q<5r;q?e?pq_?EUq}Qb9 zr1zu;r5B|qr8lKVrB|hArFW%=rI)3rrMIQWrPrnBrT3)=rWd9srZ=WXrdOtCrgx@? zrkAFtrnjcYrq`zDruU`?rx&Lur#Hs~K(9{Ej(?vXo?f1wp5C4wpI)DyAOAlb09*i^ z0Nel^0bBu`0o(x`0$c)|0^9-|16%`~1J57e0f38ulYpCmqkyY`vw*vR!+^_x(}3H6 zxfm4B7fn$MdfpdX-frEjIfs=uofun(| zfwSTH4LBUQ95@}g9XKAi9ylMK|9}I63xX4Z8-gQ(D}poP`4KoIxFk3wxFt9yxF$F! zoF1Ri@FP?va1A_~L6N4LrBZDi0GvoOg zI5fC4I5oI6I5xO8I5(cZfrEpKgOh`sgQJ71gR|rL9XLF=JUBhLJvctNJ~%(PKR7_R zKsZ6TK{!IVLO4U7AA&=KON3K|TZChTYlL%zdxV38i_|$u!A-(Z!d1dq^86AUCR`?* zCfp_*CtN3-C(l2@fx?BtiNcM-k;0Y2nZljIp~9uYslu(ovBI^&x$^uK94uTcoGjcd z94%ZeoGsif94=fgoG#oh94}lioG;uj957rkoG{!l95GxmoH5Uj!6CyX!zsfp!!g4( z!#VT(85}fRG@LZtG#oWtHJmliufbu%Wy5L1ZNqWHb;Eh{{2LrNTsWLK+&COLTsfRM z+&LUNTsoXO+&UaPTsxdQ+&dgRTs)jS+&mmTTs@pU&+ozE!{x*2!|lWI!}Y`Y^ZXwg z09pW=0NMZ=0a^i?0nZPjA)qCoDWEN&F`zY|Iq>`;8U$JdngrSe8UwV=81{3RL;S`3;D z+6)>ES`C^F&u^mPpyis>%?RxX4GAp?O$luY zjR~y@%?a%Z4NBLdgeHYHg+_%|g=WR`t7uqgS!h~lTWDNpU1(lB|B42N7KSEkjs}hvjwX&a zjz*4Fj%LpD^JwU3>1gU`>uBs~?P%^ie~$)_7LO*6HjhS+R*z=S^ZRJ{X!&URX!~gV zX#HsZin2JRN9s1C*L=Y8P}-UF1(~kwjXAw@WA;JfRPymfryVn#nXV;nXW295J5 zUd8z>7hG7e?xM0wp1w5qA9H%1tsH;F*H`wxdV8<)tDd~(*WN?=wDm1gCwe})?t&Yp z-uUsq+&4ey-EzyBexBPJZ;$prGvKN_9=LPWzz^;^HK=sR4ZeGaHVs=de9MT~-Jg#< zde3qHFQZP5J~8Hpdk@_gzrTI#hS~)WjDPUfhkA@VJ??{tSB$^sk@M<~)UADV(7&w{ zwoUL)G(GmhW7khQFlpT6Gm~f4r%#zT#r*iR$4@+d_tf1}FMeX~6GxxuJ#F5!{nJXP z`=_s&zJGdpLsi4*hB*xz8g@1uXgJnzs^QOuzr??%#McMJ-)#`z8!dh&yHEd+_nvlCyw=4}?4Ek})Dz?xNU-U!k~Yz zee_7(d3E1F$HwnJbl(s6o)~j-^e>~1`;Xr9`N-Ja zTSlxI-Zbpqp*Q$ShnyPp!Ck8cK5*w%cbpjz?caF2=e9Hbw%qcd*M0NH|C)N^1vh+h z-9%53+SYeSpI>`FdCmD%+k5rD`s*vlUvai_PS4zbJbh`|CF?G_u%hLHit{&|*W=u0 z%AI9P+?lQ!&eM+ZMTZLp<;U#3b2sL=vKM5YNq;EqfW>RxX6%u=I7Ly$|M}(FerLoS zitc5nOutY3_2@5yx_19u_0z^5OOGw?w0uA9+ux2neE7SLQD1-g)zB{!U-%9j_2fusiGB7k7Dg{t#WDT@m?W$E>%m+RnJ}YtgAWynVhxRYjRf? ztvYvQ<A)G+*!}h>^*b;jL9=xGj=ykYPz`TaAR}hn8u46PX%IuwSg&t zp@Hhag@M9AdcY7+#J}m{>kGx-4He&8D}Lrw;9~Lf&5ef}FBZSQyU8V9YyXViGoPQC zD_;MPS(9d;nmu)nDY!Iv;oQjFVe`(+Yo6b4LHB}DL>&LZJF6V628Touk{;d~d)h&j5m zB%8Bp_K5Rt9_!W%kL_)BMtbE-J& zYL+;woin#Mw~MpCI6sUt$T-K0v(Sc!^VIUoxA(%+&Dn5x%Q>U&g)7?nw%t;sa^Bv3 zrJr1f=by6!Ie+l`8OnTMkS**niyQ zxo`e4IbS@Fe%Xs@Q(il7-W1OE8g82Q_<3VaJia#d?x~@}?@r~sszbNVePZ(`N1ov9 zC(k|erY*dG|FmOE+|xOW;_RR`(|3zAiQZY1)^KV_RRc3VI3r|BuMG{$2kmTlN}P8S z{qTo|rgKg;aCQqbVE8|O=I{AFKgZAWd;C7H!|U<7ygu*4`|-ZKKi9$aa9vy<*U9yA z-CRGPgU`d~;`8x2_0KClH=m#T!2RI9aDTW@+%N7M_mBI?{p7xKf4R@xZ|*zypLJk8 zSQplZbz;3(H`b4JWIb6|)|Yi=y;*nGpMAi7U|+C5*eC24_6_@oeZ+oZU$MW~XY4oj z9s7@c$bMvBvOn3U>{s?J`I3-?*TjG~ECZ36F;+r@p-idqS9~=P|d0ya|nF14y7P#sS zfz8eceD|Edh~Uh90;_^|!OQ~$?gqP`EAan2qKBXlSuT2+644LM5HXIV{@``NL0ltvj46T(flq;xf!Fy&a6`8Uekmk4DtIoq zvLk|TgR}ck@P4g=JA72|k8qgqpdSk^6+Twi^8_ypxBR-`r^gA7d$Hij;o9Nr{~*xa5wNTa46>s9t17}J_1f* zfZzoNir#*`=+D0rJvMzZy{=vKtMr`ojrpSYqkp3ZqmO!6^g>3_&-4~O34H~;LD^{5{|2=lFSkkKgBYcs*X1*XMnBKi-%3=Q_9^ zu8ZsAI=No1o9pLu@Ok)Ld_F#>{&~gc=JRtOxF6gX?hp5g`^A0Z{&635o>bgd?l1S5 z`^|ml{<99O2kXN6uuiNO>&E)Aj;tr^%KEa-tT*e<`s+HD*bnRr_6Pff{ldOs|FDnP zPkqF`Vt=vE*l+AR_86uk2g)FZ-DN%)VxSv(MS@?0fbr}7sLl~ zLc9<+#1C;qJP}vK7jZ_s5qHENaY#H8m&7M=O1u)c#4mA7JQLT%H*rq96Zgcw*a9m5 zedo^xb#Bi4*XEvSP(#_b^!e_$26fx}%lq7Lyg_YEf4|Q~-!!Oi-g2f-__GG}(p`mp z7w&3MEge1k=DgOR_B`Y5>sZ~O*5;4yyK!cNI`NXJecyYqK}|28*Z1N64XWwI<$c%m zY)}_eKHt}u-Jk}xz1nxpvFYlr-aGm}{LXZ>S9`4Q`>Up_Z}#2Sx3zA%`i~vo^gZu} z>FT7apZoU6o32jS{72u{I;N?HWvSI4ZJegg-jh~6apE-f4XdqsQ}1c&3{PS8gg>89 z4^47azpp)^ZrgZnb?fve)U$^wsw=L2LVeEGv-bGk)zu$wnyT&@e{J>IQB&1_ zuDY%|l0Q}5`R>ith3`JD`hUK?+A!g9HKpLL>Y1gFt1GSwtrW553E-|+EZU``(?8F&3DtQ-<>~MjZSN-F6uE^{bcs6 zYRmRX>XN5|)hlkFq*|8Euiky=G4+?f;AqGwlB zf0Z#&o!z{$T3s|jtzWyQ`sVxz>bEPKtGk!}TYY!g^VN6e{adv!e4%>C!bjD2X1`c% zO?y=R&l8)f?+?_ey&rwGdcyCIs3*p3uCAn+>vUx>tVIj@^O*(=YDm- z;*RQ!k@u;8j5$(0^rd^%$FBUYdctpG)HjqLs)zL%qrUawkJYxO(dv|?KUas}9i<){ z_Dl6i^C;C)_FMHiH~G~MJ5C9P>>l;9=F`=t$Vm0VyU$ifPTj3;F8ZrlJjuV*dlK(9|-^}AKQpl*oz zvNv7*cG+O{p_Lixk~asb@nf0l^HL^%loK_2bWM>h3G=R9j2! zYTw)MP%o~{Q(wKeM!lvrUoCrlfO_Cmff{W8Pw)Qb<_q@M11j+%P(U+U9i z&sBdva-;gh-nPsBg`xR15E{ zQr#_=tLOFpr}}>E3Uyq0FLlTFSE|1nuh#$NYyOV!@iY7^zr*kH8oU;-$!qf-ych4u zdvgt33)jT8agAIn*UYu^8Tc%GCO#XVk zhuBN(DSdB=J;q*R&$0K|gX~52Bzu!R%3fv9vUl0T>}B>edz(GZUT4p<_lW^wftVmR zh!J9im?3tEA!3P`BDRPzVvU$1_J~1Zk(eYliBV#em?d_JVPct>Cbo%jVx5>L_Q?U{ z0&)VmfgC}uAZL&}$RXqsatgVH97C=l=a75ILF6KG61j;SMXn-ek-NxY`^bUhLUJOxksL{`BxjO4$)V&@aw@r%980bx=aPHL!Q^6cGP#)?O|B+qle@{` z6rc0%`)aff_-rpk`1zs3Fu6Y6`W58bht2=1_a6LDV8@619mM zMXjP{QM;&N)G}%swT&7_t)u2q`>27`LTVzlks3*@q-Ih(siD+TYAUsr8cVHph?-07 zr3O=rsmau4YBaT)noaGdhEvO_>C|>=Jhh&hPwfW-h(Eu@pT+lg@O|;~JNS9=`#bo3 z@p?OWJ@NYOyuNt9cHU3Ce>?9luBV;r5!ctw^@;0k=X%BUw{!jC^R)AM#OG`0^NG*f z&gT`Mzn#x7?ngWKL)@Qs?vJ=%?c6VM|Ju2K;(kWBpW^;TxWD3lN4VeO{ztg~Vm%_P zhghEo>m$}H!g`7Ii?DuTJtM5ASlN8{MA#2ve?-_HV!uS#FJk{h z*gs-FMc7Ybe?{0|V!uV$Z({#N*neU_M%a&He@57!V!uY%uVVj3*uP>wN7&C|e@EEg zV!ub&?_&Q)*#9CPBE*A;j|lN0;w3`7i1>*RKO&wY#FL1x2=OK2EkeAB_=^yKA|4~e zqlnK4@hRdpLcEIjjS#;go+HGwi0=sTE#f^wyo>mc5dR_{M92psKSan6B40$v7b1T| z$R8q~M93#1zeLC{BHu*FHzNN;$Uh<Ibqh5*nrBS~`J=3UXqP}U= zH&O32>Yb>68ud@qLydYU>Z3+|6!lW0UW)puQ9ngJ)u^YUzG~E0QExTst*E~m^;gtm zje0EVvqpUu^;)A|i~6lmzePRQsOO@-Yt(m9?=|YZsQ(%mKzyx%0mSz-Fo5`34GbWD zR|5lx*V4cM;)hSPKmd zAl60$1BkWKzyMZ=ph_%+h0AlSmFo4(#8W=$A4Gjz+_KF4u5PL@h z1Bkt(=@{VTPz?+q_L>F;5PMGp1Bkt-fdRzc)W85@uWDcbv3E5vfY{3#7(nc84GbXm zx&{UidtU3?O1p0|SUy)W85D zHZ?GSh*b>?AYxYo1Bh7GzyKn)H86mPbqx$4VqXITh+Lq70Yq-lzyKmwXkY-5J2WtW z$R!#WK;#w;3?Ooi1_lthM*{^kL~hc+03uguU;vT3G%$e3Wf~Yj8?i$kiGcK;&)>3?Op31_lthT>}G%T(5xvMDEwX0HPLXU;t4YG%$du6&e^o)D8^{ zAZm#Q1`xGH0|SU!qk#cL?a{yhq84dj08yJXFo3948W=#-E)5JIYMBNG5VcJM1BhCu zfdNGA)4%|t7HVJsQ5!YAKknI}fdNGA)W86umTF)CQCl@IfT*<^7(mos4GbV^u?7YZ zwOIoLh+3_I0YvTAzyP9_YhVCT+chwNsP!5cK-7K>1d#mmTgmTJ`}uilKfh1y=k<0Z zU!U5~`%(LOe`-J1L+$7KsQp|owV&&!_VanD{d_)ZKcAP{&*!K1b3ds4+#hN`_lw%k z{cBI&PijB+m)g($ruK9Hsr{@6wV(B&_Oo8pe%6oL&w5h(Szl^D>rL%v{i*%z2Wmh2 zgWAu2q4u+XsQv6GYCrpn+RuKY_Ot(}{p?3-Kl_u~&wi!$vwx}m>}P5}`$Prjh`lRv2a}FSVb1OzkH> zQ~Sx+)PC|ewV!-W?I*ue`^opze)2!HpL#&;r#?{osTb6K>Ib!-dP41|zEJzAH`IRW z54E3qMD3?OQTwS^)PCw0wV!%M?Wev``>A)-e(E2!pL$5`r#@2qsh8A#>L<0IdP?o5 zzEb>FSVa~Ozo#WQ~Rmc)PCwWwV!%U?Wev|`>FTTe*NDh9?-wX&m{4J{=2+J z5>M!_&3h#AhW_4MLlTeZ*Tyv_@rr)!e1;^R(LWoXF^PBd&(1wa;vxOsaF3FBNxyg8 z!z7;4?=AN@iMRB7&l)80n7%fwQ4+7|YsVTU@tnT4tZ@?W>1)p(Na8_#Z?H#_cv0Uw z?4cx{{Qtcr_E-{c>U)npn8c&he(U*6%pTxg}U1bMvY7MyL#=T z1}6Jqy*5%Kll`(@JE@_`ep;`s)YxRdt=C>^aIzn#_S2v1wVIlp?BDfTPE8lJpZ=cO zPrpy?4}bxZe1MJ(_-?U4h)dwdvxpv21xQjIyM9YB>5s8JAwg{e3FhW!2n6VNynaGfFvKKV^c6dlCRRS zD;OZjXX)4$43OlzbnFWTNb+GiHUDV3&kmUPx><0h0W*-m8KE=v}E_^s-=pB)_fqx?q4L|E>4JV1Oh)uJ_7dfFyse_tId1 zB)_ir+F*br|E~AqV1Oh)ulMR;fFysf_wrzXB)_ls`e1-0|F3faU;wxQ@Bv%_7y#}7 z`~a5#27p@tU%)kh0pK3MA8-+10JsV830wsj0PX_(0+#^>fZG7yz;%ED;6A`Va3Np- zxDoIXTnQLJ+&dNg1eXE^fLj4y!L@(^;9kIAa4}#2xEb&nTn!ii?gsn@mjecX+X3If z^?(83e!zclL0|y5A@Ctw5f}jO2>b|_q+@{p*Ozpz2@C-D1pb7J0t1M>sdH3tRp3>) zD=+|D7I+qJ3k(3)1>S}G0t3K>frsJ7zyNS%;AOZoFaTT{cp7dE3?O1n1#iQ>fdSy+ zz~gXpU;wx}@H*Tb7yvF0JP)@A27v1W@5B9p0pJ4Z2jB+50C0u$3vh>E0Juc@3AjZt z09+&e2HYbU04|b#1a1-x09Q%B0(S`pfXk$xf!hQFz;)8^zPRn z`X?0(0GCQX1-A+YfNQ1Sf_nu6z{S#!!OemJ;A-jD;BLVHaJlqzaJygtxL*1_k^5CJ z09-KrAlxt*0IryR5$+fa0GCWZ3AYRefNQ4TgnI@9z(v!K!cBt#M6J>}Yq)FrS5eDU zFaX>({ViNK7y#~@{ueGB3;;K-_s9RQm+Ra){WDxT7yxda{#w*p6$}9PPX7%T4+apm zS?B2C>gm_v?!f?}_N(;sqPFWCzo`8>=MVQ!|DU`M@ImZ{>SSD~$^1Z!sQew@<7ePZ z_#J+i*GS?heJ}BSVv3(n_80uFo@>STG+smeu3me=9=t;G&wux$$)DGI6J8_vdi<{b zGZMG)=DbGodi2-kJ(Ab^cYfnqcnz+N*AVZgU$a$FY&JzPI26TRt|-O|Mai#J6mylL z6nYfJ>Qxj+jiRLc6vgRRl+0R1an&hGcDP`b zZHlKbs(7q1#p8%8p7ey`ads%4%udDQ>QX$}-HNAFNl~oUlz`2a5->PY0`~HhfUzPa zkYAY+Fju7n3Oy+St2ZU!s7VQ=`%(fQli=2DbZ5JAl~1g z7hkDQE>!~UR%hh6o-vod$ai27Na-6Rk-Tg zjNZbi(QAzvy^grio1QRwogGGRW~b5X>N0w>yN%vb#pJPBO+lN@)m(i5hbv%?h2>@>w(U8Y!ew<%Vtm;*Me*_vxJ z2XY-|YhJlIXsa+=3o6Z4OO@GL*yk={0joF&vGh0jiW@}ch+3Kz{TXX8o*0O*( z;0T(%xgm3)IBfRjHJgKu7PGgY)$FyjnY~3(vo|ef_7=y@-i(CVThd|nW_6mq?k=-8 zr`zl;Q!G)N)e_9LS)#cPOE9n860=oUf(4b9pry(ZEb>@_Xa4cxdaJE8U{%tC)*4&Ls$_(%HTGt!HNC}JlizB!X0%yr3ZvrpV%8c* z+**^Ku+}&`tTmaP)*4rrwI;jUT2pFG3)yUGfiy>2$X=eN6j!8$@+;E<#Z_scLQk5K z;Y|xUYSKdKzO<0jpBBojO$)i|(n8twX`#|UnkPM&7Pp1cJQ?A%xV<^eo8FQZ&u>lh zX0)Zn3!`Z@>9Mr9Bc2vdPo%}29cl5*&a}9zD=nVgofa>(rrUBI>9)M`bWd(Yx~-rx zJ(^pUZY%Pp+lp(_Z5h6FTZup2mQ|Z>bJwNYa_ZAC%Kcu7Y_JgYM!?(WKn=X7Vp%alyTZq0PqY?(@)Bhz6o&$QYr zG9CGqnby3jOh=(7(`NT(Ivh2bwme^^!|4}4Q=92<)nz)e>oXmtflS32%=FnpnMz4G z(`Rqav^rZdefh1K){?eNUtu)U=8R?f9PvzBNg~td>=3Wfndx(NW%{zaGkv8>md9?* z3fpX1o;*iZ*j}FHwO3??^DDEwc~x2ALQhtW-J2D5)MVA<`Le=Jf0oZ)n-zA|Wrefr zv%;l;ERQpom9T}fJSE|*guOY->ukwNh-cN5B(f6Djx3+E zGb`ch%1UH+XC+FN?10^x?Z~xd2l5=*j=b{hpuHm7QBav3%&W?F6nU~kc5k+$xF$Q4 z=gW4K__M?I+H8lrF58h)pY13MWCxtVY+r6DJ5UnN_T@Ea2c0e1zJk{5U`boHuPB-w za>lZK#qsP=Ng~@<(vcl@c4qtBUD>{z?rdL~k`uLCbHcf{oM@gSC!ANF6SG(3gbONj zVtG|L;UZ5?-0sZ@7uV#(^L#ns5`Rv@UYiqk*X4wB>T|+nft;u_n3Kp2OdwH(aQIXr6UzrfM_zMYd7jr%k=I;MnHO_Zt*a{0c`+ zzOBHQU*YtN@73m4xa#s91@-wArGb3K70fSph4K}5IKSN8oNslti0`-NTitE>wT01q zn=6)I>xk#u+=={JXGgxn)tO)G>dJSxyYp*Htp();wgOLqqrfk|s&G^kRJbY&yaiPS zErs5K7Kg8(#py4oaMl*Ixa!2$^#v`ZfdY>!Sm1Ys3Ow#`f#2O+;B~bW)Vf*=yzaJw z&cbLxjVo5r>4+E9xDy4P&W-|~tFxff)m7kgcNcV)Dus&6T4;6I3Oz1Iq1RPjSnjGQ z6z^N;cU2Wu6nP32x3{pOxTetK_7zr?_zTP3wS^V#xqU zTI6uqifUYrBA=_gsMb+YRO_lN>U2~UwG?@ZY;JE+OL0w6joVk$QsOVFb=DTOxa*2K zo%Ka6Wr3ooD_GRw3Kd1&;i3+Ab5YFIQq<{cEsD9@iaLv;MR8ZGsIxd;6n7_zI!ii= z60XjoPIp&P!rfieS>|x~9hDBRqsrlT`5cwbT1Ta;&f##@J1R>94zY(FR%ghel!P7r z;%0}~!;T7PtE0T6&Ea=P9X4l7{A}D|D@i!&oE_r#I~{edE{D(A?WilY7MB-0iv7-t zVynBdI9Oa&9CUk&%S(L4txkWjwWPMV)m2vixMx9}2%-QPfaJD%+#h(HtF=wzO?u?csoOLA~&gPO%XPsNTT1mIFuB@WO z>#iz^xxFR+5?@JcNo`51yRIZwQeVUrNy42d=_=_g>2i0M zbd_0M?%J}byQVbet}BhZYswPty0Q+p zue8%$U)tsNm36zjORc5lrH<0dQg5lh)K^+pT3=dK7A$Qp6$q#-T-sdLS{f{CD{U!@ zia*E1*YVO&S)#PHtV4XSQ~Z5bX}GMrw7$$*R$k^Pt1R=D`OAD|b!GKsZDql-=CV*( zv@BfKQPx@(6Mxew{@YQODC;U?GWKhd#&vlcgt#29@nR}*^ zZZk61xM$k>Y3q%9B6E3$N)i9`5zjL5JP*$l@h@NVcYKeZk@Gfr=78_>>;pd|z8&Ca z_%lDl_xV?z&tX+OibL@#Hu3)orA8?i|F2SfN~QQapHeIS>lgp6<0ZsDdLOR$<+4vt z_Q8Mm@yR||P4>b1&(b^dyS#$zi)EiI`)0`#%Dy`J`hWM`T&GQZ6o(Skudza0S)~#b z*BTSw35Y+{i0h4u|AxdBN5wVA#Z`xudLc#lqQqi z40YzZlsZ#gYMrG^=`wa1y3AcEU8b(oE{j#M8m$J=tEE^?)>Nw{s058cL(m*d37Ueb zL5o-M8odUu*_+}uc~iZXm=ZI_3^8*oC1#4H#w-;|g|Wg=VXjE25FK`frA28mwisH> zEh#OcV{Wn3Dz(O1L#??srPfrNT5IW4I*px%PIG5Ur>Qfw)8bGZMu)*+cBD8=j#P&w ztb~nWL)aWn37f*HVT(`k8GQzy*_Yxo`BHtBgpx2O3<+~0C1FaWCM;D-m9ffDC0LCr zQ&nn}rA=uwwi((4OVMU(OKr2%EA_^DL%q2^rQTGZT5suAx{ck2ZgY1^x2Zd|+hSCV zMx()KHl`R&##EzarZUqw(=gLKGi9b}X6j7KjmnM28x1#_Z%nz-bYtp`mjC1FOyFa@ zxBvglKK9s&*dz8eme^t%wZ+;ZmZ}g+5Mm2Kl6ewAghqslB81wd#M)FP8T-;$irT9x zsH&ooLPI%Q4e2o3G|;_BHxi zeGR@AUz4wGqqfn!(YVpN(Xi37(X`PvS{rR1Z5(YKZ5VACZ5nO6r` zGu^Y5)5@948OvGA8OmA8nabIgYs<~cjmxde4a+UdP0MWqv;pP;#sSs=h5?oVrUACg z+GX=)<7Mk*!)425(`8#rt);o8v8A=8p{1pzsike7w$HrJxX-%Ju+Os3w9htOn{J+N zoNk?Nm~NSFnr?fky)?fxzO=qHytKSDy|fkAikpiYi(88uid%}CirW@zi_MFTi>-?d zi!F;yi*3EMUgloLUe;cQUY1^_UbX_Qz+7M~uof5!ECr?lTO+NJxskDvwUMEbrID$T zElbNXXBo4sS%xf2mMO~?p+%S@j1krdLxd&56k&U;JvKi!KDItKJhnVGJ+}F1K4u@I zkJZQEWAQQh*w$!k%xjEmtZNKwENe__Y{Rr+=3&NR)?tQWmSLu0wp-dQ^DW~o>n+1A z%PrF_TL-O!xr4ETwS%F9rGu%1?T~iJe8_mnddP6da>#VZ7Nf*n%GlDh zG;^9U&6;LNv!t2QY@ceMnm;vuYW>vkspV7Cr?!jQMe{}DMe9YwMaxCgMOzE4g}H^X zg|&sDg{6h5g>8?v$Gpe5$GXR`$Fj$?$2L`)YMyGGYMpABYME-9YJ09dH$OK%w>~#K zw>&pJw-wcjnu{8XT8kQrT8f&A+LEt%13Lv4ORLp@F4=sex^~w%xqlxZS$lu-&rVwB0sd8*d(O z9B&mZ7Ghwj0_F^9|z->kY#V%MH^FTRW|txt+0{wVk1zrJbpr z?Vxthe9(B%deCsta?o_pHd~u*o^70Moo$$HnQfYFd#k-Qzcs$KzBRnHyfwYGSv9NK zYP4Fd2CKztvfAcr^Ud>(^R4p@^DXmD^KD(VuI8@BuGX%Gu9mK*uC^1}3G)f#3F`^N z3Cju737enhXZADtS^W%t7C)1pZL_x7yxF+fy4kSVve~rRHbxs`9%CG19b*_{8Dkn_ zd!RiqKQKP9J}^A6JTN`5RnRJ!D;O(SD;O$RDwrzRR%k2CD~v0wD-0_vD@-eFAzFwz z#28`?F@#t`Od+-_+7Y=nqhmTy)wTtzOueDyt2G9y|R_mN}5X=OIk}BN?J;q zO4?Gi6myC(#hPMBv80$%Y<;vo=03(g);@+lmOiFFwsYD!^Eu-=>p8JWHM_&lab} znd6Lc);L3)CC(IQ`=EU=e=vTqelUEnd@y~mxm%UBG^tzMEwzjdrM|I=)I3H>9i&-m zBdIB%j-aX3RZ=goKxzc2$=ok>n$&Jm&xwyi-6yr6)Q3_tN*yV+rPQ0YkQ!9#QYBXv zNc}1`t<-02HkW!`YIv#ZrPi1FU-HuAqRBs#bH;BX zw@f~n95Q)ha>e9_$qADOCihFemmDv7U2?hPZ^_x>f03IdA4?9Fyeqj@@~Z~Psgg$} zcS^pL94UFx8j=eo|4GghKaSic`Aq8L$y<`EBtJ<`GF|eJ+$$ z!N`5lD?*NoyjHs8vdCYNv(m&r<$w7z|DM0+=lFT|@5%4;IeZ?U%jfewd>`M-_wyV) z56{K(@tiy_&&~7m9=s3l#ryG|yf5#~`*RMQ2j{~1a88^T=f?SQj+`gw%K386oHysr z`Ew842lvALa8KM9_s0EkkK8Bs%KdWB+&A~m{UZm+19E|UAScKRa)bOJN5~U$g?u4r z$QyEp{2_3no8I&X_zhxn=Ur^89(^rR9C{ z$X}DwCeKaoTi!cQ-an7LIk|N5>*UpY5=JTpbnMV0qP0l{HZOW zo`f0_>PDy)p+1C~5b8jv{h;218V~9^sO6x3gPINUnAB#t>p7{vq~?-3OKK}cZrpXG zB1hCqxNA_Ui4-|=*RN9VDDvm7eWjL>8d+)oCoK^`EX907w5+LagLlP z=gRqV&YU;(q?|wZKrJfw!u?Rk%6)NfqW|uD6^bNg3|IkD95xqn|(Npvly+wb~WAqulM!(T>^c}qy_1Cch z-~ia)RPe!5JJAuW2T$aV$?4M*LQM$0CDfMCqe6|!|F3NTyTLb4?M)z94IYBg;3U`# zeuBy1Dp(BOg2DX5|L5QFcl-=L%kS{Jddp=J--(6qBUGaU~A>Ys4@;ux* z&xb7VyvPX8kL>V1$Q18~tnt3cAn%WCat6pOXMiko2FN&Pfb4Sy^4a;E0lLB&phKJi zy2TlwbDROX$Qj79yZIz^mooqpI0JN@GXMiP0neX#cm6)t^Ygqrzt6k#dAvKH&%5(| zygT2|yYoD}JI|Nrd0yU~=jYvdAKsn!Oea@0I@W_|@ ztT_XZ{JHOfGw{f#`>r?xkNmptk~8qgxBIR+1MZ$PKo&RyWP|fTRyYG>hx0?0I0Iyh z^F`J;17wf$M;18)WS{#%RyhNC_Dux)GcXDCQ#PJ0?pNGNmmdNn`B<(AoZdI3rbb#+om{+e(RKn{@8Tz8) zoPLHr{Y6xQ?e~OvS8u=rS6#C0XxdkWIVCa*cESl4>@1N{n3ML^wxd;-zz<)&kucBp zdsM>o7a2Ow|3Bww`RBCu!P(gG-kE0j&-u#m*7=$7wKL!N%IRx*;Y>0;bN*%e%lV1< z59a~%eW$nOH>cC`i?h&j&DqU*$(dz6=k&6jaz@!?nxXBGv!i{#bAx@S(^_PUb9|9? z&T~c5o&H6aIMa(RaK0-V=L{_tU~^EuV-;ny$a*5c>NsLw)CmEjM4|=3}tr2jV_ZBcdATET*I=? zxRkPyanH+!#tkgjH!i1Kr?@KRo5VTGSB<+{zIa@h3U6b#R(Kd&wBnW6i4~8=UZ|KI z>t87&c7@!+>q;|XKdT%Tn_Ib0Yz^3=x zCo`sb)rB$3s!oadr|Qs{kZM6OIo0aNRIXk+W={3jb8c1tbxvT7<8#*4$eN?oOq(;Z z=FB-qYRc5HT0wIXYx&K&U#r-hF14S|-dy|AY@6?a*<*cI%|7Xi%!JNPsuMK(VIAMu z-Tf@HxBC4)%U1W)tg&^s%{o~(d6r+j@w4XF3!ZhqUV~X5*Do^boB9upRmzTkoHCuyyjZa&1DVMYi#u zcBYMOns30(sc`|jrd|t3nA)Q4z^RMd)}8vG?b|7ib_G+uZnt*I^LCL_dbR&(%BJ>Z zro3;DuI!z>tHa#MwvPQLkLXx?a!$wRkzRp^Bf|qzBl818BP(`l9671eyGh48ot{+H zv0~CR$EZnX9L*-x{OJ9}nID~*cg6=OGbw zKK6~6{qd6t=ReMw;M*mBLUfnl31_>Molvvut?^M^H;q5t6+LY=esZ_>57 zJU^yWuVrIWdkq@%TQBc1&3pgyMSSnfFMjGh>Wi9v{Jxmn=i%u5KHEo^>Kie7c;CjO zv-&E>hOOCE*tI$={Gz%q}cGw zAtyhtI%w|aV+RF(o;~Qzus4JD4GS7PY1pE{^@m*^T=<#Kkc`hp4+;4!YlzopFNT~R z+FsBpLH_&n&=>M=vgB_@%TM?WDg5lR{Kg{r&7i^irP;+^nPJu1ts_LtjT zEVq12Zu|YX$#V1H@@bKTD3OSoUCWAe1dEi!i?rm3)I6CmTO_E?$3sM#mWWgx6X|*r zaX}<)wn&_B&gSO; zBH<%M(rq2*iq!8F>AySqy=cNF(THB{BSkybik1|Jw!EG4Ks0BuXi$r`38GEAM5}I2 z^$oCzmiddeg^JcCi}vjoExa?$+`5=(Wh>FnP|?zbqOE&GYi~}!EgGC4n(XI4P_#N$ zw0o0id4XvA%c#N4tBCf0Bq$IrXpkbPuvgIGx}d~|83lqElLR?RH;E7wNfk8NC#Z5& z(BK+a_psN>J_h zSz86+y8HPG+64*fg$nw`3JR_gG&~@vcuCOl>Fh4GiwRo#32FujdVVe_I#bXzO;9yU z(Dk^W?5~2hujkAW5cE$LE07`9AX}`$QLzqJ#7aCAYwOQK z@0oMwyT6=0-u>ac|MtF9fBT!$=j|`foHy5;{oh=2K7D=8nf&^c)9>{W=aGL8IY0k* zzw^zjozAabZE-e#wa!`aPr5VwpCwN7KMS0hFXNmYUPd{uy_n$keY{=_c4j^A?d<-% zv-95H0Z#qz#!jEVYdUkDm3Iz!R>b-D)Aw;-K7AHf|7l^IOp=QWdvYr7!(RvER{yml zuFYQ=ahD&b#7%kZj4SatGH&~yp>f^*>>GFQQKvZlQIoi;kE+HU{G)i>pg-Qm{`2r* zY}&&su}vQyjV<_Hwqg995sTlo@xhGPpa)^GzuxZ?8+*TPY?b@Iu{rlj#fIE_6Z5jL zFea_=Y)rGl?_$o~&5Vh-yD+Bc-6=8Kej6Io?YE$q2Y2enB;F|AIfsA!bP=aczfoYTfclhXU;D{bG(1?n{)71u{lF-J)Qmf=B3#yZyuN(aC6mc ze7>1CLT6XJ5j6X|>%OxGUAN4BeeL&IE3ciJ6>x3atm{{kXU)1gewO#u;8{OhX)tTp zl_Im=|NJm|?awEpJN>*l`p)IV=!DB*(X}r-qK{vy8a?*X+nM%DS7&a&xNl~!i>Wi8 z{1h>B=}+Be`u|jW=9LQ{W<+1OKBLNoy)*L8r_306K70oL=9Y6+W(1#m8TI6BLDbT- zo1$8sjg7iqFfb~%pm9{q0&~>yA8$?{_v4=FC4O8ueb1TD>4VO+n*Q!|vFVwo?@a4* zdjGUPPbE)FJrz2w)hYjJH&5E8#h<)6weHDXQ_r4Am^$smz^Ro_)Rji@w^PO(FPKu| z_}VFZk3~)ydhDYq#$#os;Oq7~x_9#HBXcLqCdbL$j?|v~^zie@^uvcE9fwmRAG$&# zm%189wsXCkbT|L>q{aCwCbh~RHR*OFJz&22pK#-TS6 ziHD9wG(EH=;>Hg{BIf_D6(o+20~OWdFZo&HHo5 z?%kI#cI3XUW4-nj8|&J8eoW-vWn-%C9W>_L9`7-6dw%(%$)3zFZtouT#gg5AUpRI@ z9Q`bN`{?!A5u^KOHy&-yemd&FuIy3ayQYlt-qm~*K7QQJJz>pvP6;dgwt3i!Z~q<{ z{B8Eg_gRr6cV{&oIXdg{h)P-8M-=P`9}&O9Z$zsdg`tnOXNIoZK0I{5cJI)l+piAK z-?nUc)V6-Z8*VE${O;D1pRe3H_w&A613$NJeKRa~%f4aLw@ez=a7+DRg_{dMTfI5s zv;LbyJ}bW2>$78&MzgaZ6=Qlxv zt>3&Eba+GdpqLF~2L)`XI_Ty4%OShgCx=9=cZAei|IfhtnL7rq&m1u@G_(9bpUg7@ zuCI$5kiO1;z`%9C_btd(mNym6Jncl zYwq_;S(Dzc@0uR{yw<$ydvSGE-({ZjhdR>k+e z|8?`;TfhFTSH#z;y_$X9sn^SuPkVm9a&6DpmA!fft$Y`3U%4&#Z2I8fW$D)7A?f>i zR8Jq-OO77xbE#&ROoJ8akSf+uO@dRt{VE)>8`cEit74!dCji-m!Itt zw>-K_x8=TFN-sbE@y%tkKi<5o&c~CNUFh6?*__VSWpz4VOuG=2kv2PMT$*oCtF&_; z8PjHdbbe{gkJcgj%*XPxLljy#RpqgUmV){EgamOcrtzA+GbN0 ze$=ej!h22q7A|ONSXjU5t)zk`IZ2b6EK4fgBr<7lh6_v?K%e}28F`F{06=AW$F zX8zc^mFC;(zMZ$#@8-Pje!24=*2$cgREJphi+Lw~d(0c_+i0H6*K6M9+AkBk)V`j0 zzgBKyVyz8{wQD6M9;rDoab(T@iCWEeiR)_ANDQoDOT1P6$=o^BugtAnJ$G(SwM}zF zs-?{Rr|OKk%c_RXZCsSE=}^UdH&6 zUa#~Wr5@?sO5N5AOJ3BSB~R*AN*>a`E3rrKUt){?v^X*Ra=mWxWc_Hdcs;aOwEnK> zWIerTxb9zcgnq7wOvx?siEb?ttZ%S));roe>ep>;^e9_%-OJWU&$8ClyIE`Lg_df% z)8egrTPo-W%w_aX%%$|dOvUviQxVS+dp-q@h&r-il|?PhN@ zef9q|z4iYL`o#}Mec}gcart1;H@>&&j`v0MoBtKpXZ}}8FY{j+edoIhdXIPB`u(@n zbp35D-REsxJ?Bj$z5ko$`qS5K^yJqab-&l0^&|fV>!1JoiT>u*VEwCCBlPC4!u5iG zChOtne;(FPNPE~Jq3OfE2?f80C5#gm z#P<8bgpCg}5`rG=PWbiyiGy_rezSd^`%4;F>1Fl8QzkcpYMJ3=lMTec{P97m5K}A{~WMj?axCNbozPD zf;*Qp79?EGUr_t<-37-lS(3(Hs+VNH)H7-O#mJ;y7ndbH`6(x9=})(k{C_emymG;B zVf2Mw3#(k1vM}#_`ofXI2AR*_Te#(1vE<-${>e|y4ozNqHX*sy+3m^K3oa(d7Q9QY zS>U_q_>a98jr(!Nq7px5F4}YE%%VYOUM_lfy87bG)4_|ooQ_)j=c&xasiz7Sw>tHD z@y(OIU&f#8_hsFav0t7&vHi2S+=g_ANNlgb9`iq%+OBRdn_+y=&`?2jK|=r zdM)X9G-k=`BUww<9l5on+mRBfPY(yCrXP+>bsWx2edxNFy3}P}+RoK_>D~NsOJ%*< z(pLHBm)_1ZrX}UIN^71sF70M+M%ujGi)l@Bt;=p4YQHS;(Bx%J4{cs{zgA?ZC2EK7g0|7`k}{q~h1`-4`R_s6c>yYKszBlo>r>9w!f*RH)0 zUq|lU`gOIv_rE^3r`D>tJ)x_b>{+ww_U`Memh7&$+Od1!>Sx)@RGaqeVpSf=P{mcQ|>#Z-kJz{C3L$EpPHZD^=dAue@E!wT0iFlebNgx9%-( zUn0X>P9j`R*?|Xgt66fp)8v-h%WWH1 zERmas7i}$)kSr2$`}@Zt9s5N};zU}yiPV%{K2Id*#t)lCnkI`>wHN8KE^8{1Hcuq( zX6`tVzE&cI#lh;+&h@ch;yt>&dmMRFgyGDV6bMVbRes!ODH6A51@lK%Qg zj7WVik^ZVnjG_rcMI-heOBL-HDO%z$+G0tmESfV-H0bP!Skb0_qE)_M-aPqQw5&k1 zEmO2EO0-Y5kBBC|JN;6$@{DL_rfBI5(bnFgwZ4mLiU!AuCSNbuE?S)++C5aX++Vc4 zSn`&0_eA^i1O?Is4W%BqU%D%3 zlP{=~A?PzlP-uvtQGlRQ#RbCzp?kkH0&X$*htXPYu>?IF9j{H3u@*HdTtODO%gPnD5%m8dAz!jf?Cj~8M+?ur%pNvw%WtV*_6mrSuTsbXz( zu{u-4`h+%LWw=<)5n??DixvGutZA@V)y`sFJBpQ+ol>ux zi`8u;*0-)$;aXyitBFX-bM(cMZ+veNt8NnOZWJqT5NrQ` zR$tYMvsZ)N44p!gW7*-ro{Z0B*Mq7dXYU2OBiL{8Kz2-I$sP-KQK;H-{y+bYzvE~4 zS$;>=oby?HCZElB@LhbTi zG&ZmcrMm3JC{^b_=ZX!l3_neM>%8jsnQ{G;*UpXG@{R0C$(P+3(-K}d|Jasfnz{U$ z^MT)Arqn@yIcKc@#LNyA_G{SxzV95C;%%95@;7Ho&1reu=NIR;Nrjd#Wxq;{?BMux z$|Yx{Bg-0C{G9XSZ@g^%2cL508KP|LUSUs1QS%|^mh6u9J)`zJS7{sU%ct*jw(Dsv z!d@13d6eJ2&bjdXxgv+or8^JV{fq9}xWu`seR@%Lwy^JG(danmx-UbEIr~I8TV)+B zcKMG9&V@(ox@CZSIM8yiGwSBk;{ERRcBb9zUt(03&dwQ^zAN#M?0PAby&)xi8ap$# zIZN(aTGRQ(g2Iwda>_eDeAcbhQP~5-ZjlZ?@8iCGSkfzW@UysXnNz)5buElL)ccAT zJ7Uhs{t@psr{Ww7GfKB@cQEd91w)xePj|%i`FeC2_QyIdB0XE|LdA2aq~52`9Eau%*V3pq<+WZ zadW-9RM@ieZLFp2)(Vq1KaBnIebI_3vXh2=C?&2Rjs0QEg^K^a&yIaK#=p|gpEF|X zR$SrM1>|x6>KUwn|_PZ+6+#k-aM3NxrdH{=Vm3DX3KJ z(-z&TJlpvursb$@Rd&ms8+NaRuRj~pKXsyyZ{6==_AWl}^LJ=wOz)Y^tNtQ8aM;iC z`q7k_P8I&C+PCA-m}+N2syz=1is?EbryBcl*x}MYymX8{eNOdeNw4R4-?~+O`Dee* zDbXyj#uC|`!=9JsRkP+4Tcg!nSS)SMy1gT7ZvA%VoHYlI)Xb2*I_!d(T_R}Cud#`> z`u^xQXXi)vYc=XvY|g(=yVPdqPMqwE>C#cMUd3#_-~4!B_Mn+#efySNHM_;xlfDXP zu4RYL&S;rb=bBg0?EPIH)|n*Pu!v6G{n*trPxj7ij`)4ni9c<1C$2j+>t)8+y5$#a zn{~0x$-3cysPVJDuQ|V7>6qYI!Bg(n`_QJrtPNW}uHQ&@{3Oc$n%(CgM(3O~ zHdw#oWVB)T$Oc{=H%HgeT@A`6CPx1$J8tszu;_~CV;k1Z;M-?`hX4 zNp=IV2WR`2S7)}Z|8JvTEAE^5uHC@K9S5h*JlSk-WA+BIE9cz1ZZp$PPHNIPwD!zu z;RQ`f&Jqs&&-zW1WTz1OboL78wt4lvrkhHp%ouUQq;WGyQyw=^114foEQ)Nbp z^uf)GHhLNLdGP+`LGKHqOuv?H!7d{9@|-yy8x^_ZOpBhm1EY@I_4AL2XdIRFHo?D( z>?vY*&(ptePG4}QUCX(r_Dt`au%cy^K?|pEsrE_gw8*u@fExV>J`*1B_OoxQ23;x%lZKCW&VwaH5mAX?uPk+$1yJY%)YV2s|7g8`~ zQ0CX|*qOw>q43~s_IxHJDS*kN|o3v_h&5x?A zdOtDy{LGKo-!xiwBn{}WVxs=BZ_wMiVG}QWG&`v7g~k)BRk#rJPIf!7M=3qzSj2BZ zb2|I9S`zVi)rHR6E)0pNeY(!a?0sU_Qdp-aQiyr};|pbSCL9X!?Q-^;_zBByMt6yp zolxv!`sYL02{EH|4{cDg_XxW8C0rA{gHRVTbv!)gFRF1e(Je8B0RUL zHF*1=7U3B_gM*J<`giR5o7;j9mC7BPF8iSl6iXP}`+TpSS5I~wyTr7%XXlTLjcr`y zY0v7ipX!C|kV=hPHfHyN)LuVy7&NA(_FJ#xKX{Mn*`s-Hc2}`ys@VI?FDCW+sdrlb zs4ps7YxYU$?DxfzC6bwwy;d7#7nL)0`)I$?rTXR%i5OjIAKtgb{l=qroX_gJM0Q@W zuWDjY_NcE<_vlwpZpx_P|E2f4ysi1Di1+vVDL-P4&z`W2~L|PPXlFF7JIK|)XN^(<^KLpCzOjES#h4Rf7fG;NACZ-Pk;7kJ(b;9eJ5`pk>2e0 z{^ugXN5mTa2mIXFZ^X3BxB=|g3YPs@)jni~UhY(W;NB9$L+?6944ih?JG5(w9RnB2 z{w;QFRll`t_#m4jy7N;$}Tte^NcxT2etk*@bi$1 z*@FT?-VFQq`I|w%vbRfibq(G#X;`PFiv|}Itv_sW$;*SsHYoh8c95HD}J*a|hf7cf#FpN8A;6#@%s;+$DF)-Ezm=HFvK3Mq~k*KsJyOWCfW)c90=t z37JB+kTGNpnM3xFL1Yn`L^hF8WEGi3c9CIZ8JR}5k#S@lnMd}~0dxVKKsV44bOoJ3 zchDhp37tZ>&@prkokRD~L39zFL^shH~irh#o>99ReDfqh^gSO_M9 zjbJ2L31)(wU?^A$rh=_tELaQXg1ulcSPUkE&0sWG4Q7MgU^rL~ri1NZJXjCrt2hB$ zfK9+QU?Z><*bHn3HUwLOO~JNcW3V;Y9BdCZ2wQ|r!Zu-}uvOSBY!@~RTZT=;wqfJ2 zb=W*?A2twMh)u*cVk5DY*i39EHWXWmO~tliW3jbvn=7^#8;mW+CS#ki(b#HiHntlZ zjxEQgW81Ou*m`WfijVLG@Con@@DcD8@EPzO@FDOe@G0;u@G~@agdF@bTQfp7?w!F2onaC&V|zN5ogeXT*2J zhs2k}r^L6!$Hdpf=fwBK2gMh~C&f3#N5xmgXT^8LhsBr0r^UC$$Hmvh=f(HM2gVo1 zC&o9%N5)siXU2ENhsKx2r^dI&$Hv#j=f?NO2geu3C&xF(N5@ykXUBKPhsT%4r^mO) z$H&*l=g0Ra-X#_wCLlH-Mj%!oW*~MTh9H(8rXaQ;#vs-p<{Mj}=sW+HYXh9Z_CrXsc?#v;}t<|6hY z1|t?DCL=Z@Mk7`uW+QeZh9j0ErX#i^#v|4v=2JWXu^=%au^}-cu_7@eu_G}gu_Q4i zu_ZAku_iGmu_rMou_!Squ_-Ysu_`euu`4kwu`Dqyu`Mw!u`V$$u`e+&u`n?)u`w|+ zu`)3;u`@9=u{1F?u{AL^u{JR`u{SX|u{bd~u{kk1u{tq3u{$w5u{<$7u{|+9u|6?B z+yfi{yRi8)JF@wEc4zbR?8M{u*|p8*v4fk>XE!(B$KE`?pIzQO4?DhjK6ZceyzB($ z`PmiD`>;ct_hYv>@5|0{-k)9MoCiC~IUjbHb6)H;=ls}p&Uvx}o%3ZkI_J&Kbk3h$ z>f8rA*0~>cuXA7QWas|a)y{pMksa>bFT35jZ^iqt3m$oxC_CbjkA<>39(iGBAo3F? zyXKLnRkDK~`C>Oc^2W}3OVzZ**%E-=FbRwf;>0;s7@|LVpKgDmPqS;>dxUn1V0*-ta2Yb@j9Dx4}AG?O~^g)<}2B|2>xV6rWJxmy{0uQ z1fTXKox2NOdCP7_@aym&Mel-VzqQ)-8~FD9@@~I@cZssU5&Uy5O1uLe-mhKz4*2-| z{NZ20%R<@l2!6gC^}pNT>4;uyZ-cL+dUU)E-nNrHkl=5PggL)}$DibR{{lYSy$;?2 zuh|s|e!qVC`X+e3HEHEd@cnFyfScgG;`zdUoOuHdAoyU#8`y_suJ5j6FW5PW{b*b6 z^)>8C@vxQGurG~I1zf}4T$R0)*q^SqXI;e}?N9N(ihcTg@DEq8SM09Desv3Y|10`ksd z-?ujyc^-SO_|50xTh8GRY}g-s4*%f48c)vRF9gU=PW*?|0jw+7=vK#n#2=BWrXTT720tkABmN4zJ@H>|RvvT)f2QvJcc<}hj{TH*8h?lV zpZGslO8t2Xf9T-I)KmCJ7k+Ma3V(?mq4-Zz>cpSKpNcTlJ&AucOFMf4f9tI55yk)7 z5MKEN{#cWX`N#3kwuX*5j=$Djc8%h{b^U$sG5oo!zYRTxf7ilbJchrgc-=a?`W?j| zY!LYR2>#*a=j)E(FS4@~|MB_Rr-$(;FTG4ZjDP7LWYOmu=_5 zKmGN;yZQL5cV+h}{_EDRt@80_zu0m+5C67rv!p!yUG}5m|2luTnTtQ%G;dxm{_$^r zG|k0dJ|jC+-TrfK;vxL$vR^bkgnxaj^^G6!w|B{&Rs3();ATJIk9Xd7^C13tgztib z`0JBp7c2hz+|{?g$DhBJp8P%j{WtlozsKKKe0D_Ik{sfJpE`EPAwHO0{*Uj77ue}a z{4h4S^LNA(rMEsiKzwnw#o7bJ8wIlWmG~p*!khiXBVmPG_7k5B_YK)kyuxl+;+H+m z_U!8Po8BHkNNz&KAZS#V6*<&#A|zGS1s||*wzPj5znnR zh3_K1TW0j$MZBkY{Lfaz?Ia#t+OYXf;={lfh2Ih{E|s0P#E%EPgTE!7d^r1k7V%|p z$=zARo9x9U{tQ1~DT{bC;eEjl;?u>U@jHlD*_})L+R*iAJMnDQ{B_%jZ@+&&U_0?{ zW7)4u{JZsa{x;&_kRPMA5g(7a)NmW|GCO#QpGPIG+)6yXt#RM2#Mkx`)~&?bJ7iBU z@waQz^ex2W)BbL_h4}pW_QK7?>+JF+em5TNznOUcubRa-6WC@(moomflOhfdgP~FdV?iZPst#08W2< zcmo_j-#=qEzyZva-NJAHOUu4o4+pT}!>;vk0Ke6aSPuul{$V(P#Z~WT!U6PpzCIHU z;5S2PCLF-jUOt&{01Yl)Uk3-!d|CQBIDqUW1J}U;u*Vn<;QRI$*TMlT|1)(h9Kgb> zeb>SPu>RoCOX!vf&=)+7`h4$ppooeh68B# z@%^vi06spt^=mkQ$oPn_;Q-jr32Lu1M=wi<1BjD7&u{=&)>co41NhbF!3sEl+?!b|-~g7(E@(J_c|Pq|zya)E zYg_>b&^7GLS8xC-UsZAE(68VCR=2MG6&ye@!{g;}0PK{8186ZUZaEx4)4#echXcrP zm0k`9uuk?)!vTae-MkDA;NF?Z%isXQx3yme2f%J>IDl(SFQ&l(SgvKH!2x6)9hU|N z@Tcsrh6A|wg)t2d;DFEhrEmax#WhRe0N5Q42M~L`^-?&1zcS5B;Q%gWT}*`oU=KDN zz?`(mR5*ay5rL_20OJ;wNQDDnS2i3#%F3)IZ~%q{F-zb8ZXWEl1P(yu>Ds^eD+LbV z-M@J$Z~!ZVQd8gn8q3aYIDqTh{8QinzLQE4IDmWguYCyzz+P@RfUl3nehCLKAeUJz^kP1A~=A9vL_t=ec7^$$#4Msg0?5a0kmqDkPHXV zOm>OG0puF}li>jVxl}9}4&cdO_ZGqdsQl!@|I!!20Sx_n%0f7RUQK%~gacp~I~>5@ z^9>8(04`s4w(-JkT#;td^mt1%PP%>1Nc;St-}Ezg?b4nXB)v;Y2L9vr~1mObXd0USIc)quhQ+>)K`Z~&K%yi9}x$ZmN(5e{J9^V~!@ z0QS1W0Sx*yDG?4}#>mc4OZJ zIDqGV9TMOG*l7<3uw+QZ1UP`fV=W1A09TK^h=&7U?>!tqjZr_v!vPq!y5ivg4!6sW zhXaVHk{J&NP&_y_9u8pJ2|XSTpwH4N@o)g9?P2k70GGT5#KQrcINl{54&cG5Hu3I! zsds~TIDj+X`^3WmWNs-H4+n6x&=~LL04BZC;Q-2Xd!)kw^qO>AhXeS#@S+X}P;~1_ z9S&g4!9zM6z^*ELbU1(>KW@?C08}2nVTI*79Du$%S%(9dzB*oq11NDhT89JZ_t|6} z4xn@Ma2*cd(ZCTp96+zrgLOE735!0_;Q)HC3D)5NUcKwA!vT!j-cg4G$lB6IhXXkL zqPY$S@NG&X9S&e>bX^?|pzQ8iIvl`q89@jK@NY?P9S*?JvVsl=5V^IC4hN7lp_C2> zusF834hIl>yNC`4Fg!(SEQAAS@})(G19*1Bq{9JhnrYPG0D6xy=x_jkWN11Z!0fu3 z4hJCr(fKd_30N6t~0PG_i0QM3N0Q(6CfIWo+z`nu(U~l07u)lBs*kd>V>@yqy z_8JZV`wa(xJ%@ARd7O zAU=TuAYOq3Abx=ZAfAB(AijYEAl`ukApU^^ARdAPAU=WvAYOt4Abx@aAfAE)AijbF zAl`xlApU{_ARdDQAU=ZwAYOw5Abx`bAfAH*AijeGAl`!mP<3>~gKz-Ehj0MIi*NwM zk8l9QlW+jUmv8{Yn{WWcpKt)gqi_Jkr*Htot8f6suW$gwvv2^!w{QT&yKn%+ziu>t=Gl1% z-i3GK-FQddm3QXdIRnmuGvRDFBhHF5>xwP5;BEsA!EoIGKcITgUBK>iEJXH z$SN|6>>|U+GBS;9Bjd*$fU=G*= z27yIj64(SrfmL7@*ae1xWndcE2F8JPU>?{927-lPBG?E)`v5nYBY$Y}m z+ldXumSR(}t=L#>t=r~`?ZpOTi?PYrW^6RJ8k>#n#)f0dvFX@$Y&^Ceo3HAF@dfY+ z@D1=0@D=bG@E!0W@Fnmm@GbB$@HOx`@ICNB@I~-R@J;Yh@Kx|x@Llj>@MZ96@NMvM z@OAKc@O|)s@P+V+@Qv`1@RjhH@SX6X@TKsn@U8H%@U`%{@V)TC@Wt@S@Xhei@YV3y z@ZIp?@a6F7@a^#N@b&QdR9!T_AU+|!AwD9$B0eL&BR(X)Bt9j+B|av;CO#*=Cq5{? zC_X8^DLyK`Dn2W|D?Ti~EIuv1Ej}*3EWz6Jiu%6=D`*7h)J<8Dbh@8)6({9bz70 zA7UV4Az~t8BVr_CC1NIGCt@gKDPk&OD`G5SEjR#TFJdraF=8@eGh#GiHDWemH)1$q zIbu3uJ7PRyJz_pp2Tv?WOh{}j7h9X%t`D?3`#6YOiFA@ zj7qFZ%u4J^3`;CaOiOG_j7zLb%uDP`3`{IcOiXM{j7+Rd%uMV|3{5OeOigS}j7_Xf z%uVb~3{EUgOipZ0j83dh%uei13{NaiOiyf2j8Cjj%ufXXGnSa6#H=LdAu;oaxkk(` zVm=Wwh?q0PEFtCvF%yWnKg{-Feh)Kxn8U-Y9p>pUGl#i2%)Vj14Kr+*Q^PEp=Q44H znKI0cVKxl&UzqX292aJ_Fpq_qE6i14b_(-Rn1RBalZrCSgn1>*Bw_9dvqhL6!i*5+ zfH3QWc^=H{U@ixEUs5HM?ic>>G~U@ic?|Md6M!%v^SLwfP)x2LC` zzIl4%>3^rkoj!JY)#*p4=bXNBddKMxrw5!qZ+f}u*QO_%zH54`>7S-Ynm%ZHo#|($ zXPLfadXMQZriYk5VS0h-_ob(ozFm5AVSnhcrH__gS^8n=d8MzF-c|Zj=|QE>lwMN$ zMd=BhBb`_DcGAB|k0yPX^jgwSNzWvGk@P;&-$)N5eTwuVmXMA+dJ5?qq&JZMKYIM= zB3O!>66uQQ&C-jY(PUsx7o6tLEG@*OUVnY9zxr7cf zTM0d6h7!8StR(c2nMmj)vyaeAW*niL%rZhhnOWqXQzWyA&{Jj*p{vXqLSLCFgw8TM z2)$)S5W34OAoQ1+Kj<*Ceb8fO_@K+o>Or5G$%9U>li54yH8Xb5ZD#49-^|QG$C-_T zo-+dnU1!z}`p!%nbe`EY=sh!P(0yjnp#KwP<_s9XY#DHX88To2vtqylX2O68%zgnE znDGKOFv|seU}g&#!E6?Af*CAe1+!Mb3udZ-8O%-rH<*zEb}$PC{9xt@7{Y85aD*8q zUQ)hnX8-5VJMFA!cZRMa;?okC=%8CNcX0Tw=xr*u*Rg@QIlfU=*_{z$s=>fK|+z z0I!%S0cJ5f0^DLo1lYwa2=I%U4`3Lx9l$YWIDlo$Y5>oe$pEG?djVWy#sb*JECuk5 znF(MVvk|~KW*~rd%sK$?m}vm!F}ncVV@3hk$1DQy&nR7qU?8&vz(HmRfQ8Ho01uf7 z04CD=4=&Q<4>r=v4?fbf4@T0P4^Gm94_4A^4_?w!4`$Lk4{p*U4|dWE4}Q|~4u;a( z4vx~p4wllZ4xZAJ4yMw34zAK;4z|)u4!+Ve4#v_O4$jg84%X7^4c^kz4d&9j4ervT z4ffKD4gS(|4F=O&4Gz;o4HnZY4Ia}I4JOn33@+2-3^vot3_jDd?Cw*R-eho^9%QhZ zUSsf@o?o?kGW-d=E=9$v7VUS05-5-y?ex-u z@AS-q@$|-m^Yp-i_4K-e_w=-a`Sh-W`}C-S{q&-${zuivsQM9AU!m$tRegS{Ur+Vj zQ9DZwt?GkQ{cNf)P4$uSxYMsXimsFQoc@RR50Z!%_V- zsxLf@jmgP&1-6{C2R8?21>O)nXr>fUfb(h3X$bhPYRP~IiE>YDNsyad9U1Wf`85vOZcdCv~)x)W} zHdUXd>daKVn5z4Nzd;669hR!6QguB!+R2`41$5C}Psy;^5xxiH+ z1FG&s)sLt;5LM5i>M~S)g{qTK^$x0TLDe6qIs#P>pz``EKd1NR?Mq`9YQEQ~5fTcT@Q@l?PM#ER~m1`6ZPn zQu!X0w^8{Ql}Aze5S7I#cwN~TJg<_H&*88cVyp&?7Vl+EN2!qdp8cqjt6#cu|WPX{|E*wt}g z_D`^{gIyG!xzd5`?RY9XD%jm2^Xda-et)N6*^qiJ=l%mnP(kXQ}%qYGlN|p?9X7|2fH*pbFbZdKiIJ$v;RA> zZ-f0G?B4Lq$9C@lIV(Fk*agCVj_R@xgk2q;Ioj^MAnfp9HwgPY*bl;P56`^qPMYiq zsUtf-*cHP55B7zy3&b;*+r2kLb_BS0hp;b%{UK_H%nO;}&Hv}$@ptSO;b+-3!c2EQ zgU{kK`E0&}@8UZ>^T6HD!ZYz~JR{G_E)!a5kI~ zXT`1*nHlarL(Y;jok>uy;_rjc!A z99c)^k$rRkT|g($4Ri!uL1#R3+}*l_PO%#W9Yfd9IcDLbgXkhUiEg5!=qftvnG4^k zk?c)Dr_pV6JXQ9m{ND~8v|s1XhxoJn{UQEdem<9<_sp5+^K$t-`TSfypS=uxAG6r` zetDi;o`>BHJfG-(9?#3nc4oKB`{eOH?0Vq+^dB_vHFpw|yVjyoKf9`z=?8`tN*`0xWvPT1XW#&B? zz*0iqA=0zp662ZFxjqc5I40_YRFLC`PugP?Eh2yxHa2LnVO z^U+6kf1sc20YP6qdkN5Ic88$f><>ZT^U-(FefJE1_KAQ2>=pq7*fRnKi0+1NLN?z3|Q-FNQ}kax)k1K4!}2C(-83}80`7{ERh z@KDYs9}Hkm3K+l+0x*F6DPRD*RKNf^>wGZ4v#$Z&&j$n8y#fZvUFCxT>@)xa*v|q6 z$ld0H0dm**V1V4cdk2EZLO%9DWFsF8V9yH};Mo&_?&pI6?1BLUMAq`b0M9-NbUz;q z5ZTNJ1K1-22C#Dh3=mn)$DXlk1`J^D3>YA?pAQCzF64s&?4|(&*i!=ri0^{c_oMqf54z9u<$9hM-RJqyeclJ%=l#%q-WT2H z{n35S1KsC*(0$Ge-RJz!ea;iz=X}w9&Kup&2Ln9!f$noZ=sx$wUI}(xp!?h>y3hTh z``kCW&;6tO$OF2Me4zWt3wtV%A9NpiLidp`bRT&`_t}|&?jw)rKJuC8kymsd`9=5L zJ9a$sjqW4w=sxm~?xPRrKKg;~qc8a${XzH9Cv+eEa_A2S3q$_YNfwzPitvGxy-H`!2W>4?er^ ziaYb*xBD)+QxCqo@0vUJ;J;fIkO_}{aLWoZ`{kBpWZGlj+_H|$d+eWE7tjfheRS&zI^(gQ=sxz;ty}1r$KJYi4;}Q_W4CUi zqaJ(h)?IYiW6#~XjgF)1U;xG+3;+xGv*#QxUmlm@c2V+Yy<GznZ9~4Xbzp$U|8?6!Fu>y?6 zb+LCM`<=i5d|~V%zA+epuZ+FKcLoDQm)t%zzBTq0UmFa-_s0I>i@WWy_~zJWe04BD z?McFy2LnX6J7M4P^}zte|Ef86iU(G6>l7cX=Fll#Sk0AF{4hP@^cg6gSj~M?e6gD2 zrg&pDmre1bIlaLtmc#{o>|QuQ+%_UBc^y~H5W|r&uY$B z7vW^#X4Tv-#Yd|-T#A=gbF~ydt>$DYo|>Ll`nD8bt>#!M-dfG2Qv9`=Go^TJH8)D} z*=i1y;M)B-w z?u_Ew)f^ecyQ{e{|DS*N%z05fyqeph_;@vkMe*|VR3USUpI38I6i=__o+!Rv%`s8D zy_!p+_HMDh6a452fM&sTFm6tA!5dMJLM9vyU2@%(D;MvP~^hMJ?1@0piDPYgPb z?+*s3ITtDqpypPne1Mumq4EN1u7t`Ds5ucTPoU;LsC)r+P`r=I8>qPqDu1BnET}w! znwy~V32F|4$}6b31}eXx<`k$rgPJ>_@(pT^fXX|lxd1Bvp!)n(9zyl)t9*p&!&i9; z)mN|b6RJ;MH}AK4b|7J@*Ap8Tje>Z z8%AGMzC-m^@v6Lu z>dRI66V+#{@+hirR^?MvAFRr&sJ>Q}Ur~LkD$k<&PF21|^^vN)i|Pwi`4`pasq!$Y zZ&T%CR3E0w%c#Cem7h_4k}6N5`W{ujM)fhOyp8HhRQVg#XQ=Wxs&7!`bEp9X15{pz znm#Z<<#$w{p33v6zB`rgQGIkO@1y$S{?Gr{G}Y&(@<6I@P341BADYSwslGCmA5wi{ zDo>>PzEr+Q^>L}Zk?PA*`6Jb5rSeFsZ%XBpR3DVeE2+LFm0wbQN-EE!`i@k-N%aw_ zyp!q+Qu!y<=kx#bP@cXWm5)+=I4Uot`f5~uO7+R8JeBHuQTZy>$D;C9sxL+5uT-Cj z%44a%5tYwUeIP2YrTRKleoOUfs63bIyHNQq)kmT7UaBub<-b&)gUW-cz6F&JQ+)_3 zFQ)nmRDMkL38*}os{2>@GF8W~@@A?oU**qKoxRGVsk(WUPg8a9DzB#M+Eso{)v2pI zo2olk`8HKYuJUfGE?ni`RGqiV!>PJ$m5)<(*eWll>Z(`9td zDOJuX_Ds{7yw28WlI!BL}+XPjrELrnPx`4R)A4&;V|mv z?nb>_KcntD*r>N0VbrbRM!mvhqwW`N)LZLD-JWFBE2SFsdMk~3K&DYIy49$AXB+hf zIYzym%cvJWWz>Bx81+WijCzMVM!n=iqh9TqQE&3vs0V5$t+?If^71mdYE&}0n$wE|4877mlk+}-3V*U#kg9c*&79AR=p7Gay7^?x!So*uHvUmE}sh~SEFktSBE<$SILJaSG8v*SCiK! zSD@XjmG&}gH7l95<~7V(@p@*hY%{Y~JHV{@JItD;yICvW&#cuMY}Q(hFl)AOvsQ7k zS*sgu*4pT1tw@qttDI`q>aR3wZ8ObUv8`sUO14>Rm}A!3yUbdNQ)aE|1+&)pnpx|3 z$E=llXx6GfGiyy>o3&1Mi=(uc#Zj}8#nHTmMJrLy;wan9;;0>9ark$)ILi04IO+_x zI9iRcIBek-N5#n&N8M_0Zy|{>vjw0Qydij18tKQya)k~bR>QygT^~Tq%ddE9fz0^aiUj3O>Z~EG*chYQ*;&z*> zw3p3Qvy#o#yoSwHyq?WfwwcXUJHY1hci0>yy4zgk``KJ|2HRY%M%Y}oaGR^*WSgsQ zw9VBQ7))wA2nG_%`l1=#H^9CodAce}k@ zKfB#`u-)Ergk3KkZnsyMY`6PG+wHA&`Q0SDy;7>(UT>w{9*}9b7u{;NduQA24RY-E zb}qZU_$j;H=Yrkd=$hT$;f~#2@}b>c?U~))53i*sCDn&IQpx)7J@VjM=L zxP;1a30LA0P{VaCF3sz4Y14>HduCipT5)O7j!Q)+F16jbl=kA%vLBbWgSga%63`-? zun;6+VQ9i4u!OjXC#(q~VXcCMwM!S5vipn!7s>Y_wX)Z<0@+oRVNKp+j zMNLU5YEDj31tmo_)s!`*rKklxMQs@=s%3_swNliQouW!kit4y2D&wW76+cDo1SzTq zrAZV{OXEmd%A#qhjHOK!PfL?TT3Q2XsY0g7IVvqp(`hNsq@^00Hs`psG|Q)@4IwQx z#59FUX=zSQO9dq@HPy6*YH4XfPfJ@yT56eTYR*baOLkf+IccfmrlpLRmR9_{bC1W+!jJ2p`tOY$|Z5bJ>WoD=)D`PF$8LQ-Etd1M5dl_rR&saM_ z#_B-`goWzw|6nMB5Evq2ID$+N2(k(gWS2ysEQKIbG=k(91gWx!nB@>;hDVTf0YT~_ z0%H<_pfZBs3W5L?kuVKG=5++wG!SIZMBuE2Ad5DF6deRZ3dZSOavaK2i>>aeC7jr}xZpIB$*9i}pBObjInnJ1*tDaeCPwr?-P~ zx(iJ}I6Q&i$b^ic6EcBKh&VnWPY@IGDwvRW$qA@HO~_O9gq&k0-A33=0)kVE(#T(BnOMSDUnIuml+osbINguLue z$lJk$+=V8gB0Px{kx3gvCv5_o6pQ$zTqGv#RWNDql9N!0nzX0rNjt|(+EsQ^EOC?e z3_oeF3zK$ToP>+gq>ajxHm*$CK%JC|+N3?NPuiQtq`hZO!X<0cUbH9eqBCi?-ASqB zP1?);q`e(X+FfXh#Na6!L#B`{I)#+6DHFq|Y>b#f*1!}}A*aYJHHA#mQ%IhfLTc=k zndPRCS$+!H5T=lZI7MO76f!4IAq8a$X{u8ercEIW`V_KdOd&0EippA3$dWyUl$^%)Q`2<+k!Pmq z8ar*~xoLWqpQbm2X}Td!Q#omxo|C8Pf-+4v)oClIP16hdG`(d^(=BtF%3IU)l08kA zoN2n_PFs0znqKjz>78Jj?m;so4$sgyG9zcv8M%zjm^eOT_6IYSnx8M;8v z$a!W)uCX&_ft!(M`5Adbn2{Ue424TG@|-*)7nB*fsm@rqHX|?SGxC-(Be%>Ms$k8? zOZJRha%SX?J7X2R8F|H@k#~X_xd+XXMR=AjBC~cDowdu@tXafo?IJO2uYp;+Le7#U zYL+h1vv!`DwQKCGS>k5xS$@{u5N7R$I7=0!S$j^NwF}Cu-Bf3-qBd(U=(F~gF>ANX zS*m2s+DrDVU2_S-S_J5CNkIfuJacq9}o(B7vhaL7?a=K+#qv&>kqFrbXs={+f6`5l&bdDjgIkAe*$yH*GSp{>j;XS9VvU=VYy2FuF3d4?aSpCZb7)nbV{m1T0qUGo)#jLaeU8~Q=9oQm z4z5{q%%VNV6rDMy?aoOxZ;n~^=a}taj_E@45P;_qfXpixIm&s=~z)`GKWFE~YK!D+h-Qpa0xmi+~1J6LeK&>~5|i!^~OqFHniEn|x&fiKzw zv52mLMYKXLl4WXo>@d|?4nub7VR>>h;9grXhU422x*Zam@K-)l(8kV ziZ9t!Vu@J;OH74aB5TwVU89$nJhQ~q*d?>ZE!j1GiP;dAn1;ASRi!1SDlahwWr=C3 zOIB4|a;o|gvt=wXEpv&gS>fmGC8p#oF&%fws(DMyioe9{1WQa0S|$O!Oao+D$)d|j z8Cy01zH9?xSy=BwY3$et*XaHth4WViw6FIW)@>SQg9SS+PK5 z*;SBbcgbwn=V#3=OmaVc`I>%+r0-t5qg)Cbavtgf~70Ys##g!}z)GS=pvSL%u zvYSSh-7~XcpPx0$c9tzVS+?zF;hL8BOHKdHM zNd;mJErT_8ms|@qw`P{uAw<;O)AT4F0QP(KwU$t z+M3kV*W68G&D}HC(7d%~mF+dR=&ZSIcMYw1YgW@=bGL&vw+rXQ9FoIwXbvmmIk8CO zkTS?&6*3pbJ!j_V9F}KtSdGmgc`j!b`5d+(|_o~n6y zv*YL4ogmNlp!KjnSr@CwI$TB9)iSn@RPlAGNUWn(u&!3fb+SsWn^k(9sxs?pja{d! z+`3id*VPSSU2TZ#SXEk=s`9#8P}bF^y3P>Vy42R!)h%OPZJFzA)mpcz_PSbf*42)? z&Xm1%tL?9=JHfizgEpWVydl<*4Y-DGxMgeuso@(^iP%7EV8gAD8)194VbW=% zHFkrpaT`{N-*7jC4Ywg~U^Qt&s>vH}LD_Jd>IPHQHl&We;cgilZp++YYu1KUvp3w5 zv*C8!4W{O8SRH@E-3d0_9*l>>cU;6#94ByG4qqf3;P@_yLq!V5iZm`3862;&I9%j# z8|QJUDByTq!ev6iaiE5u({LH+IKFA%_@0R)MGLnH8^?r2naJ&l@ z!trYXE+Pe_h!!{kD_}*uAQy;&O@IQoOBTo?RbY#B!7MTbuF4juB3G~re8DOT1+Fd@ z#G+J?%W?rPDg_Rx1-z;iqF1n+eu3K#3S1Z3 z4Eyg*3?Q2#KsPl4+k^qWi34I&0$@|yB{!iqwTZRqO|i{vYE^ao8Oe$!lqUi zHxVFhDulc#17%YK>Lv=b&9MItpT?%P7k&#z+uC#pds8bqn_Ao5MBCn`1N=>GJJ{5^ z&{o)gY_R~@G6A~f5!e<5@GTAyTNVIY-Y&UCwy7<)O>dcPX3MLxTU49d;@bR{)fTqA zy0}FHX-g@~TQ*R(JfLndK-*H9`j!KXEpN}$08zrt~mF${R z;yP})y;rh3eu>)&N?Z@xhMMp;)6 zW?QSV+i-{5#ykAB)DgC|hPaJ1rER4uZ_7<(TWhM@Xj9t`$3xpn)7aKp<~Gu?wwbQ^9dFxd``g-1u&wo=9kL1UuuWvgY@$0}8QYNP2 zGFrvTST(FQRiaE(L7Cqr%i&nN4AoMj0DLzbYww}}?CQJZE(xez6VSU9V0QH?yGsLZ*9QD91B6|@F79GL+EszPivwj> z2kLHk{<|8`cSEi2>U-uc3#?ri*t;BXcJ;Qq%L8xM1OBek40iP{R0-==MQkD!xQSMz zCRRb3ctvg!6|@N|N|UUFW4(&mq$^aDsrXg4LN~ceIM%B$O`+n~#R}GxDr!@%;7z6C z1GS=5wTjl%D@xm__XB$FwWI5 z&ebr^RiegL!#G#NI9Jh{P$e2tRjn#jqN!EYwqCV>Q6*YtHH>Z5t=iQvwpF6zR>Rm< z-L_w~nn9K5p*5lgYD|-<@in2wH>8?cQ)+xutEnBmX0?qP-?D0M&8hJnujY3An$-zv zd=ILJ_aAk!jnv^bT9?{b9cknB@cyHYwn1HKll8Fus+(=PPPLi3)n@B-o2%PxzRt9T zy511$SX-*AZMlxOmAc+k>qJ|tYi+$AwqJFmHINS8kUK;J?SO{TAseCI8fJ%XP#vaWb=U^o;Tqxix50FT zhTjkySVwB89l3#bl!o6_8$?HIXdS)bw2g+}G8=5iYPcP{!F8O5-*Fq^`8T|d-w5^A z@OuC#fCS+^9)O$ST|kooXp;q4lLL5@2Sif&?cKuhibwdx`}j{CfZ?}Schwd zZC8`%2u-IgHpRBol-hDrZYxct9gaTQVeM)fO<_-OYHhPAcC4nHq$F4`ix zSW67&Dac)-rFKC}?~*O3N41b1-NJfIi|DZ}vB$OK9^X=XLQC(7Ex0SS(5~FVyGjdm z)t1!NT1r=MX z?J$<@FqZ8wmhCW>ZKV^|z_!uWyJkC#Sv!nbJB(Qybli3rv$h{Tv`)|lJ9^j=sqI&fF)1|6Y?giEw5b+K@Xcf<1w*Fjh5lHKt9x>%3yian;Q_Si1mw=!&ReEqw>;+w;hlESCC-ty! ziTC6l5w3%t(xZBG_+WcXj}KqX9@n$OHMb}9{BR33+(HW9aQe@w z67}~_{o9k5P8uh&C;q|l|8VT(vA;OFfAr6eoILU`Ns@#H^G63h)Xu=q+V^B1%#9oP zYx^GQUf(M{@cZ`X4fTD)eedzXbKqm{dx3lXZ3e#T-oT%Iu&@3;`*UUb#~Ap|59Y4+ z%h310_RBEv)AzSO@aBe}Kk)bt<_R2ljr;rWdzSlU7|eg@m*>Ds9lm$q$v&J{G?*W9 z;4$xe&BJ3Kc-H%#`+gb1V;{_)8T|e)2JiQe-S?*do?mh}Ph_zF{;~VV`;)=(57zsC z>wBU5+YHM4dw#;;eEP>em@_jt-{1cIK|Bu1)-OZ9toz#=4tM@WW{BIKeRA&W|cY^xFSoE9N(>k;y$5h1^u z5i)H>$Ync1ZaWdO>qf{6UWB~sN66Pfg!~DQhzK$wV(5rSU?U=lkBBreBC=paRy%ty@!LezXGMa?NWYUY%vSyiLvaV=_I)uZMkBWixIqUMYp zHP@Y}S$Cu6NiS+%^P}dIAZmVs#!MI%1S&Y0PC$IJ`fn0eP9GhYW|=1(~E0U$7xMPaCn!O#&LhAt5>bRWRbTMC9I zX&72#V5q{v&@m2%uJADQP=KNL5)4htFqBtdsHVcu2@Qt!br^bVz|cnvhGuOT+Hhc~ z;lj`<4~DM$F!VHlq0ev(nnPkx0gXXTEC!v%W6%vE20a5Y=u7AcNKi3ofsR32OblwV zG3YE8gKqIL=!Fo2zKJm?CB>j6IR=%K7}QZ?(0MHe-O*#vD#ZHhrPJ-;Y3G$+sAn*AJ z@=cH+f5AyH%=?RB-d_y!{^AilDPAIy;(d@5-%?3&l1_?iOj4|{N%0t$6tD0}@u83u z-%CkxT26|2B`Ma_qSOh&u~hd zLsDV^O^Hn`C7#Ap;te7tJ_9N73zZTV=#;p{q{J4R63=oe@fM#FUkEAjo0Jll*cJn`=zktgvbG7?(D$@M-g*kT%~-X>(dmn|UQ|*3`6l zLQ9+bdfI$!q|J|3+MKo1=7y6t8*bV><)zK*e%gE*q|MK8#+*YkW&zEZO)O)c#xv#( zB4a)S8S@L3F&F5Jxy5A67Mn58avAd$pD|wu8S|SI=Jn-_SyD1)N6nb$wTyX3&zP@_ zjQPXLm@9V1+;K8y&&`+@y^ML!&zNt5jQI;eLf;Mohk1LL#1T0BcL5y!GYaM@1fHM~ zc$GomT^50latM5xN8kqn0>6_GcuGd#oPxkr6@iay2z*sX;70}mf3OgE#zx?E2Z8G@ z0-y8{_?nNvPXYw~1doTA!f_Z!$6q?Y*&c_topHG9j>8wcarmx3 z4!;h@;h)F^73SorFeguu_yk206BG+3D4w36R+$NEmz|)Faud{Leu8=+Oi=Hn32I87 zpmNFtRaGab(%Pl5^R6Ffb5>fy)-7N@75%>Y)?|#&Lq`!C#ehGBz4!Hq+SP;)K6qe!q6#+z@{V;pOR=| zN@Bs3#M4vKDl;YRvQyGgZc4h$Pe~7iDe0X&CFPVUsj5y%$F(Wxsy-z>GNz;t)|513 zPf6>}lvH=8q?6v1bj_cVo&;0UCwN*yk!cA>rzL<*OB6mWF~qdQfoVygrlom$TH0i$ zr9F09I>Sv%H~DGlxiBq#m8PXdd0Hwe(^6ZVmdqqB*`AiRooT7- zPD>ZOY3Z&%Exit=rJu-*g`qPRfz4PXK4a0ujKzW(i>GI-Rc6N8WoN9T+>CXZpRpbY zGuAtK#>y!(R#ly`j%zd4Rei>KWXxC}>=|p_nX&5bjCInRv99?u){|hy`UKBfC^Bo| z=&S{>S&PDFEryu2I52Ao)T}j6&sv+zthL9^T4%Uf>n1;IJr`!JuhOiwD2F+5W!7q| zv(`Cn*1E0FS}%=R>$^2;E!(r!wliyW-C65`H*4MXXRX)4to0K?;Vc^Ft}zrof}`*y z0)_7b6n;yi@EU`{6&8h$aVUI+N8yJ83cr_8IIo~^O-11o8Vc|0DE!z!;g2>7Z#XF2 za8dY_hr-u=6n+|@@MmNWE}(O86Ptri<8$y0Vh(-==HM^X9K1l!!CTB6++ye8v)mkf zi=TsE2y^f^X%1eJ=irhu2Y1vt_`Eg;-_hsbSH>Lt!^XSHnS*=o9DLE6gYWrs z@S9)`{)Nm_S#+K%WAoGze4e^Q%v1NlJoT2Ir`DKxs>04w$GCaw3O`Rh6y~Y-@;sGS z=Bb)GPo2=_seOH(dTh*7AMJT+!YGMo2X?%gY zK`cK4C1y$}|tZ_)y_Bri}UWr6Cb3)FdSfx4qFP_K*y z>W8&Jt=J3HjmaT@nY@PC!t?T}>^)y(vJ|inu0bQ}0*ot);U$JfwE7mixVtt`ktSx56 zYOyQUS#HI;#jjW|gca+XykeD<6|1AJSm(7B>yEx+y)ss;ANGp1z0tMQ-w0(2!MP3?N{wn<>SfxK9Yc!6o(EwYcDSVA)h&7r6YqUVG z(VNT~y~nQ6XSg-`Ccj2M7uM*n@)})K*66mnMxWEx=-c`l{nA*YzuRl{wzEce-8K4x zw?^Of*XY;58vPT^$pn^@NjxXhL{4TwPUe}Myvyd~qg+nD%;)3>LQa0C$tynIf}%eVEs{L;wF-|f7-?d0XIo0l(mdHJrN zmtO~Y`6s$=6WF><;_Eg|tlKPDw|QpW-euSAqujcEnP0ab2-KSN-M*@? z+mDQO`-8J?*WGpdq_=Kg^VjVs!Mgnk*|2eR!v@%fP2n3hLu}X_*suk9!`@^z>^*kF zKErL;H~9_wxv*h>l{f67vSGK?4f~w7Vc*s_?3c!d{oUTMx19~U>u%T=ybb%VzhS=) zHte4$j+8MRIfCQJB?3q80~~qF;7EnVkz*W=T;Xx#p@1Xr6&$IlIC4V6k$oLU9ve9F z(ZP|1izBBz9J%h}$kPBvKBEPsi4~C3cmcUV6p&}2fPA3~$QDyTT5JJ1%N3AYd;xhO z6p(Ln0Vyd3q@xy)^I8G9qZg1@MgjR@7myvNfb`q~a?vXw_xu9#CMY1k&`r9GZPG{Z zP5KhCN#6&X^jl_=uCSZ*F>aH-!f()>_rbRPmf5x|?6!T3+qSRp z+xA0Y+kUTX+ckCDKA~;f`}(&1*x0r|I@@-`-L_A8+xB&T+kP5s+n>=e?}zQ!r|}*8 z2C-v513UH?X2))^JN8*_$G*ky*e`?~`j(ySF zvG4gi_M2eG{)G`Ji4!PI5GV@>lxGNZmnG1n9D!cu3G{(LpzoA0C#VwWag9K)>IC}8 zAkYsEf!19DJ?RnXHJ?DA1O)mi%=rPVj8b?RWr#A$fifyEWps}%qi47>dXq1s&xJDj zRVkxwwTzzA%IIyqjJ`C==y#`#cHJ_1!7HP8{WAJGD5F2IU53PW8JgH-Sg_0R>@IVZ z+hs2EyUYV&mwBh`GF5e#Ij-$8SM^=yk+I8saCVuxyUU#PcA0DbF7qVVWj>)524EG2 z!Yd3zR2U9a7=fuUdu)X{!&R7@e1&-~RG6MwW=J~s>)Tpsys5P$_J;a z)ZMCb(yJ=h{HpRKs4Ab(ngXzzLg6)qA!-T-YKp+rls&eloZ)K9O}?f)7i!8^rKYsi znsQF7DYx~S^3td&-<_J$b!*B6ucqAfYs%}Oru@X}4vE(tny5Q0s5?AccaCy(=Q3Y+ z9td^komzK}Yjx+UUUwcDb?1XycTReB=bB%4o&nD!@0>foaaKr`Kp9@FSX&E(;Cigz2Uqx8qRm8;dI@GbHQskcm0O*I%qgQF@PSy z0eXo5=zRdtw=6)9aR9x-1N5N)(Dy1pPiO$$*8%$20O&^-pr<^5UiSg|Gyv#ltcjk+ zo9GRqi9Q2O^h=n}YOzi9EZ0PD@lEuF&_ur}VU9~}qUW_HdPi@fuZ$-8!)c;Dw~1c# zn&>^hiM|P%=r3%KIfCyomxw*)KGrtj&h6d zC@+ML@=fh1=e3Sdi-uJh6DI;Xs@bKUPcPlK-W8S6Qx@t$*o=sC|o z&-udkoU>fdxyARK7edeZruLlkTF<$o_ncQo&-vl@oQq!1x##zsH$l(&g_9UfkQfU{ zjAu#gC`V$Kc@lddkk~tw#Exquc2y^_M+S*~a7pZ>M`G7}5_=Mm*eC1=M&U;=hB$(8 z;0PwLN3b*85$q;^1bZ$V!M>_TuyfiG?6!UcdubfOzPm@T3*Hgzu73o39UQ@a;zwDU zILfl%D9dw4*~|P<_JMFT{N|CP>~ZZVdsRQmJ~EE7AKattN$)6o%|FUM368R#uwyKR zA7dHf7|VfUtiT>)&v3`soBT2Mxp0jAsvcv{X~)>x`Z4yUag6=$9%CTUgm`qDU|es@o(7rYbdUH^po zIyj;J#80|3anfbMNtfqNx|jKr?gQbZ`%XLQUe!;!kBpP<2k)eN%|Gcr2~N77uv0FD zpK=-El*@rruE3sh&v2*QoBS#Fxp2z;s-AMsX{X%V`YHFNamxMfo^mgEr`)^#Dfe}7 z%KeE`*d>C(?gI*Y%Td@Bp28jq6!u=Duzj7v9vc+)(W9{IK7~CEDC{$S8oNQ9#-4%G z*cbLRc9uJh-QrJUFND+BH}y1jUOSE5(NANqjMLZ;_cV6VJB{7*Ph)R_)7UTk410+< z!`=sH*tgsn_6mQ7eJGq^-)m>sefCDu_PlnMy`!IHUm0iFAMRQ9qIZ_P=bvTY1ZUY__&N0waZbGt&Z%#? zbLtiTocd5Wr@q(Dsr&jl^|5hI{pg)julwiJr@=Y(Gk#vZL7Z2gf%EDY?!0=7Kd-(J z&a2OKFw`X)H9{=zS~mxv4QeQ?2j%Uy7<@E6>N!Ugxe zcER1(FSw753+_knf_vS+;64p5xS#Qh?hWFi`wU!kzi=1bTl_`$g>cdRrd@RJ=oj5r z#zpsschSA)Uv%FD7u{b3jkAEpd5*>}^ECcIpz(JajbGJi{Eps$Ifw>zDAC#wGl_cL~4iU&3Dpm++s&WsU`xIiA1F zJrFK)@3hO@RsAye$hgdX@Gf)L{L9>v;4=3Kzrr!Z6^;W}IDxyu-Q=%u&xI@8SM3US zTff4+G_G*py(`>Z{|fgyxWfG;u4*i}s`30)?SXJrd#7L39vN4)58hSnntxS$5?s|j z;rkjx>}wp@*92}~yUFis&xL*MtG2J**7voS#=iF5+t=>;``YVZU;9a1^H^}r<{Gx*bh!9No>@Mqu#{)M}N-{NoJ zFN7QTH|+*~N56r;GH&2Myc_sE{|5dhxPkv7ZgTg*P3|p!lY1!Khbv|HRA{TBDixW)bOZgKbgTil!A7Wa#|t=$K=wYU6j z?V)g6d#~Tt9vio{kN$1#X>eQnOx)3)fjin4{*LxSxTAg3?`W@#JK7KLj&{$#qrD04 zXupWN-hFV_d&}ST9twB8_xfG$v2oY?=->6826w&B#69mBxaWQ0?|CnTd)_zwp7+YQ z=l$^Sd2fPy-Y>usJkJsj1eSQGv&18VB|i8p@g!i0PsDwK1NRAmzfU|D?h{}2`@~D* zKJneZPrMH96Fbe;qvJe}YFkFFexU8ISZ2{v-WK@JRneJk~kzSQq%m`g7s2{#Adhzce1}-~Gq> z>)^5e6Fl*G;fepwc;bHup7@`Lr#=Us`U3yde=a=rzv@r@m&Q~7yZ_XG9X$1a0*-hq zaKw9qBR&Qk@fkcLzVOe87s4~*oBoV=WjrH(_|J$p!876)c+S5Sp7ZaG=lsXuIsX~F z;J*kj_;30P{+029|KY#j-vlrCU*M(wR(PquH(u%=gO~be@Jjz8ywblJuk;`OEB#II zO8*63`)`HU{(IxK|1o&&e+F;-FTxxDoAJi~5xnt#2|Rdb@ZdwhgHPZs5QMkjtML|m z58i^G#yjCd@J{#y-V1{8UifOf7rqDYg`dF(;}iI32*O9>tMSqJ9(*)@g3o~Q)m<{$mLfB))#LH^duy}z1y@$c9F=-Iu;x4AoX@@eTm z`_spB|N8Gd>i)ZP4=?^)d~m=0*X%$0KkR#d_xc~*{oh;ao&W0LKfL{K6zSGY?eE_F z3s$=E{vXKp&Hm+^|LkvH`fK!$=|B8~ zzqx)rKLz{DpRTQ)`Op71;q->_=hXlE zxkO!``TM7q#D9D8U;p8ylmBzrgZ@u{mOXL&zx@Zt|F7hKI41n7m&gA3U;f3>_2c_T z|M-9Wvm^ige|_@E+TZ(^oZsT?6p3>u+L)aGgK13$`u zU)X26^%<{y)?1%n*cT48?VpE?X&U@c-e73Veind^REUx?@jJ+_}+ci?|@(2>oWlR zEZ{y9aKJC@vjPto=7+wY0l%=%7VI;I`>eq}bGXkQJm8NH_=SBoVV_al8}JJcyhD8t z%Ya{a@ZNx5+~*e_e73)j0l)BI-~D3@_=SDnPp@Bw0l%=%FFq*afM0k}_CABLe=hxV z8t@DI{Ni5!oCkiHKFhJsFYNP+`~1R#SPl5a2QeJ*3;X=ygBTC^g};4K1AgJbwdr4@ z0l)Cz+V!vDfM3{WQyyI70l%<&=&uS{mIrlWz%M+gEB!ii$iE-(3lHj6zm5&~g?*3E zK^+|M3lHjMzm5+0g?;wsK^^Yb<$j$W@C*C=;y%CdpzilIFyI#+Xrr%@0l)A-JADle z_=SCb@qxw${KC$_N7QGD_W6Ye+8pqU`~1QK?e;Z1;1~A!#RnQ6@C*C=;sX!ZAkhdj$ezU834{N`UC z@-Pqin1{T~L!Z|nPxFwkdC1#5mUHxG8uz8mBrezj?lc{_!{O_mKZP=udz1fd~EVfrqm1ojl|T5Blc= zc6pyUKIp%H^N0ui`)^(`9C{3q&_{@dUO^0kU_4|H5g~U7gsdS7B8O>+9AO|b%0eW} zL1dhV$fN*~X$caCWk?)RATg>!BCJ7TT!+M@0f}h~GKX!*9C08s>Ov;$L1x^C%wzzW zX?O^VAVbh7Is}bjLr@GKf)d0KlmbIgh8iLx^bk4943T5(5Ey2%I1ya0*1=3>~3HnFuw;MyMDU zp%Q$AN(m7vBS)lBB_fTf5hZsiSgC z8;4l^^U@Qq>EX~1eoQK(@0JCWgR^vLX zCJk6kd$1e#VK*7TZW@na2_lB2Kn%-pF*d=+*pv`sGg?ed=rJ{A#MF!za}$2dO$9MG zL&WhUh~sHK&LxF7m)7H2(uiwmKkg-ixR)jpcnT!&44>dqLW0Za2`yzLw2YtdQbEGY zfFzL?l6=}o>ggcqr$LIy2q`{er1VUX@-w0S;DP>XkUXSBo0}S7_%X9)Pcm53yBdA5)(co zjs=jIfkXBe67s>&knx564L2-KgnTd%GQL6`#^}G%VJg&NWT3;bztN!y%R}afGGr#z zA#+$8GUNJ?88wE?(Ccf)?7z`rD%4?Qpu@4g4&h-8MuxFai&zpL4zJlT76rptni|Gp z^e{Hc3}Y#F7>jVjSb`tM#)M%kBMqytJgkO#RFm3pcs+;Js4=Xjtzk80538fju$pp* z)rdE&Cj4P_EErZZaD;`C2s?sC*pLOr#)$|U1rat)Mc5b}VM9%_DK5f>dSu6h2%C{2 zE-Xjf5hda#wTK(nBW~1)xS@a7joA@5)TEp8B5tThcPxmw893BpsL7D^b)d&+UysxX z5~D|uQDy{5aU)2AA3?^15hNppdJJ`$9B4Ay*Q7Nf$LtY#)ESXe-iVy=N93_!M9#pY zG>neYNqm%!6Qgt#jM8Z;)MTj5)IgVGeO*eUHmr==No~}Q>!Wtm7_~#+tsM)snHuPF ztglNrO2BB8Na9f<4x&VwiV`sI1mm=Gm0QdEbPsGiiKdfbTWX)CJ7oT#4i zqI$xQ>SIAv&%k3mjE?akV~dZ2F+NR=@iAtMPjO>>LKx#S{~v2-9;anh{{Ls21%_o( z({W`qQ#3(Tgi)CL;69oQf(wGmzA4MdqN6NBi8`7l=F(W2XlYcMWR|4NeQ+tq^s7{s zWQ(YkWM*Vm?+b{r&OdRWi(+d6xUR&pFrid4I0!v{h}bZm-(fXHC`C z-s`Hi$`iY_*QTnieYaF?t=U$!wSS%ZSq)T=s|NM4YO1d8HLkk4@2u+TnwIM7{_WLm zeb!XB^g>I)S7*OXy*m4D>D5`YtygFNx-d`2^&Z%FR_}o|ExiZ!Zx3^IQ|~o>xAb09 zv#s}<{&h98`ZUzc>NhUT*Y=t%eb&`%>9;AHuXX*#^{MOI(x4Vwx^~Fd8*e|jEB7J?d;G}tjkmwP{amRZHU6^ksjqH7Z|dTPHyb~7%yylmaC0&F z-sY~e-pH9As;*5IE!wV|{QlxSl7;`>exB8PzaN;aUA|pMX&-fXa>zfopMN#{t4Ag8 zP2R4nOnUQ_Wal4u<(lN2Up``dvT`pwC(3fs8B1p*r_S51x19dN1<8^JyK+`?*O&ja zJgNPA*V%F8V9#E8MY7Aj+jW?#o4=5J`IPN?%om=pPlJF7uIe{*6h4p_qjCvUGhxYb#@&&;5$=aO=`}cp6Ngj<^G&3e7ox`J95HH zZ+bJS{rr@y{;F!g+sRv%lR0aFGnd?;)&EKMzkFh*6FsoY2TA&`uCwmQ8NYXQ!96+o z+)OuG`F6>Teqwy49}T;+%3ZLRor7gs$$d?|-G0qyn|6YRvhnpk?#3UTndwR^uj=m} zf2T`pA;(<1*ADI{hmGM33DaVZSi6(Ef7)o%X2?0KM(*NPU3aPr=VrLvW4pRbzk70~ zKlM3!57+wSNtq6{!}`74_ct|Vdenao-rF7c%JHTNk(++&_D{KgzIrTYU6^LnyJA0g z!0(UFbgGIO1Ko=oM`e1|=QkYac3+=ly4CER2D#$uk)}nF!`?mlVE2usM`k+Ko@)+q zJCA9|^sM!-9p>iL56g5dzUF&T-(oDk6Y^ktEFLrD$M#%2XULoFweXsv{>5wMHHSRg z-V5(Zxv;%Q-Yf4p>SA0Au1VC#xK>=VsFQImxu#Js<63jg!?_>!S@4-e{fy6w&n)U_ ze3pEsQBUKu<};7F8utSCMAX-~SGZ>~olW8QtXuXE1_UBu=Bb0X?<%oXNL&{1qIF{h$l$6RC1g>y%2E;1*he#cy8&PE-N zxy+o7dLDC~IUjXB)&kaqsPC~>ux3P^kF|s~CFn!8*0AP8-H)}1H7V+UtW~U8L1(hH zj5RIlfvk0`c~KW+Eo4oM`XFm1Yi7`~Y%OI?jd~$#Eo*Mn4Oxp>lcRpfTFsgrbwt*3 z*7T?+vevWa2VKqf0``QcFS1v#X9OM2_7e7#s5i3Lu;+wxQ*19{Pm1~@dlh?D)FIi+ z*wdmO$zI2v7j;SYLiWU{PqJ6CX9gY7_EPrLpfB29%bpu_N85|plcRpgUd^5zbxihh z_VlP{ve&cc=Yp;o{{2YQH^X?&X|r=&!sBsXo1O2%-mmA&&V6C;*Xzm7gJJL2>*X9b z(?P@g$Pucl8;eN|>*Kj|kQGaFc*ZrDC9X8z0c9taP z_k{aBjk;`@57~J??ERWA**QRAK5^choevb|TXt>`d%xym8ui;SU(=}LhWVVGKNRMB zrt60FAUm%ptQXliMqxckqu$Hjuk|L=eZzW`orlEUuk|WBCn>CFoM&g}C$aZyy-TAm z9M;3^yrr;S+8LLe!xYw2&bzbonb`Za-e%`EvG;2|=KMQi0MFj9_1Z@rIjrZIo*dSD zA9dxhA7tl6h5aJanZtgPoiD}Sul**|ox^^Voktb+tL&Vru%Bh;SB3p9tA`HzVWv;B z_iMk*&cO=%sgHU!d%yPE?A$E&e(lHEd0OoK+OK`ovBQ4uqn;i1`>ZZI!~;I++aX@a z&hZNIM5cF#cq2RaE5sw2{vG0#?3}O=&t!UdhG2`n&FbYtJe-~P7UJdX9JmlqXL@~zx3hEOLOh=7_aR>QQO6JQe0Kg^i1#yH zKjZ`1d37OQ@KNUv`9!AohkPT`{X;&Iorf3l6(2c3$Y(Mh5b~Xj3xs?qJ8v)KOW8Sm zA)m^4LCCj!>FJ|WmhI}&P4I$sm&K(T- zXm%c9$X7EC5%SsW{KAm$W?UlV!x^6l`Ld6kBIMHYPhd5UqSQ}L?1!) z4@BQU^b16vK=cPhUqH;$Vm=o6f8_p=_eahj`F`MfS)LQ~nV7f4{3PZfG2e)JMa&;! zo)Gha8288cKF0AeUXO8kjK5=?9pmX3H^=xm#=$Y(jd5*^Ut^paFA`3eTU#N#XTnaZikIB5#hIImRWi??>dx@f^j-k7Ilg zd2!^#abJ)7cRcSgo&y>AZ}|MOeKd03xGzSo8+mTzxRKw6`zPCn;yIb&e#`cc$YbMv z5ZC?K4<+)}$XVmM9Q&rkbvDe8Y~769H1g88-bFqdxoG5}k%NZ$nyoK!9f_PXt_#&4 z;+mtR&5kMz5zA~4%N!+fvPryTwD{#X@ykiM4N`136q>~>Tf{6S9_HJ`T2_g>w2QT@ z&W*~i$&D(m&5f#9mm5{Jp^L2)H+Hd=DlyKy7-vz8vqFrsDwod{s`J%_+Pv6fzPhqL zze4A-G!=&An@SD&rpi%bpiTL_E8 zLalg9t=Q*^(!j##!jQt~QbS>M<)}igqN%V--&rLFx=IXmMa8Vb#zJ#pW2vREv2ul& zXc8}mG#9Hl>>{bDu)!ul^TlUDn}J_RZYd(s?o*v(zs%K z<)q?@s#(QVRn5gsrIzBR$`!@x$~OJps$!j3X&tPza*f8VEsm>LR~%QhLA5_c-CuG(CxtK3p*tJ+%HT(PaRxvIKCRJCG7MP0?f%7GQDDuz_FRWwx0svK3J z_gYb3HM(L&)wqf^m6Ix}bskH5MRP@)c+Qr}wu)7i?G*#XS_f8&wN|aw*Xt@~Rc#Qb z?W}08+^Fwus#sICxuULWONHK}{=cnaOO@D8WkY3i<)}(MzRp+~U0GcN*pT3gvxwXU+cYC~mxRj2;Fv2tM5CUKt4`uUd1HC0%Wt##Cr7K4LU<*V^vGlR{d*p)jIvXrfO}~CjH&1e{a#>)tXba zVj*>!O9OMOb3?>K8giR8&sK?tY}EW(n`_B!&9&z`bL(%L>iQBJ;93Utg-t*B9#Yx-ate6+`m%#fE%+Ra1U-X>@*dVO(DKM1FOCR(^Fw zbAENPCBM3=EkCKWDnF^vo}W~?CO@fSZGKX5U4BwkXMS^OV}5gCQ+{*hmi*?5t@+Kx zZF$`XVa^TI+!>-d)S&sJxmFsj`NmwEr8(2AxznO~)28{@uKBn|^Gb88xUMj|s#9}t zljfl2Q^i)zDdtmkafs&85Y3?>6%EB9nmcPXZ`M}MDz2?)F0L)M6xUX@6`RE{n>A0G zHAk8?Kem=O6}MJyDQ?xA*jiPm`*~ogx}u>}UDc#HFi!XKEZzGpx`*3KO}f{$wv?Kx zHkCScUuzvHbyjgNH|TyGr~7tR#hQv1-G}YEr`PHJ+@yP#`%uhZ_g#Bsi|(CumE&~( zY|?$QPWMADU#okfPHSbo?u&t1Lx+)^+f%&Fo{Mo@jNfA17W<^dI4#C!F)oYoSd7DB{1xM_7;nWmE5=tbu8Q$g zjH6=w6yv5CFU2@1#z!$Oit$j4gJS#>jxG>(8h{z3#h#T06r1Rv4vwu}N#oXx)S3v`$RYJ*oAi*sOc8MQg(f{cc;Xy0A)P z+H*~X)%to(uC1`v)~e3JhFrDo!)opKO}ZDGikow7x*yw$TXUVdCp(MP`C9GuqjYbM zF4SvpADCaoUaxy}W1%TuTO5}kU7VC(rFCUhu{pm{_w2^v3VANt@^yt(@>jIy#}!s9 zK3J1)FRax*ulu>ML66m$uhSksy0|GnuDDraw&dHj$B)xGv#D5JsMjt(s!&&$R2W!T zt-XCxp`ox@-^mr5f! z(7!ti1KH1un+mgvoAt9Tg*DpG+qM2|DOMNji?zj3#k%68;=p2CaftqID7F`y^!K=8 zb5ZM%)}XEW$?D>&;s*U>v%b?=Tvyzp|86dB($C`k`NjvW?)m;t9r-=|{bc_WN1Up^ zAAR~3W3=RMJ4(MDGWOjON4($a&Ut$0kw?7O>I#27IMa6@{ZFgQ4Vg0Xq;0M4v!^c^ zdGEhkUBeOA7}F&e-1b(h+hhFKN4~nX)y;nW{*m8&v(yzbAf?w+swa%9D8 zt!~MIuZ;Z6A6ng@hu<^?Om3O`y;$)Z#m4(z6ayaGyK(pnt!~|t+Dw1`*>kO~t@oad zuRPuAo;m$fjn6#U>i*S!K&De4=v&=;`weUS+QY5xmvcupzW#$&cf*56XL@$udt2T8 zN1fLA>OHNlU)!0DH{99kPJVVmrhB*C((0y+pVj!iReE2m=QTcdO{@F!9~Wi%_}t~K zZqB+DjnysEp?`CE+}3#A@K*O+ztzUD$<43YU)O)kJ&h+0Xmt-S{8r;1c5Zc_x%u8q zzyC%>t9#^y2O6JxZ@GJM+YcI_{KsQJb>n8Zd=U-Uvj#&CwRH#WSp%pG@0E@}JgGB>!gU<@8@znhWP!UK~d&s*wB+dh*Vd-75@dF7yt_x$mIrS7TQh9sBOEp^WiJT&=peN%H!l zCGN!9Q5k1??bIc%YQJNW?~GXDezf-3q-o$1cgl$4Gal71zr@vzJ~0{o*UQ{#FP@Yf z`RmKv%xNc^M*;2X>9v=+hL+Qkb8frL{XKtr^5|8UxvRf0CgWRsoPU`c_q8*V+7mBx z*YAIJ^1H(>bKh7y&O8lhVWnP|xeFefkevUIOWkgtJukW8cbB>~zc@eRWtV^NQg`kj zCMU;y^-_2FoTCK$!(W)4_yaC=2k&@c#@|kQ zx5a&D?|I3uUTtv?teKyTc&5eObnr#ynLw+%@wOJXW#ppd%9Sl{{Nsz0F>_knJttn0 z@w`h$w793wye#?IJ}vGWzgd!$dbhZSXto7rSkrxF&gH*2V6cUtD7z4z$VL553sUJL}ryvYjt>8+N%a z`TjeL-Fus^%lPH@A6x7Wop61!<%ArW3vA)i=BVz#*BwP_1i`6x=A-DQ~Vn@Dc?-)_}N8nK+T%ui)$}(|Lt63 zo)xs>cjsQ@<{$g*uZylbyIL|%s!MbGI_4C|b zkNhZ^d*M7c@8XBeLxVQ{m%Zn?AHMNO^45EE-TmKOpZxNLx$X;7Ix>Df=(@S?FE6CY zoipdU`CszMTSv`xzdU(^d2Z0!_x;x#*YxP4N!7+V?#v~RB|rYw9Cz&Dk7qpo`E%#E z&NWXY`wpAq&Ykk(WOV;I?&rIAd34b3M?89=oASjclXq{u&@DZoGr4)eh3=AES8W!a z{qsL{p{rf+)8yKBFL2*I@ag2{UtHi0di81Z^uPi}UM_FX*#Aj>J^ljsdd;)Rm_zmV z2EV^BcSPe;vkhkWff$*rH9=^h>X+vK>{XSl(=x;#d(k0CeCaCa^I zeR9#v8SYyHUrN3>Vuri!cQ0lBi1S~a?%q89<)rqZ>F$DeUrttEGu=IL|0|h~;*3M4 zyMA?lNG>f+cmI9*56O}jrn#qE|CsqLc3L*gz5Ay>CHI~-&7Jp^*OI;WndWXgWs7;3 zU^93AWUBk__y3&S+dkEOZpQ1$%@<5{Lw4<|b)&}Oy}nc3-pk)emb^5@O&#*rgA9%hyY4(53g9Y3A@)PH|fBg7^ zR%G>Xw{@K3`rTRS?rS^8UHPv{ciY%=+?LOFdBR|MyZm{aoByvWcjx!Vxi5XT+SM!{ z=k8oxo%ww(-C>+-J*k&#{q5QA)H`~)srQ`idcEDtJY=xJCyzMWHQwIaH5Jcx5Bh-}-Ty52)X{z1ueYA*Ubv;pa|UZX=<{c~?a! zeeO$r-Mc%S=^Fmj*Twwzgs-3BreD|3jkxd(_nXcAT>rz)a3h9xdDLK+XFfL8t$VS* zd-CeB?w5mVUES$p-EUXaX8xvgUK-=Rx!)(;iT8|g7hd`aS2uTz+x3}Gn5PXEdd54a zyCE0t;2zs>y8FuGJGk1bPIqs9vdim+wtdo$r@PS)@92jAdbFF^XD3&@W3(H0ewPOh zwmRa#(XLeZq+9d1)7(R2Kk43n@HBVE-Cebq)G&R(1^Eou|5& zUf((MY3(uQR9AQ1F7E1`Pjx%|ei!%47f*5j99)tquI2EP-HlUrb5CyjtXucMZka!PjUlZ-oyR2-$`!ekUcZM*#S46=qjJv)9roc ziEf|0_Hys+e4^WLZkLA-Hht<>n%p0I4{$%7(B$qoXMo#(&n9=&nyy+?YP?q7ae^Ch zT)n$u(h2Uy8|&T7y-#pIf4SZ~f3WUn?>gR9F5laoG4*)&?$dj_M?Q7DdtujoGC$m) zZye{2`N2N!h-t^UUlcy&_S^S3_u0{19zodo-CsY}z4`j5-0-Q#y4@P~b>G?NSa;AB zUEV=FgbjBd<4OZQ?M|O`jC=aRPrH)`9OEuo_vy@sx8=5@-OAJVb5~C|+P!-Fey(P> zquqh8@0a=Y9=hcyH|z8JyO+;6%1wTDfA_`?N4ZhEb$JkB```NFD7W@|1KqhNk8(%7 zKhSOMHOj4P>Z+xsrgp-scFn^w}Y9`tKUtKD!*^p8j%!yKiEbhZ1kZ zF?|}`MOzPXXZ~ck`*y>j?xYpN-IFU0bVPyZ+*#?%mHG?w;!yn)xyLn(y&5#xR!OiM~x9i^t@#c@Cb7 z=Zy8rycS*)uZ`EpYvnaZA1LpI_r!bSJ@Q_8&ykCAEx0CJ8?F)8ifa~pAa*Uerd(UD zG1r=F9_y$1Eci_LZ1{}$toY2LPnFM-&y>%W&zR4e&phgc+zZ?j+#B2@+$-EO!DrHS zFX^7*-r^qPUgMsN_1xTx+>_j!+@sv9+_TX~%e~A!&ArV%&b`h(A2~5|fjPn4V2&_X zm^0Cr%UohkF}Ijw%r)j*^zSkknUl;-<|uQOIU9Yx%w^^@bDKHNTxZTly_B_pHG#E( zHG;K*H6!|lSxZ<`SX)?QSZi2wV!bC=XA+wgTrm?oM#sj-oZp>c5p1|I~9>HG0o)LZ5>?Q0e>@Dmu>^1B;u^#|?5qlDQ6MGbU6?<0nakH1P zr?I!O$FbM3=S3d@dm(!wdn0=!dnJ2j@DbTw%AU&J${x#J%bpwi6R;PvC$l%RN3&P6 zXGfnodpUbLdpmnPdp&!8)X#|phzW=dh!Kbth#8`9omhgHg4lu>gII%@Blb%m79l1f zHX%kKRv~7IK6qjoVj5x_VjN-}VxH)$AQmDfA~qsMB32@13O*={rHHABt%$LRwTQW5 z{{~_)VlrYgVl-kkVz%I$vRICoj@XVEk64eGFLDH8L1IE;Lt;c?MPkP2`zMwprX;o` z#w6Ax=8XL$h((D>iA{-7iB*YNgD=ZsSz=mZTVh;dU1HwoGa(ixCMGr}MkZD!W{!0U z#L~pn#MZ>v#M;E%v3`MAoS2;0oEV*0{Vm1pvCe^5o|vB4o*184pO`=L6mkJ_0&)X# z1abv(hFCX2E0tIb*ClA(telB)25TB-bS8jQvQ+MafCYP03NoRmoXn9SgZE zIW4&@IWD;_IdAkKkqcW+tlXF!nOvEiIo8FHOOsQRTa#mxYm;-w{wU<) zK$}3LK&wErh;=|{8E6`48)zJ89cUg0hQ2RoA!s6KBWNUOC1@tGt_Up!O$BWQjRma* z%_a7aL5o3?L7PFNL90Qt3BEzoa?o_pcF=gxdeD3#XG9A^6G9t8BSI@eGm3RjXh~>F zXiI2JXiaENv7ZfE6q*#;6dDy;6`ED>C7PCnriHeJ#)Z~}<`w*kriG!2p^c%Dp_QST z#kwrCv;or8(ALn{(Av=4Vt*a9I5au5IW#)7IyAdj=Y^JsriZqN#)sC2<`;P@S|FMr z+8`PsS|OTYtQ$j1L{mgtL}Ns2M01S&e$XP(B+(|(DA6j>EMpxSS|*w%+9nz&S|^%k z^zEUAqKTr7qLHGNqM63JHndbURkT$!Rp%F)b&kJPkuGmXqnFb&uSj04sI^N7AqSO`o6HUcAomB375T_r39rUF}mvA|kj zF0p?VECwb6n}N~5YG5|8P7{^`(}C^4cwjv+pXe`z1;K=1Logy(5zHvoeZrDpO0Xpu z6RZj56#HqxqF_?6DHs*33T74SNMTtpE!Y-}3)Thmiau9Z7)%T{1|x%&!OUV^DlE;I z+B>fqV}rH9++u$(SR70aHV31F)xqpyohvL4rU%=D@xl69#r&cl0~QDqgbl(7VTCZm zST_qxgek%nVT`awm}BfW28)DA!X{yqu*$2%EMpxmEEA>)+k|n#I$@sC_X`X4Vxq87 z7%8k2W*X~yVW}`x*eZ+_)(Uft{m)>rFj?3vj22egB4!)wgkiZbUDz&+7uE~&4L${9 z!7yRiFpL;h3^R^($FSsQ#FSynFlJaY%sKXBgGIxnVbd^bST)Q#)-l7fVcM{57&ojN z<{f>|uyB|-Y#c@oD~FlKx@cHBOdYlkV~4fF+*gJEaIp9z-V1DAj2>1GvyXMwuzZ+4 zY#+uC>xcR0?9U4R{V@O5&mZCE8vh96_4|)dtEI<#gvS&6Uylbs&$piE)AO&VhD)z! zJ+DWvZ#}P1uXjDKSFe9PwOx8Y>v=zVf9rXFdcW&=zk2^x^QG&tp6j9Ov!3gt>$RTi zrR%qzS}`*Smx3t?S=GjhH@<4n7ZkJ{^2M`n)>$yr>zYc1)jV2cM@t z-wr-svHuP}Z+-q&Q>Oc&gZn}EM+f(Z?w1bk7i!F?HPijn!TqHBtAqPX_ge?|o9;iW zLDT)%!TqTFvxECn_iKmUuc}F-Hcj_)2lun??+)&7-R~XT@4El3W=->R^6pzI8C)H2x0&d4%Q2;A66@;^`wLKMC(fj>xb4%REJUmeueX+7&;J=6Nu!TP54u7mZCT01-dS`Rx|54Ap~ ztdCkRQ`SqZpDDF?T2E8fQ?0Kl>#Nq=l=W8Yuhr;jJx*DVwLYh;&swij)@y3^sNK_g zp0b{6eNS26wce+!_geq0rce7p%6_2zA!UEievz_YX#Ys5_0xWmvY%*wN!eet-=yp} z+JCGDQ2SBJex&^=Wq;Csm9k$^6G&~K_Oq1zO#55P{-*sdWxvz@XWn-0hbjA^_Q#a{ zQTt`eeyRO4rIt|pY07@8{WWEO)qb0@-)jH08bj^JDf_YZ=al_f`*q5GP0b;-huY6m z_H*s;Df_$j`;`4&`@hvBDjrCQ2NWNq#0QEOQsM>04=J^ZiYHRy3B?yF@rB}zlz2n& zht)7D9!ZHu6rZHTCu098@rvS?l-fqcGb!$N%2!kEu`Y9lz2+3VUEmb~~lFul=Ny%@-{!{WD6tAW7!IXSZ`C&?aDE6O{FDidbsdZI8nUYT`zf8$5m2alxo60|} z23GlKNja5FIlFur?P04SS@22Ft%73k9R{3yBKCJvWB|lca zoRTjqe@>~TRX&}PPb zmEWi2_saKE@_pt1R+B3|AVm+5K9HghNH0jy3#1>U)apu4NYN9dFQn)T(i>9r2I&u0 z!z(=^MURj^k)lsXuSn4=q+g`g*JJGer05x9|EYNZ9)C7P?~wjsHNVnBQuGk%BPsfb z^pX_4MEXfeEwJ>I6g@@yN{YTBy(L9&k^YiWBP=~8MURm_lcLW^uSwBss2QeqSb9#1 zo+EuHMc24mZgWK=wZ^wQuHzD zWhr`@^s|&&X6b1udYbgL6n#y4TZ-N${mp8erN^b{ank2f^f~EuDS90>&(uCk&r8ws zr0=EZd(!(-^gii-Rue5fFhviPKA55pN-s>&3#A{X)JjWFOwkjiFQ({=(i>CsM(K}M zLoGcrMURv|nW9fhuT0S^rC+AhR!h%J(KDrQrs$i}J5%&d>7Q0}Ej=_v50yTeqK}IG zr|6~9PpuYPdTNTEDt*kDe=i z*Q4)B@Ac@t(toX{TY9iZ50*ac(TBzUJ$f-U-qdERwdT>7|2AD3S4(aWWu zduqw0r+f5t>FXYSU3$AmZ z#XCK`Q~c9vCB;KMJXCzt!$-wSJ-k%>)YFSVJk`Tf#aBIiRlL>1Tg6|kM}c^(hsTP~ zdibo^zsCbW&jNZEi068EuK2Ep?~3<&c(3@c^)wI<_V8fwVGkb`FZS?adK}Q}Ks?#Q zlf{=kd|ABN!<)sQtp|d5w1-EFPkZ>Z*uRHY(-VQ-2;$iuo-MxZ;oIWf9^NhfZ9Nmj z!#zA)eB8sw#mhasT>RYAOF=x{!_&prJ$zlf-NW0(-#s1x@puo97oYd=dGUG=uNS}f z^j;9p_wao2eGlIk@AvS2)rVM527T@E0O)5P4}ivcJOKJ#j|V`HIj|V`n)#CxsYxj5n^jeYtM}$5Lj|V`XjmHC^&&uNg&}ZlI0O+&y zcmVX-dOQI7tUVq8)yY^-3Ec}G4}k6sj|V{aipK+>d&ipx;Df~DC(*s-@c`&v^LPN% zAH#Z3=w9@A0CaD9JOH{^JstqvyB-gK?q!b$K=-!C1E71|;{j0JxAm;hT<~}RG&ejR z0L>MT2S9Vj;{niI@^}C=w>%yI%{7k)Aot2K*5g8R(c=No-1K+=G*>+y0L@*G2S9V# z;{njz_ILm^*F7Ep)eBiq46Owo4}jJNj|V_&g~tP+wZr29&|2d00BCLTcmTB4csu~= zpJhEXv=(_h09ue-PKx?hX1EBs~)}upfvBv|Twb|nV&|2;B0BG&@cmTAP zdprPI+dUott@R!cfa<0^9sunH9uI)_29F0odxggXpuNN60nlFJ@c?LV@pu5V*LXYt z>i=auK(rTmJOJ98JRSh;RUQw3_AZYHKzo_T1E9Ul;{niK=kWljj@){NXfO150JJxH zJOJ7&Jstq_EL|ZPJ64z1E9Uuo8PW(to0btUhMGzXm9p-0JK+oJOJ9eJstq< ziL_x_aw*qFBh|0Z?q@ z@c<}R@^}CgJ9#_+ilsb$O2t;*{FNQ&csu~=zhga86pML00E*2#9stE^9uI(GH;)HE zv7E=xso2ir0Z^>x@c^if&U&gS7W8-k6dQUx0E!ho9stFT9uI(GNsk9Wv8BfYpjgx6 z0Z{B|Jy;ZrdOQG%O+6j}#i||;fcgk|#juHDS&yGpv8~4gpjg-A0Z^X-j|V`pu*U39stGm9uI(GeUAq~^@P?FM!A5;1EAc%;{i~v;PC(`ckp-sluLL#0Lm>q9suPU z9uI)}D_IX2)^JOJvuU_ED)3wb;M z%8fi80Od*^4}fwfj|V`xl*a?0+{)ttP_E_i0H{Bm^{7!U=J5b1H}iM^l&g6>0LtCG zayb0l9zVBoJC6rIxt_-Zpt?%yX`@`w;{i}^=Ah@OS{ERd_rA(k?t60BIQ>4}i1{j|V_nhsOh;z8oG8fV2>g z2SD10#{(d(#Nz>wcH;2>NK5f}0Hm#WJOI*KJRShf0>A?xEym*kkT#>Z-Ppg!10e0j z;{lMCtNbB)<0Hpm`Pa$bR9uI)DA&&<@T9L;CAnnNG0g#sD@c>9$@^}EG zHF-P$>W^kUh@?e%JOI+BJRSgPRUQw3v@4GXKw6fko<-W0#{(d(%i{r1pAzf6AuY^P z4hS_fJ^?E!2s=KzHPSS!s9sp^>9uI)DVvh$v+Ofw2AT8PB0g$%r z@c>9`_ILo)|IvCtNsIP)0HjTOJOI+FJstpQ*B%dmv}}(DK-#v)10b#2;{i}#9qSn- zE!^V)kT&k|07xtMcmSlGdprQr(mnNb($+m50BP+W4}khhT8}Ad@g5I=w0VyQKw7=W z10e0*;{lMC@9_Xg+xK_?r1g6|0IEN?o>XE19uI)nfX4$MR^agfh#h!50AdLq4}jQ$ z#{(eN;PC*cf2H-X5{vM70K_Id9ssclj|V{P!s7uD%kX#r#5O!00I?2_2S9yW^tXvczIM9ssc!FGd6V_jmxr zZaf|Uu^f*FKy1h30TAo)cmPy~Z#}idf;=7ou_2EKK&;5)0T4U#cmTwbJRShCC65O{ ztjXg6P=844!6g>u@c@WTc{~7ORUQw3*pG1%F<#{{+VtXDBKG1%FWqLdSVw)ZhfLN!;1E9W7)^kiO z)Z+mV8})bq#7aFL0I^e#2S6;<;{gy`^>_fpT0I^B&QiexAQtQK0Eo?cJOE;~9uI)n zt;Yi(mh15Vi0yhj0DbRm^>_f(m%)0Pi3NM=!NrC>9ssdoj|V{P*y8~ZOZIpGUU|CJ z;{gzB_ILoqo~;L(ShU9jAU5ss0Ekt4JOE*UK{2cbr_(#I;!~S`^N5uYleAqwF2m9yw zVgI}y*gvli_Rs5u{qy=^|GXdAKkpCr&-;b_^ZsG~To2ek*9Z2`^@9C#{nm%;3H#^z z!v4A5uz#*U?4QpA_Rr@7`{(n5{qy<3{`ov%|9rl%e?D*6Kc7GBpZfv!&;0@W=YE0x zbN|5pxu0PF++VPN?l;&!_aE$^`w{lf{R#W$eue#W|HA&cpJD&p->`q~ci2DoKkT3R z0Q+Zt!2X#p9bx{!{+Um(f94nLpZNy+Xa2$dnUAo4<|pi*`PvcYFYKTB4Etw(!~U7? zuz%)1?4R`j_RsnN`)9p?{j+|+{#j38|Ew>tf7Tn=KkElf^w z^$hmU`Ud-Fy@UO;{=xoP4?Dv82>WNfg#ELA!v0xLVgIbJuz%KD*gxxU8rEajKkGB> zpY0{dsbf&H`p z!2a2f(y%|l{@Jf!|Lk9|fA%xjKl>Z(pZyN@&;AGdXFr7fvp>TA*)L)L?4PiI_EXqD z`z!39{TBAm{tNqOKZgCYKg0gnuVMe}->`r7bJ#!oJM5qR9`?`v5Bnz`fc+C6!2XFB zVE@Dquz%tS*gx?F?4Ni8_D}o)`zIcO{S%+S{)ty$|HLn_f8rU~Kk*IhpLhrMPy7S> zCmw?R6Cc6;iI-si#80q);wjj_#{&@JE!aQt7wn&S4E9fa2Ky&ogZ&e~!TyQoVE@E- zuz%t`*gx?f?4NiL_D_5W`zKz6{S!aJ{)s1H|HPNDf8tHpKk+B*pLi7ZPkajdCtij9 z6Tia#iDzN|#J8}2;$7H3@oyU9Vc0+MG3=js8TL>74EraZhW!&?!~Ti4VgJP6uz%ul z*gx?(?4NiY_D}o{`zM}<{S)8A{)zWt|HS{WfARs?KluUdpL_xKPyPV=C!c`*lV8C8 z$v0sC`zN1+{gdCp{>k@X|KxwLfAT@t zKlvf-pL`MaPyPt|C!d7Uj{tEjipN0LC-@^XM zchivn!v4vJ(~uv-{>hhN|K!iGfAVSAKlwH6pL`qkPyP-2Cm)CXlb^%>$=6~3{5t{tx>{4}krn55WG>3t<1~2e5zi1lT|N0_-2X0rrpn0Q*Oefc>LS zq(QHM{i9#N{?RjF|L7aAfAkL6Kl%skA3X&2k3ItXM=yc>qo2V3(Nkdm=qs>)^cL7Z z`U~tIJqGrVJ_GwluYvue-@yLSb724IJFtKB9@szn59}X32=*gyIc>>oV}_K!XV`$w;W{i9#O{?W5w|L9w=fAlWcKl&H!A3Y5Ak3I(b zM=yi@qo2Y4(bHi6=xeZl^fuT(`Wx&YJr4GdJ_q|puY>)g-@*RT^I-qzd$51>KG;9{ zAM77J5cZEg2>VAbg#Du*!v4_{VgKlhuz&PM*gyIs>>oW6_K!XZ`$w;Y{i9#P{?RjG z|LB{rfAmh+Kl&%^A3YTIk3I_fM=yo_qo2b5(Noi)ulk_3!v4`;VgKl{uz&Pf*gtwL z>>vFW_K%(m`$yk}{iFB7{?UJ7|LDQ6fAnG4KYB6jAN?5ikDd(sM_-2hqc_w49sL>h zj~)&CN1ulMqgTWJ(XV0u=-IG;^ljKbdN=GJ{Tud=9uE6QABX*;m&5+i&td=Q>9BwF zb=W_8JM16*-3L7$_K!Xf`$w;b{iEN*{?YSc|LFU$fAoIXKl(rHA07bvhY!I1;RUdN z_yO!6o&fuYFTnoc4X}UsgAY6c_79(c{lhC@|L_agKRg5W58r_O!#iOA@DJEOJOuU+ zAA$YDOJM)-6WBjI1@;eLf&If@L$+JJQ(&5ABO$Ii(&upW7t1D z8TJofhW*2vVgK-F*grfP_79(i{llwa|L|+rKRg@u58sCUdprPvf5ZOa;jn-BIP4!@ z4*Q3n!~Wsvuz&bE>>u6^`-i{7{^9YkfA~D?A6^gphu_2g;rXzC_&)3(-Vgh?{|7&S z{fsfeFJQmRV+22eJvPq~{08>iyoTUMu-C?G41NWB?YxKJXR!Cid*r?Ho`e6vt_9a5 z_#^CEam|8%!mcIPH25p*T64{V|H3{CK9k_ju+NImEciFx1%HjrHRfFK-`HGaPBJ%{qrtCZbC)?B{5&?dnd8ClV{@N1 zAozi7ZD5UHtzgXv{vlgSSW|+($krOxoZvsQwTLx|wTU$<_?2w!Vhsy^CR^KBsj-I|I79Q_JrUMv%P{ngS~@2B>2f}Z()xKely#9*n@%}&GshtsNh$#y^B38_}Of4 zV~-1dH{1Kz1A`yV_D1%|;Fq(#lRY%}>1=Ohj}3l1+k4rAgCEcKX7=dd*R#EwJv{jN zY;R|e4}L$}`-uU9AJAe0VuauqwAg_dBKQd{wjjm`enX2rh(UrM(P9%~6k-)(mf&Bs zScaG;_!}+OA?6AGM~j7siGn}UVkKgx;GeWuikK?+D=pR{<_i8xi^Yh^fsnI_{lA|B*zSXbIU!+ zL4zONa#M2D;8(ZYl^izs*)6vv#|?gW%YDg#$%QQ^?()Z5u1wAx{PVDX%c+CE-g0en z?%=<-T%4Rd`137SCua}-eaq#^>4U%Da(#0C;Qu!*08Jp&2bflXW`K5ph7jrrOj|%> z2=xZ0J)l8^dIZxZ&?rK^f@v3M7@?j4_HP;oS_hg(sDCgm1WhE=N0?TEW)kWrOiMvi z3H24GwV=6#`U}%y&}2e=hG{iuHlcpQv>Y^@P~Tx%51LP?|1d2GO(@idm{x>l6zWGz zOF~l$^(Ce?p*e;66Vsy5q(Xg)X;o-ep?<}*EHtf9-(p%9npdcQF)a*D3~daJ46O{! zEY#1KmWHMl>T67ELvsuDH>Sm*$%XnH)9TRdLj8_ud1!i}zQ?paG`~>)V_G1ZV5ko= ztq{#H)DM}Kh^83oi%e@oa}4!IrbVJjhWaGaD$y)M{gP>!Xqsr7Xq=(m$+S;2P_$4q z(NG^{S}B@osGl+|6-_nNSDDs|=8E=;1{>mubIf zz@Z+@v|%*jP%mcMF&c8HCo^psjTx;O%{kPc!TwE?Mw>>X4)toLU87-#dN$Lx(YQms zn`z%@;GrJQv~e`@P%mfNIU0JXr!#FGjXl)cnf8tbAL{W;n@6J$^?Ih=qv3~oKGXKm z_(Q#)Y5y>QP!DKq07ek%1&tlR5JEknu>}}Is5dnB0D}nih{h&h6roLrbxz)(UxCG0NNmqTQu^O07sNXb} z1JeohoyK}#KB4~8SP)Do)Q1`?f*FPSQDaFkrBGiA`#0tk>Q9YD!K6ZcsI_)gAMiA#%5u( zpd%cu4;PaT z_35yG>eY>1!>~g=yRmH;cc^za_6-9M_3*~VVdSA+-q<+|9hMGL5B2rN+8-5j5B2xP z;$iZkKHpe9%s$lb8_S33hx&flKlT2w{}p%uLO%fW2H*h*{Q}H8fCnJ-6EJT99)Qqq zz`O@|075?k^Cp}m4}e~;c@{$d0`oH90SNsK%C z{t)IB!2=NbN0^rc4?yTIVO|qF0HObcc~S5H;7#HF#H)e_AoQ;=FAMiG-WEInq2Gmh zU+@5gei-JB!2=NbWtevc4?yUrVcr@%0HNQ8d2jFlgnk_6&A|f@`gNFh2M+*V9_BON z9y|b{--mgB@BoBn>h zn}r7euNLby-Yq-;p`VL+yYK*nelOsRPqe=zcmTBD z&~L`PXY4narz+2O#usGA}0{fY9H` zyq#RGtMl=u-ZDIS2(U&_3ucmP8GDf6NdkK#?m0}%REnRgWr z0A5z&S-h=y0PwmJ@5XcXLO(3?#u6Wgep%+7#RCxfX_>bc4**_U;%&v>=D`j9xXhc2 z2O#w8GVd-PfY8s2_})Ceq2HHzfAIi>eqiPe#sd)gg_(C44?yTAX5L~v0HNQQd5`e` zgnne?C+1Pct4zLvcNq_W@)`3qE59+1GhS!%9pyjffyN6>K7=sm5+l>bx^m{Y!Hy(h{56-;dcmVK< zlP@ZNG!J>`CuiPrJOH8J9Qmht&_h2u^QPkg2>t5JyN(AS^s_T>J05`0@6NpMcmVLi zlMgFDPVfNWmB#}R`sbOK9uGk1uV-F+JOH8po_X={0N~9hKgX+&2LSIr`FrT+M}BV} z|IqKxy#IIrLO(#O4Zs5s`URpNSPenwCup?=cmP7bL90E$0}%QVT5SRzfY7fH{laP( zLO(;RZ7>f&SHDB6eL(-976K1I=#OZ%5_kZpoj^aKmI4nz=&y+0Lcc|;y+D7V76T7J z=+9`i8h8Lg|3<6jzyl!mZ#5p&df)*F{U5Cs1P?&y4{5a`cmSv!K|i9F1P_4pC95%! z-bBAit35$~q80@YKuAoMS_S|&UIp}(osI^h8b z{ZFkH3J*Z&k7~72cmSxKLO&Jzr=P0TR^b5%{Z_5^3J*Z&$BI5{HCmxxtJQAd0SNtE z(RUplfY9&NYQOLRgnqDA8-@pfS~2uuYRB*ZgnqJCTZRW9^qaNXGduvHAFb7<;Q^pl z4ZWJ$H9P>JpRLul;QBK(3{Mmzwazp>Ri;sFT#kF6FG4?yUTY_*bj07Cy{ ztEI#P5c(@yttB3S(0|!#G4TM1{acMDwVHSUsNIC$gnrKO9joyS{hqD%6AwV>2W_>X zcmP7bXsaE?0}%R2TWu*GfY5K+YESV1h(|eiROnA_wW@dkLjP)bmesU|{?=COiU)w& zSNIpTuy_EdjfIaR9C-ktG&eoKrJpjj@n#20HI&E)$ZZ} z5YKb)ywKmfY6WLYSZxmP^%8Frgj|n0pJ0k zHvs+sdIjJCpmzZN0eT7G0nlSxj{$lO-~pib0R97d5#Rx!Hv#?xdKKUSpmzcO1$r6a z0TBDQ9tZR~zylD^#ikbmeh7La-~pgl0)7d4C*T3lwRHF?=&gVUfL;suEp+W29sqhV z;K$Hsx>^_IW`AolO@o9NzicmU`{fggq56nFsWRe@iH-W7NN=w*SQh29o;0O)mr-zA*; zjvvP1hoLtH9ssd_hhK)?8F&EbrGcM@-WqrS=(U00Msv^M0iYKLejIvp-~rHFb$9^i z-GP6HULJS=={k!2>{V6#P;2 zO2Gp_?-cw~^ishCKyMZNRa$Eu9ssSq4i5mmSny+MZFYD7=+%N>i{34G0O;j{pNrlu zcmU}2g5N8in@TSj{9yEk!2>|A82n<|I~*PWddc7cptlVEGJ4J60TBCl_|ND?g9m`# zH2Bl#Rf7kB-Zl8w=w*WkfZjIv+vs(J2Oyp!PcIxi0QAPeA4jhoJOJ7|9sW6b>EHp- z-spgpcM$$TdI{kH5c_xd3+Xk42SBlh!+%IGB0K=}Cc>XcuOd7E^e(~! zKrbWwjPy3b13<4M{Emu!93B9AA>oIlHxeEIdL`kPRP5yN04SDn_$leFWd6#IuAWPZ zy&N6@dNJY0q&E{D0D3jy*Q9q79stF14nHToo$vtA>j}SSJV%#aQ20UV4TT4QUQzf( z=^cd!K0D5ELk5#Pf@Bq*|3;(QQX@>_u?BC(9rPmf70I`3E|CU}{cmU|l zg+G^GUFHE$?=Jki^zy<3KyNSnz4ZFR0}#&>rWY6<0ObY_e=xnm@Bq*|4F52_#P9&n zTMU0Oy~gkWi2XbK$Mhn@13+&w{K@nx!vjF?GW^TRWgH#=Dz1r{qD0g%C zx9R1E2Y}vg_`B)#h6f;?t4uFAJOK2D!yitsI6MIKj>A7rFF8B_V*d_*Ilboa04Vo# z_|NG@hX;V(bokThRfh*axvRs!PA@w=0Q9!Q-%hVPJOIjl9sYNE;o$*LZtU>K(<=|Z zJiYVq0MJVh4}fxO>#;|#J^c2{y&WC^dhy}MS8nd`0MM%szdpVD@Bq-u4?jP>{qO+L z>kq$wJYSk#fYbxf8xRiwy#lEhkapnk0MJVi4}i1N)7`hzEdPkJNk6`wxoHkOlf4We<#h1`Wc4@Kw6sh)TFm29sqi6 zQg0*e&EWx{7bo>N^yb6^K(9{fb?DuR2Y_Cl)bmK&b9eyg^+~-?Ja3#{pwt8H*>ygs z^$Mk4NZO&p13)iP>WSzriU)vRqtqMGd(`TW)QgmQBzlwL0iahY^-A=*?b+c0pcgG30BO?>4*ig*Riw8jL-% z;HWR8*DxLcv42PXA-#z40MMJ5`b2sa;{l*|G4+e|GR6ZyZ)55k>2-_;KN&-B93B9%e@DHi*pI^lAolO52c1fL_yh z0K}fG2esJ0qaKys)OY~sRZYFB*p zsiR(+-syM%#8Mp|0I^j^eYIGt!vi4p@2J0~7dsvRv42N>wpgvh10eSAsNbfSJ01Xf zyHnpS*2@_H*85!y*m}X^0TBCl)Q5`|J3Ihl|Bm``v44jL;1%_j#{(et@2EEydv&dU){CEJw{vGxDV)xd=U+mve&o8!b zJ^tzSj|bp`4?bw6{{OnGHnlGO^$C^N51Z0@{x81J=e;v;Up}w4a|bu^nq?!`ZL53p z-2;{``OmHcCR8lD?7Th$KfUA1l`Vf6I^Z)S??39|Q-1vJkd1%&!NMKuA0GCTr(bDq ze)z1BJN5nP+-Z9~d(=1D=U(uqH}*JTz~`Qu@sF3>$@k{pnsU=Khn;@)(ihJE`8WP~ z=2tHL{CNJ)*L;tkF@~}H4!_G|@K`)1kIi%NTs$Yw&1>Mb@S1pSyhdItubJ1*d*HqB zo_KG(N8T&%nfJ~$xO~5L|KZnP0k@Yw(x14*wF@;K-qS zUe7f+c&C%DC2!0X`}@cOt0 zyk4#Wub*qc`{5e!{M-0 zSNGRn#d=+>{HKR$Y@twbt^O+Rp4WHwYqIZD{ev+(GiLaBzEi4b*5edPRbQ>pU)2@w zYjB~uYMzFbN)@x`E#hYn@k@*J#D&8@!y`VSe;0-|^5vO)_o&nCp{j1-uYC0gzE@qk zk4G$(erAtYD(ZJCj^|fe^DFgN#ZG*^GXE96{-Rz(@r(I~^>yX-`p^6Nf7RXk&j-a^ z^;|tpX>@U{4dMKJrKve9>;x7vs1c^;BI~C7-LQ^RQnYR=(Scz5p$%Ep}# z$F0y8_KsV1v9HiSO3nM+ST=Be9Qds`@Pk6G<{2LGxKFJw8`vHP{yZC4k*gV{IZ}FY z-#?ZOd^8SxHyc=!t7+oB{B8e!8Xw>D>v7<|`exUsqKjCgD^V&99$q$ZM}2Mcdi*}%bZ;H+$*F7^c8%bHP3$_Abt2i}kk)W!b0{!!{U{u^ZjSLo}S zdwEG`owL5|`>Yx@C-VwspYwd#_gN-tF69ZYJ?D+G@3Sn_9LeK6cTPzke!K=O12qpb ze$4ni%D&I6uQ{0y>&yv5%f8PfuX&Bf8F${vW#4B`*HrNR36rOlecz@qi|?iSrriWP z=4y81b#EDSZP~cl`q~!hJL5Rb%=tXtn`0g<8+St-_f#A=JXbS>$NSfq-6>;BJfxXf&jtC!*g<6jd+BR?fycywUIV|NUoQO(92d+eIBfh*&{G!FDyFDrR7 zr=0n-vVr%-fq&8$cCmH$?Zvo9&-zcHMeq8y?oZyW#eYVad+qo`w(8z zwcV3}Z=dx**}yNxft}ev?M0J#v3ZlSV2pVqW2gV^A{|t zC-h!8`?Bf0tq(mUzhJNL;~!HGQvM?uwz5DVphYlIq(9`AU_L>hn^dqnF@I&-HeJQj=!qxKo^tNk`HL4!oqp~K#~hQhmo#nuVoj^u;&}^a&zv`X zTK&{nlNa>#X@#4&`!%(j`6I6=+~V6GaQg+%o~Zkkw@Ij*w1*2Ho}26cpYgX2OxXz0X-K~ok?o;P(?{etNi&t5ot z{=E7_4>|0Rp~KIsA2fGr^Ww&-T0N$>44OMs|6Vj}@!To;dxpM0qxs^YgBCUqns&%A zzQg<&q!qkTpYXK$K{KaaGI_y_L5J24I_sl^(L8AC{CSHOOrE-^asG@MADT_JWR!oVHe3HMAF*A0 zyIDT;F@>A7hs$cyx%{)RHKXe(%hm^dqkK@;Ebq3maC=Rh7(YV$%GSUho;BVJ-Im#| z$=>a`dfq$YE&VZTWA|ys)Ys!?y9T%O$G@(gx1TU6!@k4A<+KVMSwE25@eGRqX3Squ zubZ#_xDW-@k6ti;>hy&R=Py`z!2gH)HFs2lVv)&&5xM+eeOYl#*R6ZX&|GETs#AIu zdROjH+A06Z{4T}1{I2=k^1B!J$nRCyC!ZU<@Y1>3zxDT`1zms7ieKs8Uz8inZJ8T9 zW#Piy;05#f$Ka2@KFq~9s{FRFn<@U_^mq;?H_` z5oJI9$Zvk=mG$tu@xCPjiBIv72l?0+XZv5cxaGgqwfyOh?CBx1wXvrkhK0GOA8Fe3 z^zCfse*6!0W5*wUXuf>(n`I-rzn|3FO+>s<#%7#J1LtAJv`6HZ7Co6Xv-fohDL)G_6?pkeahmQ3O#1b*G6VvPo6SG z(Vkv&_S4CV0cR@z4Fl$odxx*J6Xph!=%S~ClhG!r1LNy^zT3Fx zo5MH4&^T^u_i-2Hatw`s;<$c#f93D@*aaFR|j6A8%~8aV0?9 zs5ol-<6YE!+>08+2O0jv$Gf`wxK}iwPaL)V@$Tt9?oExU`{=mGyN|2P=O%3*mVF+- z?>26l#;xdK+&{aG`-8^ihHM`g-^UKR@${4I{`|Igu3A{iA8+U{dVb#F-NxOd zaXsCqr*kSEVm_n)tbG8mh12;;-+=ai8iw?#Q0U zx$fgeXXztv z^}qN>Kej)QcONHC*3)|bYPWIix9P!p_}t#>KJIpn>tQ|E6(p!v5MNUJ-Fn_0KDUN$ z{BGkm-CHQX{j%$FdAD&}HLj=o?~ZQcn!l@8+QaAD(S2O1aq;5n{lza| z>^|K`;$U$a}S@#vE9aPeNxZc_0ijZbak*#oU@Nvi@&94(Ti~lG&h}@|o|7Ds00}Cf zQaxz6DG3P#h=@u81XPd+il|hsK|n5n1VxI1h(f{+j^Um2hn;=1{E$aNvoM+y7XWp5e-JRWiW@guw`@MKN4)wOt zF2B)qSql?F^LdU>sdH8MCDM7(=7*TuunvVCi*(1pvs@mITVwV|m zo~MR6$CXRBBUbK7mt$%VjIrEWcvo&A?p0hKmURT|_46WJu$!iHUEa*oLd=I@4(phX z{*YL@IWt0oTdb^e=?+IaG;4O(KZA5fWK%_TDnXpr{H7R_ua1nB%WSmk9Uhp}6Phg; zygLr@Yv8%PJYBdie0xu?4$U?y)zMB{&W}%;*WU5dggGrp`+iL*`z2CNn*DqOQoAT3 z#9WMAJx)T;g}6}U>anvu7n=N--fJ+V=k6`96i0LtE>N$)&$Mo0{ zo(plo$t~Zz03lsyI>z)Jz1-Ayis`)@Ey>?GruQB|L|+`!^T>!?Xi8#w9)*z$O_!Ly zOQb|7H2cK#7*6(Fhymo>?cdkaGXH)teQxT|bdBk|#`1TI>AS`B-D7(1#t11xvwuv# ze=Pq2F+Jz4L@qQ3#`Ju;ja+DY#PmHPB|@S3L`?79c!>U>nEs$x{)1zB?}1VBXJYzH zEPv0KzGqB-NKAi7On+!he`ri!8q=4?^u1#GUNL>|n7(&R-zTQ;6VvyN>HEg?{bKrl zG5ujN{b4cv;W7Q;F@67-o-9P{S@f^%f`P4KZJLGHx|W(B7M!j2o2_+~trDqgxGMg8uX+3UGXu zD#7(XAL&HKrLhF}6TMX?cU6Mx^JpjI)};hnGfU;?fh9OTE^so8l;HlQMde13hnWXe z=9yK3d8H{agUsJlw)H7Do%EK8&zL3VaKnk#bmUMpoJ6Y;iY<}rvso!B{o0Fw}eX(*tisQ)x zdqu$EFjN+m1Vt(uNVh;yBh7DTH6)K&bJE)%> zlFJ$H=lGmIcpxJZGPKYtR>r1U#mYELt5}Zxw2I`YORGo@Z?uZUa7n8;RJ4uJ5gmn* z8t+^!Ro}T1+eP zf;u$sN7*`K+|`e?b&f^aI>#cV&apVDb1Y8k9E;Q8alc@lQsPIk&asSgMEPmtQ1T<> z81f@{@c1&18eit&;>)p z#`8{`$U8nF@2rT&E7mK1QgOB-?_Zd1sp4wIixk%>eopZ#igzjAtN2~TA1Xek_;bY< z6yH`XME{?7&={F|jq(Rk-e}BtBIMJFEygTUc@6OaV{TIUtHk?_;rJKR%ksJJ81u5q zZxQb^W?x))s6T}GZDWp7`FJ8KKS$+e;zGr@g8u1 zxbD(^SK>D?w4n0Q#Ji0F9Vq%aL^Rq3Du0%Er!iks`92~BO@F5H3&h)v`KQVSxGpAe z^Vo}s@&*yVhW1kVbmCXhUMgQm#LoJ>%3mjb*_ek_{u%L0MmRLuBj295&6sW}Amm=e zTa6i^@(IK*8Z%GjbBMPXvq9yJ#4libRKAaRr7_=Ec?=(`gy#eP${f_RBB!&K&auf)a1OjLO~@gieZsC+5$W@Bzq`EKIpjd@(;u$hW0-}yc*;EDi0=JWy}PXKS|tR%sDDwL|kvoMwRa*;^cfxWsMu&;8}xN4EAE6TVg)PTG-PFltA7<@dMtu1g}#s2xQM zUU|yAoGuPtel+N@Jxt_pso#-2G8i^t>!Bli?noT@=2PE&X?xH(#yoT&&tEAv89W3G zj>KO9VyY!F`op?m454woF1yGOk2xmMtCs(X6fGnY`8X_0C>`+7)2T?N#y}B%kzG*r zLW#-0gpkI;PRM@%s%YKtosdF|>zZ&dANWHqVGC>6V~2cv3TtOFS2F*1h(|sCK}aX1 zCrl>ih{Ys_15?uxPOb{rXQvi0yf(lgZSs+ACWP>bltJZ!_sB4Bp%K?6&aWVbV! zh%BN2y|jv~fGNV0lqrxbbC`vu3M7k&f5~PMu>=hP=dD&cIj9MBa6^MQGSmb_r7=4{e17OKH0hief>uz=>jEVQ_LDS3ngpAhpCE z1}4mTg4~-3@2e_-qwyb@dIHr+^LkLcE^xsDKYm^YRu3swDm-LamEufL4$m z|5;~EOe9$CRHx$bg4Na&O5sD(RNTS97)L(z3=zOkl6mRT52m zcrDxqw#1H)w|u6U*1VX{R#+j24Q{o}4(**?W`|oj=Fw$#vJX3U0mNq>ZIQ)27u-98-yE00x@I zQBBR}L%ohi*WB2}fOrgTj@phpE82BAD|OrwC%23yyP$E}w27l9nVAa~&pK-o7CG8Q zRMEo6_p*MC%fF;zQkQI{wBr7Hw#G?IXYEa^U1T~G-v9GXU=k}k6?K$;%ym=jpK3ep zyEb)E^5XE4#HBb_&2Fua;er{ij`2=;f1>fbPeaBI^b==iB}WsL-8|(errmRuz3I+# zuui$bZSpShK%`(hxSNT1pKh-e|Gv4)e!0`V+PbULXsw@9U5&uOu2P<^24Os|WZk93 z#_Yg`@p{HPZra0Rk=(V&en*(@o3M4O4a&dM;i#8(aVowGh0_6@bLplb!Y_Aq7x3yx z$8uSoD|acvE)Rm{QdBC#fI6pJ1lhOu{JwVX3+?gd$Jx6GVV4I%^A*?|%YZtky8yCp zZ#(QwM;z@H!8?0+Y|XK^9rmUo|=za|E!j$JCowH4u^`rX{yx%TUupPyS z<96WwI=dYu2&3GryB_wQ%}P;OEYsUOQ-QI$3Pg58JPrx5NBb<(w>KS;e8h3iue*yQ z`tf^W4ioDXIoB#ShI5#F$2m#9v$N5n7|tp39p?!7j&pu|7ow%n+|u4Qo-H0Z&cX2= z=k)lFb9neb$2MV~-i583+b!cxthCu+j3_r+xeT0`tYM;~a;rerhw}bJJZ1JGB2j;h zAEa2VI9hR>BAw|DpHS?n$orTC zx=D9DL6r3Fcte*XvODhBf6<;ij{`F*yW_8~%Ka6k-$A0pkz14Z$Zh9b{+2#xeho?T>B4l{2^m z|H0jeAnO@-k|=Rt72?AnZ#={>NDrfwNWF&iAb@8;VxM3V!p(-sR5kb7S=h6T z#xk*Rv(Hf*akD&zJZ`qeijJFQPYUS~7e9s33!%WZ$-AL&-sHXmYLD`%td`uGIsTL_jxaYY>#7j~e@dXb zHGj%;9(*W)rzZ$W0@KD=(h(9hk>D&%%o34^l->hH(b7P8AxasrW+xG3Z<>0-36cav zDFe2+dW5nLZHGI#rDk9+zJg4RPoeR{-~)3KL5@$n&9jBZN5C@&cvA*P!Gkx&zc}V( za#E$vd2#IO#CdTnHy+0>Fdmn^CHC^>vn;#iQ#FTdgI1w1QlHX>x^txFwOL#b{Np@? z%hpxeO``OV?daS%9Jf1pCs-RS+J}O~9J(hs%uaK{rT2%OGU3wW!k$x3I4LYB7uHf< z4O0z5EP7jvP?ADZ;%|__Ulrf>!$fb^GbqSVF7OTtSNm!Tipo%i^(;wgvv%;Vlj zQ(~4XFGc?yJf(k$a2FDLsdN_(W3EK-XL8$P<6LkAMBa)zcO~xKzXBzBC*0o4g^3r< zdU%%yK{E~4t*aSO=X5h6yD(L+Bi%MH!Uf4o_~llWAOdMwF3aO~5c!KA?D2-d*}E2Dmj^*p0(~Z^8zfSPZ-Yp0-PX#>P3_Qr4fp&3@I(j~T`{^EnF}9U+F5SI|z|Bmf zi?2W>j&K5y>F6GZcVWs4kj~YCGV4e82)w@?Q@wUUFuNVxo!Ofxgl|HoXMoPRvWVX1 znJP3!1tNFFQ_jY5+RGUOI(uG}1pW9u!BcX(BIjDg#(WSw<-RB?I$qi0k!uf6$#!L% zu+M14Q}X)Rnx-7e5`<5{F~(z`JQmx5xHF!TxAN38Gx2D}(Td{~PgG=oz;qw;l(ro< zVkeO!Xp^TzJAF^}GS?LHlPaSbb9f%vU)sl!-^r-HRB?BC#Zxrj>5B6e7b!YEk*opB z;}bvevx@95Dc`90MMdG65r3!3_b7fx@wB74bPm$0xp|@+*q3E551twqkK7_HzVHH-NlZ|GjiTcVzo0Ui z3hITA26F8a<;{x1LqX=Xobkd(108=T=jprfe*HBc`w^d~8!)6Ig@$1ho{@V>DqMJmfya5@QR|kux@bO&t5h2@7wl=6~R$`w)I&-UT*EH zX2qmeLy1kkR-9yf^3@P=35m0E0&?KV!HVae8WL2Fsu)E!uW(Dtt9dK7zY?t2vF(p5 zf?;QFyJW=+kluJ|`-7NqiAzll+XDeyx$G>&`w?+5eB5EqrEsr7T817HsZwOaM9V)T zZ7A&i(0b&-M9bxj`4_|0GbJX!3u2;)mZgxQiIy)TNmveBVa;d;7c+OQoMy@V;Vc7e zo8(WvKuBWlD6J(ql8_pLKd^QeA!mx4lKf0?H^O6 zXVTC(*tzG)4(664T+I49HxmKSTLh|i%A~mjG5TzdWS>ZI*>_5x9fCxl&yp<+^tM8C z3j@Lpo2KP03>;@QD_f!>>k*Z8yx~v^jX`b=CjSu*kl@J#YXnmdX@s>?3XQ=9@SxBL zXTyhP>8ch6xB(uu))q6xB);=y-ts2QA^eZOt-g(i_74LyC2Y|9BB!3j1iMa|fpw*I zrDwKW7@oT(Jm9zyGcl*GLne`IHK*=FJw+{N=9w^L-fXpq!)ZOeFJgOgOjxQ;{&Oe1 z$z(zK^C&o*y7eS9nQZo6=CieN$oo8%J9Kn@o6cQqW2T}%^DUw%Wt-jHxaw~_EgqAh!F3aopZsFi10aumEZuXq3nuy+}dV2g-HmzJP4W~(KZLw5KDIr(jDz( zbio-&=a;()oWgV{S#BDh+d*uGcX<$$^>7&m)Hz)vWZ&Mtcu3}@nf40coxMvCc6ksq z{IDO>Ip=g2BEq*<>e=ISowIiX!Y&VOgixI1MY!NK(E0YrxpDhgKQwvP-fajoPX#<3 zzoRu8ZRi|z^mi+|bT{F-V~I>^a$? zAHOF!C_cMIE-Cd~n~iX-WFtNZPKxcs_OXsF7P-h;+DDR-@GMN8Q}-11V` zF+3j<*dI6)1cjG^ygy|qdl9i;c|0-QAjM&dHHvkLlN8C5F+KYf;sV7c#S0WKR$Q-m zvm(zW=DS_-n~L`O&k{7Q?x}im zsZ2Lm(;cHS%!qv+Ei4C3B*^_pIipyr$m5*x0~Bi%M=Op~tXJe?Bh$}PoUgb@akb)F z#VZsYPjtP?H!0qx_*F&658bP>v?I# zUtoN`nd67#kq7$2HT?j^JlaKnGve z^DsBzIDpIHVX&r^^QAhht-G{t|1Ab9RtxJU)b0Bxyce*jW6_YLNtPu$B!gove5uC# zdio91xu(_5nkstvv7+?L9lG0DQ^Vg%$ePx02liWcBKm2S_5?>44R{c{a*V%wq5+Cz@l>nmaL`B8?O_ud5c!t&ExLfm{j6$wR_A zZlCXb`E(rRiI2!qP%fLqQqVz_?~AGOmV%ala&T#ngL)qnF3p4oXDSa4r%ee5=PU({ zzPA-o7H!R{@|Se(lrZt@|9;nfe!S8%`?16vvJA|TEY1~1EZgAOPvB*#q=;+#cxF|* zKX+DyUdZRP*jYKpPH7L#tBQ8pUe0R$H_fY>?sgQ=U0OyXEO$w&yBhdSFTw?D5btvo z#Vg}SX-35?+d(ECbo-3|? z*CFik&_o~Do90Eh;8oE1_SV84w~yP~3EtUbn=%h?mgxAd|5>s2qyA2KKi!{TYzZ@{ zqmKUD@S(?PorX#rp=k(AL&xWO7p8nQ(z!ZNX8q`X1n+Ohm0r6bnB5NSPWx~Kr28Q< zJ!^yV@5&;2n`fq?F~|jwtLXyIa=Cw4CblE%IRCFtR?4lr7oD?BdxFzqog(L2#m0OP z92WVa=y+v|N3J~_R(B+4o3l@kIIL{9oI9~98@>DUs^r!jJk}tTLq3ZSAjHv%;}qGi zFrM`xvi~49DxRZwzT%aN>lJTOlZBl$d@%xI8DQ;2xx#A0oe^(69IOI1{ihFwf z=Mvh*!OSI1tnX@-FH-rlDqpSg%__?av5@`_l~LUso`!uA>&;_>m{BZMjPqhcG=7+( z><{FtSNRl0H-BoT%5xMKD>f@Ub)SNR^rdles5d_wVO ziq9xMulSxyqGzO9&Gd!ZcJkHC&9cU5%rsCuc~Pmz5P^HnJxrC6g#`ht3nUl8SC z4amNqGWiT*lj8Y`LINS41PAqQewFNB$XpA@crqTu?<+p3_>|)FiZ3e0*J0wa@viGC z%QPPu7=M11e{-F)4zi-{`Bj4lwV&4;QHa8DYE=p3zN_vNV0)`ecgbK=R#C=hQ5;vQFcw_Vu)ClI2kGID#%{r5ybMyeW*y}pGU<${2R)%0?Q*$ zgF*&<6V=NlCjTr#Iz?g-%OgqTMav@};4T=<1a^5Or^bbYYY~wc&e$3`_fBMCwF?=M z%zu?hf;6XbVWlMd4y=?sj=FS`cL}L`5rvhKpF>n?6#l^eeTiY7)?oj>0mw^kmH)rt zKR@^c{(~{dWz0F8n*iH~@C?=^r?m-0S!&~-m91~vwv0yg- zg7MToN3F1b6L}W$h_n2kh+HF9a5xiBqILm%VMSJCcV^#LCtTw!+GCP}bxb1SDvH-- z#TJOBBN?EB;0q<&Y-Y1rBq%hZWD)T<%mQ<5@`(S@^_AoiJK49{VaUV1ysl#*s>%Tr zaY_6;UXi;FVV=xcSBnsMMFQ2W$wc1DfJh_MN$?Z`)5hkH@c;ukM{t%RY7mifqlThr ziPw3Mj09Q(ExBA?B{xyx>j_gNzVZAP25fOWJhP6s#oqEuS`Ew;0y_>Yza$KY#|!rY zG0vLl+%X1EfcNHzF(>PT<(JD{y)YRKG2%S+N~&oYNt>P=h%$Saf4Wc-taW#J3rkN97!LQRhoJy`~FsGK5pMM z*P;1%EX*7fHkOB-0JF=(gNKJR%EN&>U9l;&Rm3vpTw}R(vyy)U-TKY!3@KK653T0> z_+4_lqHcL;?9Pf$-KTuV+{eu0Cru6eyBQ5LX3jGKd&^Y2nMXUOzccQU9o8Ot_nhkk zK3>zQR|Iz_K^}z{UB|ER`szEEu0J9f&Qm4R@pjKScR3n`2$zSt>*3pa_uL4?lh<*M zuUOcDjJ&+!(MK+CtQYSNe0$%<)$f~#bI$2_thg|B^RYqy@*-UD4CwrFdE=6SO_s~@ zxE;hL@GcL6=1f#7!+<)c^gk2s4%_XqcmjQK7w;Hly zAddEUW9;l*i?GXspt%e7rg{-BxB)uf-rcar?V~-=ZCQJ_Aj~{0i;myPT#a^djyn1~ z6kWP2V4Q8`oJ)5vBCrb@UHm_ht}X8IaU@_K=c>_Y&Nkz?y>ySj``dA!*Uo$nbL~=s zusfC!ly}*YH*n6CMf5fgFZpU8_gGQ<@tRIMB^O^9ixX0L< z&TMCmwCry)WA5C>$|Kt5K&$XE51Vq= za~n6|{DRBjK)J?r2-cYP(lw^ve9JWEZ!2DL-?krR*O{heo#~*r@>V*Hzt(inTghy^ zTW>n(twby?Sn7qX(>salrpj%*plj%KvC}N9S$2zn0%m-S+b8ik0m@?vgyN)&W(OSnE&3%k7Vs(@3 z?5xLs&yv>wB^k;D==$D?6J#u#VL`clUbQ z?Z0XrtA88D?{5dkdtEz|^>OWj&11P)_blxFGAl*pvV0sOS=S7%VFV((A;#IG zeU|Cl+k{3tJew=B=S4}-Z6Ad_G3RgJoC54RR&qbqxmL2$2Qdeb?Zo!6jx83s_V92A zAUWG;BYd2Pa~D2u9jo7m+h=a<7@iMY&&hpG6fO?9KV>L;5wTx+JW)SLv08Do;yA@g zic=ID6c;EqDPEw+`*qq~uXwZKZHl)mepB&&MLy6n-;WhvRFr4c)ZV*}^;B*L>iKd8J_@pZ*F z72j6e8JER}Xl~yjie-wzfg+yQFY1RYj#T8-CdNBXi~Tg^X^OKH=PNE!6mAshNC7Z? z9_xqxjOQI?IwH@0A_)s3`-%h-b=P>gQ^bpe?c%2By8=7ok_J}}8q!`aDP4#{VqB72 zC%dlh;4Ou9d3EFKChtfdKVfTCfB0JXGmEyb8kg9A#xJ6|;Z9th&oEtFA*y_wAUowq^CG;-dT1EwX$9oGvAJ-I-T0gxOD#Y zfM_D!nUE4aksxU&(ve?G*3=^+!B5pDYiBZZGXL9%N8!&B(n%f>m_6553@6KwFf|iV zDgDksIpR}otd~6w2@^#LnN}AbiVW$+jg^e~5;7n>(1kJOlov2vT00j(x}bnp_GoEs z!6HV=(%Kq?3dnuhrL|v$SZF^N`wD_ThcBwdpIus8j&xXB3j*qS#9auf;|>IPYa!kH zjQbGPsVn|&VW0qiOk`6r#X<1F%wJN;RQJMnW-3!mJJcS+6thJ8cvg$3Hi@kFFh_28LO|a%97;P$XXz;GRaZVj;}NK|po_i;B@@ww#Fs9`l$hM{sqDm^0oI+q5!M z&(>)&!IpgXN-5bEHkmL59-By*4v&w^u4-YxR)VF7iwvJi`#ib9j1jD1Fk`gF^eOOT z_(%eSC&8nxgqiSpWci>%P#o(u5FYdW2yCr{IeR5Q9Mv?MFxA;COk?9lWaHSvHg0S- zu7~8qpX_6z-6R{b|J+39R^aGQ*wME3yfhBfg8d!4Xx4&dv+?E0VN)BIEeavhuzIdiD&L4G;TFIib4rF!#w; z;i~vugPcpL_bCKWR(trf2OsKp*ePY^y|}LRw6~qIW8UErEwjy`#@y`1EF%`BgX%x} zp#yvocEUs~T^u=bSf(%c@kw&_%~`xOQ!{aVX0)Dxnfj%RXEii6EneExFN3qOyh_f; zilGAsXZqqBqYX2f8v12UN0tHZq%EtOR$Vp|-yxkfH?y?i?0HS|7B9*StQ=HXHS~Q< zjVr?Wv$J_|?4S0~nq0R}_j-cvK(q<(U~pX*$19NUq$@&1Pk5$t+(JAZb##5;)9|}W z*B@!(<@(nT-bv7nf_Jtl-vs}6FTw>!AfC65&Si?*_pO6#v4JnTOh9LErWdAq1vZFd z>(0608Hn)9eH0J(#jwe1E!%(FSV#IMfuu0kN!0yZ*%LtkZ*n5Tnb*?O;w|VAKG)4s?`H0p9p5@X$%XH@k zf@TNi&-G$JowMg;hkpE?;ODqqk#ntLV?GEz4$bWyuWa$iwTF*myRuE#XGDCQ>y~qu ziKH@Up3yNBSJq)*ew9CGV$a9F8Q7ly?$IbWw ziZzO(6=gp`U$62hif$g;Y?XOD(asXZWs0)j5Why{D-?G&ukEX>C-UE?@nCyH|3;u_-iKQ>$R z?)W%b)3IM^wKmsw0F{HiZ;O`gztt>Gl5e(J!t1=eeQfHWPNTjwmvtHId-}}H)UzXKcH5rXnk(VuFsu;tSPrX_g_eYD#?7c zbdvo_v_7|q33+JbdFylYy!E+xZLH5-#~Ooed=Q%vaxB-ejf`+?Bf}oP_ahVqT*Hc9RkD5fom5vV!9}AvS~f!kh6I9KSEb8j7617mTB=i{Xoe zm^^`r?}6BnT~07TDuSpY5|gsZm!}w{N?ql<%!&h5Nh}R%FGk5IY@! zzwU_Y!RXmFs6^*#M6sbe^LoJV3!6@C8K%fcswGTC_P7FpVi#XB3o(~5xlPZsrSQR- zUvTMfVtN-Z=^v2vT?QiE5cp>yc6<|df~DM6sqi`ktoRdX_qi@Bnqp=l0cEo+VHR#w zN68}M3p6NMMEt81_d!#vN|p-WTCfwowJ?`&CBf=mbcpV(V=mv?$){6!unEmdzO~pb zVJ@js2DXchVXA#1D`+V?=@D}|Sayn8Hx{9H`eGLtLo~NFz2jf#g2wYcsW2^2LFBG!QT=%2+{%b;7eA& zec|#0S}3v^y`|7RgKUP$1fD1z@Wl?zK#`U7mRmbQ)|>noMV*Ya;#{No^e*G%gf){1 zTJ@DSL)1%jMDf-8?tAc|nbK~(dbYUJA9c>CfmjM>tP|QK&&%lyGh1(XZ>t&gE>)pQ z8wDY8(Kb$YQEjwl8|}sV+g>5*GRmQs6%d%~30I+mNtjyxe?-V?+zai5tXBGZ(!7PU z-xquR1ZIvFmvg~)aVA_cJnWq51NQoBV6Ve)JSptYoOfK$uqgw@fI($pVR<;?I4%co zi^YznUV40XhA+=)ESt4>QS;Invzm`uJZFw+&3f;GAx;5pDaSMCTzfO5&Y=evLl$MulhCLXD?+@`%T%O*2-z*fo`L9`3SgR|K82cdeHPLGvfryUrQ$bQ=)%?R^FIxP7c2=-;fpTM%aU z3V6EJ$i#66=cuD6SLCPbib}DqoO9{!MFg6)(ZyeabnW57HzS>^1M_lw=^laix8rWF zUHH`N+NA_xZ?~K6u=fn&oMZjyh~DOzOOdfXT=;!BPJ4+3`{(R=Q4;jyKjy-_$QT3L zgtxSDE?h3j-o(^wXN|OYw%j9J_(<9T7gnz*+$!X$D$i3~r1&YtHHw!h@|m7?Zc_ZR z;ysG81{nIsRennGS;gNf{y|YVQ>1@WW#LF63l|EM1&=`CFo8?ah%EnHB09?R6fYp+ z1Q9M1`t>SbON6{p<=a%|Tso%zp5hNQ{z;YpSCPC1)4iqmHWBvHIC&V)cK}oFrgDae zddW;b;2@2cFNq>Ozh6PUOt%A`s`@iDex~AC8h^IRD-=oeu-wn6yg~7E8h?w*UsAk_ zi28j;_1{zZQI(%m`8gu$^J~T5Y5Xfhl=qs-|4^Bo4DA*Wp{HYh_CrK;JA%cE8O2gX zvSUow-m!pFHGO;M0bi`?FIQZzc#WbQzbJpB%5wZdX1~pP$#D$)AC(_fd_r+oV*#&f zy4Muh;Y#}`#@DoW)p+uPOn0baA4N9?Fhu2}6l)Y6=YOioGZY&X$xza+J8xF2yjD>j zuc7BPl<7!e62GSS4aILM{!o#xeq=gQhD14UfO6gd$=))a#3nJ|@dG5kN!(AdhoU=w zNO4kMrO5YkQ$Ai%zEuNxvdZ%m7b?nm0{y2|CI!m;8x_B-_;p1RqSQa6NY0b;PZddM zQvN?hGMbckC`v!A_cV;BBf9fpf^I*FDu3)_KxJih#&hm_LpvM$s2Y64K%0EmYw~Zk z=Vi{=M|@5GRc)-vPs*D7eclSQ>+JnC`TMk5f1g;f&s#w@tzD-dt;xSw*5r4RHTf5I z$DHfKu`2&CuFAi@)_o6JSLI`3WewX&T2I&H9{}kBM8;j>XH4nFO#Tc30~GayL@FP7 zFi`RR^tol=uOZ4_bkGX*k`+fU5HK2(0$Ke zlSXFF!&as>yU1TZ8=alTy^HThOFh&^wE8|foA}*XTX$scy>om)S7hBrg!aH1e0fZ^ zJ9#hv=nmTBziEyy_m6YDDACoy%e{q2J70re3%x!LO3E!D**LMGDbT- z$GySTlEeNv-RxMpJCJUTQ+m4T2>a!xagT7fmP@{m+d*uC_p+M-P-GD2oYO5vgm3RY z@MFB~;CA@D=Eaa*9t6z<*kd~9oNf&we0wqn8F947XJuDEUbtNz1kE%kCV3Gq$hPwB z@f`u&KHBqn&08TePX#>PJ=h5&(1y-YM}L>1OZOK%%Pet;RL6Ap!Q+v?(Wz#k(6)F@ zJ|{E1b2lMfeySl``hun*Us<8Yd#8loQLO}D~srDo|z4fVgw?)A>P^J{$ZKe zj;y;Cjn*$K<<{Mc&e^6t!E3TkkxR<{BR654Yb7gv5OaQc{IGqj%dK5|=KSuDjNAts z;bT0fyNJb^PTPeeJs%UuCGmXVT6P=?f*hitOxp=4dl9i;`3S)Hp^7qd0`h2;$0<%y zoTAvExInQ<@d8Dj)3m!@@n*%_6mM7jrsDmIGG7$=eys9~itX}66+?y$$z%o(uCNiA zU2{cii%C5XnZZO-wy!y#MbsF9B>iiqc zhD+=Iw#{7rJ^12vCF`Gi)vP#k+hr>{yjI-djcuD(ytb|Q?@vE;_qMSs?%pI1S_80 zQM!?Jd3QSn>wnVi*E{-dF1+^Qm>qKizR6t_9AVb4`s>2GI^Ou}9V6ELddH}Z`vf

6JsdE^1f2ez1aP)CIl7+v0YX7^x z`%3bP@4mGCvvN932ys!g*TrOT4)$@7f%FOvG#*^O!@Dl0GHs9+YCe(r9goID{$wNy z*#n0|>+z3wU6PUw$uEc1GbJW}6xDnaML52hG3k`N8a18IQJUzrmz=~K-pHt$(abRq zf63ZY7-W~99M6bEGXEANK|O@%OD9RXC6dWQsl!_iPP-IMDsDyKK`PGvURF`e95g}~e2QedmxKKU*8l{ow`Ub4%)tiSL`92DjZmA+ z;QM%6=kC7b;94?=yZ4fVh*v}lwK)S9T`A)y1}EpaHzAbx32nRC{#9q)qWi`9a9$~q z_wxu>5xM6>bKdoU$W=OF+R^b21Iy3m=-ZSG6#}%6L;;+aeHISLfsag`9>j^5UuY(|sGdMEhUz z*^08;JD5fx7Uka7y(LFxbLPHCpcT)EXA=Ll1L)Y$0b!T?%mh=yeagdynQ))X^v@4? z91}HvpIFngtS6>v-gMrYipqm35cQkHUu@JD5H;XV#5|Xna}<(%>Aah%e+rgQ@a*z%SOzQdf`GO6w}~?Y zhg5+b6B=yLK!oh={QLb_c$Q}S@P9R2nob(A^<>VR$(TEtqq$_rAT&F6gfxGaQH)ZP z{fx-gSqtVhPLn+H?j|#9?u?~&r`h~-7cXtjFw4kcQ%8=UbnGPiKW$P&^RmWildH;? zFW2}{lj^69n>Tanq{YjY&T5#7_Yatz(U|@*gIUd4QZ|Pbope1Dz@~g=Q5Z>9l0%4a2K{Ffn*nZAA-6e?d?Nz}Z_Yv)Z{>j?=Ji;yyg62xtd%%lu z!5g6S?ahWg?kC#o4DagqRfL(xox@|0i1SLEqmF))qD!|4H;_wQBGoY+9|nBRv=J3%qvT7dp2ce3;7NIAQNMh;z=BMf5h$EWl3V za}Xa5aY%?gL`j*xy$4Z1HR7Ff_MGg{kKYrVDYr3l_PwQ?hh&{=B`bw;200zugL^!3 zVNOd@k4ExbC`Vcp5z3L`%O!IBuzjq{tz9T9=bVoAadLZ(oazCdOgnwxxjF26vK(sc z3TjEzY18D>bkpVxT(F|m{iZx@6krE#ge~Il6c2-4$~P;rkJ%mGmHi+2(Lst_14g+< zu}*Q4;uJ;pH%vEQ@f^kT6|YoWuSg!8>A$SV^NsQYir-g!OmU0i&lO)#d{r@p?PY$M zTL)x2_R(ZP0ixrzS{(P0!6Vdlxqv+<+-KnzB5zzmL zGM@2%rSZ=zzM=S*A~qw3Cqx#JdCagJp07lCP6L*z%)XWJ>~o0ZC5WRG$10wvc(US| zif1X3{9r!P7R2)uFHl^kc(o##52kBT{EFi3itHDu{~yIi6`xT2nc_2we^A`2_@?4N z6#3jqdqs--D}F+;RI#sOrQ%>kISGj@JaU08Qi-M!n)inrmfdezMDy{-5B;z8fqwt2o~ zXSZ)V^R(^T#+){I+r{(KRo~tA$o#I`iXSg}y>nhEzE!@@tD)p*JAH2IJfu#vJ9QGN zgLg?C9F=Q5v7iO-T*xmDUj9+QZ~PpD?JGVFTQ(nCHh;UYrMKlUv~$2Z*R41QtaC8z zUzly!ZQHuzlCO6T`G$r+*slQL)IJs$K6~v;1}o5z!T-Zf{2P4SfqLwVILs&Hvk_R* zvCL^-`I_WTNc5`beJX+~6m(dV|^ht~y|2D!I`1CSHp0ES|H56}0>R`eh2;K~DXCw+w z%F&yGTKokQspafSd>$P{=qr#ehg8Vx1+Nh;5DLCTI}4cdS18ZEHde$xLo|hR@z)Ih z<80a`ViorxHm!)md0SF=E>Se>0o*Y^FUsn^wfjB<&+m{1l$=)Ub8<6x047n^weM zFl|v6*gGg|^9H6X#$ARjU&KT0O~)?TRV7-{ktF>W%cfM2Hx=Y{Hid)vP9*}85nW`ArP!n}@T-LDV==SiTtHOM**6TFCMP@@D_di26qM9Q@e)nn<0z{{Iw892@g z%`FTpx5Dxk2EJs4l~Uy2ARs$|dlu6&SGF)yik0(=u72zWsp55Ejq7Ln$

P;w8^`y1V_d&OS|}Z@S|Ycp zlWA)FTe9C9I3DeA0@A>MxH|l^!|-@(*RVydVc)EH(@5hUhlE{n8&q^+Ne$hSYs|HA zt}(VV+ZM+Bw#_j{LqE+m=9)X#7@M5U3}b#X=NO}*=i$B0+zgRzookFSY;hR#TRg`Y zk9^)7;a$u~DbDQ#7_&P;GH^$*@w??gya2l07!BAv$p2Pj z7O|%@_il$){6AVQ%m3rzce@rhut&b z+%;j@l#v6*;{C(RZx1_U!gJPy)tN-H)#t#X*EU29zWqklp5gJQO{-V2$Z9fN5fU7t%t#o>az5n^j z5rKoI`Iw{E_H`Eqa$dMC#+{gTyk`5(rR$GKhVxX(bpF-EU3120I!z|L_IP_)k|<|y zBqX0py$Ltoe6s6`cu)yhE|nKXmj^+455rd&Q0H_FkX@LnlTo2hx=MMv83_C3zPO(; z+p+O1m+inTM0+cPfVz7SnQ;QpmBnX5-`>;vTONb<3gDf+OT0V?nxDd+f8X!yT?n0T z??umE5p>Sp4G6nD2%6u)UZWS`g4aOj+xsi*ar;<5K0P~ow;{|t74UQuQF*@J&^hYp z?^bl_9z>;gQQRE{F zW%e<|(-fyEE>Pt0P5t?b7b#w;c$MPyieFT`Q}Mm>=6Prvmdiz`8n&eLiHn6o~S6471GU6Ifq9_Im;Ojynu*wS7^F*Dsu`U%il;ux?2_RQ2n=6 z&q-3u&*@A|{{#`~w|5K4S;k4J82z&dg%-5q*cJF@ZOBwmf zR6kVpDb_2VqIkOEY{j{X za$La<89v&T;|sV(@o~kUC_bb3zltv^zNGk?;v0%@ zD<-u4J1Dy2QK$iwcYwx|a%A~siZY%9dAQ1Q972|H9Uv#jF})m@z|&QprZ``5k>WDN za}`NyGXG~3uT_-e6Y*bB`F2H4$z=Nb6ywL^vl{QlgSM)?P4RDve^>0p;|cb zWjP*!{Z)4FRH#;2jzj1C_!6foPFGx{xKz=-i{yNjHz@LbNz8w>>L9w4=nIhR=>PIL}RGh3x0+@P!AA(2*nD}YM7R4_r zk_4vyM~Y;DDgRRO6-C~!F`i^FabHEU!Ib+b9-(-YBJW+_%QyE1R1O`wTjNMWD+jiB z9O)+XM{upiks2}1a{O+NBPHE9()=O!WMx4e-$frB~j zFs7729L9`ziNVo?@PW1b5Ax(>4AQ+Jg}mWR^s3;0B7Zy~nK}mc!n4@}RPz}D<3>jk z(y9MpTsr?MKs4q4V%q23P}pxM|G!3gFfS0{5E`nT$IQum>5_u9ToKbrxge*Ld>%^i zB8)d%T!(b21Mr9OrCS*O4ddGyQ{q)LI39m?K%E$**`);I*r8|O(`Pbr{0{urP~_NK zZ~`wQyu{csrFtgj6$LMpfc8XcvtvppzXIvg$R%S+V0r? zXbR`!k7TWkDM{K!rmeybuxUjc!~IcsBmTYuFJnrQb{W&M3$bZMyh+kN0mU!jWlTxZ zu3*~VWYdcH8q*f>TE+Y30!ep0(+xuRU~P(62N7fIbu3S>-a4l-ka>AV&OuC>DXEet$jg;g!QkD&e7m=cc_jKdII>Fpa+8YhPJ zJ=z>C!D!R+76xv&!b&L;#<_I_K26A&5(Bm>JlC?0ySD8yr6-`lm=b}9l8h;FdtQOp zF(n573Xg3e{1d*dSAFnw;gAcl8a^73p>(uriR0ko!%D0!TbLGzJZB;cloqL$$hL?N zE3HNxcMB~Lc_u{`DDfnxmUugSd|2sj#BrxG4UzYekp)UyR7?B~e0*4m`=Tp6EKDHs ztb+v|R-(kA4{F`u-_C}W*taZ&_r_aX!xsC)N+U`~^p>F|Hfq<_LrbEEN*p^OcA}n9 z*Ve6#vd!7fFd83X$}!5`>gimguK8OV?E1Evv@XjZ9VjqW3&efW-rg~#W|jVzVqcd&?P<^Z@G!s zi=mi(I@q8^l2SOpN_)l(;eYC>%!`C8F-QbCca4}8gs(12P6Ce zr|gOcSqGpmS&;#VtcDYC+IZW_M`oyL*F!$szpV$P+WppVH!8I|Z~2ykOUAHr$AO0G zuHsJn00yBxEMrdWqW0vN)6l(t$mzf89Xb9b#9e6WaESmxqm%2)My6Fh}=i-BO+r=V<#sL)M6*9Kk)w0Y z1+PYgZ!ZIT%+LCf?r`>QMVNUi;OQD*@6d(H_!R~FIRJTtYO zV@@0!?bn7qFG_;091444%!%6=Is1+rjxAW{TFFWu#F!J0pXm6_tzCP@oG@f4`+|K) z8)Htqct`KZ@ow6?>IobbnEPPQG`Z?Zi;9&@tou)AYUBt6-FZjI3mD$Ak(#D87o zyA)+C6!BaFzeq! zgbOLR5enpbR)c;PAEHULb6bo^gqug1M zWHIHTie!r^AE!87akipdH*oXA>lV||5up|=*ZsOLWhCmZ@$xV?Z^43Tc%cJ6%^JOP zYG~W$=Xf$Hm*RA?2NI@^Ksv0>xd@P#{2u=EgU66KI0}E!4QY@*6jE?B69n}g z&Ltc}mMsI{;cjLau?|5l$SW9+zo3@l&G3ctk z^lO54`2ulVB0J>1PdxSl@xtgeK)jxc)?>p7he*^!0<|2>$Q@4LspXOUtOb~T0-hTX zJc(dS$2Tuo3T-LL&tNG$NPa?Zcq|-QC9fX0m6?bracwc4OyWCVuEX(?u*CO={k`6E zT+j7>=+4ccJ4-TCd-m)Zo;y4|VE74#VM0BIbAw=~L|jzt*)tX_YuMv&$N6|V{bGDE zu{A3Uk}-E0y(Gy_Uyn_vk6y#=U*-PIEahHAP_lpW-)X~p1LxSG)O1R(OagFAqTCqPKZwH5!-4K{v$nK8f~dpJie@vhHpir-x>x+`4Ni8ct{>^Z1W2Eh=+{sT|5%f_0^Vt#KFqrp6}r1 zz9sIbNNzJxsPE`TqW&5$4?RdXOywHII>kwfQxqE%7brFCs`dd`KL-8Am z_bEQ8_yffsDQ;1GTJg7vzgOI=ZNSEPB#q6kA#DV zB3a1kn_*2ogS9kNJJZ_u1L9GScL-^D8wn<>o+yTsoSK?C9%0M@T?a^!?Es7MIe>ky zNWRPyRThJXGF^~9lK)5ZPyvhab;2>P;6DT3;SH1&jQA3Qm%|sFg}A>~CF&zxrnoTC~vJIw#U@HlxgO#BzWjYuvhertnTOBYRQFWG{ zpREqN3tmD%q~Kp%5B#&OSTX0^A=j2X0>{WlivDm_K2ke^`X3RRPVfJLDow7^#b0*J4 zyDul&P5WxaqO|!kf`~o&_fG5Ddk7PD&puz$-E}`e_DD6Iiq?h~CAb#jeQ_oqzdwKt zXq~hrf_>n5?FntPTt+k~;L`Pn#4s-;biB&=R||Iy8Hsq8hv^#O?T(`q>5f6z-Y!bC z;rsZOBO|YNxNXfo1IIa&zah=-HjDhbvSvVXVJdFHrH#{`opZrBXYx{K`_5LD%XZ*) z5Ls`R2SM`_G*E^CbxyYcvcDbGCH6W_d%PoY_AW%&jpP_bbDoINi}f`0tRoJkis-q}$B*lgB-| z1MXYmeu}%|OoS6a`q7$xoZ^X!XDH560mbhtKBl-u z@#l&!DE?LPA4HsQ?I$<=YYy~E20{bj^`B9OZx-aUs28|mMR{uI6zU_9qG8QnSP|=7{z+U zlN3)^oTfNeae?A8#d8%eSNx3PHHtSV^2wLw-lZrU7Ub`#{IH_zAH>W40Y0tqIh+>a zU(xvOig7L`$#z4!v?3p=DStvyj$`zbuKi#}^saq(&D9JgRkQ0kB)jqc+oy3H!DYD` zez&Y~Q(oP}_n5@$dq!`~YZ#PFjST;~DqNQyy){hbZ{a&}gCj@nNS^)=ur{lOwMlMC z*HzXvK8WvmjZ)ING~HY?j%w6JM^5!gb&2aV{{_*0@C9<^o__v z?n*fuyh2uHqO4*O!r9=<@;ry}N%|i$M>_u|fO0m_eU=H?N$4l(zsW?x*(45TdBWKs z-2;eEB~d(I91y0HoPUn*)AtwCNzS;+yBtwi#k&qsc?0pMtWAEB*OqjU!N0OLwFuG$ zi;#sgw!z#mQ3k%lg%pq3hW~LCe~KiQySV~lK^?Wi-P}&GiQ2KhL-0U^3Xi6iMvH=p zDa@G|bO71Z@rX^ynH=251fBTbX$}7_!yjVWoRZ=%ehs6~So!N<`8ri>t^bPEeD{jg zbepeO4R9ge#blJr)&!`~HMK>RNLzF{7`{Zo`dZv5b&M=tGNMzTqGR_NUW9E(8NSg~ z9Cibatn=jPVk0Ar6p_P)!eALGfj2f_ItWbJdcEu+lHf!_xdcxl@aO|GL^w)<^=xxm zh)rSP5dhkS;Os|JSa_Cqhu0}A4BF!A3G6e$G7s7T@D2hkG&2Hz7i z&3C?Bj{`AbS>}(%WSIA~^l$jgW%Cv^m(5$m7KckE_#bXIK_={&xw^+d%!%nXJnS$9 zmy00CF7%6YJs=ji+%KYOhVJ@nQPZYL+4B}nTiCF$siE0^J1B>@Xk#tlhkt^MwuY|q zYiyhK*_{=C?`h)9o}qr;oj~LfD~y$HYm@h#sJ(|A!ui5(erNm;`=s~G4=rt2P#&9C z^YMB=G^jds@#6a6pO@9piaX_qDxhZ`pCcNjc?i7UrRxuGZ$CverMSnV{ci9~Lr+=m zhk(v4M}RYiopV7R1HQffus0V<+GAauJzg_i9t2GX^u`Y}pw8)LLv~@Reu8wI*X*1N zPDg}a?$x;TH$usB8Slz%LfGX&&{RN?VL+YJEr#sdOLno(477(^v8=s|5q5bHH1)8@ zyAJ1^ZVe)Qd;5C!@c5UtcRj)`4{c0`y_38M7rYue-(D%~x&6l5bho{?BFsEI9_TjV zS?DaZp>x#H-=*l%kt15-5~+^q?t{m%*XUI1knRX40GWpF33wM48R>YeImi0ZJqqt{ zM}Mzf_Jz)E2l)nf%p+)az}|BVsB>izz0ETZqH#wclDB>^E%vy7Sf+39pSVHoi#X?; zJtsT#6vd*Sk^5T@xtO z(om!K0K8v52#*)+BX);p;!rU8lA(&cxuZNAj}?Ea_>AK375}FA zFCxyx0F6gX5phsblU08j5%$>^((c)c zC|=@u#8F?Q$YX(WMzK`!aK!TS}w=3SQD10CCKcw;_ijONkr6{}~()~u|-zmPT_?qGl#eXU~KB-9ClQaP9 zd$3|}#lsXQC{9w8r%oh{>c(4+_|5T+A1Dm?QKTrVY{@X2QfEd5dKt|F@Kq@)`6{PLOIjjFS0-smRU- zIuTMd8|YGGmjZ4jDJzwDd_zdLFu;p4gd$m~l(9l_3j@93LCp|oov$SG++h+W(}1WYr*vYA zr;)YZWSVYd&QnTo+Hj4$C+Io+SmYl_V$fZq+5@$ zZ!ZIT+&*qEHa%jOZP2^s8XX-H6dMF zJjr87z&y^~j&yyU0Oa=4Jq+(}M_+6QezF}Lm2>Sx~F097g;GPi)DJ7XBMDw zc^q^@{JZfaH{m!vv<-V+lmz{4+7mnpw>5IERcy@Ov`&eAdG4GWdy$TZ8^|rPj7qv05J} z6s=Sg|G)mf@9deqlM8{UXsa^G-0z$-GiP>ZcV~Cc%$!wRr6}*>(07CKH!E&Zyi;+j z;-f@#W=|-JZ3HLrc1?d-@hu|cdz6=VZ}9R8i271-GBKTj`grt-><@@MH;6IC_KL|i zi#{r6zs>xE6o)7lD~?s1s92^rLvgku-}|WNQblPe@T-;Qiy+f)Rs50SeTrKYrM-|Z zxxKb&`VK{DFXVew`CW?AZjgVV`~k%y*&O%=%kAT{MzYPJtfKPbgZ!oRs>5GO{;5b| zII_)Qihmqy*&MpQwbz@t>$su$py$WZsfrWWO*#15X z`-HHxDMHH^ZlJ(TXvmunYS$>CX5i;BZ`N0*1#S=1-4XJF-WqbgRz4UM-=BP zB>W921|^|6ep%XeCinv1HsXtDfs??7X@eL-;}HGiK#8BkoNRGFupT?uyiA1rdYD3j zzVx%0LLTN4rW~&-2Md`-cI)8P zKN<^`jQX$BN~OT;5tu}1`l!Q17G6uYm3y4q+H2#s4V~y_BC~BHVV7e9yO#c0Etf}Dq^t~I?yU-4ft%H* zvXunq@-bV9Hm=*GJOIrFn{2Sy_ATX=jGecY~OTgl&%=lhVGVDyzjU}&bTz=ISY*-S8GvaMuGLr1>T z$9h>G_k&o8Xv%NN6x=Gr`;Y!Sz3UccDJs;Ele^K$|ikomNO-J`+sZ5(sR4 z(=2_wR*b%6TS;dmaQ%S^hFlAQt#3Z`asRk|X!1bc_dv5uE+WGc9E2WdLlcftNjp?pA6v-;tib!jYexH8vGxl&k_k~%a7Sg66=%Lrw6tY(=FGUL}G+T-&VrMWZF(j6vru+ zEAm=qI^WEQmnyDQfTHBuk1A=b|3d~ zRB@W3v@7IumA_bVmEvl}b&B6oyiM_kiuWn9Z(%)K6(3fVc7~kSJJV~mGx#@E{*K~4 z#Saz3Y&YaH^FpM(!8cL4_|gF%Q=V_u%-=(iuh!&cL>MUZb%5upyi`%vg+b1H>8JHE z<6k97K4$8&<#g|p3quaVk!?9U&|f0dvgPdE{HVaZVlBXCVFIrfkdIA3E&>MA~uoV)arl?!Tzlxg@Q?Eru{Tz=rc2 z^SV(^lk_+nB=9%0j|rjFhnXOAON_snN=iOrR^x9*=JNzIOgPIbVa~}!)gCV_^*6&~ zto~*$AZh%~^g}*u$7IN0*}0z(4iEIXw*V;(@T2}_jE|ZBK;&`~m*WiP4}u%Ln8MR{ zf{r0ZdG5Jq?8GlEvQZ9mxM%W&|2AUU&&U>%WnTjNf51K?8^Xh97720RK(jXq0vQ-f z2)@w;&R!px@3r?uk9SOp)kB~GfzZ>;bqAN608Yw0@dp3A(91%sEp7bQEV_I{Ou|R zC4uiUA)#2KADG1sHeZON{x$Ic6Lepn#e8z6>t)8~pFPNHwZ^xW(D!ZPW&JBZi6r5? zCV2)4c0I3G@BuSpsF0?qk7dI*A|>XS1Z564K|~A>pZhG4gr%#N0c0A?4KW^Y&KWT$ zSM6Cghc~0iBKfbt9253pCa`b$?BD7NTJxCgL>m^}w1m%MJF)wHb9Wd3twuL1Scu4H zdlL+qY&&@q?*e_0*c=)0SQ)(2C)-XQM4lB!8PMn}wP+^un;3Z}(MsdtcO(E1gRrLWg?VPQHbFr}{yym}n0y&rd2?a~Bkrd=9=MpFdgW9WN6;1YGQPHXp^^=RDs*iIh9 zdD`v}`Ye%<_C6i6og{20>@$*VCrQ3tg1-7Q&ok+Rx@cnvAHPbPxTS02ShFRuye$EhudOGYrJ*k18SHj@FG?<~bpilY_JQ=F(c zO>w3o-wwGQ?AwSd6|Yp}>mubhD{fM}Ls4u|NdKks(yritr~D4Z7ZhJsd{yxs#l4Es z&M1FC`3Tz$Jm)168!0wZ6dM)fCn_IdIrJ;0J;6#j)80p(zmnvurB0hiuX@`&9*%M= z4z_t@Y)gq}#!rin*&n_Tc8&|((>~n(tH8by*_J*qd%t^{i+E*!-@@Vi%C>RjLa8j8 zS%aNV4xzuZMOt$l#d9P72L=vO$_Sy97qoPqR=68LB7PPrSMLs>NZTS7SeO`mIuv=lxN z81F1$o-wKJMM&1!E4^4bf*ZYxLNRK@z(QpH$%;3YN5O(V zq>aN~8B>QNl~27$2IpeZ92D6Q>@03?z9SUwTe6LVT>@+q1fIn(5fGXp!gR1u7QwXj z<%E-k97V`MgoVRjbwbTa77kx=5y4k5n&4+-zZ--TLBak&VCoT#9lqjo2;598!XY$A zgdt{0vUgspRbvN9-*i(hD|Rda+zGe{gDJedCy4l0=7% z9$G?2{PNMr^VvH6l5{~j%kbHbAs>@$L8(OAq@;YOplj`J6*S}otR32DoZ zhJ6F4sTEAC_@Xaj9Zh3Y#rF0CTRai!^Sz&D$j&xlf1YID;L}TD8I3+rQ9JvZ5KdN} z_k4eEq)1)lTM;u7-}~Y7H|4z**~gF{q&Q5G&)JlpuUMwYla=zXyM2Sli0}D*6$dDu zrN};+=^O+lo~uaPG5M*AGZgt|Nckeg<%+8muT@;9c&p-Via%1kPw`R3Clvpn_`KrZ z6kkz%Q}G?eeTp9{^2Fr!nYkg!b3*uz%XDMsknql45hwH2&c#@oBxMGA>%8g zF%yEB968_;GdbQyM(-7f0$(Bgf-&Z7a6$;?Z2W}~4%5I7jy^$BI6*4OSIF5AsjraH zy18!jdla6{+f@uPx*tEjvykh_a+;9uEaWF(({_;+XCXVl`m1roSx5mAz~T$X!j||f z*5e2})n~CDM_5i1fu2L!LOxH2AvkZ7Y$5h~9G=w-ytmLaLS!?6wjapltk>xuO_3}M za7Zu{n5fJJInHM?H;~BjnQZaI(GLt(;}GIPjv@?2l+`#SSZk8mgqIrpda#tA%04^@ z1)y}U22&5VmEa~K<_`E3A?a&7mk>jQb%(&)hpfn9Ed_{bAR*Zw5j7Ba7m?W@B>atG zM<}5we*GOBrxIxvUo^pp*e1T{93yHIh{oC?oX7}?yFIJ3gUye`S@m_AS>mt1#ZFJ0 zQa-hG?#!BrH5XTwSLaMaD>&6PQ}9|08qc77r=L|?GYy=yq*`6*qohI3jBeddILWJt z;j_wcR+6+T=W8_2B(Q~u!DC=`4ZdMy87wNwE-ab8puA28xGa@uty;?bi6((zg)5{* zBA;HiII8(Pp}KhdBS}~*5R-xIg0CW zc$AOLCDE>0Zug)&BJ%cwK1o8pq5+ey3k0Oi9hv#;p5ELK_*`zvfOJ+N4z&b^JQH&J z-FXro+zw@H8Hs$R3`mCqNb5;xFlnXW4b7yf=x|qC0z>kBz^?a3yu{v%#O9E*9k?IF zN<>ozr1KscC`LkqNt+4Y)@Og$Cmm@<-({dp8LDWE1m5dSFliibwe{KSdNPq_^zlj1 zl%b9jk-#TB6AZZ)0$U%~^>F{VzkF6U`o0I6WpWW2=Hgx9B>z?~JkuEORy6s(gLjTO zlEeQo`5pj^CSx;7$Uvp18V1OG3{N2%n*2cIGrGxh`xqWawD+SD`;iS9_v3K3mKx}L z9(hbKbrG%Ib29OcU7xum{m^Lbj546nXNiQgLjA<^QR?*aDFM|CE>YA>dn} zA*rW>VoycdS}A9+-~HKdkmvCu#uVEto}$=Iv5z9(2bh15;t)k+V;QUbM8z`28H%$N z=PDYT%QEFxDzYzQJ>OQ`s3`3U`A?Mpsp2mcA5q+)_=4iAif<_HQG8EP+7)``RUa5( zy8+V`%^Z?e%EuJNT7Z1wHy4n4to2Qxm(|LGk<-+ZI|_KcGjQZ8#W^wepw=E^vlvZ zP4l>CFvq^_(RcrIYIeL;d}!Qhhp!aZ3~4{pJyRA`T-#tzK#$M%S9Xw4?~%hJmd>6_rFE`B$C5d zxVJ%M)(L$Bv^xTF|FiEzH(G^)?#OpQ#}K2tk?fB8F362!uOwT<)Ta>Bs^`vf+>)Ij zc}=BHVcF4SIZ-H`&jUV7Lsr`K*^WDg*XUDB9K^)2RNNA!(i@XKXD5Cy1`GQ0wm{v` zKNI_t;&@r=^95HQEl|b<3|LyAtW<86e=mXsir4BN5MhDpM7arVLBKvlC_wa_#o-Mk zhWbo&0}0;zkdnE9gnwKYXKx@;h3Gox6BY_Nif|>OSfEH;=gXf4a08NzQGWeJ1m=MA zmqf-Q2!gU*2^aIQv4m7ds#H{vfyY2c0+giH^f$7H{tC3wOqU z+YgXwzSA~2Uk>sVAj0zvVW^Pj5NH~6ov{R7dJ$)FG}5QT2GTqxF!L=2toBL#O31`- zQ$+O+Op=Y{I_D9l2swek2MfGUP8aJ=7ejn$nu-)iu-0s^jW;w%RG{ zJE5|w;)1HuS+S|pXO>sTI?eCXtMh~lX3ve)hyxJVSYpOo?gTj16_>hmdQ5=4>+Fiz z=Wi#haDW5Q_v~1e++2u!BtpoFo|3Ad9$G5+kTjyt43bx>X`49a(cG) z8s&Hw=6KC=3iI;31vz+& zW!|J5FP5|3yKTuW-9nsU1p`vAd`!g~I=sAeHruJ>;Dg+acCticeWfRLNxRDts4On8h5^@1l(H<3wVJdJ1LK@t zJ#ZA!=Kq79dS>BJCr+s^x!<1lrtbo>D;tp2>9X|YX)B^DQ!kIKO1UC@rFT{68uV+Q z#D7n%??;*I?MrVubXuc*&=R$2kE)=98yRU~)dDG1S*~n2Ws0_3jW2 z{!duxEM>sgG@7^c90P zWk5PNq9N9k&|uQ0fHyRgx}br6W*W^(n*`dfcS~c(c^LUvFXg7*YS6a6f8d=k2AK&a ztpWmD-~48YcHwK9(Z^>9Q-(THu#?#&G?=ty;B9@YEPXI<1p00SZOTwZGw9<3z6pk8 zTiN<X7U!~>q9~Vw~ygTM0-CrTJ6#lX=Xog8U@z|NM|qf{h5RYQ!mllJ!dl-qX5E| zkmHmPeLOy_(_CvHo%bQkBcZ|QGrU1tel%>1JXVQdTE&-qS-u}-wx8{K5+d7(_l3ab zn0S!!O^y>Miu<^UGp9_yXja9PT8~&L$7_HusrM_g-}of+zu2eM$0j*a^Nm$JPm!+< zEI&(ef#MRywTd?>-mbV=@fV7ZC_bgQP4SP4uPDB+cz}rh=s$`c8j`lfG$OW#eoM%= zRQ^QeJ1Q@>F{JZ+XFiz*gK{z>0Q_jpcfO|2RGg#oOO#)#JPik(0pnLj2rWbh}meSxx$ z49NM>m$P zu2BysP7wLcMzt&(o8x%XhtWL|bpKQ}c6U5{~S9X|Uh% zA7ty@d)5`O^`5m2cHXSP+u(yKG$#%p!6%K}>qLw9NBc!Tx@>>+?RJAZ#2-EIXnFDe zut>VaDa)tqEcevY;~|uL1J>MUomTkLSNgWx4@0M&9G5ba-Ba`9&Ehu>e1Ch|yZ`AG zi+6`Lw{x8K+_VFc_rl;-9f-Q*W5+$#=9M;>V#J#dL&%F`B%@fUw5OyEK zuNY8haLpBA;s-WdjvvE@8|C2$r#=o2%NzM_3{&p)6uQxJD&q5tchdRzg)47*$A(pR zH4~0wLhpG@2&XJXLip!Y(&q}1q_Tew^Q8BDt8O3U@J4i|^q-K1dzO%-={8(AlO!L2 z!u@Gok{fP#_!^SD{f9?<7r)p_`gOu~#kdvG@K4Bv!^4;s4POCaN*r{`60z~7OeDSB zy^kP{qONeC038YQR+!2m-B4=C$y(l#MvFTSGcCswU$-v;3*w5hct<0xJ|J2Fr3p;o-zbX zS_`<5&d4CkwDbm6nsK8p88cmXNE2phaDp?WNjJQ+WaYSLX8K0b?VNNt&1{#WU zdnF(vx)0y9f45J^Btd`3z}imehlqKW3pbD$fe1@FVYDxwFNS>{8RRF-7CC&2k+{g0 z-vnSaNd|m5Uz{QWbHGHM$XEnH5SoKRwFE!o_(Vot1VM;_3OTtOh;sEg4Bv{e#}MGO%Dvz#qqLIH?4BF`|kq8)hlm~cP3f{;I)U(a!mgGLm-90MVVw_9=Gg5AdF3Ckyz z%_^BbYl=Th`JkE0xU~c`m(lzj4A7a&a!7RM^0Sz^oaK5|F?>@X$IFO$GpC;7waMw$ zEgbT`=jDW5@0Er9$lM~#s|#bGZx;H6h5bO^;l+>%wAZ{}fAFg%ZO_7?9q_%z7=}w$ zoYL+*Z`jms-kh9v@_m9@VCDON2}`{{A-LKe z4Ee0zGC0y;iX4GsgDJE1BLaK|Khj`|9Asqt1cNFQCzcE!Ryb^+j(xEfe<(*zgikX~ zJD8s>TN`Y4Fa`U9+2vDWGIjh*Jpk;_w7g|G0g zJPPA1xFC;>vzTT!52zg>h$8Akex2hnxyZvZe4u5>N3?Hq=H}T2a+u(Pu&Js4ltz0! z^DweL-a5@TfOK{urkjlbZPNIZVC&lqeU-R5P#?F&=#y78@FwhnF4_rAFys^n49&FG zu#4Pwh&91jSDqMz$75YeoB;FIt%^3`XYrB7Dvu|sYj!;^^ieq>@l zvLWMs;M58BqY-H9usbuMuRh}}xp>noz=pR(`Npb``dO!~uM(BzL1qH?^-#f<9~)4<;ahAc*E|gwQBlrA$Y(0gdlvP~Q(UQdrJ|gVNWWfrIWNI)RGxi1%l}02 z=Ze2nd|dG<#TOJ`RD4bGO~rpI{!8&A#s5>J4VLxMsz#&{me@m)R#@_7inA4~6qDz~ zFIV|0#kGppD{fTWq)1ya_1~koMRBVl&Av?ky<+k>(?3=IFGaDrBfqETiChQZn<#I_ zle#Hy#*;W_oAvZpj4RTzOt~3PDpkH*k=A9VoAD&tmdTsz;YQ_eQk3fg>31kk>ofCj zReVzM8O0YAUsROq0r}rop4MoV&s3y6n*28uPf_fqc$(swinLNQ|2c}ZQIoGwq=lON zGR12Y`K@irrN2-0p99D<5Y6=%Ro+~eytgyGjbcpET%Wnh=PRC}#}&8yLyoI)6%yQE z9C2K&XKr418CI*uH%%VKa~DD|uGSKFPPcRJ=HhKH?>=S0)zN$RT(F?yHZR^KzHYZO z{<+=m_;tHOGoIV+%_!fKGPL)elm#_=ZeLKo=Leuq5_;;M2s$v$rXp7@NP?r~;Z4r%VzUVDBs zqvM{`1;5#|a>f(L(^2w1vEY&2&H{Y>wq27+x%hqxcS5dT5*TB<3cqMh$N7i+l1c;& zO?3x{;k4d7wcM!mjG+{|-NYE0^mpNu6Ora!N>Lx$1u@7qoDfa9CsW!E+)!|g@Wvjo2`5H!>KwdD9%1>`p_V>a11>mSlbmmG z6eoElgj|v8i(?Bm8$%~iZoUZ|n84TufhPhyeTL`8(4diY^rOMNT$~om=`{$ow8!2x(}aI+(v2r+DaVwY0!r*NWXf$f6#y zEb6%ZSr&CUf7PP?9DRYfUUkfC5c4jIVP%0gBjz>d`hq+xAn4jH&;R!-xtO4vt}n<% z5-sMGP4{whyy3BYZ^6*~?q27i-glS8yni@3A)> zqS*V|_H8~Jn!uYz|E%cp&i^1FaW?K4qjTn9FL7OsE(FOYWUT%UR z*Fa$FTL^vJPi`MfxPiWnpjjptk>Md6=&?!d$Mm}p?R-t3d=3j}U>f6QM4VHVDt4A5 z-=XZ(PilUX?_uQYWEdd#m*Fu)dq0+2?E*5`4;;?mTn6d9i9&xQp@G}RK(uzxS&GIe zfRJ`?qmRdjb((7fr1LP&(-TN&F!~H{(3XE5cIw8ch;8f#(@H+~Mff0L{cImUu*DLg zK0ZjAAv@cMeMl`kwg0e_a6!U}wtO%_VBbT#A+LiFju($Lk-CVjh)CpXA?>4GRNh0e zuVSI%U`0NPv;1hqQpIVC>Z2OM1ul7%r z$27gY;wg&V6#FRlQyio?M6pl=eox z`;>n`@hQdMDgIgUZ;Jm=d`pq$1MauW_5n(}17$n_nCz28jsxT;X?`(G|ITw|9o}$=wz)w|vhGMlM%_+>EJg;Bg=O8zBSsFN)?>0plj{tA%u(WtEopu%? zO&-LZiZcEH-pucp>n>WiJ<#lLQ??sAg_hcWeDcC{rGtH<zbM~9Ht(k_V*H};3iNKFq?TWlFf;mo zQD_rClwTBnTNzc#kW@5GYa5J_<5*iXOnZ2W8=mDxA&$^G??fH}xg>&<%vl^M#P6aA zSBET&WZ>p|NrX=w3!GHmiNkZ<9pJ>Ri~3bb~34@;pcemnPEm z15oRZ>;f_dS$aFNfp3-cJ0N$9nEEHAW{AD9BnFmafSJ3Qc{JHO$B7wPCS0^3QLG5EAY_3$*ux8NL{LUB8j39qyk7=^HQH04$>$@QslL4F z_P6*r=wTK=3N&AOO#VrrmsfJ$8Z7JeV$gu*Lk-xQq$v8&No7$cVUg0*o0jU{FbkHS784n1T;8 zsXcK`$-e1)XgNLSRMqf-9Omo8PLB3Z<rqt|W#!e?6;;)pWAHSUlP|uea(j308S4a(F6E`w<(*^a zp-4C5kg99`#6DdoSC!5#n-;4ozi4{(^orTB?s+}(@_T>NDda1r_y%y?9FQpk@U8dq z`CW(SJCO#d!_(@vEc0E~wkx-{I$id;N8d+{w*9fW(?LtiLoB%Z+M08bmu2`&$iT;) z7liVE%w4n#*fdMNqp|<)NgE#XF!GIpk3?o0KsuRZ{2MaaAdQbvw!U|uZyWMbAGgKm zjm8x@1h1d~R4 zm96h?D8g&G=*s{aeJeqmG9aCIppW@XFloymu=Q=V^zk*^=(`cLDMK9}L*H^sV951I zv-Ld#eLPOw--d`r-zLy3!}Eb*DKZ_8HZ*~0jQ1#-d^ck!=a@{I#(Y~4QM}S5WubF8 z)i6NjVR#17(BuarA3GouxP1&yBHH`0!)g~C!eBodfwneVz9mK*lnJITqIG&W15uE+ zqLz^3R1|$YKCIK$w;qXSKxTr`XLy6Q{PVC$n|g>}W*;@YFVH5PXYCN%U1kR)Zmo6u ztTDHMS~uK-{nzldt1V6xTqZD!pkE^5g5vo?Y^K*L%k;#$R<6mM7DtoRGXM--n@+@|=F;%kb#6!$9rTk&JX z5Kc_iD|S|(*jIsKR|V#4`e{ViCB?1{96%ly!*ESMNBIfLiyal|7b-tj)7dAn+!ZQc zr~Hk|->SS=t&r~lmH$fRk17AG^3M^mJz{&q_A-!XKS7k^3gkINKBm}S@f5{witKBc zub<)|#UYBk|1e#SEAX@0)2~*2a@?VBqw<>+?^0wx%X%MF{JG*|itG=W{wGBl&j9~- zOn+bTfZ~4?>B5@n9FHb8QWPUC_!E>rNwJG!t|ASH zEH^;W_`@ky-ppgBNtpSjC{9zHqiE(eFI9fI;#G>*DsEIX^P0I{iF(bv=Esyb^O~jq zN==;KIGmE-oc~?59e7Vn_M;rZj_wLgtCgI5A1FPAI9%6jJ_oH*R_|X~m z1^ChF9*@O4t6%hk{pdX0q$uwEtDyrAI%hfetJUA~r}O(aZpDor&5aOtv(b+3r6B(d z2|IZ^!1gcahkhY1oZ1~#&bS-B8%4sre+2$?vL$Yut^ERLg-=9tvdEcMT7?Q@H&O+qIIKlOVXjrb8 zaQG7B0LS_6DQ?Ovmp6dOPmsll@Y-1tX%2F6|WAe>~}yKc0+U&`Ezh zzd?aa^~b})nYKTk2I`MzBNCjft@wErR6`Cxx=yw`9yPl|m==ubyH{Z!8V$maJ9G+C zVn}Pm3)MZF#aEL30CIO2Qy&7`SOzOb3`1ab5u32n_1Upx*>}66L={<{ zO>Pk<;Jk;}m_r%ouqeA2aPY}9j%~!F)s(}MJcStCS=%6LwjQFJNUQ?E?xNX3C3vKq z7HpiCA=c6bAox)0&dI_?O6e9PSelC(q%?`<%q6A!gF_+K&BHzw(YFD!1lOn*#f^K`#K1p-N}rtdGnKl(8i3=9Pe^rNy|&;{&Lr?E{GQv@%|R zj$=+rTGtv$YGaKg9Up9MFp|`^j*%pJVs#e9c#KSlfxzGnp&#O>b|Ez1*TeIK)g+A< z$?5I85V}QD&m}OkKVFn5Rs>lPc)6%UA-~vo!uLg5L@*kP#qEw?F`oy65Ce4xPeZ=8 zai-c&>}iPQ|LdNHc=z&m`Fv18h=H<)tH|@vnjtOHLxn%Iryp|+;;{^Z zKvkh*o`w=_i}sMf12O~Aw7DQ>?>!z-n`5 zhYfylU7{vT*ocB#E(N@=bw})r$YX6n0f;yv?~@}CO;`hBJ>m_B++I8IOf^BK-Z=8Y z@-^^kWFG2eNbhKQHG0OZ!N|d9S(CgPZ4w7XFZo`Ld>2PM#jDXqN%*69HM&c@8i7`? zM%PN(+qJwJP4IHYdBr*2+5Hl}jcU*D$EcCGs|kjC4jvf%ME;KgJ+;RPZC6M~8t9Rg z{h!rE(!_}vC&RFi?RF{HwqqlU>ZwS)9R#T3KGXzrJv+&c&TN*l$-si25riK zbb6;dPK<;GlU4!V*0TnFh(RDO-(w}{xj?-DU?EQW35qXnJYwN>%gn*Ox%e6%`sNHab26%kS2cp}u9LA}tl6v5~godOdePLmC7Gg{H@~e6*+>!@~}c^`5JIzGCwA zK3L_$6wlD}rYU(m^BMi-HJwXSYx$+huVWosk3P9FOkEGZRPUp|L#VZmE%yPp^JVvz zz%y0;|A1$zy8Ke@+w<^(clTs}!4E-<0F?j7J#IqV5X%$-3;!*Aj@ zO-|L{w-BvfdnD6oRcKoaCW;fP(DoMZgT@?H_A2TrYbPZLF2~0k{DTQa%+&?40Z09P zZ&`Pf<@!ChgsHD1X33!N7^;sUp&>WL9ZPl~*en_6B{z+UE0{R$QvBXc_D@uNK2sZj zYRIoQ`D_oeKV@b~Jqv91M__M5WN>e3)B*~whP+WGh(Ca6`~niV`FLD#SK~Kjq$>^M zHsv;<(2<5v>+-mDG>1@iwA24kN-)eA42r^O7l$Sr)E*Sgsy!&$u=b#6wmm2+1FHUK zQ5s`>(`kfHp`by6nt}n%rq+NaS`Vl2BA&+nR6%D^CeOm1zMQ>O5XfL8l8}!m4!=kg z_)K&I3HEnL$=pEVe4okQKw=6aMrsJNg&aj#h$s%fNc_f^KMUYOtH zKW`CXXOI9Q2!6?8yQIG+&M#SPmn;s(b6A`^YkZ24z6Q~Dj|KLiJh%9H_+}%4*CpEt z<%XK}0)2J?WNanS!-#Ad(8Jj*iUL^bf}v0tac~PmC}gQT&Nf+cZS= zCq}Xc5l4XFH~SahPwZY)hMgL*1<3X%{Vb48P8uNLHvBR#2B=L|ke~2~86{9W(r6)V zRaon&@T}*FWWr8E0F5r{c^Z*Ab|Ttgr^U!bKL7K2Uz1Td->=Hd6#xj;L`_kM;Ciae0RuaI0@G|t=Q)Km2vpY|bE_OVx5fzuXl$Qq)mSw()gQ$P z(z$%>NFQ+zD*E~ipw-96TF@+q8$hdL%q%FYV_u)Y7h6#D;88K_5&w&K)aF5dO`uuEY*SwpN;M~srZN4Vq$^&1bnANlID zzV035_rqb<6$@zMIVnN>$IA|>4LBo@YuTcvzLj z`q@5y;1Ng!&;R;rAn+u2z@k2Xe2i_h6OrR#CnS=6z1Cegr_4$CfHPgb{}|@%K)G~O z&pqb&0Zt$Bf5!8Ge$a4v3(C4VB%VYb=LF9&ruR_nt5~QwSaGD{XvI>+X^It!ixheN zQt!2joD4|*W<_3SKd*P99B&}cMe^tt1o;wAUXC*` zSNYzGrzs9pl;e$jMaqv+q$PxUCM#a3D90W0iPyCRn;QQy0Y`xQS{q&bu6TuVg!hGIKK+BYfhtw;kW`Lh+x_)od=wA3Ta6CBIhjMny9o^nK-TSG-U00Yw?FMfr!7r#+SWo>!Fb>wy2e@?wGpzejoL zC!>k$1*eIWH`f!AgipS%(8Y>8rr2Jwx3;6C<03TIAG`0WS=IIS_t&#`FN~lt9C%JKy|!PjSVr|Vn$2Ta_xHtm}D^7xu~FMPdYSlo#@C#-vOxpT|3zfF7OK*)XK zK&tzj0}dTJfPcOLvQiH<{q+r6-|>$ScE5{XmnS1v z!?989kQl@`8)CTOlhOQ8Y85zf!{_xL#e{Imoha?Cg&MEVWRav!Vjf;y-tZbqqA5+0 z2P^)54O!yT9GjWLLrS=C5KC+%+5a4ph**9%9l!7jn8Ctsw4dk*%V=#ld?wSP;rk(! zagQjJMT)>V5niXpH(w_R7DWmnUl`%I<0X+5kYLa zt8YFTZ`tm;O}V)v@smE^3H`xkujFL7FG8uVg?%Gz^qDJgHUqf^n(>yF&-oz{*YwG?ISwhCeUo+OyjGK&% z{|loZ!7xNH;DPVJbHF3B_JD_3O{S~BIR0UMn1tgW{470FaWk(q{y}9}QkED2!G5c+ zz$VrTucpD41Op;iN*4GElzs~XB1E1e7#xWKg1|9Dj7t#u30Xpj3ps%>4AFBIE|dWf z-t}E)0uR?xAx9CY7gGENfmbxV_7VIt=Mz}YALbyn3=w$x?7t zF%o46Mp^L&Qoe>_P(ff(dzq5in20lKUASmn*c7w#n8Mui5r`OtFd`fu9iupxnsWS9 zLN7!aqhQk&Af{mB@XZsFd~U)R1;KAgj8T}1U58hfgf{qPY1d&FB!Rt$FB+>7arW(t z*qRc~$L|cppu*Dqb}|3aqUfZ4!>@a-OroT58prOc|z-MJ-vz?uW_uqHzUXE z*stK^lRD$`D6rr^7FyP|8|?dA7mX7x2Ku2zIbFSnmgIyynD*{t6|#V(63PhAmNnR0n}m3PHw`}VkLykqu#a|@FvL@=~L zMiGr|(tj5+xp<@XLoR@HM0w`3?|)&HcLBnD7KHYV{ddF`kT4G;>+_$SKxo(kF^zjMD1fy>m1h&3@(8ps$eTTE} z&xF29jS}QFiiTWBMn*H4bnq^oQ!)}Zhq?nTjJkuEOQ8fA9!(-tb$V@Q# zc-&FE(#Xru7^fNr$b1aXAR3zdO~_}TtK2?@ClT#-sj=D_hcMU=+I6kXcD6y^pCL2B z)J3#TOJ{v{!oH7FQS?D1b=vw~Lj`9TWk93P5(#O`KM(u9UEi0*o^Q69?RpX-+h{pr zo$Fl^j{tT1&oj3G84oZHYyBxyT<^k{rlYyer4af!J`h(dQ5>gOuE=*1=9{O;cOLSq z71t`>qFA6n81^Rs6T&$BH2|HtSDQY^HdEVh_b4#c{+G zxPw=mM8pL+L(^-NzgYRplwYO%b;^HFQReNV{ANw3iG=#(s}sPtl;5u?_I%XOmkO@; z5F-}ynfdrRlw*GwxSi}LhmoP)3(NZ#=cK`8u>RBaa;UM>jca=8SgR4^Zcdj zN%lwAxS`_@#gV-dZWvHQY_dL_D8#9#KZAN z4m>gdHtH@hQr?z#-Ds7kTcm^+mEJ<51z^?Fw_A)G?D#va%8czu?MB=uS*|Ckc_ z#Ef?bbNEi>!YQ0%=fxoj_Z-H2BS;pOlYE0@e_oni7JkCRuOK;?&MA&=7&V3>n<6Dj$ zgz+s`Lt1^y6;OFC-*U?#`S19aqZ>arjy-dnrTjr~OCf92hzV!$+Kxfih=W<~;H@Be z`)afWa(4(*+3Wbe<<8~}B!(#d;fjWVs`NSdhbt}s`CY^&t5Co#p(YOGiMzPAU^-Ad z@rS5JT(-3&!8;4RT#Cy!63tCcaoH9by)HavT^Ke>-l9&10tUDAHRNoy9wJdN$|xXl z9CNhhh#?QVRzDPkymVA@X`)omu{J5qg&tBpiRLD!Xy7;-Ru|DSIs)aIOa$-F=Z5Tq7MLJ?u9knEL%;A<#OXc$Wk7b8M1!6+-6gL3(NF^W zCEnu9KKWAm#8dy<*nYFk*nZybB%F+2%InxCZm6v`x#_r%JU5c7<^J1E3|4|^m!xLn z%~M8GO4i9o*d|%Ll*11<`65JXMUSbyiL=kio#%Ye`-9xpA9OzRgU%g3=*@>)32pF; z?hqj?zx-JmP=2?~2MQhtwuA{(J_B(kV$fWgxKxoKPmfL>x`NQxV9|zo{yeI#)1Im| zd^6N*$~71FiTktd3x|TfN9d=;P1=Ko_8RpoMA}B-|GIE!4-W5m$KT?W<#;9iWFRLo zN1sn>^%&Nv!!_F6gNoK3@v*(3eb#Xwb#xXCAsie2`CNRP9cdKEcUt#Vb9z>L2ncT7 z{3)$p`XL~(!PGSd#NPUI7z0A<9UBAU9gsm@8i1c=3}`78X)yO{K77Cg7ldie5@Q|A z!x%;6!80z)(H zNthtIAEMq#NVDthgopG3*n|iB3+xkAj&cz@z!K76{VC$RKI?*mLT?YDAf;MHS z<2V#5AfdseEdy`sn-6`XAmjGY(QamfA=g7->w6OVc$}z@rY56r z6KIy<6Bxt4(_!~ZYCopmgJ|dL38Ts!7SO;n#w~~_9z3w!hJ2@L9s=_)JcDRx@;i}_ zPk<(H`xu@?wD)71)y_?kX7-~IXlt{brr60pLuP`hi-^-L2ru9baTJ6&9b`oU^<^Wn zPFr6moTq0%W`faYc!Re5*cedVKF^k-!45wLbOfJg`XKDzKxGUF_XEe7gvc=l&ATcV@pqHzHN$sRJqKRhrYMSqn_Q0 zA8S4_X(OETHt(FD%)&ucA)pT6+}Kmex5$U&d}quW`SF6!qm*2r^WcFE2hjCwzIaS9UpG<~Voo2f=+5Y=bSR!5z*{t_xxV zUajtk1t9MxdndBEBboX-qVLPA=uMF9<-~bcF}Z2r8ZHOnmaynHu;P!4eLRD^O8jx< zLAm(jx)4O;jY!}o;1=gzgi*8OJTUxe&7Kyfmi=bMC#%GE=9Z!k-F@BU~BO=pi>BaZJcEBHPd$rh28#St78t~ zBwRoA?$YXh;@&6!~%_15!XF}Nj=H8)sft0ac6b!onSDe_OQ!QaflV@{`w5G ze9=Czs;4g~uerFg-1^Q8$Kxi?tSGy%1Zhs~MKcGxzZ%eY!hqo=LrVPLi6!MVb1Nr~ z&Ci)XU*!W!MokuMoh;#zK|t1LFOsRAe!=YWDKV)y7!;|l z`O*)BWTLmU$3g77J$u!oQpDlqQ`S4-u>j!;zAd&jGEk<84Xj2BH zLthWH<(Xi}DG(T%X}`seUxmCTn6ya{*!8{!yZ2t?W4)A{dTH-5Wk5P(u~9J+8cbRR zcw66&=Khlr^<^L$eJeqmG9aCcpsx=J4JK_Fcw66V&^HP)>Vvr~(03zfQwF5-W9a*i zB{1ZAq}lrNp~xIJ3=IVOHi2dto(~Lzk?Ai}E>NEcF4D#_@ zGlA{L@Fb$WAN{Z&*^seanj)HZP9Fc*4}J9+|JVv;X8Z%Egy^Gw)@iOGkWMDfQ(jvp zn07Y2L0kTLjDKJ=Da!FgxgE;CuDDC_T}2tsLcU}>zKm-@ zo~7*?Q#5w`T;+{Dzn}62ipHK#BOCWW*{)9;8Rat-jeUQ<@=F!vd_X>9-(REh8x_rY zu}OK}+o|_nML9pfZ&m(b#chf^6kk?+RZ&({pxhqi_bGm;7{Wb^^+XgKDK=9y_Wqdi zH1;unPsL=r|4@~4MFsPXQ9M_XHbTmc{ePbFmnh=446|(F{01xe&H0Zc;ghce-qWZz z`FiN2a&uiA&c{?`#k}$=^)i*0pO@FGdwzaiU3U2H-TTycjZPcfQxO6?d`ox|?E2Q; zhF9L3vi6E->UEK|=WqMnThY5#$DI?Mc1z=z#&3LclC$DK%Al18A{V@{Kbk#q*ZRJj zGluS3F?8gvADlLD*X4t@G;yxK^ng3aU9&NxVAqPm(AvMf<+zRCP7e)uJHu<-a=_cJ zcW09q_GeD=kP;G2_hvM1Rj}*wf&p)*ct306=i$np=)2j`$G1mrPJ>N9<))^4J-6Yu zQSe~3{6KgRYi7OF%(|)FJ@ud4Q*VC!EvH@jy$`*)w_)X3-0oN2DCapPyBc;muIIAR z_d=K)V6*Sfgb66M=i-M-(7i)RsI&!10h>q|=LO9Ha1+3-ig)%8Tp~Ak; zsg(PX9QJ)qMZ)ZnBH^9*O?7#lDcItcf_q>%y2l z&nB2;@!a|O7QYnqa*JODdb7oIf4Lb(pVE9ixrAiDz* zW@^I2h#@Co-;RQ3BdUFyB=-nSOW?*~?E_&oBGx`E*+7B^3v$9Oh!M1M1j{8zbNf-6 z@JmF`nX_aA3AQEV_?6HGzqqUr!t%=>X0e0KSKxXHIWl>ro|F8)93Gf_uTl6lj-$lJ zoVbC>H2;IX#(1rkGE-F}r0V|ljsW%A4m z2fz-&~#UOl~HcC33|kG%Ze-;8ygRaQCobbNEZrhIoUT>B+BpHVNZ*fc8*ZQnPVp&Bkaqx-odU{U6Ug;MqXr286Y`hNa!hK_%crZs- zRLrc7O|7Vk;n2kf>7k2_s;Vd}udc4Bs_uLgjhQEsdZclfyi8CX;0<1|Czl&f)acs4jWldG$p913!3UkzV&i*9Q)0iSL7 zxWJI_L-6Z&`i^q~B+MsIalqt!Ok=38J+}+;Cf94q%%ZX_LVlnn|2TIMpZG9JFqhgSmVA5tmVC&0o>c5jwAMf@?-*V8V3`plH=)*1t!K5vP#MU>^ z(#LDY=(_>5DFf2^F7#Df0z=ZiVCx$VecV58UlyX#cPnU?$wg$yN_Cu)r1oR_j}YyA zrBKecGJ$D~4d{oWVH{ z(isSSe=e%BOCN@)SMTFge$Aor5_ESvnq1ackP%*Ap zqBu^mTycitJjKO|s}rQE#-Uv%MKO(tlTUof zV1HUE-_`PgCS9P^QNfjXjk29Li-~0#L4hbZ6%L z#Nm*1_JGXSO}CHzQ}TRa?MTF%P++I*erR7py}I{A3d50o3B8Ex4I$Z1nMz;yosAcv z_RdN0B6RmD@ec8)4?JB4FG36R<4+uTVgS7e9j{)5oVTBHFgw^y+m`!b=(o)K%z8K!Mtvir-xVy zy_5PQ9VWyRnGj0-7C7%X{`5YN3E>p_+VM6rf1g<*NnOF@%PASYgpz2=$7JXY-Wwqu zVN^b`o3JMSjOnl9C)~3)3%^aWa1==zw8Q-;lSG8Spc;~VX$X&yi#?qBFXYBHH$_fZ z6~9d`96lX6z;PW)3U#W#pA>e~>hCAzZ^)|tej;IBsgW?ptx{!Da%#x^1M+&*7pOu>nVgK7GplgJ2~9yu@`E5qS@g%5$gBqfNgq(a*nrj$vr()@WAcnDYjnuu` zl-y)Wl4xdfN$Huy?YA3W&|th5ZZD zF5DjUV2d9OdV-+thxLtvzP-dh7xFXSK1v9&jc4gU@DX z{|b1HX^kdeJ4DzP2+4O2eOPr)KpOMOOU)tjNn1kR5s}XgN6Oa)d6Mh3?^5V`B@EPj z%F2-O>t>^@v;xpD2L<7Myxnl+C+)v@eU=A9ZWr&aW?Mlzi?N|amcWpclk)u@8}#xa z>gAJ}T`#}+yG`q5ecTV?97LlVr1N9E>&HlFFll@xwe>Z{^H4Tq+z&ie2l|$SHf2CM z&q7}(5*kd}Qt-CE_RyCL8THX7X14DJ(54JX=ikt`-Vzw{I;7e9MnfO>kNUC@jlNq! zvkdEExDtiFlhl4pr(Mg=*B%?iwlaZfj1MB>P*ocF^~iUsVSvoT@HC>K$!|kG`<&+X zG5iM6-j4}ZJLBai*pEh_&AANH3BxAxClVS=T|{g5oSRUPFNiH5$Ehg#cpO>h|7Y)8 z;HxOk_IJ7 z+DfZM`qf%0RB6RqzfiBA#eZo_MTtgIu!8t~{-5XFcg~p{0z{y;sPj8>p7)*0JF~O9 zv%AmC&f4}~LS##X8E5Pn-Jl)*HP4>l*(acZl6iJ(#TRQ(RF-v-e(pqg_AV%oymW!$ z0L7t-><<_}UXceZ^*M@56mL;nqsa4x>3*cRK~eZ!gl|**6~yA>-HKT`Zu(Zzv7 zyRv=-@NCs(UNiJbstdmgom1M#H_EqlflpD#LAyoMy`Z}At4RMpstd0QUFMS_{U@5< z$4SBbvTg+8g-3-h>qkHrnhtt0e|nkb>#fMXoOY7ukB-yuX++d_CK05?VhtC55c%#@ z{d*d}R`o}T$oH7yQyMPoNFd)!s&Ci$*A&hAE@)=S&whn=(A@~~T&EsYY@v98VveF5 zPe|8I^`45o6^AH}P!tjq>CJeC6Qk^04oJroNR&3Y-LRiB_px|8|HW)tTtl7XbYQjz>4^+y!RK2ra+ zqO4y8{YBMzA9y0`o^;oCXh1u41J;z~Ssn33T-fB;;}n=WCGObc6l>6rz*QTkz!*j5 z-i=MmQ)3hGg@P*%_*W0!b78BTPnQ2P=aXe0wK|m2spX+?C%0P_RxbIrj7_AJ_iC7R z&^>2u{^^I@P6xNwFWS4Qr1$vP-rYlS!AA4I`R+sbm+8IixRRX&`B)(w*LYVJ_4nL} z5c}*7{FVb55el>K^Fpb-l?pXt#6=Ss;fKc{B1C@N?=oLPQWp~<;Yx&gkyIX>ItbzU zsXt^>vtJ3fZHxcVOVGm?=2Mh`f*w~>;~|ERZh@huKx7ERrwk%7{ct@YR77e-9)45R#@YLne$4xSMFB03pH1L#8$I5XesI zt1SBsH%MAyk|Kn8(|*U;{}I_q9Y$*(Ytkp;Nk5io8P7m0vqA2}lnE0D0~6_P25P1w z6TC*#xf#4Fxc%zDVibA?hk1gLiR+>2w|yHhaF~ACmmA4l9(>uC8(t1yr$7GOAuM$- zRa_?=cNEiJ3y-w;PQeva`G^^O>Q~esK&{&df4J$BJ7#x$DQc9}1woI)XSKuMR(Pi_ z+miRxJU-m<4>Hvi2;!L2=_b71cxWs_(=%-orl0VNNzd0YPB-C_o^?Qa?f|B3&h(Sd zz!9GHeFR<2jJHFWPGN}(r<;`Z9!AJbh{A=O7MQygEliQzjFH@HOl}INn^cmU3pdf# zJp7>((q$gH*8&sLFU#O(H$d}>h$oHkk>;!)efUF%A7qFl{RjgZ8P*5}`a%0^#Oc_N z)dw_^zea2iMsWB9!y&j9ZL^6 zxn)Equ|CerV3V#h1Qv~92EqJ5<}FFw@qS5%87R^sIB^0u1+&ZvZQ!vO%Azs~*+Dpg zmDLdkiYyN!4g?mJ;_P#WVj6j3BMK2Jj`r)phtOt38iUNvRvgcipqx<}A}2`@G|~hm za(0PtGsEQEb4C)>@IpJwnNUu{gFu%C4Vs=8ZE;r1W@QXwnXWU6z??}bjIlbXaf+1_ zDaDy=SV_ht<;Iz4hBb%Bp0b0Iwvj1!SmIfbV5A2!a=&~$Y`_I^F(nso!@Yn>-Mm7hvxWE5L}W5NF%V zg*|Q`>sJTf*!v-5=E;SpyAqjhOKLyHuZOqO?aHWmeBl>Jhh4>H6gLu;uW5YYdBoD5 zaVwFool$_SAKmZZ?d|AdwF{mO;@fdLWb1HqHo@NO2s6%T-TT->tfg-9i69 z)sx3C_UGdl7ZM6kO0vBn_sI$v1pF^IJ|@8GJ9LF8`yPUO!YG(0>Gm|9 z>K6wqt3UIBvmh5^6fC$U_Z0<lc|LsXVq5??D`db+4FN@_C`e`YA1F&5ab%Ld2IN(f5V$iTHI87xwYz z2kV=s_>Uk{s>}O2UA25FL^?Mz4;I{k8zD#GBd1f970Y=inbwc$V8*(`(&Z(Bp|tg1 z@abGDWf-;pgU|RSQ_6bf6Cpu9+0*VX&lKkQ=xe1|%rfq>xmF5i=7Z)A;b7+c`#K4g zwUm9yiR@@CSzQ@&L?ZN0+AQFMc^e@MepBceD3LM>?4S{oSw^9Ipk$R%=m!r@kT62T zA%tt-WwjIv+!aY&F*|mh+RfO*7xQMV%#z%cSqZKsZ7RbhxmlN9LHIx-E!pc$*Mr_X z2spmFV zqY|wJK@y8MAI`=m8mn6FVEqE#h zeN5IlINYTEG6`EYP>Tp`^Qed~bA1Ytl9@Og>~%&O@bpl}9=1oF$kNa<^e`vDNAeu` zdR>vAQRQ9&VrzI_n9)Uv%TqL9(zQbXW!}5eF&+1danh+l;l;+}Vcc5ywpM@4y$2vOPcA$izaPrQ3XNkN z{ZAE5x{vT2!?rTcr28)f;Fu~g;S*74O?>1FNWeVCtwp*vMgg*ZbiaqUwe!i_z)JIgfZ21I8q8m%P-b;h324cg%+gO9{vWjSBo zBb*!$F|8B?d=dO4`)9UK;66V;$#!NNu@6b&CxeSzGC|4C8%~~`u~T?1aJ^%;3-Jua zvx$i0J|d^qPQyDX@@|{ydnoo%9H_`UVaAVDWE)eTt0-J0^cAY#p~&-*>3*QNPVvWz zn-rfV;@o;p@kJs!itQTzC)IbVzDM;BRhLIwq~|Oz<`WJF<({WHl2zjpq@7S6_Z7>H zDz;Ee=Ek~cI3FCCzCf|B;xNTgienVVD_*NOU2%@0;mDS#zFd({!z||>#kGpkeh6nj z!uY2Y*$+^ELGh1@uPgpP#lI@;3(Dk5YO;y73U~kueexosiMp{L3)lgG2h*a_bCcDjqpcR-=O$kigLb0 z68j&UFLu~t&|Z$F{fkt@sh{K?71i1UF}r)n9|v&ynAd^%stGvty3m)0LKK5Y2 zlbZ`;%McRE*p$C*^N!f2{6{u-i+NR_UGm)I^%AlkA?*gHms(-FkGmw8pb=Tv1m zuWgT1q&GZ!ua{P*{P_ykbgns*6<%-X;gAel$n zD84rEL`Fx#ypO?xz;^)>)YTGb9`~{?2+aAs!GgeGv4jkBBY&2RehI<%3&fhAhlJt& zkg*EzGC+#|H2zcFp$K<*3B=1?{DX5@o5%o0^xz4{&NT8G!rc6o5O0Q0n@qJQW8Gm9 z9;I$C=6VbPvYXw$G@p(`5Yt&HX3Ur~TgAUa&14Va_M<)aWtl&v2~np|y)YijBOH}w z!Y_mb<0Q!BC4&#A!Ibw3NHB{N%dCMDlXFg&6K30h6N?hr+>qM<;*RGd*egO*#L<%h zv*1B+WtCCj5ria!r6S7W!H)#uPXM%w1rP8acS|6F?;$WnzCmwGC=D;%FS z2n*rE&h-xFMN$k*UzxDS>vr5lA#pK7tmL~D zs}^Ko)q-rVUeueOjgQ0Sd-MBw8PS~9%UXNsOT6o|y~(e8zjc;Ox!0?o-LzRV@4-d= zWUAn_Dbq)do!Y?(5IjJ3&TxEXYf9#*#j(yo1k13CHK&K?;5*~Ts->;V- z&^3GwtEQxsMbyQ4Hd0h2eWy<-o^O4Jty(Ou5J5bWevZWk5)9b!Fm;EMe%08un!eM9 zgNZjtr_$sr0-ff%a zG3o9@x-LcmvVL@1;qC2MX|)T)_;z4-vfQ|P6`5X(Yl${v9j(oCrlK)&5lB9$9z4s< zf@hhwz58&SHba}PS6rodzv4rR>lL3+6pjexZdUz|ivL5zdHS~EUx+xsDm4Bh)jv_)M}sjwjR<>Z zDn>QDrRqFx8DF5`!udcSq572?KVEhAvrIorbre^Pi$PP0&i&2$HdK@c3+U3$z+4T# zNKse>gy*X+?G1gf>eBAe`HV!n*C-Y%PEjmToUM4X;w_4|E8eMipW<4@#}s9Mpd8sB zz^66*_lhql%Kkz8>#F}<@jb=8iu)B0DSoCXTqyDz4o|pH=;yM1fh`o_Mq#Oh4bPU~3~rCG6+YnhC$2o(JoM7E-Z>GFFj8}*=vwL{g_w(v4@zU3O>9f7D zyTAvo^cqBF=j3<~948wnbxbU78t{VlE5&j8O6HG!%?AFf*g$zjI6l8EF~5(TVqzws z?1X<08^~4KPMxoN1@kD5#0T=a@h{*5zXYp}{%7%l+)u{&D&zxs>tx)g5EfejM!XE+ za>u3#_v1N%1>-x&nis@3vN10ZoDG|dy|Y21RHT>lD++~$L(YN>cAU&YaugFENLL#^upH^Sh^64q99LVR+U@eG)h-a@+kxF#jlYXvC%hJzl7G`K zMCh;iv=ou+fUe zic=L!6>m~puDD9^e#M6r*DF4uDEt%bpKLy`J{pkxU_&D8H&?y2>M}PB;k`9{fQAd7 zgnaUzB;t!TUgm;9pRGEoUya9Me?uOJ{S=XpK}31D0Jc+|eFno%HZM3|?JiVI<^^Sc zpxp0j{5r))6dzNR{epDAR$cZB^lEbZzz&g;CAg%tWx|)@qZODhfC54Z;SM& zsZPRy`J;-459Dff49`>KGIrE2SL~@Mye`5AsZPd%>BcE0^Mdm=T=*iSyIJ*H6iIO~ z|MwLiP<&XCWC-JbuK1+lCdI9a+Z5ka+@UBl%#if}LV=OUwad`D@5qFh;r$66YeNDOB%xT^vwxz<&xFEKrDwMvZ z%1b*dmOpCsL3hh)@QM>QJOFO5ZjAp8Vi^@)XhOl8o4dx=flFK$TYb71% z$F?GDYb>q8i)<>`xOoED$4v#Vf*HV?j*z09cr_0_m|Z=WuF%xFdJ(T<+^G<0K@t z2O$!EmdPTiJp2-?aV}@Vrc4m5#@UvZ^REapKE)hv0jjI1_9VBs3##0C z9F1E%2MIH}B4xlH4yDS|C{TYvm7`aI`cJ6NQD+pMz;cc?yjEM&jKUM(7Ui_X6hb0f z7-XG&$0oOz;1+q8$twd^*t-kxlR$h1@OmJ=31EICz<=EFsslQaz=WU$hY*<>B@HpT z7>=O0BeMr)k)YW|TiHf4+gm{rLQwBjqanr}4{$Jx1hr6TStzs$E;M=0gurbiS-1ii zY^1PyywL%{m&jFufWR>q4`LKXpaCpoco*P4_!MW=fD}wOq|7TCq6jo?qMn9K`$ji~ zz#u~7E~r^<*1?o^Oa zHF1j5tvt-%7tcUZ3hGRqu7z&f+flz}PVpwBGkIuY3hZT3P-o(9fNtA+-?GQsEVeW6 z)>gxtJP@7hVUN$6#u@Pr1lab-#W6qcYiv%j3_A1hHiGU?xMLih)P9T)Zb%a8I>Go% z$r1c94gC}FHmA4_>1yH>`CQNR#_dEpp5n%tWw{97SY-~XFVFDHk{%P9H)E&GS1jDxYQTrl?H`U1UbbAmXop0U;*ubHyfZhTyeBwvEo$4QpKATmn*JPykGGl z#r29$D1OZ+qP@`<<+DA2F-7*{)Q2ic`$I2OozL}*pP@Kcae?9zMcE%ncf0C$Dn6k2 zu;Nb@f3El|#os9YPVsrga>Z8_cPYNB_@UxH#Y2jpDW>9tXZ0PhO~oaOLfIhvPSp*sn9L`V_F(>BDgIXR zcZ&S*3ggQa-%upo!|=ZNZwE`~ronsI09CsVD2eaR+{M2%+M^{+hEjB3TN1c|he&AfS<^%WI zS3d|{yXFIL!T!qKS5;MJebQ(1-pb+yYpcA-{>tAk=(D*X#?WmDjUhCI(03MWvqC2> zaH>A*vcK{NKq`rZrN%TTW4S7rInZBMO8JFD?tFZ0~;m-sev^q23u3pQ5nUO?+^ z1ulYBuEVl>qs*4EqJqaOCoOn?`x4ao+@jySyVon}JuvqFb~AK8-cRQJ0(J+S@3Q}M ze};hf;gcQSPnK_$xsi^D!u!dxw?nB{QuD(?1CFLKvz}gWMnuAE85T+9v6*-&nbViN zD9Vkmr}sT3b0e=vYG00g-)}A^d=ivllGjP=>GA%>?Tzq&Dk8dLpho&3gWG2#^eB9! z4I}!p7nuj2))z_KevEa8rIk?W&s^?s+4Zh0uot|CEMo8;vWUFt%B*v+nIG3 z)qF^qygmjhXFGy5WXzY~J><8r6`=DPa%+r}ZFPnaNaKO7S_1esJeHBmDx<)z8LS$C zS4||@1o%TBvcIKWgyKK$?t=tEk-!we{KQ0BUOmLITVT0dRF4JAWf?L{*s9?~W<{Do z#)Q2HpRs`tw$sE?czLUsLQwZn1k!L}yju*Kk7BSXg*5moJTeo4O(}#FcR}@XxG(t)*VXPX_YK*a>E8xM|5?DW3%+OTFW(6A~G6c_NG>-MOovm}m zZs;pDuP|6e2Ah4HwBL*Ju5oVL!JJK)j&Gf(XY*IOQsxz|_r`9+yuu|@{^Hf^m($E! zx2T)9&B?}!$A|NO0qtj4Bd%i;aDR#UYRAt4enlC+c!Pb8cZrWc?j3_i4GtrjP?%VD z?+cw;cHlx5-N{w>~$(5*N%kDKe`N%ZwQ#ing}LqgXY zJ^~MJMqHkv0h6vB0w||w1k>$MnP4s{`H)Q>hLi7`XayMYGQ`>Z&06p%LlDXPI6M}J zJ=SXwyvYO6nTspf1`6s-ToH65GpY?X=s7FEh=qu=%iWvh$eP|Pm*sIgh5OfLv3_)0;qC3{Vzmpz_;#EQ*&NFdosG!!8U=NxETXk} z&HywuGoHj$4amJp}4cg%+gYQGJmNTsq1bq>FAKQfO5jeJZ z!qtZFI|IqtChXIz@qNL?GO=+?eR%Y+UhGeZ+^@u_VhhC!6mt|iD@wZ}eNWZp z=^i@!YT6m5D0BeyZ>T;&QQ8^dd;({BX=fn&Nb1WKS1PivWB7xLKT>>5@d?FWD{fY- z*6zsviiW?TxLdJ8@gIu+R5Vh^UiP`)z4Nu(!0Ys8sABgqyX*26bC5|Q@m2~ z8;TPYrCQpU@YozF3hg1MPGE6Y*ZfGR21#f1>z=;x85Dd`nFn4`>FlV~!U& z?qIh8!_gs;0AM-tm{L48zVKiC8xy%lSog1Emo8Cp$NtXst|SibY+Sjp?q6?w>pJcB z*wWaYvG(Pm*tVDxb(+?1GBjbJpVjotax0HuK3UHxjDK z3hlw$y=je`?Df2q^1=iD1&a~;*O~4m2e!|O4c=2(`q{_-_t^^v90v^9EwuX{xUuiB zjo2XI#)|RpazZ30QzpB_+I@2Rgu+iVXDF2?g%`nJ^|kx1W~|J$!xDVmnMRJ1fwP%1 z68<5hBdMi;1Y^egDQ_kJdK556;+0;xQh5WXFteX}H#55tp>QLHl;#T?cb&CHgLQ>s&_;>pt+>u4(h;HzfZ{PPJN8uxnA=>SCFGTi^kpWcu zGj=rtkhADZ3(eQX#cTpLIB6x(GvSA+q;u_+=JA4RjL!?p2Y*leqyx$!m zLD_M((~6EHqFKH;D>}0~LW11GgGim$FA9&pz|As34Z3tYPBWZ#Ux{@D&Bf_N77`@6 zS0~$>mF?BR%szZ^IJ;T1CYLw4^ipq5H?PU;%SU<{*YRrOdx>QL?Q5iR zc}MxAu)L&Njj#&nqiR84Y93EoPTKIubM~sWM&iBRYQZx*cfx+a{`kVy1Uwo!m^cnU z=gNVn4xxw6CKKM~^rG4U5!fjmHjj_vW}k=Gn^inDdv@{s+1b_3s#BiaI|prpmZ-+D zL5(}P?}63~p6NV|;YHJSjH7D}&#UpV(&Zvea=Eh+W}LaC@PduU&baHI71$?d!Zh?O zuQ$A@14LOvca;@j#GZ(=?e&2@KI_n43cRt$tDMOL(YY86v4(;=6DRlOCJ@MPPcATx z2Hm6^3)wFBagat^kdEat+?2~UFnJ(4y~Bu+WRnM? zGYR&v$#G}mZbpc0Z?R<$kMnVR_dqszXk;GjarD|aBYqbFw!M|G$Nj|m;V~|5?;*&{ zlM7GxI(7nA_%@Dl^p7i=bgf~$CJyjdNQYyu1R(Biq~jxiai)GRBf!Xv<2rzOCJ~VB zNB2BDqT=put6d<*wYZyI#A1(o2wU*=d@W@O!&*71kaGo3)wtl*N<0MfB zws^vM!V1_rTQK3s5uTY)<+yJJoo&QxLV^=aTq6TgaLkyo#bd`!88dall)2MpOsK{- zI8G7rrlTnK7blY|jL{yNgnbWjv|_R1wTkl;$=fsCw-r|@-lzB@#f^%>RU!Q|s`J=p z{&Gcf*3|!^xL@%Q5$Aa|ZVCseyuXU{_0gb5d(XIo#&=gNAR^yj)#X(m*qf%ha7@r| zQys-uuU7oN z;{A#bDgIdT3B_M3KCLMG33j%tF8c@i4%K%m?pCZ&B=5oU|4-3yhxOQ=2ydd;Trpcw zxLw3wrn=z{lQ~1#Ur0Aj(@j^LrAVTM<=n3LUB!D8*D9`4{Hfy46`xexq{uNf+Ivy) zkBYA={#o&FihC3*70L84zl)BSn5HP-wT4dWhvCf>IhTw&zbi#d{_buc4d(|Z7*BGD zXui8UN%iX#rJqPm9Ix0dlAgUO^JQ!O*t^xtaRv(@9*g75%ge1b$2kD!7hJV@hTu0d z_ik)n?o>tm;+S*Zhy#&@BM$gey-#l0=T)@s>3y<%pL?lS(WvK^g2N0R`dO6kPQ$-T{*pT;*(EqkUgqS|7hj9; zX*N(O^(sc-x(Yh;YX0l8gjX`Q3yp(+>_doim@^TT;4sN;dn@=CEK3;BnM066>CAC~ zjp`icFq-%M)?zr|Fq=Wf3WX~H;r5i5y7vMMhsph@9Of{HbjciMTEJmG%&4KkS9XQL zG+)^rxDzqogwN=~B!ifcUOu`zd?%!Os1{=W)r{o#YGNc0|GbFxMUk4mvMXl*2udQG z1Oz2J@3^A^f|3x0$Mn60WfZdEF@2Aa2aoXiWfU%x@F9eJ2`{;^i~?=L4*uhgHaR1W z$b$n!+8{tsi`+7ZamVw~`bsTxfY~Ip5^*Hqe0UE_s!Bb&K+&(%QtS?o>Jox#&34O7 zVHQWq<0A@>d4~jU5MJ8FzqrQu4~dkx+cJkykRqtPk$LwW`ijwNC%6`$&}y#GYEiGW zpO+Qw&@LwzU*%}S&vcyA?eYuGI~QN;xYQevjXC44n^;k=CUOmn&)7@seNC~I7LT7j zWybWEAydtDyxnvf&9mEoNE4%X)?iQm6GtR_KMSyLO9|+*poc4GdY3$t$+2n!f zyajtqXPk*!gaF%KmSvCUiLpoS%jBVrJ+Q|&PK-0+Dg@Z}qOiy9WBt(NaeF_6%sjd9 zbOW&yYU0S&BhF5DKb|>eN{--URjR zw}anIG3{I*ai(1m%yQ#yHtf9~*Aiv1OmnU_26lb_F1NFuNxZeJcJo% z*WH8>?eKp+N5(TI;XDUB#d4nP@kD?pN2aaw$Vxa*jtpDRO5(`a;t5xqd2&47*e2}H zlQ^;D#rA|K<7#_yN00r-+L6oQz9pWacs3DqUrQnq@wj0;AMS{}T_zSN4p1Dbc#YzC zMINk7|DVo%wM0X*p52HzKzpce=Eupys-7%-_UExoly(I2xTYReY@wLUX-WGbT{n&I zsn}a_h$628v?mYDz%i;%R-CHHXHBMKA4j}J@ixUf74K4fSn(%{>{FPJ{5x@r;#S2M z75`iDO+~|H?N+@)@gIu+RQycQ%!}jWFUvVo(aeXF=>-Uv;}fTvX-{OA^rpR!&A9}N z#T}D#>2y)YsJLU#E9(;M_Zm2tXn9Huj7y7A2mDKV?n`am>yw-Jck2bIceh^drGCYE z6RN0smQ zvvF}WES%N~sjxm92{o+GHVYb$VdYz}R9h<~3z1X__!iGkEn<#H_!;Jiq}~olEY)@s z6S6zfrP>~1q8@T&l5+F%$1%=NCI5%Q-y%f(YYD#JNDTWqNEjv|j8)rKA}AciUlQN) zUx-$|g-_dbZiFk&x$!w;Y2{4Qk4G)|77~}ijInBb%k_u_dx1FNTh>9U9p7?tmtVt8 zfJLz2Ku)t%+_%)?(++a6!9g+W0${^O1o$+i%C!GjIy2VhG3wLqxS^I2>QbATfuv=DJ5A*d4AmTV{;;gxNn z*cl#c!4bN{Ym6z*;#;_F%x^7sRujoG2uW;b>q2>db>2&q%lwHgM^>F<=|+yFJzhY( zz8g4}Y;Y_CYvNeA;8=oU!DD`61+t^iD#v`R=azguz3Ir4nhsxx?8pR6^*K$6$uJjL zA4$cI`?r4O;MAd44x6`R^DFFtP8Pp%$}c*Gw)jutS9lj=oUcMY5O)@Fw-i!M{0gs~ z`UoIt`5stzWIPiZZe8Wd7y)ws+x9rV`5?lKGjT--Ff!wo7`Qq>8wMRnCUI`=4>q%o~%_`pEBxbLW zKS|79;TxFVr~JzwAo-Ktwd+VjzVwdxl4c#)4qr?Ix4Yj*@)Vy(QmWe>|1QZ$$C<-{%D+(XXO&Pd=QA5+tM_P9f;|y0agqEhmXK-h`Lz(bScyJ{h9Cs9B_XR56 ztrL|K1QCmO>qPAosCc(d)ZtKJ=hT?Vf|kO*zd`mt8xV4Y)i(~8NL*iqS!o9m?{H<6 zQRph+!wJ1a96}&jA!{d5pt+>UE3}s4-0uVAj^!$#y?hkI8F?6wGLku4z=MDxVK!WBzJQh6xrkz&UiB3rPKe@0ej443>(|?v<01a{>98 zv}pevZ%($?gmYmoz+9OAP5aARW+%EFynQ|RO0D~zSe0qanD~oW$6~I6eOvA2vLi4v zM_4r~v3A!N|E zW32!qu0ot`uLSnEecWDN{EfXILS~*^c)B&%3H<21ag3v1uV~V3#xu!GlSt#3j^oid zrr3<)a#3ha9L)2GWqRYLB3&D!09ik}-@)74G2d#Jqj4~6V2{sY#+kB+*5*0wPIH6< zroF2a$0|-%oU15vG>~qE>USvKrT7EIb&5Y$+@$y{5$Dx&iZ2q;No?2nKdHV` z^$!$%9863n?|Y$qKF(2ZuGm4byP~|;#m3`;B^3v4vtX2h&BvyD9cm ztG;>;{T~Uv-*p9%aisvbIQoKmb1roj(Rcu+`Q(KN5#?VQ$B~sJLU#iCG^UC)GF{thH1Z>z!Y` zbIf1cB_{DAX#@5v8Vd6^I5>xk=P58_LRg|TG_31w`; zHw<^g_}?w&Reg5JbCcIg2>;t5eEsI)*tr_-UglN#o>P_OytX}3k>2p^y=GvN6F2U4ws@ zHyrQ4Cp+*#U62rbkR0-%@DAn-rSfsw!-<87HbeODhtESYuODO0I!(NIfg0M(uxb-+ z@X`}2;Qfq$!QxCLoq}&7B9gOXP~sbs(U)Vz_hr{c{B}qfZUW1gQL_w?;y;c5RJSj} z@fAtP&d>M<=gxx~>BWf4Ux3ceE%GwL-0mwO-VC313Dq8qb%#YbA>7SpuE!9NK9V_m z)4c5QKn&J4m(af>CKH`3X7bS9*~pj42}6N8g(?nRRUd_l$}-^>LLAlfMa07=<><0Z zGKt8u-iXRP#*$5J5b#J*BAXj>8$jIgSp>uoAu8hN$pH3h;EuA&D9o4eA%vwOj=mf4 zNFe?MK)YCt2>)@n1QM2DA}~d;Hd7+)(0D=!JVw9~5oi=2Q!FGhHELU!$Tb`x;?Bf> z6dnW=Ya7&RM50zB5_v`-UR)y2Rm^iOysU;!ft!Z6qzDV)!_M_wHi=?j`pSeoUPt3D z3W-yX#sPzrBiZk>_Lw}B*oacun4tNqzZMonQd(e@rc1Wr1l9!f-oi3dusy-4F(Prm z!};>hKiamPt@HQ}eRbv+>BZzkmPUF8v{l_~Z)P?=bm&db_A;aSe0eJ)n%jC=YcG8X z-sbWqz3x4Wwa@SM8e}(Z*34VGsGq#fHEryCeE6`V6D)Y1m~RwtTSu8_^z|H~BhMi^ z8kH5_-PM?^T7K;CcwhGV0$$@1GBemXCpf4&V8xc6J-bHRaG|UbGiFRJjZT~~E81h& zz-Ym=am5oR6i})^JhrsBZS-nn z$tl(>?eoTTX+Lh(*y-aZM`sn!ol=Uo>!KYybn1|I(KnnPUC^n>autr74Kdtv#w@&C z)qY@}lX6<>z_d_$NO#J`PM9>XfIz{-fq0J#OtYbE(Nk7;lh_+Xdl9E5L}CA>8IP$VG82BwmK`*dUj# z2yhU*$pg_Dhb!9#3hGQ;5p*Lns)6S?f3pINSco{gT)r>V9X44m%j0$sXTY005S@<^ z5v8Ec#9as7wl}$c@Qg!y>F~zh638YGMCUAQWEKT=ChkV)w!Qh5J)Seh-Wtdz4^6a& zy=hi}5qXr04s4s|G3oG?sT#k3xD^TP?O18G3&i+#V0W_IxZ~PNwV8)RZmTx)knY2A z+AMCp`aZCNtL>YU!GWPz%W}Q#NmZnE>)wmdGZ`70foAqs|C=V9UrJaH70~mji;w6gtiqhVQ zAFR5xJ9IuHG2bZ7=EAPTE)i{Wq%-E_6P834gbC3 z3yQLT5dXUBe^-1@aj)Wj#Y2jQLrY;hB7eFf`2*_ay|5Olw^0<%67d(RF7N9>@2qj}VP)A2*j;Hu7Y_P=8G3RGp*r8L$+H!k4dGW=q zM4mt!lz9f%QBQDt8Q*yq$9YvKGj+v?@^P`zWcONZIOr5@I2c;I;b6*;%Qt}KOMg25 z&CL(Qo(6Z97wZ<=aL_L*YtpOW$<0s2_}?owrpZR|b5F(ipBGz?bgg4Kf+J#$V{Vtt z8_4s8sv@Cstit|cCV9RF%JX%NIXj=)(CuI-quz#>!S^je?z3X4v6bNc+JW)gyaDSR z-P?4rdvD`7>sJ_idpBQ63ogyd`SFB5Hs=?t#@TgoR-UiMuEyu!986RcPfZOyuI#M;wp8Ch#HL zof4aiyzoYDaj<1qaLYErW0fRhfT@k61?F;{tCs>+z$+(6agD@WX)+=a0^%+xEmxS+ zptKRZCt{sJR}z?!bKZ;ro7+Q_);G6|^<4muttYT1!U@)tj}07x4{nr2klhhThwE~y z@YUi3PjFqQ!#Kfg;RG8jk#8Z+_KJ3a4_xWhi_Ff+@qU=Z1|}AH3V1<#O{X|-C9|l; zO}(xs-f;Vx4NPJKk3|8>-nC}G#aor{3)Y?ulqI141LwP0w^FAf8yJkwABhj-b>m;a z2Ywlrefp2$1G%4!^Hs&ox687}=X6uQ;HJam#)NFxn`De2*oZ5W?Cpm= zZXfGc2j19Q3z>Ox;pu*lhrHVGf#;#JGlMMhPaE{So5C)L-$SiIy4vu8ECqk& zxY`QUZkJE3c7Yh*4(!fqd?43GuMHo#7L8FGKCm3eX|tee^3QFp$=Tsw^MUnbttPe! z`;6**VDhq0nV^XE6L^^Mdo$?n1?6UQqT2%Kfg!uTy+P@i9f&FGy$R(#d{- zUTtn7^j9>!nNvqrf!no5u}V>RTZI3w>X^eN>4djM_-U$>aA5wZqTvJEsh+3UMKO7f zo$$KI&sY9vM;3+wj#E9E7o4x*!WSXk&8m|pVSZ8^#P2IUp!l%jPZfWz_@v?{#jT3l z6yH?bp}0%&UBwR-_bGm=$R|_Q1DBW+;}L^pvueR3=H=FwM|__b?HYK*<&PIM4y|%8 z4zIo~;;!=V^yho4uPJw%InA5Iwp6$o7sR$yh0?cFd1+_G@<**c=x$jJUU9;P2f*#s zjXjY6$mRyIj0!I_0rLmD#@2yLTo+q?&?`x=@cgaNn#cIRHI`Q4MK%?z-#h{ABk`MDt+8`n!;VUJ{P=_uU&E^f z6fC2~GaqYsy@>Q!!|Muaez+cYuk<;>En?BF0!Bo_GHWoBx(ulk3wO=rL2(unv~7$3 z5Esl3<`W_#={XcbA{wi84JPm`})ixClGVU_RjkR5^z2=96381vPC5^9rFT{p4ZX;yFl|!F$?(TO3ODKAI4! z@fTEiXA-FYgo^5}#Qzay6rS8gzG|9Lcmmv_oVJ)kNMs9xtmBn7?s%YpTO{!Kz|6P1 z06z)DX8^AU;+p{GM*{rE9j`i|6A4TRT5t%FsZr7plZ)X9iaQ<^U=|6QZM2nbG_$=G zBq0R#UNstG++{%mw?- zs~h!ZMltp9Tta5Fl{ddzsAD70i|auzE@{@ZS@Tc|+S5!m6mpS^nFZWpwUy0Er%alT zX<E_j8FgpKUpbjl%+VCBtWp|MKyQ?2c;S6?@d_ zf{5dvXL!mlcXm$D594wYxI9GzK{p@p9_+Kh>xfHE$2hvy@VxpTD;=L7na3{IzGRpS zOAk#45SN8ai%nq&G2*3=^)Xh`eR>2=aiEol3Hko)gOVfoGxo+nH8Nv5VS~;zjbX)c zyw5IoDsJ^^;uNP_c_2D{@eCBDpw5(aEp*%7j`}roiZ>yh$wL!UU@wb;IumyTblcwh zmOb8Pv7NcUR>PY-5S{B`kI$OM8SxGT*!IZ9F+cBXY)-KZI`i;0g6>b)(W8^vkMY3` zNg`b*7@sLQf0jWfs9vk0)a!*7siXKYfu zU3lk?a^tRHI=ta9&~S|DdoOS=L%EJ$mE}LTJ+&h3tj2r2%yY|M;@im4Ut(3d zjg`9>(7IcJi(r-Ou6HD{pD>vlc~MgP69~S4xtQ?JN5U`ByK+HR^pWL8o0AqDRti+TrCu!c-{1lF*HlaX;*24C*>Yy#2OaNMGWH9Xw6 zK5W%RdJ3u8?&X=Dyiwdb^K`eK+dT!JVyuZZJbCXSzlE&;o!5|CV;t`VKpYa9hk zz_;PCoLp8J1$NC~)d;+5g3;Op_(LGFzolJ-;y>>0g9Jj6z!bs!#6((NJ;bqFV7XlM zjs?qQ88S=Qs^LUtMVdjz1k)o(oU!3LSJK2%czLUsLQwZn1k!L}yju*Kk7BSXg*5mo zJTeo4O(}#FcR}@XxG(t)*VXPX_YK*a>E8x-e1lCX12{hHQ zS;5AL48gM*jblA+XX`S=_?4Ph7%b_6bM-iv$a_KFHSXXo$R48a7<=j2{FSbhnT6}U zqHUo5mQ4AJ*PtIha!|IYoA;uVEeqxu1~4H045P#KWR5}l1eHF~_4fE4YR{AKnrXEC zwDBc#E*&4dTRJTd`s~Sbri}wmMEJy#xq0nNOWIH9(3v4qXN;ZQ9z^e@lgG}Q5N$tc z!o0DwCbsVwZ9ljZJ_DGGhMzK+1~nkEZ;nI|4;pP4<-ipwzI6aS> z?~~IB?@nh=C>}Rw(wHgJC(dwG9y@LvUYWKR-kUmOyseJKd)1SQOYNY;L#A?+LM`Ih zb+X6Lm^Q5#yFMH5X=jg}jl+4|oY~c_OvETjvDx0*;D0*jmyeC$4Uci;{3cofM!XCO zYz}7~xRfD?Bo~E8g*b;Z2(rlo(V2^@*aiyfOk5FkBQvTEh@a=I03-6UY?r$~%W4CbhFw8VthMJ zhir3xPa@N62s4g#qa#|IC#x~%B9Jp0>cO+zEO?e_+gps|v>C#TGxm&b&<;NtoF9s{ zoN1LH=!@X|*d}a`z_G;>t~Q+C8A#4HVV_=&^9ycas=rsvt{M)9ARZZYJ{x#E?pyMD zv_(9dn4xRw;pAwi;hhw_D)vz9qc~9UD#fvilNIMGep7LU;vI^2DgHolo#Kxbd27%5 zJxj!SNnV@yB2kY=#{XIMT}0@Ws_#>s4aRVpmj-O8y1b_eJ7(TsH-NV!0i3MiC5kfd6X6S0U#v)` zfp%9b-m6%q_^_gIEJ!Dm4A8tsEazKl;&{O3i#>C^$Z?1C4H%9Ni6j8a%js}&=cwi4 z-)}eq4|h?=PMZGMYya{4K5%g!?rdDS_!sg%DE-!#-*aw-^;?}#!-|wh--^_< zl-P4;q0C9JervBi{r$mvD(1X>z+e0Jfd-E|Wh^aym2)Wk(cnEVT<;&sxa#c#?H=#D z=Zdt!d!Cz*(kFR`GUh#5k&-f{A~kjGA-`bV*&}-uRHTLn@A>=ngZI2TA9l99eIR#j zpFIT;=TO@I$f3+$YY#$zu?$2Ry!>LZ8TNvPSU?xD1Kcfvxdhjw^LwzXj~w$+Po zt8U}I2ukBN-qS1d-qY^??I90a`Q|KaX=(l*tW9{x+ZU1)A@}TFTkH1P)5BkP_TW8# znNv{l&YWLV>{^7jD-D(3yw~Zqt7m#yx1u^ayHciqJHKdpr#l=s2*Evq@3N0^bMcpr zkZSA~!oX{8<+If9N9~=5r3O*XkMxNnH!@Blz0@IRo)EK0xga7O-xdXHj?GnhS}{VLB{#~;YtsMdQ( zf{J7z8gF-Vb|zR=>4qczO$ZE6XS${C!+@~R__w;eilz8_@Sn<72yJ&=Dqc(Ej?8yL ze{|VTV$ln>hT9#X=&6v9&g}#to%alG4`yl)pU%sHn;$|#UMSMrQ0+pp#<>7y zJzjj!ZuQ4O2`}TP*j={)o8{OfaDw;sZ9e#jB(PAx;ntab>qj#T`^%*zg)L4yB1xQX zvBK#3lU_~Ftp4KqX$iG464yD`?NEQ1J2GW-#+6bgo@YAL$8)M zm8#dw>06&~W7SVgVZA)F8}30Gv_cG93r;RI`Yya&W-wos$OFrBZg^7?nZIvC0QpH^ zJPG0D{7nmlncm zuS9qTOErNEVD>r;#IJYDAh9WlhL{FSw@I49q`g~KD~oXvXWn8r{WG^wnMrwCkn%hY zHa2;yoF_I%5O|a3J9C_lEhu#pZT_N;Ehy1a2JNODYLRxRWycl_kh=)H!%y5Pt#AcF z8?4Z3utKC3$0EDHqd~hfo2Kn!rR@`>#6vxV+3;Zh32Q|hO<+#XS+#MIWn#2tVl>i- zqX~9USeulR|$no8p^f7n^o2P(z;;ZYh=iJOZ5`S6&oO!$L{R}(n?i3&Wv zh{EHNYZPIVh$9I*;ZtdPp3}ID3hNhPz^cNO#$~3q5$A?JDK{_#X2r3nyWz8(kNmdZ zbUwc5^=mngGaqWZRgtcV(26Ajj&h&>oqf| zSG6>}fN;330gji$3uFv0axIf%OT^S1rvo1I2DfZR>rI-MF)14`UcV6PXIeDFxgn@D z1JM%Vicq~-@F~uy)&3Q$rN?CiyW%16Db9%1{>VglW5gjCE}m3QPYJ>w?eQjiGCXgp zZO7BtxOWg2axUS24RfG-au({0sZ)z*#gv~0QJ6ft_|%vbEpwnjwvQPM6L8Cec(gN9llh!6ea!5!<1qg_$c9r?S`=d-Zs*pm&*2w@ z=5b-x3vzOrb!~rn)27Wk&S-f~%bS|D$IR$vP5V#wO0)5~p}sj@=@Rd>Xy5+r`?t^W zCUx@~MswQdyq43nSR|mT!%JdCC+mxLZ_Fz+Cxqp;6{t zDqSADeHk=)AbSM<6o~%c8p@({b)e+HZ`10^Uy721aTc z3)+NqXx0*dxOegJzKS4??*I63&x7V(Vmu5{_d>XG3Kh zv9ICSP}@XwU^l6Y$BRyh@glqHuXb(4?LF*;P#yLm93R19?C={(GL8h4aU>wi4xC9Iv=)~e!1$mss3HnA5{Fg;%3E{6@`_A-Ad}Pb3nsg?l;tv4-DKd4TwnBM8lga zw%70iBJ$HQAI|`y>~A3Z2I@SYiRdl_$x2f1px8yRo8lnFVTxBOn(?e+)u$+4uXuyv zQpFXDBsN*z{fa+Rl>LtIXH_S4$aH^G+^txt_zy)=p-h*q$ZH|>#)>3Ismp^aFnRom zeH`OQD9ZkZK2G&gMcLm7U!=NOpW<7p->yg+h4#pC6Mv%kGsXW>d`j^d#osHwuK1QB ziEY~XyW;zbdle5V{;#4OFG$a&2$+wgE%97M5)RbcC|;;|u_Ad}#`jU=y$bcK6-nh% zpQt!Zai-z|#TyluDc-8MQgMyq4;3F$d_wV;isYeL-gd>^iWQ0(xTrF|u3`tp3l)bb zj!-OCoT9i$@n*#b6@R4oTgBfg?p55c7{-al^3xQ_jZ<%>NJ^agWs1@d6v((M^$*;xp^By9*Dy!_yC1myeqLF8 z?d-}){W?|t{i@ED#>jiTvZ@KEX{L1~NEvRux z@39%3FG17vV)Oi|Zr^Tr=|JzLe0L?n+&u`Wj{`Q@VE~F5F*wC;B{6130uV!0Js1}X z??jw0*Bvuv#?IB}P6?SYGtSnB8M*pK!W)qT<8j|+#y9Zi1%qU~7I{62gAyNQ8aE>S zPsHc&07k_~AclEq!rKMB12OB8@M`a}iwrteqPrbxgtwdS$fxlig->fqb<_*|ACh)1 z;R;cPrgI*ednFUHnKGte5K6RZ&@#s`;%d^)BFZ~cfu6sIL;^dELo#<-~9Ejq0))79ihI@cB7agUv#09?dpfYK7R*kshl3Ce6EC+P zteaMBlC&R_)3IQ>#_;Tza9qhh|9D*5&emT++~*s-IW@*=4jW>sHb@antHh=sHe7?Y zix1b}Mvl+c)5gl+4%(Ai^5Bg$Gw-c&1$_f=xum(?yna~Rrgw+tS9j>#njhAypY4@o z=S=F{E;r|b{y81JI(Y3RI|rjT7_gC-VCH6f8QJX--k$*(*-SALv2_rLVIF9+tbc~| z^Jev9_#7)7Y3gP-4Mu9>&-$D!n)p6nFkEAXXOc%&ciw|1J$VIi_V~w@o#UCdaTS>eyQ^P1rEymb_qy2bZvH3C$yzmypUYon2 z)g`h=EU1&Y)LRx>E}i8GkG1eD`T9G3rirCZp|pmNz@ujs$J;a8nRK}bq>LL?aZG1l zwam4x9l}9f#$6wfzqHSX52m4~-Vff`hA8~?M^=ClV~Dfu4S~JIh@?H%#n>AK+2n!f z6kvlsprFpgO@?k{MsV z+ZzHyd@`ZEqm8xv5%%N>CduCNBzr}cJw9!k`rQZF)PW}c3VVFaG|q^3Bfzd-3GA8u zMh4y3djvA`@OYs66*AdlZj7UULeZpahLe3J!i+QNHX#7bUt+@VM7oQO0%SV6a(E+C ze+lV$tQp7p(Y*w3Z^wMAU9bz|+d)p<+U?E(*n1mc#+kB+!QERBvjrJzGuD!YTIjBLHxLT*Bo=KCAh2}KGwpnzuNuR|7Y(@;H)UF z^}FvfbB7sVm|+tUFU+th%M1*Qin0&;HUo-?vdF3|BMgYRp`xND%Hp0x+?PlqQDfp3 zjr!b4z$MW(#Jqn@tlzKich0F(r>d)~yQ`{C)x{h= z?EU}z*0LPc%x?f^30DcfFXa8m_?v_qguJgPzfbs(@HyejM9fLDEffDt#PHvJbNNX8 zr$pGvWjz3`K7g&rL!Z8S#B#+SAv{L%xk8(3hu*p3*9xy7!rp`8ZSD&Ev*Q1vcof6R z$@@1vms%)3DJ&K8o~It4E5t#i7=L{neaeiiLi^%eGBU=exT6SP9eR03j=a0jrJA_ zPZO>Xt`c&-k$TzRJUFFBx%<}fwD{i$|0v`P8}&XE+P5(9_3*Hyyn&E&a^!mpCkk!a z6!KN#zbE{a@Dbrl!dHav3qKZqA;i7}mQQnGOJRkuw=nw~1D}9gv*+3yShM5WA1 zyI0gXhu^F2y?nY?RA6-x!=Bd=U5j@#LTV1bDZlEML>CWSe9q!W7e{Lc)}B-QXl-=K zz$ND_d2~t5keR#&mL%r)2l}fa_%9sU0ZTmWy7-AhnIsaw-ypXO6r)xXz3l#p#qCp7 zEZ62P67kcimdKp|NbiNinu*TiPyfM4j~VS+s`-hF2#J_INn%(LU|a+RjI)wsD}6ru za!O-ea$7?)w||)zE6ZiSB2ogb+>4cqi{7G9w95&4H zdz0|Tdi7&Wz2|x3@bZV2ER-FwmAeiOX#e1CE6v|2iQy4eJ{Wx|g$aG>3F&f!1JK~}D!oW5e! z&s~7(T5!C)OBaMaNHeBptm1a9Jy*xO+3nb7%D!ScCi~+5W1g~moSJbbooa9R3zdNb z4^4KUOZ0f#YJAqhMM>gl zn+4v{j9P$-NRm)+anr$v^X-R;3w9BhFYAHlL1drZr2*+(413gb!No0sAZ%}J$R1va zDSH=zc4=ti8rbU>5;*dF#D(omg*}#s)v}=1b@dE5U zOG3frMGT#uSBQ>D5<>bXI(xi6%rk7S43*XyG8ddZ$2$zmzX|_SmMa}xtpt*P#$F`N zVVdV31lCA8(El_XqUOn*mPC=#Jy&>7r}iGncvNP1lxD=x5-yvKY1l^TkH{Q}tOw$L zMBET6A&5iS*;DqJPBF*fqOT>OuOHwtePz9F=+F7$1z z3#>$g;23ha(9REIB-SzI3`Aa8Vt48BKII$)uLtE_yY=Y75ts|9eIIr=X6sR=G2WiX zY!9P62-#z{MFSU|v*^)99J|#FIfdmiwU|Ev=wA%Mqd2ky#%Yb9h_O@~L`4r_y0!yA zV#szcnMf`<4cU%iL@fR{M#OT<$R*+{$R%<)Rhb^Lanc|xmLO6w4;$+N$%4$P-2?~ zc(Jyo7b!{D*sYyZ8`#*by|_XfyLAv(1Df*UT~U@;$K2n6%lGLjsj-{2 z28`X7Lf6J_By8-))c-zXH=buWg!%v2vD-iRC)>UK#*xHs$8Nj-*X&(KB>$n~IUDZU z_x8OUwwdl8hHrZ}ajwOv*!#DhQsFS2evHU~Pe~U4lJyrhEG2Pes zC+zRWbRJ(*?AtI@;0Qn2U9WX0OS0^(3fcRr zG2P9u*UuS&4M%2=>8^x5mW%a*DoT|vdrbFN3}m?8!UfvnalNoi5eMM{o+O&!^s>iv zKY-rejOjQAONQ*R{uu7Z5w7QJL-oS`zN=@_;W5~Uu=gxvF0gzI#L($^WqUcM8;eTo zY!-qaXD=i&GA#d39@DXn*EOcg`giKkn68fhs79TC-7y{K{W$g;EF38uCp=C#Q#en! zSa_E3JmDJQHNu;O8-#ZW?-SbhQsn=P_|Jtlwu8JH4TR;JM8pH?I3b$rSN_+=?#Ft) zdb)8QagSrY^4`4z{XLKMHn32;j`eo?ea^nkT9TNL;i%{HL3|ZXFgsw}w}a>HC*}|$ zaSp36*t3tWu{b~LVT4ygNT7}gxf~?B)hMytZ4}0Gxj7lEa0G`6Z47 zMso!*rrz^tZr44@Y-)suS zo65S`%a3n$yH%&3AAwH{>WrOLIZoSyo@0769rxMFdcCPn82{Frv}6oX_G*w3RO0SN zdl<$9`=IQq;6@0+Cm;GDr82j%hW$9D)G&g2sY|ghUcwr^q}`P37?y^=wFTcSEz59H zI87~|S$j$iUJBouK@Hk8UL*h1Z&kcJd+ka5-MGg3mcc7C7}xCWw<`7tTyW$d2*Ul| zdFZEZhHOvcnj2u?R%Z<8?9B?%jOL%WCrKzcz3Je?`Enyj_T`xGSB+~jqyc| zi&_c2y&2a$485dF1l--YW=5!9*yr8dxMnNtJsYye@-YxYr{}dq%(gs z9w+rdyZUZi!x~D5efU-tyg1Vyxf%TuTDJZ@8Y(Wc_5YdUKk}_=sM3!S9w|Ilc%pET zkn<4CZ-tQe5&4US>xAZC3pxFe8Q)P@Mnv1I5Zd|RTM*k6B{%3 z1`L>b&eUl?+r7u(u{&cUYKC|Zt;dZO+*>i9-Fg2pR04+v*#YC4G1T=Fi&;&P_y-2L zlc5-8O+=mF;h|8A^0^=FJsolkWrh<{qaA)ROMlNgi;AUCh?xswv>d5p1C9z3ns1|@ z*v_mHF%BQFgny7(iw%TgycOv9O8;CyPHDVLE?ofm4J%$2{)QDV7iZpx@owT036A9A z-7S^85#tq#G;hRs4{_#=81E@A8GO+ig3R0(Esk~Lz3o$3ekT@iam4l_h+c?@f`v60 zh%Jt+Mg(XK!vebgO^A#vF*%llcSp2;I7FT|fIkR6_b+RRvC|PG{IP`_5bgKn`TFA; zv69&+`LgkcdY5bS{Ba)CLwO@;+t@Wu`eWeW-=Yxzcp}w2)DE;X1XefEa6EY z8ao9`xDpa2ECRvLi2iWyNn#0a0BZ?JG@DWI$&m5Vk1rC3>C3+F0C8A1W7ioz; zgan~kj5WOHapM1l$7c3^*UnYbMxez1p_7MhxED!9LfG^L_4ejW=I~Bu&GKP-CeG-i7!HBmJ|DUu*9xaJZ{K?BxOyzvC32-NY*cJdVlnWP_%kU`f- z{JIOx6Jfs;(FEof^A>s75I}*_h|xU#AW$nD!o1DB1Y1|_>q!3F;a3~_3N|<7MT>vc zn>pq9`PFmh&)EBYcpy7FE~oIFyYBI|hcBEp%hPN?XzSWtCM&q@Z04j!iu;O*5lo0I znOE!Cyht@YrYq-7o1LC-*u$*M+y$woW-}=N*yrDW$6amtNDZ&8W-rSHKBoFNz(NcP z_W2vHy9Rqd74on8Cx!c?8dw+MISN*d3&CUm|HhAZkjoV4UNl2M+qF{MGT;raP@%Yi zpu=+%6?lohfrNbZVd!D@I44kzBW!Pf41D>e!39Uo%+ec+0yS}wp}1+F!}+$v+qn>W z%$ND`JczY8Ldm_EC{z+M7hGHo1Yvufih~XX?Xh#=>~XB-(tz~Ng+2BgTySycKoGVU z{x3e>C(hngpj{f;xD57|hXjti3~^z5BT+t{AIry4fwOlLXr?K{!O#%nLhjAy0^@jW z6gs^VV4U4(7o6U`5a3ePIQf4=udcb4O;BJO7aF6|IyeT%@-aMxBYYm?L-hB|J~KMrhxYkw5PpmScnPF5!Jb z`<{&WFT@W;=vNm)1G~K1#(d#^W)qqvAyEEiSH>KEcs|*wd8Iuag9+`F)3T^LB?@ z6W$=aMfg+Uox(?ij|(~Sr~Q|OTZOL)Is9ilKd}?P6h?Ku_>Pa@Iqc3Ktm(P>87MtI z8#4YguzPvk^K-o8UyeN1@R~U4FzdGmVHh$6|x$%?2 zerrE%{Nct=ipnniwD`l=igozC^wT2D(mnE4bl||L<(#Jrd6~PpIoo^H?8W@Ef&Nc% zVst9c4w#$c{vDW`>yM}?=W?RX*F2XIk=$vFV1-0`$=95%H9Cu`z2`%YX*!#4O-<9S zLR5O1j^FsBH&Yb2oqtKP|5zGi^N$Uf9@uyta+JfGej+x7oHpG|#JFBO-UE8^Gi`3n z&EC-|Jg0FSb8Jwz*}GP`FVI}zfgUf(-D+Gcn6GPVdh$Szx09-QpvT*bGY|B52XXK~ zr@dofzTVGh%8S>sEFE*-2ABUaOS!}Th%S0H=wP~T$IXZfX6uZszn*FzP>Q)a-fNnx zJAx7f|25dOxjGVJXcV0TQ4(wscLO~dM6pw7%sJ9C zA;I-#LQa*iXW|bz!X;b_))M{_M6pw_gwH?%S#$if!_nkDSnx-&;D01ri=Tk~JK0lH zY%Azlc1&p#DWiVkvKz!wu$&~!G!-nn6CgqHSWe24IQ&s|a-4FsL{uquk(THNNEn*M zcvb#|=J@i{|7qvu`11Kzac+*!m~VKFF9)^bruG`UsXff`rKSg=u-7wvY>t@qO<{VqKdPOc_(a!JVA;0WgVNKpeN#;=7We)n7!cdLAL ziCMHhI6@_MZThS0h=pL;pyi6V=ZQ(4NH~P~lX1^P{sSi_-4c;+c4G3U{%}l8K6eHu zBY*053DKOeeCdqg(Y)a$(F1DtdS)^`zs4ypIDh_wt52p(>0dRZ9QzRfy8V0q`PQzJ zm0xdJismFSYiX-f_G%8&TGj4mF{eza8eEO4=Nxl+&-8zJ&B3DkBqvAr#kXtM*~-0I zwUTl!W1IT+xO1^dsa zM%Cire?z$7;yBjC&^8q&V*+X@^w?FvkS;YZRSnvuq4Jby@ZTY%8C=}V5KZ~jD9~dr zG88urbU5D|(REu5J?6{#J)Q@VDnI-c_Jo8rrxR_BaM}!I76i5VkiS_IQ3QAG>DG-c6vH zrVIx|9+dbWAuceE$3~&kTZ@zAe1Hp1?_LOSscM`&ig~6(90Q~t!zLV#CQqNN4kQ#< zK8B}ogwJDgs9tahQ|EzZlrir(1NQc29+MYiZ{{(}kio&o!-a6!os1Zke>aa=BwvD{ z`(4L8W*tjof_Y57$k4Rm-lKUf%>VHkf1P>E-qIf|94Q(V}tRNg>!_L2!AN#n3(fjw+L@1;-+|5@mnN+ zQTUqT-x0nqxy@(54(Di?K6^hu`)?x1+u{Ca{J})%b5%ak_W6UnuXuV|QO@T#&x8L! z&vZ7)1Adx#`;Q{fJ&_{GHpFA65BY{d&fk!4BQ*a;@SVkT>W1+)&knRT zO+Y$lQO;Q!;sPP3Z^)k|GJCWrlYk3!t8)K+a%kspBTp^5&Ih;Ow^V^F>@cse5%EA zTOk5Yls}+$B6l7jJv+;J)+n2KY9Gh7RPz(JnRaYAAr|8_2mB}-!(jYTi14pNS3`t- z91lNTmKwFzvYPa$9WCDeVaOFdi^y>dF*j231^Ss`b0q; zm`FdY6BmY{9wJ^_{_dr7+PA|OZTE}etj7>|qvNdiaf`=?J-^Ak=<+V*L&^^>uPCW= zyGQ3)_BA$q+?$Dppy>bB%kngRlky(3X^j;3)xKmiYwK_#%X9?X{ZhN^WpevEGn4W; zG(x8nUS^jux5rgv-`;r`_K#e!C(A$PN5;zdwk@ek?bF7-3Ipdo!XbDf|KIqHaopm9 zdk19Cx2%A|Qat@!a3s4K>H=HTW4O3)fNG2bU9!~pIeWf^V}-{oMeyV7%>?Uc#@vUB zNRm)+anrzu^WA{{KRY7K7el&KzRN(nG$6e{z#jEnaB;N|gzY^LvWKaNl)Vcbwa1N2o2{X$XsxG zKZYP0njiTK^y-=)`4#k-#)X#XFDD%XbnSpXGvV`iAyh9MFT3*~jeJv~5A1QA;eyMH z7&<*~8Rk)v5MtWpE7#OriAwuVm>td~@!`|%w*aGUTV?I}Roev3m0+~zdT<<1p zJ_Pm6-08o?YeU?Rh?}7;5!bDgip(=W2U?{E^*ezvnsu9 z{qxsWR&9_aBiIIw?2rNg*lr`UjErf-og^*|He5)(3 z>pPpvDsQ{s$8#QhV{1Rw6)m;eTntOG&Fx{SIV}CbQm}4cd>wYqd@jXr0#Ex5%>FjB z|7ghmgRd8MynoB%mg<$w_kg>5%e${P!~GmQk7GXP5Pbe2cMTe$d(l{X#1G~TNJer0 zc+r-JnIv%=l%vg%EZTMyC6PGi#G+BW38L+$m?YQc2pUk*>m*8I@eP1z0aNup$0WI< zcxNW!)5#@rn*!2v42MziP^6C?#4<(s6p8g1KynMop5sYghkRrGXOVoH}Y64$|J@_=~)^iE03@+L2dyZ zBh0`fP0D@?t*}O1Kfdj8|0eqXXNcZ2>1pV zXdGxaLcq5L-->ra!p@+#vAh-Xe4g;R0grp3p79TWPr93-Ijf+Be<);jH+({Z&8$9Z zttn%ziM0lYk$J}5aDZRyQdJ<@QVj)>c{@xFQfAx^2l_u{O5P8Qw)OS zD@e(wv}^Ewd*2HA7-Sq5Hu)upVi4(DVlyPX2)ZR+MdVp9RX}}+xF3@C(q;Cw;dAN4b=v%Z_@W5uY{xxTk$b$EiZy=bQaT0z8UK5 zEHye4=jR_w_7<>3BRzi#Z=GHk5VfcT!TWO-4i>1K_dSL;B@+?h({bZ8iy4bjj`La| z#^c*)bs(f>i}N7k3+~3WtdyC#b95##13!QTJJ|Ob)sDq&$AY9OsBDA4FZV6$bVQo+ z+WW1M5F6+D?f4n59XlrN*n@$vk>9pKaelPH{tYJNH1ezb!W=wswK*PqJfeHG|AG6? zkQ?4TFZ;i$+Ie(!#vXZr=W*H5ISVoLYF@N6GL>NNwhgz@$_dx1JR5W<(HN%5in1 ztV%*5$a_*c@2Yg(lbHAOIN&o)aK@@q#)=?Kn!-dvm61mhj>HkgEb01XAkM}S@ye`l z!D&rQn;z#(=kNr|+h!O)4JmzZB7sG8Dx~+`5VOA&N5orv1~EA237{-6`f?l*I86|P z==u2 z>bT7NcJariE$q4Jrps^)lLeRYm~?v>>)Jy-YY*0gOSK7}JyWqY0W46~4+pE*1o+ua zRc9xqT0b1Det?BKE(1kb7min^j*FG0MGamZ-#d!Hn<8Awe&Dk%FGah#yfA`D3pAFM zkfN-FRE^>I?veD}BMJ95n*&2B4mSMn9!abXhVLFpsi$8*R7cj6g`%t{3m-OomhRId zDT0K2BoQA7=t4j$uzjLuMCf4T1i}%4l)zUr-l2qvID(!LsTzwIOIT*)1i}g<#}ZZ< zIe~DEkz)zB22ujcgS_#Z3I(9>{v`w%A4%Y&7>Wc}hH>jj1s3?EPle!ws@w^&yjANv zAi5t8+?WJsq{@se3L*$RgCGT|vx5i%Pa=pQbuA8z&J7|6ECsWzUQg=!AcDYB1QDcy@>GMez-kTZXIux6 zgK?m;nR}4uIOZ4RGLCj{3KY_oQXQkQ3!@I<-o7W)Geb zq?i$$+5W+q&72iI?4N#SuX=vT0f)DVHcdv0H{kl+6fKz8_3+NoiCv-%HjHQ+ZO~^# z^w{K0N8?gP=k>w95%_!Oxw9AGe|gQDEZ7#UH~!u^?P`|cu$KDToU!^YC0#Ua#@uBU z(@*JU3q9d>X6p{qw)WK#ZOWADQ4{(PO79^btRclh#OetHun@6kz}(uZnM=n{n?7%* z$MuAkZ)*8u_0V9wBFh;Ramw^1wY4)B&6;-#{;_%K%tedwhs{`h5!x0mz0#7Yrq8Wi zG?RMM=1oC<_})Hp=7RJtaXhb@>P5!~1)+v7Zmhba3C;dQKhd%M85@_+`VEA!4xoR@ok&Z_tYu?wRY;qO@nHt4Xo zdd;0NAm8r&8x)=!J1=@ZtbDya{ua%g*CqA;-1fRmUj|+z^U~a%Lijq>p_ocPW9IZF zv+*dIwb1Jl(9@<*#}gy$1NyJI%65O$Eo#*Kj{yH?KA&ZEyh9EwOwo zm$SD<_5c>HL|0^g&Pgk<>5iVZ^>}^EBXpid79{tW-8j#*yxFOqE_l8_L?v4;m z`HT2Sa#lX6AUGShgAM2VS~-Ssu*rPu<8b-@3bacD(mS$6rdy7S(&r) z&fXT#E)7WUJlG2l`&`^6#D(qE!d?wzEMFrW&fZ@@yEGuZ-@#s2j0jwCaesm!Z0|ML z<1>f$ig7r5?}BC;wpRx3({y2$J;r~EBdm8x>$-hmqfkO}7Ci`U>h^_g20hwyp%3&< za}1E>V&ARVIEagh?%DW7%pt?itSHoKJ>@j2ei ztoZX3&u3c^>SJA2d`1r_WBqQ5R%LIgJz?<-;x zAxzmmdu@rhu$?3?7vlCb{ei-AWPK*@)TUnsm(_!HqPL|m`G5aA*8 zx^Np2`F^DMFU8030HA&YBI1k1w-Vn;c$jdw@Mz&2;mN{th3kaZ32!DMpPz}pNBpnF zKQ4ZY_^rbCgdWa?<;x@Ds82*YIzaMv!hBAk|49Ch_#HwYuWp`iJz+y4;);bWC2ueOVBuks z4-yWOe3bA=$&VFJr#9NXMfkArT_Ud6$3%3FJ{5jJM7atfBeoKj5TV~$d^hoZ#19jW zCgPYaJYBd(c$4q}BJBN1$TczK8F(MzwlcK$7I?gxjAsvn@$BCb?R^C-6W>dCm~eow zQaDODPB>9GSxDDq+U0wdXzwxL>Eh29UL;&Ayj*yzaD(tJ;V*=IkJIiW!l#6rgf9qR z60+Y<{l5t9eFy#%@$5`79y8d6+51Y+rH%0|h3rF@GZ1$aVbGqk}f_Na3-< zX~Ox!lZ4BJrwO^@pXtvR(#4zndSS+XDUj3YoALCRCO$5tyC-?NffHX9x_zPF6u(pW zxe)XDrk@bfSDfkh7nTUy3*ElZhl(E{tQ69xn(57TA4r#S^7DlBDJM@4MF{V4Fqil+}h<7lAkVeQMAz>cB7U^6N_e#J zSm6xe9N|LYV&S>M3xunMmkP7{Wj9OyV*8giD1hge!#?2`>>|F1%WJozV3oH;CUT{Dts-;UmJwg z5}qnNQ+S^6LgA&tD}`Kd!E)X%yi<6O@L}O&!e@lP6}~KdRrs3l4dMI3kA;61`k2FK zzWKt2!luF&!ct)eA(w+E~%W}SVv@`~O`hCT1Y_5dgA(Z%37@#~RW zXMfp7th6sETGMcKqqUoM_IucS@46MdJn(6Gd6W?;SUP8G#`xh@KfhZ*qJDNbX%msnD;Q*S@P^>4N6uN zUQjrs#hADLvOKmfkUsHQK}qatf34Rhe_g$`h&k0;n^^bioApXI?QDGQrk$l5Fa9j& z_B*%LiyXf#Kl&}#pdF%Dlj`7wE9*k1vT(N0q#l}rLTRt4yk%+~2B;wa>X?SbylfgRuS9kWg z_SKz3H#WMu@Tz*-F2eF^tCzcG)6VACKGQ6= z=G8ZI{8x8+8{_MqM5?ntOO)KVEfP6#TQpj@!|T_7hv&OGhplCaHIa2MH%nZNtF$7z z=GC2v74@zv*pa|?aVHNN^VZPF_Xf|Ndi}WD$GN(`c}sq%t~=q3dS6@r>Vm5h+b&Gi zb=kEIQP-U|Cbrf4nswbMW6uTHF#82p)xSEhZ}F<@Z}VOSHlJwsZOp$H=yL)8BRH}H z_9|$Mu~pO_cy6x(nheK0FN&Eh61(7Jp;$FR61Ub$Tx|N$v^M zxtx+w7gCal+oq(6+$dDjdlmc%8qpR^9qd(bFUg+6n79|o{>PBy_%=FVK1m#2bkv#n z#a;z{A;(??QwWLJ?aVC}V`6X|`^Jw19b4%?0Em}ED|Ue`#Km|Kx;Zhj2@mhTJ$s z6niMaojr46Tql{k96$B^xACj>^=E)&@IOT+`AL*FSYO{6vV4}qzw`)tv6r!g zPk}Aq`g+DSg`hr`<{DFA3+*W$0CB||dXUxWmQ~*AV{^Kd zo<1n24J(@8X8hkEMX+5ecd+oM;>8|R^lw=rPQL^dy_xmY1a%x#^cGe$Kd!K%pJ&{S zU|7+{SVg};@n+LOMH^QH^H$L>vbwsFV?`UsPZ~v5(Z>4KK{Xq5CpB5kzhk=pG7i;j z-0R>P^843VoHyq`Qs-VrHOG*gdix_$-FkTObt_%QY91|J&WT9Z76>=uGIpO(h+I6Ja`RN?1zt;W_)JgQ9z5| z^g`iaF>oThUO2CQ@Sj9j{@NRzax4_?Ti})o^PkE4xxYH+dSUn9=B)nA<-GhaC9Uqo zgF$O(wIsHoTLQ}!uZ5v?xs5_=WzpzEsZf&Q%yqSmL%Oun#2Ll2EnMbcT`jI5mpxm+ zb%!rVu#6T3CtXV9Ln7*(zSET4Pfrk7h(Vw)OvGC=i1@kDHHMRrj&dUByP;0tQ=4KU zO(UB@NRe{{QO(swUXE`*T+vHGgLqoX@g|>xoZgu4_30gkP z`rdKe&c7#)I5yxbFI`WPDMIU2*;{yo3B02SkK@RJ8`4Q$%k`w6#8Ci#2^N;L$?4Xv z<$9XzZ6+7dB+0;J6;v$@!0#(Kd~b3fz*Yqy?ljSnPDDEuW~Y{RNCtM;)v-X0Zl+N~ z4U&OI#zov+YvjWet?>Rw5ncMDF#3)<~EoF_EUTTVr5( z96=Vw5{KeIZ4+c+Y{){!iF83yv_?W;Y;wrhNE!=@Qxz)C$dIv&*2tu6fqX9&;UG;D zLDB1KjT6}#slwJstipk{-2~=BF;OR<(HdQDOqQL)XqaUQeDCO%fHpYP8c8xms5MT9 z^5r;C4}{;~$nnm=y6KkdN&gN<0r(}}Qnf~!A=FNtU)BmsDM_^I4NC;YNWu~uB*TZDmk7XzDHIDA$7FVJ&}cx>f+x$^DXvCwUo z^?4zmL`=rn%C~*o038e621S>385FJmWOVUF3~eLr`7@Y5w(<=7(}_BQ)FJ$-;Lim9 z^yQDOJUco?bs}YH4cF9?>B6`JTM zimXJ@`6h@K8yrNrSuuOjlV(MmCnr&uu+vGGI$b1Fx58OL(#!0kCv}My4Ue8M{D^4d z)m$VNUOBf#^<}pAD+C0kmZ^>4kH&8|V{x@0aZOsytMt>9vP?XtiS7a?<{V5(L_3z49cUM87w zb(jlRnPn}MJE>=P2ocx48*uU5dHE+H(Z!tUEaUVIy%1V>s&|Izriy0HC5>jN2hL|*B;j@fdgGS3l%~KPOl6C(m9Ht z-U=59+Vw2i*UXa+VM80wO9J`nkvcq>A3LXEdv}AGSBE|NeTMBl8?wi;ID5;p>~Ri0 z+^2QrTbgC>ZP?>jisfUuoV_)mL&dROTCc=3pbIYU`w)c7*SG{@bmUEYm?KNs%U(xU zi$wjL5$HMcjt~vfyBkL6d*g!ByB&gXzLVQ|-U^%m^R17=od^9^T^f*H^P=<`Gx9F( zKG0!%uVC6B2^sA*#Nq610qxR&^oGJ-l7xbb+XOyr?{nB=8=}2NIGnw|fOcs>dUIg! ze$<}}E-rf=U8kh!P;p&CYPwA*3o@)>*)B-{i=0zeAgD?X*<(h2q3THc{q4Y_-xz5Iy&oM zrT_0DdmSC#g>`mx_>$a1XROY2;dgH;y)zbGN5}tf^1i^q^>dAJGQ{JA%Yj@+_ZH)E zukmDw!-caL4}O5sFCyZ`Ih%+Ee?1ZLoO$~u*U=4zJ+5;YE<8#&SvXg?KzOQfg^=$F zroU9ka+1GAc&G52UPou^1CY-E)En~~C!8wep0|{*6JAZkd+r+H^+dc-HYolc@%M}W zFY!-{e?k18g*$~gk-$!4AwLz;uKDjHe}2*@-;)TwpZL+j$--$wl#l}MU>86QaC_G(wk#IE;c7G(iMRN0t zNBT#_KS@M+-V?UO1E0LDrvpwW4?A;-cxap7I?(*qVdosmfop`9OaEH&H;Fetb?7}H z`LBtv^9SL3!Win1^5(*>MC4y3Tp~pCwE9Le!vZ0nNxTkxcMwJLpF(GgN ziwwM3{EvmUz6Ww!-vfMHa$Da6{yFi#6aG>7KfOoA7<%$HFg!wr&Xd(qV`BHx;%L zwh_{Whw(jyhYR})M+(OZ>EuKGNU4B=|wrNZ^X8-#QWqCH!`45Vui z`KN?02wxJ?S%~p&ozTbPKNZqFhtKW$!X`pnw+uO*br?^V8)Aj9x6sxJL2m1pfwoQv zI9lx6)(h(BGpQfTXj5PymIb;7HKwr&XVH;KPZNcSSz ze?a)C@Co5>gwF|I7QQO9_0>pk>#KqEPoljqgmFwBkk1p^`fBja#M?S+@NLA~dTa1y z;(G~g{Wau+#SasX6^<7kC!8*vE1WO1b=t6Vs(3n3v3wT`FB4uRyg_)2(AE_}|4#7_ z2p<+cA$&$?>x-ao>x+O}C4Wu0UHHE66XD;5xoDd#U%rq&UgTQ|ZT%5=TYm&Blib#S zgFj5Xtpf*NDSo(coN$5=*?xV0f26g33efr~$fq&w06XhFWbX^apTp;gi^qh5>(5w! z1$;lIgWe1x_&KuEwR?|V$xtY-C@=5Xt)il=N8SGVy$;#?|4lDNKMWz|ufHEg^dk~0 z4lcagKRdc&$mV7*--UlcJA89T;EILG&EOUmZ)rWO_3$<$#(cP7#>%tKnmSM`G~*1KIX$e&j{$Pufyhds@aI=UT+Ml8K_N2v9&g!pLl(<>^$Hh!%cGj{3{Gsg{`iTp8i6ikV0MS=Tw;Kj!I6+^E&MTDL5B6Am54vxm@t7|BO$>-hd=w9?yBpLDnmb zJ(J)+u;$YRG`1;0VWh;%AJ0U;u_*XD=a)0~w+ZWumL&4o=ZCm)Q4l~P!dT<8t@GKVLXAEI2tlfe?$z)lVp!Yp8hD-V+Hh3 zWELzDW04A3@D@;PbS{Vky`o8gcy|sgeLt@rz%=?ejlN#d1SE@B3=1^4GmL2*=QPgr zinxq9-h)2&u)#j2X{>M>U*dn!sL_-EA_NWgGEL(K5XCIVm%dlj1%;0H+8C&?qiHJa zIR+|GuZY9Jc<<)}6^><1<;|2zu2*z0Pv?-21C^JY3fF-LRvLOm^>{vqva5))d3>I(Pm_WjFEaKofUd5rV&Z&q~i1F&hfrO_}#Ek*s zVAQ1bSqDA4(}HjVdv0P*xNG|Y%7F+z=O)%lLM8boyzx}3f_c81z_SQTpg&K=2SL1 zl|MD`indba#0LWv_73;mbvWkd=O3DXnEkm;P6s&swycj^SN}+4e*lzl|2&kZe-{cn z6z69;6c>b@bB7gYxD=yz>70i7*E#%?p^%5M`2P-=^2q?#H`Yrk^aLeWUp{T=(lvHHsgXehf%64H1SwiU3Q(y~ z3JMN^1logFW+9Pg;xt%NNOB?$Xc3OXK`r8pKukD6V&c+3OgK$q;tCuvLO2fxjSw%y z0Wo2<#Kg-3G2w?26R*VqZ9-5dHSD^iLQhciy(IR=fwLvBDkvt74#Wi3Nz}{xa=oh@ z>Of|pC4O;lBE;;MKkfnT1Y!PqyF~r@yLTI&f1BOD7V*E1XH8pNi``b|g6iIFUmU<} z9(>{a`3o0JspY28i@VGTDm!i!AAQR6o0mqHCfgra`s+5W_m6h!(z;D;grqn(iOioU84K-A<>YE<&2nO5qad{8s+<`srQsG4a)A-20IFKKjA5M zYCXy`h2>@4D&XFc-lIEXZ{%uvd4z3Xb82KXz&2GLwqVB0Wws|ajrOk^HDy%)@k6In zPZ&6GaCLRaRV2gTq>kj>dh`rwGs}H(_Au9u?DBRitLR-kOd#Z|xhE zT}Q#qnB|G2E!cOdc($lrg=`C{W;$~4=pksWgR82>RPCyZ+6_G2Qu@`yMh}@VvVW#- zdAE?o(fvmc8(o=hB<2*Ac63Tv>R&Zv!l=Qc$Jdc}&x(wq@V?64K|E!qdf24FQ$`J| z#!WYHXv!64*aTIqN#~$I+YNvT!rZ2{yk7VpmzH5Dd=NA=Jvehfd_BawaFs!hE z7L*a3UKymM*@tDIUbxfbx>lVa$MjMvyoPVo4}-&}ZtD?HkNJ(m;cSES`ha=V841OW z0v)z@V+(X*(W#(4mc`jSHk1aW$NeS$PC~)uwGh0c8TC1gaH!{kBTs}NobTu8MQ%kT z^QGM7dj@Ei2Bdc;PA*A8!NqZ47`FFHD-6LPqdkluQua6x%{Uk#Np2O4$w@)_P{Wq9(3G52R!3= z+$VH;^I+s8$XsxGk3xX9SL5WbLhlgA0IA3DdmN4?-yD_FfrNri!R9w?gLT4|qlKu_L zzX`u1+#aD2!`>&sA5{fHS4#oM{k+40`*()}MpR)I^~IK&4tuj-H}hxx1R?x{XZ>gM zMNZK$iW*LWVjb~WLqDQk78Cr??wBloY8JmVi~n90|AQ=kV;28p7XNY<|85q~@7^x3 zeEk0H0{Mfpcn&jNVEouDo-?s7FrI!xE|9+EPh88?}yqj^Rw>H zuCG-L8q*$FyGGa5-?H9JxC^t3;43>rSzX60){?R>R#z8|L%?vx)>jM*EcNb&QrUg& zY~B*HCtF9>=w^rW$zm-fPNa^67{7%RX0etK#_C9zJ^sz+EvZ#N9f?_i8QEs>mYC-s zJYyoboi~7v;2F7**c5)fL_7Au6FcGu?L2Z2 zp5MfSgT4g6ixn`w0j5@kI2GejWG{k9m^QzpPLg*Q9xCiB94V|8P7+QN&JptY#Qe;U z4!BDECBn;vKN8+3G(S4%TfG8*CArln_@~8NJ%az8_*aE*3LEnL5#LH^-wVOBKSudc zLi(&*IfWMr&5sUxwofkbPRh|AxJP&&5q*SbgK`t& zjdQ@CCH_X?6GHPpL419@jG4~--+<-f2MQ+$XA8{_1bXJ@2Kg+TH$HJ z6~c>z*4~hhwKw3^l3y>pS@;v-&xH319~3?&d{Sub5BBUn2L89?e-gef+$MZq__6Q{ zVTA1g>GOp3g-wL}36sK7AwQ!r9k*K`_7e^g@~a}{V}#b;!5<@@pZ6F)OSn+DSjZk! zB$2+JU`^j$Z+`A$`o@&wqT>;0eAn*1yC*|oPv6tadvxpG&Gh%Y|J}qkEJgZz`u@nZ z?Cv%1c+0oE<1de`8aTJt_T1$sZ@*>vJ=?wECvR_m!pYlbFQ2u2cME69uM0wlFE$?{4UxbAh-ti|rkN7pfb%${wg0l38AsF(_+L&Z(_f(x%&24{uVL=#IVbMzE|bbE5p0cO6u@`|?(7 ze?3&*wpr!I+a7yY;!Iyc+3wrv z_4~ul#@<)ezTf95)b3L}lQQh_7fEb;ES^BkbgV?J(q62em(GHS{viDDw&| z-hSio*|-8dx3|SLzA^KR`nW4_6Ltz@?Q;{>;0iqW#(U?x_A+>GcI{i;SEBY?_^Whm=cx0ayxS=QR^S+(EyaaepD ztz`pt;B!0f>Yl_>ELtL=xphs-C(Zh@H3=ZBAegtrxA zk`v?8G$-~pesizK5B7q4CeaJZdH)Lz{t*&KS zfim}kI~*o*X*=G43AZG6fKJdq;#?a4g!*0c2C!5xK9D+Pc|mgi9|PF(ysZHGN5q$r z@0Q00U_GC&EACUp0_DRWqLUFdp5K}J1&bMNWc?F8zbjud^=nVA^87NE2IMf24bYYJ z{PL}o*7W!MZUHsG^Sc|h3=`IVg(X_nABjW`NJ|H#q_ySP1+7PrLHTq?a#OROCgc`i zqPnFhe0nk&YKwK!a1DMKHU{AN2ce@-$bSz=LQ;4ui2fvg24XshMh}2^oCH@C@Jck= z45A1}BQ`TS-4yY<`{NqXhj=cIMxWw`1G`52oc0unLJ)6~VE>4|#EshFr#}g)&w*pzp!Kg#T^1mBFU7K1I@C&-`T(|Ocd=oUm;n=NOThOL!z zTH`$m5^KCClVIb$fdm`xqa@gPx07J=Ex=>Jnr}Z6Y`*hIu=#$E1e@4;FaG-{15O9EJCDZ%#1spB7abOFdyBoH^_JPZ>o|KKjXS|EU z{()791mHE26XR34rGFia#GX(1{sFj>2iVV6hz?*&upelaAS##Y`|g<&_QA<(;q)n8$*rsyo5!>tlmb{3W0?x zLK%*zwnY&)u)Yba+AyLdmdb;M*Wy4a z3D@I@dNqDVJoAfqi_KxD*67uvh&Jqm+yz%i=*A{Ocp8p~w|X>Dx_IsefxWxn+^Pwj ziHYL>3)YhePNy1_1*%evdLmq7w6Oj?8o_5LJ)!Jpx7sw`_WX$P?TZBpeQGS z3PQTrC&k7?v=Ik%hb!8O8Meh5Mf@07vl070#Xvi3Ya~Q9f$j)mkZ*0O3aHCdWfe^Z z&I{;~MCum6?#Ho?C-JA{E*GQ#tL_-fpWrI54APGwGJQR-mXRL~M?6>yEHmvVypKkA z{AgsyR_n>Fz=2YXBr;`DIOoMQ(kjCOFFq`c>iE$Z#E@Hs0~SURX`wKk_hObmGd&wb zPy(hWr#c@EG8Oi8b0wjPW=ml5U2m>XqhUQqy_1%ihn~~kyE~0Z(Z~p_z2N2w?jyUo z*!qH-E4brAH&+r-Uv+b_wXybCb41o0Z!{P7bQ2XpF(_W@W}&D82W}QZ)@_l5hzZ!_ zMgpe>be*?F5^-e~AKVrj0^QVY!St*U*sAkZV0=vwUuW~LyUAN?w|1Xy^2}w|#*KDu z?K`t^tCT~K!~)aq+T5g-YHrk;hhtB-MW}T9cw3}OopoEVurVBbn-FcP);m23G8Hi6 z&IV6-&d5oG)9^Nfl(5psNrVdmDS@VTy*UD7q$(-f!8hJLL7OxW0!d?Px0EUC;Lkr`6*H8X+Zly zMbU_bv}lqOG3&c=;AKX53`f+fO}~&`(YS-_Qbb;kgU=5lv!>jIkZx=_gv_0{zKib! zf;wnEgz-4=@=usU?$khzUkg;7iUS*q5`yzcJ#`p6Ifx}ZY~%z2%a3OfAxJX;l!bKR zmU#;xxey1RCB)!F(htIrZj2|b6QS5bDBf(H4Jm95BL=pX1d8|#>BgAvS{%?FL6k0U zKnv8Jii4GQ2Jqs59!aEb0XApF+s*Ff^z+K)P~a`&yVHJxwsB36ehiW6>v>Cdc|~6c zxy~>36r+rJrk_vb_~t>$MiObQFkBkE-_tK$re_05zqHBy7zfgiA}YNrO-<%Yo9S8R z^h=xE%{Y*L43X&@q|YWJcb?4`IB?Gpf+xh0gq}F^@CwxJL$(G-eo7R&eQ4!lv$E&M z6Lt6DxwsR_rXqiA4^3cEqTb2rd#?=y9D}jah%<~%H?4NyhX?VaiHc7(r&nMLC?wF+%Y4h@T31)&qj&1>DrSd8fg96n`Gx)&zIk*T~ zY8%9JKn~sEPJ!vW1hQeoApL1B+BOK_v^ZS_LzF&Q%|K#-5r#%y3?(boU}%}!cvQ6NZ&)`>{Ac!AtLis*EcAg-JI#W zh!%L+({~ZMBXQvTM-geEFkNbUIHc3_DH*Ziq$~EVj5bM@cN@{UYxKk}(ZJa)~x7($qcK{MEtT&Wv$vq^SeafI(>Lh zLtUaxx`b;ex`Y)}-W4X&Idwd!d-sEoJ9FudLMe~A(bxQB^rvTZ=^8z`ixsphirS}r zr?x0yyL9qB7W6@wsn;jEvo-uIoux4BcN_lmWBFK6wQA9v7#;151~rj|Is4`=?& zMPW8$L)n@!OKRz;v%3Wmsf82f2v5c1ZHW%d?z#e_j;&@hO>>Eb)^_Z=(Bvf3J3pO|MBvFO~QwZu;u>FHSFb`u404D8Som zck2WA66@a}u`+_MaE(K6xv)GLlJjLZph0qF;@sTxa?X#hid_)BFmf@3UuSIr7aL#= zLdLz`#e`XR{O(pE@OJ!`Z_J814Ti~q&m60`B2>>LgN}*kwFZqEM#nb@*?Np)XpbX- zV^4bQ^e_$P>MhWo>&#H#xrnLduM}oX+V1XFV-?(%XX1 zS=|~iMG&0cYOvvan|FqvB|bheUnEK8djn{f2Ba5lk@oi|@8Z~#4%>Uk+Zu>6}?)6m2jHgvTT2&4Gyo*9pC*`dHS4w>=p>EY7zj!TCqhKk{^FKZq$ z(-&Kt!;>Il#-SiZaT z2~+O+SueA!*Vr!U(p@CJ$#^eu4^mF3a<5X>EPbT;-sawlY>!0NKauxc1UGV9A_~Um zIpy7jy@i8?BZcFH#|dW&PY|9gJVSV{aGmftL^gQ7u!YhT>34biSOZb5BS>cO9 z+oKQmY!4scdy?CpeBdz@viypLErtB&K$gSy;6wRGkOwXieo4$l8^tY2%q2p!Zf{WTM?(D@gd2oE7uw#SDEDLJ@gRLt z_^jgpBz#BsJ`wtV7td=$-u9qFK1Jg3`QGwvM}*yjgojE#P&iUJPVp0j$4PE`&B1Ps zc-vzR{Mq6!654;`LjEK1bRyz;-yyWUX-J|mCo z!@z5W%VucLA@F<#Ql1o+3J(@`74{bn7TWU%>BfqmE}SKtFFZ-OTxicBq&r{yMZ&eh z%Z0ZHZx=o;d|J3gXwMXi3gzpPK7IH@1+A5zb(5G_>v8mA3c!1~hEae9YIUP&h zreA@aiX=ZwI7(>KlaNmmKUX+kSSws6JX6T^wY10g6OqF%B3&AZ*9mVE{zUk5;l0AA zgqwtJ57w8(zbSl2_>s`ok{};C;W9r?-Vy0HN!(A^TG&?DS!jDULyzv2)E_JyB^)O_ zTIlv>r57gkPZfS&xJG!D@JB*AX;S}Qp{;2F|BQHUpT+p!3)$x-|Cun4&tvem_668P zJU7guoGzb4+dCCFO#CPz9VYo4=f+sXxx)EEx=>PnmT;BudqO(JG5&fXedEagM0k(z zJ|P`28SnN;{k?d%N9t?hxqlq>_+P@r4}>v3pTT3NIKvX5y>B4rzGRGdd!h~$KSVf2 zSS>tWI9s?-xLA0O@O&YiL22LKKfvq6+uqdR=_AVcUkV=<+It9cd;b78OTJb3n(%Gm zdqQ+|&7SRLjdbvqGak-whDl+mu#>P%*iSe}XzwN187rP{sw}VVc?w)Aez}m|tBk)~ zXzw5JKNfHAAMm!9DezgzHw*tL{2$?4!tFx3z|ww^Fexk*+TNsyx4lV$^o`|vph`GN z==LC`qb%bW3GICY{&evxg{y>@2-gX(7G5K~NqC!(uD7)RknnNg)50x6_nvx1{8r)X z!fisg=ctc!quqqCKv*nnCUkp{wh{04Anh#P?LpdGyxVhhw0O7Y=+WYj7tR(g5H1qZ zb(rN^CA>tqPI$HO8sSaC+k_j1cMIF~_>Q-$XU&lg@ITqnFic#DvGFEIUG!bgQq z2!A7dPWa!#KMCno&GhdJKN0?2NM~!tb1eq3nQ(t$8(}+PXJNUppKy?Hq;RZoqHwa1 zuH4M0Mz~CPnvfpej9)FhQussRjlx@nbOfjV1H#9IPYO2+Ul7t?oceDF-xGc){9MQ( zJ@x2TPHZJC6IKZO2>S`?eNO$!LOP+7uMwUhJX?67@M0l-)v3Qx_$%Qf!l#A55z?id z`tJ$95JvI?c|BnRA${Db-$mF%c!;o{aFDQCc$AQ?@l0PUJXLt6@I2v#LVD0s|61WK z!rO&+3hxm zDRR<2;|C~m?mp>a#d8!VDo#EszCZDirW=;D$;|2@%Jn4Q+z`4dBv9$>F7ZDFBF6LMol`bn5>whh}+`7buH{Z z`abYE5%-K@J~tzMesSYk*ZiKv=i{DA=MW)RsPu3m#w|i`Pq-+>`Or3S<+rq!953c%EeV{6SO>TYQ*;R#C76uAe7rs$% zl^v|NrnQ{=7W_<~LTEoY&(>QdDbwDl4w8%^xxX*4h03!)Bq#_ekHKOMSB8B?WbFcEk0y-4RFcj+woC<3EEy z91$cZ%O}G~Plj;;8`A`?lzh={P^>fbIL_~0=&ezn{+0C|`Rn}P@fm%x`}EC*|KTdT znUx$vj}r$Tx1GZ+&`@!t<1|eMF9~`uYmwuh`F#^>?PX7|s8}-Z!lf0nbS*Wrh2(;H z3upcCUoNLFnZ9ri4Ez&^_l=uqGUPy9`>UZkV{yzA2yEIbxPeh>LBIreqD zPL_EVDA(B|fS$d4UzpMD5V3^;Jv_NHL1T!B991X~^MN7H;uYgnBF%3~o(_T*zja*0 zfF54lDA0a;TVO8(Jlez16tOo2VNVA^YY-~T|4V`wx3H013FI=Upa=8DV?IuQx(^`T zWbl|S9!nzW^0OQ2FLLl(_T>>OnkT03T|-6>M`e5h#859bSueEDH2wAlB3=5ZdWTmI zk3JbRAZ27I?GLJmLUaXakINX-?V2wnN6W7h+m5&}L{>Buv za--3x2V3qr3zSEi%PaBc7~jA$6)RijoWR74mmDi=<_UcKUej0~s|c9|m0=#$EcZ5+ zDS+azE-?0)d!rYR2Iuj6=k+=HJrLX+x!IZjxj8xg`{VAH+b6e=;e7u+Fu8*iJaP|A z#V<&>_ciTRmwdza-G8ZjW>=f4U{2clnCi7fZL8K4jXnIP{R}2!H(M85-DXGZ&CP1V z>*EVUNA_7gikjPf3!U}3kcn+G_7f|yZOwD_!M(wpHiehjV-G)_@LYZJ&gbgGRnOI@ zta`gXyvn(`y3X2FQfJ3E$C?E%V$}h=_U-!Qy=w~FwP{~y9|^`Ctg~u1VoihBaBf97 zeq%qkTYRM(lQzJ;zI&N_=b$n-P@3!BRvFk4w`r++U2#9GW>8RP7l#Vhz+Oz7m+S1c zo9e7Vuhv=JtLm(@x9byEtw#)2=O`WI7VRo?KZqabzB_-hJ7j*~NHD&t@J+0xfK?>c z_IJA!a}|w2?zH*2u9Mc!omV=*%^I}ay|w!QcV=al+r4@Tf!GvY6C zpTgQ6yXH@Gcg5$p1>G0B?+sewUYWMUeYAUDH!H2LI}rTyHP;#{}mu6}M& z=@K`yW`NseeqVP6aCT*do3-{5cPDZ+J?#?roysNdh26{DPJ`wYUWFR#=XPHEG|JN7 zogM!uY6UBb#6N}d*_*Gdvui5cnXo^rbQ$dJN68;US>jNyr|o?bCA$$+KFWSIY8~r5 z%>QE@9Mf+O?ZCPdmA@(2i<&7dJg@Nl!pVhaf6?og&3HX_;#yV3_P(nq|I-hye7in% zZ+J`W&51`wg=QA@EG$T$R+LdVy~r-Su`qCCSm2DJz1G;n&nC7gOvQDcyf#W2h`vQqao{UXA@|d&Ny1%gH#^zNqTU*`SddqY51NWxwc)Nb?-hOz( zinD`#f&*Hti`)1da^7@(;^x$vw5@47(r#{vJk8zPe9K?0W`)7NoeR%`bd&0Yb>WRE z8)7!0ZS76l+M=e-wq}KieeKS%>yoR38xyw1*Tiizc@NzjTZu~z zil3`UwEjUk z?w#Fp-K^3wHwLX`b!i_rvvR51xpJ}lINEquw2+x;So)$ED}2UNR3Wi0nkGdnbO0dwp82J8SI{cW!Zicjur!?rGhZfnNc+a`y?y z&8z8)^=Z1hvBeABuIL$0q0F62=cDcIs0*NnS@GrW>OsBTj-@@&v$C;r&PDDmsE0XN z*CtqcG3utH+qt;68(urz&Fp?LbO*ZA(Nk7eEt3ta6c^W5O6roa0b$`wSprp3Qf_|DK(=rQLP#-c}EhpRHVun;Zk@j9z} z0M{35z7$U>EJ7T5T1{!8jox`Bu3MIQW(%X?Kdj?28XRnabH70NP6A)$aI^2kaF-I{#L7=) z!O(a{q>?po9{&epzkz)$-ohI>7H`=Lh%Vmp4k)LN|N0N*|JV7iKxQKZV}~P8Sg|Ed z^n+YC1uM4HKqACPvdD@pe*h5^d=39&84TNez_rb6GyeX{!;a%GN%l=oBRmLa9Dks) ze{v&&b4c=;!~W?3{9i*dj#W~{*x%rcpEn)rm8_?uKZ1B+@Pd7#!Mtd&Uo_Z18XTa( zgn6)4OvL@7H zLLqxX@yDfv3Z%D%>2bG}gbJi56n`*EC`a5@#@!$k;)J?eDC9+`5H4jxIr1XZc%hIN zp)MB+c@gSWp^z7$evId@gmUCXs9%%f@-sC|kE?$qlp#H#xFK0W8PXH#BB79;P%n_0 zu?V8usCdkfkQFix&-RFgu#oKxiQEavkK>3%_Jka2NaRn*^9+d$3VAWf@_9&TI}^In zkVr_#jfO-*LjK&4NJz+s4T*$=e9@3dNJxI$hGirqWDC3xBn}yfs@TE46Xfj-t-hJv zIjKd0lhih8B3_Bd*~zG)K$ew|a2A;8oVq>*Hf({8@?ki1%5^Iu>oX+y)`>tri>^t* zRU+d3t5PIH3C1Nx$#n0P0L=rhAI1|GSztJW$au%P{2d8!1ORaWZ9aN5M-c9mgij@Y z-G-G6sPKlBQBm_90M3!=;4z*~uMJ&n83V65f?C_+x3=XZ*2YtqlZqT`-To{73bU%Y z{|a9|_Fn-hIlAEgOq|?&g}4XBf$IHNFz^aaIKvTMGA8f8;!O0p?l5axQ>Fn{nc#<- zkZn!!C3Aly8Rm-SZL5@^*7jcE=^@Fz{tWJoX!7O7)PqzM^9v({djR~(sUL`#Sej@oVAuun(hZQ+?;(sy94)?BnI*46h!bQYN6CPED>PQWWOd&DL zgvXo-tTN#t#u`_Fi8!1Mp*@+KVO0$!(q_DM?3`}mG?rOQTIOEBwT!qEXF3+vfJ3QB zq>GE@GV!8IKQei&_NX@(NZ zjNV93?<~ksp0dPJ6D}Y!hl%(ogB(h>G9^dfz#^n07FY*Mj8-v`7XfH#47zX=bf-diS(0#BB?TyNsX5}!8V(Ui?GX^iq@8PAoMV0SFzWzScu zYKRxlT4FvCUr5yaN)6v-Yz_70x7gET9%&nTMMTvb!>ggST0oR}Z>S%ijWM1L$}TWz z6ccYZVLleg;fv2_{Ea4l3~?{c9Jrz5YRDzYyo5nnSs^oX3B$6OL8de&bG{c?*>9xMP9L2PZt!O#ZYkf5txyoL7qCG5Kdf0rE)^H+ce5OTupuc}*O8;W~sd}N2 zismU=$qnmuwn=j&k)??@E4dsi(bDZR@gr!d5GPvD2%;%z^fETIYHBKaDNId0p=m{P z6}{e3eYV3@CZ%ECl^{>%Y@!bm*{0z5I-#4mc6%)h+cN!gEer;t4zWx_?M{i>-2g7i zJch_J|MO`~X_Q69Q&&*Qa`U5sK^vJBlcO@tL`J-xB^yqK$>YTang~c{L`Genokb=($v}An zYNnyu2^g(85*9PqfR3pPKl%@j%n`1*YQvS84E5f2mK(}sr(v9w$>?a_6O8aB0w&Q` zhBYfgj2gdfN6ToEb`}^BmAuGMsRrg5J(G2@Xv{7&(I#7Rd7>WaLZ0lOWVi=2BGnsF;MJ4Jzsi5BF~>JNOs^kj%+Hf1`>nia zE4k<=iJIQwbd*S6bC@g)r-y+H4P+RYE?`=#vc?I^_~~aGDb?|{LNPBg5^^pOL6hgK zs7=Y8SeI)gH7li)kTXRj#X_{q#)#IuX;%GNKB;u636YgDM{E9Mv0_*fHl=AT$%!#% zw1l1R1{$=`Xr@I?vM)(GrfoW7{kmdbG9!7Dd`Pw=9m#@_B4R3QndnOuh>j!^)s|+D z?I&62!Tcvt(U8+d^c!)b@nTL!wcMOQ*B0TFQoQ}!cGRIe>N8Hia^s3F`_TEk(q)kW z`Atp-cl_vHF>A@}1uJA@MB}(EhG-+|HvX^7B@i>Zd0@olT^1PdZ-p7nbwq|q(>q-< ze*#y$>rb)<0rw2y7M!CO&73!T-mE2NQ@{Vw%MD1~HK-u1Ze4xhyQhkrcz=(qBTzPe z$qeg1*Iz&1_x#4kw-fyDZ?FrJriDsUL*rV7CZvQWH4jZr4wWW_rX+?gh##CJpTqu{ z`77dzFHVc*aj9XC`j2k^oet1_)~-bz;m-4UGblvBJs>F$9Ku~L@agi zg;Ng7`5(uXKs${oCcC=)~KiZ-cp$4evUK3E5{~p`SV11F@x|_@6gX|8sNzj%$qX ztH|G6Ne@;mQXH?yPc4k+XC2}K#d5_;#WjjIDQ;1`L-8KPUn}lWd_?hW#lI3!Cm$+) zOiaMf5*q)F(l#0#^OHbCe6rH~&P|%Xoio0h(yJBURs2Np?~44fm3rbA3GAwLKSgf* z!Fcg|1j?RVz>AeH{*IupS9-JJ9g5A0VBo zD4(@JcUHQaqO>#c&r*7*;s`~4?53SbigOe%Qe2|AOi|h!H}IRXy#re-wpHw;DE$!ey_N2(c!uKHio+B~Dss96 z?Mgod&Qbaz#d5_<6t7dfL9tp<`Z4r9|Kx|2|3}5A6kk+)Rgn`knEpqKM-`7L{$0^# zKZ9JHViQG9=^($OVmHNJiv1K%SCn-sATQ$qkdr{DKSS{%#YKvjC|;^~wc>S(oHj!J zZHl)k{!Hd3ObfwgirA1tXjx|i;f_k5ttjhjAk1kt)IV2os^SbqPP}3Km5SFZ z-lSNoc$?zgin6W-!jCHbM@3HEp}jX0KT@nyJf`@SVjDc0Q@)+z*^07W2Kb!(!}#fn z^As;uyj<~0#p@MsQrxJxRgu$&XzzE5Pbog9DE`QZe?w_bFrxgIikxCZIzdtVjzNpx zF;Mnb1B$;fkdu%ozew?N#VZxBSG-A))08Oxvf_U!zOTr6ON{?YkrS6lH&NuwCDI)g z#jh8%`1JxgcZu;M6ghc`^p6!edx`X7MNVHLeT^dLFOlA=$O%lOf1$`3Or#%GSzczGT$nBqyTy>jH5ZWG=q+x3`zUGBbLTH(%_pNCn-FCpK3 z-Jzwk;0-Vfvy5lCKP&C*#+G&g-32p>yI_Ay?3f9i+c8i6kEMB-JdJ0wLxz`k@7GlOXu7^Dz{P}?md2TG`asRP&fP3|za`%qn7H;w$ z?9KTQYXVY(s&I8f+c9&0cerYq8-gt5J{T0UF?NGf73$Ce`+3G~>FWj%Gpu+OG%DOD zibrC1PxvEXw)2zS$Az1&&vWM#!((H2h5JEqaQiaMgYJX9MzMpag)2QjsVa7Riklp7 zA5Bh3%`L1CC-lR0dal0b?nKNd|*)QhVXW0-MDa%!pCv# znyj}z8FJ-YMQ_(Q7nntP50W6muq zsSA`&K$}84nvZ(q%=${quwVNkN{xB_-K`zV-8*WQyYH_(-Mtob#JgfQ&TD{k))qn& zEl>PEc-1jSea|KC9cX1myEu0nbL@*#(HqiH`|t!v!+ibHHfU{=P(v+n=D1lkIqpo% zu@4nv?mAlKYRu7}l{TCu#fdrp#RI@Q!@Y11yg1+$a_6oQuu%$r8d}#!TnRrEXV;l-kEeUMS$pQoxq4T3H@GVu*R(Ti&2n!qEx@&1>aHz4!+pHC z(tT#v>1g4XxbM-|Wmh6>bC&t*byn#L_lX*$k#>puSmkE$2Dk;4D{%D&xEEGVci*q+ zinf%6-rLm;Vb1$C*n_om<>|0VkCr*^9i`LVYtnE{_Y895Y8Jcir&)D@8VmJ;w)NmZ z>^D2m-Piq(sEtV%8;YO)qR$xUDc1{zd!jqzwW1mmsDpaa|1N;G;cZyt7IJ+npWk zduR=U zU!b+jK`*!#y9rwu1FxIk74<&by#u=h-%)u9uHQ2B23%Qs1XafG*nrV&{@kF9XTdG= z=XNYI;gByJ)^Ib7a`BN-&f+*X%jM}yugmB;;K0~7@_T-KU{%jgUL1(sXEBcc zgHj(K7+&g&WEg(GpM-Dg7q_uXxQ zJ0SN-c7UvjuBesP7{fR^eSDBEMN3rftmx*hQAk{QT0=MN9~kZkhV2@yTyWv4R#Nc=68m$~QuBs>hBUu2+J@!}U8}ZHx+${Q z>NXhC_%lg6(fH-0UyH_XC;e8G{wwH~6_=pChSp; zxaNlL54shqT$ORj zyCewTi5M&CaTVZ-os9)nQQ&|I3_FRyY6v8=*+rTv?T0SEXXSh2Mgz@CaIX{7;%{sNY?()_?XkjO)SPX!C@G{BFx*OTT7)OLZ;hd{SMD=rMM z726Y7J0?67KV!5iWrYk4@H+jDbZfA`R1Xdt=8lpL=IZvX` z0S~1KT!NS~#PB1-aEU3QblMZ(J%+5&Mnn=lb{1r0SJ}4qT8P*^ZJVm;?|?|ZmH*h{ zC4~DBVU zb{S%MEd%!&;<8!>_#*(EdkB0w5p}TT;D?p=IBn~E0>AeoQHj!+yMU0IWnw>w?h%)F2orFuc7K-bt1!+IOBz` z8Vp{T^t(8dBfP4j>R{Ed>L9r;&LpE9^!ViQx0QISI_&XCv!24rtLF8VgZ8h$2`dG# zI|OGj(hZXL1Wu&u<5!KW4wC!kNn^$quMbn@y@-n@=B3<%G_wn*7c_DRH zBPr4a4WwX74(9wSoG8&4SR9RWEK5Y*OE^&?AHQl;b&y=%*ClrwxNJkr@- zx?&eXa?t+MIAMP%WD9W)$2p=pNbd7E#lDYE9?K?IN@YoNxJK?_1^Ubn(j|{qFww`4 zUPWq+!%0sC;(Q4&VGovr@x>-y_M6jqcG^fh+X#Fgip^fVq?Q5SEsKn`5mqz#5quh55 zUGa#+X!R_r*E~;x;BSM`gX0j!Ai}$_0#}DED;eNZ0E8PlO|}x@a|lV24Lox&z-oo& znw1Q2Ep}|exxAKv{=89J6A1Hh3jbP|W)iW~i0Krr_0o&AE;kI=mm>rJ`Kku5PNDH{ zIZn;!27gAQzM?*fRep(8D^Fr$wO?X&1BvwzN6ip4!79ISRRdu*6_f{0Sb6ESBtAvq zu{SE=EGhU3Y^RI>R}co@pOxW87Y|?1CBa&RYp5r~dyQdDB=C8Vw<%)0m|hyLWnc`> z7(}p28D>%x^bTGrdaq#TSi&TnvWqwabj$?bFUquVQSXYB(|4t}%at}|Irk(=JALsN zc=25j;Jp-;O3)Ux%HM+OuVAYAQg`DBtUqkyzPy%!O3CCnwx4^Yc~*pL8PLX5e?_Cl zWEfuZ0}(jOBu~)fSNoH{aV2fvFSfD0IsNfRFg)9AbH4VXwyVT8J)>~%C73G5 z#@Y`0l%tVH>P+_=~E_7ZjV;;xZzELdv?6C29I(9G5glu(~GW&5RHV~m4 z6M2yQN-Sd*;zWKM#F~LL9b2uN{8DBKPUN?NTyY5p+m$#_@mO;}=WfzR8U)Et{P zba~Un&8|93nwwVWjg&V)JQmO{xiO{=&5cp{H*`{JYm8rt zb#79mEmAk*gsst@6bC{xUab543I-P7w5^E*))R*2sG~lWpbrD)_2pX=&HzM?9E33R z5?FYwR6r;-T*4m=m#|lYC4~JFJeNSLuz>%OqYpwD+z7^~>;^u?a0$lfd4zq2OE5;y ziyDo*njlhEM#L>Y4?!B`JJh&ZhNj{~1c3%k1Veu`5d_*a5mD>oz>6IH5yGvG;8`E< zvp(K$eSB@y`gp(f@wHLwk-O%#Fu4IISBD^O!inq>9>9tF*veW4XcK%|IDnJl#Mgv9 ziSQ0i$6B_smVpm(;&I>$z_&Ol4v>Q>(we^!dbz+;1~ai8CvNkX)iPkRQC=arXPOS& zsU`7ugjl*ljg4sSIKNnF%sq`YHj)34{C5uji6KOPiUqieOV2wu;NQpik$`<( z2PY%LnTBnKxs@^h$}^m)*`0pmw9V+(wl6#=5pZT_I~_B6IZcYwxj}PMwo{J%gtMKB zV*DT5-Wi`wBiQkHSvJbvCDS=S1M)qv*Kj{Ac!1%-AFOZJhHB+WX$KByqG{UVoEMFYa+XMzEE(Hmy{%R=qOY`OFGr+80kBgYLzx zzY{W?bFqVWw3B6{;i5y#)~*wm4TtfL+0M9(Ub(2yTLqZGXdJI zvvYdofSjG(%Sp?|zUng&XqTOv)4OM1>=NE*+1$A!8;%A0;254hvJ;bU`r7=no%xej zV7-GMm7aACvmH|*|3~rv9R6GBEIM*`{u-G~ckWKN!O^1X0HAMx(RGQQ(xEgLm!;hc)O-{Bt|^(Jnxf4H~r z^mn>BmJMBqEUMe7@gnxNIX63qM|_GS0jl)1_&?9*XdK-S{d=5O&0YHc5x?Y$FUfmgO!3)-72Y6&l|vD?*!EAo78b=H#dS<>3sO!`>x zUSEKYfd3|p=7VsaG1b>n=Vx(Xj&y+r+p3r4mg_|!=34U>F2noeupvVRWt_%KGGWo8 z1?3sD7cI%as`ME{FTQZr%$c)hW|S;hG-FnI`JyG|-7@mB2WIDG^vTK1%Nfw8U&d)m zW-XXCy?j=;jPs$=dzPy7%9}c{*M(S-e#YF4C9{^zE1$P$VMd?azPWh=erydMh=*_8 zmLMC!lWa@SJeXp)v|Br=b{jj*ZtJAm?J>yl3yFVka=wmv2cO{!lCoCET@$`G_PUrg zq3eTdog1**ctKKOsH9nFT+`5mCZS0QB}v0ArtckmC-@G%QK6C+p>fSZ6Pku5H3>~l z7@UL;)ft{5kna%%|9|&4M+KVg%p;eq;i%PcTXShXo`7j8ClUA`u;uyxEx+p=TvIe9 zdPx^2{;ZK)J5=5P_)B_+CwChd{&Eze^OnIT(`|y&OZT@3 zdpZbO6FNkFt4Vut_aW@JcYl#(Wq?O}Oy0Bi6vCbkg4Sx-%V0ncFOHvJ{PtdfJ+>j* zYlhRa_a}rs9R#i0Vee|xwRd=NuY=*Y7aV4Opr^eSI6ZrZ5T*{(;?cFM@wqaTiDUey zIQ??hc0alQ_}7rbJAIj_|0U#3_XxE?k~8IK&pUE@G+ZBm`QwoQA%8j2Q4X(OQW5W! zgLQ;-BgaA5OZO$<1&Q)~K_xHC#Sd{{rh{&UllGEvGEKj|o@l4hADkNI9ioxLONWeq zhyOV95Jsk0V@zcBl(ZhjvJUOgWj-B)`?-h-fvZ0$uJnz5UKmEr_^Pbuq<)7b3 zKKh_!o_w<^ybU)R+!D=`{&zm7pKy;gx6lZiH%<}_cl=;h?m{`@TU#;*r9F_p#0jnV ztRjCNV|;(;FrHtW<53w4h-v1Nb3Ce(SNwnTzU?KbPx?`vOAKM%5yh!Q4D5>)#eWzy zXD5@tjtD*R9|pZs>0KKCOQmK1V#NPJ>HQl2n&Mv-KUL)5Li@6qJdn%YlkTC&y?sc_ z((^#B)j@iu;u6J`imQnz*A7MT*G0acBOQzNH5A2P7j`}*4g69ugh7lne@16{#Sb4e zSCS;{?GxW!Y4OKJ{2--=57S-l%wo;%^imR}}wR zr1P%QM-@3BGySHD;x`Mrx6*k;q;s~?{P~nL=QC4pg3{tA3wox~i!@$-j068BrDa7> z(BcORd{Fs+P`zgq4=TP-#C3?lH6nIZ9Iki~5&0=6;-+$m;-y5`=YrEjZ(sOZNkje@ z%D+$Phn0R^QTBs}+##huR=F>g{)UM3+G2np_EQ|8xPS#oc+&u zZ`|SpDAMy4=>b6ca>eTvZ&KW$c#Goi6dzK2LGfk9_Y@B)(x-s-y?xbNa=ZZDMzQfa z1tXL{T5*P=w;sWzO3SzfJ3m$0TYumdrSDMujiR?60lgZS{>zGo6ptu+>kEW9E-;^p z-ueRGdIGYp2;%7%K{;YchFU2zyWn2Sa#xtPj|36*hXDQNSgZe8JuT%8={prNP z_*zAo@Bn(3(sak*`1OdQ`1gaB@ecU1@?TecNAa(U^xdHTSBhM^h;&e~iK46z0Dh*@ zoXt3%}}7K)tDPrAKgSH&KRbWdS?zT#-b za}*~lPEq6(e#*=G13HYs{jlQGiq9+3!H4-d zr06Pss`$0yKNQ1wHKTl@VoSv~id_`DE7D_#@DAKXlM9DgCbE2a0^brhHJ5YyOe$saT*` zq&Qn~zTy>%S1GPn+@!c$@qWdFif<{>r;6!)s~8_|=p;qiXB_dFO3QxZpk=>tV7~GT z6(=alzT=3O{l^ly*pD4Xv@m9q<74KD) zea9icPw6KVpI3ZI@l8e9cO3E`D1BJ*xZ<~piFklzev=jHwnjQjv5#VZMcHp0@v`4I zaI*4cpK;K1Y@>deqUc;p@inWTjDeh9dSCNiod@g@X@fpPz6zOHg`1ceK zE4qru6u(mBry9x!6%!PjDz;KgQ|zeNS&?pR)E}sLw&D=QVnuHs@`*~Hr#MYQxvBu&QrWtu|jdV;wr_}iZ>|! zRB?;qcE#Hif2R05#fKE1QG7x1HN`g--%~uK_=)1@ihozM@v)obj8{xjY^m5rF;lUN zA|3~1J-!C-m*_tk0fB>f}#hx6w*NNeXBK}zhS2nPVyxlAH2Qy z*HM%QU7~i@D1D>a>7AE1Aj5Zj?>anv`wYYqJvhF9Z`}LwtsX~YZ``)X71lOrx^s8C zs^Q`Eb?w);sZOo3J~`vcw4!!f+ih!)-AgO>jy=3LE|@#A@FnZHkJ9e$ux?FJ>-D>e zT2)W35B8i=AD8ncc8Y(qKA1l)`TXP;Q%58ZuMehUr+8~}eO&TuY1lWn!0Pnm*D;;) zlSd>EO&fdoy-NethWp2_V>|t&b)cr%W~-~U*p>+XZEU{jm7=8DWb6Yw zZRh3>Ehp42STvzNA!lNJFmYe%xa6Uzmx=WWWz*;G)za_(+UoRt+hFw@txdW2qc%e8 z-e?`S&gvMfiC>pcZLbfbx%G~eTDx!0!f^kG z3Yu3ZZAjj<^F{1nyE|>m*ux{8{4na`w6v-=)%F`H+b%zpQrltM^6;5O?P|sz4yOGV zcD^l4*o&Li`1;_pttThqDh#O)PMI{f-Q*{aB*w-Z2_-IVyAOLJw@PhY(ynA&yzJKX&hJ7%z@_F_v-Lrc9u zT59sf?4o7i)J;ncq-{->mfC8=Q@Bq1;>RAwvrCsY>r$kJHpL#SDYfeg&_ZLzzR_w+ zRgtfqF8H)TJN+W<>9%N@`Bq1?Gy9p=!F3)LutU|Lx5QOjovdoR3cC`oLz(UP>Z`tv z?{rn#bd-Gh+@@%!@zOS*hCWN4d~-}S+b!Gd?!xC=H`&zmX0}<=VvB~dy~b9ty|S(T z`e5^IDcf7!jNa*Mt0@~=ZQ6#mTDCi_7Au1#Txv}&VrzYloa)rt;2X)C&njAeD0O4+ zqW`W|+w?nIZF)_ruhm+Ql>O%F<-sDmM-!}XcH!KPYi_$f?f}1o8#Xm!x6Uk4~wgC6$(dgNa<&QjrC1#A_PKLL*CiP zFKb;U2q*SYfFs{T2h1iX7~%&m=M~BfTrQm0UsC1)az?KuCmb3N8SG@s-w>ipu6zgy zr!%#?=TPG&2K$d-uz;g9R5eh|_XLuf%`sky{KtGCH3S4nD`!g2770g@atf zGjtuo!PWNf0iiR&2wrbv)U{%Q{CO=V_$!2ClY^&+H-ilGt7-6zFqwf)R`@UA1o zInF+Y|MndGgToHwc-X&0AifWz?72*#7kKf^o;~kL{GUm30AuGfmN|@PiuOg!`-eCa z=2`Z_S_J6Z$Q^8j;OEwai7&!ewc?;mM12Aq0P-U|k5o z?_mk33nAVl!7BJ0mA()PD}xAiCZ6!53WQosidFCl3vxRtR)J9UpiC7A`7=DZnJN(S z2uP`dqme3*5UPN_rZ#^7gwr<8zG0Ab%1Rn<+2=4Y9vo92<5=RgAe-_*@HPXm%QSc2_7g#|fr`4Op$_J;7z`LhH{2zXe-TBga#4!-hMV4g_dd6%XI*c?TmAx?;pl1@O}zys zXf@fl8b&kUY8bK%25769oeQxRU9chs>dBwGGx5-l^ zPK=N*Plb?|1C=NXQ_)MR0990kQ@of{pwOF$QK49v%iJOA;kJ0a^$7l3n~`4xbQ9rGx`Gv6M&Dzn>-Y zT_;VUBp#-C>qFsouk>f#mqz4Dd9{KjG6?1(xl|kQT;IJiCbx6#ci72?jvSsHRtJrE zRpZ4^L*Qnda96tk(Hn3g$(~4tH_I67GV2m6y_Vq#IN^dwm@QE&;M$*F%doi|kv38W zd;7%Z#QCttrO9EQz-NdA?A9Bz)VkElj7hH@2yNcwW2|M?QdnbnGEVri5lV4}um@+E zm3bk83vqf`V%Vg6E|QX?2>-9biClVZ2X#F;hIO<7X8=2`68ZQe5k?Ik#}K$x6eq9+ znpSe2XCp)#oq|3qLC=atd3K23H3;x#cB(;O3*y35PfM3to^)X$+ zhUxlVKKu>xOejXWI|HVvOnw%@KjXx*Jee?%hm-A>Sc(%ppCgtTVSJSo^|DNaat=;v z5jl$mwRG1?2I_J81_9=t^2mKj8qBuG$*`AUFJJN2x}EHD%dJd470A)3r_+pF3QIUM*`H0)LQnCbF;Z z#)*D82stXo>2)lI+1b#G2o(}#`Z~j=)+3FAeZ59(P9p5a8H4V+7=4-HeK@&k_Ht_l z`g?Ad^xA1i)r>OZ2sh)5<%qyxhQzZt8w?ReNR-c=-Vnhs2OSI%1bVLP5K)F8?+#u` z7&h5G*$}~=ZW`HnUL(U5njFKLy%i@%3*zlKB?3i}gQLa0IMEE*fK78M^=#;n;Ik6+ ztej-DfNdmnIZpGehj222k%J8k&4Q36!3hLD*RfZX)H1|pMC1kkBL{7u?-MY`jur^U z!bCz>!zFme&JklhOa#H$jjRsU6D(%a3~>^WJ0nAE(LAW)Kkiii$>QY~=l^{h=JuJo zxNmOu3|y0c)q(hkWuNIZ&2SdOmF!F>=`}iqIe6;;4CO!Zp^JJ0i~HCxMs(%B3H+DO zf7~oGAl_yj7~%$$hSxqqiYbYekeKhx*faP~oI{0Fk7Rhak)OwZ;+{8%A<2N~JBuXV zX(k{Nl4>*sXHl_}n$f9U?&+Pd;iWSt+i8;lH@I+Vp4p2tj_!Rn{cmlWwNK~2F8nu< z|L8?+Gb#IA{-be23XcieOv|Ptoh_t@j3+5OkVfUAAxW(*MOap2K-7e1%4{2FXj?Ym zWaZdHoLL!8hy6}zw$mlU`=8--$#zOJIyqg7w?GKr81PT7gH#fC6%ELhi`LCq!Bi!h7s6J~w`;tMMOoVgiJ`fO)rv9o-(GpQJBkl3~rlJ4l>Bk=#(2Go;zkt@5D zp%MHi`D2X*viOg?qXtadsT7w@anp6mjQgf>^c_tZuW6Y!!>Towokf$K*4k29XT#aH zU$|?x&goKn=ToXtO-WVDKgko@hcP7i`~f{cI!@G?Sjr=pNqy6`@ryaQZcE-1O?#JJ zmEqVfRJ0C6R7huq5j6cr8U($+;kCVDzmu8mT#(`Y&yet$&h(6SolbYUocZ6_i~{&% z7HLB-S$1ao%=THsyY?B`3ohN#z_9c||GcT*=CT73`W`P$@znB0#HmxgOt!xs9Qs=`$)8Ezv8;YZ-B-{a2iTsVw^oN0L5iG2tM}0`Qh@T9a0q ze+T2nZ8zd^N+oedHM=hV=lYrQfzmtp#CL+v=MDDYq@A`re|mC!BK$5nzNUHypC|_> zC9e)%<6H}GRXk#ruei8k`h~!XB?jkuA#Sy6WzU>mG2P0(u)N%g`i-8neV!uPe_c=F zKk6HW{?j+`ZHxLvt>T@@9C?Z!=mWgf5e&-V>#`h;r{@HNokX;}wKG9R#iZu$RGr9$wr5 z(0+RhV2{^>_Apf@V($ZlJskwCNwD`a>e@TJxOc(u+uII%94Bb68BQ;MpCU{h@7j06 zx3V93jZxzmPk#r$-0XHI_xp^25Y)>cF30PTJKZCIw84XZ5?+{ea(jG>U_cMA>9m57 zza01b>IH6ak#ew1zHD1J!d_Qj0$z~l>kih(o$&n)OceW+exEmXwyc$q@ea?PM|>1JHU-1KFy(ULY@QOtb zM{3+pqcQsq2fO~F`A9qAeUg5k{gvkZusOdJuNcTFW`Kt(N{-#3vzf$@EVl3{PihDKwX^nqH z={J;qPigV4%6Iupd!;Oygfwe3J+}e^vS;BIN(B*aAZwY4L-C91s8ePkz}Y&Av_K zJ&nj8T8O{(SKOp{r{XTf zUn%}ZQTi3^JgW3liq9#&qIgj8L&c93KU4ftQTiF|h1iaP(%*p1l;&&&sV~JYirp1C z`-SmmDHbUfD>n956#r_-&(L`3x1bj)y;RZjV{GidxKZP`D&DGiry}RvFh36}KB_1? zNr5l@8u+5}4=PIk2LEHFKT-Tr@oU9I_8Z70E4Ef_tJq1gt748Ke_Ny8nTj$VfG$yb zg5vk>+brV*^e$6*{zOZ=YZUo=BkApm{B?yipZ$q4ZUAN606wPtCl#Mpd`VFjBZl0& zN_+b`*D3v#BIkn9KIbJ7lNDuNHE0=6fSJngqR4qgls`kUvH#^b<#WAX$~E@KT&(=1 zikt{VxiyM1?trdVdb{FI#k&;mQRK`i>OZQuU-4N*@i#~O>q?8?IcP4VOg&feQ$^0N z;y4|r*i2FUIKgkHbVo(by`p@7#UCjSRve)?T5+P{d5WB@Mg5BvD-@S2Ua5GEBA0fi z{CdS(6z@>vlIx7$t@wcA?-d_c+^_h8qUZO?>0#7Ar06Pss`!l}9?e89tcd;Ygl?hO zT9Gr%XwUQe?5FhUiUo>AilY_JQS|&irzkyBajxPbMe(~wI+aRap(uX$;ICJ@M)79F zpDEt0$a!zf?;jMOP<&dEQ{fo@XGKniBYj-a#)BW}kYbWzb4BsfM|=mRPgCrv$mw*{ z&sQ9#I8t%E;<<`573V6JDOM;!wpAilvGdD9%@0 zsJK*dh2m<(HHwY>K{+dt`MX>3KE>ZEdVZjfD&5#0^fl$bsmN)KwD&i~FBFd}+F=tP zQcPA%QA}6NP~_xCK0ggm6#r1r;vWj+R7l2)UnuYbrNu84^gN|6R=h;`H2?k}k02iY%?Z@zib zAIN*2l;=gz`Q$@xrpC`DLcVw2fSe595%CY|n~`B6%>Ue+oc{g$XJqv0H!!!4$bY|o zP?q^%63Rnbd~@{tgVyZ6p=d-nwko*Zt`4oUKB-#;PnfvSHtwWs7bO?Px7%vj+qlQ^ z*uz)H$8NK_jH?gcNbir>xnmE{4UIj#AlNH$_-A9nS&5@Q8C$ z{BS5V>Todl>hYBNjmNV-FQ^ZW>iTu~*s!ltKhH|c3Kkx2SvaNS<@(?%c$e%gsgE!F zXDv>d=C>Ea(_q zZG%G#ha7G_dTGCTOAu*c*D>gB|j^fQF!=ZSbcCF!d|rX2SVEd)u}~oie5VuSl^=PMfJa7 zI|!~XMoU0Dz)shPq#eXcJ4kC6+7^UQRLX9)g?~>w7>0Jx_21YI{Pw=19Y`w}k5&*< zjXLPD;*BkA1%bf&!UHkewpnZePIc@y8`pk~{bErSYWmb|pa5+k^LyGr0op+3Khp+k z##^D9#%*BNp+L>l!{ZX$9>Ctvt2QBLHwLY)>xv#4+T@KPMT3gk%uPM-#pB7x)*Vki zT3lE?w9T}3=kzW7?4Uhh&d~7DVEFKhUK z!d!zVFi1!Lts0oE4-YY#A8x!$f2~#&#>;&MwGJ~;UHI*2?fw6H) zCLv*_5#l$3P`r4&#QlSbcC^K}#(5Ls@r&Tq0nST^Kp68fOgN!}#q1<}E3q>q178`f zCdgnD(fW!?2trAMNuu*LxmKJM?~tZc2pyBsAzw-+Y*PBjq!cF$_~ZsmQe4%?sO1Kt z88l&|)>rse;#JJxQKQ9gv?hZ`qZyQ-$>3)ugR-PqH%;mNNJ`y&DVeZIsfS4^4l^jM zz~8i7=^#u7|K=-~2^%$&C#*Ml04b>RPz-`R?7Q%^kvth$k2((}vvt_>n8iw*$=o^G zI1jx}k{8^*h;>Vsq-JoK5r>~;B;YV3L@dlVgTssvT}Z%TMu;L3beJitg$2IjH(LmY z8KFKWH4i>RLQOH&Zm}U6D)g4B8c}%z{N#~a=dpn8>a*p$7$Y~IV`8( zJtUXHtRY>Jl@W3<#();LL5z#ab5ecG;mn~Gc;uPb6xIv_9zftH>? zs{!DQHi~S*RJx3c8(N_-DHnn@jf#^HD5s()&}tz#*BV8ZaSxPaO7HHmRAd>qQjukR zf{LDil<^It$TCuCA5*+<4Ha3&FR92fW})@8^aP}geEQZhK90bCD*pCSDzc1|5G!S@ zprR)rWn6C*Sw<>7OU2*u-BHT8n~E$WS5;~02}l_~21l=BA7rUNPW#V&c@Z z$m_@jSXz1lQpU%OBFji6>1Xf%nTouQuTha@{D_L4fRynYqsZ$x31=x&{E9DzQpTqE zHCM`*i$F_HK*~5294#Z2E}-JqB~<(ZK`zxIWvry4Cm?0~iBV)*od(I7RQv~*43aYb zf{HBTUMhM5QpT4>u{Fy`rMXnJ?8m6dLViF^7V;}ZKWw6=C(-IwaCR9@ruhm^enYi$ z?Zwn&>v@=(Y(0OWrY9k3ej%EvOp{uFreQW%mA)d3GmZ80Vric4~|<)HkaD00P&wj7lW>EKuRwj7oXxkN~e%X@HL z@%e}(2Ihxs4!8mQI?)y*v!Sjeg`wF{XE(!-6*4yeUSzK)ErYY6?;|avv!O%HF(;i@ zW-jVz0Z#ihJAuuISLSp?%9WXoK*RBQ1vt=r6H?TY@%f<5o*<3>Mrv~KdXSo)gf#kR zjVABj-uP?3Wv`^>v)~<}=3WH8rKTs*>L57H@WPBVc@OsnVEb+RL25d<(piX3`4W)> z5Qq-ZO%YXWG+9n>1h(t#&%AQ}n3`;XYpLl;NDJIyG+9n>2)2*gz1U>gxgVk?%lRQS zJqao2*G7}&^u}QOTYC;QShjJEayN7a4fca1jbU6<(y7Uma~GIo`hV_>x?F^r#FJzJpH?YI+h<&b>yH6=v*)g3{!lbJN5*Z55;(O83%smW@N7uJOCgIpXV$N%ULgh%91BwzD*(KztiX0 zNrHcJsB7Yg78wbivol?mL-a1DtFy$DNX)i{NQeqIiTXF=7xJj@Gk)&(`ztr_rcQ3? zP2CJyJ{RfcQ6m97$+Tz(CupiqPB>4pmlCpaTQH_&0;;Jw>Z?_ra$5UjLo7jYDcs)g)7`=6)1A@Cr@Ld+r#sX5ba#qm2vtg- z?yMi+)6G{cxLWRILx~(&2*KBiAkEM^hv1@i;IcP`C_md;mro&ngA>vOTBAtB5(2na zAo?6awgj=49h7iFayXGj=mvI9Ekj^K9<045B>#$#@~~ndyy???Sc?Uv2nq@pkw^_q@Z$3kVCLb*IU!~loJYNq#KGqotjtc) z@_4M=^hiehEH%j*I(6&dtb@BG%j*xI zu|{{|R2>F?i!;_Lho?4lNIZ@+9xk1p4oErj@t=vn*Vs!7o}ZU789wvD%haB?!|e6=^XzO`Y(&l&0&$`U&D5c{gWXP0`!F@R45=vmXlTD0I$IG#L&NB1NDSUpt42O^! z-0qoo(~+jI^Dz6W!{7m&C_ljzrh>X6T@yzmJ2hoHO&SrhnN zWYU?$#|plbp$mHNW&vd8AXvsKe78(Dg9#XtBOm{b)pJjS;1!}j&g=W|-z|yx1ia%o z>DU{!aIVoeS9=qP5EdfH?=1W6(x8(0P-GrM=(LFCD=xDe!tw|pJ##ATnY;{vD{$gc zJPUZ<1X$%`7+Etv4E>S5b^H9a0c;Hh@bFM!Dn>5CJ+uIp05eSk0pHh6e9J=he+h;i4dOJ2*+_E zdN`5d=5>G}*C-Ar(#VM~3W;K796?hr@ugnkOT7dlks}=;eI@u5LG!fF&|gi8lYNSl zJ*_YT{c(QZlRwLW4xI&4-ErF1d4ysK%8EnFO>hr@O%OeX@TLUEc`5sb1R6|7EE6W) zD3a&h37`$KiOjoi^kZ>qBzoP1?LdlS=pkq+Cq&bV+~4z|wI1j9y$&!>zGr{Wl8*%e zIaqDqakW_(+}Umh+>Votz?Z$@GjzGr@3Pqf885X{Gk4Dp6)tWA14qCW9s1UVM@p2+f{YShnV zr>~S)Uq_DI%e;q7-!nY*lspr9OjDoXryqv_Xj=0vjhb=QHq&>*%FNO@gH=d zkS{qX%zXRqo4%SeGQQtDPW2|}7j9(of8;Z~HYxAQ`C80>!!!JMC(dVhZLZO*McU~8 zNUX1^M;;HNv5{M(uUOI8b5COVSyxb-33Oc#HN&(;#~idXbk7S<8hr&SQDq)_21utC1pEjT9-Noz$~64y-9S zPaMx0OZXp3eFK#zM%Jkfc@lm@rO=v&6C*2O2~K}B4Vp4U9>t@qNPSS#NJTDUloe5o zvLcEn8L6Itty7QUo`nCp`9^E6KFB(?q5qG)GXbokI@|xuottnILI{h1%5q8AmyiSq zpbIy=^x}+}k z|2$`&xp$JFQvZJaKKn5+`JMNi_q^xKndQ#RIp-Zu!*A$Cct{!KcRW&zp!2p55 z() zm`XXtdCqb@t95YA8!uf>p|?BIO%oVzYEGP2G3|3{dufro$0ED=P1~#UYuX)o-j>Zasz32@c3;g3 zd=sgF_DZDu6Wppku7hm54k}N6Qt}fx$ey*r(}sl_*Eql`YL<0ZKpRW1`=E~1$iZ`1mjL&~c8{L&RC;n-ZjW|;y{Nh;zL%||cv15^k8-_l(UV%# z5mqhlTmG+c<1$JoTE>G{Gzi5lD^CK>{ zU;rCBZrre|3k`)qSu<+kME$qFgy$i+FEy{qK2B(<1E~alKdD zD+vx3x8-?k!nFuJ_Ider6peP>ytzBr?AEA@z=^X;CQr6XJ%4bn3pE~*wMvTk@gdgh)OQD))2=288uWxMyzQZx6e z-=){gQv!J}``_V@4Lj#p{IOB3tYk)1wZ<)^n>wjv!kj7aCOLT)+`*Y}@q`IwC3F3$ zGiFWni^XNdGpCfmXB@4&d1}YZ;Ek|S;dIVQojB`)3rcYOruG{?B(=D_ylfg=AXc|B z88_l3z6Sh(;QuCnY#}|zu*$g4Hp`j#Yhz`11sD2@_>>V^JiWP){d#FgNb{6HPp=GN zGYnp73r~0Ftiq*`DT8_;tn0A)im}Ec;i5!DYVp!mLH65Q2YVfGg3uoAc=k3S?Bzkw zdZQs^-}ZWGTWaX-ZjAHBcS3l2_d?HK?xSd^3h1$1jE0Sr`(zD!Uw5hAE}lL5QSsZ$ znq*mF#L*r`V@B+~im;alL8}YKG=>?_;-&3^?6)@-_P9T24`aO}_TER>%Y&db81@`* zXZzCjA?&wzHSDojXb&U4BlbQ)nD)GVU(g)`R`CGmEllJ3jp*sUl6h?Y*m8Rvn?JS+ z=q>aL1$i8BX@bK2+i{z(U78@BdOU8pO}=VdU&G$9_+uM;nsrS6*uL(2+#lQjq(3(P zPWt_^@!idj^T%fHX}`}O8-Bxn@J8im_tuQ7d8_~5?vJfMj(hsIDirymn(_p3idZhr z7nh0Gh`fF?-!0;uBCoHE=k<={8*cIyaj*D+cu4$AnTP5>@Ta5SooxLyF_#r}k zOI%!-&Y3jy)6-GxO5%cV{173%pX59ea-n3-tEBAtJDVhVrqVeXn0AccA@Ewsw}_j? z$3^2$2zti98Tf(XKNW3U7-6Baohs%lzDOLc__1P% z;!7nPe?iE9nc^`Q-PB{X(ytY7Qv9za|3)-^fl%*fl>WTpUliX^{65L=i=Qd}pQ3|0 za69UV7*22MakAuAVyfbMiCK!z76&PQgk&!p6@JxJU8(#1BZU2gFYmZ{ANM%zFZ+8$Um2PvhqY`g z`1?V+@$ZB95lTN>>F0`*6@Q^*&fKM4cPRcY@wbY9T=I7DWyQZK?p6G|;z7k% zN&Z^o^kcT~3F1j4w!fv=Uhx@{GsQf`7liB=orOx{cc!Lo}yhlE`Oz zrgK0i*;Pyzdy83Oe{rB#AaZOJ^PeM*6DNz)#RcLb@pAD>ag}JECtz=*FP zYQ)c!Z2VV4zEm=O)i9sukJdb|LB3P*oPEvoEh2q5QGQ%}Ry2OC5%2k>eO>W2{nOGL z4)a%uoR3Ypj%fT_LvASfM6rcf^ZBr+;`@l^`4IUBNH))fkk6J}(?9JT#m^UO`lmI| ziO7GQ(tj=fMto3wRD4c+L3~d%ez9Tauw?Tb3HfWuya1VY5bKKkay8?dh%H5axtj4E z#javcv5%N5o*@>BBSh~xbG&5E)1lpq#3kY~@fy*4-n>)t-Qok{!{U>odESKGHzogB z+%Foxvq(43nczPZA4Hh-F@9&k`jU;`S%h0kP8N;-S%kYv?k#%Hophx{dvq5>juOX+ z#bSv#Lp0B!2wx=mVsVMMOk61%|FZ~RC;3K^zMEL?X7Rs7^IVGXcFErJ=^rKYn;^{h zrub*^kobxCjcEMRBAmeIHZVyv[&KU%Pp;!{O>kD~qnaj;k@8b7p1KS%Ne(LApr z-g{1+ulNelJhvkK7Rh&rbUVfJ9unzjitD!57B!LO~Aby3@pxokhB#qTE-c6DrEX#PQ-Jk>016evwGuQ6d#8KiHu~;k->9UIX=ZTBO%S1Y`V)}aV zM$tTPBAza+n7&nfM0`S|XDg<^EbbBC7U}1T>4!!0oC(?Ca~qf_HWcabit%kly1Sy> zN2G%*%7ewT#B)UYy<+-IkzTJTFA=X4uMy4jDbjD2O!rsR-zw7i73JTH=D8HIc`gO% z^@`~SMe{rg8FR5sJiS~oy^+{bOcv?8sdcLB(U!(&p%HN3Q`4e&ypU*)0yCPG>RM9+t zBA#xrm_9(H6D-PSi{r&fBE4WSeV%xkc!fykSWLfOG|!um@0CnnSWJIXG|!umcS)v; zET;ceq=PKVUyAgKMY*2XOl&UFSr*f~i8*4PNDo%mx`B* ztHgEU4PvGEJMkg$X>o`6NAVT$Bk`bEC4MbBcxPjd53!-xL~J3p7Q2XPBHi^de}6Gw z94d|!&lbmvlf?7IS>jxAfk^j%w117bPTU|?inoe%4@mt7#3#jP#9iX6;-AI8iigBc zM7kHGy*M#RY%HEEwi4TkokV&dWd75{T=5K%jtQAQU8Gw=%9n`rLr8g*_)GByk?skZ z{+LMTgp_xQ9EU{tO_AOSDgRBRlS0b$?N8E0A$fvGpM;b4}hX zu{c$nA<{u1(^ragPe}P@@mJzKBK;FG{R#0|@p+MM3z`10NT-FAzZLm?O3Lvfy%th# zDYg|migaek^enNzI8dZ(L#B@ri^UR=z73f^Ph2csCer00)7OhPiZ_dNfXMW%;#1=9 z#h1m`MLI&H{zoF+AX5HDq~AlzN#e<3E0OLHnVuoi86xF8afmofq&GySmxy$VNO_(} zmxz?F66phx@=YRLAyU3yq$5PiPmA63 z`gP(a@iy^p@jme(@iCEp6`6mR_=fnVxKDgvJSZL!tHiIxSacxJUcA^qJVC^3jGy#- zC2XAhQ-)5}~lQLK3$G5r;|=44Zb-Xx_@C86J~N1yIt-||D>L+RBg z&HX@1_=mrT@-BYMu|&Ryaw5JPnzZ%)&ng!89lWIUsZzTlcl_90jrJgB)`VTzpf#)A zE=c1_Ub0g%^Dn#fsY{oPx5C+5&aDcbSvoM>@zh=6J=q=W?yBfG;-zp(YAubgEmu(Xoszf^R{bh+_c% zk-_^GL}sIbWd04t1bF}j@zEI|6tjxOhU(B0c=W3e zEoml)f84J=@Edhb<{+Bl*9M$^rn4(p=L!e`J7l^PLcz~jZZKGG3m>4^FfgM70 z>^;!5V!uIfaqKjN7sVDL;*!|25ndQO8M+t8Rv~7ARmXg7VvhYPq&n<03of(2*)J_`-CbX#vh@=sUfp5DOUUmFc-`UtwL-dB@oZPli+C*o%ow5_6>!RF_03B zpTfMShuRr26yKX-woE0&ucX*dVxm=t{S(2QP#0*|wR0fYL(Qf^&5X$-?FJ|z0ghb@ z7ziV#9xG@UvVQikL{`rp#@Z#rOd_ji52sjyP<^(qJ(A7!BFtk`xrIs0+5yQ8?nmHT z$7+c8FIG%yPv*57u{SA+4RdBhrK#00g(?F^yDFyuKi=hQ(5_pT-dgGJG`0i0wKm7| zEj|(wb=w-MZ`G|!|E+P2e7f=VA}YO6h8DUB#L`FtL+jlH;-*LfLz~?M;=xD) zLr=R2#Lh?pL%ZDsVlP&=x(t1c6}2Kh#p)(7^tqcraQoc^2$7`=LU4jZuoVJUX~1iZ z7`8@AfXy+~)gneoi)4dHi@|cNutl&LXv=F3X|X+cqCtyTFD;TSA}t1gg%w%^8;G{N zhLRRr>QPsVU~5s!Yc*-@MD#9Ki(u1H%WFbu?M3vvSWzOucBB^hDOPDQ$X0|FLXo8t zLU8><^uUUY4w;43&FC;V7%Q|0HK9|z2^}`!cvp+yAx2x?p(b0Uh%UnlTf{^cv` zy-3>UY7rk}r7ber&`z|Wi;xgm+}2I2Br~z%h$lv2rDrR0v>Q#h?Uz}+!fleYN^*-EO}K54R!KhVMiaZS(g^t{H=1y_GOdz4--mEmZO^e)%(`1+4!3du*N;ejbh%YWat#HE(y?%xUH0 z+|S5k<7;_aKpRH9E#L>2vk>HM0qtt$DPR)ZteNA=izmR_gzJ(4hqq~Z2NRr~`eA2& zYH~8>K&P~SqD^yzriYz%_!-QNvGp_r1i;UbJdY_LP!WXw zXH=ig?9P|fwAY#b8Q;~W9M_($d{ieO-OO(AIn(g%(xXgo*5v3&Jx2^E8Zj=f-=M)G zhYzs+qh~q$rV?vDbEFaa4Iemi$bg|E#tj%gykK~ACU9gfGv_HsXVh1V_NEoP`z|sm zI%0chzoCPM=0y*T!2^a4#POk$W|nu)z?|gj)2$&0Ok;$)b_{`wu88^39=+ z%#i;v6a6E_nSk2He^}N&!f>?DoLFMcgxZPj6~$a0YM&KD2aX)vZ@Bfdo@3qE_cOv@ zk$#DI0ApP0?D-eqQV5opxt!{S%1h>9s_>-Z@?tA>!feeoW@PGjHlS}h^3QTQGrsl8 z8xHr`oz26W5dY%-LR(gAL{g8BbX;ocnYKlId#oX>KctriotowPf9<_{f-ca*>z>GR zbrW~48(v?T`v&Ta&MO<%qr85%%)X#skRo4_|~AycubJdr!k2 z_Y>=fuEdBvz7Aj>9uHjZL*?gr2M=VXaeY+u^xDG++umC|y=M@C?4@4(2I%$i1dw`M z_F(nGlwXBj2L`lwyYMy0{_WW5YZqQ)y#3YyVPCbauVL?f*&@8MNZ(;;?Szr>h~(jb z=YM05`-f%v?RCL%%45=7JbRw((H|eQj(qFIlTM@-Zmd(SCQSF2NI7W6l}Bv^tyUBw zg?O#x+2a`$T^zH={j$F$X`e@GbUBv!#Vnug<1X9-(Zw-uk^OSRsDO}z7ET6PeO_xg zpZHXt2JIHskiYM4yiK{)X3}>mnETIKH>LO`@!!Il$^@_(LDVOJKA4c0Ae!;&i08{O zrZ*Fti(%1>V@Epo0N;-%kcoJqBqGVk<{c^$+fv4f&Fd@m(#5{w05M-YOB^ds6HCR5 z#6{xO;%afDc&E5kd_>$XJ}2%H-x1#x_lt)`K4r50UyA{@2V^teA3Q;FrfB*f5I;il zM6pb~R9q!)5`QB;NXFoLByJ<)HO?M?QfO1C?@?a60 zW6I$f#`4Vm1d}9(#WrGRv75+i9`nJyfnlzAhKSoc6F*8kS1cCK7iWoc#RcM0ak=;l zk-s-A_eSw%@mJzK;sYXIy-@#2@fq=t;wvIwI8e_V58#KAKNkNkej(ayXXwR<=6r%| z&L@y>u9B0R_>%aVxK}jCCG48s74UD0|3dsqjOB5N^mvgy0hIafpKKwv z7Q2XPVlVMjvA;M_94_*sq_oGb1CqTeWT{v#n)&*OuaJC|_zQ8pc)fUwc!zku_&f1Y zahte9+$p{xzA5e#-xm*wpNQXxHhw}`|B#p3irBd4ID-IHeh$F<& z;&{>c6+pgOl4pwx#6{vVafMiO9?2%f-zMH88b1WE|A^!#ME3QtzAuZ$F9GCtB-fm0 zazyc;i8be$gmB@by#%q5*i{ZAQW7U$Y{U#c1Tui9sFG!%P)+2{o)f5 z{+@pEa^wmww%HVJzc_lt?a+1DG`C0G3Ejb(phuivy$%K=J>nxM#zcC=w^EF)-XmVe z*a@VlM?54`>Jg8Vn23T|Mjc*vgYl*py{`QV?Ae2D-iveLvjUe$zxa^q{o+Gu0sZ2v zq+PHI0`D#oSxLK)Vzghph&KKG;>`M^`o)JH?-xJbFMhmV{Arv&ywnX3^H@%>Q-vjY= z$#bv%KyUfc`&n_!{xqHEwat5-HFK$i~bDrRRNn|N&gFEI?_n+1K#S!^)=@;*hW@SHZp*T{UApYF?#nbQu#qBv=94ekG&JZsa zSBRU$7cbk@)XW#ZcvqpBFP>)Ri)SCcw4&hff3Kj=^A*crzRaP<1qw<8&y=m%lJ zIgysUdFE!ASTLpsa-akJOR9xp9-v034kvj>JJC)5IY%j}6a5PY&E#@q{0(#1p%;iy zuniFmatJe|(_q{5oPPp2_AR7Yv7EQQIQEzLyC`-8A})!&0^x@BZ%Xma`u{o-Y6U>J&5JpTr*4G}&Z9qplYik#M&QOJ8*o0 zIobdVo5K6RH+LGs9C#F2vJk>FRU#LwJO7%YNp1o$Ba*<-LN|d}8cAS?J#jEa+!RS* zh$BRiKs+8vVCZ!>fp{m9z|dhgfvAckFvJ5Jrig}E-Rd&LQPW5uxrZA|J;pEe3aDg%q~ z%WG(9v87LPwFtI0ZF#LOEjIgjSBqA?B^3coz9!VrX5Kkl*UjiKILg%`*uXIFkTbAK zi@`Fiutlh$o$3wkEJYHBG((G6kCnE_o3P3jgJ#T+JHh+`X_1ddwHVxi6}E`ivCa35A^5o&0sdP6&G=&xNZLJjRyZ)k@N%?mGV5o&0sdP6(WhAx7s$dZK+=WUaH zvEsZS+~!QHBqzJk#6qmpCKtKU#Ck=O8{BB(0Y#G!y3xeziY9lv(S+LuX_e$BZZzR; zbXp~uV79W5aJMq8lH@NX>P_&}Wd%vT5cZTS;V zLuYq;gRpZ^YD$W85xx>17k29HIHgmXGd1jdj_&X4&|ChrReoxhZq9w^A7@lae%F?* zlUq4=NdE2Od}cT&n&B-g_0%q>Ilq(wZS=^ZPCr-Yf_&PmRPsn8ab`QMXB%TfjiB!K zf1yv?ZKdy=xBi{okjVF)z4Ns*VGb`dMEYWXa5{UWf4z2xea(Ra)~uN&6Xt6oy6M-A zWIoL zU_$gZBm&<%|NH6LpyjdDM1hTEc8w_MhTSwdJVuzGnAwBANy zm;o(b8t?o3+tCaYbCVFq?cl6l&mQLkdU+7EzCkAHd5f3E`GbCY9enoK`{~)c9bqpI zZPdfu$zz#+-W&F~eXL)7te(C55vIK~tXyJoBA4;Cf)=K6eN^=H=E2B?(jh#(XAnmA zQZMNv=pD=a^EPOd4qhgZ_2cpyR)4!>``U%q7;iiH3es0?YcTA+k2r5({kV|6!_sPw ziNWI$iNoQ0=btacaeodCXz}cMvPXaXf7kr;-jPDQR&q;s%o*g>gzdpS9$j$X9~BV# zpPYZrHb2_@^TECvVi(GTQ%%=F?hWSm%s=<;B>nyDwfflEj+}eW_otj&o-O8zX3i_( z2TLv#&D?3kkCr@E#O36_b?*6jw2!{(5^;t&Tf9_UCaxB55_#=l{(HpViVurB#23X^ z#XpIAMV?o*^Rf7M@mn#>_CUJ%mK@ku@(|Iq7vj&Cyg)Q_ff3IMP|Saact06qS-%q> zB5~dOgSd-?{@daQivL*h=aS9bUg**H7xO2RkOzpUzA1-im6>}f@;Ia%7Tbu&=bXFk z@`c*NW;>&uj?X!F+hMQT<6ZH8+nn=rdE8@v6^q{7^9v-i-+}4g-1Fme&fWI--!kX? zS={h&|2!{xeeADG{)_0%J!f|j^{YhQJW&pc-Zu^FOZMiPpDfw?reQnD-dytx$=){& zPm}D;H6JAThrVq%MSACp-duC`u`W*FMz0k29S$=4adU}uUJu!V9 z%MbU(KNv<~xCHkw=m7s_&8)5;9j?E0^SJ%P>N=~e!>cQT8G$v<^?{8A`~MJICoh|@T&y4AidudL8 z?oElXG9+ZD(#CP>`E&B$TjYw{?BN{&VUUMQRq>6tF7* z{#CONy~oyHF<}5(zb{+=Dz<*0YpX9W`>J4%buHW6Ykju-AL4$BcAtoLzx-I+eM2_( z`k8eD9jsNYzP#$IAle;ALGb<$2L1N!s)PzFIfT|{i?ijuy?}i@2Kyg-;R>u%a4c4g znR2LNLAyiN^vQ=RrUx?Iz0n_g!*TbztyjkE z`u2-|e*4#XcIP^~N*`NyFc|O2U%b>Iul4eMSKd1Hu@6hL5&MMo#2q~M&AAn{4}o-A zZr$U?m}u`020XAQ9>XvGiBx_r5$+6fOibukL?EVu3FaoY9Um>>!@%5e2V*{Bg1L+B zUCxAHo$W*@rVt4jiNPTo(UBMl)K24{PQ9S!+{$2PA%lAv%$ereFs^6p&=kaB7{=?o zDG3GXza@q@&KOP65qhyf)*&`{3;x#OXo{Ig3w;0yqbV2(Zv?pHK`aaX(ujdjZ`iq{Fm+zYv;#&{#Ehpr zKg1`EIC}+j?F!TfU2f(t#Q#EEd^~>8>`V6|z6;j6tgXG|H~c#+o{oI%%l1N;k2Rjf z+e=y8cB~20Ec*&7eo0}vgi~QW;d}{WAk>>7Az@~^WiMxjHPo4zA?bEX(~2d1NC~bq z?JKz*jZuMw`JQwWq{JEc<0b}B^TeB><%;xzlTeyw*(;cHjFC{Hk!~^)N;J}!M(QqU zI*!VOV&uDu`R+9m@);=!zd%-f`*ar4!A8~4m5#qWj`m(8+=R#mrujOV z4_Da3l1%$`HmL`Ynq(TVi+u~Ud&EMUd(7@?n?1HFyCE7h&1Ah4i4D=BuC$#Jn$(s4 z0;v(&)Rh{tQPWMPx^m?QU{^VnmeeiYst}HY`QSt{BGSVZ%~1uPeSwk?q^Vyll^`Wj$M2jZiBM>2cl>#*g;E1Rf6>(Bj|3F0jND(pZ6RH(~!`u6a1&uWDiQH+j z8RHhwC@SLMP!UQy0XcoOX>#Qf8%>yQK1Ts@ZT z!2aT2JB?B}QYpos~+oO49)Z}oQq!|ts8eR## z$g%<$v+#Gy;c^=lN7A3YYYz%?2 zS@Q9hn~1oQq;WNoYSdn{Z$Il8-1|^j-v}2iNYQ-`}xMfI-lFBGR2D9|VUycQ1 zxg@tOV3jZ20rSP^$7DP1#^M!JKHBL1-MJXTQ0e6~Z&N=n+Af!rFt z!gN#5Kq@8K$V1R9w83)RRyq?}l;&b(4QS&XH}y>Jo0gT7K51xjYn%0>G#x8jg5=hjeOAtW*0Pf2y^j?+P#)_{>2s{C4Oz21>LA)IEN>K6cZ<0# zlwQV)-1)DAJaXJrZVM%~2eX=m?LPr4w9L_%Y>vkDh=Gkk&w~5iRCDAdnpYDkU8akrEgf>e?{JOmZcq=dq%M0@m_SwNy$fp@1du@fsy4FC~?5CKMyfcU^I> zhJMW}ZWy_6F(UXIY+IuVcO=#7u{B0gtuO{wk0oWS+7*{?1#rbB8e=tATn1>yyW&Po z4(D}$$eh)TJNRZqeJH;)Xdtf?N)R#>jiD#T@75N2bt=Rf*t@tZJX)0FK zY6z*Lb8yGG?yrP*j39@8C3vJ9a&w$X)~qR8xn|2Y|BjY*h9}{vsRJ z#$$zj{bo_p@iypjg#G7lviaRp=|gg0Zzxve)o&Ih9z8rJygMfUd7B*hz2#Q336NL6 zMwGT=Mcx8#wg2o*HfOKOE#OwOjgi+qZYnA9_~2eA-Lp1w{6tEHS?F+ezl7J<4f6*l zvLqmcUo_$r6C6QMlRqPc)od}NZ4D!unqVOjHo=iZdlM`qTw^1N)7)6XvpXzew+muf zN0#R;i?B^x_-n_7x%|ubrT2rGfYly3|BrnH%N_B6?f%#NeBt-hG{3Xdww_` z3gd-hz^V5xF~o$+@`-LHTsM_Si$s`EI>oO1lfgeuxl!uLa3=qB;vbVgn$ekLl$?`I zd8e6tlTw}5;q=Zar{9v&Z7gE!HvGd%*k|w$bK5M;rZHD!v9>dh#%z{uJMktQ)o5*E z=d&DNK9fGAb?dX8(P5`Usxvy({Ke?%j;YQ>w{FQ<$P*aIKSTM)Y+`4Iy6{g5|CkMQ z=9ml}7-2TiXqpg`oNZP(5X3wyueE;@u${y#r!4Fwnyo*;eB8`{GcVfK-6PhbP4}Z( zdb+zcC-_==da83`IHg5;`nrE#OFL(eX4{^X>i$h}I^{bPOba_<1JeSgwWAvx4Vg_h z?QY_nx$ai!crA6MdS)AI?gAXvdu!~1S1miaWpc~512LFB!33JNJOUfqCn2#^9&EHEG)9X(eSx`|jH8X){L^&#)px&dqrBA3Gxb|JVo9qJz5K`3GivH}?n} z^p%xxCl${yd#RLrA=<_q)^7&-*Bbvf!hZ2vH|1W=U z%xpH>Y)WLqj`G#C(xS47wLaj&@_*LfK5OH?;kEdW7b5!SX@>-b4rQ6`R3-S9W!Iv z%o5KcJ{o7GPQ<4*OK{?(Vgf~Kad~;!G+Ys@TbW!|d_jq?0e>KPGSbni=H)n5d+?8M zac?Fu)fsWrL!XOTYU(kK3vX6KSbs>5H>x$ut?-N>4fma9;WMOPZz}}vMwSYm-rO2` z*{DD^6|{JIWsuSJ6j_o`VIFTMVvWU0J=T96R$q0j3fQ~LGvZ5Ig|OdV2iPlwF745d zXKxe2etVsexY`%t1-I1Ddj!Tm<>Q1FPw!sH{&MGaLPR~cTy~FnfKy#3YyX`a1L5T-qr#U&R9IKO@3EllJ3jp*r3X?gVV^|4S! z_EInZZs_lgc?67*=-TN<}Q?}sOV-X=AHl7Bn)`q~AX9@!3Vldswsw1IQWSAZ8J zy>k>n>u?*(+JwlH5ccdPAiH^vC}cZV+!3dEI3GN5t*obK)-XHSu%NjIl<(#@J8H zpCV?6{X}+)FnydjOJq+d<1Zs|SYIJtMdAW`t(2?IGpa<*v3;=_J{WPU`1_2i%;=H~zpa)G#9G~d5M{B4rAh!2s-|0G$* zvYrv2Q#wC&!t{3}|5fr4@oUAK?^;36e9sEyG{D7+`ON2LAorpS4iL{1FAx`sSBck) zl_c!kCHX$d4@-Vd+%0|}elEt~lErcxi)O4Y?3uB;xX7BZx?m@zXNl%T8uZSTY{uq7 z&wTd@ynylG)g<(|n6bj5Ij?Zs@EX8){`Qg0MRPtuPLteAJXOpQ^TeUzaPe&MT(Lx) zCe9Zx5toX~#ns}q;?3gi;yvPKal81e_=5P7_@?-0@dNRI_@($yk-yVyk9e_xc!J0d zJEn(4_J&dJB618G<J7mMEczDDwTkt5h>@7E&lYbie{ zJ|R9On)4m$FG_w*+#_-f9P@uHekxXpyh&hsP~<2%%FV>EXs#28H`fU;Q}KCXzBpVQ zB~B8jit|KoE(6CBvb>cd$K_GJMZ8PASA0NxSll7*6yFl}iZ#EF$ANydA1fw`4aJkh zmLf+2Qa?jHMeHl)iTUCf(Oh?sZ-(Sjah_EcXrp;#d<7tQqx#{BP-yk9&del6mb$=KznOWJQNCX4OFR53%$7IVeHVxf4RI6>s_ zP5z$E6&Hz1#1-O7ks~{)e~b8Q@i*dD@j-E$__X*3@sHvg;+rDJhSL7u#LvYqMF%%z zOs^w05}S%G#bl9VOR3*mJYDQB4iSfmqs6h}L~)8ZQ!EoXJeBq@7q1aliyOp^;;rJH z;(g+8#qHv=;)~+TB8R-Py!XV9#lvEi__fH9u+* ze~dUmoGi{1%fuz(GI6E2M%*OcCTi|>p3#VYY@F^KmOtZzu<=w8b0 z#8fduJVop)4i*c=@!}-0Oq?q&5|@Y^JAj#f{=7@mJzK;=|(O;EZCLR>1Y5!Z`1 ziMNQG#jWC_;x>_E)>+;=;>Y4)u}b_}jK>W>^%KP=;z?o$v5VM4>@9K#0-q;Fh-1a^ zBFDxvy*BY_wVrw{CA4 zvnF`NjtgEJpO=t_nOocJ9usok#lWuE6EANT?18z4>Aj}DR%LB_7VDK;g1Ld*ZsQB~ zKN;V4YSXFh$6E*D>&71m#xKb|Vf;zUU#JRhdb_IeCi_5K?B`b8fj~@A?%P#Ko2&z| zm@T$F;h^7!DZG8^qS1S!5E%2&aKqxJ zF(2-ABt_@LZHMIWIn(LMw+;?pDY>4B9ah)rcMfBhFqm_JYtFo#vP1lUE#}0nVo5<9 zWk&ifB4g4J)|Yx?_{uc6)V?2x;o~W0&b@_jY;eE%%Qtkf!2oQ;2Jb+)j(sn}c2E34 z*9re%v7dw(;>#yH)4ZxLjQazHUd+)2Yg{VD-V}#WJV+aT__kms#CUca*{3q~YKp&P zsuAyjSQnG9vY7Tq3YddsghM7}re&YTx}As>RpV<+`x1uD0M1g{8H1ADsx4|vxiIc# zYAt>ge>Wn+ty%>Oc#L8SQ!i!J-oct+s&*NbG5gL`%m`m2jTJLOa}>df8G(=Tb*G_X zOWAa#kgR%k7V|%iJorh(`Z!|k&>tb&&m{7%D)lVO;k!GxQom=VzNKi|YX>V8#_^V5 zTKai+b4*!(U|D^cWa_)qUtc4PMH=h-0#o?Z%=#MP4hX2hPdmNJKWV7i{H9R#Ia6^y zF&2Bi`ZTG!n%|@uRh(dzs0mg$q3RvA5N-?>^TTzNnMpiiF~X4V!y^lS+%Qs*U^0gi zMu+@Si@$an`|c@JpG9OE-StFE1xzSnHZDBzKfxNXR*xW6{s;uk!WWHq_6d);t{h#~^m(Wn9+bxm^Z_D(bk z!wKf6LiP4uVHAp1O2OCOjSd10q{xV1Ae-)S9g-Q1Z1F%@EJcjv^c6lYS{X_e|sPCd;z5yL3M zPW@E41jcaJR^2(2G(PoYr*5hq)|SYA>p23?{Y4iiQh zEG*UO9Ij?62d6Go#yS_zw%GIp?Q3&B6|R71zUn*Hot@j7`Q1Z`&S+K}hZw zQ%$J)ptK9Sr(@)0Y0k9r;U#lN6i=8@V);L>%PwHwz8HtJ=x9ANBC?i7_jJp3*_$&z z!yU{Q8A8cXaNqq&-T!N2Bqx^-E}4l&DoxiI*zX)AS*-y%TrfTJyM{?d_oU_Rb#!Mb%s3Z=oqG=0CEHh;C z=QBJq0oQ52U*0ypYd$aeM;-Hsn?1iCe=?4umy?K_l(5epe^QR3_anzh`p^C9!z2AE zxQO@$PF73#PxuTk{5P53S#tx!rtZN%zQz5Sx2)EP<8QKgHUVquF^x-mtRbvFq{mwb z=8471h4y&7c#C&qk%tJs9{aI3drF|EH@=46Zs<)tirymWc}dyWKz>8bTUZts-WKBZ zS7a$~ig$s~McX^HEOWVLSDrjkZ zl4XUlkt{bJE4P>B-i_67Zx1r1Aux7P!AcwxlR9?xCR-s1>+c@VVXP*|7& zEneEgkp1>Xz#hw`y+o{@yJK!E>AAs(8GS+yavI{8z>$<|`lHEigZy zKFMj~Oz~oIiFl>>OOe+<=HvB<+#)_EJ}DCoa0`GEL^=%CSQ&x~&ZjZa`4 zUfmfF_9E+HPKES_ilY^OuH-3_XGoqa`C`fD4KnPkki1UmH;a4+%W@tS%{V61$Bbjb z55|j(2VYkDTO`sy692AvzE@^^04G1~)gd99H_?!rNKO&EO79eLpg2+-OCtY75*Mf` z;`vIyQ0a?AZ@l9*lKIU%)?=gOJ0#yN*^GNc`m>U~@s4jxZ@>73h}~ALAIlu4*iSt7 zxW9PaC!331#5A#&c&a!=943wy&2b7l=J*856hB||#`Rq-d6l?9G{-CQ-6MIk_+R29 zB42^CzORUHirzTBLy|uczZCx|)*Q#j_vW?}z29K9Q~(DIXNs`9Rshk3LD~ zdZZce2ZklL5j%_BM0QC~KS$)ZJ1Gwl*)2hNyf{TXUt~`O(<{W~;??3>@s}byGpKLI zAA?&YKOjCPJ}H{tub;3VJdMW_j`xRjT$$qu^=QoV4?pAH^(ISlHi`W-Niv@ySbzT9 zmhm$I`0Y)d)h!(92Tu=&-41g1Z+co>Pu*1cU-QPE{%>+8VH!2{Mwt8#N%*2}#MecU(X#;vgq zZ>|WPcGnSnZ1hM{LhwjZ9QvTM$5w^1##RNp6dbm)t=3O}<=8Jat-pSERd9UbYB%m# z#KA}F>L%;|(6sUDw?ArPZ~rQ2LnAw}@`SZXN386nUj3}SZ{41zuo8}6o3P>h zsjXJETwhmZv`mTL*kYYq4sAAH&m3=m)ZC_B)F*uYRC{CWx~IMh!0z6rbykHp&~8QU zWw~)1s5>F2b)Mb3VE5P+*eNOa#QlgbCU9^dZbw?XO3U>VXQTK{8i1)N$NhnO|?Gr zEAuvOMz6lTD({B8hmPPgDTjYmQMXmc>pEN?vlb&363)yEr3FyRU-Im=F*k7R0Q&LA z-Y^y0o)lb*{gh*+?EESwC2{RrO(Er-nPato>Z_P3r{-bLt*yVV$@;gNp0E!4Za^XS zb>m-d|0-cXV&zF_;{am@H(Z~QcWT~~Uj@A| z9PmO_n{6%DzFZaD)_i^JTI?Zgi9G;iCb1p}r?4)x@70HSW3JDy3XV;<*1j=*?VhHg zQ{p$~SA_=Kr@c_sV_V(TJ94cfA?pvhF>B&^ykEQc(@FP*qhl)iosbup?@S#y&F-{h za}eHti(;4O)!#L7e(yYb;N3ShW!i01?RD0**?H+E#*A>d6gKU|=d$zc)z-Cc{KWam z$kWm2q)fFs@88ua&q`@9b&!=)6+F51RJ;3iIbZB{b7$jPgG)4)pgjTC9Ge5A*O`dw ze=uf&_c%@m{0Vs9O@5A7_drY);FuBG-k5~~m~#5@8tIK$*ul)-Ftayifwu0v1)e?;zS4dfh((V9|MGsO&i#l8B?TV}&4Luy1b>2$ zgcu2r7;)oh;8Bx=k0r;wP8*MfT0$w15{lc3GJ=mwIROUe&>(H2;gR%2s3XFmX2CB) z|3Dz_Mq2wv==U=Icj|l@y2FUUxOuepmBg61rd0k~%AvS7nEFkq8SDg765>K&@ShTs z;yB_y_^l}=kkS}6`4;JQ7T`}z21~KxmLVK(zXvNe9~<0<0Mh1cp1Pe7XJ19@T@hE8 z&0t^6it-+|Za<3GF!eHueUQUmN%1y{FX4~<3yRNBX2)H8ez3RMxmkCB-2TkxvY0rnQWCAIW$rgTJj=ukLt{;5O3-%s3QrZZmzz ztuuorOf!ANRNhIr&9tB5M-)vn9iVsuO_^r;n0XgKbX(>Sw~nLt-Ig)p!xT-+{Ec}( zp=eshh#hdGxh->;dGjcmmN8-pMbk1yTuRYw`w^PDm7>{pBYp@G+diBddlr%{YaZ4- z+yvRpkdz3|zM~o7sB*U<&Zd>E6wS7cp@<(GtNvVMw8!$8x6k4Ma4t79who@G2E*&{ zd6eu?4U&Nr7<>?$)X*Lln1{cGfs62b*#jv_*av%+GS{RaJ#a}dP)=BM9^7Cs^mzE% zutEzyJ)_WwM=y(D;vCOBPLGy|tHbFyjqPbr2|gLJ?Gsqv6Sxg0+<`dr2d018p)ao6 z+>qbFa9ni5kQWL9t_^t0t#S5w=UtWj}{QiF% z`uzVk@)FQek$S-^aaIBv=ono6@=b$dU9uU7F1*c!pDw~YiDB>yY2Hd;bW2nbhoey) zMo4wEPnCN&vZNw}K@9{g)gBg-Zxo6MPobz1LS#`1rX*D+lE#42gT5Nz_;i;{z%5`n z!Kl%A?5d+Fsu{c`d zFfSiZC%1B=iSZ`iykI3&SrH7^@Km`S=2pQvCz^VWmpT-I6iM1~;CyRyTn2<>5ndk&mUP#@!Vh_R-O)$cB1U@F!co=DLlwvL z`?a&0S8LdrNQU7c$@W1bM~=O(QCK44aK=?FViE4fN6sgvw?j1AgP;afD;6{09NR!XI-5AftESJZ!lzi+_1h@kdKHuln2x)&KdU)FSV?CZh3wtW(HU zww+~$hQ)u>ZpuJn>P4MX&Pf4#4D8dcb9!edzTBA` zPHFGV54XUOGG}fU{+9MhnV#3C)3V+}JDE5PB0~y%?u7@Yk4!tHuhaM3N!cGcD zvN=Vm2=wd8NOW=V{J4lbz(SbKYd9Z5WpFoe}v?Mpm`@{K>L&TC{8ntKpQ+ z?VLv8A#0uKS?i|a2|O@{f6j1{^34c1zLzvUx~9#P6F_zjUYOY(L*Hgkn=-RxQrL`w za-G%D6=CE}X0;sO;hN42tIO=6Y^EUEFB;cBFK>i(f#+i|nwtZv`kykk|B#|VMeg5m zMJ45PO2>`rkveal;&Y1%#|@q~VQkT?Ib{<|#t!V?-yIgk%%!=rYYf_pjL*`jDbKy) zaR1n{(h(O;n}n~i<_s?>o}p2C(cyf?Fn!UPidG+U*3TUpSXwZrJmY9X`2M5E?$JkK zzjVtW!zvwwZ{tM9(isPaIo7N><%6n?T7y=)91hYYB|TjZr`B-G47D={*zD37)5^z{ zaaWn%Y8H@_Zn2TQyci)krF<%f@|hugk)2`=S8sRrGrNbgv%9^7lLP^j$HrP3D|I#jurT z6MjA;`rNSt-!-O>KafWmgV!%{vt4aWAAdlPqL-7n$+p72UtInG=Oi{;8hd%nvfvfY z^1w--K2f0o`2@zo|Y9h$z{xH^cDC7@7ika~EN zW0oGG2c~gpkCnGxKcvT-t(xWT@{AzOyKNp&Lys?nyqhf~Mf4`t&?`p;{5NZ!y>ZY( z_grKt4_g-gn{h6D=A|C%zW}SRI@ZUqM_(A;;-$?+gx}t}FrK<#gyUvt$FsK#VJ{DY zRvI!T`y#yHh8lXDXWkZX<-EnyTZagLxlgx2yFicSqB}HF?wtsGc@VTNYT!NVZ_lMhHFIZJ&drI2SMvj*b6hD#Y=ktvftha*h@nk?O{k<#NJMXy*vn7 zzlS~cjeCoiwgVAOH-_W> zs;B!-IH+*kU-fjJvC-w<;olJNcztzX3rCk@@o&f+Y*YR&a@=1>$-Jg<+}~-E=YjNZ z$Tw@=VzxbUJC558Ob>_-0<7^{=DP=q+*SGWn){Z>4Z3+(5|3jn4TaHv;TdF8ydoeG z&zAl%;{?;04+k?J)=6H^Np2T;mN-_NCe9T3Mv{6J;x!_#e~iCHX zApONkzf$r_$r~iIpP2UUlzfk5GfoNi9+CWv(w~?7s^mSA|0?-I$)8C6Lb8oZB8;~bTo+8c?XN#AK zSBNXcHR5gJuf+Sr--^$O&xtRIuZi!8ABjgqb6r9G*tO1j$B9W|W09jQnBH3KAa)Vy zu7T-&ME1>79xAdonDRLyJL@UW6gljH@_ccL$Q}~L|3X|V-Xh*1{zklCd{}&3WcNSq zyd>@x-x4_XCS`-O}Vvb{18FzDmh&=*D=JOA=zBV zAdi#G0UNZlNL(ha5IKT_>Bj#ec&FsMMGom;`s3m=;&bB5;_IUE#|Zs>k~s#1`9BxG z5jhNk@o=MIm>{C3-pD7495h0`E@F4Fm&j2hOwSjGi6cc0D`EOHu~aMjM{7n3Z7{CoC%Zn9j`eSUP_zq&a*i+;f z82?~*Pb-CHO{c>+P5)8E4 zMXy}JQ(}&UoH13w#j#Tdeii%m*;T=_UxMeZwqMoVIpC|4KWqP0lTn$C3-&i3a8Zt( zl~NU$k%CdE|Bt)3j;|u=)`hnwJMQjo#EA9X3*Yo_k@HH zR{}{0NpNQFvwBw`%z4jy&bjw~f84Ks={#j!T`g6$YOQDW?$qVUhMzWc>>_TIh^elk z4B>In3Gt!3??u*k-wU+2n+lJJElj)g)P6olU^jRJrBUAO4a5a@+aM)o>K;vSeAVKW zUTjgi7@DwF6SC0l87#y zyEx#E2~J5uWnOf@48Pp3tpDtO1zF>MS>t|n?oz$s{Duf{bR`0+jqaD=&~@CA>-^nP zJ>q7edi?ACqEyOlykz;qX!N ztKyDz`Didj7}USkv{(OHdt60gt)xptmp<<#y(=>C6qFZq9|i#yT>zUzco=;`xCH+; zBT5VAwi|f56cv-eD{kfKl5`-}!4YDIzDNgUm*fC(fBNT0DoK$@nIt*!BuWWbNGTF2 z`3{NS(Z4`C6WFxvQ3gESr4*AXy8^!QbV-{irsaslmD(hpOSyg#6fB~kKP~0OwC<90 znnpoKDjTr^LDbCqaS3I;kcKagRr84w{$tWI3CT>-7$iy83vUouqm*=uFb-h_Pghx6 zdQmn74Un1PpY#{m1FFDIAUi=Nf9114&XtkWEWOOQx-wZYReXgNCUP!GttzA+QSfwC zs2XV}`gfIQ^eP)m3wZ{ujN}e!u`H9FhnDful2)Fs>=&xIw3VkT3#7tjtguW*Ok8Ps zD^FKOE`idDR-UfRlyWQo!P8Y)MTO>2R+WroW>sE5bP@4nWpQ_$Pi;QFULkT3QIinH zPXj8#>bywg#-|HZH=zpATcP5x9bXQ6%O@xf`x3_Q@hQTJD&F&D1gh(Cl*pT%nJCzb zGkdo=vm&fG%$J=xiq8BuJF^54#bJN9IrEn=&a4P4st~d&c&DHSRz=8{DjM2Up$IDu zYh(@Pbqt+YgV%jItW%o?e+lEvim;-J&WbZ@2zkAk55Ds=3WAg-QP+jOLL!1{(i7#HWp}!)`;h6{n6yYfp4&=*gf%h8Bht&VXeH4ZW)lq@^p*GRm!1$%4B4 zrSUv&UH-~;)BB{$Ul`Bd*5$8jFI~DWNA>UHgZx$Pr?Psur~?$x=dbA}x+H!6k`zJy zig?*+W^j0|=1r)NDHfTPQ#h|4j-kMxcZOGZ3J`+uWX2V(}|d^pRq53xSRl zAUS_71xUc(Nr7wxPEep2fd>?*Mc_RJS`e_uGqfZp0#jl^Pe9F6unQjy#_(_Efuv9r zFr($`Xavk#3s{iCj+9I|kVcI;2rR%ZjQfcWB(>ZRbl_A3PElYa0=KA!){+)$k&>yX zfd&vddI{B#O0uQdB_vhSfuy;k)fRYqiUJno3t@z&Lu*9C1|3ABzwn6}tzs$1j7DTv z3ebADCj#cJr7Yeeg};+H#FTn*E&?>^2&Y8hiJK)LX*G_p=9h~5`k3870;!G6&LeP| z0*4W}O-1MuMf(Prw^m`1gM>KbSQH~rO@S8((8ua6NE6nP0<=^dOaUzf7E-_rflCx{ zLZAcz8+sP6(5_~>t}((AdRORS{EbZhVd&x>nYWhU9|o-?a3np94+#84N6rx1(IwH- z=t4J@p2lzr(9@tLgL!LF{%LGiR6&C(9WJ7qGFLd3s<1^GeY4%n5CQr~yLoE~3lF5w zBg4sQES2CW86CM;c#4jkinIngawG!UbRm5autUJSwW!5Hq(mSE4}$(#w8woIinv8b z1ZGg64+1;*5&}DW6bXV{Lf`(j7Y-Ef8=zzlHvdX!AxOpHNnXjINH< z3u(KF{R(On{-BCB(HoJ67~k8psNK~6!YDvJavTMykFKWx_1cpN@cr*G1*rcOQ-J!P zI@T9_|8u1P^}jF*Q2!fE0qTE;C_w!$3W2ZvuOk}O1-tM;7Sj1go<{-de{T^mZ!N$- zaznJ7^}jv{48SgoGoZ_%Cr+Op;h%UY1?Y+QN5H(bB>%+cAq6#1|D&UaPz|a5s66$* zjTE5%cYqFTEx`A`Tl|51|D%IO(1D8nM>%}|i=_bdze+l~wG`j~BxKsfv!L!r8)X_H zO-RqqjCxf7VthXvK>_M{D=9#I@dyQ|bKa)_b=Lv}_^$Vn0@U@)P!HerdLZCLT~9cO z?|AebY`){|rvP<4`hv9+bv)r1zS~)%EwjC_%%+o5x7$xgQnx!# zN4A#WyIr*6Na}VzILe=nTr4!A)>5~tq$8=@DQO}=-OdC7^VXt#w+loHF4!3V_-@x5 zalYG)qX2cg4SWe_;XWKM{SDqLF66!9LbIvM1sulz!-@azdatx~TftrD{Y|7j^#buO zsVF>K;JunUUOwLa1t8Go&Wq9$KYKv7c* zp|>8@HbQMAf3ap#fwvyzn5*I5>!QgP?OBQ?1u#9fJp|Jge*kWvO`CKn-8Wk`;ZRg$ z*Xn{pY4&Y=a~xVT&}ThZGde2$9HCAHo%pk&TIVm<&D?fe{=M4{>B1C>|9^Z3mpT~8 z)C7Eg5)36s$F3k;Qz#od$`Fv~_76V;J3e$f=38pN9<@40UahKPYs&t6&saK#EuL3($Y3HXj2Wnu;W$` ze62wnF@9@PTAfPwz>d33@U^r$UljkS^uM~0w)w0*16tGQ#Qm^~1l}j9%1zjDBMA0m z=Whg%-=^UI0_<>DAXtZ8iZ9i6bT~=D6MW84{O7kN_|J=jf}sSfu;aV0d=~!E6`bLd zzG=xWK55`?z^{rR{_|Vw4T7i703|yK-_~)+5yO{~{|Yjl46#T= zn>*KZVYf3?Wi6QuMZ%DW%`4{hIs~9X1EE8CrB-xn;b98T1!f(_( zM?UGB=8?@64pKA`+be>sJU`CSRntgD_zpYXQ35(I-qAHDDWGT*bw7Ti3#`G8SA(D) zJABpFoTPx_!p0ELQG7bW{MLH=XuP4*DXJaEa`}afB8e0U{Pqg}MSPow5zws^p+~oF zZSG`i(gy?-ZTNBvDT!Zcz)J=dnDUh@Y(0Qq1u0JZ<>Au6Cq`qDB=`Zw3|FJ20I?21ahyeCxZ-@kRO^+@qy zsE&>&={=)*+PrIY5!B6FJqT45VftMm1u03e))~Psn;}A&83?Xmr^5)Z^Wl9X2yZIV zM*zNTjtF7;Aqd9Kf4Z9jRF)?BZ@+u*fmF1SptZoazJgwS0p10%wZOLyf~-A!yI6a0 z$k&bKOWL&e%V0H@dW_bPy$80U*{&OKyk#Ex#?@tmr5w<-&8_b z*tWp8 zeMeDXP}>6E_8mom!EFnC+jj=x#2DK7`G~a=3zj@)m4|WWt1pe3+V=RR_VsGPiDMK`ZPa50}Kg z!he3FTu1D$9RLy&wEWSD=p_G8_Rt9dwd4yj!ZGbPw?9UY-K?Ux~kDxkZG zVF3U6t+mB%W<5&!H;tpLHus)R@$IbFT0oIXMHS5$h7i9|fq%4&lK#!LP*z9mZ5}H< zOGPF0nD~uK{rmT(wH_&?QOtTBaRAlRrdqmq5q3p~6EGekNh-58!t2P zD0m;+$@3RY9Y1;Q;F)u$c)-!~UpU?3-Yi}+1q7F?>fm zSU8%wJHmU^&Ktg?Vz*wN3WwDpK2BcnWOcPc)Jv>AO(GIEib5qq@sYJ22;Ua<5(j&T z`*|QGZ!P^QL|<#Mr?opAW6iA`#XUxdLp+w^hbBC|dRvM2t`8N@>Lo4_diaTTHsRP^>pXa;R{r0x zR?pVf>)9_9(ho=ACnL12;hBrDAAE0J6_?@!&t4m`y0rj4v108JP;66xzbHP$UlQjE1s(ZR{)SAq@>JZA;BQ@c{}2iB zBNudY=r;fF-<+5D)TLM;6#nPVyx;h?;VZyjopHbTRFeNIy)OUo6h`6k;|Fye{2%;z zQJ!~_{8|;&@PF>ttN8s5`iTQLn?|(xVUGU|AK$OP{h@HP{2zJy{)?aLXyahPJDJkw z{XIN~ESflP@wEAi=5|{;Z}O6v^XDz*f73zXG01n_|6ltDj~_p{Z=blXMCl{xb#wsAzKUtUoh^*`_l{x2MW`4e_Rd;fPlfxr0G ze07oMy9(|_r!Imve!>cW8|3{5KjHD?I}PeizkUM1yAG#zitrVTVD9O>U+|)-i zBKUvFJ(&Nt_5AXn>%Ozu?Id5uf zjfj_jJqD42KDurxMazqnUj_-`L>p6_zA43ZEov-88kx)x_?TnWcz;{ z!OIXxv%yZ~Aan5BKg;pY069+BX%X>Xl_LrFpXVLWS_$%67fK|6!oK@u+vTb7&x6Yv zUxv!j`8s27Ti+H$ZX>OAYprh#655sv#0Anj)w;Eoqvd#;<_LD7+$i(*Mw0VK3NZv|G7*HMnn z3j^tw^Ik-_^%w*NXRQ>g84A=vG;nrgi6xdlqVcGifw8@J{xNUv*J+Qz)8r6qe^rgN$ zgsDDyzi11y10Uia^-+E~_O|8B@Zx?|kt*^i|0Q-DPEF^xT__jS8Ua!nena3(7zyzx zw}oX9(Dl;x347b?2*q_!Tj@FsvA5nAx~4YG7W8pe_$nfq-&)T_*yc479B>!>xBP?K z<30Vd{ze_G^(kuq`oC@Z|M&jE|CRr*avR@VYNPVkh9dO;l7BGGi{u|{*X9be5vF&6 z?m5keOwVd)_ZJF@gH4EwV55iCB2;cS+^gdy)Yh4XA;`CA$8 zVfnnj6wZ5srC(*~cNyMi>Ab%b%EhzvESCO+VHrz*!LXU(dzSy1A@3)J_UK_Kr0X?e z=tzk40EQhI_GCDW5amZPoXpbaFkH%T9mDS#?qztG;TeXP2~po~3?H-fc!nt~J%iy> zmR`x?&l$dF=^~k;{b~%g2~od3LkpJf%;N1BhO+do412Nkehi1R^hqo}jo~tuPP|RJ zZ`&CD!1DJoJi^jX6GCwNmBnu{e84c85bY(hC!rFA9P%quWvEGr^O!SqVCcaxfMG|5 zJsA#SNCZ(jehS0643{xn&u|;VeGE?$q8(=$-el?b8FDN=nqdk{Cw3_v_l)5Smfp

EF(DkV>)MaQ(i1Ru!^k?ZE70?-Y0>cF?omj1Oo=ptDXZbrB9$@JwS^O-+TP*znLpe*2VVKI&^I5!*VI502+=NMLi7h47I$Un%P@ox^9ya%A22=fh-4l~)}wS^H0!%BwF8NOpk>mq75u|f!mkU>ZeB822CLrBaHLZbZ;k`D@D>+ico zusAQTA)VxG${)mVB*U=`$+v{^$=#2T^ah0681nKR;s;p#C`11HFG#=1;&&OgelH=C z#S<8|em|jv#VZ*8^ScSOn4|L(C7+PISO|?7S~Ij~=*G~KVMm5t81`n^pW!Hm;~0`p z4AoDZY{C@`*D&PePo(c*aq^gAy4NEzc#`R5t(@;Ku3gAtS-$1sT@|J?+n^WRMXRkIb|2-F0}H;UtFB7?QIS<*#B$u1*yHfg$-eQT!A`a&e;g zEr$0PK4Qp!{{Z=!EY5%b0P#W=CyysOp8x&R5 zF!@UHawEfXhSdxk7&bBd$nbB5oGKCXvxrtp&LW;#G>+@81`V;haov=Q9dvK z181`MT!y^-kMzwfzLVh|h9?=GWq6t4ZwwzZjAEF`FqI*{9zgx&EMCj7p5c3jpBa*m z7`0cMp%FtfhU7X%`TV*8NFHST^)n>hJH`7jxhdiex2cMhUB(J<>MIsa~)C6(yJMg^BR@^$nc-*336ql{MPjZIj>QiUrzwZ zhmGPL8Img-#aq`AqgZ?#Lvn1R{6!4Om5t)xF(i*RiXUQllHpl~j=b~S)4rHC||~qyxmCNHe+bV(1{`Wzfpb&!w81m7?N8Y<+rXY zCbRf-hWxq$`DJ6(&yUKlV7Q*)W`^Yc zNBIXC9%p!(;jav@F(fZRDlcak&oG%`4#RwgB@8PVk_RCj|DGW^5>i~9p&mmchU8XA z`ECr!kC5Ww49T64;sY6uU^s>$c^Ojv0*2&cNb$`K$*GXy2N{xYA;o`Tc%9*GhU95T z`SA?X7-lgfS3}Bw&ajE$TZZI;NcpM^$q|v_77XnfIx{4gU(9Kx;||+B0lj*S2Tn0}0Xp zLm74?MENcZ!`V7Xlhy+$7ek1AeahGSx_;)5N1Q(%<)*Ow8LS>pfA1jcHrs#od#wTO zeSH1-^8bzR6cOVQA}n1KRwDd&inibMx_zTXu-?CKKp)Y<&I^STVkSr?4oKI@N9z0` z>4Crv<89Ls8$UEdXzS5?(}d0w1=byJdOcXsy`zh7x_SNv7ggkMSl>0n+ScjYd|Uf( z;v!p{Z{pT2ZW;ZXH!QOFCKYwfx5|*&8h?|z!PelLxVEkCH*txr);ICLSsMkk}U&-O5MO7UdBmz#Q@6!&ZY64E{K}v^*dIHYSP2M5TQovaqx!qw_I|0{D z)Ibpg*hr4@(+^`Nh9mYHq za(AvtI;^M@au$~F!ZoZ#+@2p^gqsW%aq6Fo!jJ6|aR=sPhW{KZ;+&twgsY0hTzv08 z!<##axh40ngb&*+<~-a^g?q+{xt1e8hHuc2aEYqlhxZsJ;jXP(6~67Xggae3Hyjtt zogFnXd|n4BcPDX3xc+`Amlxb4+`C%Jsa*~Uj}2Gi2AFw3lK> zA2dXn`(chsc=R1*&Z6*B*fkRw$Mt;`rnN!Ft$0)(R#PM6x_Ukd3ml@tIh{%j`&+KU zS?W9r3-eLs+HJZK)^tvl8`yL%%-U3q`(etVu;_hiTxrhEuo5+Ou5b7CVT-n@bD4iE z3R|PB!7Xr|7WR3Y2IqWiWLS&3Cih;WZ`hO{HMy$w9m9H=YjJgrzG0UxYH`|AoWj=l zX>$W|O~c}1w7JVYG{bg`(BbUw3&W!7bh!KOEul-k)8*!$stG-6rN>3+JqrzbpvSe} znikq`v_9AMePrmQId?+~PZ@CW#lM6O?{3J23_c#({gok?7P~j}+EF9!yWlOM zyLuXPku4z82!t&w;aCb|z$`vm~-aWIt~vBTIt3W{N5|%!jyL0 z70>XH?StI8D;K>($|5|tXI2g&H~c)gkVD2HEv{Z%lD2xtbz5(4*Y>}IOU!+^b)u%= zttP(QnblRnXN=o(@0#<2eNFwijq_51gDw5Juo^D-u6+RKKIwMwCHFvX(6fud+Cf3w z$(MVK^eP)I}8uuKKI@ftUN1}dl$PjxXb!5&Lv`I@SB6-+`flnf-P=z;Jktc z1m8>P$jR<>4o-gAi8JvI2p+82nVWRgHMqY|7p~I9GMF3Dl{x6+^?fwHn_fHSvy6SEVI$t@ME8Vv`NZf8H_dsWUQ0|gpT>idE zK^EL_EEKZ&@x~( z7t>@BXcxJLo4Z;k@M!;a+!V1i@Vnym+%G%d1(Yq^$c5{_47jPZnX^4!9MF7x3pd;` zE8v%at=zNUVgu5%zUOWQ-3yqtXggOBbv0m_-cD|4ztaINcXx5N`3C|j$L!`Jrfdu7 zA>GT}X;>X#aeW`RcJ=&#DPw=+4l7R%u+aF4Q#~*&pvU8bT)K6yfQrS3xVo!h0Zpz) zxCtTN0gEe+a;^#X0aH&M=Xwt}4u~Ijl8dfX3pj3dnmf4UZ~yYLGaM&w@;`d%9M|Q? zD*xyO7dRWcr~czYE^#AorTEX1{mQ-UEcdT^a+%A|zU`m=%T>;9+9iMAb-!^5Z;$$m zhThjb2eYv zza3_Y-0ueUe(Uv955Q|{H%9e$a<&$!7;*ZJLyDB{Aj7x@W?lyDm^PxX5=y^M3~ zKGN^S+6t~ic^|*62dlV;>pS}Gy-~xRH*fE!l2*&T{nN>>vHm4@XSkVPcbx{Vs72FH z&A*Xbd_d$EKDLQl;`^q3@zxfuJo9<``kQaLM~e#E&n|t>$@DVX57+&~akrw|U+?-C zS3Ts9_RCibt+eR?1B71jI6`@Y@d`*Ccb zyzJ~|-wEl#^49~F`+9W^ldt=0mhYSg9pqcDjPup=kC3a49^~tAvx{6qwVUr*ukP|6 z{tWWnd84O%$4qzM;`V*y%BD8H$M5x%i<0zxV{qF?UB!p4wL1tr`+_B7EG0|GQHsQ zV#N&kcj<#I4e+_Iv06SOzq8NFM{DJ0e+=;XZqWw$w0>?r+nhJcZ>U)LG?jcO|1L(?C-&$z zdHF^qAMwbY@}%$&-WQE`%fmj^dEb7zR~~$?)Z69ckMhVBIo?Xs4$5-_61@9(9+oeE z`@sAChokayzhC#(NH`%Mx8j`lj>D(r7lICX&zo~jzV_oz?>{?Tl$SkR?>)!lS9$J+ z#ok++uEFdI-~B(r&+ps zABcD)A6RMOz0O@OPrIVyooX5_FIgh>-l7^O-x~Jb>(r+N`D3LzFWbgs`48zOUaB=| z^2Q_CUL#5~<+W4ez0?bHQ1k9FDm5r?bmzlYpIq;h!=aQh+fD)WKQ#{)UKEJIXlYB$+l4*xTK#~vR|{D>l)#e z+xxA&%*fxX>y!`j)3q*MM(aPzKR&eZ>UT^K*|bl`tLDBq^80C0uc|_&$a^90J$r~$ zBX{W3d1|<5M82;s@$?_09VvU9?HRdNFY?a8c+VS`4I{<#A9#wNnMA(se%r#6~PVe=>W1K_3$m8zy9^UH)My}B*^O%}HBvSGw$K$>Kh)BPJ1dsZI zqa(HD4?Q}+9~XJ>;th{?V<$z%?mq9K88bEV^s>Vqn>}Vmx{Uw9W5kg;kz;yn^w=$1 z5E<&T)Wde=;>ZN^nI48OmqkisV?Aa~ToqZ@G{D0=e{JNJk}e(|gEvMdr38AMOxqGE zzu(SdUcYUT(|@)0IF`0E^5J2950}AvBBQs{S zpAsK={&{!zl`E4YZ&Zf3A8<;KTwdnsu9}w>`L@{3y>Q2qNbe#ech!yskq(7w?g!o$ zMP@(yyWNT#Wsw~Uo7(*`w<>a4QFXh)?P?=?l@zq=SyvZXTb9=D@b$*X9#v88x-4sn zoLu{RyI$e%Bf}alxBEr*IWo8TWV^{Zf+&xVKek(bP7>8sw5?s`QdyLR>Y8>}d#Xp> z(Ou9k)k-@`(|k(19`E#`TpUNVGtV-LQu6N8uIF{LsPmy6+okQXijwtg-|pH%yD0Zz z&h09PIz<^xF>kjt)GaD{k#@Ur4xUi~neT(Q(`Kc5~E_)v9hQR(>C4 zf9x+;r$alVq8`3>b^UWsly^y$>!xQvMlBE*xO$2XMXh&AbML{%-UcX?LuGV1JwGM9cn zjZq=ba$U4{wnSakO>(iXdLQ+n=VO;`o&Som+jPq%^sFe_`Tj+hj#A}lm6oF}2WF~8 z$9e8`2}sw9o;-Vti(8O>bm7GnE_2TrNBdRIars-vB6^P9M3<6{Hqo0V4Rz6Oc8Fea zrl-rE8LrX&%EMg76njKV9eiAtkMNB?Hr>&sG%Fz5@Up4P;enyi3mY_DPGoe9{;j>( z<@MmM(P^vRI`7Zx8J#76;k;pdzvz1^CC(3O21Rcjlusyf?wWz>e~=cC6vzn}VD^yzDZougHEM0XbTa4xv9J34JxsB`G(AEUco@p7(K zIuw0T5^9DR4=GN)tj%A+OKvz#oGYNEUL9q&|qvMze% z?ZHlOm%WZYZQjGF-+;H#555a^dg=BlI=R8iDP2VvlQGJ{>Em;0Oj4|g)9hr`nESq( zPBu5RVoskHIawUik6EYv)^YqslbAspUN~0Gv5c{3EOxv($}XmKQnq7MFXxzJIq{Ch zVeT;ldp>l$yloR2)8p48j%F5}Vk&L+IL4ZGi&=AIv*T^k z-Z9$xD;z7$2gID*J;!mB&CnQE)rpR}&ZA;(Z5`^U;XOVkP}0k>SLl?O2b;nj6MN2# z2^aY~?ix8S=Fui6$Gx)`$An4D9dp;OhD!)j@LGI2ChyU0het;*#7yt? zi^Hzi%Q5eBk2@T0x*oH4%6^9`+q*ICnzlMD8gf4-Wz%Yhux(t-61@cu-5#0;De;ZSUR4JnTcv!QHRzZ=L%)=A2u#{izm7?8Aft`-C2< zv1K#T?LAIt#p`I*(&x;!x?*HRfpKI2Y$A{Fv~SI zD`=Pf{1ngF;UydF7yJ0dzW9Er{f)!Hv3tB`*}I54#&&)>&c0w?*I4E62HVFy>lIt* z)x*B7&w$wI!chA@kB7!S+Uady;X67uA=uIW&aV?$RXJ>4=CicqgGP~e28)LiLKCwIC{C#Y5ev+O2ja{*S?&s`Y zhU}01sm~p|7x6#GZd3l%&U(c0*dL=#*zJ6NCid=zAMM=NUW$DkzRgaecP+O2Uu*1i zFW-v2^Jt;nkgk8mhHjWwf@W4ob^Jxjxmj~%lo{sg)kT! zVEV##X}iy{M$e0F$CQiW4FAlwU3yFw=eHxlmK&}aw`9yC+i(N@xNOf`wsqMial<5+ zY*PvrKMucSGjHsLxEtM%+uRs@ zCGKP3ejDpPH{%w$eQ$HG+aGZTR%>iFc77CBskhK(QABiHxym$~J)INdw1uN>a=WF+ z&3fP8rhA{BxsT^GcD;+iQaO_f>DL@5Cs@tJJ=taKb_*oy4 zti$}R;=7CF)=|S9;zy|6wO+8=E&hbTW$VtTz2i-7PFaU11jHw~|71PBDJ=eG$PViZ zR$b!LdabwC@7F8de)JOSi|Yo&U!OD6dcuui@k`c^vktEs6F>jQ!PXHLljF}_>R~-= z*vxpH$6?mL@0%b0N3M^xbK27Q!wpW>4>i}s-&V1(UOr$`ysCq)^^gPG;*WMxwjT0y zcl`A6pR88c{uIApU8B|GIY;AfpQy5O{_}LaKUZLNTlrFaOIfOx;N31xt)cBn#d#wCtX2*-(Z?Q^=e;R+! zVU^Vu*V6b~gXdd~-d!DEw`q#ipys;xnYTt-%^1@h?^M~(>O|~^cxU4-R_Tw$GMZfW}jH}i7KfQcaqg`@KDIxVVS*n zXu{&@S1skAM<@Jn^^9f0_DKni%|BbdG@6-kBJ2lC*Guyg4t~GMa&z#qguKkb^yGwj zW_1>qjj|FNR+L#RPRLJ?KY3y?aBWFKML>#0H{a@n5r-o!2E3?Cu>AD9#e(zA3H}qV zTAZKwG2u+i8H)xhQR0Mlhb;P+$PyPF_`xFTj8#9ryC~jpRvNC+T9}YO!i!h zLvQR7l_DlvjF!75a@R*#`0VyhOt*iWZPbQ}1 zoi|sSdLc1${84lD;a3ye*X%X7>U}%0Y2jA$PMz*2>U_p192A-O!}f*d*L)KaXBbU4 zf9IK=c;>$9ncwm#O7u_YZf@sYnYeFEnE5Hcmx+BFeaxLhn-XVz?`-~{ z%ZJ40mX_wD`wNp2e%CXXj*%s43{o+_H%lw&R^4A_D_0vPJ>1c3)_J!@lABAdnc-Rc zq)+k1X3c-PCHc(CF?*Wnla#8SWR_SLl$3g%GmBE~l+=FMU9)JH9!bK_m(5ao^-pSl z{+WTE*CikW!1zy->)~S4UlFE=3W(zbICq;yVe^>|SJgYg=*Bjm9ifx9qBAy<&Fq%fq^+3u+f7&s;4tEgHKjdEB_aOnPQ*OiqYsHu(2L2>Q{^V}9$rg!dhol+A06)|7yo+I z$SEaZq>;($jh-okCuo=iI|ihTogp@9NDfb_S@_=g@X~H6 z&1)Kr1FZX{Y}#IFoR~Z`W&h6w#sgN5O|ie2VVvYPH6`$mIOCwAIVtIh4~>uPUy|~o z=$3JPk2NVfntw5FFWi!HP3@HN-1|FIhS?u9KD7MDl+EG0jBooLP4OGG$vCp*Ov>El zD~!3{e@$^aIM4X{>YFJG?oKh@+v#3PXx=E}2`Z5(yFU&vw$4gOnQ7hKIQ>LMN^-X_ zl=2uTrix7#N4$eV6jsLfv@F4}#Q@eMQE9 zOp~RqU-!-^zms;V*Nu9k8cXBUIh7SgWuL85+nW^_B@{WOZX1+gbWHAr2Q9qsKshuI3ZcfwWo4J=^?GOits-SHEtTE4LyI&@Lh^k+E|VAhA}Uk(*9a@)NqNK zS6V>XK0~Q{V46z*ZHCJSbWB_FaGhb|(jI9m-Ip5vb!IB zbNGIQVWGv$v;&{}8Sd+|Fzw`0SR~f2OzYMVV)*lK8`HMU@-eI_-<~$T+S$;^bbngK zR4YS=K}XU)R~i^duqd%C(|Ufi!~sxL%_Yo)i+KF@z|An1BOZSR`~gK=A<(&X!^ z3=StGrR|p$8vLf2ohCkzWpH}vvor&nM1#2}D$-(q;|vU*zf3df_`AW+el2MlnO6;( zH-An$JN2A_Yqm7K;KLDvAVGG$lMKcNbxaQq8)-1?P>=LI#r+K&-w#ONzPX!0%IJ~lt}bB)y|{_# z3(|cJjyujuAG^}kAa?hn^jCH^2GQ?UrMsmY8T>qDbGpVlO@j`ZJJWx5mm1vfbRa#U z=%c>ctz+ru_Py5kbUdH#)a|*xLp~MjH|pF?ce|ad|HF<)>6hoG=zo^PrRO?F z>xXYlOTS!sPk-RwPtx0+yP@yDz9fCbluP-kUm2`V4bE3WO* zf3;VXAz!*#zuH7Cqj&f!{j2BnGB(Q=>PL8+XUxo=u7BaNea7e0%G_j)Doc4mAZ|4Q$|i31r1SE}{=yB*IM zwy#KUZ^QYFUMq6+ZXdap@p?kC-l^`tXY}tKr8n%&8m$vxp$^cdKbNl@Ze0R><~Ra zS?A2R`96BRvU+E3EOpVdIW;6Rw$@tj!Mw4Vu`Nb=CLN|_ZV+kd1?tSte5_FSg#u5?`w;nmFS z3vs#wOYda*Mm^HSo{6w7(lU{!i!zxgtBYeYajY)t$V6Sbs529F>*5@lIF~NYnTd1j zq77MSi!R!fg|_LUjag``F4~-hw(H^=vT!ZBxTY*zn=Y;~3)iZPYtF*8>*5|{;a=$C zo@C+P=;9t_;a=(Do@L?Q>Ea${;a=+Eo@U|R>fjz{;a=);t=;aTY5nPlPF z=-?S;;aTb6nPuVG>EIb=;aTe7nP%bH>fjk?;aTh8nP=hI>);*8!n>e@cOnb#h7R75 zEW9f^cxSTk?&#nh%Er5-gLf($@0JeUv246+I(X-@@$Tv19n8kNsDpPh8}FtL-qCEl zt2%gRv+?fg;2qA!yR3tEIvek{4&L!>yz4r6=d!1&0qc7;7Ph_KS=%9~eqp#?o z&t#+TXrm8hqc3TrPi3QTX`_#2qpxYB&t;?UX`>Hjqc3WsPiCWUYNL;4qpxbC&t{|V zYNHQlqc3ZtPiLcVYom{6qpxeD&u63WYhw(^!C0V;F(C(IgEq#99E=s(7&CG(c4%V^ z$-!8njWHz$V~aM%m>i5X+8A?kF!pF;49dY+q>V8t2V;{q#;6>ORoWP{axivjV+_l| zSf-6JEeB(pHpaLdjCI-=^KvluX=4n`!C0t`F);^YqZY=<9E_D(7&CJ)c4}b^&B0iz zg)ub;W2+X%*c^w=tc5W-2V=7q#^@Z3)mj*{b1`;nVGPg3SgwUJ zJr`rU7RLBojP+U=^K&uwYhez^#ay6;IUyHwgBIq9T+9_(m@{%QcW7Y_$;Divg*hb` zbBh+{m|V;?T9|WkG52U;4$8$`q=h*t7ju&q=BQlERa%&{axr&lVGhg1T&9INEf;f} z7UsBI%yn9r^KvowX<-h`#ayU~IWZS=qbBCaT+Ef4m@{)RcWPn|&Ba`*i8(bFbE_ui z*e954H8JNt!Q88fIrs_YVog#~VQ$vM9Q_1ywI=55Cz!i6F^50FT&{^Z{R!rFP0aC6 zFxP8h&VPcrUlTIG6UYLZkO`hZHqeBO@C34gCS-;ukR3E3Lp*^jp$VDd31kaR$QVx` zYiL5|cmml&6EesX$Re7MNuEG9(S(fh1hR@IWR@q8T{I!XJb^5u37O^zWE)M$I8Pw! zXhPjXln2>K12R+|WGM~ERC$oCG$3Q;LDtfM z%#{b(O9L`k9%L~M$Ygnt%`_mRpGGHELK@G@+d5{e?AS32MR@8vZmK57}1( zGH^a*VGYQ{`H+n@AS35PR#u11oDbPq9Wr!2WNCHC)cKID)gfc&L)KP@%$*O}TOBfZ zK4fuq$mIEu&D9~J=R;Okhs>T2*57}QGYk+*L z1=O)7$j9119czSqtQFL;X2{3dK^<#|r&vpfCYYTO(F`i;DIu?BgH zwTL>_Bu}w6QO6qPDb_0LShGCE+C?2}n5S6FsAEm@6l)uGtZ|-Vt)q@L&r_^@)UgJ7 zinWkB)R2;9#o9?7YpADKOQ~T^^%QF>HLS6oVy&fyHP=(Dz0|M< zdy2J~8rEb_u{Kk~8tp08YHC=sJ;mBh4QsfkSj(wlO;>=mof_771z78;Va->7wVxW+ zfCX3!s$or7fVH6-)`$gIE2?45Sb(*o8rF~nSWBv5O<91or5e_l1z2mUVa-{9wWk`^ zpaocqs$or9fVHU_)~E$otEyqmT7b2y8rHA{Sj(zmO09L3g1F9mX^0GE||{cm~~uDs&u$&~>On=TQjV zhbnX+h0uklLMKuP-H0l5B!$qGs6uB_2;GS)bSQ<;rKm!uQV89ODs(J`(6y*S=TZpW ziz;+5h0w*QLMKxQ-Ha-9G=Rm=T!vV zmkM-XMbL$*KqpoN-Ixk=WJS=GsX%8|1l^embZAA;rKv!tRs`Le3Uq8m(6y;R=T-#W zn+kMrMbO2mKqprO-JA+^bVbnBsX%8}1l^qqba+M3<*7iYR|MUj3UqwM(DkW6=T{8f zp9*w<#n1(+KqpuX-Jl9|gvHPmsz7I04Bep$bcn^!CCZ>vEQW4T1|4HDbd56T9E+iQ zltBks3|*uQI>}<_CS}l37DHDlgU+%Tx=R^!n8na#%AnIMhHg^^9cM9goigY=i=q3J zK?hn4U8oE?(PHREWzdlpLsu$;&a@c1QyFxq#n7e7pi?b|ZdC>yYYB9%GU!}OpnH`; z2U`MNtPDEY66j`S(9xDaS1W_gwgkFc8FaWM(B;aY(=CB+R|Xw#33Rp8oJ*j4mO%$y z0$sEWI_VPVre)Akmq1r7gU-4Hx@#G9*d@?q%b?RPg>G9JI_^^Fx|N~xE`{z}89MM% z=)#qu6EB5sTp2p@Qs~N+p))Uq?pzr<^it^3m7!BFg>GFLI`&fN+LfVmFNN-189Mk< z=;D>3lP`sCUKu+2Qt0ZHp|dZA?p_%>{8H%hm7&uwg>GLNI{s4V`jw&cFNN-388(1Y z*aDPc6DWmkKp8fIQrHTVVKXR&?LZkegfiF?lwngSgKa?>Hik0T8kAvkD1+@m88(PA z*dml+lPH62LK!xSGT17VVY4WM?Lrwgj563Vlws2-gKa|@HjXmbI+S7aD1+@o88(nI z*g}+H6DfmjL>V@cGT2I#VKXU%?L-+ilrq>-lwngTgKb3_HkLBjT9jdPDTD1r88(fNfC;HpU9r8l|u~R>1Zsg$=R- zwn!;#l9jMcN@1g{gsoBvn`I?zmr~d;D`Cr&!lqdX+olvY&Pv!irLcKc!uBbJ4YU%r zP$_Jpm9ULUVI!@CtyBt|X(eo@QrJ){VM~?5rdkQxsuVWXO4wSZu(?*k_9}%9wi32j zDQvQpu+2(gqpgIkRtj;r61H0@Y`B%M$G%~IH$t6+PU!UkOhTeK85 z=_=T!rLa*~!B#DW&AJM)GRD&xZ0cW5Z+yMzV1l8aYNWdwm2Dd;0jzKlJ1`==%s=+;wfP+vCE`kJ{glcdT zB;Y7igR39`XQ2k%1qnC|HQ+Kxz-g!fw?P7qLk+kN5^x@BzO4K5D@IkbnbH11^XJoRH_>hDg8> zc@D0K1e}rQ;EqVZA$blii3FUI=irt|z%h9au89Pkljq=`NWejP4larWoRsI_rbxh1 zc@D0M1e}%U;I2r(VR;TNiv*mO=is(Tz;SsFu8Rbmm*?QVNWg)44laxsoS5g}#)!d@ zc@D0O7@V2s;LeD_p?MB2jToGo=it_e!LfM`u8kO+n_6&h#Ngo6f{P;tC#M$N95FaL zwczTA!P%(=cSj5kPc67SVsLtD!R--)<5LT+j~JYvT5x~F-~iQv3nT_7s21EHF*riC z;0lSs8L9<$NDK~9Ex1HtaEfZdEfRxcR12<=7@VV8aF4{`Ak~74BnBs`7ThE;I7+qP zDv7~ass(pR3=UH*xJ+VjnqGk0BnHRn1-MRPaGqX(`y>Vj>IJw^VsN5ffEy(qTi*2r zxKd(pre1(MB?gD;1-MjVaH?K_TO|g^>IJw~VsNfrfO{nd2kQm6SYmLpUVxh=21n}! zxLRUxwqAg{B?gD<1-M*daJpWA+a(6a>jk)8VsO4*fcqr|2kZs7U}A8>UVs}W21o2A zxME^(#$JLuCI*M>CAef_aLQhSTP6m_>?OEnVsOr0f_o+g2kj-eXku{EUV@t@21o5B zxN2f>)?R|UCI*M?CAe&2aN1si+a?Cb?IpNwVsPGGg8L={2ks@fa3XNxUV|rf_oQZSz|pG% zS5E}aULCl5B5?TXz~vKx(^m&>p9mbkI&l3&;QZBr`zHbiunt^65jcT$;0B7o5v&7O zPz26k9k_!ca0u(bB@}^ESO;#Q2pq#Ya1BM^9M*w*C;|tu4qQYLIEi)OCW^pOtOHk3 z1kPd|xQili80)}g6oJ!N4{oCf9LIWa9Yx?g)`R;f0td1lTu2c(k@et4iolVq2Uk)A z&SX8flOk{^>%pZIfm2xzZlwqu%X)AvMc`c4gL^3g2eTerOc6Ml_26cTz|pJ+S5pMe zW<9u@B5*kC!Q~Wz(^(I0rwAO+dT>2O;C$AD`zZnkv>seg5jdgs;D(C85p4ihR0Pgw z1Gu9ia7Y`#B^7~F+5m2;2prP}a7{(voHl@aDgp??7jkb zR|pR8D{y&*;Pk!%w^s;`?<;V9h2Z?Y0{2%44)7~*fra1%zXCT{2#)Y8aD|2748H<* zSO^aBD{zU0;1s_Cw^#^{@hfnRh2R{&0{2)54)QB-k%izSzXCT|2#)eAaFvDNEWZMG zSqKhuBe={$aGD#zZ5D##+z76-5S-^maG!n;T6{WZAnLU7<;g9|SNC;m0K@j`IqUxOCpMfU$4hZ2x z&;(xsA$$s&;9DSsk3kcB4TSJHXoBy75IzV^@I?^9C!qw@Fd1!|3gAhIt&G3Z~!Y85`z7azBNHoJ&LI|IUX82AB z;X~03UkV|7Dw^S2A%u@bGkh(C@VRJ)?}ZRP7|rm-5W**;8NL|;_-Hi4S3>}wjb`|6 z2;jrf3||fbd^(!p+aZ9DM>Bjq1n~K2f$xU^J|Hdd1rfj}qy@eq0{Douz*j^7pOF^$ zjtJmG(gI%+0enhY;9DYqk4X!BO$6{cX@T#F06r)!@I?{8C#40xDFXPYw7^$I0H2i> z_^t@x!_op@76E)(THxCvfR9THd|d?ad1-;~ivT__E%1dAz$c~!zA*y$$h5#$MgX6g z7WmEx;6w8UzBB^()VzUjjQ~D2Z{TYqfX~ev_}&QMgYyQyI0E?Oyn%0y06scz;Hx8m z&(0h8?g-$+^S?Mc6X+VxwrxMAm?AP5laNG0A_g5TjHpR>=^vR4aDL5W`d}mdOy)R4ca0 z5aU!U*2xg_R4ew$5Cc^!7RnG4RVy~i5F=G9R>}}FRV#MN5JOcfmdX%QRV%j25Mxy< z*2)lbRV((&5Q9}K7RwNmRVy~j5TjKqR?85xRV#MO*!28^TCrS)n63w6y9_a255#&I zV!j@T{W8RWJrE0KhzWZjHp~zs_CTzdA!h7>*fB#4*#og;hM2MkV#^FMW)H-g8Dh>J zh&?mJpgj-Y=)S&2V&a{F>VjUx*1~L9*BK2 z#K1ie3ulOldmuK>5F__ctehcc?xEN@LmTUdV(APqbq~eX8Di`ninTMu+&vU~XNbXj zC>GBUllM?;o*_o>p;$db%-%z>dxjXkhhq5*F?|ok_8DUQ9*Xrd#QZ%J`)7y&d?*%B z|Gt9{#ReK;1RshOG{g)(6gy~$A$%y7&=6DjP;8+g#;{JTp&{n5PVAu}2C+^oq9G=+ zPHdtfMzKz;q9JCnPVAx~hOtg8qamiTPHdwg#<5PUqao(8PVA#02C_~pq#-73t-&*AV0TNUX0R=J%1K8^jVDVu~BY z78_!W8^jtLVvZZc9vfni8^j_TVv-xgCL3au8^kIbVwM}kE*oN)8^kgjVwxMoHXCA` z8^k&rVxAksJ{w}78^l5zVxk+wMjK+J8^lT*Vx}9!P8(vV8^lr@VyYX&RvTih8^l^0 zVy+v+UK?VtAB)8{#AH7fn{9~Eek@ko5VQSQ?6x6>`>|MV<4o+($6~t;G2V~GdK+TC z9|OCK0e>tO+z=D~SZufqfBbhV4gNmClhzyj{hI#0)!^@Y)b@qJ-+!6IVS}GX;#;Q-em;#smkoYi zo4>xL8%Yym#OQj1pXZg|S~lV5TQs*r6Mo+RHT7!3&p+>#K27+2obirr!tW>gB@cV3=o!5llZ{$6l+4TD!^UO0%`2A1m_;M3I50l?{vk9M%5fSe< z;q&5m;Ik%te(t62Z^Gwk+wVU%;qx`2D`Ry!O_a#W;`Eu z+gY0Nyjb+gux30zqCLko<9Tvm%k*YEUqWK$G~;znKeb9{O*RS(GZ^rX1)&ARNJm1#8`cpHWcSn0%YR2>L*atV8@jToT{jeF& z$7%aoH0ODFYov2?o}Z~_x;N)}x@>wtbDpmoZbmiddHX`yz~(%EM;fD>^E|%1XmWF& z&xtOxn)AGV{`IovJip)Q`E+xh=TCq5VsoDF@lmfg=Xw9_SMN3F`QLNsC(U^ur2hC# zbKVcB<9}$*`@-kax#qk-4&+>G&if?d_TA>ZUrNf17QAnsYOrs?`zK>T*A~2wTD9%f zg7?!CFNL0?FJI)gx1q5;dvCb3;(U2=x@RlSo14xCw&MKhGb*MP=h2Y| z2esmS+B1GkE6%I$Z_jAO`SoJ2*{wLwez~T+73bR#jtg3G-hFz(vR0gba~{0jiu3UO z*_&E%J`Vo%lUAIUUB>Kf#rb*d{vTR#p8h%VmsXswKY8z3E6&^TuK%^-{5|V=qc!L8 zevj;1b3XqfuWM`0>%X4w*_!kF#>CLpoaZ}yVQtO%-Zx-GYtH)@R;9J({2$dSt2Ot5 zh_b@g+z(D&scFr9q08t+t+_um>{-#8`^3}!>soWa*u3(?*4#IWn(l7R{o_pjx2?I4 z{Cei6*4$5?8E~mJ_m#sR+-%MLWlQIWt+~$xKG~uT_nTpVIkn-w(=4TX8}2_7cKf&C zJ~Z4rstxy}(~AeR;lA|vPI4RWPhXFp)Q0<%+gCH&aKCcwS=xsC)*FkTY{UI)-|ZLL z{Qo|dy1EVbvr{|YZNq)-8}}V;xW5gU|5Y3AbLm&UYs3An_24sYxbKa4@Ao#`|9Z5! z(}w%t3$q*Aa6epfv~^qVi{1KkYRmmG;e{S;xlca0*|#nC%YKP*ZMkoDeSb(>?w?P! zPHoG5v?gb2TkfZJ2lCo-U-jrw*_Qk3xAUH9%YF9IxtH2ZkonGGDmizDR zo1eDjK0IN_zP8+tN4Gr`9ksFgZ9iD%2uARXa4Z; zkBj!qBOZs}uxCE;^wYKW%qtchZ`O|ag@cDfereh{KwZ?U;`|`^SWK%uA|+X0&5|a-(8yJLV}re>1Ng^A$^*=i4!F={DxocFbQY zR;_QxJZ8kDt?ii4yw>ZBcFb!g=N)Rt{ATs`lkJ%2B;UW(j`>b??BDH}_jH^0upRTC zh;LdrFb~?-%-MnY(7{379hetc7y3IeKk`2m>A*Z`QL6zC%$Ft&O?F`3v~FR#1M{be z2Xh>lM?KxV#DV!#_k{Tl%&YvLSmMC^YUA$L9GGXlQoF%{`PS{w?GDVlcIEGJVE%P? z<6#HpVXJ>T<-mMwtLtS4=4Bx%w;Y(Cc|Kp~z&x#LuU&iQYyBTOw`bl~9OTiS`CI$! zfcDJeI<1as&wTFL9|p8%UN^PrsP@e7)<;Zg&pa<_=FIlY_ol5bY0tdx{CD%)GynVY z(USJe1MT{(YR`P|<4NzdXI^;d`R(nQANKovPkZKx-LD^R&wO!8$Di9XZ)}lpxjpm8 zb_KWEGmorXRo9;R%yS*8{&r-(>-*Y6N9Mh&K55~^{5SK2 zlN0mc1-H66F&}=^+TV$J@pnFvPRx)0u_ib%Po6bC$%*-LY|%s~=FL+U&2VD=e0uF% zC+5)`KAY#ne0u-)i=CKPM_pOz#QgeE?K&ss*)H~5otSUec<)8g z9$)sY>CAk7$%zrp%>BUFzT=IKLtWT^>~lxf&V_x=Pn%A=u)q0p%@r5+Iq@&tc45DB*jDetzUQU4-JkE=)k_{o=;Q<_D2^S2XtVc^r$|m1N)_vs}no0Z~E=nj1KId-q|^~1N*48 zYv*-fKXrWJ;tuSqA`4b_V1IQyWnBmMS!<&|?7)6&z5C}K*ms?6JkWvtSHk7v9oUCm z+;^b^`>`z>{_McMY|Das9oV0p&ur3>eVQeqT}Sq7$2_`rWZ$;zkxxhVZ%>{H?#MoF z?T+}4?B{O1Ftj84x>-4?9ogTx^qbm|ecqp)^E$HMyLqd;Bl|wL15bBk|5vv9#g6O) z>kHO&WIwniVPi-3g$q0G=*a$X$+a&#vQPYc=aG)=7o8UU+>w3bvhkNYvVV;Bz15L@ zWXpRGJF=f__@+fC_LZ(nojS3__fwM%&5-nlf$|W=*)h3=l4mS**B*>Ik7YQ=l0<< zIOwx?QI{26$P4WLXl)nr0}DrN=|Y}h%9YQ$kS`cmwXX|#gK)=VUC18< zy>qS$d4!0Vt6j(^3_5zJ3webp84X>?FFbX-Raf#1A3o8cEBS^i4xU}fJ9xYi(3Si{ zmVZ=N@(^1;P3THKqDewhSMm}Qk51@Heq!g??5^Y~+%6V&C10^1yQV97i+^q`>`MM( zTG1}n9 z11oQLB@c4oUR_u6A%lwST*-?ZxZ&hVeq>;FH&^l`UtjQZC0`OZHr$oG$&T+#SMn!* z{YSWxM_KjBI9Kv1EqhOQC9hJrCf}9(%1Qf5SMn@jwgs-_TbA5>(UrW*uM^j}l79&} z^sXy;n4<8HT*=35eQS>^d6_?2A9f`_<6L~wl{`(R2293ODjadwRa@M&9UQ)fPAMN8ZOi zb0d!w-(#N}`J{xBAKb_*MIAWnMt-SF$3NW2GhNO6$Blf`+U@mj9 zgDu{8+?{+_#;@ny$%}RDblsi&*wztu-N};$%zx}ozHHHs*4@aP9sZ+3H}YqHcJk~- z9__Ee0lF4DwEV6#vKx7|CF}clBfl2-V`4Y*Y@6%Tx{+^d)hn|bdA9+{1>MNMO)9VK zMjmeTn+v*;kMr68VmI<~C$6vVMt*Lx{kz@B)9vfKy&L(u=A*voM&8b&@Y`fGC zq8oX<-?v=oMm}%J;p^SV>$UsiZa4CKIgO9Ik>`7@OPlWG``!-j*qyxJlS4ealmCmJ z9MGLS;DMsZ?&Jggp6TD6yx`PV6T6ci%zrPfJ9)z7ozuIMFKqE`es}VQOHWpGCx3Y3 z($n3^Bf8yO+MRr2xBIKQlUMxb@rLf?7gySC>rS4rUAx`g$v37tAM8%vadxNU-N`?u zbUojlJY*ZUYu(95E_3_0J9)|9T^qWSpKRH+l?Qps+Kw(Bh3|_(zNgGLH=@O zi*OI}n7bOR9^^CM`)`;BdClp6rFxLxyn1np2YJqj6SF+XcP8yG^&syV^2vM;@}K87 zJnumsbkr*=J;;YHng6y2dC`~hws?>qos{;O2YJ%l{q}m0FCE(Zdk^xaIgV#M$e${1 z=s_O!{<*(B$fst1`2hC6)vC44Jjt&vd(y#^JZs{#uAbyukC;B5Uzz6nFldy@YRZGX*^ zJn+R+cRa}l4_x!ele}>Dl$KuPhx_$#_99Pw>WaG;`C{)4zFy>wduN7vkw3ofY4IYD zJmta=FY?JRyf(&*ymIlF$zJ4_+qa$RMV@*3-nm}nn`c$nyvRHI^?A;V{PUViFME-P z-uv!frjtcbk5GJ;-~z9}4Y3{`_s&;cnjK>wo>Er#E@~jS<1#J1O@ z+V$7G;R7-ztoMc&*nj8)Z}@>DkvqNN3FfTd>kVJ9!{K{xc!QM{r@i41I{)^YH#|br z(3{@y33orZ?+vdo(z%Hb{KA0Jwm$F-r+)6}1K-d*%F_ql;fEFeKJX8rcf)<)AwrW) zANYu)n}+$oOEfl3^?{!_Ix)iso+5PnOdt4)5W8X@c#A_5Y(DT8weK(Vfyemr(Mvw? z8E%QM`@n0oU;VBR{Kl%Q+kD_TJ`dUL1K%;H`hX9-$LITw`M`gyZgb8D9>ihP?>_J$ z9hcwoffw2K^8+9FkzYGE>j_V?HmzMx_>#LTI`@P(Idj6RC;UmWLtsyMl(eCdJ>gSs z&+pe0UZu;<;XUD3j{lw76P~4Ok10LjTkfRh_Jnsyd$zbI{7d4eww~}X$9`Yf6F%lw zrVn#y@I33@Zqf_BCu&dIUhqDtr#tq7|Eas}(F-2Px21nC_@H0h z!+XICbq=xif*(3NU}!IRBCoMydc}$_x}7zt7raqI@r+*ZN3Qb=d%+`>KVQ`gK56`l z1-;;v_PnvQ7yQz@8(!-L&*ZduT`%~i#t*jif_Ez1_GvHpr|H|j?gbC^^R^?s;G@3# z@MJG|ss8U@>;*p+_3rgv@KhhX^=~ius`alv>IHArWvQJn{FVLFj=u0%^U7R(;j;>6 z`uM_Yogd%V7k=x|kZ50cuHc9SU-+($UWvZ&US(~^`NDsV`EQCZJlN)6a(&^$Y~K|7 z!i#`+eW>g+H6ye5)@!+N;0r^o36g-?i5l zUTxS*M}6VfPUZaU3(s~Y{*o_z+Ze~ceBs^tU%u-L|F-d?248r%C!cKT2Osxil9M02 z+;UepKlr($zx(*X(^Y)X*AKq#wUTH*csu{t1V8w@pvNQp;PKx5daNIO-m)jB_`&P_ z)i2i%e(%%AbN%4??tWh52j920^jSZ6zde1I`N97Uzq-l~9&qsM>;2#Zw~zY34_@&3 zW}o@N51#n=Yd?6x=dzCY!56;oe9{lzFz%}he(;A;v#$BUBd&G1;|HHuy1UK~Uh$J@ z&3nTyPP2394bNDn;mA>JPuW z{@GLh@Vt)aFZ#pxo(j6|5AS>T$vgh=zqu#s{NaJ4yqX8V2Tv+!7XUAOc2}nW_~9+h zJOki~PmSmu0AD=z<ba4QDv$?n?0N(kNZ=MN&f40>w4SRCZwJ6jf4y{b0Q~e1dv*lC zQ}?;?MF4#Dg-!VtyWbAo6bS#G82V8lJpApT-GT7&X9M;J!ppbr^?e}x{1e@O4uq$V?f7dT ze0^-2>w*90?Hm3Hguicn`(YqF{^^TN`@rX4KiakryuM{uhd%K8r`C7t1JA#0Nv}Te z{ofY{^?~;foDkgy{{Q><{(bNPZ0$b04}O3XkH_@E7Z7RIyUQzZ=u=Iwtew0%y_0lUwjPBEZzFzXE^h3&%XE?uD;v1FaCzW2~mCVIc#p- zuP=UwsXK@E#rKeyJ-RRcheF4ReZ~H}9N9I!FMf!L(`NU@7vb5mq%Zym_xEf1;*%IT z@|nK)C3gJ%LSK9nBbTh~i+{qc_gj7OQFPzGu`hm#l*!xr;;Z=Lzny*YSBzi$O<#N# zzTJ=X#c$!e?L=RE7Zdya(ii{5mp@$Tiw`3u{bpbM7+tUa*B4)g(*B7bgYcO= zb>>VEeiQfL--7U+TzuxwAp9rap1l)<59Q~8x*+^0_BBm|@ulP*X%mb;;494H$7dR|Hu!<|I)?1EEpe5?x=ae_+idJ^=vS{m^nL^2IG(MzPvIRpUeY? zw}SD@{2j9~7~f3O%&o!rXCfDW7L1Q((blhm@zd0w_%;|{&659)1>>)Y>u@F*pG~XK zOTqYU?vA`3jPIsC=bvEwHy-mJ1mnY*w$cc}kMq^$Rw4LuV)i(O;LkbseU}ii|DEQa z_YA?WllZ4!2)>=L|AIsC??g02hv4HG)x3WQex7Gr4-3K9bIN{n2>u?c!-NogK3}z) z7J}brLfhOBd_VRri$d`K{A^T)i2d)p^TGTO{6HVwdM*TC(7wydLhuLub@H_kd_sN) z)`s90s@d^g2)?0fZ*2>~KQv?U&JcV=^>e=t!B6zgghL_tin6RfhTt!X@;VcO&!~IT zOCk7;y8L!61mBVGm$yUk9}Qhq8zT0NI5d28{hP4dEm*nozJ`{h_!hbu3;!|q2 zzk4WtrI%jm6^d^ucv|03{7aVtBSY~qt-Wsv#m`ju<)Bb}O`{f!48`BnZ|K-id`{Lj zlSA=4B_7EN#rHJxxx7&PPp=Ft3B?C>^l^14ekkY9o({zqH6#D|Q2bHfdc6{gPb%W% z>QMYr+ZL<~#WxihwmB64)Zt&ZhvK8kS-dM0Kb4a->-ee;o;?(bzv`KJKZfG78s&8+ z6u*_v-d{uUT{WF{EfoLNUk$fH@nQY)+Wk=cSf@fBhvLgReW*nk{;VsL+lArNy8lmy zF#K9hPq~NT+X{E`3B$jY@n%36KCTyghlSziI`~m+7{0FNu?b=LyM}%>EDWF5%L${y z@Oxd}H$DvCSLA@HVfeq6eVr4A5A0UloG|=gqdzGN!x#2h;Jh&WVLjG86NXQ0S;rT` z@QXEBxI7HsSn2&WVfe>xX08tt`|p~4Y;zcXvP;n)h2blkymnU@{<2?Md=rMxEIs#7 z7=E+!M~;QzJDco(It>5W#f2Bc@S#n;@<$kcwBO?Y4#Sr=effW3_|q=`Ss#W^ZJMQ7 zIDWNXm$nJVx0Zg#2aQ;rQ4_mV1WdXWRF+Z#cfT$W}q&_}ktc85xex&G{uu zIDWV469dEXyx+MqSz`085auM5Xt=k@ZYaC~-QpKJ@q zZx{dbXW{tnEcd<)$A1^;d@vjzUavmihvUbyAAB+#U*2DnehJ5)x2NcGI6l3F3;qnp zuQzzbKjHZH>ettXgFzjz&h{1AOtIB?3R-S6>c{z!&)2$0H)}2mbfomt z;1|5JcxnW`!Lt=P5%>o`$|{J!M_7|o8iAiMGO{KDU*RRUrz7weRy8h)z-QR}w`CFd z4Q*e)8iDWdk2l_oz<(HD`A!5r#HYq=i4gnW?UUX+BJd@ie!MFJf8w>{Uq|3myt3}w z2>gma6#Wo^Z}A=LsR;awGh3gJz{lA2#N`P5jGw&rX9T`R%jAC|@HcMvsExqq=ya(e z0>5MWo6RHfJuaKrHWL5iwhqpb_#i(&+9eV{pS65nRvlFgC$Hyd2GN8;n$vFbA&+0JxN?Dl0OzRtsM?vKRZ>EHdkNPM0JYmP_a z_gvBGOeDU~H($IMiT`u4-5-(oK*v|#h{O-t`qrJu+46<1&Ug@sKh)v-$C3C%r^mF2 z!Y}&T`nFN{Mn7!p93}SO z6n@hq?^&bponB}h7={1zhtv^K_)y>6I64YHYT|>mD151B24_U!PwoFoRun$f=Pt~O z!mqleXHgWs)h)BjqwudT+G>l!$2#E7(^2?Y&jc@y!q+;iU|AIY)|H!9Mv49R{POba zQTSc=c3mHZ?{#g`rYQWc6Q0}}g%9@T_D`bl!%n=kI|^Uy+xB~-@W<|rJQRgbc2C9+ zQTSz-EjSs4Z`ShOxhVXz`wm}m{f?=a9gY9@N_J5+KHwpv%cJoF&x^H1;|pHs^>j4;;7q$k(fEWN|6Cf4 zU--qt%cJoPU)s1j8vk(91#6@65#OKuZZv-4&m*=(<10>X`%yIh;*T$W7LCvNudREc z@f+Wsw=Wvs@%|Bqqwyc-b~+X<_P@u4izlP;BYVDcE*f8QXzrzG{K+l>SEKPM@BQmW zG=AlN@7;;UxBPr&Z8ZMn4ekxm_?Vynsc8&;X7jmLG5DIlj&+E^-|TS1B?g~!?^Ru6 z@H;yW@`%CryziDz4F2bYmHsjKpqIu4$KZ$Fa4{kVU-Yw2#Kqu`4(r}O2A}kn&j-ig zm%f#n7=v&6(aq5@_@{q*DlG;db!n%`G5D!3ZJZv1uexK@%ozOD9rowP;IlrTR2+lf zI`4Ev48H4wljp_YzrOz4(=qt4Ph>8N!H@mSm8CKGvKyx^kHMdvaDG(`KJ5`>--^Mn z?S6Da48HA;`)!WFzwNSPYYaZ_81GMF@N@Tk>GK$T-KQUY6@$M!dB%YleBLj7e= zW1k$0Z@nZYH5UJRLe_*>eC$6i$%w_z-fc%_EWY-D(=%i7w?BB0A1n61=YlT9vH0DO zMO4J%dp|eI7Ay9@*ZSP2V)4QI&tDjeAHHz;l30B4CGWlzEB3!vZ%r(I z`MW=?jTQUf>(=RaV)4(vdvS9tK6=)`|Ep8#NxxZd~!M#KYr3X=VS5ZyT0;UEdKnr=Ut5z`|o=t z=SD1k{a=&*iN&|SBJ5r){{0r6>SFQn2j71ji=V&4$!2l*`ajy*Dh_{t>qYJ2@cDP0 z>KupP|8jWeIDG$EE#2e9{`yzJRr{L2>j4>~0bsN1wpb zgVAyH3v^jziKA~|;;@7``Ug^44vC|WpxM3=ar6`9){Kgyui)9Rv2kMm{U%lar7VT-;ftaA41QhqB!~y;_sEl(U;J2byXbw2@B(&h@(&8 zi}O#%(Xa4s)pK$5Ee!1RLY&xtzgM@u6h|M!8-rKI(a(_f%j!7#8V=;Y6({!J?^?t9 zIQksEc>cXO`W*&#{vhuEeGhB5$I<^#;QMJDeGm>?K98dxVtU`N;^>RW`EXwx{Sh94 zhvMjyShVqI9Q_g-JdelGH&OKJsW|#4{%LzIjy?*{c^Bj8r)YBPavXgXucTj#qrc+R z!5eY(SsV`fCysuLyp{jO(RcB6-Gey#FZNGrh@%gq;)^En^kbawY8Ovm#y=%(;_1)$ z=zE8F`ZRoeT;l217*x?Yp1zGvN8IA+-&o$&GoC(F0QJyI;K6e}BKazXf{1wfJQhiKoxxxo0cl={LE&t|p$olWSkhkEj1+<;ex{^r77O^SOAj{{i2rA)wkw`~mw){C#MAe(%;TGQ`d`jE9f+q7=5Uk4@nZi2r{6vrPhZTs zb3ew@AM^aalkxP)xNSZYPruBVrRU@6n+Ykr6i@%mXUV_Ei~SG$J@9%w{WLpU-i)WO zCiK$nc(MP1DWBer7yBRRwzxK)ew#(<_3`xGyy4#%PybC?ZBq+=Z@h_4@3a2RTnl|hH+$t<=r=mOrO-m(QC4t?h5nBN?K z7W$HY@AZ_0{-l*}K4YOz=`WW>7W$PgKD)$1-_qRL7cKNJy_fxpg+3vlXLC{3;j+l4{x;4_q3+h`xg42jy?IIg+8ct=eAquhjIz| z#6n+`&oetM^hcfidAEf=sUE$)vd}NpzId;NzNs~P4p``)I?&>27 z^q7Uds@h{GEc92ca`@RopVgV+XD#$weX`)Zg}$rcFMhSqe>L>ZWea^+4c=ER^kXHb z{%N5v%lgz!i`f65BOlzhi2V<``}4mR`n7g8+_TWP<=W$+h5oHB10PxFFe6PriE4Pf3W|@t*rEUg&%2arQhr91qUmAUv9UZtn`1?HgvGk2R5fo7c2c> zPjzs!(iax&-rY)nSf!Vjl|He_K0a3Z#eVVewbD2CUk`sP{bTQS?_;Hp?0)B9EB#~_ z9m1^il}&9HX{Eoc=3cawKC{q2;;i(WJ$1rrrSB|nPk$@@XSd%OXr&LW?UEr@`q93b zGu%pFn&aq^R{GN(292`Pr&eX3Vx?bg`PH#j`qqYgIo>MvKjh_C(yjEdmCeYo($97` za+;OCww5ijtn{~i{NoHOeQtHDa;;+jLrzc4v(opL*mI7R{EFv7wB1S{pVxOgtn~Ah zCVgt9uW$0PomTq$ei^yjN}u1~hxb^;{)a6e@U@k`zaKx}Yo-5hZO{QLeSj_2eQTv3 z@UhboD}8~_KXKG5_CM@{zkaaNCzzRX+)BUT2fKc<(l@xc+s{_|2OrHlW2KL<$;ES4 z`UzLZUa-5N8CH?VA2P<>z1QQ zKV*9+7n8oo+Te~R{gH)9olW{At8%-V^h+!lXa5?p%~fpQgjH7?Xa@9bdr=l+5RT|oL344 znDljyOC4m=-#H;_h)JL4jn2bN`aRp-A8yk3`Q`CMlm5@go0ClXK)-)-lu18m;J7g+ zeW9*?sV4oQD{IG^^og$9pJvi88vo)1lfKdHv~-jHQ59X7^pR#>$}s6CjedKoNnh!j zDbr2*OJ8uyGU+pIcPiVY-_(6cj!EC?&VIQj{ij#{on_L8`ue&&lYZ1I$pt2TsXOcD znDnQ*tuHd^Q*Aq}*rZ=|@y!yGzSWg4l$rFe1_xG{^s%NLsx-y^N7+xWHtB0kdRSwM z{g3Ltbe>6{YqjTmlYZCiZBLr?y4c&zkhZzI=M2NnflreUV9j zZ29@cCVjG&^d%t(Jz;s-q@Q;DwpUEC|IxXgD@^)p zTP|H`(q|j`@Kuw3+w0R-nPUH=0}rh>#r{Xv2fS|5hdb_tH%$6*tvBB^>C63S=vtHh z+>h41ZPKS}sat1?{f`-&yuqYz_u<>`nDp=Z{rj#d_CMx|`JPEXumAI#O!|5oe%fr( z-<$5b#iY-7P{s!){l2^3`p~5BclX7urr7_Op>Est?>iVXW$Z^L{lHCM*kRHa9J2Rg zlm6hp{`&f8_uKiqHQ=O%r`+rQs!(og)soi9xKio;#L zH0duM9Qu_>pYfHXuTA=m+vI*@iv5rMV*Xx}{^N%$_L=k{fAijclYV5ET?b6D|FQoZ zJZRFNJpRPDrr7`3;lCU*=~q7Z+hJ4ef9&^v95Lx%&baoSNgs37)uSf;%$`@iH|c90 zb>Rn-{^qu)j+yj1Cm;FIq~E#wp5rEc&*dMSFzJ7uxaKEQ?0?+1&z>~J{>Obe=aflb zv^nl)lm6)8v8PS?q9Z#N(`UDzGwGvVx#$;@e(LiX=S}*m zw}f0U#s0^&XnN74&-(hYi>BEBxUp+~HR-z^k#)(W|N1-s-%R?jPu=>>q#rwH+hvo! z>;-eKnDl4+2mWr-r#<27?#;6%CjIU=^Xp8p|JIkkt~15{TfcFvH|c|~$f!5zhu^uW-u!=G z{J-@k{qe`6ADQ&YZ?1V{(l2lSn#ZQtf3wg2$EMhSGw-j*rr3Wo)S=N7`)@uK z)M$$RHzy=DnqvRWU9%cZvH#}V3mQ$a|EBZnji%Utv+edqQ|!OFWM88x_TOCjQ==*N z-}L*f(G>e{4!GH9iv2gQ{?}-V{WqQJ8%?qQ=KjZxrr`g6{EyiGe*EuZ|NHTui~aA% ze_!l>KmPB<{`cdbC-%P||9r9k{rLBZ{qM)WU+jNB{ybv;`|;-!``?d0uh{>7{Q1TH z_v7y)_P-y0Ke7M)`1^|e@5kR??0-Lg9%BFd@$(V;-;bY{*#Ca~{KWqE=jSQ*zdt`; zvH$(~d5it;&(B}%e}8@-V*mT|`w{!!pWm0*|Ni{`#Qyi6uivNG|Ni`b#s2r__bv9n zKfiym|NZ$qi2d)+=R@p&e?Bi_|NHa#5&Pet&y(2y{(Qc~{`cqeCicHSpFgqx349*K z{wMJH6#JjR=T+=~0-s;8{|S7a#r`Mo`4;=1z~^1;e*&L>vHuBtAH@DA@cj_`pTPG; z?0*8^AF=-le4oVrC-D6e`=7w~P3(UH-#@Yc349;L{wMJL6#JjR_f_nF0^eV;{|S7b z#r_ZA`z`i=0N;19{{#5`i~S$K^FZwX0Gam~ zAHefa?EgTXk7EA^^1KxLKal6A*#Ch%PsRQZjt0AH@4m?EfI%k7EA^@xB!MKZy6I*#AMiPsRQZ;{7W2e-Q6m zvHyd3|BC$|#QRw6{~+GaV*dy8z83pGnD@8X|G~V^#r_ZG{Vw)@Fz z*#9A%r^Nmb;d~|be+cI-vHwFje~JAc!g);W{}9e+V*iJ5UK9I2g!7x&{~?^`#QqQA zd?)sQ2C5YC5U|A%m16#GAv^P|}Rp`0hh{txARDfWLT=S{Ky zLpgtn{U6GCRP6sy&ZlDkhjLyO`#+TPtJwdcoM*-U59NF-_J1hnU9tZ|Isc0NAIf=H z?Eg^C$7277a$XkuKa}&c*#DuNr^Wsc<$Nvne<nFovH!!l zf6Y%_J)HZP*#F_&&&2)@=e{QPe>nFyvH!!l&x!pX&izj8|8VYmV*iJ8{}cN^oco~I z{}J2|#r}`rz9{y81oua=|0B3hiv1tK{Zj1z2=1F=|3`5D6#GAd`>5Fe5!_G3{*U0k zD)xT__gAt1Be>6s{U5>oR_y->?z>|DM{xfY`#*yFu-N|*+>gcnkKn#6_J0KTXR-ey zxKE4yPvm|r_CJyPw%Gqf?%!hn6S`?}cwMDFim{}Z{-i~UdJelPYv zk^8>b|3vQpV*eAF2Z;SoWIiDFKaqKX*#AW42V(ydnJ0+-Ph`Fz_CJw%gV_H><_}{3 z6PZVd{ZC{*A@+YH^9r&5Bbi@_{U6CZL+t-Z<{M)FM>6ja`#+NThuHs-%tOTfk7Pa~ z_J1Vv60!dynV*RLAIUsL?EgsSD`NjgGH((4Ka%;2*#D8tW5oWCWIiMIee-iT`vHwZThs6FTF)tGPpTzt~?0*vTB(eWV z%$LOeCoyjl`=7-8N$h_T^C+?ZNzA9j{wFc768oRT{7US967wvv|4GcZ#QrBS?-Ki; z#QaO_e-iUBvHwZT$He|8F)tJQpTzu3?0+)zG_n85%-6*JCo^vo`=8AGP3(U%^Ek2p z$;{`({wFi96Z@ac{7&qDGV?sK|H;hv#QrBU?-To<%=}O6e=_qxvH!`;2gUv;GcOeT zpUnJF?0+)zM6v(L%ooM}Co^vp`=8AGQS5&*^GLD(qnJ;M{U61=QtbaI=9gmsM={S7 z`#*~Lrr7^c%sa*Yk7E8Q_J35c=AmN$M=>82`#*|#so4Kf%umJsk7AxG_J0)fRk8o0 zn74}kAI1Dt?Efg{v10#6F`pItKZ<#+*#A+?Z^izPVxBAZe-!gwvHzo)_lo@=&HPvF z|7hmHV*f`o9~S#Rnt8F<|Iy5k#r}_Go-Fo%H1lP#|D%~Vi~S$X{8{Y(Xy(yk|3@>Q z7W+S%d9~R8(af*K{*Pv!E%tvj^KG&JqnUS${U6QzTkQX6=HX)hM>8K6`#+j_x!C_P z%+JOCk71rJ_J0iXb+P|rn751lAH)1z?Ee_%@nZkSFrOFuKZbd|*#9xi@5TO)VV*Dc ze+=_|vHxTKKkv6&K8E?f*#9x?1H}H1VLu@De+>HqvHxS(ABg=Q!#+Xm{}}cQV*kgm zZxH)GhW&%s{}lESV*gXvPl)|bVP7HkKZX5;*#8vv8Djra*l&paPhsC7_CJOFhuHrV z_90^bQ`nD){ZC8#c zPi5aF_CJ;Vm)QSQ_F-cGQ`wJ+{ZD0ICiZ_U`!lisW7(&P{U6JIP3-?z_HAPS$FhGD z`#+X_oY?=d?B~S(k7Zvc_J1t>|@3Lk7GY8_J17vTCxA**x!o%AICmd?Eg6SyJG*x zvF{c8pT_=I?0?#P?SsYsr?DRv`=7?XSnPiq`(v^HY3!55{-?2D7W<#ZzFF*l8vAFl z|7q-_#r~(UpBDR{#=ctYe;WI1vHxl8v&H_WvELT^pT@ph?0*{jZ?XSr?8C+Wr?DRw z`=7?XT8hlNS*CKc4)6*#Gh53B>-7 zCto1;e>`~uvH#=AABg=QPaZ++|9J8VV*kgJR}lL@f&7Bl{|V$7#Qskp-yrsX0(l3q z{}aeRi2a{H9zyK@1o9DL|0j@_5c@xY{Dj#53FIln{!buZA@+X)c?+@s6UbkP{hvS{ zL+t+q@)=_PCy>_=`#*vFhS>iJ1*#C*-NyPq7Bwr%-eEv(3{-=}25&NG`K1b|-I(Z$j|LNp+#Qvv~=Mnp#PQFL%e>!;|vH$7h zf5iT$lLr#}pH4nV?0-6WA+i7IEw^Z{-={i68oP{ zK1u9 z68k@ie3#h&N#wo6{!b$RCH8+3c`&j6lgNjO{hvf$Ozi(8@?&EECy^%;`#+g{nb`ly zPEvHz3F$BF%)OkPgx|77xWV*e+TrxW`>nS7nt|H0)|C7n* ziT$5UUQg`*Wb%7r|1-$*iT%$Y-zWAzgS?;E{|xefV*fM91B(66ARj39KZCrW*#8Xj zgJStyrS6u4DyR&|1-!liv7t|5Wn0V*jU-&lUSWmAtOl|Ec76#r{tv&nxzSD*0Zq z|5M5Piv6ET{#We(RPw-L|EH1<7W+Sqys+5+Y2=5+{!b%MEcSmI`C_sE)5sf({hvnu zSnU5a^2lQUr;$$<`#+7mve^G=Ey@7{!b@Q zF7|&q`Es%U)5)8Q{hv<$T^@Cai6GvO1&{%64}i2cukUl9AB z1is_zbcCS@0TS|FhsX#QtZ&bBO)Vg6|Ofp9SwB_CE{$L+pPR zJc!u;Ecg(y|5@-NV*j(@N5uYT!;^^p&xS7%`=1SOBKAKU{zUA5Hav>h|7`davH#id zDq{b$;a9}|XT!6I{m+JP5&NGF?;`d;8~#P?e>Oaf*#B(!7_tA^@G@fmv*BmN{%6C} zi2cuouMzv74R0g%KO6o=?0+^qj@bWf_#CnS+3-4I|FhwD#Qx8K=Mnoq1HMP>{|tB^ zvHvsRf5iUJfCm!$KLb8U?EegSA+i56;D^Ni&wwWq`#%G|NbLU%cq6g@GvJTJ{?C9% z68k>`K1uBV40t86|1;p1#Qx8KXA=8A1HMV@{|tC1vHvsRpTz#pfQJ(MKLb8W?EegS zDY5@E;HSj?&w!^A`#%G|O6-3Qyp`Dh9QZ4-|2gnjV*hjCv&8=Az-x*9&w<|(`=0~P zCH6lDzDw+X4!oDx{~Y))vHv;nU}FDs;KRiJ=fI1J{m+3P6Z@Y7PbT(12fj?~e-6Bv z*#8{(GqL|U@MvQHbKuj&{^!7}iT%%kUlaSE1J5S*KL@_8|K+6TVLD|4ev0vHvsS@5KJkgvS&6KNCJr?Eg%7 zJ+c2Y;rGP;&xGd_`#%%DPwf9pct5fKGvWWl{?CL56#G9DK2YrcOn5=D|1;qS#s1HP zClvcX6TVRF|4ev8vHvsS55@k^ghv$nKNCJt?0+u2qS*gj_(ie*x$ul)|8wCR#s25Q zJBt0!g?|+Lp9>Eu_CFUsQtW>&yrkIwT=+?`|GDs#V*hjDE5-ij!dr^{&xOAf`=1Ms zDfT}XK2z*}F1)7L|6KS@vH!X7oMQiT;XB3t=fZo6{m+H}6#JhG4=VOQ7d}+%e=fXe z;%j$v;YY>(=fabU{hwusFBSVg3*J=h|19`ZvH!E+QN{kxf=?CuKMP(}?EftIRk8oG z;914~&w_6i`#%fbRqX#P_*b$2v*2OH{?CGs75hI6URLb?EcjWm|Fhs}#s1HNuNC`0 z3*J`j|19`hvH!E+amD`6g3lHEKMP)0?EftIU9tbO;CaRV&w}q2`#%fbSM2{R_+PRA zv*Cfo{?CRF7W+RNURdn^Z1`cZ|FhwV#s1HRFBbbh8{Sy#|7`eUvH!E-k;VSchEEpz zKO0_I?Eh@|WwHOW;hDw$&xUUn`#&4rS?vF8_-C>Iv*Dq|{?CSw7W+RNURvz`Z1`!h z|Fhw##s1HRuNM118{S&%|7`ecvH!E-vBmz+hR+uJKO0_K?Eh@|ZL$A(@Z4hm^WeM1 z{^!Aai~Y}o{}%h72M;dxKMy`!?0+7-xY++Z_;IoSdGO?7|MTF>#s25Pn~VL=gFhGh zp9haF_CF6kUF?4zyt>%`Jot67|9SB2V*m5t+r|Fp!Mlt7&x3y#`=197FZMqVK3?p9 z9=yER|2+74vHyAS^kV<>;Opl%{F4W7FZMqV{$A{VK0LnI|9tp-vH$t-`eOg{;rGS< z=fm@h{m+N*7yF+N?=SX0AO2te|9pG^`p@$51L(h-k1s&~xB2)3^v}x2C!l|JK7IlH zyYlf3=--`>e?WhheEpdM^=He+PoO_*KE49|+4J!i=~-eEbIbyXNCN(BC~D z|ABrM`S=j@v&qMgpr2Jfz6Aa3^6@9=XPJ*rK|k99{0jP67vNja&%OZvf_@hT_!#uN zDZtO5-&Fy=2L0{|@HgmpS%A+$zuN-*4*Fde;Cs;Tz5xG&J_`l-AoSTNzz?C%N&&tI zeRc})N9eOufKNi7tpfZK`m7b;o6u*k0RMzOiv{>7^w})HPod9h0lo@-b_?)V=(Aja z&qAN=0{j;GtQX+B&}Y8@|AoE_1^6)Z-6+71q3=ooz6^bL=HSoJcWDkj4Sl!f;MdT1 zZ4SN-efQ?z-_Un)4n7WjH|OBz(06qXz7BnN=iu+qcXz7Rb-=HL&}vt$lF5j|Vx;1|)eW{#dY{(APz!9SvB(Hwjv zdN$3$Poihl9DF5ucFn_N{4;tN72>1OyQvUAjowv-_-gd-D#Tx-cUd7m8@<~K@!RNKSBURM z@4iC(H+mNq>7CeH@5UnhIC@tW;mgsxvj~5V-lau)r}oynwFtkC-nB*ecJ%Ho!oQ<; zaS=Wqy_<{lj`q{Lx(Hv7-rYs`d-N_Z!snxRdl7ygz3Yqc{pj6ag#Slpfg*fBIvW(> z2hv%g2w#xS4n_Ebbe1T>C#17Q5q=?^HHz>J>FiO2e@JJMB78(Tn-t+E(pjYlUy;r( zMfi(!mMOw#q_a&Cej}ZAitruj>{EpQNN1rUor!#PHkykcNoS?G_>y#Xnu|Y4XQ{dP zlytV5i(g4+t-1J?boQEye@SPtx%ilLHk*r|NoTdW_?mQfn~T3mXSuofoOHIEi{D9S zy}9_FboQHz|4C=Tx%i-THk_+7qOZ=1bMZy#>^K*Hl+KcK@k!}yITyc_&YE-aP3i18 z7yp#bqI2<4>1;X|Kb6j^bMaN_>^fIx*j_rz&c$b?v+Z2`Ryym>#doE%?_B&>It$Om zho!UeT>Mx%D;ML-(%HEff0oYD#rU*zwl2o6rL%T1zAc@-i}7#iEMAO{OK0<9{9HP# z7vt;F*}WKlm(KFV_`GzsFUIesvwktYFP;61@qg(qP>c^ucY|X5V7e<5;|tT>p%{Od z?h?iL#B{eP#xJJ3MzQW3J$3ge#y_UJNHIP#-A#(|lj*KfjIT_0mty>7y2}*fGt=Fs z7{8hBI>q?TboVL7f2O-oF+Mcijf(N3>8@0aFHLu+V*F{kOO@bL)7`2Bznbn^CHU5K z_bS1^rn^`PJ~rLWO7OGku2zDtO?S5v{B63+mEd#J-L3?`o9=og_}+B)E5ZM!yI=`E zINc3P@Wbh@Sb{HZMQ~w>?vOsZOP1i1)7`Q}cT6AMHB0c#>F!yAe@=JN5`1*Jo0j0G z(_OU$U!Cr*CHU)fmo33(r@L(lemmWDOYq(4?puQYPIuuFe0aJWm*|e{qq}kmzC7KX zOYrCEE?t68Pj~AQ-LbuO*Dk@gr@MEF?%>|Ki;Ii>gv8tfoe8bh96Y3!ZLiJnjMzm57jKO9G|FWi{%lVIsQ@2BFpiS zYBpJppH#ETa(tzlU6$i7)hx3dpQ&b><@ilC>nz82s@Z2b{!`6D%kiOVHd>A!RkPA^ z%}hNtJ1xhbs#$8eW~#9N<@i-KYc0pOs@W@b?;e`Pmg8g9Y_?o8S`W=?%ki~pc3Y0W zRkPf3&2&99+bzfMs#$M2zE{nD%kjTz7F>=GR0)MV%=@s~NHCwO1ud7*m1-@O)-YYbN@2**V z1wLNQ<}2{?YF1x?uUE7C3jDpA(+Nt6e|^K49$zD)0kq zS5Sd3Si6G?{K48KRNxcVZlMCduyzd<_=dH6sK7t0T|@;wV(lg>@DpoSQGu^myNe3^ z#oA?5;4{{4qXNINb{!S?j83$Efx5dwR@?+zpPzMB|c{DW-9SBYgbc=uUWgBO8m{*DkLtX)tgK4|TRD)B>WS5%2FTDzl4{L$JaRpOJ@ZmAN#w02FE_@=dcs>DC7T~sAL zYVD>fwWD&^uBsAWwRTsP_^Y+cs>Ell-Bu-jYwfx!@m*{8RjD1AyLMrf_^`DbtHh73 zU0Ef*Z0*h}@n>t7R*6qryR}OE+S;{M;@j5ltrGvXc5#*XxV4+B#Lul=T_wJ5?d~e^ zcWakdiO*ZRy-NJv+Vxf9`_}HS692b$ftC2cwHvI|j?hiJ!b*JM+8tKn57#cS5}&ws zi#V|e zuH9!9{&Vd@tMH*~H(G@sUAxjMeCgVqR^d&*t-`mi-D?&8b?suS z@Ud$*TZNxpyV@#z?b_W|;cwS2w@N!*SM7GI@Vjf*TZQjkyWcAO@7e`d;e*$1xC%eK zcEwfr;PQF=PLa3+C^94qt|Y_3O~Je)m8ZFwY#pu zU$0$u6+V0IwyW^lYu8`**Y3Ouf4+9sU%UBg{QTP0SL5r~?!Fp-zjpc6`24loug34MU4J#c zf9?LO@&79eP)#3zvH{if11Kv{O<#br1J(2gC`(XHpMbIj)yf!jQP!ZEz5!(qs_7q4 z7NMFx0%a4b=_gQDp_;w|Wf!WIVd$(ZLp6N{$~IIhi_p4 z+$*i7A3<4(YWfnCov5ZiL0O7w`V^F{sQ!PyLZ=t1mAUAw>_s*G3(8_t)5oA}Mm7Bm z%4$^8*P!f1HT@0Ba#YjjplnAq{SL}{RMYpM>_;{I56Xg6(+8n!NHzTs%8FFe7oqG( zHT@CFl2p?tp=?Pt{SwNWRMR)1>`68K6Uw4g(?_9fN;Uly%Bob;SE1}mHT@OJvQ*P& zp=?Vv{T9l)RMU5%>`OKM7s|ra(1)RHObz`Q%F5Kxm!a%TjWRTyl%=VmPea+78u~Sq zwW*BRq`4@YRzp9HvT8N-)hN4GLw}93Y&G=REK0Ah zq2ESXw;K9xlzp?&f1@m%jXoS@<81WfC@W{9FGtxq8~r)T(%I){j<^kqb#6} zJ|JZSZS(^vD`=xHNZCOf{XxnS+UOHfw$Mhukg|q0`i7J}w9!ALETWA*B4rb8^b;wo zXrr%4*+m=uManYT=rdBb(MG?KvW_Vl#Wg~6$BPlCsqc2I>NgMr1 z%2L|sQ&P6lM!%A>mNxp9l)bdkzoaatjXox2Gi~%UDXVFtuSwZW8~shna@y!~Qnu4Z zzmu|_Hu|2F{j|~lq%5e7J}6~FZS+GaD{7-JO4(5x{ZY!2+US!~w$w(yl(MEa`lggU zwJC$@s4S|DJ}PBXZOW)RDywRvuS(ff8~s(vvfAjgQnuAbzm>ACHu|oVeYMelr7WzC zJ}hNpZS-R)D{G@KOW9c){aMP=+UV2T*>KNBzm~GLHu|=dy|vN5r7W(EJ}zZ*=h4rl ztnNJex|H3WM}L>Hyz}VuQnq)VGQRDV^_@rGm$JX}=>Jj{cpiOV$_CG)A52-{dGv)T zJ3Np6FlCA7(I=*C@x1@B_TJ%9lzrItra|Z>J){@XNDoN}y%%ZHREiiNVCaxg1l$2Z zMa70bf+8Y{$fJmYhy}%aw(n+>Y$^c)BoKNCEddhRdtJ!{(Z}!j-aplW9BR$g^v$96T#Xv^cBn;H(?^HebT$2S zs8v_fSBKhlHT`v{WmnT@huU^E{dTBzSJQWg+IKbmcc_I|(}#!Jcs2casFhdKmxtPU zHT`+0rB~CZhuV5I{d%aiSJStL+Iuzqd#J@%)5nL}d^P=isMS}~*N57DHT`|4f|~w9WEs@-86w-DM#iBHvJPtc4v~FO z(|?F8gql7?WFyq{BO)uIrY{lM2{rwR$Wo~3Q$)5xjf_PbWG&S6Eh2lNrhgGx3^jd> z$Yx0NGa{=Y(btIVhD3iOvK$h9j>vXM^gAN!A<_4U?1x1EBeEb8eUQk8Nc2M@DsgiG<8aYh+I(`X`Y^k?5mDHbtVJ5?K`qnU&Vau1NG( zBFiGtXNhc!M874nE)sp0$i7JQUm^=5(T9m_j6^>svN95VnaIva^k*VVBhjacY>h;} zCbBjXGB>S|y^-kOL>5OvCZ`p$ITHPx$m&S+bt1bX(cg(Ik3^p*vON<0p2+%0^nD`x zBhmkfERaMWD6&Bk{h-JSN%VyxJ0#H`iY$>tpD40L68)mc8cE0;wLRb;Cq`c;v&lIUAS_DVtq%NbcLi9S|jvn2Xik=2suYejZTLWav3 zSuTk_S7f^+`dyLrlIVLy_DiDw6G{I6_eJZ1WYZ-2X^~Zv=&MC`O+tpPC9-T1eYVK9NyxahMAl8B?-toN z2^qMS$ihkV;UXI+(T|I)oJ3zPvUAd5_;Zn^ljze$woXFEt_8Ao5`DYK-bwWDB8w-{ z$BS&9L_aUGdJ=uT$nHt>_ae(D(dUb7pM;EG3uOHy`hJo9lj#3N77+K>qXn{o68*r) z3QEWfwm^1JqCXf}LWw?MWD6zwg^@Ls=o?1%P@;brSwx9GVq_B~`iYTMl#p3;LUvK2 zzZh9Yi9Taw8zuUUk#&^lJ4W_VqW>6KNQpjVWFsZ|k&%^@=u1X+QldW@SxSjMWn?QQ z`jwHjl;~SV_EMsM8Cgt;K4xSyCHk3>)s*OKMs`!8zZqFhi9Tm!J0)a19g+2v=zB)? zQ=WD0>M4vUXtr9Y>j>x)7^j#zSD$#$9EUZKyHnOo2{n*IL zO32JQAUiA3pN%Z7M4xu&&(2BoYa?qb(YKB4twjGevbYj`+{ori^m8MtE78}D?5;$A zH?q7Eecs6SO33&+AnPm9_l@kYME^Ikz!H7n$OcRFgCi>}Av0``?65?CII_eNed5R# zOZ1B)Yb?<>j_k2S|2VS95`E;zCQI~_BdaXYSB~tmM1MK5%o2U($Tmy#n&RY9jsEp-?@IKs zBbzPJ&yK9NL|;3y+Y;1M4Wm;{gb_`oQ5#K#L}!6QC?Fbp2?`G9Hgh|dp-c;^9KXr5nm55 z5gzgN0VClNUoS8d9`W@9L*Wr$PcRi8^7RE{;UQmdFc%*3^#_CDA>R)$86NWe0i)p| z-!Cv59`gMI!{H&{PcR)G^8E$l;UV8|FdrWB{Rac$AwLgbLOkT>1B{4={Jek}@sOV% zFeD!G^8}{ELw>%%n0ScnzXayQLw^3ipm@m7BbXEq`1u5*;sHOeU{*Zf=NAl%2mCyP zY4L!cZ!j(%@beDl#RFvjB``1^@cRHJ#shvoz{q&O?+ch25BU87L*oIzPhe_1;P(rR zjR*X`fw}R3-#;)o9`O4JCdUJQKf&mD!0#)V9S`{Z1;gV3zt3QLJmB{mjF0>LzJvL3 zpWlBlK<;yY04B(N?jOJixzGItm?8JM{{TbeKKCa*$8W#S{RI&%iXf&;1)1C-=F(1M}oQ_kUoZ+~@ufOqBcF zKZ22RkNZn7Q|@v935Lo&?oYu~xySu07%TU5XvAe-xDxp?(z3!(;JT(_a$;O`-rI1T)L1S6+`znAa-F|~oepJ3=T@b?rTmTVO8TPqrqf*>-+}RTm&bcxKHcT<9~e+~c{~Uv)LkAQf)RC>$BSS_ z-R1Ek7*cn5JPD@M9UfnTF?EN>n_y1e;qfOJRCjnh3MSPZ9-o3yb%)2RU{>AX@hccs zcX&JtrqvxD--2;w7+QCDJPoGS z9UfnUv2};X+hA_p;qf;ZT(@~V4kp)a9-o8Jb(_cQV0PW+@jDn^w|P7drq^vA--GdW zo5%ZLe%QDS{=`?z*wu}`4*UKbv*w9gRQRdeC*qd zI-Z|_(N@RvH89)ic>V^4TOH5mz;vtQ`5hQuP!a z3Wi-R&u783tL6DE7Rz7A&JEuO!F;dhJY^I-bj;`u!o zf46wP59Z%3p8taZc#Hi3U;^G^{{R?)x7c3*X5cOMAAlivi~R{;3f^M>0vLn0*xvx= z;4St)fI)bR{Sjai-eUj6%WIr(vA+V$!kg^BxLI-SCi^qMG`z|F4KNOGvcCh&!<+2? z00Z$R`$ND)yvhC%FcNRFzXZ(0o9sUUL-8j2Q@~Wb$^I2E7H_h@11biB#_9WWkmvcCt+$D8c`0R!>|`-8xQyutn< zFd}cTzX;688|*&NWO0e~HSB)|gSLkK(O}Znuzwni z+8Xv(gIQa{{%bI7YuKL+rfm)Tx52orVShK6w>9kl1_QT-{o!EZ*06sZjNBUbmxGyG z!~SzHbg!~M9ZcP;>|Y0C_bU6_!Q8#d{&z5Vud+WLOx~;Pp9iD&D*Nlf?7hnVdoX;j zvOgb8->dB32jllD`}@KCy~_T7Fo3UeJOE7Ks~jHyBls%E3&0G%%JBm*gs*Zu0Ziem z9A5xq_$tR6z#P8H@dq%7uW~#BOyX*ePk>Qe&G8B_i>o<)0fuok$1}h*uIBg#7{}Ed z?*Q|-n&Tf}AXjrdq_lQNHOEK5NUr9137E;%96td=xtilCU@BL0dQ7?{{sI6ekO_7#qo zfth`U<7Z%KU*>oknA(>)z6QqjWsbLjxqX@AZ(wj==6D>K+?P2%2S)d0j@Nos znBtc?z6i$nWsWz3IewYrk6@5r=6EESFK10YKMBSHXF3p7jrKAe?7C1e^%xSswvM!gvEBvFi*u}hfdk_l z>tW!;ILG=JI5N($UZ%_KuKQBILG=LI5y6)-UiN%bF9CCgQJS|IB;@Q zu|5Zmjw;scz}Zp7`W-kts#wnhr$-g*d*Jw}V!aQXA62aXfdiz9^+0ffRIxq?j*u$W z3&9yu#rh#QM5xKkhV^Q2)|_Ge8XPufSkDHh%^B9W!Etkj^=@$9oMHVN z95`oK4+kgC8P>p>;Wc?rLA>l--WPKzYNtLXZgfpp<^^sR5hI?Z}kIIT{zz7>wE)2w%e^XfF~ zU*W(y&3afku}-r-7LKgbte1r|>on_U;m|tGdRjQOPP4uij;+(Iw}o@-H0y8S;5yBE zTsXN-vpyG&uG6g7g|q84>v!SsI?Z}sIK57@z88+K)2#P}^XoM0f8hW-&3a%s!A`S2 z7>=;htQUqe>=f&V;Sf8;dSW=mPO-lDp>=f&d;UGK3dSp1sPO&~2j!0C3JH>ivIMGhAJ{pd+Q>>SUGwl@X zr{PdL#d>Nu)lRX#8jiJ7tha`9?G)>;;b1$(dTcn^PO&~4j**M_t0B($|`JIVTWIP6Zco*hoRldNxtO}o?!k04#pGAW5CIHg82+M8c#5<0cYb0<~QJQJi$B% zoQ@}$?||d+1oIwnKAvFy0}jX&%!9xQd4l;6I3iClF9K)e3Fb%OkUY*j37nG0nJM`c4;8;DzycL|QWz1i}!CJ;V7M!eQ%x7)ha-xiREjU}tnBRiKwTyW# zI9+{fwv2f)IAzP2FN0&Y zjCnISXUmvBgM+q=c{Dg_%a~7tqqfWec{Mm|%a~t-!?uihHaKm|m~VsQwv2f>g#_4$j@9%-_Mmdz5)R zIC+mUp9e?pQRemF>^;i-9vr?$ndgJk_bBsyaQq%+-Ve^-qs;%o0eqBsKsbSqG9L&> z@KNRk;S4^?{2&~{N0}#Fxvl$A<_qB%KFYiyoWn<%KZJw$DD#ML5+7wg5su=c%qzlK zT*~|+9LA;0Gs0wGXDt&bSd+oa6*?dA6k{+U&_2FoYAGskHR5c$~-BY(xuFo!ZBUKyeXX1 zCCs17>hmScqrypD!h9+m)g{cU!dYFy{3;yQCCszJXFux0jcM0>naC(<8-wVfg3G=>iewQ%+3kP@!^T2R|7c(CWM|d&w!f=Kc zGd~Q6cro+DaEcc*Ukt~1G4sZ7ju$h33M|m;x%5at!GrtUnc`@_M zaGDo0-weljG4sxFo)VXBId#2gfC(~9FF)R=EdQRFJgWi4*4SH$>EeQV!j-X`6A}c;hZmG{u~baBIeQI zq%UGV9gg}U=GEb>FJgWj4*MeJ+2OP=V!j=Y`y%Gu;k++m{{3L?s3PX!JJ|*mF&`gR z+_Q*z`8&rFikP2YR~b>nJiXy^KoRrxhB}X;#=O0Kha%?h?{sWY#5{gP;DbWu^F0%5 z3z^r~4!Kgu{C?EbGlk6akIgz($b5g|CR-u%{>8hEh0OmaYL66>2k>;|PleR0`3cs!?F-3M@Yw5ANWMbYwfhC+Ej&o9Eg*m4lT}v=$YXe*Ia5GBLwLL6 z1>`k&KUYvdenatYQvrDnlWzZ6K)%E0Lw_zH@8RGl`wGZ^c<`{_57}NoKE&?N zJ}e+FqT=pb1>{FmO;}$*p2Uv_RuzyhF{<;@0`ew)%*revf8t!}3kBp+oay;&0r?c) zeKDqhyoy0>h8B=tv1eJI0`e@5Rdz2R-{RPq=mPRCcK;btK>o#mc%K6DFuvR6Qb0b& z1+O**hk}E8?yiN+Wh#bjr@h~b^3Hu6Nacb#h^Uu1+xw~;rJJLNeW`6FHH$J)pvnY4A7jeL@6 zJ^ICv^ljXaddVkaBYufxqKFi?4 z`Q){{?DS(kvj3T7#&7b;bLqJ0i+u83LdSiQPu`1%_vU=^UoM_~BcD8&E#I%pCm$x{ z<(Klwi+O+Kl6>-GPWoo%lPBYRyUXF3VwLJ23;u9|9A^V@XHu!WN`8o&PkLHoLliMagkNlk+dt)AXJU`q!l85a7 zi>q!Q$|J8Q>ejwI@_RHlcIT1j)BomYdF1Y>diahdydiyTQBR|MJYEB+`LS<>w^T-$4F!Gr^@`k)#7?Vf-&?n1==8;F_^mgAo z@`b1 zk9?%whwkQ*msC}8J(v8Xm)c#*B~R%=&&pi#l@`rEmP_7}?X!Yh@|OaN%(>(-z0gXN zOFq+k{eR0Pujz-?2Xe`85FOP-Ua?u%UVoep;2mP_8#))gP*lK-^e@LRd$K_%I3 z$VK*lPR+12x#UHCvN=1K{HPwM=I4?pl@pbbOTN_D)zfmxo3dCZ=8`{^5->WKJgSeE z4ap^+>YBArE_qdHT~l(&uUfq>HkUlBA5Mkkl5bVsJ0O?5tB0R?=8}KqZr>@FJgm?; zt#Zl7ipsOgB`+%?rNK&mmhTrgt>kI7?r_CQzSgyu&sxdbveulilE3vuda;!}t|g^b zEBRb$qx4qty6)@$u#(^POTR-_^1K%QvCm4rmtU{1t>k@Ke&1mw|7&sItyc2DI_uuE zk`MO%h&Qa{g$*xSXC*)E)U;Jr^28QjUTP&@?9s}3R%HJ(-fA_=O8%JZr&F!uk!_2c zXeFO4z&OfEUfGw^hgiuk3vK9QCC}`uk5a5id}M@lkF%0@_GL-9mHe}ym4R0B&_4I^ zwvvzLukCClFYU8=ZLH*{`MEn<$y3{*xt~M6THunp9P-w_3arT?e=Vx`d=7bRKW;po zLq1#YzGXS&wOQ`ia>#F+e88MTo?FdAO%C~PuSOrvA@41q=EofJ-~RkzZw`5IGnajp zLq1%aUZ3TV7x$~Q^Ap1Y7a_+hu^5(wkxhjYJxy9|Xa>%3W ze|BCD`E*{t&B`IK?(XJkIpo)!UN9+#JiFWxV{*v1(?tx+LH2)^wsrp;^6xBHd*qOZ zcf2qm2igBwwZBH?keBEFWk?SBc>~|^%^^?krPb~^$o|j#ZElAg^7fpjI_Dt!KXb|$ zyBzZPejn6eA)hb2*DVWqeV=!)wvgW!9DmM2p5Ko#r!3_AjfpvGA@A>Qtj$9H-@Zh% zg*?C|Jv0{b0sHqqY#}eu|EYr(@&nsG^PPn}!4?_2E#wP!ShmAL-eB14TP@@dj^6gZ zg*?Iy``@&XPiQf(w~$vDP_@QFe&K7XLSABo-4F};iC!^%E#xWsPD{0rubA*oyoJ2QDRQKR{Kc)egDvDS zUWoR!kk9zk9Cr(OjoL3dSjcZ2Q{ikO&+(eSy@h1bk!dDR)BMH^Gx?hGgDGb6HjA?+n#tdEs2*)5k8{-Q zVP^6<51#37Ca*Iky{DP{&eF;xGkKnyXT_Mw_ndbr%uL?rjKzUw@;{f?dz;Av-Lt{f zOg`wHPVLR)h0fmD(oBBn%>+9$d7_^g8cgJizBskkMBeDQ+N&n=N2k1V!9*VEhR8}2 z`J}m~<0kS-lQWA=u`!pflkn8;V1aQqz;d8-pX+-M?yb;a0MOysft(SD5y z+5hR``O8e?wf_A6A`|(ob0=k*ko})Nz;~vJeAhnbr<%xnePRD36Zx-StH+wigLNG} z!bCpoZvR0h@?xjo>TM!FwvRc*M4s%xo$)5}Wf!lGGLbi{eJ0dI{%r4Le-nAMr`^3w zQN0u7N(=8ohGm@|S?m&x?yxpY(bVl-b*9|;kB#-yEA-@>O z=M5Nnz(`*2{_%T_BuK z`M|H}Uonyw{L-m4M)HHV*Dp7cCw$#~iIIHaCCT%Q_~Gj5M)HVTfAO4= zeBvRN@ka8B_t%axl3zSBaF~%iWB0KGjN}`4TGz`+-f^#k$wu;zw_J)dl7}1|7-b|M zxngptk-X%*kNl0~Ctof0GLom<$IaD9zOs0xy^*}-WuH15$zPs&*4{`S^RjLa4CFJ* zEAAM`YwoANVIaTxrfaoMN!#2J)+`du}$6XC1PClYxBe55r$KkawN-#X1AB|5H8v))>gcj`?)Cfqd-M zK1&SbW!vqTXCOcONbqa}dD=gH^MZkV?W)8n2J*H?{yEV={`S?8V-4hS8_P!+$mc$> zaIk^A?g)o|2J*Z2f1GCcFL>Tr3Ed6kdoRk3HIVncdv2tG{BO_Jp$786b>I3Mko}*s zcZ|1zyzu-wR|EOsF`soXkSA^)*4jY6_~&(w2J*&#-1SIL{x*x4y~nt)Be#BinZCk^P?>m$g$*KKt2` zpX$kLFA3kGC%@gfK%Vp1k+2-@l?K|9#p=FYC#JFO^p6$%lV$ zUY4G`_)X6()RP}?8J?*pPkuzNS$gv2+r>}UlQ-Wve6pVW`N@G3^~nA|cg|<5o_zX) z-cRYtt2cNL(UV`_#kaqnJo|%zz4YYUzaO5WC-45p_yj%q_ny6@^~nA|ryUWlCm$aq zcs+Uf=jZ$B$d5oIu;Z$Ze1E^3i#qcDKfQZaNB;ke@Y6c_02WO?uA?77`%a0D zzJM3>HXZ!|gCFMT=o47l!>B{{|JjSnH9GnRb|3mfNB_WgcYo2*NARH6K^^@BTh@QC zqpx6<^&1_s|Ih69*sY__z$as;4%z=_P9FSJN8iDP7F%`nAM~2?fsQ_e6Z_xM(T|{O z{icq-g!+tEb@V5^q+P3{Phn8-8Xf%#lV4q-qi^B&OG|b1FJz8gsH2Zz=C7GL`WgNk zlA)uoq37lobo4iP*-zEc=P)Sy86Eu&zh4}uYxF%#AFZSRVRPAV9eoft#}C%g5Aj(+ zKOKD$A3xnoM}I_RQHqW}i51T#>gbo4dOAi&-^9BwM(XIF=vW)7qmQCuU7(JBibtJ% zb@Wv%*yX9CzapxKtByX46k7)!{T3f)w$agd(a))+j{b{YU)t;F!`L|Rp_YD(kn{Cg z`Z7AcRi{Pvf70lL8(R7_%1=~l>DM^?`b8~$8<)FRY3bjXfBv+VK8`*gpU~3JF=O;m z?QigPlsOe?>F@ab&pa)C9>1-&XzBOpnr6___i?U4*3$oR`;R}g^npxX|ErdMkWNqi zq(%0BVi&jlTKYp)R_@i(Clda{9xeSM-PY~W(l@eU!slB0M`9yC)zU{2Yrj=XKglcQ zA86?-iTw3lE&U~7Ti?>sXR`98*R}MU_)S}{rSHURprob$WNy@IEqy2*+*fFk{h!d< zAxleN%9NW6we+XhRn67Xr}E(FY%TpNWAkQck^P@=*YLcS{*^oOWG%A)6Gr_xNlQOV z{gH86`daRb(OUXjCh13L>2qmm9ipY*rDMqeEqyPGEBa{Ze+jEe)6xf%@-SITKg?$x z6SefkJRcgXMfQLEvR+YI`ee>c4Aastvu{bTmcE(%cm1{W&kX;eix%1c@jgW!TKZ{* z-F4B@SCi-8QA>Z#cf;Fi>9aYv%vnpn&5B))TKaBgmZ-G!-~8A4frdVu5q;`4^y3U# zUZzS?EkoNFUuPGfc{(dhlYNj zsmZ@-=nIC{}8yXd}M??Qm%qP1v^bsv^-l?IV zsP#+RHS`rZRe!9Zzi3+eM;iK!T#s$m&~Fqm{#^}yN1x`urJ?_5;pmMT`jB?yZ_v<> z6f=IEhQ1`9V=rsyPnw&)N<*KLdo^}E@GAwql%=6>=^f|A8v2)>{bas|KBo0CnHu_; z+Uqkk^fld`HbX;y)4=-YHS{^vd^ANvzf*nkvl{xIGLB8q(Ek*#ep*8x)bpXEHS|MW z%^RViFRFaiP!0W2-695Qko_Nf>R3Mw{ZcnJ_14fgl`$YqgY5s{b1@V zRWf~HwzHKo{b8@4IwjL5_T`BaGW}wqC(2}G|HrgFSt8Rv_H1RLOdnb6i}^DBWI;Eq zGJR#A-#5$jmu+Zml<70e^VZ4qo2jE^nZC0R2ON>rK+W%{r{mdW(f?R3tP z>8o=~Uo6vKckA#1nLfKTuX!^4c2`!uDARZ6bRt8h|L)DcGiCblR_=a5rXR1M!}BtI zc^|HxBGaEIUwT%iPw&~ulVtk!Cg+Zq>Dx05cv_}^Z~JefW%~F|CykVm{U7<(eiZ)0 z*Y{=IP?`R|&;x^H`utpy2gu0&kDUK|UzxtYxWT<;`u|?ArOEUG-kX*x(+_B0(_N-7 zaM{{Knf}1>Zt*gGg4_4T$n*=2AJR>xZ*cjU2$}vt$8}*ceT0t!LuL92XX}Gx`U-o@ z3y|qAe96U6rq8hJkuEZ_|4;Ru=Oxp3Xz=!s=|B9{>MGNR=(Vo1Oh4lJl#Viei2*m- z$@C|h_O_AfQ#?7hm5l8FQ`4hb%JeOcsd1F)U)=kny-XkDiq$Hae#RdLKNR#eKGXTW zpucfmWxb%!vF5-XLBHea*Xjg)kA0@y67)Z|NxmWIgB;rFnxG%@MoqP#FS1qsWkG-B zd;2d6WdBFJ_R)EP?Ei=>FINfrCXdWHBj}&Bn@}O>qdYL+l%SuoFtJ?FS2-i>xS+o> z-M362`#&PztyIu&`CZ3iLEmLVyFx+#<)L;qK_BMX4taupOv%+M=*xVwi$&0%*&@^= z=+nFzXAtyjj_Ruu^lf^L)d>1GC(aZC+5h2oFC7u|bNasjyP&W0n{R&;^ml%3`bE&^ z>2~pupx^UWtDgjYp95lk6!d@EPuwr)15H$aFX#s?{_l5!zR>eWzZLX{&UOAq&?owQ z&pm>EQQhL*0@?rJ+xF}d^pBoB^M#;~bi4mfK|iVK`5l73(u~iy3uOO?WmRnx^qJm@ z{6x@iT9vg`(04lQ&yNJM|HFLS{YTJ;I&0bof__xrAKn+p{tp}G^q!zU_1x5V1bwP? zhc*fNRhPTGCFon7yYvk~|EjI%bwMBNe^Xu)^t0A(-yrB~J+C5|D3;JreoSrM_udQE_Dd@A!Yw@B$_J647 zXR`%;x5X(L0@?qePQ^0?eYoE&ogwJQ)wrY!`f^AAJY69BKV zm?G%gZTb9ULH}-9yXORbyuRWYK|gP4_9Q`HuS2(qg8tsG&W#uJ`5xXmP9Xa~Wbg}5 z3;KQs2aXl=|Nc@n8u!;@$j)y@3HpH_E*&Z83(oKTl%PM@z0C+gpK!tPVS;{PyYGey z`i6I}8zPYXA1t07Ea)R1lQ2loPdvW;K!NQ4U~6@ML4WaYx%~uv#=iUe3i^$2f7D0N zcRWbyE$BaPIk%Uf54rC%Jq7*9SBInt`jR{L=ppD&-V>cF=uwwBA1>&V4y+0j^h?`2g$eqmp9}9Q z=${T79V+Ofp1V9m&`%w*Gg#19Js~ehAp1Y)-h)6vpS5RPprGIS+gSmEzU!a1`3w55 zyO;P0`mm!q`3d^5KOW;N=*wR7o{ykEyR@i_pild2uP%aq?V5CNLErY?yuk%@6l6S1^wSWes>Y{ zfp7D75%hy+zuH+K`#(T?wUeMf{LN=O3Hrp1`i_Er@ipB$3i`(PeBD9NKR&{zgP@Om z)(7nc{p59R+Y9>2A8c$V=r3Q>vYnvMeCfuv0@?oo6>ZuI`p$Llw-NN82Y9y;^r7F{ z)mqSx-aDbSpfCNA+)B`&o;snGpilkcMQ1_3dWW^ng1+^AUe1F4b=^-b1%2$}CbSgv zvrnpPA?Rx_+S)?U-)`vBLLmF!KmLM~K=!}C>t-iG-}}P8PJ;gTzSkTDeefH1Itu#X zhfQ)6jlTGHj)MO9SfhiWPkz#R2SLAlZGQ(r-+XHa2SNY*7K6Q@kN(q5_JV$TuZi}8 zzWR0n_JaQUl~?TqefCrTuoLv#A9~kL(0BjFEIWbhf4`!hb^_V|ejmEo31t8K<=s#T zWdHlAZ7PB6f4{Hys|2$D{f7QWC6N8^H+{8AAp761W~NFY``@o_v`QfR-!HqDN+A2+ zZ*Di0K=!|1nV(7^``_;m7nMNvzn^y-l|c5t-!(^-K=!|1FFTbO=b%#A69Axcv^!|0 zQrV4gRH>@5@SlJ7b}jl~m4iE0*!%S4|8~w1xQ4yGQy#W=DB~@4oxm0LEuX;(hi$x^ zGMoQ9Iz{lxIk+qP)Rm1(S`Oxwot@t2^_*MAqj7X}%3PR@ty_lh7Kib_$T)26aF!R7 zhx6iEUhF@G7Xx^k0~R#h+(slcQtD#`|zgz=lqCjtlJkFyG=2Y@%vW zjxD4X0l27caRmRr+~PYdU(-UuwyRrwh7DJ#T4rO$ahcs^tZx~NMUETn_T#d%Vn|0jkurn9h2dmobz->DI-nhy>*s+ZR*Z$#*R~~Df+oWSF z$0N$dZE=GiU_~q5cFT?U&+$*^p=errI^J>iz{72`jJHyab&X48#<&EWY-p)%M`A$V)m8v6Ojvuk6lM!=|{8gQYaEl>2 zEOO!os#d&L7k6xCH`)2b-xs@b1E-#RHgKh9o_+DYbS2)+yS@33$41U z*tB+e;wo+0HQg?@Ol^%fD#osF+r~R`3Tr#urITG}yM8UU3~0++Z|9_PaOPbNcd^HV zYmZqzB4xHi(%)t~+Sv_v;k7yi;!b0oRI1L(26!m;xF?qHP;H4Q&E7&wY=kbltd1=!MHhiW{*Wjg%O)JOTH^Z3T+ysv2m zo95>{zVSI9X{W3)*rs8^*MiNn%3`*Y zn-;U-=bu}%o!hjS%}Ql4+f_}A*}S7HX8T^#VmAEb^G4Y2Zd%Odpt6|lp{B)b_^IdC zYz<9|*%T{_*_JjfW>c;#W_zk>F&n) zuc_U=_U*8Xx8v5B>|$bKCoD~0m^FLR(gj17Eu5L1xoBaQYG&Hh#Y-2>S(?5eV0PyG zjI4n0m8r=QQ|ByP7LdJY(fq7{^rZ^|G8W9pm^CY7*3_h!)PRJz_@pI?Q?WdH;i82Z z(HZG8GN)!PoH>8ltcFn9r(=!)lW=~&| z7#}l}&vN>#jM?eS=4VgOera(=R?LfdF;rREvv3fF%lLKT)fS{@zlb@!pq!hDS0Q_P zR`$|mGqZVx#@E@2I~nt85qX7=MPgJWW`a>V2L4vp)dZ<=4yI5WCwCZlm?a?{MT#+eyS zGpl-awfDx`+W64<{IkaK*-xLJu`oVaHGTRrJk`|c*{c5IMok~pf5NcoBL|Njie~V* zabw1*W@KiM%UGVVG%I7s{Pa2FR7*3`=MP+zF}wfMiSeq%6INu-nl(S8|2QmFHXWI< za8CA%O)u2n?=3Om-K5upUs5y8S^t#v*#~L&wl)T;AxCk z@ny+YEnAqCIcH(Utbmy>rZ0W`90xQ$$N7sE&Ix$D0gtq^UR<;^`|peX<(2LppP<64 zffwhm2bYPD(c_2w_|=~ILvL;4RNIdR-z)zHxs0|o}*I~0@D_$`V{N$4IBzBFTg zMtW98M8FhWE4KNo7M(ObHF^fVuQOi^SemgsGYj9=fQ0zO_@tC+0nrO)E?(AqCLU_W z%IF12n9qK3*@78pXJh&7#mkeTvld6sicjVezA(}Fj`qg$pA`^2XV!}JrL&_G0;0zx z21L(ZxF{N*{mhxzWPWCPRwiDM=-IQC-9vO%M$>Kr%Vwo#r$0GAdvP?rI@wFpXJ+?a zG<)`w?_JXuQZ;MQGQKmJc%_;?ZU6F0CUkH9&^CTx77xV6e|EuYBxy#inm?d@?_|m~Xr=Fm39< zQR9b?Z~A}w_>Amji>FUYidnf*Sw3j|*y$rPXG|TxXxY-48B>Q29N2i}#+S75Df5;a zFDUQHlV6E{{auLVYyHptE0_K67kKp0i6i^tkOTLc77)(Q_=LtE4*bpp;E4weR(?DJ z#x7knGb1Z&(bBAl{|8?JRsU4%qSN{7gWon>bQ;+7eHfLbYSFIcs8;r^TXc4GwR5xc zaPYMAvh%j<;^1TFXU|ivw%8n;zejc|`!(&`wo|!czWI;8rUTkLZ?JzA7h?!7CD379Pi~n6RpTEq?E#hgYVrDK{ zupk2;jTpR7G3nXZ56oDW{r6j$jU$7M=GW%`rtN}_@XD!LC>tmJ<4TRctXLL^iQC~v zx$*Cx+i@NL!Z0~w`v2Q54%__mexE!tYCeAIhV5EmYW^$tvTHnw^uhve!-@Ad3=?m! z`SA|o%vwy!U-Ruv!~Ea2TZaW}m5tCeZ?_zmxn1+$ARL%YYJO5!*u0L1;!i%lByT&_ z3wRKGe0*HIJ+`l4YQ7FGsy=bFQ+0k~LG#5A|FPX(Cp%Tw<_Gn}Iv(*pdA}d}*s0=h zUd#J!gQ@v`zkK34xTq>@Wv2?@1?8{#et8J{}R`S?0v zYQDWA_xl;M#I!>pRwt2fX`0y=Jwqet}-9=o++rGGY)m3cQqj^Tz zj}eiyGS}mpiI%JbH4a!{6RH-u{!1 zg!50{Bj+7eZcp9-<~=cA^>|tHtJJi>0edB`|Ld=Xiu7ev<$Cb7=e|J~{8w_;~pG zH~sM){_D>{_0M_NzgFUs175A}X!#y+-`E+i*U%@n;O$QT$Ncht%y0U~{H}k@|Mrjh zf`80k_{aRif6V{yfh5lCLb6pMvmPJaH=eCD|CToXZ2s?0E|<*w`x(ps*RdkcS^i~n z9PjHY0!`=@wc%SY4@x5gmfZqpnrQf2;SW&Raq{%vJ`vogP3nP-x^A6 zuji(;K}s8|w7ryexYFWfZ+sry6Z82re$LQxU&HwTr43QqD5Z^6TK+b2yWUDWNNI;D z?Kq{Kq_jL9GsLr5&fVQT6;1!g$HgTlCkF&1#U~}FHg5kyYiaPv zAx#4XxH0_kOapiG_;2dw#*0o#jZHX?nLSl+9Edx(zfL73k4hP7zhvMNyBG8?IHr%a zbvlNnize7o(XO2yWW(I_i3N5+F;Bhn!oYM@K)(ZVzb_uzFCx+Ab8KxyYph=@4K4@> z3j6!|ppd`K+Xn^yZ9X6(s$fj*+NHjKTZ-FSiPe2(cuOs`{F)yGLJ#FUO{VxJab z7^YsBV*9id!I<1Jwd&(69`tq=*L$}TRhW)q%IV!&9Km#;cN_5)rmel(icOfL-t9yd zrrEvQi^-Tq_3j}0VM^-VQG{XY(z}yrkIBAwXHnP7MO?yE-pf_kFll?ai9@~I#W$F? z_wo?$_wp1QFs(xaJ?&TwT^zs$mFa`AT6E3~{May0RqM>JisOcFf zDtiWrlAgiB)H6iKP~6_KX**o(bYsTB10gmL!g+br-p5$wE#`5eL&!#h$btVq038csH%5 zcqOfuSf18fWTy2M)6)8hv1$FqptJ!ZC2gRHN*g5n(guspX+wom+AvYyW4Ng9F+x=I zcuExY7%7ZBMvLEij1l{Kj1@b3JT3myW4zedV}e-IW1?8pW0IKJ<5@AO$8%ytkIABU zkEy6hn(u#TTk1mb zPU<4@O6n4^EOn{KOwATkQybtCjTm)Pd+T3PX0p-PCg=fBn#0kStA0Hb;2dtAX+AyL_>Fr zsOfGMXS(N!lI}KP?p`Qw?3i9O{NiM{1{iT&j1 zi38+uiG$@Ki9_YI#1V3I;z&6#ag6Mi__XYtI6=OjFiF0i@SI$gFhxF^@VuOpkS_n3 zFjGE|Fk9Z8@S^-l!aVt%goX0DgvIi*ge*BTVYxgtVWm7aVYNIcK`o~ytd*k@*3140 zugNY6Z^$hZ-jW;Q-;rzL-!JBQ)?4#KtgmKQY=CBK zY_MiiY?x+kY@{YTHd-?$Hcm4oHc2xkHbpZqHcgWf+eZ@>+h5}!J4oXaJ5?4I!3J-9J5Z-Bj#02bj(IgV9X|sTgdn%ZvXH5ZXvD(_aKv30wt(RHiS{L-ynv$xv=&F9_hv>$eJ z(r)bLtXT(!@3^VE*)=A-S`EkK*pEm#}gEllgvElS(5TddZpTcWl; zDn)xWs;9Oxs;{;rYM|B}HB|dY)Kl91QDd}UMUB^f9QBO$?Wif*by3r`%c5p#=SI!Z zJ|8ttJ1%OGc1To~HZ5v}HU^oqpeRY}9<^TEI_h=pqsUF#TaoW+FGPN*JrRi<8!~O$ z$j`MuM}DQ<8~I=D=aJuOKaAY3-5B|kc1`4O+QpGav>A~a?Q@X^?WjnLwtr;4wtHle zHX`z<)-SSL+c~mA+aj_`+YoU{TN80rdp6>R_GrXyZB9gk_Roli+Jg}ex;+ssb)QDG z(Y+VZQMVz&RrgYamu^9XuP!|zNH;N}t8PR@q^?gytS%uUQP(vhRo5k=m##xZf1N|b zVBMYY5xVN|(YlK8@w(#hXLRQ9sk%SH({=m9Gjv~t&((brzEJm0c$V&!@Rhn1;cImB z!q@4hhrgA}-RZDj zbwy!Ebfz$k?)NaGZhx3n_f=Sd?&Gjh-8*5&b+3e-)~yJu(#;FIq?;aAqni+RQ#UN^ zj;?pueO-K*ojx?Ih2A@?jlO+YN4-OsoBmE$Z+&%FKYc~lV104daJ{)}wEmB-3Hk$F zQ}nyL_R??b+F$=}*CF~1U7ymg>^fGzpzB0^de_PNNnNMwM|7Q~@7py~pV)PwKD=v| z-lywIeW$K!y;Ilq`i9Vr`kK(U^=Csj>yL(R(OW~2{SDoz|0(oq{eMIE>OTwJuiqSc zNdJ21Vf~s=S-&{cpw9@+(LWbz(~k}<(GLhcp-%~|(02TQ-)z7V-3ASCK(b!rWm@0q#L?~%rSArfGDuNu0B|)u>mZ0{=BSEgl zAA`J&dx8Rt+k--ln}ec^uLs2&R|lmS7YFq=W&{l|P7WGo91}F!I4Ed>u}9EkV|37T zV^C0r(IaS{v2D;2qg~Jn0(HjOffnPGK$~%FV5xC%V7W0Z@Qg7w@S-s!u*T>WSZ8b> zc+cn%XlJ?`(9(1@pq=SVfQ#v9fS1V{;BS%xLQRJPqDgb`~Syu z!+)FUg8vt$a{oQ10{?v`ga1#a!~Ta&Klsb0ul!A>ZT@+t_xy`Zulk=bt@5ulE%Lu; z%J8o-P4=%fjq$%{8su+h?&0rjj`eSE4)J$0d--=UxAzY;JNSp2>-}QPHGbXAXZ?Db z%lrnI^ZbUHwSHsFzxYiwf9E&V{H5Pa^H#r1^V@!l&FlS^n^*e1Y+m5E-aNzaP4lyU z@0&;YZ7~n<`^=o`x62&u_pLd|?||9U?-z4Bzdz0Peg^YhU#t15Z;|+OEzV?=_zO5|p_;$3c_jR|d^!2qY^bN7h^o_DS=bK;|?VD;D z6TN{B{3(bOInWHrGL($ zF2i#6b{UiNMVCoATe>`-^LCevob_Gi=dA3Km9wzRs+?I}*5y3c<&B&%UEa$X++|Bn z&n}9r)!t*a(ucR%<0tSa8AoEnw$sTmYiGO1vwYJ%W_V6SL76XU&yg|*W~=^ zU6=Ed_k)~oy&bJPz1vu~c)M6Pd3#%5@eZ`E^p3DD^p3O6@=mo*_U>yP<2}SW*n70K zr}so_y!SL~nD;EJulGEwi+7gQ*?X1sq1P+cTCX>(m%ZM%R(Nf-mU?||wR(MR)p&hx z{l)8$b)VM}>n<<7^%JjL>$_gX)>pmCt*gDxT9)yepF7;ERc>Fe zPPyH^ymF(w0&)Yr!gD>m;&R)0rQ|wz_06sK9Flv@b9C-`&q=xEp3`y*Ju`Amo(po1 zcrMF5=(#5M8_x~7pL=e~{mAo!+)bX_a$oWMGIyotx4DZv59DTe{+2t%Qd)DW+^|Z^g_jJy?>(MdqnullJIgfz66CUAt1s-vE zCXdv-BOd+o4tfmD`^IBT-sc|AHFWRLIjx_SJZ7v%A0o|lI)uY*T^o|DJXy!-B_^KQCd$h+u%E$_7Z zoxBqFM|nB!E%P<*9rJ&2_ssv^Js|%p_wf8}?s55>-Ba^7y7$YM+=t~abALL2zWa0e zGu+ejpL5U5ALG6xf3W*Y`Mum<$xm>9Ge5$8bH2a(C;9H~U*@-U|2E&j{m1-zx5N3@ z-E{fq-K_a1-HP*z-OBSVZs+o4x2yR-yVd3Ib9DJHooZE2QShuHbL*1UU^>&+KOLCiQi*(Df1-h-adAhB)wRhWOb8`F8 zcHeco?Uw6Two9)2Y!$ADY)4)HwB@=QZ8}$*?XYW^?SN~AZIA0E+YZ;8wvSvJY;U_d z6s&h`Q?Sa_wP1;>Pr-|>p#{@jqYEawCKrr!?Ncz&b!b7F>)3*L*JlgDUDFHvTr&&Y zT$dKKbzNQH;JUt`!DUmy4VV8ETy)u9aN1>eL5a)v1y+}z3$!kx;5Qd@!G4#5f;}$B z3wF4iE%?agO2OMMwFMho9u%y0X;HY;rF~(hi$~!LE&+wlxI`3=c8M<>?2=a4%Vl6; zqRYs_NSBF)fiBYuJzZuOc5qo#*urIH;e*cW3Tr#RS$L)M=E5_bw-p}iysNOF^LK@& z&W8&B?EGipq0Xkl?>ZM0?&^H3a9igyg_}EHDSWeYZQ;7k4+>XyZc((TbBChYojr@D zbq*|=*g3LjSIJepGRt{i@;uyQ<;@ zyRqURyQ5+^d!S-7d%R)|8(X=QO{<*GwyMlxJ69&Nd6m&@d1VOOP&t!5trB4eR%+Oh zm11^cr6)VH(ve+MY03VzlFD9FiDhr89B2JeImkLx*~vOp*~GeBS<5P`EN4Bge8zfR zd5=|7d5zUnd7jl-d7L#=d64zJau*9*TEG%iWwTUO^H}Dp7}m_H zP*zCQELKd_6jn-=j+I*_V=b!kX05DpVU<)_vvyW7So^C8tYcL_nCGiTnAfX%nGdQy zGhbFUFe|GnnIEcNG25yhGyAK`m}6D{FtOEVn6&DnOzY}>Oqc4NOn&u7rlNW^(^UNn z)3>^a8C;#kjHym$&Z~}L=2nL?7ghT)S5{A9mQ?GQJF8{P{nb3?@oFyfLbWaPMm3B1 zu$svHxB4fes(O^sSp9|3QQgiMtZrm{udZR>Yu+-LHP0A!HTM{9HP;!UnhOj~%}EBR zImDP%Q_2Xh*~W;k`HhiYvyxF*vxM<$O#x#~O$K92O(LVTW)93`I2rXQ|dOGlUd(67`kqTj8} zqd%`rqyJZ%KyRpxqPNus(ZAHrppVr8I`+MmPJb_>+q~z|UEg!*!uNJ`^?NoQyeHFV zy~ohQ-;dK0-Vf0--gnc`dDXO~?;B|A-dEDLy?;&H_x=g(*!#P*^Y5?GZoI!hd-(n& z?bZ9kwCeYJXie{T(7N7lpbfuYP5bfwR~o5q0nMT=hvrn5O7pHupvmhZX~w!Bns40< zT5uhp#n$O)sdX}1ejT4yT<1z#U1v|*TxUTmt)tS8)Zu7n>L#gI>qe;e>iVcJ>)NT6 zbxqWdb+y!vx_8u}x|h_+x`$L^eHoQqe}(E;e~#)^f1E0-|C4I0FQxj{Z>I*=Z=lB1 zucD^b|4PlTUqCIc&!w)ZPor+BpGz&RkD~rnA51-4??=5>Kb88R-a!4gUP-O07g3w) zJ*i#w&eV~5YwFK>CY9VkqFOeWJ*{2D$|!WwEQ2@U0xjD{DK z`3(;#%Noik>l?06b~K!$>~AGJp-14D<-234b`P+x5WX#8V zWctS&WZRFI$!;Idki{R5k#!&cB>Q|UCC~o2gB<;FBYED(HRQaH%gMzb7n9d~EF^FF zm_^?6F@=2eV?6oX$4K&xkHO?eAN|O0KKhVrKN`uOKB~!mA0_0mk32HA(Ur_-bRgR` zT9G{(8DwcAiL7sg$ZA#AVGlh`%*oChlxLOFYFCoG$MMPRl4$-D1jp){rNEElk67?++#OW zzqJU7J6k-72V1zrQ!Vzye_AYwcUu_5mn~#sRSTBb)G|rvZW$$fZ5brMpLz)NPi+L- zPt64PPxS=Jrz(QsQ#rx+(@S)h%M(J}r+b8qPd5qkKV2a#|8$;E^63;|*QcX|L!S;3 zPJh}%xcX@);lZaZgjb(_Bh-9aO=$VFjL`RK31RG05dqhlOJKF86C7HT30|#n1Vw8U z!Q2``@M{eqM6{xt(OahwvRjP=bb}>fRjZ7!xm7^e)9Oh$+R7!IZ?z}fYPBLfX=M@0 zTPcKwRy?7-6(S6^j^lr{j^N3k`|(zvyYSr4pYfv4O?d6+dc4o)DtyrAa(v9^fAMLb zpW+KYKfo{hT!#Pc^ELd=&zJCjem;x;`}0Zs)z3%p_dg%NzxrH?ulc+a|LOAh?O^*7j=L-u8F6u$e@``Ug6hv_(hV{{zB*>xPmd3Nl<$vb|>nL4)N{5m$`B0ARL z5<6DmaypjbmUI;3R(CAGZSBa%?d!&hC1Ojp=%bP3yXgE$q65UDkCKThet2yQ}LQ_HftV*t1>7vDdo}V;^-L zz`pI;gYIYBg>CQJjveaSjQ!d58vBy33!9=odt#vbmO z#GLIJ!`$c@!94C6#FY2+VH$e6FdaQ@nBksJ7^t@qL+h=_*!I?9JbEiJvfgrxsrMDe zulEHeqW1|VsrLaUxA!ilxc3%jZSQr=_TGOm2YN4HPW7I}TH@u zW>sGvW=mfdW^Z3Q=0x8-%;mmB%-z0t%*(!LOm$x*rll_w)7KY-8Se|g5WdXBSbUj| zarrV8Bm9D3v|kLEXtGDr zKNtmnAB=!WL!q$MP%!K|6bOrl{9(h;OnAnSFB~@H11Anmfpdn;@RA`Tymm+jZy(aY z2ZmJe-$Qcv>W~zEFeHNC3<==6As*Z|{rhTt2+KcFYW-=TNIqyj5I)-M(Uu_ zky_~3NHuhEq!PM4@*nhKq#UXmc>}eKyn^~hUP9v|&mrR1r;x?h#}N1HLrC=XKBWJ8 z7xMjj2MYaK2F?9?6UzR29a{4BDzxV7KhXBCm!Jb*FF>cho`k)`HdI+)|{S)#WJpjo^_d&?$9>{;R6q+--8%i1d9V!^z2`wAl z4wZ~46#r2SS5P5ZV43i-AOivP9{%KA1RTJ)_5TK%m6LU&?A`@iKvC%@%DSH5LI_rGOA zufJtL@4ux%ZQoL%!Ef`RpWl)p>R1wFJ2n^c7)yZUWATuAEEe(~i-DrXqM?+rD5zj8 z5?VGE0hNq}L%YX9p(A4<(D|`o=+;;e^lU5;su&A^n#TO0p0Qcb*q9%LAD;W)3_kpI5PlZCpr$7ng0LmISLyN~v(CTp`v~An~?H|`er^a>Am2oZfU|a*e z9#=zk<0`0aTnP=0D4$&rLklln7@|=)BiU~12_ZBGl{z7S3Mcr`@(CWa zVZs~wW5NsiYr+${FyR5+Mm?W!hpHyrpymlzsBeM`jiZR)T_B6^&Jg#z6C^_EzdJ&{ z-yNW^@Agn4D(AZ$RQ%l*T8rB8-3B`N-5NTLy7t`)di32ALa+W%!*>g)6E*Uk17RlF z5Ci2f$%4F5s!1j^1vPt;0mY)yC+W}v)XGU3v>CN$k_sJ1U7n;scTxXNlA#(@E2@8z z1WlsIKZuYu${i*BL4ZssKUCxoJd}*eNB#N(2mOZHg*uEnhsG{$qMoAuLpA=uKs~5$ zC_EZMH61>J6$6)s7lM{r~6xlkNYX znDj!SPYMF408}(84ON6%fo3Z!cj@6T+}Zx9$Jsui8=%mpfji&sK+o7dWZUe>ViqoC<==qLoAddijVfx)hHh{ z?iYlL!_c5i)Itm$T7}wz#!&X5PN4D7e^B?)_~9$mdkh=;j2c8^p+C?_C>3h~*aWp?aJQYRAc;VI2At@Jh7YuY&CHYRC((fs}YH1n@d25U+=#@dhXjZ-k2Q zCTIoT3~j^%s1!d1I*OkPUBvr9xAD`U7x?K=72X$W!Ow*H@P5z)eilR|_(PV20EkNn zgv5j(NKXicW)MQ4FhVGlNC<~=2oX>*Are|kh=O(yqM?I?80a)17P>}=haM3Uptpp% zPy-L4UTBZPSnOiYCs#5BmBm;recGa)503z|aAfdYxSPz*62N+T9P^NB^!3gUcd z6LBF_N?ZgTBQAk15{scb#9yHo#HCO*aXHjNTmgL{{tucUu7Zf9HIOA~9mFNAhs2~3 zNKe`T%^+=p!bn@7MAB9$hqN6kChdgQl75GFkaj}{Nu|)=q&?6z(mv=R=>YVW^e0qL zIs|o)jzGgC^p{FL4$;x!9(LqYkQezhq#&P#0Qo!=K)wJ)lP^K3OU#`8u?L zd=vVETn7C`z5`t#--XJ^_n~LxhfpQ?G1NqU3iXnoLu2HZ5P|Xv;!xf|&XjUUNcj)a zQYxY8lxir1QVYdX>Yyx21GI?p5n4@Yg0@mxpna59=p>~b`iIg9-KTUzuPD7xE#(XJ znKA$kP==sM%2$X&{RUZ6$02v>cSuV80U4zUh zvfw|d7VsIW6?~m)13#kL!R1s(xPj^ncTlVb z2hddT9GV7BrRm^8nh{<`Gs7EbQ{de+ANUB(7d}s$3E!gm!%t~}a0M+GZls06-Lwe! z8!ZaP(PLm1Jq~uH&xQH)WLQm4fv3{b;UIb@981rE)9Lx}e0m|glD+`mL|+V-(u?6^ z^ri4c`U?0q{eSRt`Wm>3z8-F-Z-9I0o8U3}R+zxp0dp9;U}wf3u#mAA)-n#j(-?=~ zV8&l?JmVOg$v6owWT59M#yNO1<08D5@eh2QaSgu2xB=f`l)*0{ zL;K?|VIuQ2Y{4vtU6>WHkXa4unD61~%mz4w*$BroTi{IQXLu2_175}KhPN>L;JwTN z_&9SIzRVnj?=r{Xm&{4Hnh9fCm^e%ylZcsMQZPgo9b>^_VO&@i7$M6Bqh;A+rn8(d zAuKK?p5>0oWO-v2ve5G>ON`mfl416;RG8x|E#?x-fVsm$FfUkBF;%STm}b^YOfM?{ zGtLUa5ZIv@4m%R#%#Owg*zp(*I}zi>!Bns}V;b4pFx~9mF{A81FgVUW42yFR*RGd?o zDV(#IK+XkBH0K{oD(5<;kaG*OjB^)L!g+w%#d(4`%z1%1%Xx*l!70Z)=2T+JIklJu zPCcfB(})@7p!W!iHVn<83u9~1hw-o&#K}pg z)`ErIZefW%U}1|rW#NduVu4n`E!?rMEWEL`7D8;Rg%sOwp~OyDXt6{~Bi6zaU|lSy zVTG16v0BRj>@>?@Y_MfGHqLSmHp4OwyTCFLyV5cRyU8*G`-f!?_Ako`g|)NVgY~pJfR$Sv#+t2;V`o|Yjg7E6 zhfT7&gw3_OiY>OfgjW* zzgxTE4q1EQ&R7d@*Q}+uht^8m8*3e|&f0|gY&{h>VC{>WwD!l5ZGv!?HsLs~%^aM_ zCLX7?NybgHNy7!(WaHv&@^R@l3vlyoig7D!mf<$otitWKS%*7fvk`aJW*hE?&F{F! zHhXYyZ4TnY_H&~Y;WRRZSUg5whwVS+h@4xwy$u(w(oFp zw$-={+dABQ+eX|9+g98L+fLkW+dkY8+dz#_;TtO!O2d%_F{E+Ndp zlaSybAY?ko2n!w5gq03P!bXQFgg+d72}c|P2xlEa2sa#}2#*}%2yYyc33U$XgwGDS zgnox2!gq%y1ft_I0>^PR!P)UQ0^e~9LFKrU037!a0vrz#q8yJBk{wSGavjeTiXE>I z);QiIY<0Xx*z5R&aNO}F;i6+Xq0F(0@YJ!M@SkHd;e%rvp~JCX^HEc%*5?ZKE(Y_e#8?_ zLBvZ=5yab0vBYOiiNp%0G~!369Ac+a5pmdQ3Gt`Xaw5ff4bjSZ1Ci^zjVN^9P1HE= zBlB}vY7PRWf`f~Wi{!O%LY=P z%Qn)O%We{myPw45{zbCmo+5d0&y%Fwt0V)rjO5FGKnmeLC&h8!kkYu7q(W{zX(_jv zw4U2R+QIE3?dJ}YPH-nkm$)$bHkU+x#$}M-ajnP=TnBPH*OffT<&h`35;DYN?HoHcW{aoY8;jSs<1lKHbrfVU2f$L)Oa@XbL64y24-(5G7|8(6! zKIK|U{>SxC@?Ffxii=Z^P#ZlVbk|_gjnUwEt1r&n&VhY=RImN+!Eyc@y6Gi5}lVWt=OYwC- zL%6*Y+q{Nod%ebKN4+rgb6#ZnbuTvkftMZqUoS4b%8N&D^pep#y|nZpFF>F4 znn5Re2hrKyQFMFn1iFWJ8eQU@N7s2TqWgF+qX&AgrAK*hrYCv-PS5tx@d?J;q1gGe$e_En|RJ!JjpL&UgH14EaR_cKIU&^zTxj=*6{Z+oB2nXUHmi5Vg5hNNq!lVD0s|d z30^Vn1(i&9K?74H_{`J@dYM2l!ki`e!3+}+Sn&b|D@|a{$``n>iUr=RRRS4nlR(GX zC78lGD44}MDF|g<6vVJ@3g)pM39?zQ1PfTzf~BlR!5UVFU^8n_u!}VzILN{YkF)5) z^DGXg~Ci{*sg#A<)&3-FPX4eX{*e$~O>~7&w_ONgbds4WWO%Uy7 zGerm4wxSbkSJ4HwP;{NG65VH;MK9PhMDN(aqB?f8=o33x)XmNo4YL=BCfUnG1kO4U zgR@m+!zmSUIfq4j&fg+A=d#GaDHBcOJQf9VUW+0*)uIGWqbQxzAu8Yuh>AJmqE#HM zcq4}<-pR2N@8>v+k8!-k=QvXFHI7bvk26*LoZ~Nk#|am|=fsO!IBDW;PQG}UvsgUI zSt%x1l!%!YJH)mY`^2smN5uk*Gh(I16|u?Uj@Z}YsW`~ut$2<_jX24oNt|WTDV}dJ zC|+tYE?#Sam29z~N&c{~k{q&dlAN;el3cQoN^V(bCFn8&$t#Olk}8W(Nux!qq{AXb zGGLJ-8Mjy{!CEet&@9(UtSq-moGnWwJj+88x#cN|!SbSHn&nMNpyfkJq~%LVqGg37 z)3RPtWZ5eD)v`yj#&Sfm#d1>ehb2LJ$dVyFWoaY5Y{`|DS@NWhEoIWzmU?N8!bp!EmD=$A5yc`pVFCDC#4})7o;&( z*QF^|_oca3&!vm3%B3r<-b+iYnx#9fx}^K92BpWW#--=2FtY1bRM`V73)xF62U(?+ zhwOuuNY-YhlJ#4eWMfvoGOYD%8O=IUW^J7ybFogB@vZY^3hTu(ll2Ojuk~-TVC!wN z80%8mJnKWUTnJO3A%#v$tLgm0FMn20XSsrea zC6Bi$lBe7JA}_RACI8iCgM5w64*3?Fz4B6YYs6<=&GE5>YZDX?}A6m+{63LCp}g{xhyLTJ~dP}{XDfZZ3xEW1%fxZMv$ zf*nDbVMkXM*;y%<+BqrL*?B0p*@=|qcMSD+lWTcZ47w?av>U$3;V-=cJ~->vkvKcJM`A5|Ld&nSKEFDrxXZz*H#A1G7p zpDXk2%az6UHOkfYjmpjTZOT&nUgZ({5#<^C@5-z8Sk*mys_LaZM^$NWr}}8mRdv|& zR73Vs)ug>fMRY(^YzJSJqeGy|%OPAPbBI$J9p)hxMvr zhb^i#4!cxa9QLb99sW}N<#1Yc*5Q)sn!^p%1BZL6e;uBxsvKUcnj9)sT@LlC5r-Dl zPlqlQ*>ON+>G)0M?D$i~cO03Qr9^yQ-5|`qyFN!Q9bUsLydFVqh>lC zQrkHlS9>^}RZE=yQR|&v0)WuGp)N7o&)LWhU)q9*q z)kmFvsLwg!H8-57nnz9?&1)w+O|27G)8gc%>2(rozB#Eh7-xfq?mSgv>+Gj-a}Lso zog+0m=Xi~e^E}OL=PXUMbAe`_^I}b&^KwnG^BT<>=Z%^z&f7J6oJ%!FoeyfxIUm#9 za6Y4XgHlk*czpYy+(G3Wm@SeIH2!=+JU=ki(O;nJ;N-m zOxxfRt!;Ois~vDj(|&i!(Gs~uS`K%K)``19%j2%qD!CiA2zR@77PnLz!9A#*%RQ>i z;{L5&$i1jt$-SoC$i1!I&3&jn%zdss!+oQ@#;wvm;MQwjahtU@+;(jXw^!TC9nyZ| zj%l&3KeY^3yw1**s`GH==%lW;I)kgT&ezpL7vd_=#ktCK>8=`Gk*i6!%+*Kto2#F0 zr)!YzplgKglxwW+AJ-(^UDtHoOV=D-m1~i%$#sdY+jY6_tLqva?6yHibK9n~aoeqP zbK9>IyB*Q#-A?GHyPeeqyIt1By4}#Fx!u(jx;@e@b$g-v&F!sjr(2copj*A}lv|VT zAGbE$UAG?HOSeH?mD{MU$!${C?S|EVbtCIxcZQzsZmG9*x7WM7yXYnEo_d43Q19z5 z(}%cg^l|P+eTMr~{e1VC`sMC{`V#jr{Vw-t{UP@R{b~0U{Z;o&{R8)W{VVqc`Wp9N z^eyfy^nLDY^<(ZE^f-@gdX~p7y@SU-y_d%!y~5+T-t2K&@8@w*AK`ITpXgDh&-S>l zU+nQjzsloZ{brAH{T`2M{ZWs4{dtcj{Vk6+{S%LFeYr=!zQNO(Bsu&81-s1V7Vyy7?F*bV7Gcedx6-(Tx7N6tS7O}C+hW|u+i5(` z`@?vNx8Hb&cgXmHcg$GH``g&WJ7?_ST{e#Lt{JiXG9#0J&*;E^Z1mzkH!AqAjR^mp z(Vt&!jO5oDlldQwdHhetU-<3Dwfr9Ac7DI{0Dr`Iia%z&!k;wW<6}(!@(HFIKE?Ej z&ouS%EllHl8xuj`XyORamY%@F#24^QYJu1^RUkLb7HCW{0)r_{fS3veKBi@Y8Kx3J zfN7T?*mPJBZaOQNW4bPgGd&U{ncfOgP4$9IQ@bG7G$bfA{S+)TQG~yktcA->Zo*Y2 ziEy3CAlzV@A>3jL6Yen0749}=3-_892@jf936Gez2#=fg3ja187oIa+5?(Uh5neUD z5Z*LZ3GbMig%3=@#1M{As=`Ibwb(IcBbwoHDma&Y1fo7tG_5 z%VvV~s@Xz%)9fO>Z5B%JnYGe~=4sNW=3waybDZ>*IYU}*UMQ_F|4&+N-Yk7@-Xr~B zJ|=B4UzC0_-;$%!DL&iZC$gGf+GFxPm%mLXWb4HHIT#<`159GGY8+k4hAXPFk(kzo9y)q>- zCet8zxgO!jO^CA`AOg7$qLKR|)8u|gu-qSslg~yn5~^AvnUhDRN_qx5HO}8Hm>JEUPx<3I`e+by>4+9VVUqG%u3e5Ur zz+Zm?MCnh06#Xespg#?k>Cb=?{aLVEe-0ecUjXOz7r`z4CGbpt8C2-6fF}J_(4)Tw z#`M<#-f#nO3^#$Zp$rHOw}IAh2TV8I1tEreAi;1SWEmcS#fC>CBjE7r2IcWaNNF& z5fsMU2N>orzyalL?guK=6!QR>jfyo7f^^gZ^AK2x+H4*Mdr-&CBj7UXuK6qY7gb{( z1+A!l)TH?vAS2&^H8KX=QBsr%83%r-NK`U10rFA5qJBfZgI%b@sB@^B$Rv1*`VZBJ z>Op>hZzw$Y0oW*KlmPq$TGVt@2r2=Ug<6b4`}$MR-u@J{zdr@-@lQef{8P|g{}i;} zKLzdiPeJ?sQ_$Z3l>h(IQFbUVlmZ1%0jOwH8mb7j0=03Lie$45*o?@TuQH5-Jz<3u^t;39u7&2z6%aIJkj&jCwb9417R! zp+={E16ZGLfaNm^98r9f+UG0qK?V7YfH+j9&oEesTIDkYwxIU;41yD=e|!eOebg(T ze()ak+2;!wME&sT1Jr4~zy{?ptp~_Z=4su)e_9uaLZwXW1O?MNz%o?Hw05w2S{pcm zIzR0*D4W&_o=y7%Dp5_-T0rl#W-vCb2@s|?0nYSB;4=Lq5KjL9bkiHabX4f{dN6l- z9mt;k9xRz&3)W1p0o$ing9Fp6z~88=(<{Nl=@sD3^#4Hp^mm|rdN~-L{uV&KZvfr* zHL&-61-yL!1xnwS0QkNDfxgc{wC^*J=KB;B`91+Fd>@02zK=ku?*nku_ddAjdk@_9 zy$fFW-T_s2m~k2$oN)@Ao^cXfn{fg>nsE%gopBU2%=im*%s322W*h?W%s&BR z<^flm9r4gG|L2fXBoiQEFB>DYXHYz1)TjAKL@*53kr_Gg0uerWWObbdyf`gKg z_@KE+W>7q`FenE3Ul4kp3JOQ|28AHUgJvU_g8Y#?L4L@~AYY_9$OmZ&0!Uww37H7e zBg9}0ViBxFT!LkYFj$P}f(6L*U~eQO*aL|Vc11FSosmVs4#=utTVzYH6|y&&gB%ZL zBA0_{$lYKv@-mo!R0m^`mf)Y}zTofXiQq9aG32Y+B4o(y64GxLhV+`XA)V&wA#LW6 zkWc3LkS23x$OrSnkoV^Qg`nrtkP7qOkaF|!kXPnQAur5#&uT54Vp`n!2$=yvm_ z&@JZD&<*CJq3g{TLRXv1LRXrfg)TK$gch3{Ll>I6LyOF#p?PLpShkrJmTq*^!F8;T*FpoMASFQ_X(iL~}$q)|?dn)07)N zVJZ&)W?CCQY}y{)Z#od(V>%VyVY(9DYPuiZWO^0;!BiXm-qadiW$F)qXPO9qZ6Zdz zFj+)AF}XxMFbN~>n6wc$P17Q-nt~%Pnc^bOnKB~&HZ6!aZdw^}#Iz~mpy`i@y{5k+ zcAL&e>@eMm*kXDbvBC6T#5&W*h*hSph~=iQ5xNhTn z>M{Nn)o%Pf>XY$M)JNl)s5;}dsA}WGsCULUQLl}4QO}K^qaGUvqV5?dqsolrIoFJq zb1oaXbIut>bN)7J=NvOmn{&t*JZHZ#Zq6UZ^f^0?^XF_au9#C|+%RXYarc~+#v^l< z8qdyIY`ih2$oP0pp7HIROk@3=6l43GMC0I`SmTd5kw!{%h|wxK(C8XH(m#c8~xKz zA3bhpiykoyM)w;gqq_~{m^OoDOpAdV^T8mBsWoV0Dh$(N-WY;nUKnCy9vjkP?iq?= zZW)%vTs4%$Tr~V1bH;Ee=7iyN%n`%2m;;6fF{OsrF*^;lFvM6Ab~eF@`y@5r%oO!G`=;f5R`azJ|52z_2~mVAvn4 zHk^!=87{{P4R>Qb4KHH3hRRq6LsP7^p*xmk7>%VGFmVI}Jq|M1#ZBlv;=bx-as7H@ zT(^EkT$?^Du1TK|SFg{EtJW`!E7z}#`&Yj)?uq`7xcmAeab^0maaZ*>;x6hR#huo_ zi94>Zi#w$M9Jf#3AGb^YJ#L$x7{5W!iC?RCj$fhY$N!>N#V^o<_#Y*7dTzp`PM9#N($r25=!A2Nbeg$2I-j}ey4iD+bkTETbt!Wrboq0Gbid5?)2*HBquVyuq}w-FqdPuV zrn@*-pevi}p?f;lS@&+Pt*&7%N7p`=svDe(*G6q9Rf*TMn-ec;OB4Ur{*`!Cdp7Z)_IhHe_F>|7 z?d!yi+SNB;kCDuerld2ebc;48q_o-b!*y_ zK5GV(8a0ziwHjjbe;Q8mzZ$3HCmLSzU5z67hQ^$HN#mD%MiZWVOp}m&P?MQls#%b{ zU9&uSqoyQzjpp~{<(fZ}7i&%>7ij)T&eGgXo~L=99IvTJj?{ci4$^ca`)P)fr)qvA z8#JVODviZFvBr6xmxecwt5MFg)0pRRG=B4_n(%peO~Sk%>dbkg>iP5f)ywB~sY~X4 zQtzDCpguUSN_}$P8};RR&(*i*Jy1WJcT4@>ynoaU^UkW<=N(rM%sZt1K5vhjkg`L~ zPT8n-NLi!yN?E3sr7Th#Q}WfmDH-aJlw@^mN~}69C0t#Q5~%()#aF#H1yOHJ(W>{R z$kazu`0Dd1Zt5E;4(dlKmg?6jbahP%LEVz_Q`M95O*NV_pn_AoRMgZKm33;pikn)g z5~jXZsZ*b-KQZW&sH%W8tSU0?yD~9tM46S=t6Z4Yrd*NMs4PjVQSMADR~|@vt~`1xjvurc#ieq*SHHD3SC~ zrC++gGA!Lk8J})crl%{FMd>2t(sU2yx^ySywsb4y-gLV1XgWc8F8zn%ditp1LHZZP zzv=CYs`MsBV|uNkGre3fl>S07nf^dQ%($gsXIxg;XPj1eWE@pUGWIKU8NVxhGBzm! zGuA4iGL|WlG8QVbGx8J*Gtv|*G7=Oe8Ig(|89|Eu88Z~eGZ4jv42|MuhD7lw!&~t> z!$nb@VWViuU@E#Yh>GEipYk6W-{hpsemOg{L++5-B=^j$l}j_r<+{x0a-Yom^1#fS z@~F&9@}$ha}i7x}TwBKf(@Ecx}!Wch>482QW0 zPmCN$8p391}?#otX-H>g{x**$?byD_c)*;!+tWw#ftZlNgtlwmhvsTF7 zWG$A}WaZ16v(jZRWkQ%kxZ2BA=6|#$UwG*Y*sc^ z7M6{X#b=L8)3OJp`Pp64;_PPWs_ggDP1)trUD?m22ea=>Pi9}2Ud+BAy_tPd`Y8KP z>8tENq}AD5q>b6@q#fDIrGwcEr4!k?Qd~}ol%5kOwaE#Sa&!Ep{G6#$WsY8I%8^NZ zb9mCA9IiAv$3~i*!;og@5TpxoCMC;rMkMQVdL-L&S|xjO>Lo{VDkNueUP`XyJe1tY zxhZ*?b5Zg(=ai&2=a8f&r&Q9NvsE&jvraOZvs^;RT_|DZ=16RFQzWjru@Yf!s6>@J zOJdHQBAJn^l?3NXCDFNFlH^<`Np`N4WI--XvMd)XS(iI5-kLioF3s%}AI@zO|D9VS zzMT73T$cM({5bcH_;v0Tadqw)abxaLaYybx@j&hl@px{D7@N0JOv_s=w#v&FJLjc| zz4PM5(!6l7F3(>)HE*ieKTjtP&y$Md^Ss4rdCubeJS*|yJeqiA9#&kEH!j+dHz3-V z*C9HZ*C;xZS1r1d_gZu(@3H7t-B`>Dv0WZ1eIxnl}9IvS881I*&eY{mg z+j$#`*7J50E$8hmTEII}l*RkID2aEeD2jKpD3Eu*$cOj5NXIKLlJaVcJb6t;4!n*c zHt+vfd+Ycpjz50*;vPZ-Vk8$LI0OiRA`2uWBoHG4QQ}7YTz6We1zNOFij`8V1&Xy$ ziY$9^cXxLe;<;xw*-*ay^?5zdAHR9!eee0menxg?cJ3~F+n*r6d@NyRnK)s1nH;Ti z*#cVqvc&qx(uP+TV_kUzRZbsVVMW*wG$(?|3a(--u&rf=xaO-1zkrs?z>rup=Xre*Y#rge1Gw3W^I_R$9mZ-?Dr2eXa)!3)I);j=B}2*-VT_yDF#1d!7|kYbj7k$9 zM!rc9BgG_=@zx}s@!W*Xcwhn;H%z`}Tr@euIB9Z;AvC$ppqu={h%|Y~IBfEq;coJp zvCrfKW2Z?fW0Oe^W0grUgKAR6SY*=3P%`OcNSF*TMvcc9-Ns@@qp>Wr%vgn)W30(c zGS*|hHeSknV!VQR$Jm^C)p#@WtTDnoZfwKk89OlJjNO=_#@k1_R(Pcs)9Utr1_|HzzLdW$)*^d7Tq>0@T~(m$AmOW!cl-~;2|Elp>> zSenaxu(X7Eb7?j6;?gGO$)%l4;nIF4ZRsd8V(ARiZ>bE+ZK)E=ZmBwJ$5I{E#-&u& z@}*`hgQaU&8cQu$@=Ld}W{h^ThK%f3?M6E6wT0D2?P66^2U!KwF;*H?%z8(aVLzuTv+q;Y+1IJs> zQFfEzadx@kX?Bj`d3K`V74~0-H`$L3@34O{{EdCZ@EQ9%!&mID4BxR?hKcMb!*q6l zVJ_Rlu!OzOu!_CYuz_u1*v4LA*uyq39Aax2js$I2jz zV`-4US!KZHPz{6}ErVkmMT1iu@se|#;U$+j9ZRlrYM0#R6fL>WNn7%m^KQut&hsU& zIro=foa;-HIOmsSa84}A<8YUhaAKEKae|lBb3B){avYa*bF7vOax9mOa#k&w=1`YN zakZ8xa21!Ra>e?Z+#!8kZo9rAw?^NTTd2Q^o2qZleXDQDeWt&SdryBi_p1J0?pb{Y z?lFB=E=S*!8?Eoh4b%_j9@LNE?$?jy?$oDqE%dqE75XUGK>s*bUH=qUPX8QtO79Z4 zU+)^XMei23Qtuu&SMMP=N$(l=wcbnaW4*WB+j=8tzdAoE&cow>m zycN2!yd}DHp1LlFC#x&uP3j!w_351CHS3(=mFryO<>*}DiF9u8Ug_NCJ=D3+yQTAp z_r1esy)H0(iZdbw59n;+6w&F+N%7=+Uoq<+Kc&@we|U@w2kDr z#lP`aFaDiRUHpQtx%d@dVewo3^r8>^fknyumPP6O%0)T++(iZa#6_k2SBon7j~3PP zZ!K!#f4``W|IMOqzF<*5KYq~&KV;E3-*eG4-(iuYVD}y_q zq2?(;s^%HN8_f%XCz_W9zi3_+{GfSL@U7-;0nofBplkjn2-o~w;G_9m;H>#l0RM|o zuvzoHV3npwV5pfQ(9p~f$Z6&XCN&BK{Td~LW{nC#xkim3TccipYcvb~)Myv{s?jaD zq0uimuQ4n*t}!OyXiN&CHN=7d4Jo0!hMdq&LrJ(@Lse+5p)NGhSR~Ze&=o3cED=&P zjD*ALrowjh<-%(9)xvyrb78W&h48idX5nM?ZNi_`cM315TM199+X@Bh_QH5|M`4Ki z0imb5yU;=1Q@BgrM`)q$FI=u3EYw#I6RN2n5lXAa2uBwt2)hW*^Fpxjdm(+{6=C?oYeMgZKM9={-WFOdyeqU^_^WW` z!bd`bg-?a*3ttFj7rqousQoSMQF|wBQ2QV(QA-qNsHFgd%4TIiVt+UQpc^ibvk12kfR5$e0Z1a(=k z4BfL}CAww78g$hHbJTFbMpR>gB`UYz3v^O-JKC$d6KzzrLQ7R`&`ec3^u6jn^tq}d zdQa5_y{hVley4g6{ZiEnWvKe15vqq#U)4a=Sv3T;Rt-lts~$mDsYas)s&S~gDh-uY zWuoIMY_vy(hc>7P(Gry}(R7ug=sT4Y=rfg*=v|f5=oOVS=(j58QJ``WrKwy-!&H7m zy;ZKEPAWIi-72@xO)9^jD^%{G`YI1lHI;{`w8~?2O!+C=rTiSNQ~nbzQhtS|D*uhX zQGSa)QO3~Q$~byiISDUSS#?ct1 zNi;xd8g*Bq06Qf~uuVxCtW%N&#!B*Fk&+@%R8j%ciVMJi;zH1(r~%3qwLrGwVt^~^ zfIk%V!2?ADa7~d4&MGbiM-@!~Q_&1WDlP}UiYtMO;%cx*aV^-aXbx5>ZU6>~7C>Fm z638lU0pki=L65?AP_KZ1Vuf8GO~DGhRj>w66>PvS3VXp13ijZX!hRrBa0KxR&LBkL z0Ps|B1^X4;!A^yPV1t4uFjMdbIto5OMZph9DENb6`9RPv9|Wr8LqMK<7)X?l0I%dD z!Ef?W;HG>GxF8=3j?2dbjyw%S$60jz)S8j zaFDwKcFFw+Hp*QE%jB*DUAY@TRqiJsA$JRm$o>r4Wq$$HvUfn9>|Kx~dmp@#eE=TH z{tDo)=YR{ckHB%+$ABaIJBX5f3jAfC0aw}Qz*hDJ_(Jwi_^;kC0af-D(3JfP$jQD2 zlQMsUUYWO`QRW>ek$Dd?WH9hf<^y;pgM&LVB5*|}37nQm2B=I5NRUYdp)zT}Qzjia z$Yj8OamWN4WwL;oOg7M!$pI=dxqu>*2Zp8dL7Q{|sFE%Oxza@-QMwqslr90kLEMlo z1?Q#9z%l7^z?QB6N2DvkVd*MxK)M?2f!HEl16E1b0z>IKpe|hxWFf|-8bFU!BdC{Z z0>uz%QqAD4R10__)e3GyT$XABC#Bkf03uGR0|ZNTf`btIq`JTkscv8nVItK77DFgW z^@176J}?N;BH0frAhIO~01okoi9Npcjd zfY66flN~pcA47qCjE-BtyK0cqB0iZb4jx_*!BLa3P{00wCNZromo_tq^M= zj3j1&CWJi1BxMHlK{QgtpcEnl;vK{@h&vEhAWlP|5D5^W5S|eGA$CG+fG~s5flz^f z&y)m1VlilgsD#Lc5J9|z_!Z(h#5stg5G;sD2tNoHh&>RSAy$fKfC0op2pNd6nHkVM zGY#q>3L#P<{+^ivzeD^CaS7s^nMuHdh=mB8nE)OTb`aZV#=$xWV~9mFV?Y67dU_P} zLo`E_O@9Pg5ZLqxcmZ*5dKml&@!j+g01)))K@bMvJv{&%A$Cpo0}F^{(|te>LUpvIdk)R)chicav4%>0~ANWwHYNFj)>xO_l-S zWGRTBECC@9hbD``{>dVMOcsI-lLf$ZG9Tzn<^knNIA11nz|cfCXr0Icl@pmDXCecL zCep#56KUYriBxcXA_bhANCrnIk^pN$1R^JJ;5YFBxJ+PR&%}GMdEy;dHSrc0O#BVh zCtd@YiNC=3_$$yo{u0!W{|So5Ux2jn=itrwGw@{mDY!lUJGeal7@Qn`1O(#`LEQMS zAb9)%I5>VE>>Ixec8uQv>&JfqCgVQ??eSYcY5XT39=ibs$F76cv8$kB>_?C@b_L*L zm%*Q7m%xLui{Sd$1#ouk95_057BI)Y1Ce9j0^hMyz-8s0coRb@Me?=o{ZAL?NJ)IJQ@#9j>ZDPXbgxOjRL`= zk>Jp11lTtk29VJZuzoZMn2rVl?NNWAJn9F;AAP{kM{m&f(GygDJP2|>x&zTiSMc)V z0r2ZbXK>@ABRKzYKREW$9|1xG&GfWsfH!GVufz~(^X5h+*3HWwoDL_Z4fHqWFgQSSpXJ{r~s)EMeuQ09&`@Nf|_AzP%tbBQidtu_3$+M zcz6>1d3YTCes~o9W_TFo4-cZT!~JN`a1ZJ++=bc?cc43l+fei2X4GW35!D{9N0o+a zQ1MU|Iy6*{whon|l|#j7?oa_L8p=ao4rQai4P~M?hSJgVLn-L-p(K<&griYI80tUt z7Ihu^8?_yJg>D`C6J0a(95otxifRo#M&*YdqEmwp(Eh=DX!GDNXxZQ`G;8oC`eE=I z`eN`$^#0&w^xEJ>^z7hy^sB)$D0A>M8aa3p^&LEcx(psg_Y8iCZW$D!s|IN~?5Pd#y7`;2-i~cy^g?={x_frFIC}Y3{ z4IgkseFpZS&I5L+^?(g(IbemZ9N38(3~Wc$2fjdM1}xF>{*7o)zd72_zXmPoUx}vo zFGJt;o1oA7jnKRO2I!Cddg!GPLh1eLXn6ku)Tdt=b?R3@t@>qA%YG?zWxrTx z&_5+q?;jV+^nVnN_YDbq`uc?peLcdGz7AnVU#sw4Uz6}zU%l{dUybm`z6#-YeQUJ+jH{a$#c_q_0{-ZMgG?hv= zAJL;L9PVBuZ0}YVR(Gok^ShOV$=!0o*WFUW$K7JV&)t)POWk9FlikAtL3h6(zPnox z(%mlb>~0n~bk_@Zb=L?ix+?_ByGsQ6-30=*?i_(kcZOiRD@D-LB@#4ry%&^p{VmAo zdMS9{^<410>vzGuuHOV#yY30jblnzw)pb+A?7AvA(sfyIxa)$zwd;()w(FE&Yu5?E z+ODqzOS^=EMO|EhVi!Xo?u-`jL@^ZnadeE0SQzFm6^e|vibe|>u} z-?ZJIuhZ_$S8ey;OSZf4KejpWyV~~h>)NdNMQsQ_z3mJByEY5{^R{*Tdu=QESKG|^ zXWNYUN89xI?6$@Hs5W)Jf14`by-k5{*Cx&1(I)1tZ=2wmwvF&~+xmH`ZCyO6wpQL~ zYa_3_wT4&UTFxtOE#hUg=JMXRX7FCLCiCvMe&AhieZxD~`jU6N^%;-T`iK|PdY>2A zdYgB!^#*TW>lNP4){DH2t!H@4TTk-zTaWSJ6i`=+^``=q&wd#AaS z`(txH_q*mS?pMtzTvjvAJ<|M^>)-s6>)!l~YuEgcyQBFYcSG|nu37Unu3qycu3Gas zu5|M$?s(I2Zf_IHZEWIl%bMui?50?*s40T`vMHGRu*r{mtI3mlsmYalvdMufY}(7E zHSOkx!y6fVnk>04P3Byird3>cO9*#ulOfl*NtdhLq{&rjQsqiCDR4hFN^!dyr#bbF zqnwh)K~834HwSBM<^0iD&-t~nigUBEgmbYmkMm7q28Z96#EEajIH8TNIo^#gIL?ia zIeQxKbG~T2%~{iUowKy@GG}q)IgWDUDUL+rG0w*ZA*ZW>&8crl;FL5(aWWgiI9Njf z=Z^+&&aVyboSO|!oQn;1oNpSeID&@loP-8TPFRCE$ERT>$ECr9W7A;3+1jAZS=XS> zF=sfKa(Sp5*Yr@n{XSl`Ajt8ZXu*H^Jc^(E|A^||av_37-N>l4|R z>))|Y*S}(e`e$rL{cr5Z`aA5y^*7n>^;g*T_2=10{b}~b`s3{7^(cEuJ)5mwpTL%@ zk77^Ng|Y|g4#S_V^ki4pxv~rD_Ony#Y}jw>cCw$6oV80(9=LDssuE|y7M3rnZ2j-^^x&XTGtWR2Hmv3hG$ zSWUGUtGxC#E4TJJE2;Jo>vip2*6+19S$Ar$uzsvP&pK0knsu!97>iRYWX067SV6UM zEYI3VmSb%Y%c|CwwWZdBwWijIwY1ibrCqz5rBb_ZvhfHP%pBL}oPE9p4wx)y`T$9W6s!3-$)rgpT zYThuvsQH7rw&pR@q~;z|r{)%OLCud$>6#17iR#nLzUpJlmTCdBvYN@vua0G=REIO) zRtGYlReLkdj1AwK+4qdIi(3dMVSjT90X0t;yU`t-{<` zEz4X{EoK;0k1;f>2N(*~oeXhRBV(khiqTnB%&4!*VU$#*GP0^ZFho_a8Lz6IGagqx zWc*U~3*$=Fb;g;hON?VxXBeESuNkpbfDux~W_VS_Gn}g;88%fxjBQmu4D%{ChFO&Z zL%+&~v9JnZ$W>V~rYqMmhANjc+AFDy+DaWpaiuyVvr>uip;C(RvT}<4sB(mUyRwIV zrLvX&U1c5pXk{6lQ<+bXtxTtfREp@{m2c?Il`rTvm5=D#D(}$OSKgp6tGrBKQhA21 zQTa7pz7nO+RIus86>;>=iU@jrMF73D!i%0=ae$s!v5)?`!ixT+VjKN##YXzIiq-UU z6(;l(6-(&+3N3m_Wn^vQr7Xvab^2%eV<)WeEwsWswPPWq}FyWnKw8%MK)1mf0t)F58{3wCsxnowD@_ z@CN+^nKGkS*88)iKXrFuS@IWpO%)#-z&|Jzh0Ui zf3XygKUw-Z9+W- z@rz15;+0DsSz2$M=_5#J85Lj;|>(i7zhEi_a|4h!>S8#s5_z8ULhYBJOU< zVBGbR&bW&u4RI$+D&jy%ejKwTJubQgj|(pOE6%IrX`D;RgSfpVKgI1R`614ttdf5nZ^EEv?TUckyh*vMar>filkzX7fr3(rQY7M_Tf zEfhpg7to`J3yws06$C~%6?jHh7C1*26xc>*6zqtGk2s6|t6)|1(*mRD`vuz3HwzX- zUoMc1{;ps;>R7>W6u+P=idN7V6mS1;-pI>@}o}Yc>NPg0hp!~m&c;!Dk zav=Y~5&Qg`M|S03IOA8k#d*3%vh&oABe5nFQCMVRNBMl8?Oi=gH%jL^=Nk5J2<375|u4wuO73?I*_4)~&5E`-0xIT`*a2MxcI!wA2gb0qxxoPhA} zat?+c&v6JBbGC%XK&Sao(nSaEh(SWdQY zSW32Q7?y1p_9`0*dzx(#_8@y@*w5M2uphG*ghs6H3o+3XRIH z2o1^33-!xR3H8W+8|sw(Jk&P(e(28Z8=+gWFNT_DpA21*jfNU!GeUKS!wKTLoOFOhYOC_`*ODZ%oYdj<|t1skjR&&UoS(PEb zXXS_7%Ss9PDeG;>m8|C>=d&J!oXWZp@>SNw5MI{F5PFs{Bsz;85}FkmayaX7$iXc4 z5a+CYA$D0iLw09v3fY>qDr938HDqH1!lGd`D9iHxn~vzIcBB> z*=D{A+L`$xXiMgUpbeQfgH~l;3^K_)8MGu*7_=yp7NnLL5u}jm7bKbK7Brb*7c`Qw zBd9lHV^CYh@}T+*gP_U`ji90o`Jn8KnZVSHp}-Fr?SZc|Y6D+n6a_xYNDsW5fd&4Q z@kij5j9&vUWc(C(I^+AmV;Ls{g&D#?Rt7yVJ|iM9GQ%%0IKwT_H^VN_BV$LPbH;{1 zyNu<5RvAkIw`HgYZpx4gT$?c+usmZhz$l|FKrf>@Kr5plKs6&RKtAJLfJDagfXVdx z0mJFn1A5ah1hl7r9ng@@52#9y4=7F#4aiOR2}nr~l&bmwv_n zQ2KZNF6m$S?@MR-?@5pHN74iQx1@XcZ%E(gzbbvFziGOKzhU|cf1Pv#e~okvf0cB3 zf4TJO!xHI(hbPn84v(Z&AMQ;nINY9=dbly|?cwUQXNODE?j6ogyLLD;?cCwywBv`d zH16ToX|ac2qy-;-oaTA>ewyRqpVO=kUrVz*d^v5^;d5!!!>7`;4j)TXJS{JhiN`MIY(_j5|S?`M~G-OnoRyx)$r6Mmc1xPI%?V*OU7 z1^bz%dHPY)9Q}0Dto$_7Ed5l|R{6mn+VYc1)AE~6RrDK875fgR4*7Pcw)?iG*7!E0 z7W!7DruvqozV*#dede2)de1i{^{VfO)U&>SryleDGnM1}BsJRi*VI7YJE;eKZ>H|| z{V{c?@5NLL-!rKze7{LG@I9KU?kh-@^JS+_`6Q(F`$VU<_=Kfa`UIxt`uLiEc{!v7mjmGqfN8TB4X>GJMRsrT+oDfVtj$?&dE!Mv+dUU-+JJn+s>x$d2n za^5>N<+!&fh3ow`CD!{@N|5*SltbQ+Q}%m5NZI9mJH^8LM#>8BD=AC7FQ%w_pGlGR zKAAG_y*8w5_F9v&+G}|V)yp_V)5{=5!Amz~+EXiK&{Hj?)l(^@ z%2PHa&r>2L$#W|CwdZK^W6#0l+n&A2mpwa@PkA;cqn>riG|$T9aL>|YAJ2khXV2{9 zJ)UXFTRan!*LY&dMxK8sYkB^etmyeHdFIfgBIoeza3TOSHc-h9Y6dG(<~ z$<#w`$(o0pk`)f^OP)SxlRR*6cXG?Y?a7q~wzlYWY2?g$qomll6N1RN!oO9B5B3Jk4Z}o4kW1`>`9V6 z*pW2h(VW!lQJ>W4QJqxgQI?eDQIzz-BQNO>kIbY89;r#!Jra}7dtgb&J>Dd7JYFV6 zdpu7H@c2E+-Q%|;dyjibJ3M|)TJLcq$<*V=Bpr`SNh%)alO#O8OZw>kO;V@(v7}me zkW}c-PfB%XC%ti}Cp~eGOZvqt?OL9g?^>Lg?3$nW+BG}zv1>-+&#oznms~}OCta~bf$N*Z zc-OxYLtOtz^mKii=-~P|ahL0_i59N+5|_K)PSkh3nW*M^Em7L_hs4nX-zRn*IG0#= z;Jd`411A&H4xC7Qd*G|Yrw7o)I|q1)R}QcfzlCq6z=8Ng`hl3l@B@*F-Uq@Goel&g zS{?9Dv^?OOxblE!qQL==MD+s)5@ioKB~G~PPwa8oo7mv8C$Yq3cVdPMlK9?bYvOa4 z&58G1EE2D}m?wVcvL^9M7x;Wtmt~0&F2;$zF4RO9mnDgNTyzsRyDUyz<)V>j=%SXW z;i8f#=c1T6=`5Gn>nxqv=q!;~>O3vVbe<4l&ZD9i&cmX6&I6*W&b^{D&RwFfoZCfA z=N3_fbEC-DxlZKbTrJw;Tp`-xTq;`STqH7d&KGGo=ZNH-Gewh5X`)`IWKpA&NL1>C zi87tuirzcD7Cm=*CA#PIhv=%)GtqZWzl*+fg3qgUdLW8$x-0T^`bFgIbW3FIbVIb+ z>8faz(+?s8r%NJrrwbxkr?aAQ$8SYFj;BNoj$eyP9FK|MeR86Aj;QFFBVTmakt4d| z$P#_)NEZRecoEGpRutwKCGvKR5IH%9iFP{%i#9n1idHxt7U?_sh}0atMAD82MPm-` zqArI6qB;j>QIUg#DAi$~=#9f((Gv$7(QOAS(Pf8SqEik#L;{CxqIicbq7Vm5(IE#5 z(SC>ZqMZ)wL>nAdi_9EWigX>8i&Pv;MG_9iqLKYnQTu)aQT2X(QT~1%QPTd!qQCZQ zi5~6O5dE}YO>}X;s_4XiWf6D3f+%LcoG4(wjL3bzlnCC(DB8Av24A;-3OC+AfiK!W zhAZy>h)?eu!Uy&Z;4S<5@bY~%yDt+Tw@=4=>{Ic2`((V>J`qo| z$MLuJ82;4$J^qXRTl@$6zwuM{f8j#=mw3GWA9#rUbKKMZDZbzS3BJ?*F}}h6A#P^> zE3RXIA6K!zhfCPs!H4Z`w??bI^$p1I^k<<9dN4ceq7UbA1-HWk5Agz;k`C{@kSdP zyu@Y?o?&B+zq7HzpV{oj@7V0Zuh{IwPuuLkQJd{}g3UHO)MhL0Y4Zi{V6z3^X|oyM zXk&?+*=)jfZ7gsVn~gZdW&=LFXFcAw#~iQPvkuSQvldU>vj%^;XEpxYo>lk_i1T|^ z;>Y%^z}b72<45)^!w>H8+#rNzn!M8xH+GC6x?pcbf?=iw<_fYY1YbxGjZHU)f z8{oy(OYk&^x7Paj6Kg&EwzV#P8RDe14lc0P#^WG@trz15try|@Aa+=5;pWzwxCz8! zYYkipV#Z1xAGBJCw?I@_so~iWxYYvu4~Y9#s`xdCGgd12R}c&PWmw%81~hQYeflY34txk^6-pX_6_&TZrr?DKM#2Efvd^FkMK%$709hlLMP&=&t5Ehd z)C*(*^ySMQg^oOm90Ll{Oo>itm)ii%(m>)q%*#u!gmwir=?C(Jqaq)^NdG4P9GWDJ zDT+T5;=@^!q_H&o&37n1l0O5rlE(6izJ&OgbXJD3PC|nc5l~+Gdm>AOkqd=6>EGqI zLsHO|u9061tE)H;U!?2g-;w2$9S?Vk8l`ffQvF&l6%J=`644M2JoDmN1~C zv9jWBB7QR|swv(hLbc46B5AA%YqA6?l!%7N5v57D%HM@~dFiE4tt_Dc^Ahp$v)u`; z6g4OlN#Yl1R&k?9B*?FYIVx1C5_OiK%~oS6bW3uK zNN8Ro1Y1&YhH+)~k^&bVEn`OtL{J%fQg}oJ+(!za3l3cHAC4y3Sxh~_vaP$U*g zn5t?hNvZ0oddM!6aFtM#g}rVSZLL zUUoTj(pQ0Jfb^CjyyX|bC`3j<<1=4HmAQb>Ws4&05i<(mqP!OV;{R+xGRu_hH5N*! zOYD-pVx>$(SCN79hbYQkLlRa_6^cZSNO6J1|A=Z5680LzQ45V=;B_(-iaO~4s{)_J zLDBfkABvj)Sa&LKS0?%sCfIjytr5;LF=AjIw)vm51!m!MOb9|Cq$xuZF1LuB=bV9{ z!=DU9E@I9=Q0ylIk>ku62tq#@h}_vZ13{NQ8Hn87IRiltKN*PJpK}I+-h46;x#T$m zL7ATnM6P(wKv3l;1CgtqGY~|yf3AU0_>|yKgFSG7pm~P_w?0{6hFAJWFT@k<_rYQcaiHY zBKLUCK+t>_x!xjj@8%2y&3BROEh3jaXCP?4i(GFJIilIHx-j=C5f7x1ptuo)KoAvm zn{6}U1q}odEuAwExu7`%LGx{Pn{6{~&Oi{+(zzpu+{rluLGx{PyG7)FnllhI-)6Vj zHb0p&5H#Orx7jvha|VLu+w3;m=G-|0LGx{P`>f4wQ2!}yfjLQv`7MICLcnQ3kSD1o z*n3V*5HbD2OFookZfFCon0xk(7L zF)k!BEHacvp-05g7*u8~Ju*BtG=xg*W9f`Q29y5zxr3V6;83Ck|5Vt`-rL6C(cTT# z-r9~5Z#7#R_rRd&&`;I3BB~!29T&*>JlNbopnNJaI3ketU-h*x|HAT9ldWc({2$$E zY4Ojok#LNBswiwc?3;h;>u%%b?r*!>-oeAw=2KY8UMCN#H5E>nwHC8e#(eXJP1NPI z(CE-WdguzO4?I8X=I7NK3;!)^g5cx~j-b*)S&?)&HK`lcZ(MJ&*^jy=CODqCBN%pO zC}&NK1(X>P%$Oj^VNf3y&$3uUk6#nA-jdJ|U9tvF$Q`ihA=EYDA?!d}*qRO0HO?EU zYr^G=%I6K0@Q^BG6FxB!{XP#dBUIt1~YcVg@uvB zYo4gd7tZr8mYjy6v2lVkP1&8|XwYH`Z(|xwDXX{IZo6V4C^nb z^#5(jtT*2T+V(yU$)Y;B|%y-KaL?#e?cXiwh2= z)8lCL75^9J1!eaZxI_mMS08w7gIO8txhdjk0UvK8=cpj5D61~5DWN5?SV~($M?zOZ zPfB0HK$3XNr3~H0FiB7(1**y_6iq14C*o>qr7C}1@&wGRrE_B#fkBWNv^kEL&%xQq zpsXb(3T15&olaQ`r}kPxx%U6)UTBLW9HGl+tM9*+vuoOHl#tLMW;k4%!{T58v-!ZF zAh<5fl`*G@jtl-=41|kEcqmzmIgkHS6HQ#1$%wESl(oTeF)^WV$gG9uX>A|_E)79U z#{WhMgFA!J`M&x8!+OvO_8di)bhh}{L9pf(zB;#yB%bz2_z)nt}I|LJ5GCAnHfdYrcL*VgB=Y*N(&Ypr0w` zvzPwm_xJ>Ss^xs8KC=-!-p|XubOXM*g70gIa+M(F%f0j2F)&LhJVl{Ui42+M%O$q3 zpT|qS4Y#*YN5q3~;XlPA_RjOiz$|4D#v}aZ)4c5kRD2$<__KHmpl!Z>=`cTk3=u=} zG=wBQz7xMyS!iPvx5c7FLUVZ_B$dGBi3S&_IydB-Q|LNyN&^F%= zqD`L-H;N04M|^5EpXRd!!{PQRUHSpG9V&F8hUgn2o*D#E=I8N}f22?r%?E+D&$3YZ zCw;D$rVNPxu@Lb-w-WN_H6i5BOC)4ziq_`=psWq$=1;o$UYb)#!BvT{|C3}X#CkQG zb`f=+U$y2`QWUv=`OE!t4rcx3<{Zgaso4?qk4lQ7_>TZ{QnNGZAC=VXO!!f63qd zOTPOr`OUxNf`7?v|B`3^CC~1k{=GXfVNgs$KJETz-@MFUOJ^^e|K}z5KQ?T$+y4L1 z6K`MsL;d;w|DT=f>?ZL)yy0%}KeWU?_dnEdKlmS7;{DrysAsocb7NW(E>Oh!0Uz>9 z=_VLX%6@|3ARZn!Bn`$5o|Q=MEfDn_5)<%+DXXT zBpZ^viey`oJxC5AnNIRmlAnfmV0c^%Dbq+fx&yH6p6YDpjC*IExY)0}LlGl?=e5FL#_mb>H zvMb5HBnOZjPI45`Ie@XIjlFyQSk>uHV0L!~c$`43>MDh!gUy+QHoJ?{S$$2DK zkX%D@Gs*2F50dc%Sk4_awCr0M)JSsp$n;ZC)tN& zf083fo}HI44uh0AB+t%EsQ;RjXXhuBFOc$el5dfGpX7%m&(2%u|C*FPkeozv4#@>1 zmy=vgax2N5BoB~0Lb8}-DPsP@aui8cC0UzfeUgcH<$CI8X}!hz^_CkfEX>WRRQLze-0OOCb4yE0Ds}VvEgQDX z>H`#kjf3sn7X>gFOcHRH3yb-bcB#%vG8VI%<#5leO&NPBZF~8JfwO^=?2o1al`me7 zP=Ir%htw|#Z2@M1^$B;rT%K=O0kv_e`S8`>ut0+Pa{$FOFi_rB$2RD14O{W(j5y-O z*n4THC$tn(9b3xE!F-9O6ytf@musX7cFi8w*d{iuZ&RDiSGQ3V%yvq?I zlVUOaDK0V64cQ`6j1)uew-h7KAwQNDBPSq76wV+{kWGJ{K~y0(#LOVcGh*!KwizTI zvbVwvq5*kP*);NKT8tIlokqTZe2zAaU{hkuVHcDkE2vH*4=2S~YSk375c09#rjXbP zF}906g^0$**z}$$L<#a+^(kcE7_3+QB=Y5`7_)o=p8@kxj1BWAk=zk6_QHM=X&n}0 z35zF@;UO`$u4Mul8x&)`FD8(o0WtRbmlH@+zZi>lnm{u9#MmnR3FJYq80+d7M|eGA z?9pH2h;_FZi#jomNOnQH+c@&N1KO$MNN_uBckdV?(dJ>%`b*(I`Tx6=M@;M-ks@G4|ef6nR=H#=crPij0+uu{~oS zkmo96=hh#Mr|h zN090a*v_yKBs)!vZLt_ZUZjXIisT4#E=i1~=M5u)A~AOU<}kAIgBbIQ8b&(ai813Z zhLNA%h_N2oVZ{Em82hVu2+Aq$?1F&$(G`TmI*Yf&0PR35{2 zRSY7+-^3VrFo-nWhkndKWanKmre{5fT(~X9I@Jb|%Ads8-?amX_6;$1>hS>Lcom+1 z-T=b+0rsQa0CM$vcpkL|kmu*cSYA^9Ktf4CU?<4`Zs9W2Jqn)V`b0b=aPP!H1KE5>X^J&2bV?2mIj$OjKGCgInE z=(&oqx|KahjFTAqFxHK{+6T)^?M8-eVY@GNBP*=M@aLDi5%-;9%-XygVQz!v&U7K) zZ5CsS*qPFTi!pPBPQ+7HjOmwkAX18OT-@tG?#hU4J zsTr(TwF7Y+o57N++mW=P8SK@=c4Twk4E8Ih9l6;#gI%|6N5)%bu(O)&h(p5+cC4`t zxm-Piai6sz#bq;CJlcjR6wP4a4sD17+lF{#%wS&atw>Dr4Cel-72$uF!JLn` zBH+yo=HS|ja9_?~_S9A+^4Sb#*V}@)JetAwzH33&+=qO+1)d~W z`2#$DxEa}TVFq(cY(_f1h4IffBj0`v%RAhR7=JZ`MXYW{p7UXSCYq2$Ryz5@lyFRn2c@1Lz(=_(_ zV>RM_Wg6>Au0~?dPh+OvS0m`DY0NLM8aZ)v8oRQt8ac|J#tNt5ZLSPhZgv%NIA$7i zyjF$m2%E;vL{uRf{?k~FWff9;Xc|+KsX~5sna13TDiJSxSpVCVh@90lRu@-^Jl;Bu zEki1iy&I>o1m#MkeAP7euCf9NFqy{Wf2%-h^rx|d>!z^Djxyw8*%Wr@bs6#` zZwmYK>oNpSo5D0a%8-l?QyAU23`zfM3M&~XMczN1!nWY0$Zro|+_R;~>048nv|lL_ zbY%*QUR8>$KR1Pyj+Y=KUr%AX(@T(N=oI$khY}=^HH9q+EkWdCr?4{{OOX4aQy-#AG@P5XXW^?9%H3WLx?qX8KJ5Lj5p_z4j_&SmByoTy1` z!__=wDsU1j3(rGXo|71AnTNDFO=8Pr@(?GRNvyCa7kRV|>VL^aX4X$)YZ7u1yXBKu z&CXopq`@S1UNslNG$*k=H91I^;v_clC&67;ayAQ5zc_&z_+=rYZzizbRar=wa00_8G7(Ao1a>JS6S)*IfgSlV6VX3BfmwxT zBG=s}Fn!BRM9qEz8<);R1jqzdR+NF%{68$6cU;Z?`^N2&ogLYGm6bZ@eP8y9kG)5> zd}NPoLZT=YC8B{yLlQ#geK#eFGP4SinbI!vcYdGm{nvS%ggWQ_e!cG3bv>`^^!>rt zPv3!A*B^Xh?H$;+(pMA>x`R6nfAG?JcTlC~4<4VH1hYTotO-qmRbe@I-md>_nos52 zWK0s=GRnDzk^VF49+vaZPq%UEb~)!q-iC*+oIg9<#@_I9emC_tmYpl-*Bx$SsCPMM z7AB&RtNwXhB3{{-^INw>oY+#%ALl1x+^TZUHAzJI!g4PAa|qYZAsv{gCJf1Us@!*bpln1GUMueR|x6j;WI-{WxP zr2hM(=}niE6Vu6uUK@OU&eJ(Vo^4^jK_M%LN~IE zotMXAlUD!d7P07RQpQbd#^OP{GM@h|2CJKtaq#&VR52*yGTRs&{$0wWM#P|gekq@5 z9D@VzOF8d-G)mJ;dBl}y%tMmvFbwQLwpP z!q=`xq591d9&sQFCqhd2+4LxM@Gaq$ouhEpt%R$T-b4%g681^Fi37GJto6K!oMk2a za>-4Mm|em<`rp)lE>Q`$t$Gug155bM;~Qwvr-av^y@3fGO1RC28`#>UgwuxJz{wgV zyr#K-ckU}1C-J4IiC-=!k9JA4IC{EK+Yyep`1q=+|~TtPegB3}PD0-BBb=cy4G zy|jq8`bJ><^djE9Is#)x74e~g5r9PzAFmgI&fSVQ==Eh(Z&Ac**kxqYD&j}GE+gny zA%7cx8LPe(a?LiE(IvBxyL=DF^ZSK7CMF!aqYHVBYdBh8D&*ty!*Rv0kP}S9G0?4$ z3oC>pc6T9ncyI|8>k4_M|0M)2EM(WUmr!?dAtw*M1e>Ayf7kF5xNjj_W`&`8heCF_ z9EOpN3i-*NFzl>S$gL-bA*85)SF{g9+WP`l3oqj9;{vXqa1p-}3fTJSMO3+3z%h$2 z>i6pcHtv5BWk(BmN7ajXZ(qP~pM>h?)B+xPE);%?3pm_16lRZ4SKZPK$eF1N}9)d{?3poEk2#P8d@XDDXI8>0&-@1mtC@Y`W{s@NegM2Q%8;lmQ z`MldZ7%rFcx$cT!l=|kgj}naOhx562onTztna@cXLHM~cpBG*X!oa!tTwzxbwvNqb zzwto`(dP58HbHpYEuV9~UqE5=eD;jJfEqRRUw6NNMrGf*c;N*!{rH`O`d&bTr{8&D zl?$kN>pL4i3B>1!@BAtt5Q(S1vyW{cyxqR@qLG1EYWJOcGz&zR)!(`7(|Np|`<;_+ zoQK=k@9gb#9s{)BdF|};c--|nkLht9*3G_im*3}5Q0+U{ynhbsi}U!K&pCX3m&cD+ zpTn$&c^p0H9HL|L_+o=|Xc3mjzF7fSbt;cNA_8#zU>>{J2cT?A9y?79fax;*W2XRE zP0M5F(zDn*ERT;SorO=IJoY($7MI%OamezsxLG%kS*w5imCKK6>%aabm%nD5fzPvC zt{!#( zTAv1w$mM0`r!li%E(g>+jjwHUIs1h_*4NABE+PIX`1Os~?C{63FW)$7oIjqVf74&z z{;;_9jc4ck;mGB093JO~_rBk_)=@w7bpFQ6miS@C)^B{r%n$z7-?(QDKir@4jXj_H zqG0eht`zKx+9uz4?RH-nxBSN0`p-`5So0gtY3+*+B{`h_-3LbRa(HT-52~l-@UtU6 z_@c{Ut0g|Tbs>j8nfbueGlw_U@PXCd9IpQ26k4sx;gi9q@OVxR_up{}cB6Cn;kZ-i zV3xz{+nhplyBuy>a1s;h<#2TTNj(4gm2EsuV#cSh+`{@K?mzy@spco4js42|4Nk%@ z^eYc}<&B@mzjDQk-Wcofl@oS(!(-i7J~YuAPprQ3wD#VpJ?1NSEIt8?0bjW+@dT{e z>;E0E6WCJkD_>ZC0*8Kn;RDJEczpcA%j@bNAAR8oZ;saG65wSIWv`K&KoGsO!hM(CgWcwtf>{hzP#Ld914?;qlY^ELH< zzmXS)7Jp{#hhs>8^O+}JKZb=VpV`Lg7~V&IX2&_lF!#)74(@dfDK4M+L4{-JyY(~w zeCP?cC7-!lfG0jo_{?)Qd7_WoF$dl8%;qCcv~tJPX&?EcsXOit`pCO0yTh#eM{e`f z4aXaQ@(Kt6aKmNe+ZQPK;A9z!tD=J_3z$S^VFg@~tzk0c1 z>W&W_V&jUn)*pBcTwy=)16wrEf9A0E16O~47>7H4;OEy4<3PO+9Oif!o658Guk&G8 zz02lhCWoQDm(61;9Y+1gZ0_^K1+V%$~jdr}}zSmgIHhmj^9r@2$zg^+_lp|_$R*Ob>&V74tvMZDNYFSddCg?oDi`49WPt&1drwK zIDUi^woQJ=?Twr;OL@opzd6FB<2%laam24W?|AM}NBwy!i&L!~vF&x1UN3M&&!jAl zsq2XJOIbW9>i{+%&*Fru2T*@c7LRp20Ker~{9?`lbef#SD@+gItTu})RXG5o4q5Dz zz8?;?vzUVS<4e(7&f2*j!!zFU!Abk!b?Yr#blQ)%p>O$XxdYmHzU9;R958$5Tek9d zfYZ{q+Lc6851a_YHUP(m#LthO4aD zhirbs9|rD2>bW@myg4SOH9N81r^_~;^gyy^Ld-3Qpi zv$6hpEqe_6{hCj{-iy!gUvpr@UO1$@<{SI>qWP8AoH~0i0=!@I7n8l{y!SQNtg;vW z%U^TPXM12c=`~La*@JBsui4&i4_>x;&5={~pl^-WoY!R!cIRbs_uspb^fZ%KKG=<_ zoXHUZyP*ll!}?Grj~lle2iIrvnRdHzZdNA$DzU?j!I?Ze*$(ktGMRntaI0P> zcivzJF3I4dqwEltk-^oB?Qkq1gMVi2f^BdH7arV&f7~;;q~9*I*pk7OGI!$bybNx( zeORrblb<+iXR@pD%gQ z-7VPq_9fTfum#s|zvM*YE%+Atk{xbuhSAZNJaO%2VCzfn)M7Jc&40;NZ*9V=5idD+ z)h2A|@si&*+k|a~FZJgiTWl%H!aDN>mp8G+goGE|ICdj?2fbj$W+Q64zTg#& zH{$um7aSP90e-Vz@V9?AVBX*tOpP|6N#_@QjMpQf_6z>GY(172Jm=*N*Q5Hg=lo7x zhm-1awqCXlUC%t{BExkEJ@A~J)wSrl>N%S(TZ@yEpL2%cTGX(3&PUZXSl;S6Pg}MI zw<(SMLtTye_n-00Wvk&I@r-XbT#XlA&zN}?YVCZ+(f_VO-$lAWa*1$Mnk=d&wTU}J1L=QUk{Md#9ac)Sfp z9ZctdRW|6fCY|dW+2H4tbauG49Jejfx!T(0IMgbg-CHilsLJWwCFx)M{P>iU*8hw1 zDNlJr>wjSx{*=2VFGIG+Q~qkZ44bz;SPUl zl@(8XxD?O7KjFzcmqPR83D4`c6i046;Z0AM;N7Vwe0|cz>y`HdZ-^KW8_=G>dUIe4k$2|7XBJ_Uwn4`=WVNmpA?w`F7BhNhMn{Ep+ zeE(y%#6oCo9&`4W1?V>ZF*_YwfO>r&vv$}5d~5QUOTW)Y{EtV>r{=>o^AWpR&d1ca zN4%F8oSMyiom>7&Z{;RlOCq> zjH^>nbS0JVEt&%7W2rpOa0*&)P30FclW}2ADz9BV8Qlk_a-&w05zsc3<5MP~X_Zvo zv27A|f4I*>yG_FTr2E|X`9vW2J{Rnt2v_I({L*Y9UaY>)so4|Ia+3b>=mbpbr~mrU z324dBckjcH#t2XPhQ;P;SyY3#_RTz&-zW4Zc*f`YLeUF>Z8;AOf?(wF& z<6toS9=}!p!S7D@c>2nJ@TtZ^ zVSg%_oo0y48gt|No@9IFvguoVq5RQsJ|_VW5*80-PuXp{Ldh4 zSCV)~*dTN^PU778gK+ovZMHESge94`xhQ@h%K0`sZX5`E-`m{1^FY+FyUj12LH|13 z=A%x)k3qM2wgOnUz0D@Mgp`W6xt<@PTUH|foJg>XOXQ-;g!`uxx%{ev#(NXlV3~p` zixRnuk%EIm6M1rq7E$dJ*=eU1?;TCW8(4gnpTl{{c1_SJG z@ys6#5uZf^qLJ3Igb7A5eNAp=l6B!L5q%@Eu!fiDD_VOFICzBbzo6|&+vt*#mTV&l0q zwm;1M!u8Uw_#T4+qAx;o*K5+d7^%59tT~6URBlebF^Dj#pgh zi$iK0m(S^oPbcH}Nd3N0w#TtWLLWHJj^l5e`ry7MjzhcmK`o;=-uk*XhLp$hlq0>d z=2TSx>FGUSeLI?64)s9ObJ09$a1X@TM|1m$kZzJ)SJKf-$!Tf7yH?+_(x9ryqZYP*Wf9{IEo0;u>x?<^c=H$s;ajQRbo0?r= z+=zKMcfqOxmA|j=g2*(LS9a}!@{1~$WOhbBXO*3gc80Z$%DpW+z!5h zzuE~;tLnesrW11B>3C$@PWTzCfP19gu6G<8fgf z@Vu#xH!bM^U2zm&Y|#N;kD|EXL3^wWkK$nm+CzIdiqD`uDz1#;`o--KYZ=8(!R@f6 zOB5R}Y=^GZqWFBXc6jveCXY^StKWxja{0ctsPB7|BbBx|yZt8bDQtt@vu^UNpf-pc zaFYiuXoLQZZ*sq8Z4gp$gZrnphH=^r9_G**`$BK<0&0zqPB-{qQ7a5tc7x-BTft-a z4X&}M72dYH!Ly87p>u^B9QD8$OERu=S4U%*73*u< zXmc~Ye{qcum^QNj8X^QL5ud>;!rkH%~D!(;sijVGB**m!jHm<(P z3+qsMHPrAZxV;iBL$rXNDwGp<}y24$f8$$Onf}J)uL`i%Em-lXnu6_}0`_&Lrw?}Zr z07Gn@5y2;{4B^!;f`>FSL|FX@E`87dF*%nx>RY#PdCEj6D2T}Vjai1@> zF=4?aEF40H(N$ZE9^ zupo?I#~PqAg>mB@2AJI}jAxk}AhhrzhZfdE>HUjbFRUiCK^J+~@|xJZ?;`*1SQ8iL zUu37ZHIS*j$Q@7BK=q~S8_Ly3RmW

W6UM(^X*kHJIJ4s-Q+5D_+gb$%R7jZD^`Nb#vsn(iZGZE#5J~8 zgk85FRxBzauSyW_Dye|!uP^X}hzhuI;{x|tTLF!aUSR)T74Yw>3q0`IU%Ec(0?(ZM zmnyWsz;5^d(BR*J{BiUj+MXWBvu^#SOW}e1b*?BHE zDx;zG&-24$rPS@qIlj}VlnfHiai&`dy*qV|>(?ux$W7;X!J%TZpLmYbY8I1a_j5dV ze-Rl}J;&9n7EwZG0H^IKq)pcYII=<^b#M=0-Od6^wh7?Zzw*gucmTKEmQPh$2e4iF zck(Jb%YQa~r;ZQL@`;i>3JE^TQ#R&Nk9}vkM^P@FvpUP|*XNRv`B^qE_(uC1oMoG} z-zfLX8CJjN(D;Ni+;dG1T{v}yqw>DeZ`(7xZ1qyqDQeJZZoKv*r8hs#kMloJPJus% zulqnhll}GAaW+*6@aLor*;H+(KUXSwPnDVeP-_r6Gew@4eEoq1QajPnCsah*PUg7YDl1qH~S&cX3nCi=m z55A_sfxcX~?rSQv(|_GHlYD3Ta!kWa8s5j3Z+m7?wt+8yYo0+n-}!K#Q?JNS=fj?D zUXkxnA8vm3C3RZq!%>}I()r;&ygm2@wQJ?Wb4*^)v653fJK{N2OFhL~20W+L=TC8D z)H8ap>l8N}^o)AVIK_t((#hWR6n7h)PETr_;`jHSQtP)TS)KHh7Tq|>SJR)+X}6Pn zZ_X2X@$X5lob{M$4>`%RtRIuP(Me9tc|`LHym|4uN3`p%H#aMLNXJim^Vb~@DRiqh zXI6elQIov+yW<0j@8+%dV;)dqC2wBmnMQFhPVl>yX>|Sa30{9Dl>(hkaJz1)bY$TP z&cAe@Hfc`q>jC#^s^JO##`mb#m*Z?S;vQ9qJI>bkQt00CMDKrb%cdxv6ndGX-dcWCZ(FAhGMM8&+#s-sbk!{0c zyzW&3Wq$GGA4?KwaGWQf&Wk7CX*J9|vb`M@SIEEr8dvLduXnNDlgAJ!gQZhUgj6*}L^jYH~RA^Ppg89oto?~yC_>KQ@PgIw7+>N35ubJfpZmudENSAPF2 zoSyV_5R>n{#-%)U$1HvBM`G`d9g`w#Qjvtg7q_b|ux4I^#8!#peg zBDokGX2Z!B>E#<2{+bm^?IT?{dtE3kadzPfl|$+DA{W*k385DjE_|$g2-U9d!i}y3 zllcc{zC0|L=INYy?UNwd?e5GImIl$OWzIaY^a4e|nb#e-K(`t>^VQ}TDDBH3ZWbI! z=`n}+l%jw1Jj6rppQlGF4snh7=jqOnL;OAe9Nlboh|Bh#qk!Cl+^)$vI+$>fR|E!- z&548jOcOvO)*R#|_s&ww5eK>9{IitP;vi=goT12kCw{o^4DGn>#P6D&Av)#6O+rpn z**Yiwci?FX9p%KC5BQ6O`9J$92Ke~9wk*m7+(Kug6{@d1%K5uYjqiepj z%hHjjTl!M{HjaEX(}%o^4{*QrKGY`p06(ejL;ijT_}Ix))YA35F4@ny-@WNc@_wG~;7w-!`#GzHH@VyHXP593^l8j~o-^_UY1;1RF&W3n zp~QjbtUpfok{$SP&Er(p-+|xxdeInL2cBW(MSI3La9+wWy4uEp0~Z~mtm1vV_lGAL zB=6&0Zl2V`Zy%rP;z^bp_wlP}4_ausk7>FGZEU@dV{(s@eUUvcaX3oOckH=)tE1%R zW6uq*9ihYP?b&$T5po=5&!a!M(@tZ1KDN`HRu=5#YE9i~`t7}ZEX&6O~M|&J^V2BIlhO7zjmRbm3#QZW)}({ zvWEi=UFhGYd)PU|nOf%T<|8AV>2Az!*1b7I>pgaJ^=*f!>GIvYzVRWtirrl4(m@*E za5qO-9;Ejl?bspPi8ko$c$=LQ{dKit_ZCjHZ;2hJTyvyq8awVh$&vQdwc~(q2dMDY zE*|c9fS#?|#nn3=pvz5naZb#B+8eWz3+L=7%YS!ri*g65Zn%@JJsc?N<_><`+kuuW z+QEzO@1rWUcW@J%edK**JAbLZk2=rY&Tr4!Q&83I{9~{^wY#{D&0g;%_i5Ys==Qx- z`e!RQGTKX%&u`_($UPJ=ek*UEx`%R0xA5Y^-PF@>3$Jq9O$$eDVQ-V&=kyDG-xyD8Q4+!r%gO|@-BMix{3d~?xbhto4Dlu4oZGw%YEzYpojyue09ur zI$~)6Bw^eMHXG2?#uHwP{Y-qQ36_4Jsob0kzvM2vbwvH>gTa|xlk?BgVY`Kg^rmx_3 zuGZ9c=L+8cbSV{fSiyabmr_)+4R=_)gto4;;W@#J$+Wo*zbIHl8PUtxN3)1_FI~=o zdlpj5I?K82?gF|P@h=~4xPS)C`j>6y%%{i-`sV@jsMq;rT$XD^C;wT-f#z0JvB;Wz z_ROWZC#?Bp${Y$GWX)Dh=g`j&OS#L!*`zoxW%JNkw6X6}b}5@lXP+Bpi)+F%VzV%^5N9m zXEy6ABWUi>**w&L7}g6434oJNH+Cna36o@=gR5)wUnsgtm&LHj_AdoY25FeLdVZc zZm`-^z?eHJHo~HutB{tCM*1qkdF#)+Aoqs~=hYnaC#{`%=*9 ziQFQ)kN$O@$ZrSrp>AI%@b{Cw$?EU~9#L*ePJJhE_Eb~4m_D9UE}PKZZR7c8Jrl}o zJ)YOC>_uPV$8qoEo|J1njxDS z=xSq2K6Ab!O};UjXVmOSpXZF`X*L~bQ-#rd>Rx;LeP$H*Fl|rUM~>nuN7_;0myz6| zq%AFU8OhEw+tS_MBYB|OhPpl(!J4*hXwT*mymMb`de~wF8+>U+Eux3>>v64U&cfmR zJHnVes}ASI&5bE3a2Pk*)shOv4CC6_EvRwcP#!m?1@(3x%Fn`$XjuQD9Ma5)CO#X& zcXlRSQ`mV$&l%PuGfRbozt^Q}Ia(etw=S6+)^eS@b;z%`mU|4S zL$w}j*yC(%T4k%@k%qPDZZi!JwW~#~qAd78t^uu>Yr#$D8qnpx=KMXmCguB^v!S*o zbsJ{RJA-P_><KxaHt*2C=yhVLD%k{5vscIi~-10}UIp3QT7XDURjqc4y#{N>0znF5V z*-vHdAydw4`$MVU%apg(DOUnhP1w7~H)T_F zcOE%BM~R-_ovqBjDiterXM-MJ6z!RAJf_WOW%aOb+_v#2moYv(THctz$qP= z!_$?j#qD|LrKid*kM{g1?1{3=tUYtsW2J9;J05uHk@99!JDwW;P}$$C9aoBYpme#> zmWN$UQ{rZ}<(Ah|mFYj)uv651CHq7hc8R{HtkkyQE(s}0?#tFZ{Z6v7e0ys)PQ9zV zZrPf*Jh`KcS6i{ot0d+6+*Vxl?zYn6k1-qOBr2PIjQMuaEhQED=YJBEHm_T9Vf6%M z`L33FeLr3aYu%E!7{@8O(Ji=D*I1?V{1!a3e~dD-LJRITBwBIsGh+Agtb`6SVz;@f za{oF|Y1>S#h4HK%Fls~_?YuWCHi$k_6`VDcI;}%W*nmQZ{3iWr3Wh?*^v9>2PsFb z4Eac{AVvApfDd)Lpk$nCpyy};l`YhOhgzLi>SxsFirda9{@d&GbguxVN6Y#={MuRN za#TIO`}mB~XLddQSa@0q{ZW@sHaxAgJ5iTE_4QZWE$VX06hGzHvpPJ|)>m1uxem|r z@=;=%*5PVVrxc^e+B`b*q_S#SZEj!bq@otrV$V+AN_CG~>_6s&GNxZG9=i6p;`GRX zcOLUn;@27QL_VgJHZb6*Y)_?AcunRyp2~y?HF>6)hq58B1|OPtR5{{OgJ(D%Q9^sx z;HU_9B{roxM`pSyX*Sh)jDef-!k{{DGILd4U#P~)qQlDTQPudktBdmdV^u!P&dPm< zs%-r2kP_XoDi3XWNC`@)!j;AzR1Pny!n3wJDQhZKVarfQWvqW?ew2AYX*Z}c7u7$Y z6lGT8i$nJ-F*_=8#Z3;%ftHmxCupBy8C8+jytY?r%&N%FjqH_}vI;!Za<8)CSOs>s z+oQBItH4_$cPm~O{;EH6?Uc74{-_N*+bL~2{80}@?^LEO_^r0wpmG@`a@k`W0R8RUanTzy-`U?EmM;<%wK6NdSbg|yrP8TFvFg5Zh4M)$QXO)aEB;#w)sQv+Dig02s8x%smC}NI z)ot@q<)}%%I^oY^rOS%%>X3bll*@s6s&$=(O5f~UHQIB&65KXdwQM_2F|zum)(oAi z>^hO7{;-&%yn6aoZJjhrF=_Z!-8_A!vSs`iwaTaI%FTnH)%Y#bl)~Ge)N8e;D($L# zQZxJ}E29Q|R0o(%QkHK2px#QEplrRKt?pkuUU4XTuWtYSkK$ZdolMOY|In$6oNFnz{dDS_r3Omsswnl)pqfhC3pdrm z7B!R=?{28BW!02R#y8Z(Ppc|9)32+mu2xanxksvD9+i~|Dc97_n<^=rt6fu{&a9|- z4Z5o8sDg5N>lO9V@ITswD-r5+!(ZCe+{>!X+j8yWE|=BZ%ca_f3&Yjd4#nC#Coid( zTd2M9G)%2!majcsKTI9jAWyr`@}iobo1U0cvXFr`k4u&#IyIA8SL+&#FJ_Jk<7IcSgNdCrx`T__X@2-hHiUw!gZoQHnO8 zmA~rL;;y#g3_rD6$0Y4GH(#~DG*O#z*GK(lV1m}XijUfSLY&rxPN`ED#b`5aPpTES zu(tChZ`IgMr?vTfLJbPOsSRv*LOq{!UHfMCakcTMYuW}LUTR^@t6I8$OdZlILc6H? zF}2dvaP8hfo@(EnVOpOp9_r%@q1wxrkE$QigY_8a5p{WuAnn}_M^r0qp!WV;cQs+n zIcfJi+0sz2etUxA#IDV`&8S82eonS_o>U*Ick^8u~*X`?blZF*sER`;Gp%s zw?{2HWv}g3ZI61n+Fq>=yVb0nbVqgQHwR9<#_V^>*eZOvDyv+ZYV>s(l&PV}9jJ<;4o?G-&$+uG@0wcy<(?TH`O z>Zv*tw6$%PswVoo%l74B^}=dP?b9)fRD-~g+FrT^>g4QU+8sUStM;9TXcJCasV7$r z)K;o9S3Px8(GJ)#TisVnqh0)MraEoG0IlQP8ERc!KW)IhX=+%DKH3{JRkg4)(cTK3 ztOkGXp-nQLq*j~JO`G66K^>jkSsVF#oN7C?qxQ_of7F99?X(UVV^qf>ZL|yju~gUI zG1i)?qtwAuTWBlw9I5`yZl+By1#npIEh zJbR!zwsIY9k7QEq!VR?X8b$S4Ttho0NTZ%>SxuYK+(PwwURgWOae%tPyQ20*S$}n7 z!XM4JW&PCj**`Q<>3!6?zl$|(NA^~Y0`oO?*G$x(bG~VwckHEJZt+>u-J^#(@cny@ zZI$k-|Ft)oo9nx(&)r{X%Cb7EA2&bKm`>`XrYw7`SrFSn-M=tRbI7#4+H7fx=8|t) z)oy)~Cbe!GHO47H^KnNj^=WX7raY&m8vj(MsXC{HdZ5+~jX`pAwS(nVje(|_>g67; zsd}M_`u=^Wro3rmwff*7%}0lZYUT6iG-<^R)Td3(Xs#@-ukLmA)wn&Xt5$DxQnP$W z9d)t4mqrP%rJgYN&=|BaP%k`p(>!#kp}N_-Xpa7_rcSarsF}2)s+v=}Ut{pHvN|uu zUc;j+sUhyWH7l-HP|sy-*K{BEM|b{$t!6{_pSn4YYcvrx%5(|amuo&}7wO*aU94#w zpRc>@W2G_o%hj3Ro1vMwK=UPtO*;Os$2V_oo0Qj6kXC= zV~y$0BwhNiW}5fuw{$1FH`2IWiPJS-RZla(Em}7&!9eq5rB0{6sWdArZ|L3xSJeFK zbWOK)>ko^4l_PWk3HcV)--PJ~n|-#}qYKfEOMPQe;&nlH@9;B=#T(D*qBo^kBu_k} zYrj9qqGvBZUAY=#alqh|ZfMIJ78xIo>nfZMx9Ab?sp~yH$YP`K5#5vaXDqI7bJgXx zK50=h-C4J7sE36~KPTM|7Z;0#_4n(FDjcwI&DpDab7Hr}jU+pr{dHT5o1?es`Zz7O zD66BSvX6rT$>0@#3#8lmtZ=Ef| zCXLs<{%CA*$zZgu+_aI!g}5QQN_Pw_y!E5f&#;OX4t>mYNy+)<|9&yiZGG~_e8lOl zx;i`3%v;WCuiG0JW1iE%Sob0z-2B>|Cc4I*&zNuBU0>I4gonAgg@Mkj@&WUL@0E30 zovrzpi9e$rg<6>h#pFf}csbJiuSr&v^{_tXV||}QE&gn5?ppUwl*wHK^OPOBDA#-W z11fzBi(0TVZGh>VGf@xDg%6mK>=~6c!ehWTjZ;)t)pmgCQL5sCwta&0>?AL@icr%`Qy-c{B5~u~}lhJ2zXM5AXjn+4JW6&&K_q z)Ej;C!)N1u&+FZ}@&7#li@T);%5w|(bB%nzM*hA={ymNS`&#+`wDSLJ<>%4L&!?52 zS1UiiR(>C?{C-;beYNuYYvuLO%Il+**Gns}pH^N^MP6S;UT;NSe?{I8McyAp-Y-So zKSkb8Mc!XU-fu^^#=$Bw0^M)>o4CmSp`US&vE9XOi`rWc?;t&q>yIlJ%Zs{U_NENcIPk z{eoowAlXky_7{@$$-GK3zmm+e zB=arFyh}3wlFY*-^D)W1Ofo-{%+nuf&W9xDMUwL) z$$66Gd`WWNBsqVQoJUE{rzGc9lJhIcd6wjSOLE>NIscNJhe^)IBMeTPKvA<=(G^dJ&_h(s?U(T_;klh@J`2Hz9f_ME`{7p%8r(qL)JS zQ;41l(N`gQD@1>V=&=xe7NXZe^jnCY3(ao($2KA$l`J ze}?GM5Pce=S3~q`h@K76w;_5rME{29;ShZsqL)MTbBLY}(bpk*J4Ann=ye*oeaK>P!Up8)X}AbtbHe}MQA5Pt&VS3vv=h@S!RHz0lo z#Q%W!ArOBA;+H`D6NsOp?_BxMUxD~75dQ_@$3XlUh+hNoZyvg7{q!{|n-WLHsd@Uk35dAbuLe zUxWB<5dRJ0$3gr#h+hZs?;w62#NUJXeGvZ-;s-+fL5N=n@ed(>BE(;W_>B<%5#mQe z{7Hyk3Gpu>ekR1L;QS*zYp>IA^tyv2Y~Pa5MBVn z4?uVV2wwo<4Iumhgh$YK5B$d`KzIcRzX0JGAbbOacYyE@5FP@;N9eOh|M3zKegeW% zK==v>Zvo*iAUpL6Zv)|PAUqC)&w=nd5Pk>3 z^Fa6>2=4>oe;_;%gb#x7LJ)ok!V^LGA_#8;;g29Z5`<5J@JbMV3Bof$_$CPN1mT|` zJe2vtCJQjq{g78`pehb2LLHI5R?*-w%AUqg^4}@(9&x7!K5PlEB^FjDN2=52s{~$adgb#%9f)IWX!V^OHLI`gN;SV7^ zB7{$b@QM(A5yCS<_(llt2;mRJ9}3|`A^a$WCx!5(5Z)BRpF((42%ie!RU!N;glC2Dtq|T7 z!oNazSO^~r;bkHGEQF_p@U;-$7Q){`cw7jd3*mJk{4Rv&h48%)-WS6ELU>>Z9}MAz zA^b3eCx-CF5Z)NVA47O#2%ik$l_C5xglC5E%@E!h!aqZJXb2w-;iVz`G=!&y@YN9B z8p2;gcx(ut4dJyR{5FK=hVb1G-W$SyLwIlq9}eNgA^bRmCx`Im5Z)ZZpF?U*4czg(-58?G8{62)|hw%Ln z-XFsML-GKSd;lab0Lc$P@&u540VHn#$sa)S2>Nc`|MCftyaFV@0Le2z@(qx@10??d z$wNT$5sbf1>Z|`Y(?H$)`Z_Dv{0t;d z1IgDw@-~qC4J3~P$>%`wI*|MhB+moM_dxPKko*rM4+O~vLGnV7{17Bh1j!dc@Y=i6(o-Z$!9_G zT9Et}B+muOcR})Ako*@U4+hDHLGogd{1_xp2FaH}@@A0y86=Me$)`c`YLNUIB+mxP zw?Xo5ko+4Y4+qJ|LGp5t{2U}t2g%n#@^+B?9VCwj$>-^_r~l>kAo)E=o)41mgXH}n z`9DY=5Rwms#JZ%7^-k`IUE#Uc4|NS+*$FNfsKA^CGi9vzZThvd~E`E^L19g=T{&uZQIAA^CfKH^YB=ACmuv z^Z`Kn0U&(=kp2Kjp8%v^0Ma)A=^udf5kUG0Abkap{sKs!0i@pm(suyqKY;WhK>86N zeF>2M1W2C(q+bEjw*cv1fb=my`WYa74Uql@NS_0w-vQG10O@~#^g%%SAs~Gbkp2ir zp9G{|0@61D>7Rh~Q9$}BAbk~({t8H+1*G2s(su#rzku{%K>9HteHoDc3`n1bzU%zI zeho<92Bd!j(#N6iru?s;1Jc(4>F?0bU;p)aK>9r(eIJni4@e(~KAHDlKM15R1kxV@ z=@WtUi$MBDApIkdJ`zYj38b$C(q97UGlBG*K>AJ~{U?w<6i7b`q%Q^1p91Mqf%L0D z`c@$QE08`GNIwgtuLaWI0_k&s^t(X%ULgH1kUkhlKMbTV1{VM8kAd{bK>B4MeKU~$ z8Au-uq@M=TR|DyF5qc+NkRIhAbnH#KbG!0E~ozw7NWTiwvx4-kAiXO{{|eH>g7mQ~5y)Z~W4AK*W^u-{(F-U(5(j$ZP$soNlNWToy zGlTTaAiXn4{|wSYgY?lLy);Na4boGC^wl7}HAsIA(qn`4*&w|(NWTrzbA#Le`)-il z8>IgR>A^wzaFAXcq#pES{8 zc#vKmq@M@r=|TE>klr4ozX$2@LHc}bCefRJ7wq#p?B z2}1gUklrAqKM3g&Li&V|ULmAk2%_)q@M`sDMI>+klrGs zzX<6uLi&u5UL&O623h9qRdZds(DWq2l>6b!!rjWiV zq<4xQ|L>nddZ>^-Dx{YR>8C<^s*t`aq_+y`uR?mPkUlG<*9z&kLVB){zAL2n3hBQ> zda#f_ETk6;>BmBPvXH(kq&Exc&q8{%kUlM>R}1OaLVC84zAdD83+dlNdbp52E~J+W z>E}Xvx{$uE+FbqD+lBOZAw6D5pBK{Wh4gzNJzq%Q7t;HM^nW2eU`QVr(hG+4gCRX( zr2W4y4CxI+`ooYOF{Don=@moz#gLvcq;CxA9YgxZkRCFmj|}N0L;A^(o-(Ab4CyUH z`pb|WGo;T9=`}<8&5)imr0)!mbN_nJkp45I2My^%LweDWel(;f4e3imdee~pG^9rj z=~F{`)sTKQq-Tx!|L0?8B*^quVq^Aw(YeRb5kp4EL#|`OoLweni zemA7&t$tqmukQ`%eM9=+kRCXs4-V;tL;B&6o;aj04(W|U`s0uuIiybx>6JtJ<&d5^ zq;C%CokRNPkRCduj}GajL;C5Eo;swj4(Y9<`2YQNNRJ)TXICHRf4z1{za7$ZhxFYc zy?6CGnt%OwNDm&;hlljyRU6}9KOWMPS6gWR`tp$8JbL}VKM(2AL;CcPUOl8=59!%M z`u33CJ*0mR>ET2A_>f*cq@NGz=|lSZklsF|zYpp0L;C!XUO%MY59#?s`u>pKKcxQ; z@c0K^}Fcmxoi0OA!u`~rw)0PzhV-T}lvfOrTH9|7Ve zK>P%VrvUL4Al?GRUx0WF5T60!H9-6Zi01(D9U$HV#D9Qz5Ne3vpAP}?A|QSQ#FK#d z5)f|!;!i+43W!eu@hTvG1;n#}_!bcF0^(mlJPe4B0r4^*eg?$TfcP2^Zv*0QKs*kJ z&jIl|AbtnL^MLps5bp!xe?UAChz|nsLLhz!#1nz|A`ou`;*UT)5{OR%@k$_m3B)sj z_$CnV1md4SJQRqJ0`XEHehS1>f%qyAZw2D7Ks*+R&jRsUAbtzPbAk9S5bp)zzd$?~ zhz|qtVjzAD#FK&eG7xVD;?F=l8i-E=@oFG`jr#Nb&$EH}HW2Sdwa$+J=ifj)9Egtt z@p2%34#d-e_&N}82jcHQJRXS81Mzwweh4#K(eoSr9)9;%PyAEr_=T@wXrz7sTg+cwG>`3*vb}d@qRi z1@XTi9vH+2gLq*OKMdlDL3}ZYHwN*?ARZaSCxdup5WfuKnL&IrME~DAgZO6<4-Mj@ zLA*4Gp9b;NAif&JTZ8y(5RXm$`{$p}2JzY;ejCJdgZOR`?+xO=K|DB!4+rt$AbuRg zlY{tj5N{6R&p|voh))Oc>L7j{#Iu9=b`b9l;@?3$JTw{q&&Pv!c@RGj;^{$rJ&3ob zUT65v--CF35T6g?^+EhTi023K{UF{S#Q%eMfDj)L;srwdK!_&@@dY8?AjBVpc!Ut2 z5aJa={6dIl2=NUe-XX+4gm{SR^`8HHM2MFN@e>i*@Smp$@f9K7BE(;Wc#IIA5#lvM z{6>i92=N^u-Xp|+gm{n;9}?n4Li|XGCkgQ-A>Jg!pM-dn5T6p_RYLqqh-V4$Eg{|| z#J_}im=GTm;$=eoOo*om@iigdCdA)_c$^TQ6XJD3{7#7H3GqE4-Y3NWRL|@D^FSd! zD8vhe_@NL_6yl3Qyitfh3h_uGJ}Ja2h4`fq&lKXDLcCLme+uzXAwDX^ONIEU5Kk52 zt3te0h`$Q)SRpLT)z|eu{~F?9LwszAmksf= zA)YqG*M@l8IQM^l8{%<8d~S%>4e`4no;SqzhIro){~O|gLwsUdB`i`nYj;wP-!I z0zd!N!X~r=|Nc>re{lsCw*J5C09j!*zHhO^YNS9TvRMB7LR~ zyFXWtf0GXVo@!D5v<}xk)}s3Z9iDrr#mKKZeE2|%pz@WNu0BUg8dTzkyILHuti;#1 zwYX(pi7ClieDtcs<2TgjZ(1cTy{1K@b(J{biWWVNRib&K`aImJ#LSCY1ZGs?mhzUVQ`O1?GbRHc6lEqbr5O53Jd3_4nsjT)-Y%k8TCSVs%j4^_FtNd0*&u1aSE z^>MAO&x%#Gh_%q?&PwWQcc4Cdmsg*EH+|kNDZ`pbeGVxo!}xNK03t6!_X8(LT6ljmi)WnGPWkIRrUrW(84FGFf@ zH9Flc!{de3=zqNo&vsU0Okx>cT&l)t=gW}xtQwfGzr!A+E%L1C=uM`uQ4k?Ouk-?Q77#Q<-|*cnt=( zErWx*I^D7i{i4*{o0g&LiW(ePzYMJp)SzjtGSs_XgZb6Up!cQ*uU0NYVQvk^mn%c2 zfgyVomEuKfLw@>GiksGkocE&?C&n1kT`3kXG-S85Qbg`FmHCHuvo*!LhToxnOGvG!JXjV{HlSzSU-@r6n+~ zXw2L>C3x4+m`61w*w@9F6T(XnJj9q)0!q+pk}-FCm7x4IWA++fg5FDYqC8lIn0!RxuX5tV73)V)W0cL#MQ2lvSv@49T3SPWCAx-2K(=Cx3w-EHxwi9OkL_OFUH=~ zx;#F&7-KTk`I=(rRj9{rp~X1YpdKTAi{Wiqk0ld|QQN*A!<~z9Wnw*k8CnegxOyBq zpcr-6)Z+mwb^hUcEbCMZpX7S9X;X}v@9J@0lVY4LsK?8-i{Vz; zJ$>u5O@0yV#@1)|A4SLtsZS-N2#XihXRntffP_ zxFM<#iyt)N(11edeQm@-k3!5U*O(hd7ox0QV|KPLL`0{?OtLOSwrykf?^=jS9*vo3 zR)|;8joGnDAskjV<~pN7TszR1d6f&%^?GC46&GOl>&9H2U4S~djrlC20JEz%p}~s+ z{At;QRw)H=Lle3u72wXOCX6{*fG&YexM*(yHqULsm75AsDWM6MFDroW*(RJbs{jvE zn=mM{09`YiaD-n0)|GEcbN2%E_eN6|I2ORAb5mX%RDg4KO&MWTfO?)yY1W|tVKGhl zuz3MeS2kr}odUEy*pxa|3oz??Q!Xvd$LrTkY4|%Imbpzi?_)mZS8vAr=lOWkvKhzS z%|}Nxxy`t2T|TC6ZN?i5^Kt1+Gyc}(Loc-%YX#@S z@oO`-^~%SlawhEMoR5$7OlUngALgA**cHzsz-4thH5d1uskdLvMb=Ms`IEWO*EMC#?p(BKYD$N7x#-{Bl#LeT!gZJ_(_?ZG z;cd#b{<&B>&6I=Oa6?=uLW4%_io%C1z`@0o~js6STwBlf!zv$)Ois<@BhK8 zrmZ<6@egiwZ_TDh|KQ}X);yW;2V1;blgs~L?zGmtGUE>d*0yHP;6E67q&4??{6UZ8 z)--VZg9dL~)3@Ir^}3MOylkm%&!7!;P50n0G;)Um*v! zkIlF!=Qs4eo3X)%-|G7$b8db38?zdiv*DHBuTBFMRvcmTdxmVU~V7z90V!jaszha{FI6(W@Q1Tm6E~h<1Ep_6x73w4-;u zU+|mJjyaWop=4by$ zWSMnfPRS40^y$FK-+o|+a|b?s{sYB<9oX~64~&@Gfh&*yz@9A~_;IT`|5OKBEdBxe zdmZQ({R5jmcHlPeAIL23!22VAplhv;%<1z3)66@vT8AG<(Kr&~HwH#G~jPj}?Ei&+?cuOn~l%fh0M9l2&r7H$-Gr0dKqlp1wn zlc`zgY~G1a#$~~)PbW^d&B9vePBiV7h2+3aOl+Qo+&P`-P$LV?wshjl;_t9K)rrnu zzau!M6YoFyj`bOxsD@*4si+eZ4t>Ylnw?p^{yVg7I@5m6cQmo?%+g~yvEZ;<3KHZXg^wjlpE!i(O6B*UI@cFw;ylByd9x0i)+p7ydp2@_;;axa>M<(`9 z?!uHMnOHlm3oWBF5x=GjmwRQx_fQvpcF4qt>s{EncP6^O>cY_0nP`yHg@=tYQB-4Kqd_kIsCy7A4k zFKF-9jdQPj!Ot*t{=qLeu&5iatoZ`(9o;y5#uqd@-;FPPzurMyu=RB>#yDmmJEs?2dS^hrcMmkU-*@cDq153ShB@dNIBvEojv573rc zv4QCabgJE(bE)VXYmf* zKPp^ftWFmx>|gp8oejavk8jbgmC9|VyhV%NVEvPCQEvpeYvWt!PX=4he2d~ZaGTFt zWUd5_M!dz-edAff&FP+JSA?Y|0K<;))NBk`ET%U9}ZXmCztoh#U4SKm+bIZUt$O*Bgqs1HS zoo`KTtv49E)tWnsUPJ$sHSzv6&fT%*!{pcSdS}hChhM`W&zf&my~Zj1J{%SE8e>fQ zFnPjj6m{#v4mPjV^I(0rr2T7j^XS9RwO=DOq7SJTK8$|<3MJe7@NDucEIr$Y zKMuV@lly(xVAU%e%;-Zzze4xIK6G(^g+znC3>f$d15Eoes@*Hx>e-huMz3HqtS`d~ z(r|NPUwWsfp>K3wI$Te~g{6JjX@43z?dnUtWog)TzAs;frJ+u0UnY!A!|YFe>DDI= zzl-{^PU|$d8201!YH7IAvLAhNUZRy%KkB}CiMbB_xarbMeD>-`vmGzdFQy+4&3lQ> z%hc(Bm-xF&z1{I8Y%lakRzC`!peyo%E0`Z3Z>3;tOZnx~u zZ6{v9z^Xsf*1dp(Lx1XPUSOG5e_DFJz`f}HbhLSaD$DxQ$KnO7clBqK(F=r~@2`H| z{2Y58^yjqK&++_Ye}-Lo4xOU@^xXX%9cm1q&BEsxZ90Ihranh(&jBnR`5aq^4q$Rm z6}a&nz(q}-<8`FET*c?eTddyxAI33hUbgxzp|`I;IcgllD*1=+8hF8$CtkDudV{{|SCH z8pKYop5S4pL9|YMqF$#lh=X=K!HThiIAHD*1WX-7E8iy=GgDYp5W@WLA+M<7|UJ^;c>)0@P{$m_&Yr|0g#|W^t zVZGsx(ay<+r@B1G=P5R{t@jvPG&X!%{7C&imJP?eeT2$;)#ttz!w`o@aIRs?o0gAI*us`I>psG|9=04=^blQ!*mCKchqyPvmRFM= z!ZX~KKXyDs{sLPXs@E9I-D*p7pNB9$X-j3uLnPd?<)Dra(dLaU?P@*5q2IRbpO=b` zmF?L5Wh#y|u%pSvRJ7}0$BJ81vAdrg-^@rwV`n=anV5>@es+u+l!^*7>}X}4im9vZ zm{%*`2f|w*m3dN2k=_l)c1biuOEFa1YUS?fEqA9*(rN=dX+R@Q(JZu=O4c zM%uIbjC<%c*`9`;_uvt0&#D9NVcs%(mbSWw{X6aXwaPu*Icv|m-%{`;#h$xUQc&)_ zJ);h%pl+@`2P{iLTfHHy5}X37#%c-FF$K1rhA^^g3PuhX!WMN?FmB8cCKuer1pguQ zOuGxu8ADib;VwK@58>mzcQJ=fury=xiaTgs5hcHFw zE*e!IO7qWmP}yWCrzPLPk1j)bZ|@yEv>D1;3+~|fxS<^Gdk4#=4&_|?JMft`l&3B3 zpzpe&d~I+Cbq@|@arSLwCJv?1!`nFXcqp46zm1t+hSF^1ZP*v9W9V(vtTBuxPPg%- z`7qY(b{i|Z4P#NA+imyO@kO0qnhdYvVf0E*M#UNqEWDhIEzKP`YilyPc5`5r z>B+cb>!3ak$rwA{fkoEI$eijxZsN~_u`@OEhILwjy z4X(muo+JAfUP0T9j-2}93OXHjXCj$~SD60!%35G?980^I58!qGUY$s|XFT-t}6DN(n zjOquRc%$oOoW114#iG_zRp>LH@?6UY0-ZU6RZ{JG@ zwHU>fwwIu5J&I>rU&6W(qxh`SCA9P!#jK2rI2w;0Nm~atiH>soMBDxsPV*^bw->;%g@g2*x@XC7C5tCwX^E=jAQ7Kc?M36#?a~J8Mw9|L&qIw zFwuGp?WUi>q!DA(^Acy^HE|4E^g09g@G;b>dj`()#_;W*)3Dz#h9^=_LpeBx(+-`6 z`Qe_&pGNWfG3xn?)9Q7OW9ZlHG%igRcY^dwPvoB8}*vy5Fr%%Dg z%7tH6oI?E}E({Aig|DtIEFOFc$EUh5rp+lt$Gh;4&M7FXTLCeQ6_Wn`a-9C;@_aBAH z$#J|e`zS(hjHAPZqqz2L9MgLrg~8Wx^s09hqYB6I^PeNwSam$z9~{A}hU58o{}I%; z7*EbQf)Nhw`z=sBI zY&hxwPPBF7<&Fn1t+yM;>K}m35I5$0+7AO)H^wLJ$AbVj>TleS#narlBy2xymbtO2 z!+w+{xN*AqejGdI#%!JaaKGxt(Qo&m+G97KJGT!fGu&vrY9E~cx^YUtJ{0J<^Q_H2 ztTuLMxfc7-zLh)slZad*`*eh*S!xzl6Z9`wj^=csObu&u_+I&3F_wOS&dzf;>`@WF#YOSYpzjtAF!Z^!TQp1fea9dBxS@_GI3xM||atekDw-^r83cei0d zA5ZG++6M38o~*3druHyAS#k6>wI}4s!VcT;dAcVvt8BxGWuAQWJ^^tFo;-a%0ez2p za^=bd=p=d4$1ed_A9&JgKmuals@rLjpmv2kc{gt>K9zZL{)4SpWiXL__HG55Oyr;G z>U@id+&X3}<|z|7pz~I=9x{=is&2*AaTBS@*a8>7i8Q*n1wUfcBRsy!f=rX7q36#is8!VQ*J2dY;<^y#Zd_zI+oVjr3yLlubzT^kTKXn_wK` z#U2gR`SD(K%h`yN%e^@5&PJ3bcyayqjp%pOi-)2&s@HRS@xq9WxO(4<*UUGfCatiTBp8$E2`HTotrleSfGfXS*KLR!(9Kll7RreG;!1ti!xxlNge^ z4s((wslPYZVa9_=Oq#Y1k?E5-e)Kx{{+Ptv_UkaFWD@6AUWfkr-ZV;Ii?$8Cx$e|j z7?^pp-r}|R(cPOXC$7b37|96Waw;)hM9v+F7tx=yBR z*Hzf)H<@nLR-t*!WRA^PiCyz2)8YI|n68^l>*Xu4b@ybNPhJV*Q3idWd1Z> zsrGm#GdXJoCcK->4cAuS*3ZeDykP~*ODD5q&*uEU5j#KCxwH!VZrm&jBavTht!ac2)<6GPmDy7TRPSOVpd{$*IScM4xmU#9lrrf}@&WyrWbg-mhar?CoQ@<_3=5IcHp0o&l1?sqF5qebin*~J z4!+#=b0K;wzFc^HA#&_|>APVeb~*cU;M9fc&#^BX4P1z_5MO3BT!@`Be0k>g0t{U0 z%edqP__)cJ%H{=#+waSQ;0364)|ZED7GUQMU%EC~fKHEnsrPq2&cE~J;oI}UpS~Qr zbv}}ceVG|LU;UibkJIet<5V3#8aA5`GgCiq%$rq z!!dqbF?gQ(JwrcMG?|Bmp?(a^o2&LB{P^_lTy$OP$8Ou^s^=}#<-+IU{ysl`9XuDt zXZ+a9WG+Tu_v4(rIau}3kN57*!ToeU8f=>boh&~N4xfXrg?@}5JO>_?{dua{94xHm z&kwn?akQB~tKOZBR11H$OPGzUUjDQTn++Wse|p%>Mm;BghBck7c5D4P>+dXB2KsaH z?OCvj_2=>}vw->jTpBV9z1R42zRfIj-{DV9<5{pc>QDcinP_^+pQDp!s{LwzDw}2^ z|Cv7<2hGIm41X33n5p*M{CU5@Ol&Ci=hp0agj5Zn@AY^LsvE%0>*Lk${|E4|e>^fe z2Jl$lcpOjyIHhhp0_+0VC~F4Vj}G9Sq#5|?8NiU$Gq81P0PFh9z=*g2p27^2TM)ou zwPs-dngD+MGF|=rJ%FJXr{lN!fva}ebS$|Tz}a5Y(fW1(EBBg?3r_+B9I$T#-gHIAX|@*#YEpg?ynS!D-nTgemDm8X9aS_s2Bt+3uJy-G%jrl zq~o4w=gQFwGOkRCQssGb(cCBGuk?{grJu8TxiP9Set zM`C+fAfJDYz}>1-`FdFde$|=E7d;|Sv&B^2eHRXk4pVtzUbuQ4{8X;&7!Kz_Q#tuX z7`z>)vg`CP1iMXTLF+I?`A+4r2cd|Gn92zep@^C}mAXws5wdhDcis%akGJbNC*M%8`bkP*bgC#E3zXArx)OhM10 zAf72V1$!z5v;CgQFsvEOO+zLlyiqXA|MkYR*1;UV!5f_|gL%x_8w(K3;?I+iZX3+r zizmUtDVSlFlMvw^%$+a2aLG5Acc*zl8y?KemR{%`AI!456A`vJm{o%(s@Js#)1cl& zr0oc1mCK%}d?c7fo}REcAIuCrPdMBN=Jg{U2uKa)Mkf!H4j_c) z_g%5hHiX+lTrp#02#xByVv<`3qb`rfK%Wr4@EnikVIgd4uL!Dhv`&kIjJRgJW z??QMkb_@c(hw!+`7#Qb;aK}w&wZ|CBg}%-hsUJ#TLudRj4prY*j>e2;p{(UH8a3O7 zGOcVBHg^r>`W>TSY8}d9HlwiHE|jHNPU`h!=9 zj!DU(+`oM|4nGW4ALrr7c@;|Y?+)nnS-pL!1N?r4a)G4-wiku+@bh7KtP{pNF~d-< zMi|qZ4ue_!Fn+r>6hm5s@u&At_*tma`a?0dyL$VPA=uJKUEXmBjt&mvk$ihxath*t{`}r;P0| zXIB^<&)LG~NSJz^vMmOm3u8n%TeP|s#?l=&C`}1t>>wMYJ`3ZYZ-cPqT^K!<41)JJ zbw4@{QoEXAG|QH z_V!1O9^uRx+#g5!gwr^?9|jK&XQvhY@L^=QdYxK7gt>-u_=~=%I60h7F@3Q(D4dQ> z`obtCoHkebVCAfEcAwY>HI{_4iEbavSsTvMeby*U2JE>f-}s*B;1a>(+8*fR8NuJ%dSIAe1kL;RfOA*`$A0dP@tO$Enx~F)Be=)B zJDitA@LEbY3|k+e{(sXAeYQvNvtc)MI1s_C<6Tkjq&kl5ijs>F{FK)PuWv-~*}5(` zb3cMtdUe5)=MmiX+7j;XA{ei+ghgfqots%A?{@@SU+s+ZMG?&Q?2M?2kvv+dGrClZ zr08@1W8+Bm^Y)IgX%)$!MIG_GeIyOrcf_jhk=*;B11zm0*(<06?%PE2 zhEWH24v(bm$@cg=CXzRu+GB=CBzxyuK+iW)Jr8YxMIn(i?q#9&J0ltSsvTy{isX~n zb|_pFNwX&H;IlfC5s7W_Y;zq_2Png29R}?wY z6v2I?SShy!V(rxBR=2>65mB7htp(y;qG7FiVLnluTdz4L2S>5ZITMVE zj^foZCSZINM;A4N=>qlsHZ+6IiYWS9HN)HWQT+L;DNb#RqEBp7%-t8ow~d-&iQu#%y>9)}{=u;Qp9HLq7eH}PB zM>A`B9UOCu=A&kHP~AJ4Cz6ce6%ftE?#4J17EO`+EezNe%`caY5WY8>t6Yt+<481nm(^7J_R)N^xhAqNMKemN z34sJw#jwGdYA~oD!+=rMkli$fmvZ%Sw^a;v zSLvjR-l-5i{)%@s7WGF_Tw*!=bdJ)|J(l@7zm+DFV!5ir zZ$;NHmTmlgDc^%)d3woO70V8_zAM`|#4>8wH^n_6mgg5{D)o2A@=x+t<=%lTQ@8fg@e`D!YBV9RCsP5LL4|}O(*N@}Qqc0RRjbr1i=gK_OI4*7dT)A%+ z#{!RMib01sI&XQZ*ma5Hv6oMj89n1z-uQ`f0&%o;c&xnZ7svSvA1QjaalCT#q0(+> z9DkR8s0?Ks!-BULEspG^HWou9z z-L~FUHigG=SlS(BRgAix@f~IE^f=aYxUGcGR=2z0mg2S`j#qCaEB%+oabdY+#dK91 zhgjWIwCm!i8-7E1x;c*Lj$T*xY>(r_@7I)&J?i{c*A%ORaopj4RVh0f$L<@iC>Kw~ z@%qywCG5O<9EM4Xd14%s?Glxj*W!rTmz7z!;&>?Wl45=@j>bh7l{*jP7~bWg;{7a+ z4+1VIWodCV*>_%9_BM`w8RwKHALDqm@i}Gp*EnX4KC77jP#@nFXOw-v)#FY%t+dFC zV`Syi%KD->uCqR+=xO74Jo=;(R#C(2Cr>D^bTxeN^SGi^)9^`~2xrVBprfhDnp-#a8<#A^X zQ#u_`bh>M}*mu9u$x1_;UHcSgYFLuKSBdGT;r@Dim34zO96n-?a%`}MISY3yH->4r z=*BMPiKB+iv^$lzqcuF#W2f?QtcG2KcPO9SG(3G^yYkLc!;YV}DbKw%+|^{8a@$wK zTFwc|=|Bx*mTy(IglPEY&K6}xgoZtIwkYl~8ZJ>bD?O)am>#}KF_@`g>!TZ02T?=c z%nhphsNvq`8!#k!cmH9_Bygz=0(&U8tIILN&967B%&JUI;z0PZR zrphwq$|VhV_F1a*y`tg5=p{I8U-cen_-Fh=WyT{7 z6W1(IK0noP&V%{NfS2myS!KSG@LI!4edZ~-Z#BFaHCGv!p<%%BIm(L98aDhsTX~tO z;nfzim4-hw^cpuyasH)Yh1D~a<$pBXcrRYLo~L2^%JIsdLUn!2P#TqLI3QxW(x==s zu5z2EOsF`GD^lZ>*viv5w@<9HLT?&Fjz=pys{N0>H-WRFIM>Fz&p9)57=~e31O&u` zEQ-RgiY#+HvW!aW;3&Tot(b8Z8p>Y z!u9Dp+h;So6YJ8y+AEv6cWqtz&Mw)^rnhU%-fcEhKKrEfRXwtq-#@%2eSXhuX5EO@ z=}o<}nKsw2OfTF&o4I7~Z>7f^n9b~a_KI}(0VaRGEd9yAY^LN}OVhs|V)0*ElHPW3 zHuJk97pLcpu=E-irn`;KW=`q9ApLwgoB8#RPe`A4ST+-Db9{QjxNPQ-Q;tjjc|ta` zZX1;fv4PDk)IX#w6PhFeM zJTR&ved&5DzZ*uS-#9s&d1ddB>Ast?nfYfOlCC;6n|X29!RgEEvze*OhozrAEt}c? z`ypxnjBKXo;e*rt&&+1(?;Mz(aaK0-LZ9+<&3ChzgD&cyKKFZ8PKkrkSARd7xx2Ps z`mXb`nO(2%pZ@g)+039BebbL$l(qG)z0*(qFq=7NP_Oh8KgwoqY3P}L=+bQFsnS$> z`(@e8JE!zW-_VfF{O!Z;>5Hz+W(wwYOK-d?YvXErr;oeZa8#G{A=jG!^_|kC*IT^K zd!_$ygB`b}L;A)Wvze#=(k{LBrflYpC1vRmw`4Qt{iZbi*{#{kiDTQOZ@xX7skpUu zddV*=om6qU!(G|Tv*#w$_@&jeFALL)@6Osfn}T$r(ZXMfr>_XI8BC0&54k6sS@}yZ z{ph`Rom0Q6IOhIrrtYBK6|X*!&D@^cRk85FZ05bU{#@~ghq9Ty9@tqi=aFn?#1%U# zo_I8ynSRO#6%~)!eVhAk#kG%HJ`Q=SqU6b}&Hue#vFa%+@13t!Jo4A*Memob-ko<(#Zj+hGrwKcSW)+?<$KbvDlYm%HuFW_J1cH|Et@$b zetX5kf6QizUc0&Ch1av0(;9EAc>9fP=Cg~huh{XX)z`JxRP1~!n|W;dRTY1FJDV9$ zenrK*?_@Jui!ZBq`CY3gZ~v&`@%OAAJ@A8yJKxV{);3&F@#7D&nO}Z;Tg9diEuGol ztC;gqHZyS8*%jqG?7GX&tnmJn&20Pd^ol18fAvUx#f2YR{h0XeirG7@e)wxE_WH!q zyL)xTlZJC@mRFqiX*RR*z(o~9{%rT<_2VjDHoWGNqbt7i7b}MuM^)_inbn)(i4}q2 z_4kjhnEBUi=F*K76>k}C88W=0W|x)k`vWWfW?1=?eifVkmd$jZ+pFSp!w=i-Q&IbQ zHgo5rohsfj-1wccieq-${Tf+Zaj)SgAIB^De38u@Iequ&GYoIIcgN^I8a54lee@w; z+I?#H?dYwB+e#lD{aeGwPiY+8{VRJ8Ke~DJe8WNWt{Q!r;he{QF#5NK-yU`L=vGbU zKl9t8M;I;`ylC_y!>w&6jy}`yx{n5qzSi)*$2yI^-|+gGyGOlX_)yzNN4;vlSR{Gm@zU?~ycI9Wg^0!_2 z-LCv^*Y#}I^=;SnZrAm1S9xq#`D|BtZCCkiS9vz7d>d8XjVk{}-H%4ypGMuUM%}+g z-Oond-$vc*>dOjQVyf*6jZR{OB&y9M% z8}+<5>iKU}d(f!%p;7HcquP%~wI_{gUmDfkG^+h+RD0B@_Nh_rRioOkMzv>+YTp{w z-ZiTIYgBvKsP-{Xdl{(x4Ah z2YMd_dOrkuUj%x81luoj?~_39mq72EK<}SG@1sEPr$FzkK<}?W@3TPfw?OZ^K<~dm z@54av$3XAPK=02$@6$l<*Ff*vK=0o`@8dx4=Roi4K=1EB@AE+K_dxIaK=1!R{ed8J zyz3tX>MsQ9KLqMe1nOS|>Td+aPUqzXa;f1ka~k|0Ym>Cs6+; z|0qy@DNz3@P=6{=|0+;_D^UL{P=72?|13~{El~e0P=78^|1MB}FHrw4P=7E`|1eO0 zF;M?8P=7K||1wa2Gf@9CP=7Q~|1?m4HBkRGP=7X1|29y6H&FjKP=7d3|2R;8IZ*#O zP=7j5|2j~AJ5c{SP=7p7|2$BCJy8EWP=7v9|2|NEKT!Wa(Dy)~?}I?!3xU2L0)0;e z`o0MCy%Fg9BhdFqpzo7F-z$N>Ujlv41p2-S^t}`4`zO%%P@wOlK;KJ&zMlepPX+qE z3iQ1d==&?s_gJ9svq0Z#fxh1Yea{8@z6FpzqT_->ZSXUju#52Kv4Y^t~JC`!~?{aG>wwK;O%OzMlhqPY3$G4)nbp z==(d+_jsW1^FZJ0fxh1Zea{E_z7O=hAL#o((0D+g@qs|&1%bv70*xmG8ea%B-VkW~ zA<%e4pz(=7;}wC%F9MBc1RCE6G~N+t{3FnKNTBhNK;tEW#!mu`rvw^b2{hgkX#6G6 zcub)2nLy(;fyQqFjpqa!-w8C{6KMP=(0EXw@u5KDMS;eT0*xmH8ea-D-V|v3DbRRS zpz*0d<5hviuL6x{1sdN9G~N|x{43CSSfKH-K;vbB#?Jzcrv(~c3pCyqX#6eEcwC_I zxj^G}fyVCwjpqd#-wQO}7ij!1(0E{=@xegjg@MKo1C1vJ8ea@F-WX{7G0=Eqpz%p) zyb>C}gvK+W@l9yF6B_@7#zUd;QE0pr8b5``Q=#!yXuK5~e}%?lq48O0ycQb2g~oHC z@m*-V7aISC#)F~pVQ9P<8b5}{lcDitXuKI3e}=}Rq48;Gyc!z6hQ_m@@oi|l8yf$H z#>1iUacI088b61|)1mQoXuKU7e}~57q49ZWydE0AhsN`v@qK8#9~%FM<^!Pl0cgGe znm>T%6QKD8XubiOe}LvAp!o@Cz5<%RfaWux`3-2k1DgMU=0l+Q5oo>ynm>W&Q=s`3 zXubuSe}U#>p!peSz6P4Vf#!3d`5kD!2b%wZ=7XU5A!xn`nm>Z(lc4z}Xub)We}d+t zp!q3iz6zSZg66ZJ`7LO^3!49e=EI=*F=)OFnm>c))1dh^Xub`ae}m@Zp!qpyz7Cqd zgXZ&~`8{a951Rjj<^!SmL1?}Znm>f*6QTJi+Q=$1)XucJie}(2_q4`;8z80Flh30di`CVwf7n=Wt=7XX6 zVQ9V>nm>l-lcD)#XucVme}?9xq4{ZOz8adphUT-O`E6*v8=C)y=EI@+acI6Anm>o; z)1mowXuchqe~0Gdq4{}ez8;#thvxI4`F&`P)W&j9foAie{{e}MQ95I+LqOF;Yyh))6WDC2gLt?_#hBJ1mcT8{1J#x0`W^Az6r!Xf%qs8KLz5eK>QVm&jRsVAifL4 ze}VWg5I+Xu%Ru}Yh))CYYaqT2#J_>~I1oPv;_E>C9f;2Z@p~Y?55)h0_&^Xp2;vJt z{2_=>1o4X?z7fPfg7`=fKMCS1LHs3%&jj(CAifjCe}ec>5I+jyOF{f8h))Iat02A= z#J__0SP(x8;%hma@z#J_|1co07i;_E^DJ&4Z-@%tdY zAH@HI_<#^U5aJ6${6UCM2=NOcz9Gavg!qUMKM~?9Li|OD&j|4wA-*HTe}wpu5I+*) zOG5lfh))UeDBFh))agYazZZ#J`33xDY=V z;_E{EU5L*M@p~b@FU0?a_`nc97~%^<{9%Ys4DpL0zA?lZ{Bej+4)Mz&zB$A{hxq6aKON$$L;Q7!&kph1A-+4re~0++5I-K`%R~Hmh))mk z>mj~9#J`95_z*uI;_E~FeTdHw@%tgZKg9os)&oH61EBQ+(E0&rJpr`709tPVtv`U) zBS7mDp!EvS`UPk`1GK&YTJHd@e}L9QKocJB z8qoR;XgvqCz5`nC0j>Xl)`LLnL!k8{(E1T*JqfhF1X^zbtv`X*qd@CZp!F)y`W0wB z3$(rkTJHj_e}UG+KvN#>I?(zZXgv?Kz6Vyx1MO3?ZxXgw3Oz6o0I1g(F9 z)by z^(ik1YS8*M92%}?gVwh}>)oLBZ_s);Xnh>CUJhD6 z2d$@r*4IJn?V$B{(0V**eIB%44_dzmt>=T*_d)CZp!I*ydO&D>Ahcc(T0aP_Cxq4) zLhB8o^@q@UL}+~?v|bTfzX+{ogw{7g>m8x>kI;HZXniEKUJ_bA39YAu)>lI7Eur<7 z(0WX0eI~SC6I#Cst>=W+cS7quq4l58dQfP6D70P_T0aV{CxzCRLhDVT^{3E!RA_xF zv|bfjzY48qh1R!1>s_Jsuh4o}XnicSUKUzE3$3Sx*4IMoZBcrHTYn3!$3?cnt*DpUZv8H_o)=o*3$6Es*8f85fuZ%m(0XBL{V=qi7+PNptv80&A4BVrq4mkodSz(+ zGPIr#?Er+0c4zX#F;{o*P=< z4XyWv)_+6m!J+lx(0Xxb{W!Fq99mxvtv83(pF``>q4nv|dUa_1I<%f0THg+>cZb%$ zL+jz8_3_Ypd1(DSw4NSXUk|Ofht}Ui>+zxW`OtcOX#GC4o*!D@53Toy*8fBL03iJU zkiGy&e*mOU0Mai2=^KFb4?y||ApHc8z5+;p0i@3W(r*CiJAm{bK>83M{Roi01W11Z zq)!3TuK?*=fb=gw`WPVn43NGCNPh#Q&jHf!0O@;x^glrQARzq^kiG~=e*~mY0@5!5 z>6?J`PeA%8ApI1Oz6wZx1*Fdc(r*FjyMXjxK>9Es{TPtG3`lAA{eI}586G-0)r2hochXUzGf%K(7`coi%Dv*8^NZ$&ie+AOV0_kUg^tC|x zTOfTdkbW0P-wUMw1=0rt>4$;z#X$OFAbm16j^XsnK>B7N{WFk08c074q^}0jUjym0 zf%Mxz`fecoH;_IYNIwpwF9*_}1L@O&^y@(Sb|C#bkUkzrKM$m@2h!gI>GOf~`#}1B zApJj(J|IXx5Tq{%(jNrr6N2;$LHdRu{X^D2boz)O{X~$yB1nG`q|XS_Zv^Q(g7hCj z`j8;~NRYlHNPiNfPYKem1nFCX^e;jBm>~U3kiI5Je-ot73DWNb>3f3oKSBDSApKB~ zz9>k46r@iI(k}(+n}YODLHej5{Zx>?DoB47q|XY{Zw2YQg7jZO`miAVSdhLfNPiZj zPYcqo1?k&@^lw4>xFG#pkiITRe;1_B3)1fe>HC88e?j`dApKyFzA#9C7^F`O(k}+- z8-w(ZLHfub{bZ27GDv?Jq|Xe}ZwBc*gY=(4`p_W#Xpp`%NPilnPYu$q2I*Ua^shns z*dYCEkiIrZe;cIF4btxh>3f6pzd`!oApLNVzBovK9HdVU(k}<;n}hVvLHg(*{dADN zI!J#Vq|Xl0ZwKkSgY@4)`tTtAc#yt4NPixrPY=?s2kF~`^zT9X_#pj!kiI@he;=gJ z57O@k>HCB9|3UfyA^m`mzCcKSAf!(a(k}?<8-(-^Liz|H{e+OdLP&ohq|Xr2ZwTo- zg!CUm`Vb-gh>*TSNPi-vPZ83u23f9qKSKH- zA^nh$zDP)aB&1Ig(k}_=n}qaFLi#8n{gjZtN=Sbtq|Xx4ZwcwUg!ErR`Y<8=n2^3q zNPi}zPZQFw3F+H}^lw7?I3fLvuIgF^a3A^o9{ zK2b=&D5P%`(mx96BZc&nLi$P}{iTpTQ%Julr0*2ce+ubCh4iCB`cfhNsgOQZNWUti zZxzzN3h85o^s_?xS|R4Syz!$SIEA^oxV?e$KdETmr+(l-m~ zpM~_%Li%YTeYKGOT1cNQq~8|OcMIvih4kS<`f(wBxsd)`NS`jGUl-E13+dm5^zlOa zc_Dqhkp5mspD(1}7t;3&>HmfF0YmzMA$`G+{$NO-Fr;4?(l-q0ABOZ1L;8s!eZ`Re zVo0Acq~F-aS)IOPNdGaU4;j*r4CzaT^e035lp+1fkiKO||1zYH8Pd-T>1&4cH$(cI zA^pxa{yviWo+16ukUnTgKQyE-8qyyP>63=^OGEmmA^p>kK59rmHKeZ^(q9efvxf9r zL;9{E{nwB_Y)C&gq%RxNpAG5LhV*Mg`nDnc+mJqPNIy5EuN%_e4e9fS^m{}4z9IeJ zkUnroKRBc>9MT^S=@WL;B7k{pXNAbVxrs zq%R%PpAP9$hxDsM`qm-+>ySQnNIyFoLw)U#{&q;8JEY$o()SMOe~0wJL;B$%eesa~ zcu1c-q+cG=HxKEbhxE}y`spEk^^pF0NT0pUTR8ppkiL6J|2?D+AJUHx>C1=o=R^AR zA^rN0zI~fdbo%!pef*Gqen?+Gq`x21=MU-khxGkJ`u`z&0FZqE$X)`g%SCm?$ikbMfs zUIk>o0V8vZn&sSAp!UK=xN4dn}NB7RX);WWNQn=K|Sxf$Y6N_Fo`- zFpzy1$X*O&KL)ZV1KF2>?9D*-XCQktkbN4+UJYcw2C`=Z*|&l0-9YwlAbU8FeH_SM z4rD(EvZn*t*MaQqK=yYadpwYR9>`t~WWNWp=L6aIf$aT2_J1IIK#+YP$X*a+KM1lX z1lbpY>_8n$X*m=KMJxZ1=*K^>`g)TryzS& zkbNr1UKM1&3bJPf*|&o1T|xG*AbVJleJsdc7GysQvZn>v*MjVA;pLZ|{Vm8I7i6Cc zve$*R-`?>LH5uf`)H88G{}A$zUt!asX_MDAbV?&{WZuQ8)TmiveyRL zZ-eZ)LH6AsdvB2aH^?3wWFHQ)7YEsogY3yc_T?aZbCCTx$Q~VJpANED2idQK?Abx~ z?J)dOXYUTOe+SvagY4r$_VOV6d5}Fl$i5zAZx6D+2ifC;?DIkP`XKv#kUc-hz8_@o z53>IU*#m^^148x!A^U-lJweF6AY^Y4vOfsfBZTY|LiP$F`-PA_L&&}%WbY8Ne`x$S zXAcpwj|kaI#8<`6ej;Q~5wfoc*;|C{FGBVhA^VJwy++7>BV^AJvhN7ldxY#iLiQjb z`;d^mNXUL9WKR;ZFA3S3gzQg3_9!9yl#snj$bKbc&l0k43E8`Z>|a9mFd_SxkiAUE zekSIH_B0{;nvlIsyd2u!gzRxb_BkPYosj)b$et%;-xIR;3EBUI?14h|K_Ppgko{1| zo+xBr)Y^^qv^NUbABF6ZLiR}^d!>;5QpldEjpIA}rjWf;$o?s04;8YH3fW7A?59HZ zR3ZDSkiAvN{widT6|&C?*=vRDw?g(@A^Wb7y;sQoD`XEAvJVT{i-qjRLiS`K`?8R| zS;+n@WRDiIPYc>)$;ks*7@ko{!Ho-$-#8M3zw*hlcD$L-wN~d(x17X~^C*WPcj6M-ADhhU`^C_NyU# z){uQ`$lkR**UtVmWDgs%j}6(&hU{lU_Ov1U+K|0%$o@8Dj~lYj4cY64>~}-!meWWOA;XAapnhwPnW z@6i4^WDgy(j}F;OhwP_A_S7N!>X5y4$o@KHj~%kl4%usm?6*Vq+#&n!kiB=v{ySt3 z9y?My~JYhFh0-nOhB)9_eMCGaNs}%Y10K-`-wkx8cIL=fym334gKu z`&XG%Z=QQ@F~9Ix^L8Pz?xQU@<|j|{4Pph08PLWKjP;$xfLPJP3`i6N4Cu#z5vv%G zDEb8hk_8PvD`AL%tXPD#_PPQ1?!eVotS~$nNPbqxad^Qz+YN6jQ{G<77 z^om|JA+gqf&SDiELHD`-L*`B`#LdMd>F;^l~hUbHi{QWEG_<&NnMy^ z9%8-9yrM(x6p4$H{Y`GwCDE=`g@qS4F;a(C*C;nXV-g)(g_%nf@5|7=T7{V_EKV_n zP7;fXH!`%dj!hP`+!I||g?TM0zKlujEwQY)l99W*lg4^=v{GSV6#bQvy0yC7Aek6z zQCj=M?BB0Wxtm}qdRzHtn;)~XD4FT`C#9xZl$3e3`H*pIQoIsgT^nAFUz_69{D?C1 z@7Fo`ZptiOf31^WGP!iRo!37(#rwV6D}4yX&#A-lkQsm zF1(B`Ecz}iaQA12we$Owc4!?h?N)kpVLLl*S)tv}-d^k0hnlC=>`q?1bX4onttWP{ zwB(<((J2R^W*D=}qh~u)y;=DiO%lD=eCOGFb!X(=h-lzWb2D*-M0n-T! zopTytsqJALy27NVn=7}KnalTP5E#n1Ga7QC=3q8`Zzds%FtbGjo;>EA=d!~XdtTZI z=QpTi>}iO3efaP1 zE^Xuawpm=;{qpjGvuYNuu3fsOW>w|d)r;#^tXW;_Egm(mx@OI?nuV)UOINI{s!biR zVZ`u$^Omh%o2py0W@T+^Va=*k)v85ROO{kEnK!I_L~6*O!NX1(I?wzEtX{LaYCzS( zMJwj5SiN}V+9g%l?aI3ObthL>)s`=3;nmhHu~(G2?NR4ps}|NRH^~)ffh*kjU+(q%RNub6 z;wPp0#!GBJsXX4QJiam2t8ct66>po`5?@vxKPc7bpaaIn7naA{miLKIOT`DJ_8A;+ zJt;o7Jl>`}enNS?SE^V1w`fJ(jH-22HMLchD;F-C;Z@ICzhcRfl~rSAR4rWTa=VxpS+j7-iVef;T5IbT zu3lWl>-D0951)E;YFx_hO!+W(Zw4JQkvOC4t?9vI!g0mJ5x7_i7{ z!Q$nqnyPgxYOM~Wh72A$c-SGwrv|KAT)j5Ecuh@R)rJA9hM8QqeC?`5hD*(VY4y5c z18S=WEEznUJ}cKOtQ%l=KD~Tl&63oBWlPpCtXVo>NNT`QLsJ8mu3j^swytKyVvDkJ z#lqSZtCyMQQdPPEwN+u|GruJZ>lWtAOREPgUbDKcX5r$x^qQqhy*ew7acioUPFb^L z#nKg3HFh%>)~&5=F3p(}=T4YEW#UXL+HpsC)ni?G&RV!=WtHdh=&fB{yJFeuswJt# zmQ$5?r6s?nCRf;FU13`}Pp(=$_T(Yn$~BhX+;QyQ)GoJDY3UV4Z_dc92{UKSuN*UR z^3gLUTwpY`BYJHUn;X4mE4S6(Yed|`n7#yyD;!;nXu=pWo2#7&(twfCr+*OX3ig1SvkwIHeu1p zDxDBq@z$=`SjC4jEM1okW|QY>S;fQ0Id^kBci-H-bfuGfj%FS`Zrp^KGj(s6R*gL~ ztSn>Pv*F5l+^Biurp%l;GyI=Fv#M@w_55Rom2cP}|M4@Y&7Ztt(Y%>!*48Ypns@lP zaqeJus$3?WL$@ryHZk+6kkPrvHW$mxiBk_hdh(bVo@c3!N*%xlb(U*WtqD%qb)+V! zT}@4^S+lsRwsuWTZNGoPlkAP*%Vr@PW^4A%SuieqsHY6`3fmM-X%#CjY;Qf|z5LGc zF8B*i>55#^dWJ+W49oQ`+V9!p#L|B(}uQjGb%kZF%j< ztLhdmGOVi!ae3sjR;11==L7DQFRHEe%B@K%r)T-s>XwDAVML1(-N8M5#)ii)samvl znYDvU*I3fdy>QVYYsvCMSFTx{FD|s^ZdsMiA0G2{pOt)RDMh;guYB>ERjaD3PLuDa0XKyRF?HP|@-1fIU zY5PBl$B%+N&zs+6h&mSiEnX|zqiwVGtWzfJZ9C&|=lPDXo#{pSZ8W!6&%bbs(hGYv zdGYEkoV&ItUbV^5H8H5sq^jtm^1@b{J3oIvwfxPoOfY}U7tww{VCgYlv_)Yznn!+mEA!H8Yhh9T?l*UI4AXeR(&P7Pv_(#s zM}B&nEIpPh^ViPyD7`1m&0_}H&h2>nhAUv8HimJ3K^VnbRN{LlDGniu_qw_5wpT|% zzp;2DBSG;fewOE^T++tR<$-dPg-^_#e;u3i%B7Ry@w#|TdDYFUu=L{0l(xu8jOsjt zHnjJ>Tgk^Enn{7^272EH{RjqE$;0pcWe$cSKLZ#pds(U zR@>WKd5tlQHka<#UR%~B>RspcUXs`Gh+bf0zo8fRce^^CH`Y#6Y!&GQVZC9@D(7aR zH8L#ym=yuv&oRq7>nxG?n8^AUYwx*x5VNmyw&nC6Eaay%Wqvmk-AAk8Y{@(?{TB=Q z5K>+*JXLs(@I2vH3v*TMYMW!pyWe{R-eX7w&Hci zu{GfFu6`L>R-K#@_7)x_!~u3j0Al{`^6ML0`1N4QAHp$;DJhLsIZlDt94cR0hh z2>A}C{39XXwUmDS-c;cg)tU#4Hg`)}A_YlRiTjj;9iDDbf^W~Zv4s5I$m>N86@ZjM?h7BD# zGL;&X;uii79yDn9@ZqV{;30zsjd1=8in9|YSB9fLJR94z16;cnO4dgT8}@=>&f@@U z=eu|V-upQI%C0W;MVB4*{(Y^EdjG+avtv+{>a4mYj!3I7mZ&$KDjelD858Bb~#wV-{I*-3R%C5LMgh!n9PW2t$2lpis z!|uC1aoG+pei`p8@2{2dBrDUo7g`>EV|z#QtJ?8XyNYG*D*D(}@CugfxOOhDV(pGI z+!ZV{zh!n6>vmjy;`$w1Hu@u@s~9rgYL7S6-OunUsvD~hueOK8nl0NB{tfm#_}i>; z;!AkX&8CTVvwiamQx+6=@3`)+F#@+#j&ZZv-yN23L1HYdum72 zF(6Sij{(Vojg*o_!ws6JviMqwyZN#M58;7)4aJ8~?Bw7gvo?` zKM)=>&w?%HWphydEM8&aIrsk)`!C`g)M|^D9B6+w2SrbtgG$D%MX))jA38CXtaU;bw6q%0ybBfz2@@?ba#A9!arhD6K7BY$AJq&f?T8d{1bi1->9lBjXl(_iq+=Z9A8Ps;}s^xZ<+}6c!=dM?7cd=z* ze0QaCyUUc@T}iv}Sa%tr+ir3rFL#Mui05^;|7k3$W9`M)-ewo8=-6aFt=+XPea#|0 zO3`I~8AaBIHYb|HU$Mj@pJ`$T`tdvKS$bE$YY$Y%jplW=?H&1q{+f6m1HU(#`?{q18%?G+``i4XCi=F{nXbIhRQa&y$saf3N7qvK9_xuXo?qOxX7){L8s4%0+fH{$Sr-eRDvbi;tg| z^4GD5M)-bSh)e5j2LI=$bn_=~3!}-~qWsC*WXs9hR=J7M*87*Vn7S?2T&?C+Tjz;( z`6V{L%86Zun%E|964u0MV%Ns17;z4>2}!1rh}QS zIjxU%M|Ldm2D>xv)!L?t+26I9-q5Er9abZw$zq;p@4Q*$u3^AMV@tvr=5A3$t9jw1 z@jm4`TWuzJdw%Bg@ zC9rzB{2ID#x&6~K=50HYcw^}13(jo}Uuk>N`^!=N{xYdwj|NKoR4TSc>a#@X_hXZF z~`&hZMMhlkOrQGS7HA4?>0ug+;*D-XJ}*Sw12mauzzNQStRo0F|Wq{ z!;Rt0l!YG^WzNELMUa=d$vVV4&>UgrW=CGk1e3S9a{`ZwdutO7bi5q;+rQfwmEJ}n zATZByuWpmOv@q%{^U7_^NmQRoLwAbEmy-D(kc()JF18y~erXAK;x{h%Hj^41;IcE`~vrNxBON-0v z?c%x$9%lJi0$*@;iwR+tk0tP1*Dj9`r8^@p-D54b+luW!JZx_BwJ|NX(XqsKOP|18 z#=PpJf!i1yUO+CrX0P1+ZuXk4<6NG9X@c(^LwMZwxVO&F5ha=r*`s8l1kN|dL$Hw8W`_I+wBJ0zuOkr|0A~h-fV`31(ds>)#mlA z?Uwi?1GmxdPTTox5F4HQq=bRncty;#)rTnWR+AGA%xIW=?p7}_FM8WUN?-=!UhO8A z&)wO(Mwm`mWV;muVV&(Q8ZeXH$cNR1 z{Ips&v0+*>^CPruVj03Fmbgi7gWPtixhy;H_^XPuH&YXka?L-2BSII?g=mYFC=mHL8qPANt$B+ZeUR zcDrBAp)t2~-yzQ3wkwl(9zftXCGV{fX6Xh?zQ7yDEUYOlN0`nU8suM2L^`XE0 zyNwxPxYe=fl3Z)aT(LaO-~Qd!-~L%)SRbP8RXNzcajSR#&42%1cuz|#W*s&A|6jsX z`md6dZu0%|v4amBI6S@~weOIg-OSN8)jwWb-f!rTp+-CEH+YbPcxicmvXDy34;p-M z{Fw6i{;2_n4V)66Q5QcrwRYcugN__9C1x{9HeKg#X#5?|AKHCLx73(;*VKhGUW^}G z5x>%(G$vkJF~CxfZ!8}+bXdHmeAq#B4(~TSzP5b$u!9E2k1LNKkQ#VgeAb-!A5Kl( zHaXt4F21xPURE9}&P)BAnBRL$yv?M6j#1^(+Q38y+iqEnZzvyp(D1>7Tc$TOWuGm+ zAM!`Y$;pj~w%|bJlQEj9R*tUW{#uZDzCQnw$ITIWWmUv8YEFa9lK%{i#HA2XTtwh9 z4nbX2&C-=8I|f(v_}V(JdS=by!R~)ZOZpP|UH_0P6!FFKDNHSSKuq72UTyVCqt?`r zE#%Jr^#ZCM6B4IbP{#E!T7?nQ7Or%$zkvZ2(t*UK`X9|gbEKldo�IkdW7WKUb`F zEWWU;BC1n0j~MH%Sz9+Tq&9`pTYI)5?tuTstSry*99VwrHgOvkLhe88^!)32S?o~ldEVD@XKn6gP23}%(Men# ziK0f`u?gnUD)KbExTj|`e>Oy8yA9g8ZX5f1^K8#Q?;yLtdh?66D7}s5!FbVji^Z#p z3dua9F!mMm&wH<(_g+hc=jHjB9&wB9(J|)qdfP!_U_C&s*QuhVU&O&)eGe=)BjOJ37Xk-t6|xoF&Rp*j47vPj6be=cUY#>9w&vO7CuS zN5`1cJJZrj(V;C0yVKCFQVD(H_N2B9=abvKk$2TH zJnzA=lTRMD?F}+?w z$AvL@jO1y;`NB2A%|gzx^7x+!Zx!;{r~gyJSA`!5% zS*Cx1utE4U;a$Q9gii@y622q+i|`8~o4Z7a38Gy`Ct)|Dov)AN10@fWJW}#F$&-ne z-ZbHS`7al8B$nxK6rL_TM|d95j=xBFx%{sc-Xi>!@P6TA!WV?E3*RGJdS41{9?Z!@ zg%gE!M0=TS5N;w`KF=0jApEiLYT-@7yM*@&9~E+nm+8DDd{g+5aJMjF4HV z`^ukWBZiL>l37A|s_ zJ;DcsWUDaz_d?QDD1RU%Nrm!PLJlfYZY69l>?CC0mf@~_HRSgPWv)6WriEjK(}?z5 zxOUcXp5z6><-(Oh*UnnJddVcJ@c8cv&lmnc=-OQizf$sbLf8J9ziWRD@0S0g!Y72T z{k8DtCI3O_+F|p5U-Ay&F5wr#xZ1TMVX3gau)EN;%a$Jb8@!&O!cju@__^>aVUax(3^#&^L$Zk|lQKl? zBkU(6QHcJ-h2;3~ec|38hSMb{%qk1!bQSw3D*cM8*a@&nci#m3FGQl zifHL@W4mqD)giy#S^wO7-_RXr@jBAqFyh8@(30`qBu3%(ap}^x^oB9M$*wtTJa80kZyQN44*5}M-cnfEwlZ$q z@A~EbwzA5^`Q%V1E*`oyR_XVo`_5gl*9LDr>ix@0OLsOMTC}q)?(eK0v+w8Ue&vsh ze^A;ZacR*9-|UCEM*S3JF-Y{>KG zE-9&*aOKW2KfW^+f9sjSTN9U@l^m^Or`fUF7WgBdU;gxhvu-OJS~kS%xAU1%m4j9! ze#D%Ns2o-4|7hq|x`%G1betD+d9*lNXY5LLdu3PIy@^Zx^ZgO`e)@fHVwpc;@~)2E z>TgR7Ex4fM1Fw7M%2CUwcinrz-S&U%f>A4`cm2_VyY2sl1!Y4QPbk`%D%$bPAzKSB z^)K;u`Xw8B#6KwMQ1-FSEM5@%U~>D?r~MIU-WL1d;i9rbl0)o#CCMRUy52o@+^$5o zzuIw$OYTX=c9wbVDyQu#>tDP4wB7Mu&$S)@{0(wN4@{- z#!2swE52`6;)-*Y*DT+>J4U|^N4!5SdEc&N{p0d`uC1S88u#4x_=2)QWrMwePd!sa z#{Tz9*^apTnXpT?_scoM-pBpI{V3QFl^5$?>3oteS}O5a!Iyl0 z&*00d?|cTtifUMskEhQeC($QS@E0D}hu$MjcRockD7dcal#A$-EZ}!^JXy5NKn(PF zqR1_1T4qVb`}MPc*k(Ep98D+JqQr;KqVrkiWXw`J`!K@T4RrEDDn8|Gb6P@YFpBSZ z*YQvrQaq6$kJluAffnp*u@js9XDxa`cl%46<-coCnBcfXVd7zP7nLPuC4X*W@=*Ir z9FwFcS?h6o<`c7%EW}u^Sdt^ei8&JENqz_>j!l-^F{U{w`IW^=%uNn+VloMa9;c*A zl4mgGc@j&#f~|~we3G5w!UVgdt(22rC5!DeVNSN^a^lX_=z?t9s#lm=*-7GNixvndbyo9OkmROJ+&B$LU zax(cRhJLB5E=dmJv0q6nOR|%fXmV!>`R`1u)n4{jz;-U-wIVOVa#G!j{l4OxJT<8`ZTQLV zkE3{|iKRxcpTN6!jqPnaGpv$f``F(0BZ`MpJi_+U>Y0N*{|Ji5h2jv2wRVQKH}Etr zl%4C+6{|geBJbk9mX9)y_h!wp+fpP4@@qBHUsT z9=5Bwu$`(s_RI7`eo(XF-bGc#fEtrifv6o)kIM6#9dzs)%AFPE5|@k5@Gw{tI_ zpU#Q>yZL_JiCk2d(%)f0=WDZyH*2}dS8VkkXF-SjUn;hewyKtjt@h+bM{2Di_H#>a zG}+I29OkwyxzS}2?U?-Jc6t2d_ECTpbdFqXlnO}NGOxVPSKpo8Z%j-y3&o6S|Zj-6d^M{~NdX>VPU_@eEW!|?`g zW7O~hrpw2RGHnSm?<^-rnWJMtC?p%`;25=qlr+#$9SUWR&~};$RwRV8opUzfT-%KS znP{Nn{7^_X(D8#%C~2VMiclzPpyOuSjga@6!4BK)iW3cVgm-BM;q%C!4vWl4B@J{G zhC;^%Iyll}A>AA3Fs%a?VK(0be0y463FB?I3)<8`$K+6`%aK{5a_ML!!wX}@O-)^U zkxdXE(tEwPU&B;8_Y8Ob>4dqq+nwFiK*y3$*w8@7>QJa_pkq@gR5#GE+4em0YIHtU zs3>(;d`v&QE49f6I>M9HmbjBGFb|7X=5A4V=Gu<#%;Ej2?c(lNn2p-*E*tgXF{uVR z!kafUx_LbPYv%o-?RF;!J8Y*naaZU~U|+&z&~++Y@mU5F<|qz@k_I|TL!qpJ4la+e zRQYtVf}4{t*EwepPO#nTe{};L>q4QffsQ+Dw;E2kH}tR0-K*CvD`6tjc^n&XyT=6A z9kleA!fm$4yp#A%uD?r$Jnhw`u4m8N)D zywy_T^jw&WFofbh{2R=_^ufoU7;j$}U!RJ%N)3vyofL0XF=#zQ+yCznGn_tsIBa zKApYl8AiAAP8vScRF8c#pOVK(*Pa-YJkF)Is(R&y`KzdKZ?SVSpqV<^f_^#Q)Hc-( zA0`E7Ep>k7CF`P5VP11GB(MEv7?@KRMatY9{cUWXZn%FDx$^5AN|s9P@)gFhWKsOD zW=*mv+@sv0y0z2;_jd@9)r;1e^1qfeNiiZrPt(-5tZum%aT#+J%~2SuXPT10svPI= zn|Y9{O%0|gC)`-&t*=_KYSe76xr;-WS3Pkxm79&V0yXuC{|)Jsd}ro! zDSPL=Bl(IPTiSbbt22^Yiq0(DT5wk4?D%($Ejgz2u>ZVny66t%YmxhJsdDcB8n7OjVH~>5Pwx&(kN1iBYioOSy;qx?>9Ia=`>fPP zj`k=&hTmd)emsu*a|kus7{>iqw%h0ji^pxX7H?!E7%~pGCv1=0ly9_nBk0f;W#Lhi z^RJ^ZuUtA>Sacoj%x&k*ZEsq7FXp7?bMc&c#pPYs#WHK22F6Vb)8qZ&IrG!&V)b;1 z`9)iP-XlL^zW@LKT*T<<4Ri2yZef1O@p@P@o40>Phnp2+UVUYWH*aw_u#hja1e>?G z*TL~SStj?|AGw6RnuA@sQN5!#%l*(j!Z}(QZ47rW?WpAy_4PRJP+`d=Y*y4g&AM)GSyP7E;KS3(ZoQ>KC*;&5S_Xzz|OLdWN@ zM{PD`!+DD5cpD~vOY&NUpC)v?4NLbt$&RmK@)eSA7IGqn={`WT@Fyg{Bz%o%`T0WV z_!lORu*Q-8#|j-^!j8Y1vf-mb$7?W|TmC$;tJiispF8@qjU>9E5yJtJ2Mb3CUA?w& zKD&&6l#s(yl;;W;3af;CpD=u_knc{)u6`SyFZl<;YlJrl?-Fho-Y?|y%5 z7COGKrME~jXQ-I|df|D(i-bQGx^}|iT`&3PLdP>R|GOnWAbeQJek{{>d^1DGFEe~c z{;qv7nMP+A&+*F)+0mffO6b}hlRHW7D(ofPUpPoOOt@#eG)ewbg|2M3m(jfNK0f(U6CV)9y~ndwtvinSgR4fu>O** zi|Sw8+Gkg+f7i2qQa|^sKD!eAFFEV=`WMYr*dIInQtCUr+B6-;jY0FqGlRAk?@Y!_ z2W0YxV@KR`|AeF7-{uXw$CeKCiXCvFVfjiM;xYc{)UMcZv7L$7Uo75P$#KTh8EW~wWoyUX-pBWL z=w-Z_Tei;LdePSBwsv+t)9P>8x|efpGglbPANh1W&&8|z!!y)RIiqrPWxK6=*H7Pi zZ2fs#e^md>))(si5z*D}d?x!&q18caDr`&mwglDlm)PGr=h5;nHrwPJAI4Qv_QZ31 znBTI&>B!c&&m8kNYK)_}PT}*?*UbdQid^Sy4t);U#5jq9o0-I0{2Otu^C=o)Nf;ky zIi+L~y8+F77{{SuPeyzgc3Q-TS-|)QPqF{lV{{HD8z)9~ZhVY;=MP}qv8OXEQN&i- z_%KJ%FX=Qh8XtyDut{VN7yQ!VC9?j*1_f*ijT`fdxg$Qzv*tEFOplNc)5EfyNG0h> zf(Dz0M9&-_=5k9fv0si4Lrr>#UZR2|lCXmky>on+hZx#NNtGmLGv&S#jSq7%gZFoQ z7(4y7$tDX=y3=2uJH0!>4K9d;5O;!~i4&7d-pkzF7@fc_sK7iNdqjK~UPZxB=IZB; zIb$r8SMvBUe@MQo%Y2D(Ud!=ewld*A=J+t|$0lA^XIbqM-y*KEVF0P z#J9eY55xCI;_amPFbz3A%$2R8;%3h*@e_$Lrvo%`RgMqiO5>+3`7l@K_%L>;m$)X! zhjID1_M7=IA2aH8;={DJT=^Nh2z#-(e-l^QZ6_b*Fgj8e(uVJ5e@wYWIF#aFc#xyV z@FR^^Yz4h=L=>EHsah4dci$b)jf%7$^S3(l5K1CvoCFc9>(s z96>hBw=Ea#_;y%tj=x$^dq+%ZAJSFY^|p{pErjc4q7b9PM8PcFdn{;>f;U>E>EyYz zV@H;YRJdS<2ZkXhn|qqMy$&BL;ar$ML_t>B$g*}kn2!EZ)`;hf2g6(#-=f7I%f%+p zC)$6a#CR~wN*L!>^9o&xb34=7k@Wpn8OQzQ60~#5fz0FZ! zyBU-qjJMs?HN_g}m>LQRM-OrDVOy>5^jEo8uveFKWDGVyrqziMUhrIA@K^5Oji)xy z5nlaVLW#?toq-O%;_Y;Wj@H7}x+WAi&=HnQU8$okjWrKD1Azr)_lgh}Qq8H3Tr?;2 zC(N_m5n)&|H#q;fgquSDSOXnoPdH)_9V|B!3LEISHx!Z$bc6*s!!E&XQEBbLqA42O zd!w;vSb&GwZaM`CN7!yU1y60DgGrdMseumG851@((6KrcHaITJCnnh8%z1cf4z0N@ zI4;2Jk%DuJcRetXg73(8LBOH8LBZ4 z$HAc^yty-*Z|-c~+%Igmj1a2bvd^bWx9H_RB&iGv6h2GV7_($&619ol^~1-RzbzPc^p3EQ3Vm&+06JnKEr^ zu_$xYtj4@u9Qqd$nWsF}Xx%M8_MWjV;r{u@3X#9%%Y7|!?0*-T$39K}D`cMgJ!8-A zQxTGR((#g|@z$yM+VXhoIi3+-X7KOdXYV+sjj?yOF>3Pmc@ zic|RK*g8|`>dwD;@sG`5$N8t0A3Sj2z#+CY#`i;R&Ns7in)xv~_5*1yZr*`vp_*A2 zgAaDTny4@-$FZ>koQkpLw3x(yoojQ_;De0;(ZU+zKgGDojb*gRd_q93~b{f>~n!da_QghFBH*d(55x z2w5kW-4->DzF(ibvol&1i?}_D`H<~tn3cJTs%uWyS(Kj~bLW3JV<()m%;)T+@?M2} z6Mln!v;TrE$!PTR|M7LAVvaf=`wxiuXAvoN93&9 zBi?8`nCqsaEsD3$Jo3-mv4`g!W+&u%=^vdp>`+HX+Xs!!W2TzLT%M}UFF(Cmy~A;Q zrq|l`C_TD5_!ELY~wrV?`LU2Sfr$NIqS3Jd&a_&Vg*aI7`jm*=}`@#pAYpI{tHfojDed zbuijke%v0lJ^wm3<&}#alDm#}=8o#TIlXf%@I^YbMP)|JD=u%Ekt(Xqvy1t+x1HzZ z{oy(D)4R8;_y71hU*qTS4m59ZSAzL+Ghc^o%fFbfoN$3~m5?9&49^NT3(pf? zEd1}v*Kzu1?E0Ryy29)Hqwr(l|5Uz?oA0*kz1$ic@^XGIY!u!{wD89yzaWg}v3F6n zcV1^}yoiH^(}gD!?fA=t_X$4`TD560@4P2ZC#CS-!h?hZg@+2q3MUGu2xkd7l*Rll z6jllAgd2peep|fLC7&%kSNKEWr9#fCFx{JkzYy|WMF0DR4+)s`-Y&dL2;u$0M}0k=Pk)Q zgr5i<|IWfWqsj9n?S)J%5$+}2TbL5|7COG3#UChngs?(5PI$O*nsAozIN^NZa-q{F zW$CV!e6sK~;TGZdg%=1pH^=;6BfMAmYvE(Ur-aW7UlzV4d{6j^@H1hP(D(%IJjKFN zAtwWQ{+>cEKBwGYc(8D!aICOWc$9Fa(D4oJ_yv+z2v-T$3279J=Q&;I_=hI%$>X_H z;SIuTgb|;I8V8sT=WmIw-7~yb^20*c{+a)ClAjm;Q5f-gc1Vu+Ji8@Fe4awKdzMbb z=V>Q-FCldXFgzvfCmbLgE*vEsCp=up=~5m)OL&}czR>9#v~W%yGajdJiCN(mq0>WU z{^v=)Ncdyn6~b$UKNH?2yi*tmUAu4TIi9BB6Y_sf_`L8nA?H(>uMdSE3wH^>5W0R) zQP^*0d~QSwcKG*rOaq6H7?R4{ayD=O4v%T@(2;`%4dVg-n8#F2g&%o5rk-98Z^SPO zejMy7n>Kdg?SHXGa$&rFLjCv!y`Jv!g2`*zK5hT=yFSxya=S^J7u>(V>z%Ch_S?JC z??tZDg4;#}C6n7IWam5e2NgV1Jh`>x_ugsh{mwhd$*m;+k*|(_ck8sMDf>*#=h+Px zew_W*!+*>kTJmJ}_Qk)*22cJlTR(MecKVxBvUi-WM`llLnw>fI zx{E(QW!IOtobu4wi%#h>w(Tjs_rGh?wDjCfgSPJa_F1jZ|MpRj_5JowAG>qo^JQZ< zu5NhbW#fu{A~7+<V^=PDyyHoWSA2fbqLm%jEPQI^ z@&&iIIbr_s{6jy@$e zbXJ!$Vl!7i_vG{wzWCv^H0n67` z2FLWC@X;ktk9&H|#<7>q={e@&4IN z&^0l9+G#%+_Q30Xhn_I$7lRi*JZ4aj<&T$tG3w|6Yo@+@kbmpK1CKoEtpomi*|Pob zobYa+IqR48zIn`B`(1JS!k*n;etF*>|8`7|+s}Eb`=5p!-tE)Jg1z5cIw?E>FnzE&5zEOJqOEcRXeB%SHgXGZSOT3>XCtOulbg-8#c)RaM z@!$77F1EGpqg>y{ZjSeY;dk!(Thk)L*qTq9F8it}ySeX2OkCFr+wO#J*W2JrVBrA%9b87hS1WjnXJu4&3EP1#HCy|QV`^G(@(HeA}Y<~L2* zD+XTF)auEmZ0~o@ZJPB+Q})`+w>C|`zbV`QnA4iR+TN7CrOl?MdB14N9{k|irj<7} zW$)g!rm6q6P1($_6-}2nG-V(BU{TY3KWxe#dDXn83%_smdhRhzd;fnFU3omyZyfI+ zl0+%xD4o(J6{#G#N{CJ+Dxs95a_snC54sa6=^_fLRC1)`2)T-|v6;=Wxi*_^W|)m_ ze!u>D{`o$y*YkRg@8|t_f8Ousxibw;E<7~tiA@9Mp99mDk<%b3+Htz^@-!H>vYGz3 z{|O??Y3-BKVCMU+(Wd^0*%-q<&QcgcAJR8z;M!-XE2qEU#UepP~ewms*r%aZ1o@{8vfDlmORWqZ|nRzh6SRa`sszc)kCJ zvc*FQET{98M{Jeg@3&9N8=I9NFf>bf-cSh?YhNp+8cOiA>xI%%{-jSpjYy^>Xm> zgoW}!fgBuPV5WSWA_p_-)+-O(l7mm!DrMf4|G&31RMsDtgSo=R$|p8*Q1o_za=}_T zxO951a*w7Q7%rZzTsArdn*Yib@90zD=1qx$T|NbNTZk=6dm;lA>6d5RE5)?}j8Ax~*rs(pKfk4j?#j!myuuJWN0@jxS?eepV zV=^h=;=C2zG%2Xsa#XSGn-rw6-4&`&qyS0Xr%1mp1-@Q;6(SEQu+iGB7~UuaD{8kZ z($u9u1>3BcF)#sm7AA^Cl@p*vV613MnE<74^%bs!3GnW;uHxF!3GigGmSW$Q32>uP zP0^%20U~bARH*eyK#XpZ=lmL5b zhrCBN4(#Hn@)7d?t#h+H|HC-2SNxW*jUETig}>x3C&z*Nl~TEp**G}1_M1FibsU`O z`XZ-yjDg^!5Auqk|#;7eqJ{J@+sP`mlQJc}_3 zx(9B^zvher*(+2Y5i<&wc;V&!$47ys)^)k6=_oi+8!V?yi2;lS%6*!|;I-u$`NP*@ z@JDz;9vLPEqgjXL^PI%M_^g}!=wdPO&~ui%vqwNwv#nh6Z3GnDv63IYGXl7F+vKND zjDVHWjdFdH5#XDhC%xV!PMRD!(d|{d#Yzz2%?f%Q~U-YXg|uB zdiP8Swrf(R76k}FLUrTR)-6IHLh7cbr2=roqH+qW5`gc5;;Aoj0(rwY0&wq4 z&eZCa0w7uPekzE^2N#;(O!*e@LHnKLsaXgg9Ne2UjdOTFbIYNriUuyoU>}$YOyC0RG{>ppV_ZN#VKY^+lnV&jJEsVpgTUa=)+tun zAgGAmFg58v2rlhjGgY&85a^B?P1z4}z^{*bQ=!=$5D};|y743b!_GU7FA`+ zaF`8}>l0;QRdA$xp%k;8AV)m2u$20oC z_K{DM&VGGBKRauZZP*7?171&B(R;zD!OO`#Nxh(-k~lehs28-y#Z4a9>;qT`hq5Hf?0r*a&8h@%>on0eI_q; zGJ(c|gs3A}eZOwKRs2GHo9$?Fl_AnlXIt*$8=-@*^wd`nHJ6L?>r!4+X`~PviNCsK8g9&DyOpi+g zp)Wql&cC1m?vb~$zymaJQ8P`ZD{BM1n&+~}_if-hcr3enq7BHc9?0D1w1NBLTe8Zp zRABT8$TM{i+JiZ_cUP=Kw-Th>9YFa_B>M7aL z>#g8X`BB+nqgLQVJSdy-rv*%H+b{ErXaV2(du3rOS^zF zZBo?zFDOwqOJ|E4!0)0z(ml@_06nZqy4tz{3~wrvma*!A2Irep{Z>6NeUmFyHLVBk zKH1Xzzkfi);!LT|wLjoZ^DC+GqCcSJ-ZN=W;cuYk^hkQ_KKyx!es?Mwh-kj@F5vT>(Z!Syk8P|dtzUQT_6*a(T$ysT$UkxZBos=Ro zYQT!vBT`0MHMr~SF6G)*gYju+>4&Z=aIx4Xe^rnfh%cbDvliw2>Dy6{N^Vh`DloGIAqjbV!M+sP1Q#di%Pz)sC%fyL* zV!+z{VdDJc570E8KC$-E5AZ8DW#XyH4^VRX=|oXk5%{q#VIuZu5h(4sH?e^G9aN{> zm~h6vgO(HM#KuM6!N5ZNMAf@*K+$+@V!rh^U~n&ZLXA`iY@7lo{^dFsrcY03PkaT5 z#V00~-~S3~BM(n>8GZ%It!@(@Ukbn;zSG1t`vQQyvz>5k%?GvqRugrB`9OF1wh8%o z9tfguoanoq2P&Sdoq+Z7!16;YCaT}%g6Mh6Cdzl_0$%OHiQu{~z&l2BqR#6JXtbF# zK^@2e`()FSq=+0)`&A}Uot*<*uZ>Df9(@LsjRMK!^3NcU!WL3vM7=~374re)RDYGk&;J0f zN99O7p1=PeN4=MnuX+#ErEerXpWcD4f@H~8%Xi@W)g;NTiY)MS<3ma4fh>SV%ITi|^bky!O*f z?`}Fk>bxX~Ryufg6Pj*^MA*I-_ejbzK(*T6Pnr(|(<8o+Ng zm*i|o1BLtz5@~)an0&uRGG>_yoX;Ai|T#~_^X6g9O`jGfn1-Mzs9LF_1 z2a7QJc%{d4@P2pe_`f{YapLcIu*WknP*6Mmr|~I>yH+tycYg}@Y%U&u*^mT8+=B7> zu1Vly*5`5a-%mhDz`OA|`<{Ru#&5wf+$1a(czw1U zkKo-0iNRaP!~E|9n#qRom5h5}<-qFkn8Wu#c)HQ}lizni{aL;7lXiE3sgcfjW8od} zkfAX?y73N}dZsd7|K>IbJ+2%(s&^Z37D~tB9^3*KNh4##nYX}j+|bw(+)aSG4U7fy zZh(bznPY)xZh)NH_A%X-7;yMz%NX7{229!i9lKu?4L(lSjCpR11_5Q|V>Pd$z)JYX zm|#H^;8+!m)kXtQAo(?|MM%e(mh zycLa-JTHQb!u-*Ng+btD#HUeJ{UGpsd)DX&>;gy=r;Seco(G@vUX0G!e;)k0mN;6T z9SB%vaigYMfk1Wm_NdeK0AQXIHL64L2N$kDqYo|pLHeeM(emf#0DI`l=<7*8VE!>^ zbi1z~xD|YE6km20uuOeMLzbTfj@)CTi@+I>^WJ0hGV?SrzUVRdVaP4fjt zoIRtjls@2Hmc?kvX&*yt?B4IgHs@KVAZHC(HpFIYdE@+b`p>SmyCYj zaT45Lqdls4bON~d&mA2XdVwXGvq#h1yue_9LOl8IIH+7bAy!j44l?>g;+nI^KwJh- zyrbkO00I5t<4cYL;_7a($@L=u?xTr6HXH`GGRR`q+QZ;^K!dmr90K{PYs6>io`Bl- zQ~Y6@Czz30B+iWW0NVre#sB!N&^4dLU#t&;y#BZ1pHJL@A~Q`4_-^3v`4?ibqZ|0V zHc`AJ*%d5gKM)U%8~|9>ZE={(0WfwUN}QeQ0dR>(UmYyLmT2yke*v|t;s)%Y~>-Nzg-8{UrWc()bYi%S~`5SsxT&le+3 zHfBJkojB5VXAAh*@?d0H%VzN4$?Xv>!_C0oD{7?h{3hVA6dIZTWh2%scoQzM&~tp_%l$40*RnE>Al9wWW))`6SrT}JAJ zYe6B;e&n>pS}^=+&&XSN4cKX029(kDBU$dNz_xFzM*eY|FA0Vt z5pBj`-kv2R1Nz3`mSVw(`q>p=ZpGY@&h+IVDQ5PFKiddwbXJI7ni_$6wF%LU5JM1F zFA^>PVgS~}@kGHR`he-#FS@v0A7m`-7A=ij2Ch?SBI38Dz~wnv^k6~{toLaU9kS8` z3zyf3Y6(k#YR^xRuxK%unOP*Nlj;JspnTC0D_yW;!zWQZei1MeycHqe7J|dMX(GdM z9e{?v5M9}>1M)2sMc1xtgAv&S(b_Kyz^<~}qFBBbh>eO8WteIKjw2)rxiBBNt3`-7 z>6)Op{)$MKIS*`$4-$#>=Yg+>&xvBZG{D})KBDSJa{;yenCSaobr7E7A@WsI2Znww zqI`Qb(6rh?R1D7n_c?n+5rwM2^P`1`DO3R~u9}JDCMrO>%~aIjHybb{t3+-uW`Vk5 zLlH`z3Cge~qH}X+f}alBBFWwv;P)I2kqu!Q>#UzGvizdNWbuk&)_?+Ad30jf+E9TV z)f*XhJtD{AJ9xu$?@nQ@Y5l`c*(A0)uzUEGScW0%+lQ~4$S@|KJUrne#oY56hRqTt zu&T(K;ic6Q%z1bDaKXelMp70H&)7JQov+FtR-PWiRPKHn&Pf=>a@@0qwX4L~Ii1(T zYsN>g6>Tqux$8zS_RGZKf4p|l*|_1m_lB`2YwisD7Yi|n8#OHC39!pK(C{V$0d_t- zV%Wfqj|E$W4wphh7*P>4yday0J^poWSeMSl3h(#~*Q;@{KKJ9p+bjn$gN2^M?tvWa zG|gpL?=c(8PH`B1Qa*sq^tT?a;`d|zCYHk)%lffKzS*$lzCO$`-*gxX>&2?^tB0?q z_Fx`1M#FmbEUbT)-te_?CU)bu_AqSB#5Tuk3|qN%W4%XJhO;8Ous6$;!rHV>ESNbV zeEz2cvwb@vG#q7MhL?wghYcB+s`-G>%9)PIB;7*tm3C~Rv|VWUl!nc?(IQ;>vkhBx z;IFWDfQp$fs1>f8PsL7A%Y{}uC|F$b58>3QR;=M%f$(~C3$|$eXW{dAWbA@4OL(o3 zgjIiiEu0cJW1HcZ!ktT-vDfxbgllb@u;uFU!kTl9*t@1XLcQC6u{}xALjCLpjP3&q zNsaZ`ja8Atog;s+o!n5Nr|ut2^5vpXf9G$k9Oo~5>RpFDvGEnwz_nPoikI;1s~YS~ zgQw84yc#?D_<#^%RbfZH9fenCR$*t1ZG?KOeqoUuOW`$#O6+OQRw3kHf&GfyAlw;K zj>)Xo2(#Y&#P+Bx7uHskVRsw!gwL6!80)c)&`?=|Ii8v)JYraa<*!r~{;O$hGMjkB>W6Y+u|s}C4jepj&l(0hz_Cq|GT z^bWH*ga~@EEG%a!PEein7Tef!RdDiCCRXs_k|6b02DUFOK=8CZ9UItvT3{!9gC)#9 zAxNJ62HW@dkl_8&*O*$8tKj11G>m%MNkF$x#XhgI708dj!X6Fp6p$~aV9`b9f|F=6 zhDL7`JW6_mKr&unPZzBaEdBNzE9_h<2>SgDW4>J|2x2_Nbgya(^!Z7cm(?5r zrg(y7%$y;3qV)uus+aM7S0rM7Pe%D|W{)w_X#s!M-ba|b35U<}Ou#527XRAWhgeWC zgP$K7kEz|H@Uzf3EdO8=-|fKz?2_JZe#XmKY*SAq|I_>X*i?22|KhiM7&W4hPp!I( zmD+yckCX0TIqDzywOzNd&n@Zv1H4<<_mmVqCb@|-=Cx3@a7}^UV&T*w!C`{I^~RR&e7C zzv(QD*?XMif4B%?olB4KEw2-?8+~s4NFo8V%yH&lh{j_Qf*oJ|9uBK?+{Hhg5Q)9e z+RhJr7J;GkO?;!&aO_IvI{w|vFznJ*V}54#bu4VRK0iG78g@rjmp@i`6?;#b&o?Ov z#oCh9_?i`0umwRg`RUamnAf(cp`qWGvGms_xWK#Ww}F%{bw=Hd)Y(m{xg{4@ysE9|7px=W$I8yzb|$~@N7u4-vm)X3IT(7^eF8heBMjZ|^uj)U3mY_D~Ash}H7syh~vY*oq@nf{i|g{#{Ik`4_i!K*v0E|vcWP+Xgu0(Ys~E)nRjFB9&FmHf!DisH&(f(hBvCe z3ri6Hz7^OL6W##**vSnUg5 zUyV8T;YlLzR?$|h$3Koo&o;wM%o8%sC-0)pTI`3z0bbyY zHP|B^N8ZBWRT!RS%?s~ZiCy|)$-C8Hj0Iy`d9FWJV1$Dkc$Hbpu|&f)JYJ#^Rx)J7 ztBEqi#Kn5NqgM!jQ}YD=)A z&%|5@u`V`vfzSQYxd@B3WOJKp7h=|PSlrjSI@lzY&Rz3T8>@NS$~|>s0hSio$aM(O z!frd)aXXLA$DqZPTvHoO3>_%uu3tM3i!1!frE6+nA8+MwZN}6w+VS_?BOPj(_PTVg z{;xUMNl7yI$$M4ob8Qm0GF}DKe)f?2I$|~!9dwUtergsrz4Hb)!fqz^Kpo`t3g!~Xa`b>(Aa`fs6l!32hWoFMJ;gu4ZGdGcx9l+Y^%*HT z5bwraZ$E(!pLOQ?ua=-{=5}09)p2z5tX*6odlWs_x{Yi1Ta0FAZsIz87(vG(*Kwuy zMCg(I#$3PPVYGayJ{NKoqPuvDxcfH<&|f9p@L~ z&4cs4vQYPmKZ83Gm}u1Fs=);z-RQ5tvcXsTyU>L@zYlh<>O`;4%^Pe|FwpLf?7{GM zI_jO1Iar_Hj`l^R4z@m^q43e?gAXsXp{v$C9+cZrQJOS%&}bP2ec5npP&CqlhNObQ z$a*q*@H%nuQ#uK?b_ySS3N@p<^{xzVJJN*i<6RhxHf==DmH7?E%=nAmPdGJbNvlVH z1soep`TPe}-{~><^~P`Xw1&$d@UBBEyX*($TWZnmd3y#os??xgZ(0n_r&pm)C(Q=a zKmS7eHku9&MpvQ<)2jx1k5`~>t%iefrse38cS{C`Gt5cym6QT;0O?r(w{0@t0H3_yx_lQp;KSDhIW3sNgt+d`3A-iaCq-d_vQP3OFz4 zenc-+eCD*!KA<*9?>MDz-=nL7-*CLc-=RzFk~tstW}*7JNt}=K-=dqi@tm`a4AkT2 zT~2LQI*KL6aF}6l(4Q9(&PUtV=zLoo$5bN?y}ale=M?o7+CF%RWBWPfg`MZe2Idn#WJkES?i*r%w`!RoHUmtDm6fpIULk z`HxYbkZqjQua8hahfN#^NkAi)uH(#gdWgOduHd-Mi$@!)mvQ#CJV3RR7jf9nV^RO> z^ErFZ-bbtVt8v`d-a{>x&*W$f-9Zb-CfP{tZPdA8jGY#F3+;a+WaD<vY^5>= zJ?z=b-dz=qu2|Q}UVkSFmCLE@->v}Vwl=d3wf;ZO*?-t8$p|_UUBzZ3!svYOGPbi9 zgj#L=&h}qQM8nkb*xML*w6r^$U6_nRmwd})^L!)GsJK*ii%|qB3w+ML(jA7zSU+YL zr(XYmULUZF&s;-)4c%ggEWe6ERe;^nbp>@uCbGFHA?UL3aQ0W9%jitED{OQ9V02%KRM;?6v#P zq2Zd=Y^&LRD7W8&E&q824J|WcM?j}hm8YicR1079L+ENYEINgr*>A+w_~?zUG1g-r zJbx0ENwwMbD^8%@WDPdA{Wwa=R$)6nK8Dh7C%+e*y<^Q`^vonP&#FKbfPh;N-xg(_2x!Q%43iYMG&Q(x+$wLawj zWzLJx>75PzI>S1st8Pty$#ZS=t>|a}KkbrEV^RP5q4{Y1hy4DbL`~G-_NRV7>v?Fg ze^&p!{<-KSyVw1J{|6OQ!^8rQ!*Mg=A1-|25&KO3byjP5sW zo{4fp;C_q98K{wf|y;0*O<()E{?Vj<9?D`_F4kA&1I+`$ai2q#?zt z-|VOqIRPE&H=d9nV<%kut6z>I=@w4?`nF?;|03J|H9cZv+sMxTo*N^GZnJs+;dLTJ z?eoU|@ZUm2BX({7fnWh*d}&2Lc^)6xw|`l`=4T#)u3gkWb&!kH&Ys_&BIF>(y>t3S z@oXfvVn+YOmH|XPZL%-FsSkOIj`ghw?L{nng?)DOdys+MgMAA>F_Cx6di$Qcb|a9q zqmMk;iJYNP`^s*2AjiHn_xY}2AU;Wd`f@7Uk%)+@zJfC}B=u-nU+@$ap>O-%M}0;? z)-BBI8{OWD+#Jd7t8OMEW2DSJm&+t1GB>pk%xOl{6Q1{7deew}zWTUtj`d$8!1F<$ zS6e-@!R&UQ_q9LB>;+MM3p9Qs0wJ-FkWq{9n!@{@Sl1vEIam4us8xvG!=S!_E58tz ztLOUk=TsuGo<4oEQ_B&i+3~(qi=T+Iwr3yzZz)nHa_JKWlpy=a4t?p9Kaie0>pqP~ zMM(T(%f5fQwS(bX`^2S%h|#ePePKtwA~P)3^ks4Kk+H?g`{Iy1WKyEnXQGpf=(Owf zMZC>H_WYRF7qROzf_tgjx4!WsQUy=<#`|R>t53^%-;KUUp4g7|M%;df=ot%oN0(+H zpJsA;*L}=Hj`Xp5HElAGc{PmQw@q)5wk%5T$l2FO!QG}_kth{O5B}Yo5&a5DcmLI^ zzAyzT+)~=RGW{jO(EirTH-CZXjDG38T=@(+Mg7qG>d;f9@Owt@4dxSM^~+bi2BC>a zI`XXdg8UJ(lIp#>S8)V~ z#M&73x^zS!u`Bg@_XmU{uT*tOOxQI<+NjctlZ7Jo`N|&qs4K{;r_!E^ zIU&eASllCi5R5!H%kQBryo4A#v3ssP4?=3!vwBL6E+E)^Mo&q4AmS=+?YUwSfSAx4 zds;u9Lzb4-_3+L75Q8_BJw*j)5cAt5Jv(=vM!YW<_5>IEAWsf`>G`Kw?6vsN!!19F zI2dH~SUQ|QzRh^mV_AJ1v1UK*;W{5fC=Cfco^?l%sJ#0W=o%svQx#oP#}L2M471$^M?oioJ*nY~SNxYlm>p?dc(u*dVW5EPDK`tdRgSvmW`^ z-H6Q+(;heTUC0K-sveKeJCP0jhCM2#mWWNmlAbG>JCJ~U?VkH9wj(JoG&mRwki$je$;7Tv3n@wbgEHLq33%=kK1T%$2!jH_hTI;}vCo+)7!lo%n;_Z6~^ zZZky0TfVTe-s>Z0^gggYFJFdqPp7kjp6DUh2UA$oxl0f|@>7-s(?!TX5?BqR3z4++ z`>dlEbr2AHll8E30TLd8v9Lp02z;8rT3M}$Jlz+@!tb1iRGWpcqO#{AbCz9T*%+xK zzO(#TIS=O`HACL4mYJ%EJ@qK-L-=fj{PQ4d$G}V^^8J2RxYrD1(_?$q`8p*mf%mX9 ztQ0Wyyag-Z{S;j5X~w#?bQ1o%%arv`uR5@LH7j#M0x#4uVl`YChmS~?u(GJ5@Vj1Z z)($5ztktN&!sUzL``=YqmyL(vW$8+$ZoB|4eIR9Cn;L?{@nUAwMILPH&u2PO2Vuj5 zY-Wi)2iCG;G1;F7VBOUWX7#duc#9T=>2<3Y_LVgYuRe^~wfGO*_$`Ea z8mWUlGA=L^dTZeRhki_)OEnyaoMLL{{DR#s9b=wZR0$h;c`*G5xu?FsUU%m)t4cn@1~^rwxzQ(hEMU6(D3%TP9+q{lXTFE~>_)ru z?B2nXn+4s%wEr1=Lr!=1bOs!t(bFAsHXZ&hWpp!szJ^zDDBWzMG&q^s)cqED1#hbU z-MzFU87Ald>bBeU5{`XS+P&=AbJ#oKTlf31r?551?dBa$f_H>wce8R5;k~CbyZ>pG z{oGT#IY9|<(w^tt(yDlvx#4kl*@`&WR{ue_B^(Rq&Ar|2-*ykSl7VhV^Sdy0kl0O& zy$#=P5AR;Vz6rbizS3>5_XfPKD5$&sMKrwl{kiTfqyNh&p8Iq=yJN8V-Q(TbZxQ$` z!L$3J0)pRMJkb5?I1!efbnJfr84m{@u<3SC#lii%c6LAVjewyI=G}<}VelG*jok+{ zuETxv)^_LnU4_5Pmv@uCU4dT>}o#fuk<nuyj>*S9j_$*l6+3uHB*|u$Nj;xNORwA!Ui2`!3!3i$8^^$1kA3#Sj**dFr$5-j@WrcLof2#KkI$tpZKpl(M$dq* ziG*EnhQsNu$6Y&NbITK5J*Jj0#q@C3K;#bifstERO64}#TgSOeZN52dt!me`?xY!P zA+ze5Oy3MU3bu7c3pTv(;oFoVcr{Gx>@(yuj>l=h6Z#IDJiRr;Ah* zcGa)w++;HkR@W}>tcjircdCBvTv)3H*GzrxT&OVzt{HjPS$9wcW^mqgZhbThR_#vi zJV==V@1rDjF4voeQtBUeW_l~2xs~@iyOO7%*zY$w8@goB>KwE)WQ7!J$;5a5@{>SM zldpIFeKQ7KdwjVwwpR@K-8Ey%sO+tdm!R=)6Nagn2_(r z)tx?+F6h{5qfR@WPAI@Yue1Fi1G>9Nr*rN7cIelaIWM*?YP?=K^b2l z-Rn^uFWWyu7cWB{G4nq`9FhiU6$h-GZtkv{to^vY1bgS7o2bbYCAM}9yYk>tz)TUN0f~Xi6kJA1b`<0? z*~eJfjzK(07sE#th0;f9j04+XC`?3V@XrvTlY$0@V=Nx>;?*!bzehsBoN~s3zHlh1 z{|DoyRv6UYQ^5GV>l$Rv{LHu?7z(}Ve8(_+7y_9x-Y^1w1VeSSWX74kix5gpV$7c( z1RZF7$hdBK9@5d5mz#8p`>h%2@DfH}v7hG~KV<3M%;_qhIK;ga&?$ z(pS#5fYucY=m~4KL!g*LFK{-8hKqaX4=$KN_>vC#vOAlhC8bpQsdpQp#?of`p*mA2 zx$F;pifsZ#|E!|>%vlFvG4M)kiufYB_YS`YpXF z)exf8q|q;x>O*JiUeJHgmqN4tB+`FMmOy3oadg6>#ZbcEJ9M_$A_!`Vrq6ZPfe;c* zX9X>Ql3F6^S8mLQ>L^#~IjQp?ZQ3Pz=8w71b$S5ZgQ5oUI!@C+3soVg`vkpGT?Ja* zbC`aA)hwv5&yB8TJp(FXJJWX^R}w#R?dZm#a$*607rpfMB(ZgPJ6$tPN}M;knXdC) zLiCZC&>Nb@h*h$c^xbSR(NSSQKdlfE88ep9Ep>;9_f@p%RT~7vBkCG-Rr?|0Hcb`! zloyw1s;z8)7s4U#(v`NW#S9S7Efu#LKI>ws?p|l&x=|uPKP3>0~v=fc2ez)URwGrpo{A%B3K_RL+l(whuZy_4*|JMH7 zn?yX~p4*;&xrvx^IJ?~({Y#wo%50B}uO||HQ``S}lQjLGw;SZv62AvMZpSLBiSU&N z?Mb9xM6dAM?f$F^q8l-)y>Iv@@dSX{mra)vky{b%Dq1DPAF-kBnT9`z3m#u=mu>h? zM4$V&&)!u?R7vw~|Fy4xnDN%D-Qrjt@zke7?Ptz?A#NyeZMP2nOk7m#)ZPSrBS)GxF~qaMl{9nQAd3h{t*VRy>{Ld{~NLUDQF$K_$MFtc1 zcN1wN_>08HgW)tM=mJq9zCv?H0*PUYAeuVnPgGa;r$NAv_7fA~5ozq0zoX zzx9V`S}~`HKHFVs$74(uM|E6Ulv|wsQfyiDyN;w#hSA#5s!owgaauiM4Z?Z3mC< zAiiEgZ<}*y8!>TpYg>ftR^scejcw1Iwh(J=>e{Z^ZX&9>RkkU2ZXljHS<+^2zMe=r zU)Z*L!#bjG_?Nc9RcnYdqd&B{8LT2!#AmbxEHWlOPkGg5K5seke)hArud@t^Nkxy^ z__Afh;@a3Yx=4>GqugpkIE#sg`#>9|YZ39+2(hiVRfp&?Bcd(y&jO-YE40n1d_FPH z=wh4e*LlQyoBZ20f0#>z_xQHeyiz0HarJ6j_*j+r$@@^-;@h){Ll<4!8i_NBP6Vg6 zJy)g)-|pD9o%T}@9G+RVSstAt3}$U>t8$hR-hbQFHpgm$5M8^jO=&t#h-@=%`(!Xm zh+*ruEto$-_#n}3Tdx!ncykuCNrZfYv)VKTcdzj=`0Vx^$IE@u-&E)!Iz zFa3l9?-A;&)Lz2F;34YAI2Pd+JV3pQbQ7LFU{VKzI|&u9=u|y#20`UZD|KpLJHfxA zk(#uljnF}^qxP?)5U%u9Qn^|!gk|F;)QqWS0&C7U>cYWBLdDWt>P|`np=3igbz#LH z0?9g)`p=U%?U735Jgp(PoO@2~jjkem41Y{b45=inzx{wJ^C~A)JikrVwJ#%teTx<3eO$Pv`{if@E9{h`#C?5_m7iHlVG=6phgMgTSSdoH2M=rlDqEr+n# z`~;P7=My2<=`eLXG@Iag(v7;_>pej&#F?sNlSN4fHY+o_tO zG{Q*9W@-cV6=4g>glbokOt{&fu zVQ~YCqIn^Pkj-LHiuXqmPDv;fBU6m9Mzfh>se%0eSoJX7I*Q$zguK`b3?NLUl z`WQ(#8Tg%25F1W-59Lw3FJC7teDsm>)%7aj`MbB28q+I;oj=nk57aLc#FQ5lb?wSjPqFM2jRT+VVs%3X6#~-L(i8mg}X-a z9P=i`#RpS}q!WZ)S%H*OpN16L6To6da*g+jZ9U+!j?mcG*$Rx-5N0deS}%)N z5{@n5Xy0|GCoyw%ci8R31*kJj8JdW7g#1+7f3E&*5c zxwX1mf*yH>x4+Jrpeo7TK@T7-$YDXm4@H3_HIK5dOu)gaLJCbV+f)Ckvn@3$^| zuS!@$xY;^Fm`xZ<#9D73m`PxMA+(a0P2<@OVXZA(IbMA*r1jp9N&G&QpjOFUDL&2k zTo{`mNh0I`E?} zbz2jE(eceiTCLe}G<;o~dMn{170(!()hb`ril4hk(PAMW;g6Y5w5(ZE#nzq z@V`{jS`sdO#y6~a(bBu+BVOc`*uooqk2gOb*Ycq#3m<>$PKyzmiC4>tZgH_s$EVc7 zEvBlk@dr7PEfv3C;SJQUwP-y^#;ceHx9E7jz-zb$wlwHG!*9HNrezQ13I5W9lP%|- zKE_vlKGI@)G6BD<*}a9dEFRw=+SjtIJfRnSE8cxnV zup8g8G?aX7h86yu?M3pJZx;B3K!0*Y$aZ|veP8mORp$8bxn5+|_APix+adDqxJ~#Y z3Rm)4hYk3K)z0Kvi3#4%)sDR4<68Wp>$}MReCWN;wv)vRSK^y~ZYGD;F2~abOvtZ^ zhIqN=D)QY;`gpq?hGY|_9zM-y2^oE~7;kVxn|#l45xy{6gX})8jlbNYLaxcu!rM(M zN#iFp@n)-Jq)v4Wyp8K9iTFbe9~34a{k^1$|MHSUYFjoNzo@E*^z6?Je9}+{NsFk& z?a*x_S+AGlMAjtIN}3G!=X^b>^wtEfJieNwwPPID^8F`iNv{|;tEY%WeJH{m(kLLg z*$8pP+dq@=ydj*!>35`4&$u|w?Kh+`M-DDKH<{!l>c`zmwFa2cC}NZZ8C zxY(2DNN@wI=jUrn zIv!t+TYT4wRA*6!;}mQoi8_mM?aWOi(v2eAz&sPug$>_u+Eyz`Ur7Zx??3}m5iSo` zp0Jn{X7~l?Shj%FU-=2w&z(z}AC!&DSfWDW&wG!Ha#S|QcSRCs@QM29QdpNtK{O0B2+qjadPt9K+-^3jkXEo2< z9)p{|@=dc!E5P-6CO4Odp*R|r)NH;G#&JJCZ1&D0;FfmXYqmOs!=2Z>+1xA)$C3A7 z&4zK;ai=a5nvFMJ#m!6(Ywq|Rf~&0$X+C%%824fFLNjjmMO^lVbIo3_&*T1_@@W=W z2jJ$!9&g@5_rskl@oe53c?QQAI?ycF_QhQ{bZWl($s4!spl$Q>{U>mfs8utu_ZV&{ zXIrxldIUGg+|=x+cL=v$$E5i}-a%Z1!^-B>Zf>~laD(P&{Vuo*Zx=WJLigb`X$zV& zmpI`_>Ke^9U+i%OyH%Rw_S@kKLX=HUnAW(KRB6)@{BE2!S={tn%L;dSwxDV3tp#qt zg45J)y&Z>M>}d*X-HO|u+|g8hX$wxhiQ3dSy%9GxgVgjO$rPu#qrPeOMiZQMP<4}e z#TwlGmp_~Ij<3Q^G!``#a97}>XBITg!HjSlEj~BtEHuE0FTQJPeY+Ibp7N&2eb*9P z7b&?3`MU@=L-lD>z*!xf!>)v;nPM$m`jz`lCvIxujMHy61uoIRm9=3_>))&4i1Ua| z8M{<*NB4#|QR`>n+#|0vmHW)V1!M;``SBHzFPP_=ijb*Dfv#^;ou(|(&(*6bE=3Y4 z28Wvd-9M3D=-RZmWF+$XkWxfIl4u;_OSPTUnxZ> zDn}|EDunE5cdgyE)~>aSWwDM*DR&6zRw;^l-~NKS*i8i%{$iAunK3qY*rWRSY5lHHvigP z$=XIUHh->CvpD?P=IkToEYAUL^UO8{>yy2z*%2sb=}yU;zYLVHO47v5=kdj?s#;#N zW=zQX@~5C#aaO?c*`3pj`O9SqY4@62lh~|1MK_y2n>}W|d6U{)cQcPwydt?dbXhLz zenfop!|aEwf?F}oSuXckjZMtvZ(MRq-THgyMytp#ddp}8*5`( zH&1&s!voK=w%*v%EU7=s`ea<+Tz2>jt7+bzDE)p&44^SdK7*6>B!W?LhfwX(vh zdFlv}6*sZ4`F?A8CtGTIg`w14L-O$us ze3TVxQ{80TaF~S)sc52e16a8?6irW7`mw&YNSa1+4zN(>MNM*BAJ*hic9UnO7fYD( zs43dqlNHx+zlnHd7mGIkc9ZQ)57wo?>rJsS?yS<}t4;U6ZDGx;OKc(%H?hu|#5PU5 zabubKM>p*SuVbk$)0%d^Sj|e+6Pn&0b7h^MgKj#dcV?yeL7P~6SFkEB1Db-Q4y=W> zr<-1{vtwN_32JhCw3M|l;BeE1B{r;zXV!Ha#rcEGWJ0@fp;bS#O#H;?lGw|f|FzNhd8~_h&ZE}If^{$# zoYNYmPuiL4igF{*=Q%TdhTIq`e#*S)CpM~=w=!>DC&*u*y(bUxzEzcxcl05=J{|tF4@ zPjetlK1JHt`4_|tEf+REgaMc-&8xgqRaW4+#&>737KtZ?1W-1ULf zh)winl6PSnn_hb|4TS&d#K>X8{u1-%#x#x*X5g- z^lAS_zr`Dvw+`=bl#$jkpWX3n>}*)g+%d4Dv3#{FQ?YqVB}J8txIkF;;Tw8`e~RVXPRhZXnx!VtDy!8p!1LjF`-_hBf-P zjIM!_hI@9y46wVfp^7}nn32e7cwF@@B^kUi=x8au?tkq8#D`jyFGc8&e&t{)%;6aUy!qbd~d9r%OJvOPq$)t`U z{DEos99F{^2!uDB<>?rn_dyNilNyHnU08$ch?;TIE4TsuP{}aAezf7~`%=b-KL3XC zy)wqfZTlOZrb-x=mpvOWT_VQm_8kp!w<3mW-IfORIUd9J{Q8ENdN$)jvunfGrH>g( z=M@brQF#nD!?wXpmcuBmvuY5{c*q#GGjEu8B8#zyG_S$o;T?upH?v`Q0yvT5b zJ+I&I7t7F>w$!Iwk71-QXsAzr70oycsi{A_lEp}pYw9ZrbcWniS^q&!Va$a{>z_>% z8Rz7}dRhRUVX=T)-*6qnsDtF!ceW!Ld8H5Q3s=Ay*=Bd^|9Mj?*o}Ia2*mhRmQo+~ zJ(2;oNUEQ`H=HqmyjYJ-IL)}GK39Lm5X=a%V%9^pq|d! z$w-ggTYpKpo$=&_NB!~NTNxgkx7N3MZ)Rwc-Rc*_Z(v~hR@MKlTF2P2+o@hSdkw?& zrd_?2zbnJzoprr?vNHpB(4u~U!I7cOo?riPo&#g|k6HCYfwqk2LDPn}SC%kt@qZfF z1}g?*_E&@bJWIwI@CU=80CPrm*|1@2(gMcN;(o)Ent6tjE;Jg_)Km2EmwH3P#3Y^St~Ka9e$tE5%MDcece?4Q%+MhoqhIqA8-Bn0 zMBkXlGqkVy@V}B$V8Fvi>0RMDhO(St`iShFq4L!reTn5QL#%Z_9Yahr{5alA@2XEW zth?Gpr>{;hSXaNIZ%90EDEs|_KEID;u<>Z4&-bDlHjtmt-R|QJzd6lx$`7RBQePwe z8LaAf7M`R%+?(jfV^iepJvut~+RWw^2o3d&S#u z2~kGBJhaQueqT2G2!4M2;0I-qBPA=)>W{?*IGaQw_ex;Xo9T@OEto<22Mx4P#JJp=T;Zmne| zy|m&}-JtIc`tPxSQE5j(EXi}t;$GdD}3$3J>jhw)0JpPSKK z7el&8zXLPW1?FC$Kd-K;Yi>D5-?gfu&iwBgx+Y0cXR?J!$BanoluVYz(?EK&O?Vx2hadgv+2A?^yWQ&9SJb5_-5irna)vz_Xex38raVD0K4e^$}A zv{=^x*Q})XZMUdfe8Pz?y+6M$p0%7V_&ckPpKV94MNQYH)hwmYY5G~a?wvIqLt^(YxvsQf6m3D2XkvPHV@O-MOn4+CkJVGo6K4_`fJ+h*!0?r%pMwS_)4uv-bu?0 zN~}$K@sc*GyimLB$8#EDWppik=`-4lG+HfYXDh9GoKU+atck{lplcto8fdZxXzjDx zb+m!)z*?=WhPER&v=;SDM=P3tvbOe%h8Dm$Qrl;trkV8m)yg(1X`_dHY7ZPKrH#q< z)Lz9%X^u`iYEv#3(?}_sYyIz7`pxeaydQCkvdRUt3*+Q2y41zoGY4RW3a z+}xC0ze zXlJ%R*5@om(qam7^j;fbw8x9H^tTU0(Z0mr(sRRrH29Y^J(CbYn}l4^|GF4TleZ@5 z_udYn-S)Yl-^mN2Wfh;%zgHilRXfr2fY!q_%Nqp!<$(a&r5R{FX8a({fd6X~Q12diQ>NS|ZO% z|L5~Eny-Vo{_-Ci+PdrW^tB7EXxnGb((CLO(csLf8rHgnw6c*OHE%pjY1@EfH5Lcw z(w?-uulX7@n|9lGxaJ0E1}#?cx@HtRO-*&{s+nT`qE_aJWcWUO9 z#+qCA#;7}|^flKDK2fKs+8Te+d+NKP@|x1Jx6~i(zb8p-wwYQiB{jbTqY z^{p0IbKgfnW$p^AS?w>Qt|>lQLpUO#POUjwLkbd6Cv*L4)}0nm9hU8{c@)8=!ZSQ; zT0w=>)_EQ^Dri0x7Qdwiip-_jO|GxeVIER{(pJ@U;j^fd?^e{5knT`dBJFApP;XJG zJ=Qg;^bG2oFpHWS%rt83lle6#&s?K=9hqIz7@bUY)=yXe^CjK(O;mq67f%H!zgB0( z#8QjhKUPo2#8BNtBh|~#M^lY!2daO>FsU~Sx~o%SXw*2zm(?BT$kdFir`3aJ2~>l1 zQ#CglOI?*wSH0#8ippJ3RSjjrsV9@w)uD6<)oGTZdJYvtwTY8dlSq-&&A$ZIxA0+9 z@)>qD4Reb6{OhA?GvrAsl=7e&3O!D>`f$6N0y;t+#b#9Ri3p^Q3|*_PJmp7SfVf;e zec}N1^y|3liNpJ-HQ;mABEP-Vh%QF8qt9-tbtJhuaE}Ldyd7J;X}ddh>NKLddE*x9 z`ZjR&x-}cA7lI?I_c^Vnj<<$XTiC9l-Z^o+`hle@70?`5{d&GLHQ< zI%mR;nsH=Twau5M)DI2Yssl!>sno+8tKEAosrLWBayy@!Q{NqOsrE81p!U~0R7Y0L zqfQ@MTD`4o4t0NnWwl;7lgdAAR&7=AhqAlTq}t)$Z_39bGpc)2CnycZUsd4vaZ2N{ z@v3{wuas~9Pcu@npD71|-c{`deV{1*pZ>9fMk&D|eN~OV!xXFM9aTjhgOth8=T!mg zUQ_11YN^V$@1b}B8mhz#J1O_NYpP=Yv{P&$l~pspv{AJE$|}G9CzN!gtm?qCW=g_{ zsOndBBPAQpt0Kt^l-`d8RoRdA6n|Py)jwPG`S*KOZkH-4SI^$6N};PMh^e%yLYR_* zioa47bF!3@J}0rt%tuP;zIvf5d{Z$c#5}qR;vl4ax=E{YG38SvONmvvKiHJ}57AXG z2MZ{CXIPc-$ss;-m~iC!4%596CPEn%~vS1Uu>!JwYyBY19YoOo}EAm8dz0z`C}|)3(l!( z-^&=v&M$UVGF>zU8EsSbhR>uZ|5#MD-l9=~A`_1DrCr>61=63qm=hc&n=z1yY{x8`LE}iJ&AKdUUhPLMf1wuXOu! zLMYIVXS&^&f+$zu&ARv4W0dyy1|8tUVaicfweHgP0LsXp3LVb&Af@PPna*_DhjPbC zszddAQ8?K`U2N?hO5Yl;E{MOAvacjx*PFJTQoA=>x0bq2f=Bk0^LMDa*7#)7xD5F+2+V9omT#y z?DA@buK(s+av0i9S4kcsOTSy|!jBG+cV4p43D@?K`xl$)DrR?+WqGr8SNmR(MO*%8 zE!8i`EtM16Q+J<{m!0^g4WYG?ul9V@njdQ-JCojOFRf`H_e~9GOJ~%P>(Y9(1)bI8 z7t3F1kIJ=VGto1xB)x)+^KRBYMVFI5H5;@d9|iegRJGRMRz{|NuF&59QcNbsmuY$R zLh_BpQY|BoPwp-dYJWv@$U!@}TJNC8#dmjAs*j)*v;z56_w9QmHA-NL^_ zPKYCDFU7`_pDjjfGlOHvN7zs;WOWSr-EN?EWa122+7znY(8M4YKu>Dj9#P4v??<%5 zG!psORevqm4^M_U?$_Q}iXo4ccxwMgUdX%v53QRDO1|2)MSC+9OwORXY2_dQS!=Rd zo4F~Ry!4@ycJrT8-Ke2cE!4pgWB6FE03%t&-nl3K+9HOJ6`f(U?;?!+Re2CL*hH zV(uLBpQ&4w!Y4Dxx9+A_E`Kmh3fg+L@(|(|$)ho`a_h#QBwu7~<@4{~NN4{220RO)O-NJCh7<>Kx^((r6>rPJfrq(zUyD@SoXB&cUd zC1qCTX?RA%QQQf66oxVjn3uxEGXfjCmC!c6|v1z2iETbmV`x+^1cb#U> zbQ0<7OPwaCB9T-Ut=3eWzep-vrqE=0ULdK^lW*m=AS3MwK7Q){U(Z328q{5@_;1F z%<~!!D1x;AF-sF+8%px^r)uijf=Q$iyyolm6QrtZC{5?#qa>e=P)*#NL!_Y=fTpj~ zk5ozv)l8o~KoZ%U)Vy@xM`|rQq9K3qB-sP~HC60gr0aitG*6>;kTw>0YI2utBYpMv z(5!v3i8L^}MMJ*oM*5xZrlIa%OY(MKt=T%^O5(LUX@tejB=7U~nm1@i(r>3FnodW1 z(tv)EChhrB(pTI9&F>Uz(#Az5nl%S3Ng49L6^ni@Bsl=q^EzsS1f_gB}v$y zD|RfKO)5Y7u3}NsU*h|*Hx=CYDPq9?D8|%|NuqIIXNCFbIPu)j^NQ~5uf&sStreJ) zpNYZS8!L)ue;}Uk)K|zA|4WJq+6oqKh-tKP9s59#mlcTZsPEw<|1vG!hpPGAhn+48&PBDHT~^ zdZLr&az*sqDk2JfvBFxRA+|4ysUV_ML`pfcBGIOdxE(>M2(6J3oz3wTZ)g(Yt}YVC{9--t$$410Sl_AYkx#^Sa_tO=2A9sW0_w?+}8U< z4BV&UNB13KleuSw+qGLnVEK-Uf0np4YD_PrCY_$w5!BfnpG8$T}i~mlCYMY8fyUr6|kQY^;`lE?5hXoZrsZ64(eon>99W>$x)?f98UJ^0T z^_SZF3ZB^X?z8&dD+Dog<2&{1cqlQV^No6V9hjJOwNK4|5=rdY*{OCr z8%B&8dalMeogyx{-KvJy1rhsv8`butW5m8Oy*k7CFmZmqR$W!@PXwJ*sY@Wf#LmBR zHQ2<5m{?q_HVF0-PeTOi&q2G1Cl|5RZQpkgqqUFJtoz%D2Fe5VbMMVWU*|jOFa2)B zktZ4I#-z1GMM8=ix_%W=;+~|IH#rmA1~01XD2_yzJ2C1zR`$gE0W7sk=~ANC1VxPx zw~j7agZLW9*dhrytMkHTHy4TaN^Yw zwTtdI;b5x2IutrVK@r^xUfCcaGy^EUBp&(TJJkT%EAq5X6y(d zR<~MhyZj9yo9V1RuX;^*v(7>NAfks5-m^p<{iB00e$!HIb-SIQ2{2RRx3v)@zfIKf zEvP2bli#c6c2^SmyoOcj(Q3lf z*Vn3lj{HG>m#R%9CzL|kRkse65JHwdRV^A65$v0ds>87Y!otgSssqcog!Ox?R6iw; z3DmD@75+#bVUVv-Jsiv?#KTHdDHrY&4%rD+JD1!gcs}K*@v+eJqaq`r!j=*cQ2^!W1DKs|csi1k0}=)sDAtLb5PiRdE4A zSc3^s&0Gxn|Etk))ogYI;ca)IO20dluprA<<=YfY2s`Dix(GQzXtCI>I`{Pmf!64* z+L{zd*q6LX#aZS@*yX!U)xqCS0RCC2GVb*z2vm-$nC3l%RnfMpk*J-7hV9lWt1s?^ z`(MmezvH(M?uh2A@)vI;sPVH^a|_lH%-8)XU+2D>kTNt;KEK+9;QshqIX8F(VJ_@b z`Rsms!W^g3a!2Yi!sedA^6@{`gi8;5%Tv=W39|tm<$Vt3gksz0;HmcU<+HHQ@Y7u}<)ZczrhfbbiB)GNITBJfg8jq>x#P&_KBQVDw;jQ2ZU zuDs=X0w1(Qu1t7*1fSd^R&I6;#E-K1$_E7p@n^|}O1;Z|{Ptasl%hN@y#0&^%F|AJ z@S7TLE6Z~{@T6NA${q)I{3~FJQg?qdp0YYg30t-S|39&MT&{@!JA_>0p@h+8Hza zbBkc*!?Ahz;Lf8;B5@A>7dt>XH9P~~N;{zZ*N=GW?WGLwn#BDz-KBI5{eg>Y-=-9` ze8s&k*r@yw_!*Z;S*!e`dyk`gtyJpwyv4svLr3|Vj4BR>_cJF%mztz3Z%4S8N>*et{Sc4;j;`?wg_GS*Nw zx=e^`uF{v;rSWhRH??K+X0UO=a8+3;BOll9URvfdl7qW4TT*rm@BoK;E-3S8zKf%> z*=4;xnKYV{i+1Tqv6|p26|wMwbD-7&v+dt?aCjg2M@kWueQ7xU`FyvawVwt}6sy zcI-D27qJFhhQh;eGk=Ab?dt&JUNwi5wFd%lUHQk$HYvhzW@iqS`K~&J!yGwSw(M3A zZfwQAvZB97aolga%l;4#;Zp0jmsxiD;U4B}F6$3CfO|z>Uq+L8<9rXTD$_Z6;yN6i z%34x);&Q*)l|B6Fj=SDqQ??GV1t)y8sEpCF0r!)&pe%0BIvnMgN!g*oRX7{h8D&o` zTyVpazZ7=o9C1TW#ufkCAy&LEijiYWafFNS6-0#EuvY5S`cv6JK23w9cX8u}HR z^|ee9FiI6?HowP4vPFt-w@0wkaXiK5--Fneh{uZcu-DjT_guxBx^C>`!utyF z#tv-ANT%ZM%@^2?s_Tl3A5XFA+1C^Sz!oey`m#c!ZNy#(xv2Q&YQQQt#VAIv)L>mq zS&H2ETCDO7MPVIOfxV!^D*~lTEGZkM@LW=gO*;!!e2gx^zB&z5KsrU(;B8@w8(sqJ zgn6(cA(w+~es@%{ZN_74iy=Uf4||0DQ+Pn}wE7_ynCPX@x@KXAAiEUg%eS#P-tLO- zH#e|}4x1FF{^{5|lWP?}3a???U#?UX%t^-jDI66R$V6=4ZCk~jnm8<&CzbxuqvcHe>DU3Q9{BY{35I<&-{0ti@WTWtEmyxMELHGD{GKKj!|`U8RGodolhL_tKhkotPD2n@Zu$?U*&*>q@Jf z+c3aYuBH8qR*cqcMX9dNhzb5?TMDtO$5?e)msS$=m>D$|r9B!Q#<9q>RI^Bf!Dh}W z1;NTO{pbIGP)bWN*O0&DowKDF$nkNx>a-Yx*!e{s$rfPlIK7uE$2piE^M~cH{2ybI zzP^^1-FbxZ?e3C?4?VHKxuj!6lxn$x zat#v?(8$|0Nti@`rM%265hL3wlZQvfVXT&mu7Y^6#-nFyR&$`M+imbqXfGu=pTG`3@w14e-Hi z=?Isb6z;`5H-yOFeb|NJDUQo;cDoNZy#H0Fh}PK{T*qAbC7T(T-;Fcnl*lQxx?)P^kUN1Eh=0ni z417m7td%(@w4xU}>txTWjp!{lYMK9>dUV2kh3uTa z9zAPXA|oa1(9*FYnTw$UeRG&2yEm^Ko!6BwYYr?$_dLm#)m$k-AFjJ6J8ux7ht#)Z z-{uO?l9F`Uh5!y)z`ZJ4l~jOk%ef@$t;t1ixE&{pob?bbO*tpKv;Q6%m%x}|V z2=!5D|Ap&ivROd%n8_;Hzg|?+-xac?GpEq)lXfyoNf6rdyNwJudK7)`(;^vWd_NJ40sG_$^&IXAk=1iyzW&dp*$YPsXH4jBV(&rVr9r zf=y^z{fP8K|9W(?en47fy9V8;>yd^9twitBypoENR-gyU+oZK>dvvLyMVdRd6s?ps zNO!NbM!%EjrJ0~b=wo87wD_hOy0=IrO{<%Se#9@8y8WJwzQL79uWgxuE@2l*`G_gh ztU``7_1*+3u^?Z%$@m@Ro}Vqf`R5C2ao#;?>9&t3mq)jx50RrNXl}aH_udeyHRq~S z(9n+}taRIp?G}NIMFf!<4q)c!sLWp-AUcx1dhv;-%ldHlnN^ zp`?#p4XD45pwcC$Yfz5)KxyD*Eec-{CfzGnqedPFOUDMwP`BB~q!?>CipC9;KJt~I z;`qMOESeCdF7lR!CS8e6M5&(4m2S8dhuZaG zru2s<1~t?%RgyS*236hrv!vCAfqF9dwWQaFg0dL>SR%#~P!~SEE%CX7LD_#FEcw?8 z8=dSe;f_L3BY!(eVy!`_rE_1D*my^vSPP$&kkF@5bF7UeS29kbYV7Jt5XxgHnR8Xi z%>F~DwzU-{5L17Y>z1;T_-zMJg*&As@JMe|=sr=2Nx~k~&H!Esf#-n=Jn^{XX6rW8 zwXochb3Znren;IeadmV<|7)Ho)T1*c)|Cp#b4x- zHgJh;=Wpb6Pee)9^iSlH(NiTI&i|9`-%pfuAN+!R`S);19{K|^!OXv8&9%2k;IjQC zj@=l6%$-Ea;$gnJnlK$@+kQ>D;bBYO4QA zeuYSp`=9=jbkoGh@xF1%#Tx=-=cg}{H)0O*%k+E6!sY_xF7pw|_`6)Bc=^Ep1k^)h z*v1}-`I>vkEncrAUI#Ogdych9HbFCxOi+vD^@UXAYhr^W^!^p(g;>2Lt@IM|$aSqG z>FGt}p+_o-&&Tt~Xi2H0V*Xj=%PNWFw<{BgZ7Y&Y?V}>yhB%UcojAvz`4T@S7J0xl zN0N3OiM;EOCAq_cA{{noN}$yse;egPbo99g##d4=jH*}ZQCGAP+c^7fQH z@^H4N1b|zLWJoj%JhEWN>7nWwBJJ_~;$O7RwwWT$V4>_k(^4foFo*@HO}kpFwcl=N@$yYLaj z8RM^FPy8Ul<;{5U@e6&3KT}_dS6=TzEL{4bSoP>7;@FmvVw;jSgyzsd@wVz#1O(nw zY}sZ+Y`^fTxMa|P*nPLHc**w~1Vz$PymyWc@v^a@c$G~Bf;OZtZgo{6yk_W%y|>E| zdmPloBwq;vvr|zF4HhB{!6n5@pgcqbNm!gtE<`w7;}#n(;pr{;!YQTKMY2E&j~8-ITeXOYmOABfI|^xJ^sa$=wL+u)c)cP)Z>WJKJp|klWt{E^#4Db3Reluc<@BxmB8$OsI8sgrFX=5`HNdI@e*Szd=Pn{!Hh(jo<}*mOdC&ny{!CH$~Be|{o7HNj6zHi?5*75Rw&%#4Ar zZ}$|3{9(cMGj@vq^&xL<*d{*sg9N`Bwo%+ahJ))9){1>UqTuUAE5+!yFu3lOqxi%i z7@ji6PCU^Q2~XZ?BSyapg_nXBiL;&s!G!4QzelRnd6sYuHlxCDE~(ZrIM@I1yU$ z3UNTfGb}vP9}&f+Jwj z<mw13>w6)n2rQb_oW;ED>2jF2byGEk!lQ&cl8`HxuphjD{^+I8Q`f%YdN|&Jz7=gT9TK z7H*tLfaOXjgp!YF*p+wRgcBWb*yEL-g|q9TU|#|6gl#1N7%Ou~h{*|qZD@Keth^cm zvoYxwb}~-Dw(ff=R7D+u#YaCAf)5A4W|uSzYq$Ht%HP!szc}uLJzk|3zMkg^(?w~8 znPVO>%lj&!S=Tn$?Y2^3pnenVs6~k|K(rp_aabr^aCbHA)Mc*lR-6m0P+K7EMLWXQ z|IQJ9I$;Ov-+5nHy>khynSNUcT(KDTL7X8hGckwld!HhF^U!W`R;e=ave}G!PKnm%OZ=u_* zp~ADX-axMf1BC}i`k+=f!h}zaUC`E+VBspsOQ_ELxNz_7Ht3sUhlI<{wnDwq4hqYF zMySEKPw3!dfL<~46dqhz1C2TAA>3-Bh32Jh750y)pudb8gkg;e=+%X5g&9IA^vLm* z!u0E6=>F@D!jn`16xV7id>PDv)>+yJS8gwWhJ`E=ZnMdSI^13$G#S4SwQe^N=DfHA z^|75P{8f4r`Uo&pDRJXlTR}8uB}hz@ioT!S3}rk?DY|sZ z4LZCmxu|{98fZEsq3F}Rl~64ALQ!MCBQ*MRbP+*q2UYK46g|DY1nM47E}9}OhW6Iu ziarFGLn{}fit?OHq0a!&BD;w>Q2Rn)QTUS?(0d=liXwSakVCsdid^C+Ae$177m32Z zLjsJ4ivDc=0?AzBS7bf+17r!*r|47n2*fDxEJ~LRLQ2OyioRa!gFN5At;hk|1zDT6 zvB-4iONjX8+M)`xHVEF;wP<^P3j{z}QAAZVLgLhRMfB7<$jf<4igrV*A;{B~Mfx3; zkk$ESMK-1?h{LD3MeBP?Apv`570oFrffQby7CgQzg6wLa5X_64LiNRUw^m?WbikmY;w+NGcTkYXYy(J`yOqBOy(e4+V)up^#$uUBTj*V2D9} zQ-C^j9AZ5$U2t*fVaV;stAeOEevl)=OM+R_{g54h;{=3@UXW8EF@gujc0+h61-mO1o@s5DPRuRLsVZ+ z3!47F(dB_B1@F&VK?bvr3R(_YKn{Hk5JX!nfb<9Y3Wi^qK#Fs`1@@0;LQ1~v7Fd&} zqec(!5Io&E85NedMG!h;JnH8UH^HNZFHtSW*9gS7K16jCx(E`1Z=>v|mJ61zdJ~m# z%2sgxLtm6xps2dyOZ=gW z5m8GmF7hk)pN`5V#_<33pu>$Ues$H+s6aOw|6@X66!997-+SO-l;JIge|x4+RKy_! z-?GXx%8?hvKNY_-%5FY@5A<=5I*bkFum7_tN>YE4uc=rcb#(nP{<8C{qn4)x@^|iW ziE@4K%U}L;c@*T>K7PI2HtMNp4}TBcChF`W4?b;+WmG6_E1&$qEDF=Mf$z?r7gg-B zmaj(5j@p>Dl5e*1FSzfQBj36A7uW!{<4@iH0Up-b@N+}Ig7>VlBsNu1f<%5qFDS6c`+2E&EavnP=3w%AMn0LbK zHaLDjz|(xq0P~J;c;9%b;JLDV-sh+*;QJ0ayb_yBV8rDt-k!!dFydn-@9M=Ea8_6b zFK5RY@ElzV@7yR2%wC_&bI2uuFJvb0E`{L0Dbp8t(zz&bGv+LhtAc_9o-ufEG6?*` zi^6;35&`bw;(421oC5!_Li6@s4FVsEgYhi)9tF3Kf_TD@0pRq|2%bfrFF3yH6z^XP zT(BvKw`Ptfc)^1syslCYaNgViUN~kOn8-N5dtkc>On&Xfd)%-N%sIZBM~_(rwoz~A znQm|fm#^ExLv=ZTGw-_buB9#m7tUG3qwlo_zo)zKT;E%OasA7A4<0N4FF$F^dwF;+ zc&^r(*F7;4yk_$v9+x`}x{$Mgw>xYSG~awK@5Y>QknzGyUa|BGNdIAqdk6Xf^bIt@ zJz((`6xsZZD_0MK#=SptKVthp2Jt)Y$0c2$Cr-oM(&~25qMQ9(U&=GkW_Yfi) z;tK9 z`EpHSJV9);ecZGaJ3)rad$?WI+dxi#c5uI-H-W^_Te<%_@XWCdT&j2#h)P(??Fx1V zJsw)gH6M2XnL}4_=VmPfi97AMb)MFs9BKw`a&G1n zjMM{*a_c$&4;6t>M?L4uDjo1>ww80SMhzr8s5xL*8L<9=g0t_h6c}kQ<&0#Dfi4e3 zoN!M8(Aoa~YxpG_81|r$lg`Ws>h1G5rx)h{u@4_|21HpvzvcHhyN=ujhUeVkoF2{q z=C8QU*^`(GT$y)`Gvs&$*y)nQi6~D5Ha?E$WS))#ep!8ibNBN(;0azd2b#hH4!SWo zUsut95)qkmOiKjHw&FRYNG$M^48;lkh5$l$!8mi%A;1M{5GQU85cqyy1V^I{1J15F z#nDHE07C+UIGJO|fgQ#p9JiFiziPIibF(DC(dPVl>3 zz;e_MPD{deVCwrV9BaERz`L{!9A}9e@a4}nobLf^fG6Wta&Gjv0B4%4;CyE|0!LHr zIL-^~fb*@FaBT8yfRG24oK_D@;3t=boDicKP|lyn$$`!TmTa5Nk&Mp*4wwI7r>6V? zg!ukqZ+7|x_|Z7d&XSD-o}C(FHwKOYhPpqnYr8%GwxHj#uTb6sNd~Xsq6?T6;M!3U{CoF0bU^( zHm(^1STq1<=Kv4@J9-rR!AKMUI19jrFadxUw?f$;W`qH*x(2g-(}MwY`7t)s?l|DK z{~>k&`w-w$`$6{jRzJW+tPh(|;R87Q%adIcxEF9VZ6{m$Y$qUTg*!VD><;)T*~GSg zy9tnga6S7xeLdh(`zm(f)G9y@&Y68D*%|P8%7GnZxg2or#xnNP`^x}(S6Q!1Jk}RZ!Vx=U~iz_Oe_7X-O+|MsuQpJr->?kb!;rBT57d@{quRb@j zXkm7t)v*VWnVfrt$6N12%J*j$o(#DeY0-7P(D6lDWF9M}P#S(U5^tGYXxVuwl2nvX zxD#|Sk{1wLxTZHI(qZ6iVK3y&|K$y4A*7!cDYT;&^5LY&hEhUd#UM6vMF^%a3yF*r ze)^B0GyR8xivn;dRHA*8NNl~Ij zky1#Oq=d9ldHW0Q{oQjv+;h%7&l6h=9@rV4%8V{9-}7Ji;Vluxy#v(nvip?co;}3y zHF1RE(g95P-C3AopFPNMqXtnd=!b>h0>g?c;~?RSy8?=JeV}kfCa9Pa;~gHo+PnC9 zk6U=e4Y%So(L2Jq)E&i6Z=Ayad~+%`iEs!viXDoLFKxqfJvSCxQEbBH?KZ{GwpHQ7 z>8p$Vam&IFuUuX{x5X;l{l=nVA!0%JjxdYjk$a}$|E$r)3j=3|w5NI$rx4w)^BaW1`EKuq$@s#;o#>VZQf28Ho;qVN>xRj9<0y!oDu(H%3{% z4Rg5IW8{fC!+3-)Bg^VVn8&vcBeCd7*kXB`@!jl4VGe%(a1z;#VQKFk8vmQD51THy zZ-gh^3ai;#Z~Qe-6?XMWtuZ6|TG&8ZmGM@`r7*npHDe3*T-ev!my9KiXTqNDIcG%p z8^Q)HN{v@5)nOi248~z+d00)D#yDgYg&mub8!uV&!qU%(jSxOF>@0?FRG1frE&IkY z)*a6at5Ovi&wV`}CWhr3V-qsN&VR}=_I0O)O^dRP&gA5Kb-{M*n>2^eX2bVAm9*E> z_YKsx3fjX9^@fxF=V=o=Zy8d{OKIe#Hw}Q5M%viDYlf;^4ekDs3d4fWa@zB)=M4^F zVwz2NsbN6_kEY=p4b|IOv~alA;4UkqVSgzM878M_$1g|>`3FwW24Vz;|2i^hg)2FR z-vQ~gxJPuuzOrQ6(US!R_0j{hCeK`hIy;_*8#!i(?~kP|(H}KTp`&S*v@}ClWjHO! zGTCr)9ffwKA<=NS08jfbE8gJp8AbC4#2G5dA+&#~ox!XYO1rF$FxYPLrv=ie22%!* zX0eE9s2ua4Eo#CTcFS@gE!oevuQIeZ46?d(d}qE%fN=I(RH-^SRcb) z@*3LvwH^lb&E>T0b{B(Y{bCx1yUmbr%7PY-+-#T`GNWndY%=Ubo6t7Ytv4_#{!m{X zwKkks{)^h`zS7`#bdowfy2Q}b^@SQ+ZfUR%7@^MHJKq2_3{rbHni@8m_EEpRon?3t z|CS0@{MHkiJE@PUKlO6w7gWKrN&Pv_6Ds%V7k$xKGqs65qIV%SQhiWEdi~XUYX7|V z`nSt(QJWjP_5JBp)ZzTs`pS;0)S#daJ>L5g_2uj~{S9e3wd78#e&|OD^+L`={d=08 zI_7_0fA)rodf@LJJ#dwbYFAgQ7i9>k%T843Z?JH+LNVvU;HtuOQ2CtzIcRs%tWjAU6@LpdrzVNm~fEVR3OpsX-c3rgb4KI_Is#P z^EvwJ++Ebf7P?;C{U3EDw?Gd9(WujeT>UvIk-B!pasA*|3^l#;sQwcUNu94s)7PGZ zQ9E}g>%+_;)OVW>=<8xZRQnI{`Y*SbpBceN)~BYTjwA{^lENYBV}jpW(HVn!Yqx|ChUjdcQMJj~`x0C20Nh2ch$* ztM&r*H02!Xs_mZo1(Sa%gh^LD9X&;9s&Ur06@Q~-oZ6xv`aMR8LD}mY$)6|%%WU;2 z=Z7f$U2FA&bKX-<6tB{6{;!)tOj@RQyYh+>lmxpHhRo5R; zJ_}6rxP?uW!N|WlLhN0N_2wzvhN@c>`uI0pmE}!}TkW`RUEDRwio(x2bk!w_2XR;z zYNU)NJcuf5UzTA-%zQ*F4odHRDna z4?fa`MKCCPuQur}TqvN3Pd4aUX5~`;Vs7iMla5ggYio1|&K#lS4qw-O{&|?9ym3Vb zL>;7jDY&R3s1qnB$mKeZFS{v-O=om{kX;nagkBdZ_>aP_SL^iesT6a*TzA=nNU7Z= z*0BpPlnbtWoks_P(m9K*D|LiX{GS!+`ZEG3-THjpXrnKs`tV8J-IZRHXF>m(ReJ#x zyA?-uk1L%imj+XHrlwmc8C8dL^T?YhM;VE_4#RrN^~iYLq47189WHUY7Xd3M?`H4R znQ|6Wp1g?A&3f9Id1FfIV>E}l>Ck?2}gAI~-NKf4v-aB&ZdVo&y<_#G(>8vAe=_LPnxJCCW z^*MP!Yp-*@{g`Z(VXH$eXeOtkZFHWL`{bpYR_jKzcgUZAEz>1^tRb5`TcoS@xIreJ zwa`63afRHIW3H=uaDiM(o1;ruT1GB&nb8jZS4-B8y>zTKeK5ve)`Ptt{*mdFju$+Em>M^47LjTI&y)<7!tvu_w>k!PLH6YD=zNSg1WpT}!?; zlBeyGuOtsOpU^INyM#&SM@mg0Xs=&+OG+VO zv`4>olFB`iS~HIqqz$X#+FfZ+NKdCA+SAvXNw?mDwV9LmNdtF$v_Ow~60+DsdoQ(? zG+gMawYhqObU)Eq3z@h=dV|}d1pqFRTs-Wxqld~!w^rL~k6bJ!75!POZT+Mrar#zi z$F?d-Pn(u$yZ1>**b9ra@-uvrxzIwpv7bfybJSd$zOjh3W9J;LIQkSx37^sADNm4K z&eIxjXC`UOvLBke%hO57sR_+;LNcl3-KfT$ok;S3_))Xr;a<|x%Y&Mib7M(%@;*%@ zB#Lw}w_9@|JB;)_;kD+`brPwX*rBN$$C7S>+B658LrLH4A8W?;!bwS1%^HXvLbCmN zUlY{@A}#K#*MzL_CV^URY5ri{NXF|oH7AR>1n&+t2WUg39!Y`F;Vln2V7k@>X)deOb(FjkY zsQp9ab+RP~8kWgm&JIma}cp9~P^96zebFnved zmzbszfZh=2MqQ(h8>5C=4FrESDnKKnG4Z(51e&AT;omp&wZSh-8HG2|Zcx>=;g z;@EBCo$oZw-HK|W`4CAHJWxqwyu@iFYc3O!4^WzGnDa!~%@B z0h+E4YNCz}(rmYp6InUl8Z=HstW0s&_~dbkYj?Y7#;-AmwbX5zBSQs51#+{dc}*_y z8hDfDBkCB@!gYh@)!KK5*q*bdl*6)&tnHI}52bU%g>u0PqyrA90;K>D= zlW9AN=EG(ha7hGlZnuf%emjNe|NO7o#*9F`_Fzg4@j?^h>%OZ2dqarSYZK}*F_f5B zKB~^X???Qo`>1{~=|kj72i4P?Jc!AhKJ_Tkg~%!BR$t29N*q4+TJ2ZiK+H+&P|Le* ziKGK<>bnbVh;h3gtE+rh5idnHtF!klB?2jp>V*eo-WOE-u zu}Y(UNqkGFTdGilPjnJCSV`1}%AON$%@?Q-zIaTKnsU_OnTLdnvl;4_PWK5We+$$B zf39Wgw%eD`cdF%!rS)*bxA@l zq2N76jpiRC?0b(?->o`ApudN!O?wX$hTaFNSC}6pbe%g}_qUpA^)J|TqRe?@^;QBcC! z$u;W9JU>G5j}_{-r9OnWQ%lsM7Iy;qucdm;_zr@($pUraimiknrevK8+_`XMwMC2OMGh5T~&K-8@?jFPIcJOir;#oTGf5`0sh_T>#9}n8}RMi zE2<51ZsX167ggWvs__|ya+LyFiQjbojA~(Q1%Bamg9?*-4)1!AqMJD&TEB z9@s8X^}ki&SM>^1(Z8j5j}eaQjI|KY{?1U{^5Nj^O$t?dDjomR@|234mXBXxoug{! z=itK~vsDh4vhV|LM^r&A>G(?lsVbM@Wc+pXA=O9I1Nf=%L{+L?JpNdGyy}sEEFPR5 zry7rl!UIq3R1IW=;Zynlsm=;W_z^8l1-yvG>n@U1@`p&g@D@(h)DOcqw4hY?W&-el zHz6vnH34m>P9iZal0QeCLu$twpuap_pmvN}M9m;c0&f~sXw<$06m*P4BkCnN<47e#ov(nB= zgZpn+qf%%m$4wo%t8DWU;X1f=%HB{eZmhIgc`KTML)^KpOgLPC>+Zaw>@PTpyE1-J zxm})(Yglkj8GJqix6Hm&x#M;UPUmM-4m>-6OQdO)`}^Z@X(>wO?eDR;TBcO_eqJ;# z@QhH|VI7W}ThCR>oXI%TH%z6IKMn``QK+QjLUHv=^OaS*;JEA^CzaPzAh@*9W6JzI z5boUGqe@$$7tZ!nnv!J%;GS!fl}%TjarbHuD4#WK#(jOYPg(xl4!7&aZYA;kI-JFd z80Eu>)woHwDCJ_4LiZi=_Q3mx@;(oXKkJ zF8MO0)2!=Q``SfHgT-a+<{k^>$jbBBeJ1mibL>j79~|Z?N1P4V667qU(OZqxC;e79 zL1ox3{!hh8v=B?aKB*|7a>dWar1H{R!nPFG~c9Q zr%yC0&eapKnlpD5kq?VUl`ne{gmm>z$uI^?RtZxD#hOunS} z{mBC>l%G>Dzq(*Q-7Qso{IwN(>YrVF%`8W3_)48(mDxt@L5NB*Xkmk`-!D_-FIj~p zibaZvl}oX9cX$d{8%r!;gr)G`I1hVbC0()BaSnC?v_SE2>t9TJQm!J{DVhZPY41DG`QLB$ZX7jr#xzXBHAh4C)kt4Kk1V1B%a zRUAY=!+bN@sQ}?xFm8bV6rF@7%*CBF1)O{rvyVekgz!PM=uR_J05WA-Rl zDtdM$VNj2kD!%O8hdDHRk>YW59Ok))h2lh1G$wtYx#I7C;TW1~jsh1!#vFM%BTo*) zVLImimd8*-F=@b`ayv2{LpV4ozea#yl8j^Wl{gUQLFXqq0_}x~wHlVAkN^w_HXvUg z?2I90y_4UCZpM^Xyp?+e*kJ;OUdgjS>oCjLcgVTkt1(+BZSpktWteQ%WBFDWD~#p6 zW_iWd`IzqMM!C7;T+FC@gM7!v8MNPl+j2*nDfFY_8u{qTZ)o}38}h;>W9X8V*W_as zBj_<)g?y{oAUd0VUhXmL9U9(nR=#Me3yt|xEU)?6ffjq~<=&s4p=}PU<@tjx==bO4 za(zz|`ooY|&h5O5-o8m7$3DA-z8uYwzkOJRPE#=Ces`~;GdfPo4_049-&lG|e&|XW z+6R{-4=gW6|72#%`}JD%j|WHOVR8l9(=1J{;)&5$f|BKz3wh{6xd-IZ6HIjC?R|1= z`e}6OpWX8I#9Xu;I7Yrb_89t2R+O9?b_CsiGhB|x9!6XKqR7|6lF$V{MEMQiKD6Ia ztbCJ89NN7qRKCkT8lCVnSbk_tIJ(CtNRG84qlK9P^1miHbYV3}p7R5Vu9^0hKO2Fe zclde8Cwl_Wz5j-zho1YQ+wM5a&o_CZ=ge`ELu*{oX>bR5*~M*W`=X8VcX~(kvPbLW z!=jC7sFk(6q0k0>nXpoRFl!Zhr+BISGl`s!I5MwTf2hBnA z&&-jVdj3TnADNL!9e<(Dy8f2^S~ZDUn({Nyul} zrLG>74`*1mrR6oM_r-whaBVy4!P-6<`}|YXSZuc}Q}qZ%D}OEXVl|@vj(5oJXV;_p zfzM?QiM1$;yeBeh#0^w(^CMXp@(OC@vIjC}p9`qz|L)12Ii5w?mfVpcRv1zFqqQ>L z91UuV&rMm`xD2&0uTm!L5u#jMF3WJO9F%b7McLbGI?5}iTn0Luk6Ls7j4V-{g986B z$ddB1P#UOK204_Df^d|w{{NCucCV$f2t*<($WbISc$vGWEknsNi!1nf}TGl;dxV?1<771;>QSHssGj6>EZJvIEnhL1R$ad-C_t zP0#?@EWhzks0bt*wf_{VAM}=8S~wI60eZ*+C*Or`V7baly558a^f=32-+dXXadVRO zm9>TXopzAb@LEIHz1}E`Kk^_HykotrKdK>Am1iw;ht-9GUapjpx84k0>%2@By!cuu zD0h*};`_x=Wru~#&{Y-+a-Ju%s4os(n>SYmKcfu=cg~U#nTk-=jz3b@WO1lp!7u4M zGB0%fn{U!MATu<;eL`Bb?sTY*F)Hnzof``6`zU=mkR7_ocSve@m=OvWyqEf4NC_?d z*dx8bI}nNtdLtc8jSqEJbxLQ`VncD?UPuRlQK46`&!ifguu#g`R_W#$Vkpq0S(^6_ z6B-%WD6MEfgw|ibE3GIA3f;5hwluHMKQ#0}jnpv#7<#DbhEyHu5&FXJnsjiROK8@K z3h8Xit)aVKpO=n)wht}zDwAG#ydm_nphOyQ$vRZ@MK3jSSA-rzYoxCaEeJQIP%Tgd?}6f3E2eB zm2ONNLQW`;OKXvR$mr=z>DDc8kqiFIkS3aSB7amLmY(QuL)x!BB>hKzLJG1IrE7H$ zkb!UFr6tE3kS>0^r6&K?A$MwaN!@&IBA?7eO5ImnL*~SUOXp2oL?$;-q?aC-A@vSK z>6UZF$Yn)XX5E`2k|&=ZYXHVl59DyBs3z`OZMDItrE|+6s`C zZ+xWr7fvFBAf8e|Q8u!=7$8lJ%Rr{g-yz-XpMuH|pQb4RK9*S$y^;3lbi zYYg(GW`oqNG!of1*G4)gmxi=VTrDk)AR-yhmP^-rV2~j`OQicO5lFb!Qkp*qMV>NS zAWggNhn#cJOzI``K{m9TNFOD;Bk%dmNZgS-kfvv*B?mV;A&abjO0s`#LZXgLN+O@F zN8)E0~}6X6X>_`)UxW!5#xqIdO(;iL+Qys{Qi*L7a< zjeZ0199brDh`xf@T2&(1;&uUX*U=!EF+Gb=iZzn6uMCK5bCnW@3u?roG^r%*qzrNH zy-*@02@ypko`mDbL6kJGB(z^eh`Ang$>gI`h~nY`$!^UFM8S$YNojH>qV)6$NgXr| zvEXNx7P80cr`UP?V#pEtr1*GkS;(Wg z<6=W$aY)R`&te5p8{+eOSRB7j5rRKDC^r8f3MrfH6K7xHhQL#L#CMM|LN<jPn^jLb~x`S-m)(} zSmm`z?Cz8tOs?M`Uixu=FcxhiZYA@x(_+@ZJlv#G&P&;LE;$L`M_6f&(7>5@l@x z1TUg~7ZHZG1#j%15dA4}3{F4%MRa`k#$b!tpG0kTHo@ub^1m$QSXqF##N;@|L{qt8W|eoTsArMHBGRMXe(5 zmQV0C`iG)7MMLn@ZjB-;ybtbq@2;q1_FMR7>TS`(TQA`eA8JH*Guz-#v#LZ~&sKP$ zWu?e%ya}GGyDTa{e-~coeo^#2{uUhER4!V*sS5rlqEuwneFZ)Jp`?(@v*HO582ilnkB+v4#F=pj)*>+Ccw#dX`)?qad2RD zvgm9^G<+8^Nz}L_9NzpfK~yzJf@hrCD>|vc!uQz3iPlk(a7pD(5zi6^pO1?ay}aiS zzx^RhG?@*A-^ing2Hia1<2FRm#o-r*Oy?6a{ma|vCCl=c2h!OKnX0g;k&SBTnl@&`>SwPu>!_58x#JZh+&empM>|! zd9a?)VPX7D1}yROfUswO0nC@zC){px5{7o~5#n33V7iVjVd#l;m{(S(aE(hcZ1MVb zVO`IDnDgCdLLhGsjJfx*kPg`e+ivklSTPm>TT;;^Jg=j`fRuZ}6L>t#ICV$pI12^C z>23*&FTr5}!PUZ_(GXb5r|ZIvRv_4*;Hq%rEl-#RSRwqL=n9kfo);Rdx4}9J%Y>UA zI>2ZyXN1{DY+=?f4Z^byYhkuITH(3pD_{wmRl@w-#jtNrWI_)Y3s}QZvGC>_Q&{^( zfp9rv7R>1pM;Poq9aNvj6k__n1u54T3Agdbf~p?m3w!)Vf>x*I3io{+2&!3kLij+^ z8>D}bCHxER3TjS0B3$sLJ;-xIn((vYX;6Q2valrhQBX%llF(z~e$awV`-O7#ouIrY zdxb9$H9>yI;)DZVD}#KUb_rWF6+zh@kwOOYT+qy^aN+vNlA!wls*tYH1wH8@3Lher zK{gzmuy;ZnbPkLbwyJnRCq@uLelRmgq<{;zjuixbMnZ*3`N<&qFMr`XXm-%PGLZ1^ zNO}+>+($SrN)8&E?APT{#58Dp-d8~iYF5zex-WtkV^dJm^iKjS$v0@)wqe0~&=}OQZ$Mz$ z`w?m*?-MlS4?xNI9zmE>FZ8MT8$m~o4~5N85;ZH zvEW72eW;86k>K#`JJ5iL2ZF)kYN%k@eE|Sb33Y0%7m!9SLFW|K2~eDJ=*GYr!CF8G zG;jKbp#HfQ>UjN{ARt2lwMw}x5Uv(OeVs1~>Z-ZWvqR;AJCO`%gt1g0|C4M@Q!Uu>J`LI^QV8Pm4?!Oiq=G{Z`=N^$i3Fs^-B4u6w(WDyJ+7j#@;wIu-BWRfK)ZvsM- z?q&$q#d|=*@=^uyW-idv&}2bTi4*jPNs=HJW)D5zkRZUnUk@$G-z)f$y9W9W9w$h* zT@H;g-z9idX9cx?7%BJ>IUl->87`Qfngh+iPz4>bzk#NUNdmgpufUgWIKi?PUjsjh z(So#;(ZJwvq~N^OaNv8JU_tG<_ks6%p#meKJMcqsfFNd|GZ3Eu{l8vdIj z(~!k?tN7EF-ysTqCI72&43ZFYh2H=ifgA%|;_rVl0BM_jp8s)oFC?k$EI)ASH3V%e z;iquhA&1fo{G;|yAsuinKkQ~RBzKjHzX*FDk~}QqYx{0Pj5T7u*^z39HAlb?wy1=3 z?BepHwU;36?kqmmy&ST}oX%g_R1DF-F5q8}&_a?f=J9uo$|1+|a`-v9BFHo9F@EWC zE@c0St=Glb^v(fdJ2caZ$0Zaxqfc`#pk*A0R{9K`=d+zzQkLHOI=Z-zuW`0;&H z?I5TbAb;bWb&%t)y!gF>RgkY&-T6oDmO?IaT=~P77eX#1Z0EZLnnT85Tlu7?vmr-q zH}f$&e+R&RZ{lwl{T@K>wB^3uHyG>eismkTF(De z*%feh%MyNDP)7jC%!-d|4j1!080X*-j4Gk8npq}ZjJJIL`48z^RI#2 zEeZhSeBc%A=LS%B4e;RK=>fL``*?42^8*fU>fzxma{_jmzTwGbnE|q)PG0S%w18#J z?Yyds2LoQ5Z{x9n2?4LTPk5kvaRGLzExfzf=zz=AhrEri!U9hDHu56kNCC?A4ZOt9 zn1CN9cX*T|hydwOEpN^2pn&5oH+hu|zkoBBuk*Gp_X$`by~@i}y9GQrR>9LbZV$K< zdx59Fv^n4pqMVoIV;6A3rIhDfZxaApSAZ{H_x&A85A#}Y z-S$5wIK;abRPDd&!~vf8;WhuC2?;z1?vnpH>Rw*Mi!%R0XdG{2M6ti8%Pt-h-bGn%3p}~;q4aF{LTD4 zc{!_z{4c=t-Y{C5x7@qTRv z_*cK&z%wu3=1*z1;f-!{^!K{8hIi?Lt^a=&D|w+VYyIyVm+@{_tng2lF6LRfE%r}f zTJpTEF7P+zEZ}*2nEKnLne&!a&iD=No6CFPIpsGRHJeAfKIsQ0{pH^A`r`KlG0mNG zW7x0M|0j2Ycfa2~k8j+SH@f{Cw@q*dysQz{?$ z#hDLs%RCzVHq7*KtFPYjv;EP-J>yp8xA)5%?msA@-^9=>u7&Fbzq`F1-298Bex0wL zb6+|e{M?^E<<32)@_XLW%C&Hk`rT}7=6*iI_j`Y*iF?+bc&Y(MDv8txkF48Nw*D()(2vLD}A$sJvm=%>?O;p%vM{JtqKah)x9`Eh0E zxdM8G-$8L1x6PE|Cls9Fe#*u9{pK3E@BSeD&arjeicFZFj;ZE`fAjZyO;>Q=Bm@1z zi=r%gc1$o>vA(nniPv>wu>dpOT7arsGf=v9piZZ$PDu073=>JrQEVpS!Tj$4uJ?~4VD8@?+|;DQ;OAz}T*mtY;K)Tz-0bjp@V3>CT*Q+YFl6H4gS{Lxg{tt3bBg2(mEJiLtM_C!-aqkM=jwt&jEoC?z7@1 z9rXlPq*`!4esTeO=gi|mW440lGEKSZ?e^eRQWNeedOn!>@+(KfoCAgojB#53{sDo$e&%$h`~)4FJ;JH$p8%OG{=hjw z`wV)#et=`$JOt|9-pApC`#?T^J)HL!-+F2c69)>e012Mo;~*}SgNg_0IZo?K zK+`|!I0GClNWP$!b9_b)I=1d6XY7y&bjI~M$G?{YS^>Mt*@vftnrRiB19wh=?k8U0 zpj}UZ%ubeb%ymaWEKw;(vnUl5URKOmoRb7PP^afajmCrSJ=btfN5z8ThLs#fOC%^{ zM#f11(LgCHBpmy40;q4BkW;-H4U$259OuGdkSLtZ$@~TZy-a3s^l>22&Z0t2$um#T zc3nOvKfo0fSe45OxUdzZe0qY@VeJ3{4`*`_MH@hNCYc=Zw>2Q_+6+!z>~c`OM=Gb` zi4`alo6IqS=Yx*yOX5VA%>mWs?dN=7@z*y*9nVR~`{}!?YB%S`=!EZ%=P{gj5ubgT zqtTq9#v$Jw3nDoW-THi2IfipiYu@+q*?7+T-bcPiWf;yP zbffR>%23X#8+Uv$&qFxV8*6+wj>9)HmgT9p`-BVc!n+299LpfbYpmHk|*+@xCd~)^PsR#`uD?YJ*yU+7Y0}r!73KL&i+#s7e>ksfG<2@U@_XqIH@IfnzfMHIQzyIecP}uB*v__y?E-?c+t|)c?LcDj6ZTf;r@%|CE$q4cW+36m zLw5DIdqB{}CN?JGHgG@c9=o>gCa^cXo^8JA+P}|1b!?Zyi$L9@8n*k$S>VU-RqSOr zBQVSEI{WDrH4u-z%HF?H229GTVE1MUfX~icV7t9#0ki*Em}4M?zyq_+vXhLtK;!lj zHpT21aN~al_L_tY;6RaII$C01r@R1k|Tg` zQ~2!G>trB8&tc0~a$E+Xt99JRO zua4gJS@|5!UiPxq=llF1_EyguKI;M@?DfLSKFp(j>@Q>Id;%(b*=p<=AKwq&Y^U=& zpX0WkZ2o+uk7>9YyJN4|r=9P@{@K9w`PA&p{%OnbLC)REZa<#y^Vx4RoAdgFPv;SP zwu5)3&w?u(*>Yj3!A*&|<)e4v|c*lW=He2}qg*bZl7eI)9YY|FV(K3iWcW53u* z^D$kq!z#i|h6`?!LCveu5S_j#K2jkO!G#;5A$1dCx<<}>*73yb~R z(&s;)&#Z&gc|NO;eq=dUnE0%%8e%<||HpgJ&wf^5+z;>XK7A}{?YQ^j%pTUG6`#CE ztKYER9vt*0|9-`4Y3lW!?f;S`x9#%&p7Vkgl-ceLxciLt=-CtRt8<^QT(>rR9}j6^ zrRLr9<}eH3)H@?BU z(e5Uz;DgHhLHu=AWq{Os$%U(|1_|F=KT*ND_?h|dL@%lZhtZWq2`^H-at4Ig-PTgF@O8w^Losm+&0*3;; z@6_b6-fOmb6U|Pt;=ek0ZzCLMHHX-Gqf}We3zfC^)uAJ-tz*l*W8KqPn_-K*!*UL@ zOl0%D#g7iLYDVUGTdz)H5d;2u4eZ{}Y7+eP`gJ*;Wj#3IMVi^oLIFQ}eM85x{$mY! zbt`tV5Iyg_tcD|5%iZ31o%W7k)#Z11!B5jz!7rbBq1(x<^G=VvZCJ)ul2^ju z8kWO4tk-MMD%R-(2rmJDIqO~x)Jrh5gw?me&+E0{B35^}w^xE_A*<>vzzZ@mpOx}s zn^!c{oHak#(d(XkE-Oc5>-CR)#CqOm?X?#e?51ZPB52W|LJM6^9wU)&R5S*RiBs-@t-}{FZ;-xP!D-ZlZKd6 zAK!V>9`rMNz2A85+SJE9li%T4aiWJA`s}G^$m=)EmUWLj9lc&NckI9Ki4nYH9=v|r zvv%|alVeitc^K8kWMQv)CZB!6Oi*0(tTb(9It-rm42o-J-T@drSJgK$fydRJ9vkj6 z1rMa2vg3D|50?o%VQ+3Td!t#NKA>C7_OjESsfuc5`Q%B@@4s#^qXM!$>%%LVWAt>- z7dNjkV_qEc++kh8yt013=hLhU%)WiQJ*&IQnPXR?JwJiZGP{3=dG67aFwX^(JRN5l znKT~8(mFM7zSj}Osezn1qdyL6cZM61W|E`ERYyWc3Z}8L1pet6M%g>!+?wy+FnY}od z84sP~>6CGTiD3Nkuzi!woY(flBO02?JiBJXqyKCMb92lmkE@H)m<4ACJsxDFFzFMy$n5dz@@Rn{V7@ut?ooXqfqCQJ6OS(|;+d%y%^pc7b~7!B_dMK(Vwi=pIu8hb zC-Yr*m52CdB-7gAs)zfg2&P-&1&`Hi8guLAQV;kKGSlRT-lIB($h-+wc^qlMG4Xj4 zk7M2#W@8i2quCJ3w6SD*?6g8K3B&>qa2A}oSDNDyGYDn=_a@WhF%iOa*_h^W>b4*A z{hos!C!ImejPiXRjdCC6@Mx?D$=r(xc8~JdlJ3qtbcE&sfA7l7ts!`vBkW+N&Y(QP z?rdYigMvM6tvry(9pjU%(L+1F!YTJ?ufIMMB1<2=py z;r`0qLjRKyoc`S1xZ*n_<9e(6DaKbu!H*{Q^D|?Nbf3HKHtC}bSZ1wz`^OQ+L7Z1yB#8U|R0J`sy1-I!NT+y!ACB zIGf{s-|&+0qq@j_-r9CX(NvzhNZ7{s1w8H^zwjvom3hSdR6#4_cvXt~hri7X?vF%w z(a{HtJg>d(^ojcna{4a!#sduu^J@|A=%G6d7;*3V?HWeOtqbJ%n`UgxzFF zF9f-JzPQdfH{$1RkH5yyJNdXrwp?ap#Jjn7AuchTOPt+{@1JKh^f|g;gO)RZwj13o z@02q5QES~V`IRspC|0=3YYdEcFBiE#0_qsAmoIRKSE(6S33J`&c`F(JWFBtIuge(b zkAAwvdrBC2=3m|BRtg#2L7&||c<>q4Cx_ftR&p3#weQ@Ro-BsP&n`FQbvk3IM~55U zyO8np&{H=}RX*d;xn?&n-#o^b!Fz5iYjYTQyW4L5{>T6As-~4VlV_LK@scT9X+j`6{ zQ>q-)<#w=m8{<~(6aeJv#OV1t3BcDn zGTv?d0=R&%XWWk&29Vn~GU&4RfS}k74A&=b0a;&c7&lBi0n^8<85_WDfO`v8GZGHB z06JtV7^1U{0Kn#D41M<CVo4DRw8z#W(sBRaGa@a?$;!|LQEKx*84hOV*<0Q_pk zST64E<0cra? z=%zC+0QXrh=sy8l0bt29dh2d`0LS?W{giY)U`s;_eQon1}fX{dneQbv% z;9}8z`i>ZLzyaF^Iz~7fkXm(zj=4YW+JLX4yZ-p*8aZ4;pWHI$>YsO$u88>Pny~f; z-Hz4o`u5s2I_p-qs{(t4-Z|Ros{3$>Zf5)3^-JCb`U*m;YvH94QU zyYfkA=-l@;u5-T_>5j{wQNpeJZWoby^%S}~cnj$>yV}LnMtqT zk8!QPm_fIdhqw;o(&#ZwfvyqbDfIkrAlDVbLv;EkFW1$cN%RzgtLvVZ`{}+pTV1C! z_t6K>+q=HD*-KAMH$?y`6joW2I#>H=(r(npRoxtvRZ&~?Uom-sdQbe|_RE{XLZ`jx3l zmzxPd`Xa{)7yMFhI*w580;utzryMJG`ER!yJ-t-p^4QXq9@QpuVcghGcl;x8;l*sD zKi|xD>9KI4#}W%&j$C)7zc`lb5*}kucPh!qJ^sMPaE|qcX=tms( zyVNdPOQ+&?yDY3-O<$84?Q&+{N_w3k%!R&UIX$?A_&-Bu9u3tShw+&)W{hQ+VP-Iv z8Ow|@wuB;~Y^f|IiI9*sl2WNK@7-o5TTzLkBqiDq5mBf_n-)^(r!1jlNo1+~+<(63 z-1FXZ?s@Nh&wI~vpYQWAuWY0pE1g_xF5Ihp?4ORi`8RE)V`i&XnE!k#e{4nUGIN(B za>tgOwKnfIA{|p{GB~+kIzy6V~+oo=Al{G8P zNu!%f+@_^Xm5SyDzbB=yK9S57u1-iBWbx+90>-7MP3O!izv-6}Cq9{lihHF3%}%pS+b>ef6|c>xKmL>I?09DOCcjJi zBmJ@2mkl4J`IQgM>?oa5>#iEJk9FCq9^S=fhd;fL?mlqI z%<1Ga>D~o6!8(stX+Xmnv+MKCQp14^GoL$;q;C~d%^aeeq}wgUW(N!!q@VnO+0@5+ zsZHV$vj->dN%s}RnY~?8Bh75yV`fRLmYyEoVfOxBr8I#SZq|C>w$#lg*o(8(o0!0roBbU(x|%=rfVXlQjM-3rhg5@(vp7zrqjKM zREOJRy8IF(J?PwJ`ZP==E#KB*TBw&OeI;o#ecW?I+FsmhYI!MMdhh8&(}iSNsrW~| z>3~6;)LQwjsm0e=X|u&`)5fA0>GJhAOfT$=mY&&PWco%B)22W7M@ajBA2)Sc5+=Q^o^1MVc8fH^7B#J|50=gZB$@WYo2C1X#GCrN2S{I@ z-Dk>F^p~pCMw#lo+90+57-_mUYrWKAF4R;Z$VVzlo9(4p z);!aBeLLyy4II_X^SfjXC)^t9WY@DrX_;=F(xUqlaebRcABhu zHX)%*g`0SvAD4L3LQL}ajxLPeWMc39Lz3*i-h|8iE)j*THSrl5lx#|LGikl|Rl>}6 zGD$ztC%Id0XL2s0N8N6BI>eUqxH_YyA~ZIh*G z?Y?3Yohb@g~YCEUP!BZCMj#15qh0!l_-6i z5Vr4rBJq+L5ngeAEQ!+^6gILSN<`K@LjJD?NsL#Q@ZGcf5|`~A!dI8;B>zNhLZ+xz zl9$~oEZlTg!YO+wOth?$9BZi;UQn!*y!%ouR2(Rm$j_DwA2yUqxbz#sN4Ym8I>tpp zTKshhZskSc72gs`bHF*F#Qdscf9z>tnZgx`?6KoQ!@*0Eqxr{#eGe~6-c=#O9~Uo3 zST7TWD@1vcKY1vgij~H0_J76=E)kN~=AFjY#$gg=m)FL>ltU$pHa#=`I~lwnHa<39*R@%~0}qTx z8v`UWCu@v5i~S{KMHR*h8GaI<+MCAGcwfnz7gvpaLf1)__Y@e1t@4(nPUaflxA2rS z$el5c)L0|wVrLj{B6vu;%uIt-y@g?Jkn^4I<;=`jrx=?T3xY#ZHpW!~2b+ zPdZ5aQlpJ^lI$hb=eHYc?6i~M%eESaY*;F>XxeN%;%FmrZTB;75n4%{2E2_&Se6pb zjE8YB(LypH?_$gvHt{Tuq7&0a>k)f8j|W}g0YtcOXA-7 zM>6@t;&ll19H^L!Y7~MbIrEbjV9Yw(kYA&2o}W z9&ZH8Ye*9HfaikN>qJTYj%LB73k1pP_y)nFOq}GNq*kz4{7=j{Qz`g<_>XwQm0N<5 z=vndM%3{H?uxT;&@RH!o#wqckH+h0PYkrBnd(H@Yoqmd`;~9b=n=x_ue2PHFWJK&h z6$?!ChQ+tEfB;qhCMFAy2>8l_VmI43fg0(nc(?l=!P>vQ;)8xW1TTMm5$^~O6XXqd zi=ASF1eJZC#PdlT1?rzZiVIVH1drR_i!IKs7TkaFPFzsrA|O0z7td8V2u?J-5!*E` z73{2iB@TUQDM+n+DUR+k5zO9tE)E^y32v7>728d51XY(?#IpppfON50d{LPpxRCou zY_6p&K(d>}my9Ta@>31sc`F%#NydG#(~7@FV`+8bou0pqa4EIo_<(VvKdCKih`8)}WNB^HS8|L&F%l5|N7^%NUz5nU8}{J3N!1{cKBzw?Zy zp*(RqA={_|IVYA^$~3x%<%svNQjL_QXT*28Vx#NHr^Vle!01%kNiosph*9&23^CCu z&dBxDaq%~gJx0{*G;y`>4kNwX6mfKLm=TnJOf0`W$VhluB2L@8(TG!miGLsVG1_tq z5qlu3jlNYtVkp(c=zfhzeDSn{(dP$=;;ZME8m(zQD$XjhG{V0)ERHHQF_LLNBsRLs zGxF{_Ab!@sG5XrOU+mwiY4l_Pb>H$@&1h;OMy&slYP9E1v^b(y&S;TrlsNS}!N`%i zOPo9Lho8;bA>iiF|1<6)MvtWM z2XM~fVu10rRaS^A#UlQBT}N?A>S6wF^W|bJb3Y$;TqgF&j^_7!+lqhXZRcl(E)h#E zZRMxLT8r_;oB1!{#o~yYe*BPAi^Ml?d-IoGF&BTX_TYz9n~G=ZocS+Wh2q)9<^1GN z0&#Ei5`M-QUtIBQ5x-Z4Cyst4eOw94->ea+Ie^2t3x6{Q3=SF$0-&MrC z`61pVg0i@d(8qhMp(I{T`j2P5NI`s=(#acLMG;RbzUKW3C5uf}p7C4`%Zfc!AM-wE z$cX)z4|vTbc(JQS4R5At9@EyU;2r$*7yG1hljrz*4ij^)@_cEt7}KDDS1z2!j`MPP zL2gsnm{AsQ{nlTYt?&fzWWrBuw`nqulRbu^<|yy??Ga48D2b=pHjM3E9M6*uf5V)u z_wiOzhOmD&Q9O6v0CsU{B=3xKKW1VV%Cp?si(Ob2$kPyg!RG8Y@YdvYV@?iUyq4Ne zSd`-`UdD%y80@r?cX{SLCR$<7lhx?Nwym_`l`ieT7CT$;u55aXeRDSE4aC33j=31{ z;&R$BnyU`av*rZ`xh{arKR&}gxYBvue_AoNn2+>{^S*4c~(+GBkz3d zu_bI+eCRyZX^~)fFh3W2V|LK+c*|L=%4DzM#LsLDG2UfZpmhebHHt9Ib32W_GYm28 z+j|n*qQA-T;JFO!C1<^%@8jc`keTa}EJFzgKL;-uJB zx|N~YMKPAHY-U*X9K}KujSMf(!WfgHXV}e$uxeQ?!w5eS=1gE3S|f>A)jws!^<_sf zwKaMr8We6T2X8eITD0jxpm3l4R8CH2eF`&(MTvfrS$c`X)_ z7;P~7cQv-@&~}3$D-X;rcB_H>Zg-5ld$R$tz!j^D@H6mu?~Db7cpH3FS&8-gdl*!$ za>6#Pb2j)49I%Sj%MCW%wZ~?iml&x1w8M;-FEZc=Z7~-cp~0buC78Rpp@HUkYizNR zt^uWUF(%K|FmRz;Vyzmg2CZu?usFJsL7v16lT#oY)Ha%6m<-;);GZ!zJU6TV!B&7d z{Q9N;@cpp%k}qbt6`oQ*Yyd(bW9|@ zqW>vZ1v@Ls*O&Q3#qtlH)jy!Egq?^!rEe9YfbEJ%*LS!;!OS*G^-p~!W1rT+`qp|R z?7*r7efwMqIByVmpl*%&yU2mNbP37txCQqOtA8qvq*N&s(ZHx7{WsaiJ zk4^PWJAa_RWhjH`b!;u{)vg{|*-Z4i~7W9Ym5{EB9uP}Y~)_M;~;ioQD3 zi^d<3(Vuwo1zi>MSC38mj1nS#>m3jH4=vg>uIE+Ih1z(2*9-jq0ll@NU$4ySJ*sNc zt+yfR9lF){y`IaHcJ!>y8$A*IEm}u^u15-fjXotc>wPF{Lm$pQ(3|=B0xcS;(Ti|+ zj>h#==&_TZq9z?T^>jO0(3dS&_4epJL4)fG^e8cp(e~0@y|LPd=#s)LJp)P;ik&&3 zcWGk-T9=%xx2Nzv`Z*ER6aTD3f9y@t8*;jb_J_yoWgo9WpKRQxcj~`tG|MAO@1toI z>SZ6P7n4|tj+=$*c|X66inxJ#N3_e)Y1IvSKch?0Ad;8fo%)+-$+WxPW91uY@3$3t zdRwoda-WvzwU!s7te4h$^~9?vt-)OH-^MHGRJlMexwsI0RH&~P_NM>^S=xFM?~5o; z%F_E?Z~?74Ow+5F%0n%8E9lj&&P8*AWcBD5&Z6Hu=ef5hvQfU{3^#w(8PwZiVQ0@f zjfQc5a6=|eqM`Hwu7yV?>LK%m>viD-s{QK&w`wvS?dp5Wjb59EirZgsV=kqjT92P_ z>t~Olxpx}5o7PKFxuSbqhY~Tm<;)#!ECE9=N=mt7fe8BYPzks8HiQmrFXX;f1n77F z^IV(AB=m!OHn;zN0$RBwllw*ED0+mS$`!;NMujXfx9-Iu^a%-Y&kGKs-cyIUt!NzD z*uS6a{COYBZI9;4*~g*_7(A{wz0s-lgB+h-o@kO&4`=k*8uX`W7w3cdYIGgDgF`#H z3eA;kom@Yk2N~Om2gPai%|zE z#M!NDiN?$x;jkqZXzJHEj{2w>diwPqPME(bnq0qwGksr(?k)-Ad@wRbmu3ZVD49m+ zIJA+2&hgN!Xdlj+ZH6d6U^QpUOMSG^#f5XJ;le*7pmCyj~QQbgeMf4_lNY^??9vvC)(G8NLpzN+L z-L^wy)ar4E?uh|e)ULEmH_xAl3eUFcPBjxydGw*~xutmYZFIeETJb!R;$N-%O!FUN zzM@>$KlKlC-}t(&*}qw2nc5ZI^?PTK!oL@En|gjDvtM&`f!`Ej-*!^>*ppw#uDfZv z-ODBrtU#g*-x^2KQXt(}{V@cJJF0u*%m}hI_<*jp;t#~!Ek;)!`i=~l?bH=c4I#%_ z;kr4y2N6A7u&(cyuSmh*M%_UFeuVnUNB73_US!AJ)w-T8J;;rVF1mKLpOMeU9CY_v zb|dq#OLb?8KOqW%mby>5T?lcdiSD*+! zZg}Eb0HrqU3wR3Am;11RaGHl z-*R+L+1x=CU!Bx3yHkNMtI~9sHn$O_Jc*9Soibz`hICqON|DALM|I9r-9&)b0iCj? zHxLu67#&v4HRPejPMy|eCCKXeFrC)At4MuckPgeK2+?WXs8iZ_8Hu{(qm$)Yh!mY# zt<&N6OP!OQxyT(Q6CKy!a|ry?P{*Yw z2eEsnt8-#|HuAYvLr3r<3yI5D)uHY`jZC6SI!-euk?@^lo%^Cp`IsRIcq6mpWLAh>ct3g zPn&kRJBHM(Yt^=Rg&-l;54Gn4VPsUjUR$*vAklxSwBut$$cOGSZR6QQ#H#6DLZySTQT=A@-`|*dyF5C^n0Jw)~h&(^jW59UvxTvv@s;wQP1}y*QS9s z8n_SH|M7_S(7;|qP#>p#?m!IkEPs#oS(!aZ2(m-FKO+kHv@J|Kk+U0FvnohC{MJt7 zit$G6(+)e3QAHnZwHJ{HZ`4D(J9rzi=9RPd^p9{PDc%>fudDRD+^+fTBP0 zseq)t?}8t)9K~sOT5dp+x6Nv$K3*x?Tc2R zx+j8r`cW(W#u}veTDun2c{Or7^`%x<=PG1hbc@#19(P37t4S+F)(xpKtJ9+Ax**QV zRa$C`osrtnQmwGo6$rPjMC1aEwRU)uP@=Et>%{DDYd{0Dcoe8l-ren5i zK{FOeiuYEn>Qm;3qWNYmdkZrpVId${>6r=g;fI%&aEB1#KVPMlMKngjuCLVcyl8}^ zrr2w(ci^&YG_5Zg+Q=?=A^2vI7BU?wt3`RGi5zg8XRE|&AfL5o*by{!#O}{ewrn{QK|Tz# zf30UAHPv6)=D$>t&sm?@Rj295RNM!4+7cQvv;Hmn)_Y}S*y06SH-U=0pgv)D=_n!R zha1>m8x)X`)>^jxHhDzxY9;%#90e)HZn0loCnMJ3#cY*zB&5{o68qdF5z*AiWA8sJ zgY2JMpzt{oklM}@Y=wRt^0P9T{WN(VW}QUY?=1eoCVP|Ei{AZ#Ej;7dor!a>zVSZx zGlN-JmK?=adNvKe>)poA-Txat^I!}65PJ%C%L`!VH~oV95BstiQ4{dKjh^gIwV&{) zr8|4DZVcY6yn^kzeH6a)-Htt~G6LhDSg{9chGDxxGq!NscQ_mvvFnt-!AFDi*ts=> zFtSvO{bbt!d{~XiUP1c`Zy8f&lk56mt7jB8duJ~^QzXMqVD!K@kiVM7jh|tkEx$Dl zW4hs9yK&8Et^eR{%XfA-oTu(yPC&VyoQyY-qvg%Z-a*}-_VRHcnRMDMVcFZ zU%;`OFKQ+epTpWV=QI`WJcX-NPHVp3-U_e$o~}8m(E{IlB-IRg)(rFVVNEsBV_0+~ zL6c?q2!68RpyrPLCKzwNSCf>}2n#5?G{@IAz$<#gH3j$wut#06=B>(lc*PliO?X!w zY!tgrvq1MAJimI4rgD1?{Mf)%vo-lHobb;<^R-hotlzm*lmGh;e7DR}v-L(L?3iMr zSrbtKS4QwOf3t7HYzK}e^rj4sWoc>#q?E#U##A+voNvLyElQeWb2nhxC9-B|#dVmU zfY+>xz6P84&1tasC9s~^q{jWvS79=FRO9y9BDkx2P-AMt6}X_fM*~y74EtwvX@s?2 zg8%I7&`8A!;LMe68pIVBVHUepeXO@Wj(P4Z8z*ut#B)#=xRn_;^B@ z#+Q+^@S_daGz8ak;O{1vHR^X}!vxt28u|P)Fy&LW#>@WG@O(w4#@fPD@IY#+1}pp| zTpuCUFw@I~#r8ns)Rz;mgW3@dw~NQ&uiy7;xNS{`lbWJ6PIA*=^11CAW<4n|*tb=K zc_|tG=CN60O~f(Sh3lvB!cYpQPkU*c9}vS&Uar!pEym!9D=Rg4Q7EjOWUtX}hQMq; z8;!nk2xggBXe_M+Fj2->qcdIve|fL3@z_2IzE!HNLBJ=%(Gr$M@}r}$RtQaFYw{7e z)=EJG^*#)*QIOS`Qj3S5e)*?f@!=qBUp=kCPU$ghGXh}4O`%qXApI6S_lkBC92y61jFSk4yj)>41(V>W7YkB1}@C& zE_MI=0r0m65$Z*$o8bRWhp4**`om4THmRE#ZG_J{u2+wo+5m4=TdV&4p)ag4kO zay{Hs=cwKtwhj)?v{m=C^nr&W7puz=yy0!jOx0fUXeDxg#YvDzG9CgM0Yhb8a zQ~jUwYPc~~O?^4T1O63CRd4<34y#+ssTWqe!6p=f`m1f9!ZnN>){7g9;KzfRtX-G|{IE8awISFXzMU>+rC6K6r?vu?3e^;jv^v7-{VIe7 zy-X2kRO5u`CIO@bM`xmcb`| zc;v|{R(Q1@>~L-+Yy2b^2GRDcXE7YO!qJ8`xkeX$PqSd{HqwE|dIcEcc`8aN1va)`rakDTazuBR}#jcWq~Hlu5F_b z$(Y9s^&Wv9&ge2NZGS)qS~QsJ^oJq!993q$(s$^_4khN{=^@B!DVYiN4njA{cxLB| z0f_x>mXT2N6*_$77h}(re(33e5yp+oK8Wf%$XF)ognAl1zvnKbyZW2j^U4~A%?NR&1E`)Bs(9qjsKq4%)WdLhX_MS%^R}RRpnB(PBGf}XsEYrY0I9r;Q9bwf zD6}|drz%W23VDQwt5z|NK)$BIs&;yZq4mEvsw$YrLoN+IszUoikT7MnYPQEgNY>9q zb%Xx_=&g=}YVfu==*-{})yn<*A+Pd9s)6u6Xy&L;)hi%*$98Df@Mk(26bU6%exS$1Y=e-bxAd!U1SE2QK{w9|hhkKo z(1|5sknj5jI=_A^BrK?rdl7s?fEqMJCchi;FrqdyN?2i4zQ zL$5pN1JyyU^tlt>P`QUAU3|?8I!Cjmhd%a%4!^ggOTVmz)?759&;MBisqW;_o7C4p zFD*Fq4y)A=nAV`%tn+|)4^-*>(W{^ai4wgh*&XunCezKXxYe{s19Fp5<;yg!a*SeRq z6Lk(yih2ue=+knjpu3Tl@y{N*apfLOth-R7@6cMEmO%wprL@gqc2L?}F>M)Y3q>_v zqV2k}6k2gCkM{M+5=h?X46W?D4b;NSptVqKpu|tfGz&{>h+l}(zWP}~k9H-|h7K== z0v5&7mYuhRdVa^!7FcFbX#H+l%YX&+2Hi%JRkDEW*KDDkur!Cx(gJ8ZHkm;`-mRw{ zPcnt9&#$G)UN(XDN4U|RJQYG$jGbs7ei}nB$82eKn#RzNJBw+9D+CZO(UjJ=(+HwC z^J(Upe27fp(w@}tpt%>Cv|GJ~P~RyvTA!jJ)EG#m?XWR`vN&=yyHI^-%U3)tFj)`M zxjv`zq=E~*iJerzx;aqdl2Mft@*GI(@1V+%wJucN*rSrMRR^+{cBzQdw4plB4wcrs zTF_$EHkIJ7Z0LMvi^_6UHZ-5tq!Q(%32h9oQyGfZfG!zTsZ^X(hx&h%s=R1nLE5)V zRBWc1(3zse)^lhb-{!DxPxkQ0*fpmBD2cXnC@o%BvVTsKU!ig;Gd{xTu0(=9o#U#ASIR=Bp=_1khltQV1BS|-8#2(1L8{8bUINs8T~39gNr1?) z1eI1FJY-<~N4ZIYgO<)rD$C!W2P^AFl`l;F1J2NpGGg`**t+&AS4RE?Jjy3!>kEH? z-181)V&@$Aa-vO{OPd2_8(Ni9SI>fj>JOFO&>3LaRj2G#KMndWEI^f}e}lB}GG&j& zzk!f{P1%0W6nOBhP&ui160E&>UYXke3%rQURvza30&dos${N8Fpkg{j`BctNpm7gV z4(=ES2Sg&}1FGYodF5f{k3M5SnY3T|MEWT3YKc-l`D_FrsgcTk@+07ucc?Pz@dLb~ z2P*HA4ufy)zREY7zk``JYgdv>T>UCw$(5 z`T>l(=Ik4AzF0*4+4~yA?LJH$FntYHn(n6>$G-yP(J1P@#x~GY8cEGlY6FM%g;Jkw zdI`8zfmDye7oc&{m&zD>4mMYLQqAq3gYWU~)NJW9u+MG<)w}&E7@M=B`sqCdk#$zo z;+R(OI?0T>wyp)(I2lowE3|+NydE_n;0fq!WK-p@HUl%1K^>TS3}RfBsdTr;pom1F zrks8R-Zc}bzWoouKj|N(UDgkQ*6Jyxmsk_9R2Wl&I~sx0vmqsv-w0gNdX?VBHvlKE zPfGh+9{?-mcS@mJ4}fl4n^Nwc`+$(qs>E-o2VLtPD$T3bgB$dECI0q0aPUo)QeMqH zu;f&k(pKs{FuLKIQe0RqxWKrq)PAQ1xOJRY!W3#ie^#~<5_%UL_0LpltE>hT^;D%O zg=%oT6I0r_wF)Tah?LT+?f^L8uo8oM2aIU!SNaxF34A|9DN*lLfLmuHl_1p$AhS7C zY31(Qz?&VYw63WfWPbEjy2UOB&(C=(1;v#CT#&nx|MOBH)LNl*kyi@5y6lu}!7Z>O z*Gh@=;U+j5WTxb2brWD(MoRC~ZvaUbSLxc&bpYiq$WAWT!TunI(z5((AXrOTX=bhj zICd@2JvWsA^<09|){0{AZSx;R1zItvU{5K^?70dKejHWwcv=L^&kZSd8x?^sfxU{2 z;wvCU^ONFa-(_I>p+oVY^JUPS)28TJPzVA7S{1|bg`ijcp<-L;C9titPBG;{0r-5T zO7S$O0Ic^fQ~Uugf;#3k#ZzDM0jHx-@z~0IaP;(f#pjnUfR`Jx6+>k&08O<_#TDDn zgOE2Vim@$u;A|$QI4aBoFV~3_@1^I0IhDhT@5avoPTM}k6@KS{!|^D^+3K^v*DF#H zuYDG5RSH$~hjPG+!Y@%&H(EtPKp9vlLSGc6J}nM>QErkyK#Bvj z=lA5di1q`!d#SwczI`B`SRz05Jr<-lT$0y}j0Jf~dGhI>_kzpI&dB?0 z-V2JRPsnfWhyewa$?^^BV!)YwsC>-xJpeOLl8^G(1EPly$yYy$2HwT7^1dshfpO$+ zdHefO;Gf<$`8fM1@T@yTe)jHea4L6`{L3Y~fnUIS`H9M1K!v$hKGJFzc=Xy;o_~8M z*niwneu?Eyz+P)BpH;R4)X6QDcV4suY-~B>CW6BfC>knJN zqX|omlbmQy=xZU%bRjN2iAaS*Q;`4a%;d@T!EZt?rP9f zdroe~d^PAlcv^0v$pgq(9+z9b$pf%|NafmxR{^uDuv{&)3fPAy$c-~s0T-QvatE%v z1NZkaa;sLl1J_eK<#u(t0SE7JxsQ9?fTet}+&Nh{z|^{Fcj2%{haF-Am-sPdS6NyhU;cOq~Jii?Q6b$1B07a|Uu2p({b& zMjbhs*%cswrY>iAY6VbvMw81jTLBuy3UV7;oWPzHvU1xZoB;FBKXT)|Be;8KnjCY^ z5%|acB=1_{2*!lNjSdCo;^^&)sR^Y%Rqe1Z89%(8Tb-+gN)AG0ax=P@}diN;POyD z+0@YvEaXp;4|UsujUlJVD!>*Lsi%{tIkw=}YYExBaVfA*gUFTPO95~{N5h?w%DezFePs&d*1+vepNw_7Z;GVdgbgRb%#5i3i-AFe9I32< zAU5wO#a|VG;~<)p;x7P9yX~Z5k^p2+gpzXa7y;IeK+?HLBaj)nfi%Q40u+uHN!-i_ z3GdxW`{McFd*%w#4FMncuU$s6`N#wH3qk`mjR*AZn~`iBc>s<#B3&Oh1ph74BgGaP z0-Nt_66$XVQVJQQ0eM5v6|79ksW$)u7KN0v&j9ReBajAp2B7-bA6fB7eK5OnN_PJV zeX#V;sO&9QeXy@`NY-vn4;1g|l~pU#1E2VxWbL=>0mUyJvbVMMz|ymAvJ3q$V5@Jd z?C}&X5Gy{Eomj~QMUU!augr45qogX?qH+%CUQ#AIy^8~;#!6(*=yL$2q)=Aer3*B| z&&xKQ)&)GRY*}w_U0~jxA!|(01y<=PvKyLofQ>sQ`#ezxSmQ*prf0v!gr^PWa<|B8_G*EzegU$z7qq~0s;}&|AT3bVyjJ#` zh8D;KZnB5ou|bTjlkA4mY~bY%gd z7qQ}`I!HY?Ld^722M!wsiT7FRU|6w-xa12h)z~a@axqr;^G+wkR}%s57aY&hVvyN31xty zxm@B`4+gNT$RaXS7@#)l1o32t8gMd9CT_`715KY0;?W2-;GC66>=&wm2CqZJ^AoCI z89A0%RI3VZ-`_?2ho}Oh_y}U*T2*k?B7~U3PzCZs{=`rJ(ZQjM>xeN|>EKJi8sfTr zbl^dECBpV}aI@8ch$qv53bK^g_KF7fF0&;5$fbej6GCFZ4jM4JZb($Kq5%-0OVq{D zK)aR(G5(nfFlwh0b#qj};WR}eGg1XKyOM}Oi&X&q-@ME?P6cefGb8i%g)%7EGa*CH zQwCpoKV+o4m4Q+BSD64iWw8CsXPJ14GAQ)^AoI183cAT}WiDN%0@j1)GPmNXz%#yC zM&5%8fJK8$g$5Or57x-s_@)Ft=U2!~)+zy|fSWQYX-Z%T?W#=d79|kca#7~;A|-%9 z=VSy#B~Wa8T4t_85wwn{%V?D-f^WrAnbbr@Kn{at)~-_odYTC`frg5}?)3qgsu=~a zE;&Xf{DlJ8wsNOT@FfKhKN}`f6t4iJfdVMd^N|Uel?T^9c*yj& z$%BeaXPN3Ec~HB0xy;8Td2pYwM8<2QJZPw~kWn^UsQZj%bV&>6jSXay{-c1}1-pq! z6$MnDWyuImP{7UgG?@cCDWFhZK}N-y0&*IOGBa8fkb2}F!Sc5pNVJ?L)Vz`dQQyW1 zC$7tZfP(LYI}$nI64*~L4wnOF^lrir2RXoO?IhsXa^Mg2ny~dZ8GNyQMxebVgQoFE z1eG!}C@j8D2uUXcbn9Kh+-@@1s&Shz;6Vnz zAzXh*0=cCp3HpU3uy;oqVGtn!XO4vMH=G1iI{_iog#>zzA0en3l0d0@96^ml0txfc zgopuI;9j+zKx~l(DluCLKTBl6JKko3d73OZ|KA2eZHz1k%km;*t(OHnuT_Kx*0Nww zb|t}9Ll#`ETSmbBC4%h-tO=|yL||xYPDp%21U-F51j`a4$jj9uSRW?>{|#CMX&ezK zD>4a!K;pu8lrllni3k#oQV0P&B3QIohA^N=1byHB;2%xMfHMVC`0)=iU{&B4KB`d$ z{HA@w+my(FD=ocv?@Sr60s4fmIwAvbw(szJ!ezjKZ|}puR40J8T~YXl zBm&r_7m1gf!~>ZRTkz+4@gO%N0H63853D?V@i!arpcUtdH!H(~&}ujQ-+VlnigCiT zGw>jpZ-nRq z!GX|4J-DuB9QZ!?5jS)X2M*-7<6O&eVBY^FZmb9gq{=P0Z+SRCYi`6XK7|80N%wHA z$vD8Zxq~Z%aNz2XTeyLE95BCJjEmZf1C>FSaE?20V3}GTE-VxW8lGn1-fqGHH{=BF z)H)n^YL|>FT#W-hKM@?k1qa?1C*p1`$AN&Yhj7=I;6RspEbjNBh5KsTh08F(fnG@j z?g$?TA{|3;xAkyfXv!aFr-K8#Z?40sXyU-gwlz3wCJyY?cEuIbap31$2V9gg4#cG{ z#U&}?z@)P!uA71bhvtO1bTST1mmA{JWO3lgE?wM586247YT)7txP^V5jtj@*z`qlU zxbrw15UnEN_zQJ@eqMxIIK-XvBJKEd^USb$QT&+Ae0lCak@wEm{{p3dMW1`37rFrc zh;{~3{=M2aD-ygf{96z^EehJ`^cUt%iB`0K{1XRHh?pA>{fR#{CenOQ|C8bWLv$?U z=G=p)L!wJxJ?7-b`$dJZ{jopDfn zA*u};o!+qNiD>1&B&coDn(yel}TJcwDsk;f~1(p+q!yhB%oTktEu>FaOtqFHrQ<*Z$Yr zq1~cG_MH>QZNfwaCUFy0R+~i01}YQl`aDH@46gqScXbven=GIw{FjQfmiLWQwM<1} z8^L%*23K@8UTb`$njyj$R*yZ*porQ#H;mb9{Y~;^jgN+I8cV9)k~V7N)|=#9E*O2> z-=4Hc`SFP6k|#;`4~C7{+SMcphyMLA8NHTN9(nG^AHTe$jL{`O%J-xvkBTnpXroEi|v7z`~4}ViqQkf z83c-@obW(2gAqm0ps%0IEKWJ+LFrd%x=c~~$liZlct2$iOK~5k#c%Rsf?l7L@E7vR z;!1B~Q$9KQMQE?;!Ekc(ZT?;ZCK@^ZPj}C^Y!k9Y6QSoDi#S=n_(YG(rHkaiih}PM zvrJ_2fX?@Kj^iYOqbuK>W9mr<%tOB&d!9nNQP2PFJ?AUZH|g))nmBus%mAsIl`2ol zd&Aznb^j{KShu9>M#^3iMbNM-r*(oT%fI0(KJ}_ut8kVWKKB7*>tWVY_yyZ{E&H!8;^On?p6fto<32Vq#s>aXlI%cbK`xw#)@1J)ZlC zX^$ADdszQd%>h=-ogF(r)i#Z|`bwo#Uy{moy_}_5y-j@LdiCK-6~;!xwR0h+Dx8JW zRlixLDg?XW@~8QCrDs5;OXp%pt6()*ceXw9 zpyJ8p2Is+zk@BdNVCNsq-sQ-Ig>$m>y>j^&3^T%#BVF!@M6g zg@T=slHRg4E_0__A3e*s+HN?FO!Aa%++B5Sde~DMs{P6FY}wP&)AxKFk67`PrnKof z_Ve|Wm~vlq%)aeeVlFc4P@#LPq@A_UK_aEMxH;jmgVV+5#iRv!2TbGb;-#%44o@Nm ziYy!Y?7xM)DwjUR1 za{cH5)+$7o+!7%j>(AR~a%)Q1t@H9*a=xthTM0$cbM|k>TKVVR%<(U`u$o*Qc<&=| z*$U(8^ZxS72}^?$qVEykRLh>(x$JU1M@x>saoNnHH!QVoX=MA}{%w&P&Y0~ao^4^n zm!I|dD8?e5!8WTih1VirCwo@Y>3J2e(-{PM!W%+8EuIidnSk#wKUVV^Xmr>?XwvnyIg--NrW! z_NAWf3ouSzDNixlp=zwtgiCRr*>7y~|^@d6^ zzxJx(zn6vNp>rP$(=U|0)6H=G@`@E0a5IcYEoz2xB1`DY_-fA9>GO&$^cw1Jk zZNN~i@wW9Ii^1&q18?)(8}zjbKP82eJoK%f(UQ_+1oaiX`I1-%{^;>G{!ZK!O4pMR zO-T&3wA4$VHBbC^hO8I%^>m{5!A{+~OI-<~eqOrCN`48N{o=ak1{D%k7FKoYQ+6e2 zcVz1{WK_mSQEYTnrm6A&&f0aJn)AnpUGLQPKe8B?a`%;X!d6zC?ru@-VNS=mj>IJ` z{F5tj(#&aE-W;Q`Bci5SN(*tZog&AyhIg2t`}A-p9`3cn-E_EL4tK=io;TdpcK+YK zHQbqod(Uup8SWp$9b&i#40n0qJ}%s;g?q7Zw-xTE!W~n%Ckl5x;l3u^xrBR@aQ6}J zFTx!}xJL+g0pUI$+{uG`b#ONh?zh1mHMnO6cg5ho7u?x`dslFG3hqC_9VWPk1b2zx zJ`mjLfqOY{w+8OVz#SL3rvi6P;Jygl`G9*HaQ6c4Prw}rxW@o@5#T-n+zEhQKXmh< zUk@F5=($5z9s1_b8He6Cbhn{@4IOIeK|_}r`pD2JhF&mqd!e5T9b4$hLe~}gs?a%w z-Y9fGp}z?oOz2TU7ZUo6&`E?|A#?+w-v=E%=-EM64*G7;Swp?E|G8t(|AGz|^st~y z1$`*!G(j&3x<$|rf{qXLbf9YkeHrMyKyL-QC(s{(4hZx(po;;03g|>YuK~IV&@X_F z0POi;R}cGk*qOuL8+O;Qe})}0?15pI3;S5uslr|qcAK!DgdHR731Qa<`#RXU!QKpZ zU$DP|9Te=5U>5}Y9N5XgUIlg|u-||k1?(AMR{-z(;hjCacZYZ9@ctX#VZ(c9c$W1ia z-&f!}2YhdU-~HkDclaF~evgLVh2i&E_?;AfuY}(X;rBcE9SwfZg5Qxg~E8nVH+hQyYvBASA$ z2wVON^84Bf(iQm^Y1#7^>2_I0=G&JL4xS}M@A)F~w&xGR#Qg`sxh){e`SZw&F1d~(>GnSn zDbpXwZ`BbbU1%5~a}FW;OoNEhNI#-h+=tk_?nQhIdXUD8-;ooO-3TtZ3mG^6irAm* zME+~&K$5ZTh{dTkgtx2(IjrA|Ff247dpsMFb4MBwg~&SO<+)mks1?CB&|seNx7|p zd<;}Xrsw65TkleNP18B?}?5MFL3mA|LYp>RqJ3fEVd{eiLENx`r6F zUqR|-FClWfIgwHJb4WNh2V#4N9Z}^!fvEEzMV#&&MiRIWA`9&M5yRbkkil6-gx0L*-Mn~~UP_*(-{za3SI_*UyF?Gu`4tA}r~mZOPX~9? z`R{hpU7OqJHD=B9`|}O-8cHqQWk)srzDGIz^i~P|46cwaJpO@B)_hOzEX|-Ro=c^V z(BIO7zs1vSZ^Y1bX%Tdr`Ve~H!9eG9%M=$8Loq{|nbrE55yq9dnI&|7L*>EezD>E93R zqX#B4(Xk>s=*0F7TCDL3ZFcMr&D8!k?eD}CE!TXE7SugVi<0T5HRgPyaj&tX*hkPV`UlgZKlsr^ zJG^Q8rk~TcwmfL357KGoCrPvp4lK>_j0=sI-JW*#uoaD;!IVas)2B^-)1rBls?ww* z6li=nX_}h67%h}th_-)>kCvLwOT#-~r#WBa`gekNo;DhMnr10=f_C`#VcK-S0otEC zyJ_65J7}-1HmK+RE>nk}%v0O<&rs*yj8R3HhpA=Hda3s7U#YSVZB*^9Mrxo?4V59f z{NIm0~ZtuB4P5X73 z`nvfX^=&dcb(wyYN>@Ed73SDOy*s*tYLUE7X|i6TIGp=Uk^DMA(e@mn#NFznT<-o# z86~z-`j0hGSTd_9bg@#(<+eP^Ui~b}mBD0+he+T9eT&i^P){i|fJkp=SWk!f;A|4*_(XFvIJZ5Np@x0U=d zqMm#XsU&Y06_YvmbIBge>Es&&iDZt{D6$47nA~>9hwMN9oE(|@h&*FVB0oLoMz$!j zC%-bWAg}&sNY0MZBxm1KBCpmfATfzelTL^HAU&GsCEdQ)N#dn_CebTCk=V9NNelvcBq8SvQgw6^ zDZDX?R5>3+;y?O^w9WgBbXLQL=^0T*YIB-xr2_sE!}>Y+_iN0do#3DP8GhleCN zeLhl%~;z;9Pr#K=V6BSkgH_=wf3a zobO)6fAyKeFG`H#sek(MuF;+NR>>xO*jOdL?MWft?Q|C2BRdJdB@&6BX!OU6sJ+B9 zenIg3s(5^Fy(9jYkOkf)T@P=1LKR;{lg0-Q3gN#A-NAbYapQ9*&*BvYj^lNn9>9NX z+=;I{u!_4b{~O2jWE7`S(2F}Z-i}jZt;enLf5dSZe8A-sQ*pI^u{fo-!8pZyZ(LQS z2QIswh&$Qjj9aO<#Hm&3<1Q7b;@sXz;~oSE;b`RBI6nam*## zSb^tD*dNN%*aNJ?*qpX5?6+5+u{6;tY}|YSRysNZ>mZ$gJvewL}$Jy*WOz1=I@om`*fp7CFVyTe^y_dE+v_g8Po?lT`;++)bEO+?UTwx}Ul&;NB{H)16g{(|uItq`Ry%v%8S!PWOs?f8Dw+&$!W!47(Mq ze|38@*y#4-W4T*b*atU5*AzE`c(fZAOMsi>_vdah(NwoWV~krlyS1B9hrU~Yr;3~D zT}ii^0e-hnPj9#xT)yDuU47h5$8f(}>D)G^^wAl9KT@bU5;lW(X<-~0L zK7qkqIe_ss{12n*z37@(FyUG;(C3QT(e7G*w#KzipvcupCBwDYG|u(CQ;@4F{-tXu zndbV6jB&k;w{mrI(sMO6RdU@_7IT#mxaa!tEVt|Me;ls22UuKr3m9DoyjENU4QE`W zuMD~DnET@5lw0TW%B{pj=SG%G_m6m&J;A{)za(C{JpDy;Y4yjrwA`_B@o3X^nYLAQ z*}Ey?GT?p3#r7nZOKJ?eOTvYNE?RLrTt1#!avt`Za4u!&b5_T+I>+}^IcJFEJG;lG zI4^BPI^Wgub>>NV;yk{BcQ%r=clPr#a(>#P>U^JB(m6%uzH=|_s&h*ghqFgNi}T7Z zM(11C|2kb$nsS=7>vyvEX#2OoUhP!;Hs9%0PKwjn;z%cQnU7OcsfW|E0-V$ROk1by zSOcepH_A?%L@}p!VXE*BD$NSBZWx3JuNPd~) zPfWI>CwGG5a$k@mpZ5z#+4~g7YXeS>Lyt@yZO&>qRu)M){#N04oEyICSnI;!h*>@4 zI8Wc{DD&Tv1C}=KKv@3npyBY@VOQTr2Y=c34u7)~9Qcj}JE-7ZIEc5C9S(ClIh0aO z9K=7XIlMg~=`e20=ddgOiUY$iyTjlqW`}U~ZF@e?dHbB)ANGd^zS=7@*4sN@F1B}* zOt;rHj<)B-`r5a9de~b9VD0-Ot?h;4b?qM~$lGVc3fWhL-Lx-xbIv{nVYPR3WVGkh zTDJQnFkz?4-eXs{++@eyT4qN~$g<0GkFy&P39wt54zhLYFpWo8nkWw_+@Pq69jDE@4IGO;&j@!@-wsTC$4Rq8v2~gr}kl+%5z_A zKK?^|N^H&PSy_f#?~y^ zD%RBjqSl`7yw=((7p(cYj#yt^XRyA}v}h$BGHPXK(q)yvS!Xr>qrgf%Hrc8{H_S?t z`IXgj8QCh+-oc7?#L&v3P|?a=yD30m2c>kl$qLs7I;+Sdjzt6;>7N?qDSoCcYE$Xh?S@dh@S)3)wS-cJx zu;41>w)ox7X7O`;uf^WARdd5VQ|5!LJ?8#wjpl^Y#pbV1rJ8>|9&WCB@Rj-24zl_1 zyq)<YD zS07@w>G9m`{sV$p_AhHQn<#BFBROfafcbl7`+_f-Rq-7&EB(S~w(7WOO5FL=R50+1 zslVxEjHP$n_?oL5Na|o_1vWDCc$LY+1kV-P0Pgir=-anw!0>* z3Y;d>L{<~_gdHX^4RgknnL*>M{jJ7=Tpx|kiewlYYeX9VweT{YawQuJknM~|5nbb7 zk7bNC9`PBUpjA$3ndh_lXxsfj#xd|RI>RZ`il$A4Q_{(28D2+$H_P3_tbv zs&wc-4yn*5_GRkNb42OS7Rnxy@x7C z^bUya&~xDVt!u>IuRFY>Nq2R$P&cXet?qb2pzcSShwgPvSKV7&#=6bR3c5S11$5iJ zxO4^7j_C>=VbJYqpVK+^dO&AJ^0SWVYLSk6>N}lFx;0|WY16O$Vy;p9C$3O?{BM$WAU;5QYW|V-l%2D7(13yV zjEbE0?=n8^m@5~xw|ow3?_1o`s@0s)x}Eb~OXWbF7Kgx4@&9kH%^DC z6UIH&{j=QEA7M?@MfnufI~V!Yg|jcIQ*2q)eK@w&$gR_ALiBHH-P|>5@*VHhLI}}n zOfV!YPfiwsz7<1 zY8n3<)k|4qRrd=vs>%Kus-Lz+RO{`otA1!Zsru?Jld3|{yvp)IzshT+MirK%e3i$m z@hU^|J}NiDC@S_pZB#<9YpUd9L{;i?ud6gHoK&f}$)u8MGq3zIs$bc-twEXlzkKEC z>+#A-+HaI~X=G)lIBVs!N_AzW!H3FIt5=nu9zLOb>N10J_Wj>VlG43O-_+`q9QAXR zc9_N}g_?UQ@tPBqT8u4}Ty<5Hj;jbNRf%&cVecGKx_N$Eac=*#V#%K_MW1g~iq6HE zin?LpipscWimJ+Pil!Hh6_LMkis^Ot6ek1EE8aI@Rt&kks<3DJr^4&>Hib(Lr3&qr zlNAC60~8#B5Cwf%2L-bgZG}fk;tGW-Hx>5%Wm6zTFe&^eJTITr+b3^BsF#;!`5-U# zHb&k;z)L>90WZHp$6VfHSV{h}oq+u8uZ!|ME-dm>v+Hu_9meJ8KRe`h8hn(?YDtlM zDiS33G~tloh-*-OSbvX?TV zWOY_w$bJ;Z%Idu|k-ge1FMInSpDaf4yzIpD1F~Tie`P$DM`Ye{x5(_$FOrFWo+v}f z@saWCA&ofdDW!+M#=~Yrap&3&89-&g#?Vd=f zC^<{j-qe%wWtNo6oV+P@zM4&HI*d_jzw>X&Cn7zP8V746X+2qz|L(*k2kkv2*?3$f zv*+|B6SJfwmmO|NCSN)wS=7fQdChN5VoSVN;_gC?#OLU2i3ZsSiK}y-67zws5@+ul zNPwMtuw@VS>cJ*G*qsO4@?bw6Y{Y{dc(C;j_T0f{JJ@9h+v{Lo9c-wBopi8;4))H$ zra9Ox2ixRee;jO#gB@|O6%O{m!R9yE^#gB@eARSfos z!R9d76$abEU>_K40E3-hu;mN(dch_y*xd!&x?n#SY~+F+T(ETu_H4msE!d?6+p}O_ z7Hr6Zomj913-(^YrYqQO1>3A(e-&)37X8~%1zV|L4;5^lf?ZRvT?+O|!3HVV83kLS zU@sJGf`Z*ou6f?UxIy0uwlvbZ>RGAwkZGYO@d8H zup0@sA;JD5*mwjxj?w?N8vk#P@!#em*i{7EiC`ZQY#@T2L$GBC_6or!A=n)R+k#*} z5Nrg39YC=42lo8HW*^w)1KWFGUk_~Pft@_Cg$MTTz@{D8tpnS1V1Ev5%z+&_uoVaP z;K1e^*mVQjZD5}bY_NfyHL#@y_R_#68rVGp+h$vt4VE+niT!9@cuvG>2sKDkF*p>Rf?WlkIP+$WJ>^y-j zC$QH9HkrWg64+J(`$=FU3G5(&ts}5!1U8GnE)m!s0{cQ>LkR2yfh{1g_X9S4z-|xN z<^lUVU}FdD=zy&pu!jRSZ@{h%*scNlG+=`U?96~I8L$@vHetZ-3)pr6`z>Ij1?;eZ ztrf7R0ya~?E(+K_0sAIk!vyS|B5?3$RxKHYvdF1lX1U`w?Ix0_;G5tp~8@05%)``?t#gwim#@0@zRh zI|*P50qh-sO#`r70JaIh{s7n*06PL;D*)^P0P`QX{=n`BK0h${fwK=Rec6s9=Pzpeh0ogFx-LD4lH)ytpigXxaq(~2mU!Q&VgeNta9Ly z19Kd>;=m3EJ~%MIf%6S4Z{T$UlN-3(z}5zSHZZb*gAJ_f|MRT>nbp9h2KF@YrGX(0 zoM>P{1MeA_&cJO3HZ$;-fw2r6Wnd)(4;h%pz%>STG4P3jK@6N>U1@I!$S3LH>ieFD!Dn4Q4o1okHIHG!cCoJ?S0 z0`C%-mcXq9HYM;UfiVdjNnk|+4-%MfUyM}EnsB<4-1%Az_kK)74WHmK?R&CU`YWl3Ybv9eFC-<@SA|q1RN${ zEdfsnm`T7z0`?K`jeubUoFZTm0dEMHLck3IHW2WCfbjzyA7J$Wj|Z4Lz|{eE4)Ae+ zfdiZyVA%k#2ADL!odLEC@MC}x0~{D&y#UVzm@U9%0rm>;Re+%aoD^W80Ph5tCcrHL zHVN=YfH49b5nzP?4+NMW!1Vxj2k<$7!2z5NU}^lHm+{ZU0PY2_Er4GEj0)gT0BZtx z62OcAE(EY2fbRed2jDaSivf5Gz*GQk0p?#c8hOycgVr7N?4Vf(T{>vbL0=9Ua?pu`798~6py>wPHfXa! ze+?RI&{2a{8uZYhc?MlGXqQ2s3>sw68H1J>^unMC2Hh`cdqKYo8eP!gg4P!Fw4j*< zT`Xu{LEj1*R?w+}78UfSpeY62C}=}L{|OpT&~buR6ZDv%xddG$XeU7*2^vVyIf9lE z^opQK1l=KM3qd~!8bQzjg4Pf8e4yC_T^?xfKwk$MI?&0177p}oplJi$8feo%e+C*e z(2;>w4D?{2`2t-RXtzM01sW{SS%H=c^irUS0^Jj6n?Sz=8YR#nfz}B0M4%Z0T@Yx0 zK;Huz9?Xh%RF0vZs|d4QG!^ctYa z0Nn*>D?mR18VS%rfYt%@44_#6T>@wiKwkhF0?-M7769J=zu4SHm+Jbch#sQ_+D8!kCXiDNx7Nib#*wPD6YHmck0B9n zw$@-bv1|4xGNk!=?fBRaM1? z(6J~+h90E+Ei5ZUiZ1*9y>_Gk8D%A)J&1BvE+RN1`FCUKJ!13y+TZf~*~nBaE82-5 z>FLN?{LnIWFco>>SGW9zIR(Ky%0&B-S^XqL&xE=xL{9kEnOH1G2gV_VBJyZg5?dUF z1fM^-ELt0ZoIJ9s;*C8Qpx#u zLF>2%LgE})s6$kd9L|~r*vl+PC?FY^0v1xEWf2S)d4aMhg%op}p&gB-pC~fS!?QsB zCX7_vIlhp=E{JgRZ_dNMM#uLa5-#2}-(GziNs`T(w^-mogjK@O?xsWZDssZuW7&L~gs>LwlUQ_%le52gCfCtW(Iv*Hd$({F8`mX!{)Obg22Ph+1~c+@-8T zh(Ou1x$*b|NO7YR+V2!ob|J6E1?QSf8IYdk3vUgpQPtKH~4+Re~g|QDUNnPu1kaTC-p49Yh(K8 z_JemfUBxTu z!I`&aYb(m=FPcuEJyBz3KK;?|v0ub9x%B6kn}12X%%Y1+e?U8B4 zXLQ8RY%~8O+SgyAy;6(GzcUDB-5Kl01o|>jWQHT!o$i!)8SR*+>mBIHn~T#7-8OXR zYkkv#Ll*RPz3OS$Hy!wCKzA(in|?Q-Lsy?7PMddX&>2sgqTQ3wdj)#q@KQ0=83UFI=Y2 zx~ojN_n)WRW$~f?)Ke)o`sfv=De;A)^a<;k$&2AE^qQnEld!8&@7+yjxg0+ki)Elc zws|>uc<(l?CB+r(t;{)>X}ftvCdE_cX^XhalQLI-(W*+A(GIJE<0oymeBZ=f-$B|V z|LTdB%^uo7Zz|en;Tqd%N*L0_WA0{}S()j?hbQ$kqkXbyxAmI4oOb-(@rk>*Vp`|& z=J?LiJQ^Z1Iu3iTV}j|lnCaYcJ@YQTKq_Z= z)X0gGKGfG2J<&ey8~F+KvykQpQxc6D-zYd@)kvU5>v5vpT*WR&>VC??a4Cm1mCoEV zJi}v3Jr!3u412msDNSl;lkaeWoHF%~IdQmHR+cKVZi04pru;%w3m%?fMs7Z;aMSVO zfupymvbI}8u)n)Ez)4+7Y97ih;h=^}=MC8eo}gkTBGE37aDPAb6OZFi#||c{*jJ4q ztGX@9GDQ&W_3lb8P!2Zl8**KrrnnOp2FEf+DMvYb24TlXW&BS02h0sdCwEXBZukwZ z$$X~l9w4H9pDD4NvQt8K&|z;8#quxDV0KUrWnab#wELTl`S&0H^!UISM+_z6Ys&yz zNGL_mHy`Z*`6ynL_j{iWoE>{gQK)wskW!>mcwcCtouJ%44CTlEO9Ncy_LTRn2L>ea zEGR93i~X=4Nq3l}RTK%k=!c8GOKjFg`7xV}WaP4eE#mwi>H z%jDn)4B98wnNEyYYWdpp(#w>e!GnJo` z<#x>V!2VIC07teTFYkF}=}eC6d)LFvY(tj&;)8aP(<-{;-=9o+WTsTfv*j{9(}*0| ztds}sB@abCAg2^_LTx!Tcor}k?)5KmPrQ7T;KVQ{wBR*WI?-2%Zfpg{iUIAE{DF6IQZ+o)$6s9 z)D^SQ9@BiNf}}wD#|EA*A|3L#{dQ0DJxM=Z740;o^5RG@N6&rxG!RB|X59PDpTVEh ze{sGW_M7KKJV++?mEA*HWRkm2O80_|8|iqyAKG>9p_`NT>@n{?=%G(CxFg?f^H`lE zVtO0xJz3nuNfjS=cAHr|Aeqcfb?s8UO$y-r(gizEg;N(u6>k!{W>(oq#kF2tBVP`a zl>ft`eP}aj2T77B*;OsIN=(kb-gSt1o|v+H6zxXSUJnsHDWhN4rN0r)E1JJ1thW+} zcIBfz>8f@)u_E-@*W}H7;>DlNU$bK}i8pw4(9X2!YZUQj8`sxCyCC9~3oKt1SG|di zxRp-WpYrXa68Bzc=*;zUCnl5McY5z}ATD%<@pPl&9gbR1R*BkYs6L_66Q!{>x++V?uD4e5lD0get1T^zy4 zZWr3mZi`wF-ahGWe|b}%fICvrPCTJTU`|R#yIQZ_hlH?ZQhQeZJ%X>LdHaLc*9q#I z@@Q}S;yOD)~Ig>UBY)1d~733P2;uDTDwsow;;_Dh`TA7}O;ADL&%z5@~Md_{4__?~IGR?>(jeme7ZE2n}2e!%?{ z+W*!cpLxFQA0R_&FPk!)-Ifc1QXg3-@ROoOZ>09Ia0m|_h6*FnPQ)XtE@>z z`{Ibm2wc2Bxw${n54T0JXbvrXj#IKxM7v{LqdTrq;!JZ`qaAMb?(XJ$wI;Z;SLQy$ z9=R_|0jG7e>hpM%7|x10?X%7_C1KU17sfnN&V&{&xsR*~5?a z%eirDSi;eLpQ9b-usDuCO?!C9u=p!|O|Wa$%529Xl9^2ptn09^v_hI<*vhcswvW)> zdBQCj+Y+eW)O<1;`zJ%N>27fV_I$%dw1f8iO~-~a{cXfN!D1&a4>b<5+GEA#8yaCB zEqzf7dnP2JQRJ;WHlgBaV=1R7_Wq0$+D%IyzJ~Re6Kzy|d=9Hm;cgt6IflKT#ftXS z;rahzZ*Yt@R2*G)m(^)$aCV+{CkGUuoweD~E_W{0R}IOgP40=B?hVA`3ik(LhG>8N z;cA+D@fDti3s$l2N$w{bPDKQ{XIAV$yX?$W#GS*evtI53&fW7vSv^MD-u>XdcWAF| z`&iTcWeKUCKUB`0a>AlMIQ5}>08SC@xVI~>xZmYJTfeW4!@WFmPkmAytGheHLLKb8 zy-POSbh7Z67Ad%O6L(5~OV@0<%Kol=o)cGSf+!>Yn_WVg%h zK^3(3*X^ElJ}Q5)LPuf5neWNL3YLqi#UJ4ISs>5ogP-o#maG7WS5}qzXG@ z6&622Pr&fRMd$BK4IgjGoN#Wp&iz>9w$E9)F$#4C?v>3sb%(lrJlyxgX^g?>bt);yF0;Dh z;*=o}fqDhHC$*f!rCiJCjIvInE&657GY_2D4Wv-VAU*4xlQ4z7Z2i>{r|XB9%8r@u za>`EnT?&1JEQT3JO3$ZKo|XZ}PsFTJYGAu#5?eUx9(WuraJ*yTQYzSz;yAKjzqI;E zq~rAhNz_A-8hPv(dW^kP#0%?KT+dj#|CWs-mHxW~ItlDfijITxpGu6FL>xV`vPy7a zypDA);i#W*KJU1r(27e*zR+GrrwaX&^A+n35?)fMt3W9pa`<`WREa(B7l-V1rV`%7 z8iz~mbH&hGkfWtK9C%t=9PuO4;gQ+<;yNiGhgh*l)M3cnbaxov>sIWbVeP=OU|7tM zr0X!z_wW4Xe?CK#ps+(~F-P(GBOZsKj6KDBs?IyyPWV#<-G<8hyBuBwHxxNKuGotQ zekfXroU+dej6pqzocR{}{3u+}$gxU$#kZzKi}!NvBi<{Z&O@bLh`mkQ`63$arTy5C z14UOxcoa@k)fA{S;qXR{9* zu_}Ct-*4Y}P!07WmSuk11-Nh(dS4y3V^3r)Jh=CZolWm%0dyq36y@7#sdpBzc_-Vg z_>~tZ>WAA|b*7@e1Z9e57ispmfSB%LXP53+U}bM+w_{BQbthPQB<&)iZWgq7@!3WH zVJn~uT(NUeWI{cPychfJJa_fw3t!!|ZM3P&FRGih9cjuzoeH1jcH7sHFY_m#SKFT7 zi_3p-EYH@PXo~t3<(#3mqbB$BmlI#wc6DFKzj%RS8>4;@buAoOjBP7bNAsRNRFGanJf>KUf4VQqtj~vHrFKp5Cs>!=-+kEU%2czc7q)l^)SY9=$$L5Uo zjl7E5CL6UsCs7}xSTobcf^Y6aK~Rj1cwg^_{0?86-JW$Hpqo)F>TV-782zCFV`)?2 z`|3kuw3ZF06dv_7re^NjB5l7t*?_58tw-xL;7py(3 ziraSOv>tW0YWuP99(o{7)|ys~N1EQ7?3J?OLYjMyTg3)Z-d}Rw zZPi_7^FDO*ujR2x4b%^5XZdcKCVTyTXkddS6Yb=C+RWH0SgJe|$$l1a z(9&@5TK3A%Eeo39Nz^A%q7GVYZOmoyR<&A~nD=K1GFDi0H#THJx1^35YjG$kK1)8= z*P{KnPuBA2Ba3t|3hJ3OiHPp|l)E=np}y!jlTL*{`a z{^n^tI+<~MJj}fwOQK$i^@N#u#W#-3&<-{8<1hDRZWoG~2MhhpfR2hA`Mf!6Mq375 z>##YCeOX4;^&RGdS5r}6WvO+@?D&T#8KV(xX7x1J3>M1@vs8H_)Ll6_8DqBbi!bAE zl8>45C(aC36U2-)ng#V(7;25p7WAjmd)$@HZawTypW}FFmT>VC>a+}4bC_|jN2M1q zF`GS{ewE%4yJ6}zKtTPL_NHFb))uw&0)r;gx~7Ne!{f!KYfaZs*M(^*%=AbXQ~D14 zOVjnig*3@OMANgs2GgMT5Fz7<(k@l=nR1HR{8EKjP3!GtmU#%a`_nGCBn_AmRJ5}%uAEW-%R18YWgMr|$|xZCYI1n^KBLpBCs8Ly?BIl)U_cULxee08PNyfr~`pHT@sQ;sz_AJj52TbsKbu=vM3k_PS>#ap~SB(fRb)br84iMm4pvitOI z>h4cW;a|~J9#~CKzci-1W;2lhJtBj}O5JtOnuM~hEL~Oh4+*(>QMz|?;!&r_+>WH1 zK7%BjdT667=Hr~;ct}gv=AIGi7j?b6rR(VZAYtD5jIM$(cfz~d2XxElPoS>R&#ZAB zYpbPrC%dmY5f^{P`=71Wu^#V;hu%@)<7k~4LUw%d4R0MishD_!E|Sjk<8M$0=@EyP zPENH${H{`Qo%b>N@i%pD=_n#{sE=g#WWSD{99KO3=&E+}o#XKW@nhOU=b2D9DK58C z`{$k?ajN&Tw7Yk7#3dI*YCCRKpq`RuCPACJGbS$eqLudA-Zyb+A?n(vj?qwODaZYW zwi2H~Tu~ppwy~mooU`~I?Gx4lsJ}GE@I#B9cp@&&)thL(2v5Mf1z>HgdwKtC{9CeZ6Ugw(Oly~*hn;V zrHpz7HCRR}quVO4Xk7MwAAKdH$&B)rIK5^VM z8ahH{+~}(^Hodz;g_wbxgc?MkJQK*N9s9iRdWkS>fm*PKA;wPVK#CM zx2j5cFc1k{tgnwdRI_m(BhNCFtL_fVj8uA@rh2C$Iud$Wn%JkR``D34o=I2Ld_|YY zd3_^QfhQ)B(9z<)$ERAeE)p3RbwRaN_*UdjhC`~kPtHX`U+c-Iag{x%c0?wg>r^2- z&PTi_RjAZg4o5(DE8s$y${L|6!p_Z8W#C&*#LaSyN~~}~1oXIGs>rKUvObMC7r>`- z?g=&`^~(hn)4!Gx(CG?RSXX{BEfuluF|KUuz!#xa@I{&D_vHxacTFEpSGL``CxTl% zRJqr0CEV2hsq&pmli|?yDtd3I9Hi42-rpvx9JgE?zAPJ4$- z^QGk97;#ebcJPK-K#XPUK=)hd`U5^zaR{HVo%3DEB;6i z3+rzvRK$kA3KL6BR9x|*gh6NQhB;NSk8BiHAYiK~OjHh2KB%b}KoSXq{#Z)pHN}fB z&WAaZPbiuMv4%-WFev)HWe9^V*_F>d3PYWvp?u!83S0ACp}KN83dfJsheEHczxbsB zpIK_Cs0&U(^i4!)$vHCx>2mK-=$NgN`4!}ExP*S>yr>{&ZyFlaa7aNqO)V7qW?2Wu zDeJ7S?uzGzvDunlV+ANFW1-qH00`)ez|=H_>fbv^>Si;HX+bY z!#=>dAS?z$ zZ_O`vP1d8fJJ|fdnCxwAL$H;3yX@Shl3?htZ8IgyMg&C%hiC-IzR>Uuwv49BdLHu# zhCW-wH7(f>NmjvooJD2F-F1S~GOo$qkd_OEZd=&Jo&PY}>%n6Nzhtmq&jdU9ev{c( z$Px@ax9jtnGK80lK{g!WGOEO}paE%584-tXLC|@7;b$OYZB!amnjv_5K_B#Dq|Zz}43am0 zC9QmrHwb!h$_}Q|dn}FxeRNQe4h+~GM6~0R7O7tigpOQ`;Q{Ft;ekL0^}kX~NL!$` z)QHr*PgQ}?mpjQ>D7C5oE^v-HK`JOcERb#awUqi!??C9znSQj85-4^Jd=#xLWp&yj zaFHS)Rp6l&2tB&qn}?)Y4ITulGOkGmw_FcA-ThP2Q|fFWbn42m#gc;}jDZ0nNs{u_ z%K@Ku`$`VVPX<80PQcen(#yIffUc@4nXpz7aQ>j623OUbH;+txhsPpuOWcdEksLuaq)<3aI@4TkBj(|(A38WQ)1{@&9!g<>jux&7HU;>CV*p7!Uqc`eo?e#jrXd^z{b#ROk3 z`SFA)inSF^_;IcAi6u_-`a!SH`@?>*Jz7&(ld;eL63Qf@KMA0z6N>EW0B?xm>Ae|SIW`yGE^ELxpy=og5{irO4f^$V%GEvo7!;RoHn+hV&# z=OnNCHB#qAQa*6_&E)lpBwsn~2R*=+bJ-#kjul^D^>7i@=xN{n$4^C^IR|~A6L|i+ zuE>)IwZ3dSBt&SRi+p1*-w>%V&+vtQpqc#+kt>mbzL77cA1aBw@O4Q1`taiz#TUAQ z)txC1pNm`gs!j$x99-7+bzi4Fe3m8e3%x<)r25118@GM!IE5an|GDHld+qW=zA`pn z=n&T5TN9o&+TnZl{!iggcb9yQ^0f%h9GdijK4JIuc;P!=+I*5PdJAimeDYyq$NziW zDD;7D;qa!MaN6rwAAy-W!W_^4{n>ou5dQh}g%9)$Pp8Za;agQ*QWP50wfFpw)79RD5|W*fkw|4!$VeH5Fe20?MLe=fVJN_p5Od7R27~hnHIE~AU-`U-IU6J&# zsL<}4;Bk`r)(du0{d-A>->6Ly+Wm|@lT_BV*RH_%SkgMFn_c&$xFp1NJRUyJ?rJ;Fqae8{8`CEMM$?TKrH`)&Gc8xt#De6yLn=5r$AMl#~> z*id&oPK;{Kuz4AJFHy8U+9sXMPDDJ(u3lf8Lxrh{*d}M2{QCIBrp)Cw+vE=>BF^MC z$1&@lA=Jd(iNCEIPVP-~`TWj$^T+Lph(G!Kzy<5rosNnA*@@P^XDk!HvL%&eVS6%wl&=UN|d8&5#I$}-P(s|D(R60#ycS>=#l6PWjktsegU zkbpRrW$H()*4Gs$1UO<=kNxrz8pA@Y?$=&RKzz%hJZmex_S6KeFS=HT@Pvc|L({D= z6>~W6#tC#LtZCe_?TbyfZ#>D92*q=U?$r z!zV1X?$pI2uI8bBn#D2k%lK1W+by(%isG|dS6di*-i=4R&F`OQS(MwIjh|LNU><6f z7H|FVyLp0DVm#t--bue>9=1*#KP585+`x+&zlRZJzCSo59`QLH?RT0-rFzCcpYLQI zlIIfdKfc7g;>)Ud#O-|aaLCMI<X?9k9N_|Qy?ko~!Smya&ik&2)0iD+>biDCSGi&w;*Oq3Qd<$@G7y_;GHiNRu_N|zd6TKQ>SrwC zk=~q=XZoC570aGD5_q}2iVZc7HWe5?jzyf(?p-@gW1DZrCbT)4iYhO~?!uRtPA<-f zMf}nWX@e$Bm*Zm>=rx+Gz95VJc=eTu`2}$-;+pp5oigdjIS?CS7im&Z6cDTOfNrv& za(gV|oh~U{ZSwfPb+Ktyi%rH2>|v1G3%^u>|c$S#zs||vA5%L zjDezZEaIciq)(`yV@6`KYAD9872PrM8@CzjX|~27ZmPvR1LOSsFEK+AGmHhZDr1!X zbT9u%dl`dxsta$IE+@?MWAxN+EPs}9Gls`WU4DB;Rt(~-Dlb2jhPF^Iov9Y1aPU3p$ib$!P&y)7*?4 zo#Gbb6e?LZ?W$7@;z$jDKF&gn^Z{FEzWSg}jy6J_DQA(##bXtwBQHJBfXvCov z4tFem)v6MGNuhdihpR&L4$YFqFRo3FMtoYk<%bs^#k-=|7UIRRZGWPS?e{G<4{VA; z+**ruD;H<^eu$E7&|1u{t%%y`GHLO@pl4BtXM1MdyG0rY??tIO6)Y;$xD}=9aCVVK z&gCe?xy?6bFY4|}kJ@YCyGVE{B`QtJY0+)h_$b7`&7WA>Y`cv`o$u&3ETHqF7JmI| z_}Q2dg}Asig|`gXKiCsB=hAV*l(?NyZOOp!guiDL;^q49*=ks;;v6-!&c<+dmwlAQ z5?w=uYKthu(G|D-HCU3nC@QAnlfkyE1yL5+MFw_f=0qXBE;S_CV9gnYsQxuV1OKck zQH!?sX{^pb29WhACyKSPH&nUUBA{OKXO2QyM7lVCvtkdgZ``BtC5J`YfhV?|HwTfa_h=& zy)UOzBj@+j=;ik&MuOj)8i1&M$<)-&LEHrZe zGBdrojr$_&nzZ!P_U(#99N@lf%?mxL9+4T--z`k-bBP>#n7{CBj8i1y0}txOER-*> zh)jLYTo|;|B=VokXJO><;z+~|ZmV0gaPGFbkx8*i3lGc9j_fk;)vb7-6p47kijk$d zr)(!j7B9Q5YdSU*vFhDX-ME)M5r{K*>I=|&NJEDGn(0pPcEn;zp+x)Kq`y&wdc>9>ve5K!h5vwC7&964!9wD#L zJdYQ#B?9q~*UieGH``)eM8VSF6M;C%_yoXSslqrSF=5rbZEK7o zqNf?o3(M1sK>TF;kuII7xtbAu{2HAk8`X%+w#PcZ9?ytCT;&JVhjnKBoD{LrL#$Ix z42K^t*{dVc=?h1^W&4Y!I?MOBhD&B^>a11$6@DXPbndbz-@*}xxo=O!T)z3IaHaA) zb3guj7e3$m)Z7{O%EJ+#d8q<*?!V2C!5<`b|1Hz57K8A4dsMXp)gYQ6{cua#BT`yx(I^l>r zy=HxvX5mM*@R{*nG>d$c!w27#XlB+agd-lcxz8cZj=o9ZAYG`rFJVO1`6WQ}rs04L zajG458Ee+NQKjU@dBnOb6w#`pR!vi#@AHPkad z$`IE&-0pzJOq18LYa9=aPs1-|ldoE85N}Imh<9zT@t;OW)I*uB`=8mDLJMTpWaaGA zEq7&zgFVu8W_ITC>#~~~F|+;juE>tLFlYDZT$CX`_SCFZv!Cf^$c}t4m_52AUFJJw z#%v9nV=~0eKDzshdQ)JcOfjZJ{UjMHE53bM-TZ8%4DqxZ<%H^!yKtGeNr1Y&zC<>4 z$9nbcI|VYt*wtr-g%)=*5?TYtq z*-|l~_WIUN8RBvm6>d^{B=nR?zL=}Ue%~xRIH0X&?d2vzyl$~&v#PzLvyAHXR`u|s zHL@Fwd#bOT9At>&ZFDhG_16wd*}fv0YT56Vvi8s0R1c9RGQ{_url6<#^8R93+QR9o z_WKNEgiVLaVa0_q#QpXOex%aE(3WiyUsP#ZtSLK{n4t3EhnfuWz_;D;Q`yFvDSPnD zNu}9AK^FPhNF`WFUWPc~wu8O16pP0XE>@_YWp!rcpirxHmP_Q|LBtP7o_pl8N8WnG z6-OR=o_OSgN8WeDAx9o}cEl$~o^|9?N8WVAEk_=7$~^Mc!7#rAHoCb&RMcz}y zu}2AlzMcz=vy++`3RAB5OMyIM-ce}krxo{|B>ep?ctHP5ADN|hY$JokXH}+^U#hL z`S8%L75VMZ&J+3Ske3em=a6R(`Q(r{4(-#B2M+DEkk<|Emyo9o?Rk)Q4eeWyM-BPX zkQWX4&yeQ~`OHu+ANk2pPaXNjkXH=#r;#TN^@)-93;DfJ&lUN)Q127p`LvKX z3-$Am2MhVGkk<cq z`y2fZM!!eV??UwZ4E;_*zgN)j2K4=nzDLpb8Twv9f8WvHS>y{re|I4712R1zw*#^{ zAb$fgHXug>vN9kK12Qil*8;LDAfEyfgu6+&jfDG0xN(F#Mz~dkdqlW7gu6nx z9fbQpxB-MaKe*+Cdp)?xgS$Jpt%LhHxRHZ9IJk9#dp5XPgS#}iJ%jr)xFLf(F}MYT zdoQ@@g1ara&4T+YxUqseD!7$`dnmYhg1aWTU4r{0xIuzDBe*4kdm*?9g1aBM?ScCp zxY2<-9JsZCdm6Zzfx8&EeS!NHxM6`i6}Ux#dlR@Rfx8j74T1X)xbc8H4!G5Tdkna_ zfV&E~oq+oYxPgE>2e@T`dj+^jfV%^@Er9z0xDkLm0NC}1eSX;4hrN8*y@&mJ*rA6# zdDw-AeRtSthrM;!O^5w+*fEDaa@ZAzeQ?a*ujQ9YuKfReQDTguO)AJ%s&2 z*dc^HLD&U^eLvXggS|c2&4c|r*s+5>I@pzieK^>8gS|G`U4#8J*g=CmGuS1AeKFVx zgS{`hj(vy+lKdRc%z1QXn1Re_hfi8hIe6j`-S&ic*BKvT6l|v_f~jQg?CeU8-@2z zc;ke3On9q=_egkigm*=FJB0T^cmsrYK6uN6_d0l!gLgN0TZ8vAcq4;%FnH^N_bhm` zf_Eu+dxG~Rcte7BB6tge_a1oDfp;5tn}PQicw>Qg6nHCv_YipVfOideyMXrzc!Pj< z26#(=_X2nmfVn@+_F;YxGkTcA!>k?V=`b^gxj4+eVZIGBY?xESEE?v`FjI!PG0cWx z{tGi+nB&5%7Ur=qbA`F;|7NEX`6$dlVa^G&Oqf@~OcLgfFk6KAAF_NM-`ns_4d2c1Z4BSP z@Qn-KvGA=5-=px&3E!3Q?Fiq8@C^vxdGIX<-)rzq2H#!qZ3W*?@QnoDLGY~u-!t&d z0^cR@?E&8x@C^aq3Ggk@H{t)fJn>PO_{lp_cT@#M* zj&X3RbsRMR9tS_0CVXLE$3b_^IFS1^;SGB?4(!S&ykXDAfm!i5$S)WNe{YY2PuIo) z>%urFJT(sP9vugP3FDwBd>m9r#z6vm9E=>8aE=FzgN|(z4l>tqaAoy4NHQM>hDPIn zrZWygW{m^o|Hc8OZwv@p#(-Jf7&!B03>1}&f#lpVFzezNa84Zqi=xLsp>Pb09T)?> zK4T!mWeoIKP5j$%3>2u30mCU{z^QW-C^w9Pr1DYluwWFNzBCF}92o^%augh(j)ECJ zqabkYCpWTNH+X@XrLttb7pEW)FfniGx6nJ_ycl8U+8A4T3I(L2#jY z08D)`0JJX+fco$O;Jt4ENLCL3uek#g+@gMzV>;a#i z_kgsF9x$ET1D0*<0i!xSAiT31b}1bpwN+T>#{FfyB5j;J&*H z6dHGdFQflJ_M3meJONG;t#0U^9NWP{sEpXEnwcw z7I1>w0$y0RfUKcrU|rMFtlrZt1Wvfm&y;Wt>|@f$=b{|1?Fe}S;Wzd)1c zFQB6O3$(xc39t!J_Jgex-Z|x;z~l7~a5muwxajr+_)Yr(ic6coXIT?Cv!)4X4>y8! z`HeuAH{qo-Z3KT>zJo6pzXQqM@1R`!J9u674akzdfuAnl!0`B2@TA}?u;+XQ!Ark_ zHQyURS$YGI_iO;&@(tj~qk7QDs|QU>>p|+*Ixu*w4k)?TfvT}u;C81La6)T=yG||m z@TLaL3arOP|e*zp!zOn(dJtbGeswY&jpDQ`f!?Hlm!>uXRL z{TggHc@54~Re%gh1#s7`09Q-PK_R6aNR`V$d+sZsvhx-AIaCH{nPuSo+A@&v<0UYR zc?nocUjkbB3!ue#0ffpgK=iHWz{T@9DCm3!Y7ajHw^lv_R_{syja3S~l}ka}^{2pk z(^Fv9@&q(QKLHMgPk{U5$3Stn0Wh8P0OTIO51LKygSXELL8yNr$muEo*|7y+ z=Yj%o_f9@|;+hX+_4hy*=N_0Xe-HdVkq2lddEi{hT@d4a7wG=F11RD@>RuY9C$&s;*bT!22uUaKIJt<@aUqfpZxg9L@suky)Tk zDGOXry9DOzUILDnF9Nj{7s2s+7r^V)7eHR=dEl|>JUCu?4jkEe4mj4I1sOqSLH6%6 zfJQ$9>N_*RBta(lFmM|9;itjj@eCji&j6}ZGr;bcQ(&jUDIk|{a>Cnq5^$4F01M?4 z;8Jorc&VHYPA4A+2Fl05?xZxZZe|*&k52_l6;i>Xm}8(y?ier+KMK~39|3as5g;B& z0U7)h!0kK?25E`VsZ?~=ex_arc@G!ZOZod}xp62MN=1VCiP zgY66AL0xJb&`^p4lOkh5#!w9S!;S$hzoNkj|7b8&83mL!MuEx)kznJ>NWi=p0bH~q zz}tjypg1lAeHQ{lraV6$e1W$^&3#>VD8R5CRDQ5KvMa4DRX&gI!TU;P&spiSM#N zz{}nTzRuhSh8cT7*_%DUZN(lSJrn@^JN!ZC7Jp!Ub2l(n+6_L^b^+5@e!y;tALxtn z1tCp4L4?yzu>G_T_%yf!DEjOG9k;iGXr=AoO_(=$`E(oLE!YO$ioHPndrxrM*b^v6 zZv`vAZUJ((TR_}l4^Yy)8C-GN44l(9fus(15bxp+Y)`v^^ln#h)y);q&uj$WdR&0K zy9=n#+yM4>uLox~t_KOH)`2A*&Oqcm@kw0^mNYwo1bZiNHqj9rXjlUpR;&TjWUE1A zRN(+!R z-vTsK%t39Q8327r1}W2Jbbr!OWdnVBq*1kXo$?erQd6d^JE? z`fM=tSsl!pqYggpPy<_!sRGG+6|h}J1vGlh0(uF`K=q{(xFe?ormdX`l!zIiv_KJ< z^eBLhD-?h_bvj77I1Q9E$b)lQ^1x!-)Cq^H9AK3G2Q)^f0H)OxAYn`fR+lD$i*@7V zQ}uB&)qRZAl8urc`6Hx7`!HFqKTK-)4w0%!gJjX;0djs{KWVb8pX>K?H^LY zZXu_iX(ruX|0W%Vf0198{35Ma(CZUtqU+P3j%HMh0KMO71MZLXOm4CcV3}$Nk zyy$U(e1z=FPa%h2942!=A0l;rCzIBFN#vBNNu*3Yk-V*! zKptBWPcB&AIOJ*z zHhJ8ZMP69VBm?2=<>?ONH_K=k!0c2o^KY1~DH<=!^i*yY1BaiR(CC>-!B=_$2A>a7! zAUk$!Cm(O~CSA5}Bgsu(Wavgua>}}`0|52#6D-z;_q5A@uw4cyv~vIu3AGrEn7|gC|*V8=Q)t8vh7L! zSvzu1sx3JbXG6M@)}$-fiX7T+N$&BpAO)Mv$u*8@cAx7y^s2U=u()*Mplh$i_L*C4|~XOm@K>f~bwHIlwam3*nJLVoU7 zCQp1*B4?J(B+YNnAQew2lBow3$jZ>^WXYCkWT2Hic~@sDd4IAT$^AWrtgDzz4&I(b zzDOG>?U5>b`h7g z{}EP09fYXnFG0QEPN$kb>iO1gg$M=O64b8r11wk0+Zt0|2{ z&4%y9QvGkl^05Zu+n0L6C9jUydw9YINUI^PZ1_S{>sAx@2R{*8t3DEG*FO-4qpFBi zd)^Z#tt*La<#z=0*Bheg(Q9HxY6bC&R!(r8UlF&p%7_bpUl1EhpA)A~JR`E0r4#=h zPl>m4o)8_aCB)<6V#4KU5kVYyM1tQEfY{bhNO!`kWa2F|X~JTXNX#FJCp@3T5mvFW#A}ZjVvc$=F}pgFD9wl< z76*nC_KRf1lomkX*Gb|Eiy&gmaYDOSN(AIfi0u+FF={U&{6+*s*dso%l;jbo*Kmo_ zF*b3!h&AzVCK0-tLHLeLG$rm+iER=JvD+q$nA3ZJh|1khWU)dBiE%J7-W*8SUfM?( z2JR)E%-ch#SNjv1M|Tqy9=iyu>3)RQlbwVv?n9il+CfzP^(O9L-bQ%u^CB{}Jc-lq zwh&ulJ&4gWP zxx|Fwh^X$EL)4$tBvLnM5R*IA3Eh)wM8`T+g4aHaxR$0&9CcJ8Ry5Bb$is@nL0bjF z>f1Epbc{SvU^LvaKZI*f9>mQq_2a{? zeYm8p2fuo#8&5Rv!u3CP;xthQ9;*Ep*L={1i~U>iq|p|9M`knrZq09ewBaY-K>onF z3!3nPN8j;W|8Mx7;Rd|uL_Pk_rVda0Sc5C`zToyM)wtG;Pxv*rkNDr8RrpWYd;IYH zO1!<`Ek5S`27mmw0=J1P#{&&s;j16L#9#Zoz*Rb*;Zx&E@tb;2afSPjajk77cuh+Y zzE$=J7im4jy>8vdziueR7uMzD8r*yM!)bZA=IJ}Qfq5?e<9QCgbN8(Ybk7akH{v?} zLo*vUyml3zv-%4D=xr9R8FUFZ=(&J5MxDoZ%sGckubjcX?K1JNWf}N_U8iuBKPT{e zl5|{I;W$1wJr%EBd<=KbJA$*;rQoiWhw!RB$+%iuBL1Hw0lzXe9-nk17N5Bw27h%m z3SVUviSH{3$L%)B@Y0U}pR$j{ds=Y(1P{aijY#m3C^3FtS%e!O7vNsHe0=F;E}mz~ z!MpQV_|H{LJpL&iZ*rsIf8SE@8#}^q-P!~AhJE|-1wVuFYm^|orF|b>%h`*|dIRtp zu|NK6co&{U`c3>l^u-+`d~oflJMgS%Z~WJ^ZTOd1PyC?5R=g(818-K?j9-a!$LA@y z;p<~J;=0pZ@EcL<@xTAA!<%Gl@q}?l{5QS^?;Tu)7YH42lWsfQhh>Xfv|8g&4p`w+ z8!hk=e{($R^Gf``Z7cBE6()G~24j3{@iJU$yA=1mZG=y_Q1BJ!4e=#&4e$>sdbowc zLfqxx0(@rwJUp7AgWqY=#*g`F;Y;3X;;i)=IJHn6*EUtdvGXeUVa-{%U%V3jadZYg zm7|C^H%-TZ&osR3*S!k78@tBN*@75Vp&65bG)K$JVas z!<;jFu)dky*dFX3CT;1!+;;xODoWe1Ddw$MTV@LuH=`M=5&goxHvPbkZ*9V+Jot|3 zE&hh}9B#m{;W{jDe=T z<(RCo3^Q_ji5u+nQqnD?wlSQ_sEmiW04vvw%Jj%D7% zE=|tEs3CW-rsuaYm8CgYXZ%epvh6xn;gOBKxOo*5&boqqVP#<*Z!co^S6sks51qp( zf6riBJu^Qc~APr+4Jcg~QKY~56OTh+H4`Dz4C1DXBiP)zr z@mSq|aah`(7)-7(3R|omiH*?1vFPUqv8TEKyDKIzze)_tT`I+jWMT|_5n|md1(;4O z59@E>U@=x~tUQ5`UThTWrhV&3<+V3!m@?VO@WEo*{or^GQJ3~w-Tp!DOwGf-4u8Ya-o{trt*TD?_Xk%;5 zv@mtCCU&A|HdZC4jy-l)#exsd!U{hsVWo3tPPo<;vEB>QF`Z_4tZ(^LEQ<9X_A+-e zR@^%-rP_{3Ur9%#^$&-nm&OL9dQSaPFIlhD>Pffs^^`8@+;yGOxe|si*%{DR%g>bXVym zX?y<#snzoHQnNj0rQZ){N?o32NcZ-hl$scwklyk=F8vvoDt&kVsFc;3B7LHBSo&&H zvNQ%ul=feXm(Ht+mG(`Kkw)4?NuTeJkUlyplZHJ8(wBb;X`K!(z33{H>IuYB?{h+_ z?Q6cYYJe-%H{?hcZDmR8B@C(CMVgfQh9Y$w2$h!U9gt4j6e1ns1xe3k?30d^?vX0B z`%5cl@0M;_?K`2x>eexzeT#+b+c5=aF=d6;wr7Y=OR_A zT`wISbC#adUn?Ej;3%C=SuK5);2>Rl(@x5GXCw9KvXVBcTS}K(nM;@Ytd!OXO{MFO z8%y`*FO#nLyhM7pZ?W{R#v*CGrGfOIx1RJfM_2me(0u8o8#+>*a&75`<~dTsshZLP zz1h;qYt*D;ek#%&fwFW?%1o*Gbw%lv7t^IN-{qx`hvlTVH2#xrTQOOB&2?OIFK|>M zk`7DSj|@t*vil_iPkJSZHQkbr|Ncp;rguuBb^l7*t=c3CoBv2^0-GiKM871b5`ReI z&oxR+?|qZRylRl7Hq=RcyJ{rwrhbu(XnmH{FaIdvt*Md}c~(k_g5FAa{MVAYsB+10 zTAAd{?n~No}{f{K+@((3@H112P4GJXF%Bq-RMEUc4xIeCxdA-u<(Zz-O6~$8R$vAHSTGoM}pz zEND-Yc=a8V*pDBPR8LEhEK@loG1p3xbm%5X0*&G%F{Uw+V5=xek3)pS-dQHGas`r~ z9)!f*8}<>k`&%L3C3P4nagmLuqdk~;{6U1n?O5Bw!e+!!%izn?ludFi-(!y(8d*#q_rjz zCx_*dtCmY8FHDRiCl@c0=<6Ct_RZ0gc+b+649m}#_>Ik#(0jEcmTj7n+{W3GAJuA- ziZ?0}YN@j1QQ=IraBX z@pYW|SWb+1{aaBJ>yzEn`*yiqj@lZ;zn9B+jpWD1w9Jw?=yg+`pnAzwn<`wyfO;2tYX9~87 zpLu$U&n@2~wvgW}#=g0UCHFUqjgM^*r!m%v^IX=7<8>Xy8Uw4uJKougH(#+84*+ZN zuAP=*uBo}$Y3fRGX|0KP^!9Rbd(2YtkpLrcyZIvV*faz2v$}<1=i3X!f~a}o0Kd87 z5o0Z}*Cb8x?kaV$PL`_phoS!|Z-hvSY8vS-D$uy{=PKaqX|@ytqwd>hed#R&N%CefuezbE8RwNxq9x zH+&WCSFIPd)zyfWT&Wh#<$V%8UHw6%KmEPP`u$tcVG@L7%@i<3R5q(p%Zu4~!TlJdA`_pAn z+sR9!ReLXpoDI&2#(rgr*w->dCm1J1qLt~Qncb9Z`aQ!>M1Srhx^i&4=#>37(Yl_kqVqRA zL}_N z(bZfNQDNwE5tz4BH1ck-XhoEvNZU?dRM@5~QaL+cG~ZiC^nI$fXm^38D3Ll_#Gj`o zQhPH?bO0!cxGQIfEWS?{Wv9rCYSzk$O8!k2`JWpX-t-(57K{%G#Wx3pfBpM}Ix~8N z;|2eOCk}K7|ERYMyGs5Da~RFSMRR`%J)buTEx6x><@3J^b;|05di)w;!-8tzwz7{x zoL40bm|rREef~zcj$I*i)qW+Ed-6gkqCOLzReLHtc)vtAC#XocU*VyUl2a%&+?g*- z8@($mzK|=-bjuN1cH9ukj%5p@?5+x(8nT49!!HVJ7M~XuzB(h^$~-MRrFu$u=5D&s zZ)ckD)!;Oh%o!KH`7RN@ zKPVC==?a8nkGMi3f3|Si5JPzSI8E4UNfCBb9uQ_TLxl5Z1PM1@-YYa(7a%NZ*fmiN z@D-|Q_z2(J@)kO~dkN`3wg^4Q&B9-E+=W)RHwss|Zx9YPIt!VYlklYa8X=zTAkDQFToqPAA$*Sr(jLUSAoL6Iza+a zBPdm<7Tit!DDc;-5{icJhBkXwlNdT%rO-_SYj;DKetq{R@+FRm0~EkJY8SV4s->ree(oo8FK~7KjsK5 zc4-Jy-l+*LZBP+(-B%Lyt(YOmy*OR4SX*AOE$Kgj_2kKdO8yvsQS&f=NaVHuoPt!LWmGlGetLnf8Z&Qv91A((;4<%de5Y@YPqos(n5G!POf6eC=w!b?is} z^#1q!l>P7c@2g((E7q3tiCZuEzveyXPm6!b|JGN+=LQ$?AH03Qf9O!i7hJx_|D|@9 zKa0H0?`*!wkMq9HuYGit|HJ4q|5D0D{(|9ie9w?Ge7n~f{93D%e9O$^d>8ptz6$dQ z|H#Kf{PI;v{Gto-{4m8>{wsDA|Hr3re*UV1eCP87KXMwz2Xrytyi&l=wBqp}pJ4M( zk23gXfiyl|8pf9y9pJBy59a5#?c+CW*~5RDvzs5N=EuLs^Wm3%@aD%`dGV*GZQ-x! z+r&5VapQl;bKzTPtmkjyujT7ht>IrVTg7iWWXG>-x8^5pvgG$&G2?5=ui$qD8S^8H zm-65081dhW4Ef1bdi=>NbonOn^Z05%wfVOk=kVoD&gQH2sPd~lX7PP4&*UdfQsfhU z)A)wDa{MU8Dg4tx<2>g55#E665YL{{&$BG);r-U^;(0SVc%r9mJa6qkyk_Qao>l1& zo`ZHHZ;Tytby>yh|3hc$yK{c~0-I@(lDY^NLv)dFn;ycnfEq z;r;Z>;00ek!8_TL#*15fjAx#l!aG`%%)7ogkq5YOJjJ4D-WG*Op8IwgZ_*i($85oP zsTLDIa|t0&=>?CsM}@-+^JDUspQrJ%{)F*r%@6QiN`raKC;ND>754Ccc<$!q9rxv} zY1qM&8G7?@swZz{jtB2_uRHIFy({k=*ub+bb>_uQcj6t{yqdTDus!cxl?_jBjur2p zpE>V%#tL3vgE3D@ZyB#4$cPtq(U6z@Q;&Cfu`X|S=saH8Wo=&PZ%y7?quIQ$P*vXj zEM?xapEG!Ih6+6SV0oUyx&L^}zE0x3pEt&}+%?SIa(sZR_o0`2L#3PBy}6V7FSea~ zwe$~n?xbe!dWWA}BVi-=Y0g)!R%;!1@uC{;-#wqXtn?4utCf}948^xx*L4-#8(0~) z;?8sK#nz`>D}%>eu&an0k@A4+__BbTHFw?Rbf6 z&OguPUOB_1)n#xOsGQ`+uRG4YB|OGWzM8^aT$juhDJOEno#MC~xY69F7b3WW9}aR` zrjp#F))=?%fS9XxT)_SPoXZvVvAD&H7~IF(sa!lFl-qebguCEdAXi>_FZZ&8KX)?4 zkE@a9!)@!2MI^%zf44$PLzA&AsPl&wa|X;l`b| zbDYWtI75GXISjRK&Pl6Ij?A~6qmTXJ z;HQ6c4j2F6?D_tk^K;5qj*(#_IJ%h?ql#hHI0oOAL4;JmNGIZs<9 z9Oi!_PSspKr`wFfsc>a-_U@%|ZV19ScN6w=1m}V{|L*POEUxh9XnyzOl=S*=3>CL? zoELa;=9+KeT;H&XGvMpW8KZ6B6qC*zyA($b^TH}lK%N~({)IJ%QfMeVFQU&|Zu`;%O#&hgqs?287KV4y$)Lde}X*kbLYdpi&{*}Sr*>ZxtwJnW3x#K9C z`R_10tviV=>5XS=^vAFn1CeYnC}VFPBH2|#7+Ygl%vK#1u*-(HZ2KV=J9LoF-ZDU8 zclI4%Z|)6d2Y2sdTm1`QKmNOmJ-uxwTd`$3`^8T$_L{~mY<9yYc0i3QTkg{a_JK-g zc0`3Ed-sb~?DofYY=?)|>~;4n*i&;>vLmjVupgXX#=dpRh#hduko`PSkKGcvfc+BJ zVF&WH*m*P!c4?3rJK1j*TitUe+uKEfy=9d=`#@)L5Sy8G(ti|&Etni_3 z)``EJELvkbYvAJ_mQ&ep*1Cs3Sd(vkXGzaBux=i$Wu1<~_bk^jVsjTAu6qapMGK>Buf#qKq%bIpEibYQjXC;XNiyDNp zCU2Iowp$5VK?``S<s7p1bNf74*|qMh{*sNX@k{GjPvY0IoLFmEQf~(q%f^;wrGbx5=~aoBhXX zP?^Mf)G@-``DT!L<9Z*nD88GS5Z1|@?b6QlHTc8yo%EZjUf;xwFZ{-Qlv>Zs=F~8E zczkBwU-E%j`(Guqpy4&sv+x!3;?Wn(yNpuiM1hSduUEu$8@kWjSe4J5a{Vq-6nUF@ z)&C|l%`%(mIP(hgV$(%t>HTxeb19ijyRcKtq&4ZxjM=Ho&_5~6j^bpdd1?Z4B{i1W zx+aPls2IWpI%tzxEqvt?%Av|?ho zIdi)E3g(2ap1I@45~juko%{%)&n$P-WtM2nV{*Q0F&nOHFsF&tm~GCpn8`{rnXR9v zGpC-P%B-PHVbZO}8TZGA8Ko}<7zu}a8A^U#jLmu-jEya=jIo?%21oppan`YsktqL_ zVfnh2k$$wAQRw%Pk*fQiVfyn8BjQ>)BbD`%5oGy{(KhgyVezPlVI_OO=viODU`@|s zTrR)OIF)>pvB@i&QJ{W>@%`gP#`ELn7-4>yjOTMtF}~FvXXIxbW4H&TFiy@-W@OdJ zGnl7i7~TGn46AuEhD9yGXg?ukg!qaW$2Iwkm=A1*#SsQ0V=I;McxEW$LRm0lZS+1y zhI0Vp&X^w~=DrVOj?kMCV&=(UwryruUUp;T2f8r&bk;GtJ~}e853OP>bhBe@n_|sy zdSK3I<*i_N8yho3KbA0jGZr!Wy!9ELGjtiDPjna#5-mo>3Jr$#FI9#?hBBkYYX*Zc zZ93z|LpjDZ&SXaL;xT$n%@AGbP(OXtxrctOuamBRt(|Tk@P|HM}Zs-e07f9y~|)Fv+AZtvN}55`CPmWpRvd{Pi$>BtD5AXB|(k z`W{WMO^l$Qu{lUz*of2jCQ9hLt%Y>;Z(Mp@9E<+YoKC-98%Fnw+)pnx4x+by*h7DZ z@1}DNed(3u+v)9GFZy%sE%bmAcY4l&jS~v`_4GrzPIMjL)%4&|J38gOHQjil1^q_r z3i_Wz#`K>SOX;USFQThs`t%J8bm`WQb?8mOTJ$aQ8g$_mRr+psW%^jFB7INNG&*J~ zNB4O>w14y7&@L3dqN)45pgDFur7cS?p}k-Fh-UMwkhW{zJ(|OCF6~R|Et=)Z z>$EMeuFw{RT%r|@o}@A(n@$VTKn`cTJ`A=+ClR`+OOvUG{xP!Xl;LeXbIuo zv=$9dn%vdRw0Z|O8t=^p+RJ^;w3@CpwCqR+nw_RCE$Xr*E!ozL=2K=utMgk%)BUrU zrYAL^eN$LS3pg>4mcB%rmXfbQb9GUpJ^G+b>kOJf``$T?c9@i-jn0@%TXJHQs9 znxET8o#)t1bu90oF5KBhEpBY4&SU9$+XCcNR7ZydYIbo9_2aro>Z2D2sUe#P>dQA0YMYmk`uYQx z%Gk-GmVcp9n|Fs%pVWs?{r3h^?|ciOmIdyjW;Xgz&4RtD;Z0kqDZ!hm`RYvly2DeSs``2XHPKCn`s~>p z>ch3OsoX~@)ZeyB)VX&Rs54i{Qy*TPLS1e+PVvherfkp}pme76Pae zB{U$OV*ECma?2@#(sdh9y7h6&-J@cPg`9xG<#Q;k9}LR!?NmzE(*u<6=E0Pjb9*UA zRQxFlz?b6GzMW#V+l$ij(u3k}?M^v#!G&^AWgW$gaHO1VaiF~2VM}@R*pfmuF{6A+ zH=#_HTSjSRE~cb@(Wi{A)1@rBsY98mrA5h=&8Ez0RiQX+SEA@XQlLCpBu_C+oM@COu)!$2!9n4!4Cp3Tz3}e)%)Z(zG#b*0F}LtAqc;(4D_S;V=OJ zPYFrMkzIDNtovrMSgf@N>sWiA_CAq9jxG}2lBgs)Bt;|^E@-p%x69+*7M&hK+WBX8LLjk$;@`e&~&R}f%aU{{-{YIG<>4CpZZwQI$WzL zz}-_g+`6MUxVc=B9bKvrzA08rJ6%(taxN=~vlkV{)LcbHO^#w&H%p@)a$<;R-?lQ*r(e zRZ&18DTH@I72ni@6m~M4!nw&`F%Lp2_9h|}4V`dBlZ~t5$YCdi+GjgOFx*-Zdd6I_ zZNfy6gECUQyJ(>3oz_!a!0RZ0*EALE#mx$Kn3@7~Q(1B8-#SG}ANI%@ldbR-*hnGekaB6ezF$fswnrqvZP!`p8pTJ>^&}clk?}i+o#= zgBZwVYX6KlUt1}|oK_8NNU+kB4^nH*S8uiE=1zj?wq7K>F z;WpWr*$dgS^r`I4%_lO+*kjpa%LlSf`8`=l$sHMTtW0*nqEuETEtZ`qE|i%KUy>a( zxhN~(pO+&D`;onT~tOv>|X= zGXo}b&vKMSzOa??RxD*Yu4b~6kq}u^Az1dP7bx4Uv0e5Pr6sdY+9ESA-y|Cz+9(rl zUoX3cUzHXmFH0qN7o=k&Gg4dNFR4@Tq;w&9OqxE~RX4la3&sOWk)gN%5B&q(<$Jq&0uB{lj(!2*ZrE{Z2Qf=L< z(rHwIG<(+t>FlMm((Ny^q{|B#(yP$pQWfH1spElEDX{c_w7Gka)M+hV%Cm`;hSH*? zs|O>bvA3nt;&(#n#Z|79XvLPclIYU)`^nOk>jdfJ_8_UpJWiTqh?effBBh9EgtYM- zT&hwJlWrMyl=g12lM0=zq!n~CY25*c^kflO3Tg#PcmC9srfX|SS@12=-<(a-pwx~3 zPogA6wXR5pCYL0BnhO$<%Zvm^o03c>eV35)ze)Djf0f8Sf0k&k>yxCKyq8q@cT0-I zZzS}?uOzRETO{kBKa>0$`A<@-TrYu{J(R?uYb3ixRT8&D<&wu&OC{@`6id|l3ng!t zE=hQRi;{BJ^OAZ}w&e8AOo?g63CW(4Ba$=E4oM;hlO-yD_evysiIT(4aS~a`PKmla zQWA4WCdn%hNz(4~Bo1%blFQ?CNrw_e(r6GSNq_}Qegp?d%q3_E9KRQYxe%nf>Rjef5hGvpL7(@cVgC)0kK*_(|x)SXZ+a%vFYe)`Pt4Y4RP?oIg zTPOK4^-p|c{gQZc`@C4kdRn}K_$j_km=GHXN5#Rrzlf1X2E+@wAH};$d&IXNb%{$~ zc8C>yZQ{wv=VGUSO=7sl6R{HbvG}xYt$4tzT0DiX6hCF&7PI6x#nlN#;*Rty;_~c# zamdwN@tyJ?&-zX=?19g`u(izwoYQDNeW_+W8ba)20g6fI6XjTE2HMTirxz{UDEVdB&Z zNAay1TXAlkr5O7ZDt^#vES`J~5)Z!vh_8Io5rc*_#hlU2V%~REvH7nJ;>y`I(ej_a zBDH^iM4#4XMY}fq7PYAS5PjV=F8WVnL?qB05;be}izanGh~8~~CprY^6iox$MP>%A zA_Gvfs2kKM3Io@RvcL~T+29%x16(B<1eJ?yL8T%ugJO|}exc|Z;F4&0d!A^!?m5w% z))`T*<|)x%jpHJy`eBi#YO3hTh65s}b$dk8f4fDz#a$wUxhT=aUvg3Zcd_WpC|^`I z#1X;!7@}i66jA=0Fi}ifut@z`fJjk~79GEj6z!-)h;&QfqLiyJQN;yE(UmM)5%rj* zs67QLQcE-zsYQcCufzZmiLE0lAZm(k;Wmr*d8>-Hx@-{1EZ2l-;J-ql)*qp=%B(PI zc}jSG>bo%Q>o*~+_p7k9?Xz&G{*!RvPOtD%(OV(p{A;27*h^vT-WNi@sHeiW;ZKBC zgvUY@vQ}v1R4x1uQYkdkx-ASW!oD^+Q`>)ip~Y{UlV_7-uY;VuOT3 z{s3XFjgD}ewx%#_NnJ=9QV{}M)(fv!tO{n%E(hg66hVx5DZ9<2_muSg2!eD1)UrA3vPW) z6a+TK32tBADR`S4DQMux1Uo%Ng0Ff!0eFrjFzBKQ`YT8R@ySrZ9T{HmpFdV`&Il!N zSoRj2>hTcVsd5!u$Z!&%Wp;uZKP$n6ftg@<&R9_N8YHkN1qgN?(h=-uYYIYPn*}4A zRRzeA^#XqVDj#!hnLib^z~`c8_-72J_{XOw_}JD_e#@0F{H+NCeEr~${O^z+{=tP# z{>NAC{Kdjnet$wU|42|Hf7Ym;Z!!CTZ`5*+-4A910&T4CC)}4CW`U;P~)Y{`@C-zI=6=7as(3=TEOW^E2D+`BQn; z{OwY6{yJw9{@s6IzGW+rFFvcwm+-dnZLBr;wX>>x)h8SHhR4@m1-+%KONR5cKf=T6Xa$zuI}RwXHmAax?EAx{(*DUeCMI z`G9vJ_a2WPeuwwTq>N`ac9Z8?Uc}oJdxcl*me1R`e4c0fB%23F%jC6UPw^JxN)Fij&))+TKGR(Cy9^__x{KTy} z+snNk`j*R5ea(H>*v8e{_nd18YvN8$)^k&fA96p1*Kn70tGHj<%ebcxmvEK5uX7Qz zSGZoc^SSGUx!g=Z4tKC4le?IHg8Sa{2=~CRRPK230j>di4_8|=p4;_o7ni;#id$qS z=hh5~xTntXxHf@o?wP+dZe1mbTOkbPN_Fwvkrx=Q&0asQo2@rjZ2-`pkreB5MzT6VN3;!(q-`tb% zu)@dTis0IC{KDPv--Q+7yx?2m=jMyUv#u6~lku0r`)4kM+g&;vj=^Syn@*h!Z^=Cx z?utwcmyacf3$ylyo5B;qZ-0&nUplfQT+?0=KG`h}&)UZiUxskP?ON#J=F#NvQEfta z^h11j9TywkxgHf>QQ{p=4DkrB`wa{Kan3P()WbIXM!!Y4U8-sLeyCCSnHT!u(GlCj zwKTNC4^(P|R}$62OJ_EON1R*ZOuPN%_`P4?F!s!F-1Mh7pB_zcaO_dezU3iKLViC7 z?)8Dw^s$?xz4r~r7Wj&@`N0cLHSHrPIgrZ<1?F%+6;3OQ{oF2`(^$q76~<-p8|oNo=m905ImQ#9qzDL?AVNip)`0BYShdqSN#*GB9( z+54?Hcx^LITd6Te3kl+w^yqOGBegks>$Y;%&Try4*ly&QH?HFhQ~$9eC;qS>CeO0p zX#HYW-1yF>cz$CywSQs%;SaFqXFjm&j=W>zft~EDw_mXvyj$4UUq59N1y9&7rXR7D z)9r26qmDixs|dzo?mCr(yp?T4`o&N9p0V1YGsZJI@~{>eIBHO|U`kFa=823fP1J{Iv+FDsGsmL+}P!2)yJ zSeL#wvqt2Ntoa{xtT(X_Sg{M$tbzY)I@{K6v9_e&V7*nj#uA*o#H!tr$LcwAmert> z#oC#Bk~I!I%Cadq#BwuCW^KBx(>D1rRsZ$`vP;m7yIATwuxi2!yf(xkjuzItHwk zGuv6ETeMh|lNziSDr&6t=^I#TYpcxn`<9tI7v`C7VyBr)KYlQO%Ey_vz78`TxP#2( z_n(;ONxjU(S6xg9wu5=@Nh`Ap-pqVo^&j)5bsf{UsFqo1P|bXmQ^9Ohzr{>WD`qM$ zUuDu_3z)mcbD3m*4s*39lNld!f_d-hVP>62Dl@ZkKhxSQiFx{B9J7AwPG(Jd1T$e# z!dw?EU{b$un6Welli5aQZt@{8)2r~z7AThaF4vD)w#l3Mf18zAJLSTh5I8Wuy|rdm zV9c4mwGd{WC74;42VmaXq{9^K+sgd%eG}7`vyq8>wT@|s_{VsD`wzq2V3rYkVv3Qt zIKjZkM;QY>LkuLQpAl94o*{&EGa#p5Gj9KFW2`8iGYong8A|ASM)jQs414fBM%?jA zM(W%x21{^*@%L3BLjk|UxKeb1ab?R{M#P@ejFqn^7@W`}jKdF78Hpwb7%mw}j7M{E zj7_|q46~L9#wI5z<3XN);iMGK*d4)Oq;`=R3{L`MsSwYQs9_oTyZjjWy$FWH2hLc$ z?!us}J1`E$STo{!%@~f}5XOURAcmSMfMK>no1xydg;D3WiQ%5F%-FxWM$ZuarAuBc z&^Ou4(33KM(yM-t(`zUr^h33Sbbb9k`hoqu^jia6^lQity69Rf{nz?tI!^K*UH<$r zonlc--*oIQ{p46Vy*Hqg{-fkNyb6wVIz<(rFj6_>^E)NCbzA$$+S(h zi=E0eZKHKGdemR4?BN2{f8z{wg7lLber24R|9zNx!+nstFYOZ*{JMvFLcfdpRMJj; zai@ivyZn^uf_*~G&w51d_*g@2hgMN9M3+$=9^9m!Syx2;4}Y2ZC?}74umic8lB#b0}fVo2$uJU`n@@qE`s z*{9nTHou}NPPP#gCAoxBSj4An{>-NM>(eO# zR1yV{6+*e+7CWgV|*vb#`57;=F7CB5lS@@Zp+53^q)#xEF zp*qRpq*vsNnx>y#yojv+Mfg!Y*BM z(3&RssoiF>DqDrDe@uzIbnhSO=FlIK$(C7Cgy$3~MLIzeWsi`w8wN>d#y^qzb$Utj zzFnlgh<4JMb1fvT|DKWr6Ah$fokt{vPYnqozeBol<~C{R(G8Npa3M)e;}WUa^#X~& z%^}@9l1X}1ah&v|C!KU~C55!beBb}u#01jW-7%z${3sH!Nk$qO6Oyo7xuo5$Oi~P+ zLPDexNZmK^B+pkEQuJ>mY1eiH3F+ld8sIsT0@LkCX(g7Vldnuk{9lHo^*Z{bcz0dW zJ(eb^>3}-v($$S5+|zZWhLOL-4XS^Lde$?<#h{@X^MtEJtLS{<@r?7t zhqulU@3&+S4~-rrf;OZP(;>;k$3A2Wr(LzzxY zf{=*65Ftc&MgTD+&Y$R%=|lWl;z1NYg%PX!9f(~E*2IQw=EOZV5aN0ah{)#Z5f3G5 z5tFhsh=@{EVn^e8qT|PvF#hyn7;n>Dn61gLuojQ+VJ^hcupRQDu=td|u;BB(VZY0| z!lX~z!%9E2ggu^m8djkEBrMqAQCOQ}O&9=sCk)2E9cHxaM%ah+!Z2Z8LD<9c+_1sM z?67z5PK8|@KNe>9FD)!fGbOCibZ=OrTYOkn;I1$SPGnd?v^4DfK|$DXHYcp%Iz3Ew zpAKE1GO zC$z$@=4pgQm8gcP)vgcQ-Mm7mc)Lh=Ff>azGc`r<{5L_kyJ?iLs5eB|YSu@XbLu7B z^64Tt1ho^==q-dBqNjwsoec!`zK4V#NA3|qvnvV7mu?Y~ONt4h)mI5W>hlSlmh*&* zU1tb4`!WdWqelr&zYY<~7Y`5?mG%&HH}58_>Fgvt21gJu<`Tjcdp@DXjZJ9sp%G4E zi3HQoU_u5JM|j3T5nhSB2}KcbLQsqgp()Xxpq6Y!FiM9KHl8pd)ScERpw8(ME?m?k zG+a?9RA1jn*i*WWu%+T}=_{1H|*`pZJmpKpfl8N3#nJaj3P^5sJ4(wCgj zU0*Xp?|(fW`s!G)2vz zaKxJsp!j8oQTX$aIcj4_L1bnyK{KZ38vjRlLuUxQ~T1Hlx`hu|Zw-NDDr zUI%k^+k!VJHwW*ZeG>fa>!aX-uA1Q1#yi1B?%WR6zH%ct?o?rL(Y}J7x=ywSK|^S9B#ho2~dYi^5!Yjb(QC(>BK_B*M;#jLR4 zNlZ}iMkj3WF9W~e@{NdKuitLL`JbGEUp3nXzpk_hF3K|r4om|FH%0-1)oI$n=Du5k zwJp_xyEHch3l~>{o((Mq{b`*ITB(`}dY3m5l$<&ev?w18!iIeclDPK-Q4KqT0Lrg| z%Dz7j(&}mq!at}BqFk;Ga!kJ))UPNH3MZ5VRl;IL4jrLpz%yv5Icq#bd?+&RO^Zh zx~hi?VlN_s#y+|S1=KkQ?Y(3dl$>lCMB$kR{qr>pN-_opHLqz0jSOxH>iJJCDF5n) zAg6&kPbyx~5{7Rp48s50i^Z>}_~H9(5%{CZ z?)Z%ZPI&r#Tl~IE3w*591ds3m<3H#E@Bu%x@F$;X;0yCr@yBD=<1v9Nfp3i#16}85 z0u`@*2F6?)4-85g4qOcR9Jt5yV_^HA?!ejh*MUE;wFN#(Yz|}v{}>d{`D6 zcq(~EAS_HCSOF0QE>DLCf}Sw~x1A#gzL$jlpIitG{IU@p2<`O=^tkB}Xp#sE9KbpR zMsK$c>>Pmxs@50{upzh=O^__;y%#4n=)y&Qeucvny}(UNn{e^g^|+TmYH{;-?&9X+%5kl3CAgTyYq+0}FX4QX zFW|(;92{3E6KD7A81BvCG#n0>jLT8ogS*!nhbui1jf)LZ;50XjacQr(xV8)?ZZw#J z>)lMi6}$?>xn-bn*Mod@srRva5mi{Hh1=M=svB5PR3VmVUVvo}p2vD#JcFGgXJC^wj$(VC zr()F)?#JqQBx0w3$6$+ZMPcnkGVDnMA-4W42its-jxF*hVX4c(*#5gXtY-uY8wK&k z?tbr%4Lj|OU5~ZHp7?8l{dU&`3siuy5F-F~rCSSo=Y$3pj#R~-n^VHRxb+Y7hW7_k zt}}z-xBkG49T>x4oxfuCj`m~HF22VILf>L^l{zq2YFaQW@~0RVPy@#M^#cs}P&MW) ztOCRRR)TqwSA>}lx{Og;xqun2%)t~0GBH-#$1xet(lE{O$(Xn1doT}r<1n$uqA^My z3XE)Agel77V(tYpF$Ifc46`&8^PLfhp{SxUIki5R5~&9!TNj2QJ+sG*$68^i5a|E^ ztr}wP8~|c2+vs3~AGTor9Z|#VfNj8353QizWGG~vkhp`m4|2^{vO(St^)n>N-3I!zmBe)y^Q{JIS<_* za28!Norx9~97m61($VOtWOTxXJ?Lb=-Du84G-q5~#9~+`!LLi!?s)NQ(N$MR{Rsui~a@UGyWGcfBHwbjQi`n|LT8s|A7C5@dtlE^ILzAqQie-bE|*pou~fJ zlm`DZ3lIETE>`=$^RDoJI9TGpJFUonqxoh3oh=vqDT0rS63YKPYg@**PcG$ zee?mU!mFgtIu2bPn|XKzvTk<_wLg3zp+cp|JxP~|J5=T|0%qZ|NXJQD9VuqRIBMU zYJ1}(%9HyI<+eP8QoYcJx(n+?!8$upr*^zT)vLWgH5WIcuKU%Y*!}lW<4IL0f=(GK zqw)r-5MPKoHIk1CJ9r*7secB=tvQJ*B^*J$96yM9mbMRd4xE7UsojNY2#ZANO-NAK zG(IX6#75cGP*Gn)!ceiJc+~r33~IX`5@lQIi2~wWQ3C@GsQn4ns9zdpDDPq;ln|kh z;=a{EIY(?o4Xml5gt;3~4R))3(@z)u{xN6$hNgb{6&xP-b2J$CE4VY@_ZjoSZ|UP( zzn?oh{2p#-^$X8?>i5B}!Oynofggib?Z=rY_k$;w_)Tsr@=GedOsf|1_!SmY0^A2Q*M7xF#R4XO3j5osP}gVdfg zLw-15j7-{Sfc%xIi}cgeL`GfNgxqPNj0~z=^-z^Y+7+z!#8`b#rNsHr@kHQ8hopdKJeY8QSGaeQ|_AtDDiE&bj^3frr3gqg3BhKKp&IH6{3FVPkw5ZIQl_V!6Fy5r={|H` ziqEOOJwBJ2yM2!JMEiu06+V-%MLv>XuFr!OhR+C^>@)dah))M1z~{sRl#emY+b65i z-RG0Fv(IX=tpHx5xVCz~D1Ykx*Q~)?{qh6vIo)dSho{QD z8OkNzo%^qOo6Qz@QzCP{!@r#I_G4yvuf9Iworg{J)~Mg-&2~xfPA}c%eatA*TXs(3 z4N>QN*BoSdL+2^p(UAo2?7=|qY%1D2s?En6;_KmERqf&pvb6UW7Fc>8(lqr>P6vBa z{^)rtM`?Lyf8Ol9NK*0kdcMw^;qeziESpC_jeaA#&U{C(H;f|wOBh6~j(tSvv)>`M zw!cOU`m`Z3?mR<0p=R8E*-Ea@l7GHsA7%f4Zq8B0DTP`8$;1>|!(rg3+cnY!e z_)&y#F%{vU*pGPsJ^>LP5QC_zjYKS%OA#99`H0mGY{aWLDq{B+0^&~?9>I8mMr7Oh zB1-c;5Es>82w9>%LUY6tah7C?n0*39IM@LY*o#^SxQYg1<8Bqioxybo*O0$n=N`^` zb(#J4nmF^_tN-7KSGi))i}CKG*8uXJmtWayuN1vDue?LgyfS|@c<~tzy)>Ryd!4td z@LJ9-@$ynC@?u0?@(Sz8^@1X^y}C;?y!hHjy;}CCdZ~}@^Rgi%cv(Ey<+WlQ>2>$G z#LI7*=T*jHdCfLay!31cUV1r!UNcMnUblokUOsJbuL>s@ucZriUM6c6Ugk0ruZO>Ll8rsPs`Wi>b#y&NySI8KcB^^HVH-SM&#riU zp84Y;BhPrey!*pLU2Dw4D&~s^^i7|~U;AE>lt)z9F%S3hLmr>i4tPkUi5@SSVmwrg zqCBAcq#lO7e2;l&w#V&Est00%;8BLbd;GbI_AvSD<6%Yj@Yr(K#pCs6dyi|SB8$DM0*Wkz9m*Ky&=HTuVQ*f651e{ec42RDRz-K}} zz%y>Vg|A<2htugT@MD!t@Cz#S@WZ@XIH9%*zObbXen5HyK2(1dZlaqH_lr6Q_j!66 z4$waVf3qtcE`5;<{|Md#x7i&BXSMBs%Z%l4Qi2d}@QMR(g3#gEL?XQ8RS~>FH_uBm}xz%0e##49TpL%yS`~&yi{JZXH zKg!&<_}+9+%qnzm7|M4ac0TVumX_t-*8TtObhE?m)(I)@CC~S`uh-k{?jwtKr`5{c zLsUfWru1<4-WzoHhCrq%r^*O9NV;Jc!aq)5wJLKxF-|67qWMu6g7!7r=s55k* z-UM{lWoo-`zp3FqKda(igHm!QXZ>}1-9PVUW%Jujl=R(gU-O7ttk$4g0PmyQzuVnz zS${g*lrXJsrn|$+t*yq?jkf}Jdy56QS)A5#WA<)#i!@Sk3zw~Pv#VTo?Vq1> zjq>^B`swh5t5y53D^2IKtBC!-zPzt~P;HuCUX$ zT@Bt9yMEQb>Ux}i(N*)tS=WT`nXZo=kGl@Vr@4+iI^f#2n&_H|j&*f99_3ooE_DTH z30zq;w(Eh5RM(UNf~&v;?`k4NyFM%RamDaUDZ|TuV~6 zy9P9Ay0&akceTJNyULEQ!j8UNgdNeCg-HoNVPV9i}$U}&9wSP``s_Vs)xOzHhg zm=f?g>>ZOU24pKyQ~SnyVzYB zaq;~0*~LQdqsu(0+od?O!v)sX;&NU2smmO)-o;{nt&2x(m5c54ZI?CM8!k1nt1kF! z7hV4AJL{sSciM$OJnkYtndTyBKH%cDn&`3sk9En3jdIZ}le+8};k%R>vRz)$sV?nV z1ec1|K$jRLw2Q8nk4s)0+-3E)vkP|E)@29C!X<$Map7kexY#_?b?IH+>LPa8yL(WOxKRN$`^f(7H-Z-acwmDyU_RP6pslj=l z<3ndJX|;1-ez`NZ^QLpt#%s?U-1_w_uf9I zIMrUKY>!T-?1-06@%hb892@-n7 zsrSH1r=8`8ohJHHoUohsI;DHE$boZHwlk+sl>8z2S)BE6UPOE#=om6isJI%aZb!=Q) zbd0f^bzIN->6mn6%<;|LFOHi&_c@xY_d1%ncRH$wUOKjAHao^Vdg8b=^3YMT?VjU3 zM1|w9ti^f?!BF(@j6S#J60x+rX-N# z-o4u$tFLJ~zHZy(*fG7qu~L84VK-{g0TeOgP;%yn!}f>Y9Atw-4*4p54tMQ)9LlM0 z98T0?CUqEv3LFXp*$&8Ps>9Q4f`e6UphN5@e}^lp-VT+f zaEBtCv%}smf>)g1gp>m6K={IlO&x?um}PP$MiQV?^^E&L?AGg>S_cz%KSL^JRAhq^KQC0R+qTBXfhl}ka zZd|cXevxM%KbB)3rj}{1X?@JT8h^;%GjhLu@yP`H+1tD9EnY>~`%H@MJvQ^~0k%y0 zPeEk+Ly`X=l9qN z?#9_ow(qdxjLYoqY!KRw8*%JZyl8f6v@pA0yYO~(C((9MH+<~YHNx%oeR8(@FlTEA z*0iw0SVQbcXahTcuCASa(pI~7XVmQCZ?CsodiKv&Jg{JUcj33~sOF^Yiq)v?U(}%O z0Q;kD@$PP0(y0#Huf;94%!Vf0dp&iwb3gCf>Z?@QLXB?Q>bMu%j)h*ay(Z1GMJDIi zK09~H)~@`h?Y?KJww0gu*}j;Lw{2G2WqZ>&!giOt*cKehwXGC0Y%TVYY}3yK+rGGo zwf$L-v|WDdY5Q{=X8U~A-Zo9w%GS)r)V3T6w$-QU+3twkW?Otv-S+7@W!vYsR&6St zEZXevp0RNp|6$Ym@0$%y>x<28^FEt7&mJ2n;f;-lsLckJ_{>JrVz!KT*2hi0S|4}rx88;7wMLLSt)~Pp zt&hbtTdSr%vEGsO(E8z(YU}S6<<{#PZdxm~7g~S&ly7}^;+(a3@wD|{l@r$cwx?VF zpY^o1aY?e~_{Cbs6QZo+!ll-XNWL|656ime2*o=3Y^e2*!T@V>CCd6r9m2Y+)y?{Q zkE8YXuh!O`zo6Ea{~217HUX_Cw`*JPFx9Yr=b&N@MXa-C1}s~}Q|7D^`BPT>sBtT& zq_0-r()z6qpYFBVl;3F;f8(Xqi>hX;wYn!(#w`!6EZ$aI=?s)xjgQ^5x;|5AgdSTYS}5-N)?f0wTy|i>LEl~}!D4Qm>X3Zg8{J{;`c#7k;f- z=Koo;JhC=xNmre++@?8hS*7>Y(!;3VvedlSa?P&O(#Q3sr5Mp{8RP%NQi^|Qi6T~8 zZe)~OR&j4yq9uiv4Uzel#>9 zWx!3IWo;SLQsXY!GN?Aha#tPBGP%*uGVZyTW!OtsOWijPmW|z3mb4G1mR1Ov^c*sV?kQ^VKKjM%pz6!i^ZI3p9OJqkHxvIZ!8+M z+AQAbKC|cqG+5LaJg`VLyldeKDYNJ@yJH^btZ56R-AZ?MHO5^J#mg|wJQd0M>jhgsyH z?JayTmKL2D6N?Zm$f63n-C_l+X#vA+vLN9$STJxa<~ZCRb0gfe`Dg5;`7!LMxjuH# z{4D09`2xDz9EI*MPxNmw&p|br=lRu{A4T3b=lb3;H}tt>{sM8`oZ)rZyvyT)xhp)| zJk>43{66f6`CI3M<{upQnz!2THZQb|HWymU%{N;L&99ho%neLw<|)Qu=Ivm-`33{D zITYYyZl?=3H_~!8U)o}8-k@%79;s?8^Z5C7=6Tc0W;cJ% znO&NgGCMFjZie~t)oh`^-z?`tubJMvPP4;rUYhm2Y&HYGcw&ZYdT7R~uQsDUC^th? z-!$7?QE1j&l5Zv}I%hV0>9m>b!f~_b*=c55P8~4wJ(_67N{un&?Ta)EiI?HA=%7~6JmCaiZk0p@H1lvc$uB|b2WSH>0s9CVrAB7Yif4Q3~Ux{sAp!Xx6Q0+ ztGXFpRoSe5Z3PNk`~&6vo`#+tpM;hSjY7*l3_|ldKSFo4c0-*TJD~j!TA;CanxMaL z)snee;Epjy8vAmkqv#r&ww7MAA#D29)vzZ?}a*f?S|$! zMMDQHWP>N}Xk<7oXiQ1wFWGdgAs)(=V6LnnJTPO-YB3nMNcX zGTjlm-;~8oFm)mBGM)F2FfDQun);*KQ2P;elc9od?;9oNt4J$Bt zi9BzT@0evmGd^MRZ)>{A>D2=!o2UNIZVkkkw6;f@sMSkMU}ZcLd_L18_ypO+V^4_5 zHaX7Z9nH_=FviQo80Knn)5O69xXsEWan;1+zaJozxlh|oblWsdAP+W~0B>wC`J1x> zd71hLa(L%7#5Q~q(tsa@c)}zv_?UaYorirAs+%b z#e%#@qCkY=P{=qT0K)M?LF&vA5EU&qi0?lKh;Ymb68qK^65RlX&`b3oHfOg%CX>}6 zc?xBSGiBAd)@RY!%4){=sP+%z&VQrEs$+x3HeDZ$J?pxS-EMRk8)mf_Pw#0mt`^l9 z3qtN2FS*?@PBp$|Jfn8qm^^dI_;O#aaZmFZEz#+xr3Hr|w)VmznVWBig7XMEag zhp{hIX56<~U@V4VsOGZkcbB%PH&lu_6K53+M=CDzJ zLWwo4t{PgHEgDkPW(;@zm^4i495vio zGiXT4`)CL~&~5mY-(h$f-C}5M*<@IyUT0`ARbzOftJ3gOO{t-NUXdYo|0P2{FV|3x zI%61acGA#K^{}DV_y4ou?Ma5ocVZ0zIZ=j%@lr!Q2H$X>C(E!ML^0g58e-@*gfpZ+ z^)nO{dl@p1x*GZ_91OLCtPHztO%2nxfDKK4Z8xmw)HJlL-ej0{c7x$){0i8H{s$Zm zp9UubC&8zdM!+XNeFn$ZeE^4EdJEp3+zx)peF5I-+Xz-Nehfaeb`Sh}umT*~SOUIS zcn#d0S^)klI1koFWq|=EC&21T>EItj2f+1>iQxT(F<`6INbobh1RRRwfnOLg!S<^p zaQZ+nxTPKoUMfI>LHj+ywrm*K+S4Aa2ebswEI`2ZJqF-}8eOpA*{$H3ST(RGaXq-g z;U7qI%K}I+`3rQdZ36VBWEk}G$N*?r{2nxq>H-ZKzXCm6X$GbCJpsWVJp}dVR)b>W z%R%#`n;^MkA*fX&AEf{NEQr~X2|8AM3{-sR5U7f`A5@M=09^p?0>#WLK%Q?!py|qR zP+kTd&Kx4|(`lf9IJR{c=U6{wKdu{Uuc2QD(TDSR`WM}p`jZ-DefyDMeL)>oKRpMje<8wCzrYWsp9Qej zkDs#84|)#K-*(AB|3#dxel&io{zizJe&&LbzDmbm;I8ZQz_z`=fV#v9V3@@)aR0x4 z;Dxunz~a(QU{T6TU^cZG7-RDU=(p}6P^tGWu)3@aNIi4|I8MI`jIz5398x+9#JxWS zyi|S^IC3Zz2xja9V(sFAe5IYh$X+>6Rwe{eQaL~;8V$H+9R~bwH4qrn?GMy0^#(3^X&|2y~uZ1vs`W0*ne~0Bbvc0J{9Y z0nX_S0r1~H0;U?e0Y|et09&Okfa4xbfZ5G;fUvv|az!p{!z|rm!z<=#L zAmD8lz~{yZfcc(uz-mx3pv^D|aP)T!0QM{r(0yJ4kSKV7F)t>7vxN+38Vm*itFZv# zVI<%Z-4oDi1p|CrwgW7*TL2cXKme0527pd~T|kNMRzS=*Re;SyB|z_qzk2bUc|B$O zUwTJZ$Mu%peAVM$>({G|>(yIBcj|dn8t zG7&*9*(Ff#=z4#>w6_Som?AelVw|I%slT<}m=;v;$``O+;9Whvk<@K^asOlO%>!cW z-v9C0_hy=Es7RBNM0+YFT9itqUE243-(*|HN^LWB^qg-}_3 z=bk2dp6B!Vet&;_&+C2e*SW59o$Ku9J~O?aVMChtSsF7h;KNVG)l=UXa)slJ2=_5Y z^NJUYhtrQ4KQ9k5=-X~F#DlLgM0ENXzi_>bM|V0I2luoyVqy<46pZ#UZVA^jB8Imy zejF%guvvwSaf=*=vqT!BZ8Vkft0SJVIwO)1VHeCOWBM}ozjtFCIqAe`%d=tBJ6kZ) z<<~Jbf6-^ioY7`HDpF(QyDw*~SiXeO`+X6^tWTVArc8vP;!R-`DdQN=rhkhmT$&W~ zsr)Qf==)CWpz5et@6RV4P;7+nb?Yn?O#Y0 zL%+g{ZEQ!16>+9T&zet&z7hK%ihc4*RIK@#=)8m>Q6a;-qTk5|N~A37xQOe)gt*5D@A;} zRYX)Xmx+9`loe?blM-EJs7(w4&A4Dex`Ow3Z-RS4OIMPK=SdVM0;(aHpIwjikLCnunig>+0Up*80ArsV;p&6Cb-z`+9JIb~)x6twQSp&2g%iMmg0*>*5`uxtkoM zeIqo|vaiu4nH_5NU*WP~rxP|cm@ z@x_T2d(4K$PO+eI^w-f65Nl}uXSHeOS!%Q;=F4f{$V+Iw*B8;aCE_$K2NBxHJPIxQ zK9(j^^P76uW0I;X^O@Q?@|LQy_a$|E&=cw}#RpX9cLUU>)@#)9=nGU8&C^u>uU*uV z<434RQVvpYtZt+}`BhJS)w`WKnpQ!5w62JH1(!>0y_iPL%VSa9EEA~m)F|r98^P4t z5?`v7y*u@@*d}W6T^p+0RtswD=5=W^-`<`U}aXN#zLyTz$D z{6we}c?#8F6iW?l{4G=%JSo(u_*tlH?5)t*mX|_j!=DJ9P<|lP{9!<-4-D^K0R33Lw$ZTb!(C3MIp~|D%h13!&gwARg30Zy55xQ|aO~@>nCDgep zL1^(*q)=K{u+W1PUm-<3ccJKMC!w|zHbSpbErjN;UMIBXhrW>8No}E6mYNW6^>U%? zA96yOCl?8&vc!dgSBnU3{6Q8{I*AoRv3^tf^(HBm)1N5zC*D$ssV^zVbe~Y%r|wgx zI|nEw$=4{-t1eI)zV}k(j(1VEB_5#=wGUFFzV4&k=%}a2$8V>^YgSOYKNnJd9?qex zj7g&esIe$TAHh$`wnkDeMFdkGD)~}gymh0zYIdTGgxFB-F0-JVd1Xx5yHB5z9-vKe zUZO@>@?4QJwo8t(-+K|on<-AA57Q}~JIE9lH!S6|cQBdW}rE)<<^B?Bq6Aad(LA96vM8`)3MiLCi*Bl%~8Il0Hzn4BV` zPgWk*B0sEACG%Vq$xLxMa_1c>@`kecEMjw70pFbTz1*G`8db2{W>nG;ill(qi{* zq@|MOq$T$XNK)n5B$_RcG$oWu8onGy>duZJRjdml1t5J$YNuRD6Df|QcI}O%&@W~r zsWv0h#qiana78T=c~ph8d-pQZN-tT`>4j1x)BE#CeHFr_wRR*@8x=!Zbmb>8Bl{ci zh4DCXEnL;^fi{~ayXo*9T7;RDtZ&2yl^2l*E;K zU^4+D+dxoxTuX4Q-b#pfC?yorwh$UFXA(LxA;M{cWJ2FG__@)eVT3c$0ff#KUWEOl zn+cV>>gzA-tH~etZID4}PF;2YxxP3J>X(;IB{Q;Ux}b;5|Y(_?>b|_@T$qc(LkG{CazT ze1ecCzW#zUzK>^zAJwzOW4@Z;7am%RR}EQ(Un{49w|Kk)Z@X0*iY^|%;0pqeJ~)LN4g7-ZlX;J;e>jRus(6aC*!U19LA-+-IddJ?#JY$J(K>@u z_;>>Mw5bCJeqjW+UaATA66Vq`ARM|NFHwn1QyQ6US z?jg9rd44$Oes|oR+)X%ZV_V$W9~L;xqw8?HBG=%^%XDzj&(v@O+n3|i9GBqosnWQo z7sPRzJP};FE(Le}GZx1<@Ef~1U=mv`{TX|A@GX{F`Vwor;R!Y#^8mZMdjNYa;Traf z$_4EF*S%QnU0qmv*CW_av4dFdwSCyqta|LuwcD}#zn5bVw-sVLLUOQ2Wz(?jL#f!7 zig@fU>qu+`J{X(X>w}F>cEh@;J7L$3ZNx6#V~$0-8)F|a^syb+wXk{Fs#tdeMeK@6 zS?sqqDQs`Zd~BvH9cwm3!s071*t1r@Ff816jC#*F=0)Ndrb6`v#_089%-i}wOqt6q zjJD`i%;1&tn1qZT3|+qy(=>4yv*ut6<|g>XBroZmn0NQ8F^R=xm|tcEm^5TI2GhmG zq{XCQeksOb5=X)@@3#kHydAtTweJi?)QHp+WEg$_o zGZQVg20|-;O+uRL|jk*+?h^my0M)^DpK`k%yLw&LEK%GE2qqtqRsC6+LPOK4WEui>s&5h*$@z?AYQ00= zc=r;?Zg_%Jbbo-nD|Q>ny?PC)m~jDlOYbx?<#QL3*?a_f-sd1PSh5jGxmAxmn7bWm zV_1Rw_`MKWbSMX@6qJU%BF#bu-it?~iz1ObOoPGCY55@gJKT^#;ZDfkayH1yA#>#N za${ug27ROhS{pgqrHV|6QAAP{<&Zm`N+Ff2=Oa(q(2-UIGV);$1{s|A3-ML?J0kt% zID%F?hS=`-0wFInj5u^|5TVPug*dBm6=6Ac9&u+^55nE06Y-qhjtITfg80PUi%8Ph ziTL%Q8j-QD3_0gxaJbqWzE_Vr9@u#8GJ#gw8z$L}%e*gr4a_#L1rwgnkDNaVm_6SSyD{9Ks?H zCf2f!K(b~&tpzyqa|#Mj_kV1a<`f+YeT0))X}gCpXAHNFnEt_0=LimD(3?Fh?S z=5R6}uFTLCPKv_@M&Td{icErTfF_y3l@c%>uyYK?7;Yc|g93y_V#1M&fEpJ83LtQU zKnLNJz>|aX2Zh+U2#{vs%)v7i_ZS$aAn>&y0~3#Y0}9{~a5@9o2GRtKBFHCT_JTA~ z7~??b03vBCcwn3euo5MUAoaucn+V(aB8s#K_{BI2L^LT2&fQGV0%cIL7?K%W)`hT| zFA_*iaIUMs6@_#Y&UF)rR0O^f_{6vqjDVVexd5JIK}$LbB48M1T5{q~OZau275PEoRgb|euMfs2`T>;u&jFz_VfM?eyjOl$`v1Z1#d0-5|}1*f;b4-k<0z(3U< zfed28DJD?SZh{iXU?$vfOIU7)?LwGvCFvkZwMHOAnQ&(?z%32#4Kj=`>%%hK9b`BY z?v6W%!bQL>GKvYWXEuoRLD+jN(-^J|m?98$Wtjhs>2U9nN&o+hMc}b10;hy1(jKWM zinK$jiXv^$pOLokkf?$>#Na`-2QC>GfGHXw1~<}oR{o8cR}Z({Dh_C{{3elMW4=`$ zNX&;z{YE3^IROD#y#23P@~m0gA2S+)ehBtfhCKV%Zs)As{XceV5%fsV3S=dA?62L$ zSvv&i4!^Mwg6;~tYi5W5m7sMWXU!CVZl-le1YHJbk=Gfzf9>XjB)=Cnf9&uGx+Yw$ z?L42qc57$tlK$99Bj^gC*GNb4yuWsVASsT-fqF0~B7aFCCE(Q}0q?ZG4^WJbTtXEk zqp1t1jyO7)5n&uysB#E0c@0p4DVT>qQ+3IDWOGsAOQ0u!{$Y@0GSFj@K#x-ZMhk_& ziWXR7VQT^nc!3i{(K)sxp&5t3M27@+q&xyPp#Uubb~mFHQbw+&@ax4crI?G-ks?R~ zT$K?8u8fNPV~PT8r2!FcASelo!kYgO>2pL-n@DaN67*ONxDm}uLn2V55+k4%Ln6&Z zVc!fH&>9so0x?fe4zwQy4CeFo@R3ionBlTmxH?&}xo+(EZq|WJPzEOWIDyN+48MPY8YVY^8fL#4HB2*oj1mLMKS2ki zkO+I2;F{2IrE{yapVM;tKczsz07Mj`gwHdM|2cSqd<@Kj{C`vozuZv>)jF7A8zjO3 zrWsS!I*{ath2V+er!X@L@PuvVhPiSI*n}v=68MRnrV1gDAOKr;E*0U!QM4KpbdhY@Bz5uRq*Wgl}Z5XMneFTx3kF zt%jPXj@l}9M3fycL&OFLM)>L8+wg5&J`6CAvK!u%2NAgF19QSgh5hvi@}5T;??fp&;Z{=tDkaes$!X23Mm zfo+sSVz8fIn7@&ozjqh{l(6)VK>TA={yR>wL6I?W%zqg9@Y`X^pDM(k@pdq=cknbd zG`DoLGeNAkc4Qhe!NyS5E8t0+X;{@7Q3lER+HQ1bbd7 z)_-R21D&6DocCNgAWF$MG9oSpbXY$!AOKN|u^Lv+e||#*n{iX4V6|M*qybq1}2% zD-&x6L1Uwg;XNAx4pcDCDgFqsxBt0YXO1TR66Uw&UyFUEnmT`MjU)X7?5raFf&+s6 zV-RyTKY!iNX(e3XPh;%OT}(W!%t%T$2Zx&!~M0A3}kBtQ<+Oq!# zn*m`6zmdJ+R||M?fh5*=W?xuoB5*=@DS?& z>)#-N`x1)^ZffE{o(=Gu(vT{gj>$l0q6)$5LOC`$JkHw(a9qp`2hFCyE{sDc!y5#l z>=PS{PzGCC8CEL)=S%~6k+7lizor*nVzXIuCXs*K{||b2a%a{5^2A@Avw3q|{crlY zHUG=i|DhH^!$3d%{C(mB!Ga2i1Vg}2d;9o+6KiG^W;9`uzH>!yaI6LT3&v^2;=h_O z_--KZ2nHGfMl3wsAM7w?u$Yv+vn;t2RqG#h5~#6V*1e6YZL1c5~X&jm&bj`Az?YR*fNnO-`kR$!d9EIV82>%1 zhZ+56wr8~Hf3yV7pIaj=V-WD%{|y-a`!(#3Vs?~f6lib?&wc;Gr!ss#^8@H3^3N$f zqe6r4n*V8!N5F6YnSccL_*sF^Xt09*X-`0`nY93ehMaqV06iLv;y>+)2&-9pCTu@< zW?_5MzwAi}?^$~T*dBb{GAE!BR3!W2eLZ;8prJp!p}oT=}1~jppyvx%m?O_QUIQ zCcr!3Z$KmdEld8*1SvFF4f_DYYZQK0ih%Xi33xW}{r=~=1wKN`#UbSU{-@6bbM8j` z+sqspzWDs>F2uh+%`y463}2)ERpfv0!msE*t(^OzUGOmgp#wTb0*4B`Ur=BvM8PbD zK*Yfez8*?~8B7TaW^gESVFv3U17`3t%7GaSA$+$%$$&2+VV0kHU%(8{7R(Yb%OMa; zUQd9u-_`s?-uAA z1#-JUJ}!{Y3gn9d`3}rry*`2&tkV}TgZ2ClX0XmDUClEiEl3Q(Hq@L!GbpB0(mW zrZZp4!?nThJ_Y!A`xBDrdo@pSgl-{AAwkagD0eybCfSlK zkYA7fmKz-;XaK}65bJ;agmOTP0MYT+4`?-rvLKRvO+({9r=h{0Q_v|88-7kgTR@Ec`5kfr z(eURtNC8CJ&#%zLkFU_sj|u4Pk1x=E5KDf1hLV1Kf;>Sq{V@)$`0)`E{qX^sntl&G z1@YqaJE(Q~EmS!@2C=8#Kz`G&A&co(klOSpBtHET`aSgmdO7tRx;8Ze9hrItZJ&Ay z@ur?YK~uxf#;M1U*3=_NYHA3=Og(_cChtSHCI_L;$$QYw$-7Y2(IyVSD|~~uRy21UxFIGUxf0%_dzk=&qJHPpM?y*pMjQs?}ez}d!UJL z-O$jtlhE03UC{n-$DxvM$DpKd9gxSjcF5#g8?@rvAxQMwL1^l03-t8se(2)YCaCr6 zKB)3*1H}Hi8}j>F4{i8b2dRJE0ZDw_4k5l)L!%Q_(6xyQ=*UDFw0)ukN}DKxf+q?f zn~8i#dmHYATv+u)4PT_}locIr~Ic^_ba*RKWa1=ibbLbz2IN#sj=M2BU z!@2PO7U$sm8=Q*wS2(Qq7dgJ~&v7i?pXR8&@8*cV@8bM^ca$^wuAOuJT`Q;KT{EZV zT_Y#`-5yTJyLyi8yB!>zchwx`y9y5eT`A}N+d|Hrw|ShCZ?ibN-==f&-a?$1x2c@X zZxcBNZ(})2-$rt%Z$mi~V}YDUW4@eoW1gJmF;`CM*d|W$m_5gPY$L~PYy(GSY&~b* zm@(()o3)%5Z}d1<-)M8%->7r8y;0`y-Y9Z{-^g=p-pFvY-$-#5y^-MH-iUGDy%y%& zeof(=c#Y@mevRhjz5dOPem%u@e*Kkg@OqrR^z}P7_4O{Blj*bOhE*#$4d*l{ld*{&~r*v2p2*@`cn z+4Pt8?8z6_>?beG*%x0Jvs+)RVOPFb#pb-wWc$BRVOzae#@2ix$6okCnvH%T!G7~x zjD71ljota2$gY2mVdp&m&5C+H$=dY%3v2E3_bmD6uUXXRBdm#$$E=}|LDspE0ao+K zHCEZkMOMnl8J5q;NtXG@F_zj$8%unonS~hH%X;-}C+o(uZLDL@%2~C~idb3Ca#`We z(piqr*sRsh5?ON3qFLl;VXV(j16U8Ada=$tbz$v)>cA>_YRyW1YR2+ox|*f> zREstLsVeLDlVz;YC$g;TPo!8!pUh|NctU4oJ|VNhpI})IPkyDYe)2t4?#ZWA@{_UD z&%-ZL9}W+vo*BNMx_|gqYU%LR)a2pwsoujqspi9-sj9<=Q^ki{QW3)qsjnW_rQUeF zHTBrz($u=g`Kj5DGg2cSb5fliC#J4>9GxovI3!i*v2W_cBlpxtkDOA^KiZhu^2jW; z{E<;A>ycin-y_Xb%STG78js{t7d(O?mq8e9EPV-6?GkkET>VY)#=kY)lD$Sf671a9hf% zhovbp5A#!q4>MB6AFxvfAH=8hK8Q$Zd=QvY{J=9M>49^K*8`grGw`F!st=4(#2@IU zARcI>yt=w^eE7{=w*JOqJACl?!N0TQ9hm)TU z4klk3>`!hRyqH`)*qh87>`V?GY)iHsY)W1=Sf4C2Se;B7EKUA&FE9DQy|m;r_fnGg z--}5uy%&<4a?dB(_a6AickbCGYuvL)UU1JS8GTPTdF-xw^6k5d$tUkFPTq4@B6-VQ zdUE_-VzT>PWU|TK$t0z_<4KIWuabV`FofqRL> zf$NE%Zkz_#I z=^smI?0=R}(tkf8x&KCjPk&#+hW_pZjsEt8h5h>zu>Cs|-rcB5xO<~8q31?M!oC}+ z3B@;}6OwNPCHUO%NU*r!kf3p6L&Cxvh6&gkItlNuD<|B&E|<`AeL+Iwb$UX{b$mj~ z^`G%R*T2MXxc(+y^ZJu`sq1&+ao4ZLf4Fuwe(+jneDAf^_@-+O@uk*qbm>N`mWrJYrS$IZtIoqINp`RaUoY4@xVWd6L*g!9_Ka)4>=;*b*&;6UvO!$L<&|;HmzT#GUS`HAUS`CJUM9!= zxP*v%dFgBHjZ0&($1gpJt-o|PHviI<*tko*vF?{TVofhK$Esf187pzAA{KQiFZS(4 zDE7|9_}EhyLt+~*dd8Mqbcjv4Xddf#aZRk%MU7akiwd#Ki&C+~iz2a~FW_T`F8qi& ze_=eP^}@@Ttrs4~q+RHb3B7PW#_>W|%$f_WF$x!U$IvfqjhX5zh`?V@zD1d5nACnwa%{8ZoMUOJgMa7RI3a=rQlkV`J`}pNj51|2}&E`H|@I z^Y^0J=dVTwp6`veJ>Lew0ksGVolN9CQ-i;6p=66JA5 zHp=YGyeRcEq^N~wensNWe2V;d`eo#U(+?ugoxT=%@bu}(t*1L8(@!@=hM%s9+;qA) z((rUfKGdBXexaKc-qsx%UeoOpp4IIb9^Gvg?%J&zZrZIBuG-BEU(hWYj_byS ze>^!E_VDD}u=6J$haEb3Gi>|Gb77e$kA+2@YzlKdSrcY*vM5aTBrj~i$+$4=$-uCW zCpL#YJYgAj{>0j_LnqY2wx5s-%Q`VHEb0U?%=N@{sOgFKp=u|dgf2WW5Q;l-K6Je6 zc<4~q{?H3uHKB*Qib8jE@j`RDVnbuQ0z%!poI}mJEJ8K9^g|bQse}@{WJ14miiQq% z;zBQXeh=yBd=s*>b0{Rg^Lj`^=jjmd&h`+?&V~@}&Z>~bow*@Gov9(;kB5gmKkgZF zSE6!3xKp28$ja2>x~KT=1J?M}zMi zYYgr^wk^2%*p}d`W9;CxW0Aq($Gn4`kJ$&WJGL%Z<(O8mh88@DKlehu`^^9e(5w9lq`#dbr1b)8Rw@#)o(Ms~j%zUvN0hAAdO3|8twK|8Sdw z|J61V|Kn{d{r9xV`xm#(^Jlf;{e#-R`8l+`@-u9^@2Avu$xouK%MaVO-*5cTcE87m z^8GF!O7%N>D9mryAveFGLsovNhxGjd4=MRM99raOaER)+;?OT&i9;WJv4@6z$6Igs zK5p&xz1(`p_gL#r-`%anzQwIvUsh|hZ*Z%(uVbsNuVJg9uX3xJ?}AntUwkXw_sc<~ z?~{X{e6AgQ=F@rbme1aUXM9Qz9`=C_?gIZhZK;p*!89L}gV8?f2fck39klf!A2js& zen8FV`2iW9n+NDVrw$-}nh%V7R~>lbopGSwJNiJcx5t4)-Wv|od21gi@|HUQdD9O> zdjD$i@E&Wi_8x3m<9)tG$@_4Nly_~5kavE|53i(_w_g4&554SKu6V6&>GE39vfoRh zrP>SElI!)kImzoubCB1y=1pEFn%8?ZHfwoRG|PLXH8Z>-n=xK)&0jptn@2pgng=}P zn$LLBo7+5p?ceD+w!heOa6jbPw?D$OeZPn2&iz)Nh5J`~rtV+v8MI&0({Vq^(|G@+ zhwA=U9#Z@7d64(_d3`bp4Z2S>UT`02JnG)x*x-JuvE046G2OkoG1@)5(aSxqaihCW z;~ICHMkROs#s%)n8%gdGjgxNp##e4%_T6=Rw(q=K|Gpz`r}ph~Yu;DlR=tnwmc1{+ zEqmEJ4tDzx{P%XGtAm)8vsUG6npayj2{ z%%#1d!DUxNxl3_FnhU2P$|bD9!^O41%Ei1v&qcdonah%f`7UA&SQk{o=glAYJl#CJ zr+@RcJ*PIG*weCk|DJ7|x9-W=oV_PubNn8^&Axl=Hrwqn*le&zd9%u%g`1`JkTz5H ze0QGO{nGjM?%U4ycAs|c+uiEiv3rN}?%ny$rMr`zxw`|MBX>JGd+auHw%o1ithalS zv*K=wv-s}GP59lTo4)S4v+2dIvzrEX9olqeSM8>@U0XKo+?BkkXjkAS_AbXwVY`er zx$aWkWU)(X)2dzMO$xgvo#yX)>4e*L+i9ZywA1tYR;Pjb8mH6sc}|Dw6Potcj3cE&ii z@APuqwbRP6bf>N(Z>NG|)J}$@*G`n<#+@G=*6bW|P}+IfL2BnQ2g=Sp4nOKj9LDN6 z4iD-=9WK{7J9O5WI5gF1IBczBI^@&|IV9Fi*$38*+B?B+_KK3KE*7gIndiG~(73>e!GVFKNqU=j*KiKhVhwP$jFWGt5cG%g}?y@te zEwWRsW!W)ngY9Uwj&{Fy7}#JD%Cr?YM4RwBv*=XGf!L z#Ex=Xj~zT)>m3ocYj(KUD(_ftyJ&}oEp-Re_IC}%_Cw92&2Y^Nn;SK^YOY>H|!Y`8U1Hc>V1HeNO6Ha0a{HU>3|ZPaRLHZnES8|gKp8&Ng4H-6gQyYbof zmW>13t2dtAp1HAod-TRV+dVdxZ@1W(xm{~x{Px8g{kPLLI&Gf@|0Kq!wf6P_>!sU! zti`vtSQEEzwVvFTVf|)Xl=XvcZq`?}nOUFMrfJ=>O~!i1HX-YRZIf1a9f3y`Zk`G?6z<#(QTWpFxyP5CaTq}URFz4-K!>AU8tV0JYN0OvZ?y2 z<+keMmig6tELqjXmf_VbOONUx%Z=3zmIl>pE!C=*TQ07iZz)=hw!~C_*f6p6!G@Px z`!?L$dU(U7t+gAvw&reV-WtE5W~=vxf~}StI9qi#L~WJZ;JuZ$!EWoch4I!=i6oLdWX&fkY38GqQ)YveFU>Aj-ZVQ| zdD84aWusYLWtmw?CC4niGT1Dx($OrS(!k8Qa=DpB^Jr7%wiBZkJM*A2Bwj~gnM?lP1rEie==O*BN8 z`WSvKu{3;LqGdQ#B4gNJLN+{G^3~vI$rFR7lFJ4=N;(XROX>{LOL7eoOJWT|N<0kQ zOUw*xOVkb4l}H(Am*5SSmyEAnRPu1GNXhxN*pfqQCyTeOeOsKd_DONX+JR!{wHJzw z*LD>vtvy&ge{Fp+a&1NN*qYqpJ8M|QJ!_(ho7VUhm#x`U%wDshIB3nRLhPsxt+zL!Dvn7zgsz$e|P1R{GOF}@*7uP$uC{mo1eP!XujXd z=6tJ__4!&WEAypSZpkOCOw0eInVA1jGd%yCrceF>P3QbdP3wF}(>Om!b5*{rrb@o9 z=8}9_P04(Urf~j*1}^`x#*e%U8sm9~G)D8PH6G=qX$<6rYFx^5(CEq2*XYQT*J#e8 zY1HR^SFg%@s$P(HSv@_kT|GIkMm;hwQ{6u=LftiQle%r5f%^J91$F&Ay1HiGl$v7R zh#E8Rs@lA~4mC<%tr|KnOKmbYQtd;ov)YSXL$#q?MYUVGB5D_Nr&W7$pR0D{UQ=z! zJ*v7Zw^ns)ZnkPsZj@?f?q*e1uAyp7uA*viuBfV4?zDk3>BZ^h5-;1yr8?N+?a)?G1@ExY1D zHhIOZ?9az3WkTCwbU7Gqgo)=z~~SuYfhW?fS_nAM@MH*1GN zZB~{-WmbejVV09ZR@NE?PL{kvLKamaBJ1nYz^vh=o>>=`Zpvz1x-qM2>G~{asXLx<)<@?WtzYRRe0{w2pUk1sitxpPTlX3moO%%~;Rna)c}GYyvHXDTd7&!jD3 zWqy;3&m5ME$h;sIkl8BdnOP<0oC(R9pqq;k{G zNu{SZOR>|-q!QCpq@vS(q{7n8r2^8`q`cC_rCibxQjY1b7H&+xvCusI*ur(`wF}pz zXD!r84_~N}?zm7Xef2_xbh(9#)5!~^(mySjpZ;KhNc!mol=P+r`1Ilh$n>NIKhiuG zd`nxuU_4EE!P~TX3r5p^Nl(~&%u z#*{pqhL=2$_CcaC?XJY`v~G#ov<8Xlv@H_lX|WPTX|57^X+{#6X^IluG`d7;+IR7U zv?t=xX&1!9(hiCTrB#airm@96()`3Xr&)?Sq-luTq)CczNJEL6roEnTnASgEKke9j zowU078fjVcRno%eE2cTlmrq+gUnWg<{=ziUeDSnT^F-6`&!eUF&LgEY&cme@%|oUo z%=^i6pEt=fnfHaaV%|rd=)AYQDaI)88DoTZi80JO#CX7~V%+6Hj9a__#&w<*;}TDk zah|t;ahiu_bo1Vbb@FbCb?}ahwejl24)C(Yns^an4LnD&dfsZW9XwgFY93jvg7-2Wq5amrFh-oXY}?6&*$X}i}GTGg?XEWg?I+SB;HbCJdY}j z=1tHLyhpU3+;g-kZZqv0x0LpUn@k($dePo<*VD$h%CuKp2JHp+2lW|uggVTHs%@dXsBKz0TF7Ug0jFUgV;v=ee(i&T{*Odb!7hy1BJNC%BnH$GKrb z9b9{%cCN0_A+C(j0WLwPnfrm#$h}M1%k8G@=I)`?bMq;++!#s?cQd7$Ye1>uE~Qj( zsgzRg1i6?yL@wl>CFgVZlXJNx$dkOH{~l0SEp=*zuM^yYRDJ-IbRcWye-l^a6b z%(W$M;_48cxY9%iE{Vj5sbNH zf+6=4-hg`_zlPh3*XQoT>v0S5y4-lY4%Zd0%{9WW|$;kR))J3%j7~>X|6wZ z5!Vtc#nr$r zx$n@z+}mgxw+l_>)`OUX7UD*tDO@KI_0eRm9Gb)>gE)>NatA@|K@qrnK`cPwxp5%6 zqHtUz5EW2ZE)B%5NDTK8i043TMxwc;ASQw6i9~TtK~w@!48&;!lKTwAOCYv_SP3E< zL_ZKWfT#|l1c<+(Dd;2g6uJ&|KvhsYWCh7UA30qdh_jY6#XiLLVbj>hST3yZsimpl z-=;`0O1YS9k$fS^An8b=Y+_-;mw3nc!*S#|&)C+Osc6IK^r+L3(-Eo>KH)`S;JeF^ zpTQEr>OrP~n*x0O!~CLsqkSU1gSF)F;*IkbFbYMHA~C`vRC}SbWDU|Tf-oM! zzC*jBE`k5=1B_qL4`>>iguX#vpij_yXbc*KMxbHn0dyDYhps^9p&sZs)CTQ`c0=2t zGAJKPgOZ^rC=hao>>)EqA5w>wLJJ@ogoeIyUUP;xH#ny`?VLTF3QiU$krT+-#97bL z=E!rzIB3o|dzgKV-NoL=E@yMuVQgo%F%bG zc*A&!_>XZH;%ejK;w<8rabIJv#O{oZk2Q~#iXD$RAG0+kG-gcr3~&qGbH_b&3b_7?KK;+5;Q-V5V( z#uM^f?K$bu;Suejw=NAX9xn4;`ZwonHrV{# zxz#z)d6Dy-O9=GdF5&9JStRZDu`b)nv8VifDD*GRShiW#5MQ4RRZ9S@0}WEFPKX znd_LpG%GVRFnhOt+j`UWpH1sbH<*4i*==HNGPSN@oz1#w;|60J<0+#Cqm4$BhPw)i?E$^rZFrbi;H-bvsviuEMQq z*0I(3rd^|Lq&=#&MN3WV?#k4a(kstt25C|>4{11Pd{?hgH&7o@%TiNRyQUhYDyrI{ z;;b^QyhC}d@-w9jC3&TbD}q;$R~%Swz5Ih>iK4pVz_PeyjAb1PP6}U_RxQLx?Q(S>A16<!~#eKNC8L&NP-dp5&+@>;-FZ77=UQ-Mvj6a0V1GqfG~hifDkAcAP683 z3IOnj`~Z9bd?0TCF91)-1Hc_}18@a!fi?p;Lz@7cAV&ZP0DH&|z!tIr*a%qzSV5Km z8z2h+b8r(dgVsZ)0RJCLcfr)=)-_-lcXxMp2=49{0wE;C-CZB6J9TeQ-QC^Y=&7H& zyBBDw_uJ)rXU#SH4|HJdljuDH+V9{6}ugy7#0d91PjK3zyx9e zm_Hal%oprK!8}8s zqEFDrU>>0l(Ff>#^d6YI=pFPndJDY?=0EfXdL6xnUPZ5fxr|-{Thm3f7rg-HJbDg2 zi=IJGqo=@}L{Ff{(PLnzI)WYsa|k_%9zgelJ#{a-2h47C7rGPO0XD8}=vH(Kx*5zS zbR)U}U5~Cq*P?6C)#xfPE5Sy#99@PkMVFw9(M9M#=t6V>nEB{DbS^pvoelQ2ndl63 zIyw!VicUc%qdj0Ip%c*w=y-G-Iu>kmqtQ|5NOS}`932M!d7>zS!YG8AP$Oypo1Pxk zp;}afs!l!LNS7Rp2!C>^DtRJ0qVpk%ZQC4oJW zh<2duC;@Fl@n|dBf;OW~Xd~Ky)}wW3E!ZNf(JHh8El11HQm~^JqeW;TT7c%Gd1x-! zFtgDtG!w<48E871hNhw^Xfm3JCZO?X92yJu&uBCXjYK2Ra5M}JMMKbFG!P9y{ZT*E z7xh8C!G7wAdZ6y88|s2OqfV$J>VVp#cBn0CgIc3js0C_{nxTJ?-^efIC-MXNj(kN1 zkuS(+WB}<$`jAh^2jo5S4ta~bL0%)TkeA4FE_$YNv>@(;2QnUBmv<|1>D zSzzCuflNoHAybgaNDndznShK(#vx;oF~}%nBr*aSj$jCiAP9_@5F=th^oSPGAZkQ~ zC=fX!L!^ip5g|fEfbbA5!a>*w6Ja29gobn@6oia)A)N>j=|Bib8-hn#k!GX`X+-Lg zI;0k+!A~dAH*B+L_838a5r;7oDoOF0kKDH5gWuBu|zBobL0>F8~z3V zfWO1v;6eBcJOKB@eeg&41Nf>1P8+YupdZkd&8cv2kZvB!p^WG>;T)rw%{&i1zW)8@E_QF#^b&dwJ%ye?kD!OpedsQ92f78_gl<6Bp{vkk z=n`}h>V?ijXQ4CDDd;4096Aaefet|jq5a^Nw+Gq= z3#lO`q=00Q1QJ6+h!61~4#a|(5FMgI-4GcfL7h+sM1b0$R;U?jf*PPYs0ONrDxq?y z3@U+&ph74g%7t>EEC>gsLupV7lmsP0@lY%j4Mjl_P#6>n1w(=0X6gs|Kwgk1ep8?6qv^frt?7;FmFb1)ndyn?vFV}d zzUi*%j_H=^Kht&7HPaQ-CDTPyuj#z$tm!nk^PVsrGaWGNw!Fs(POHLW(SG%YtRGc7SKGA%UCH_bE6G0if~FikT}HBB~6GEFdzGmSNkHjOk5 z2kQi4f=woq!K5>3Oe&MoBsWP-Vw2FsH}Omy6U)Rf(M;VYimA)gY3eW$On6g^soB(M zsyEe|s!f&P(~vS#iK)m`V9GP)n6gZnrVLY>DaDjzN-)KlVocGdNK?2e)D&zAH2Ir+ zO+F?slZVO8$ipHI6opG!6%g z6=H;pMx)-SHL8tDqueMpij6`e-^ewxjZ7omNHtQ7UB*shhml~!8(WM`#s*`ZvBp?s ztT2`tON>Rv0%M*r$Czcr8Pkoa#$;onG2R$!j5bCZ!;PWFU}J#M&*)?HGI|)@j4nne zql3}TXk)Z8S{TiYzYRYP-wj_4Ukn3=KEp@DJHs2pE5i%JGs6?ZBf|s3J;NQtEyI6? z>xQd_%Z7`F3x;!sGlo-!6NY1kBZfnU1BQKuJ%*iz?S`#}&4!JJ^@g>E)rOUZ<%T7O zMTUij`G&cM*@l^h>4vF>$%cuB@rJR6(T0(R;Reir7)%C(L1)kyR0f4XW{?leQx`Aq-7)S=9q217CXf-q&8Vz-Z8bg(#!cb-?F%%l|4Y`JFL#83akY-3WBpTuk zv4&_vq#?`@VhAz>82k)A22X>#!PVewa5UH%Yz$Tg3xk>AxBiFzn|@ILS>Lb!sDH12 ztADM3seh(_qJN}+pueZTt-q3BN zrr)C9q~D-lr(dmKsb8*Ns$ZmEsGqN&tDmKxp`WIoqMxLnpdY6nqaUds4%TKwZ_*p| zI=x1()XVi!y;v{M^Yk1&OHbER^%Q-Vo~Uovx9MB-P5K6XoxWOMsV~=;=!^6P`aFHM zK2x8ePt_;u6ZP@>7=4sJLLaIR)(7hS^*(wpy@%da@2q#!+v#oeR(f;&AKfqAcimUr z7u|sFlkS7=o$j^nrS7@ziSCi^f$pyEw(h3xy6&p(vhJepg6^E|wC<$txbBGVknVtP zuWq+)hi;p0i*BQCy>6{;m2QP@nQpP}AKe1oT-|Kl4Ba%{6x}4<1l>5@Xx&KNa2=|H zbw-_Dr`4%+3Y}CZ)(Ley9Y@E~(REZESx3?lbp#z=*Q{&Q)$3|>Rl0IrsjgU8pv%)` z>oRp2x>Q}VEv*J@X3S7?`N7i$-4=WFL^XKANvr)qn&6Sd>CW3;2R!@>0i)|#|>tyZhj zDzs9qSS!%-v}`R?OVf61yR<}YyB4o)(Kc%9wKdu*ZMn8oTcj<}=4!LGIBmK%MVq9J z*T!n2v=Q1+ZICuV>#OzFdT8CW&RR#Uoz_NcsWsRB*8I?X(|pkkXg+B^Xx?gGYhGxc zY94DIXzpolYi??;Yp!T6X?iv1HD@%ZG{-eZG>0_%HG4I?G&?j~HJdaWG;1}hH7hhr zHH$S1HS;xdG_y3*HB&S_nhBb5n$emOnqeA518EEztwya;XrvmkMxfzo*cyh0rlDxM zG(-(SgV!``8Z>p9YE7l4OjE2W)Z}ThHJO@pO{ykI6R(NYL}|h`p_(9#zs6VNrE%A| zYMe9<8e5H(#zON){Zsv2J*XZ~_o+Xq->P4$U#Op|AFCgz@2YRB|5IO6Us3<7zMwv* zKCM2XKB_*fKA_&K-mTuD-m2cL-k@HqUaelCUaDTKUZ|d@o~@p#o~E9xo}?bH9-|(m z9JBwQ-KuU<*Q;yQRqAqesk%s=ug+0t zsWa56>Lhi7I#wN}4p)b&gVg?NAGMd-UG1WFRNJd<)Rt;9^>5V=)mPPLRln+^>YeJf z>ZR(L>aps9>aOax>Oa*r)n(Pcstc;Ks#B`ts-vnys{N`xs-3Fssx7LGs&%S0s+Fo` zs>P~>s`;ups+p>3s>!NJs`08Zs*$Q;DpUoj3@WWkr2>yzsYEKiilbtx=&Ej2mx`z& zs9IIcss>f9s!CO^Dp3`w@>MyiOjWunMU|wASH-9zRbi@NRiMgG<*o8ixvHF0_9|PI zmC9W8TlquzRry)jul%Tdr+lq^p?s=*qmQm$97QLa=jQ!Z96RL)b*R?bvTQ%+V+RE|@QR*q0&N?2)B>XjO$QYll4 zl>#MK$x_ml-O4T{QQ5AE|Cl6JULs=kW=Mkd8fQxj+Zyd>*Y1_N_m;QSY9B{m1oJ*oGOmmzqsu5VlB`44CTo#3%4%g*vT|98tWcIK%aUctQe{c9 zI9aqTLKZ3ulKIKJWgaqDnUl;;W-YUj{gM8VewBWf_DMfT-$-9dpGhA}A4u;=Z%VIA zuShRS&r8opPfCwU4@vh+_egh2w@Noj*Gtz(S4fvi7fBaL=SXKtr%5MECrHOiM@ffE z5vfV4mujR6sZ=VG@}+DkLrRr)Nr_T|v{l+Dt&>(uE2JgTLTR2fTbdzFl_p8!q|wp{ zX{a<%>L>M5pC>fA^l)RI?mb{QWkvx>#liZTrkX)7gE4d&! zD>*4SCOIrQAlW0?DcL63Bv~(6BUvF?Dp@3%FPS5mDVZwikxY<`k&KiKlfV+AL?=;6 zN{h~dh9ipwGO`>(8)uQF1 zC8C9*d7@dO>7vP^iK4NhQKDfYL}V1{L@JS7Bo+xo91&AQ6_G_m5kb@Duq&^2s|Cg7Sh2(tR!K(5HD;J)(fkJ6~Yo>fiPE?DNGk83ll)dH$oUH z3>5kay@YN;XQ92&Mra}YE%+fA6buMH3f>A{37!ca3+@YU3;q*a6SdkB^V}v1xA5Zpc2RgA^~5(7SILV z0+OIzfEP3g>IKz;azTlpK#(KI6r>4~1o47sLAW495FqdocnVwvjsiP@mB38!i~o)P zncv5M&wtH-!GFSkz`x7C$-l&-Jcy^~fj4(~VxEA< z;W2pKye?h`56^4j)$^)(<-B5EJ}-xdkNbi9hWmp1g!_PdmwS_YjeCiEfqRyFl6#bUkh_<=le>+(iMx)wio1-vn7e>G zhdYBig*%ZujysAwj0-mGw~gD(t>;#AE4U@x0&Wf$$4%uX zapSmA+%Rqs*N^MPb>}*B?YY)mbM7zBH_jJMALl*iHRn0!G3P$#4(C74RnEVh^PJP1 z+H+yUiMk`N%m3pA@)A@F7`I|CiXh^D)ut=BKCatZ1!~aWcCF1 z81@J@$~Lj}Y&BcX7PI+mHk;0-ushiVb_=_KUBj+mm#_=iIcyv|m7U0rWk<3@*@0|d zwkO+_?Z~!eTeAPKey|2v{j86yx2%_}r>uvpyR4h6YphGG3#>D&6Rabw1FSu)9jq;^ z4Xib+6|5z!g{--(nXIX-Nvv_KQLJGsm}Ow8S#p+`#b>cubQXox$s({?SPiTiRt2ks zRlv$&;aI7xL{=;-k`>AdWcji@S*|QcmMzPY^@sU`Imqm1zGuE>K4(5=-e=xs-e6u~ zUSytQo?;$j9%Ale?qY6ZZep%uu3|1_{==NdoW-2R>|u^)j%E&LB1|Jw%TzL@OaYU_ zWH7s#B#?AzWi~QvnU%~^W+5|&iDRZR6PdBhNMu@0(ZRqonizGADn=Qjkde#CWTY{Y7;%g!MkphY;mh!3 zxH23WwhRl#Z~Axo7kVH4J^dB^8T}Fc9{m>mI{gy;0{smA1pNs80DU)oJAE^KJ$*HO zIeig*K7BTQI(;&I0(~@nI31xI=~}viE};wP96Ezep?A^=^cH#py_#N5FQ(_yv+3#d zWO_V3njTIMqWjUk=x%f;x-H$3{)hI1Hc0EEy{EmVJ*PdU-J{*2U8h~9U7($zouD0| z9iZ)|ZKrLft*5P`Eu$@>&8N+xO{4YD#?waAhS6Y}fu^C!X<{0m#-`C|WEzpyMr)$g z(W+==v_e`gEt8f;OQglpB59$t0GbcYgXTiBr&-g?X}_pnsRPuH)Hl=@)F;#j)Z5e> z)GO4B)U(u+)T7h`)IHQ4)GgHY)Ya7G)J4?!)Y;VO)E?@1>S*dPDoiy{HB>oOOyyHq zR2r2`?V#eRP1HJSCAE}VNX?<*sHxNhY78}k8bbA_dQ;u0PEccOUBB*S)KIYxlUx3*i+E$J3?v%Bftlx|{oTX%DJU3XP?S$AP~Za1zwwL7spraPiLq}#vSyW73n zsoSpGvilF^2jvT;kMf@Kit>!|kaCxDlX8{vFXcSt6y+G@AZ0IQCuIv|17!_mIb|_r zK4ms#I;Dp)o-&Fui~>{i6g5Rg5m9&)CWT5NQQ9f3lmH zloCksp?FYSDE1Uy|-b&s; zUPE3^UQC`(o=u)k?jesSk0K8vLu5T!MV668WGsSY6bvuCDg3)~<%G zny&J$;;y`|tgf`Kq^{Vm$gYsCfG+PY_b#U{yDrPF-=y!P&!kVJx1^V(C!`0Y+oT($ z%cNe?8PW;TVbXrmF48vAM$%f+3esZI0@7^KbW#s#JZThZ7zrZjNh*?zBqVW23=)OZ zNopfClj=xSq*78LDTkCnN+HFQqDf(-Ad)Z1ljK6OCs~usNIyFVJNrA|cfRU;*7>mW zZs&iUS356up6xu@d8G3|=kCt!otrw>cCPGP(z&p6PUnoy$(`dnM|TeEggf<}s!my_ zu#?-#=}>07?yT#q>MZRn=*;QN=uGL1?~LjU>kRDl?eyq$?zHc;>ik3eLHt7O zBfcZPBt9iRAl@O~AYLZ+63-A%5Dydg5qA-{5;qXn5SJ4d6Xz3W5vLI+5yuio5>cX& zs3j_h5+a|-BGQOm#CBpUv4L1kEGHHb^N5+mRAM4Ah8Ru^Ci)RQiLOKkqBYT+__JfM zqrc;Q$Lo$~9S=M1cKp|IrQ>49*^Uz(M>_U*?CRLov9V)K$BK@{9rHV8cTDS;1pXX- zWCz+|?9g^7I>a6P4ps-XqpPF6qot#vqq?K4qo^ad1J{w-k zVbx*Q@uU4qdtdvz_LuEX+8?yvZol4sx&1=>>GosohuZhH?`YrBzP^1``?B_b+UK^< zXrIzPp?!4wuy(jz->zzxwF}!h?eum^JFy+#-qc>(UeR9Mp5LC;p4Oh&9@`$#9^CHN z?$z$v?$B=2Zr=WrFi7YpyeGUOJS99N+#%c`Tqg7q&Jd0h4iWYdb`rJ_))Q6}mJ$9T z%q7euOd(7lj3x{tzyv)(MUWDN1P*~tAQOlLJfV?LL#QAW6Y>a|gj7NzA%+l62qO3q zJP9rYdx90gjPRrFOWUWmw{0)mp0wR>yVZ8R?NZzMwo`3K+YYwvY1`hmscmiB%C;qK z3)*J4O>66E8`n0n4Q(^FY1(ww1OOv}L!Yw+qHM5_|zZ8=sC(!pGtx@WFV0 zycgaT?|`?)o8f=74z~8SzH5Ei`lR)K>#f#nt(RKQx1MS}+IpaMck8y+jjd~2SF|o} zo!>gEb!zLx)-kOkT9H;mtGZRzDs1Jn(p$-`#8!N3V{1)od23N?ZY!=er8T}ax;3md zu+^v4z16AJw$-BbSIgIyftC*~uUnqAJZ!nsa--#P%Y~NHEyr38wd`%#(XzQ^UCYXr zB`phDX17dhnbb12Wkd_wVro6HYO!sxX!+IrwYk6feeKK=7Y_9nzuJ^YF^vC zqIq%i{N`EBQ=2C?k7*v>3^yB^)y=YIVKb+h-b`-pXl`w8Xs!k?v==t#G-os?H^((c zHitC(H+wa^Haj$1H=8y8X!_Fhsp)Ogi>Aj-_nK}tU2VG9bhhb4)8VFlO*@;mG_7x1 z)wHx}Vbh$Z=}kRNt4blcd1G|CN(ACi1(9%%fP}NY{P|%Rokk*jc5YrIe z5Y*t?;L+gRVAo*T@T>l7eSiJ?`d9T&>mStLuD@P?ss4QZ$@(Mp`|EerZ>`@@zq)=| z{Xg|{>ZjND)Q_tlS&!Bm>oxWAdQm;6o?cI`@2GFBZ>X=XFRL%8&#q6ePpXftkEjo> z_pA4)cdoaqx2*qN_pNTA?nB+Hx~Fvy>TcIvue(%tzV1}rk-GhLyXv;qZKzvax2$eq z-JH7VbvPFU~b%r{1ovcn+$El;&k?Y#)TI%ZSs_IJX3hJ`!(&`fHV(P-{g6e$h z-0Pg`Z0juQe${@h?W=uP`?B^)?fu$YwO4B|)}F0BQG2*{U+s?C&9&=lSJp16T~Ir# zc53a!+A+1mYvEd5t+G~9%dchCcGq^+w$(P(*49?k7S-m~;%ZZB<7*>pLu&nNy=q-+ z?Q5-S|I~c1`CRj%=5@`pnuj%aYOdE@sySbCs^)0T{+eAiTWdDdtgcyFv#@4P&Ged{ znz1z_YLFU3jk-o!BdB55&}v9Egqr4>x|+(G;+njg%$n4i_?oDi(3*f6?;6({hZ^e| zvzqVKpQ}Gszo~v+{jmB@^^NMw)#s~ERUfTBP`#^qYxRce)zwR@7go=yo?hKkJ+^v8 zHBxP;R#i)@1=Z|oYBi~vP~BWzTU}9IT%A{qt4^toua2q?srIk-s&=WiuePfGQ}wNC zpz1@_>#CRi>ysv}kVs&-awsajXHvT8}yf~r|nQ>!Lcjj0+|1y$*) z6jkCXUKO*7Qbnx7S2a{sSCv&2R%KVES0z=&RE1XsRryxAS2aC=~?MqX;*1k`K#h zthidyTXCl1c*VhrJr&z4Hdd^uSYGi@#oUS+6+IQ>Dn?cy6^06Rg|tFY!LFcIkSYij zO%=5j6%|DlxfQsI{8kJvQuS8%J!G- zEZb7HzHDXLlCt?_v&yEHO(+{(hLxGhv}N)#Q5mO`UI zD_vMRr*vBBq|z~^!%N{(U8%BET*@nDlu}BGrLCn6rB$V+rTL{%JrO~CKr2(a0 zrLLv+rB4O8zOCQ!>3| zQpwno;U#d1u0&ZPF5#6hODHA8lGc)jlB$x@lKhgalGKuflBklDP&EFM!ltQacR z7AuNH#oS_gF}b+CxTUzRxU#soIIkF2oKhTD99bM(>{skj>|AVHYyqOsgGHZ;-WEMC zdQ^0$=tj|{qVq*3i;fiSE81DKxoBO{ilW6u^NMB`O)eT=G_nXSG8Czcq(y=vRuQ$R zv#718v8bk~tf;UkyC}UVu_&e}tSGR^yU4A`p~$M}PvN)1fx`ENuL_?O-Y>jac(t&% z@J!*c!h?mo3%3<+C|q5*v~WS;?82#q6AMQd4l6VjY76CsqC!p~y|Am0P}p2pTUb$8 zRG3?sQJ7p9TNqIoROnOaUg%h8Q)pKBqu_JF$AZ@d&k7zC+$y+MaIxTQ!SRAa1$zp% z7i=t8U9hZRVZoe&X$6xC#uN-IfC{t)iULsqw}4(iE@&@kE~qQ0C@3z-Ex;8d7sM7s z6a*Fc7PuEU71$J*75vEmoc}TZb^g=*2l==1ujOCNKbwC%|6u-}{B8Lg^H=9D%U_s3 zJAYdK#QZV&!}3k}+I)GwD4&y0%kRo3%yQz3=7Yn}Ti=X=gT&ikBKIZtx#<=o7T{}cN^|5DavoB_!$v&2SAbWTA*6j7! ztFo75&(EHfJtcd5_NZ($+mNl!mS*#_S=rs$#O&7WhU}{BlI;BK%sHp)tlq3MS;w*tWbMw{nzcS_Ro0TM`B^iwreuxJ z8kvP=8M0Jak}Q4}GmDZ%%xcZ5&#KHS$;!*ZWu;`rWkqBKW%*{gXE|osWSM1s&m747 zkohX}N#^~`o0(TKFJzw1Jes*bb64h;%ypS7G8bpg%bbzflQ}MPL?)c6%T#8HGr5_J zOmb#>W^-m;W<_REW=>{CW>RKMW>{umrgx@mCWu*P{>FX9_2b^*Uf>?#?&5CXF5%AM zPT~&Z_TskVHsRLbmf;rS=HRB`CgMiphT%*&4Nis=;@CJUt`paWYs6LKN^u3aELHnsmO+TJ~Fnv$@w)73@tJ0UIFG!!2J|%s8`lxg?-H@(I zm!$L4ndy}Dj`WuF`t-{5;`H3~jP&I6*!1x9z;y3)w{(YetMuP#U(@>2-le@rdz5x3 z?MB+Av~y`E(hjBVN!y;bF>Q6)(zFF>v(u)gO-LJ+hNcyOT(olr^Tj)rv;|@q`9Rzq*2cECq#H?>lFlcc zOgfyjH)(s)#-!CrOOqBP%}$z{G$CnJ5}IU4QYA@}cuCA8N>WEsOHy4@MN&~xPEvYO zVp2>}SW-ZeSCUJTU6Mu8&%`f@9~0jsK1+O%cq{R0VsGN<#G{G(6L%(VNnDq>B5_gT z+{EdLlM=@y4ofs8Y7*s%!bEl=HL)`hpV*LCl~|IPmxxPDPK-;8NDNB!NpwqeNVH1) zo$xiGFX3&%^MpqUcM`5A{F`t#;dsKqgxv{S6V@lJOjw*SFJWfFd#D9zLkAENkGX8P=-S`{v zm*UUGpNKyczbAfM{D$~d@k`?8$IpzP96vsOWIPhDk5|Tvxv`9HO1A$mBkgrWyPh&#m7a)1;_cuxyL!i zS;zf}{TACF`#$z%?Bm$Gu{UBb#h!~j5ql_hPwckX4Y8|Ym&DGGof$hhc3kX;SU6S} ztB4iFa$;$*q}aCD#@OoE(%Agi%-EFJxY&r;pje++w^)Z*tJvQ$Ut{`W-p0I$c@%Re z=6cM(F=u0r#~h5=9kVrNeay<3#WC|@X2kTwjExx{1I1`#8ny+3+q^ycWb z(aWR%iJlWZEqY?~=x8k37_E+$M)RYY(UjE=)~yg=+J2YXwPV; zXq#xW=(Y8+9YzW7+Q{pLkfR~{Lw1I24p|$rJY-?W?2xG;6GBFXpdp43Rfr^n z7eWu|3L%6vh17(Ug%pHjg`|eWheU(~h4_THg*b#*h5Qcw8r&EBCiq$KgWy}iSA%<3! z(3GI@K_i3UAYG6mNEE~gq6LwH@IehhRY4^|c|o|KcD= z>5us9{T2Qqe~v%RpXA@>-{4>6U*ezVkMmFVkMR%l5AgT$ck#FLH~0VH_u21*-z&c- zes}$D_+9cl=Xb*Ikl!A^t$yqMR{AaWo98#fZ<5~_zhQnRKaHQvkMGCyqxg0BwfNQg zmHQR?W&5T1CHO`91^fB>x%)Z#S^NF={p#E2`_}il??c~PzE^#FeNX!y_1*8g!*`SK z8sBBU3w>w#PVpV@JJJ{N)%z-ZMZO$gnlH(>&9}j~%D2Qf&ll&Luc`&!{@Wl2cMTdkA3d?-0->NbI#|u&q1HvK3jd(`>gO;z214f@OtQV+v}RwMXxhnN4@rY?eyC0wbpBy*Fvw^ zUQ@j$c#ZTzy!2j5FR>TLi{?f0YV&IJs`4uF%Jaf`C40qqg?R;dd3m{b*?O6K{qX$k z`N8w0=VQ;io;N%%d7kw=?s?F2x93*Rb)G9c7kSS0oaQ;vb2RvRlhISfaGCawi z1kWbV8qYG%0?$m(6wf%%2+u%IZ%p+}ZSszq(`ua zkB6IwgNK#JFZV(BPwsErpSj<6zv+I({et^R_rvac-M71MbYJDZ#C^W|O!pr5vF^j& zA$P62%w6Ela_@HUaBp$1bFXkOa?f^8b5C%Oau0U*b$54nbhmc@?e^8J&+V<-Gq(qB zx7@C}U2r?)cEoL;+YYylZmZpvx-D><={DJIoZARD$W7}ecN4m?-MZa~Zmn+hZWV4t zZaHr0ZV7HtZXs@dZXRxqZq{ypT)(;YxxRIM?)uR6mg`m5Uf0vEM_l*0?r`1Yy2f>> z>jKwVu2WpcxsGs!U3IQ~WR4RQ5z^>B4^wRZjE z^3A2+<*mzemxnI5U9P(Hx}0`7>ax#ehs!3HH7-kC7P!oEnc_0uWrPdtqH|HW2wm7N zRF_VdR+oC0N|$1n9G7&LM3-on5Enle4;LpFYnMOH-<)f%7cqDbC}ZM>xaII%m1F(3$N_btXEuI@dc_Iu|+TIHx-&I!8H& zIQuz!I6FF9JO6R|=G5o(*6F#^L#JC#SDkvDPCFfO+UK;xX_M1xr=?B{oMt&qb{gk2 z!U=ZLI?0`cPHd-cC!$lUQ@vA#Q;}1SQ@T@vQ?7Hj-c1?CQcBOXtcA0i5cCmKh zc7b+Yb}n{yb{2L&Y(Lw6uzh9w*!HgN4cmWh&)OchJ!rejc8l#g+ZDF|*v_$?W;?-l zlr3s&uvOZMZMn8|Tas;?ZKG|KZHaB3EzUN{HpVv0Ho(@?*4ft9*39<1&4A5&n-?~Z zZ0^`xx4CF@#^#vKew&>(n{C$GEVEf?GuvjW&3K!UHi(VRMqwke;n+}ZI&JVa^){6@ z#WuM%={AWr(Kewrel{L9PBzvyf2_Y*_glZUes2BH`nL5|>t5^A)<>-OS?{pkWWCyY zsr3Tunbwo7$61fChOD*La%-VA%evc|Xx(C6XI)`kWSwoDW}RRiX&r3sYwd3BU~Ogn z+v=;;C#yGB&#dlS-L$%5b;0VS)nTi>R@JVl~fdhEDQ zX@OYiEtD1_3yuZNf@FcWXt1cVD7MJ8$goJVh_(o|@VD@=aI&zmFthk(-f#ZS{JHr< z^V{av%zMpGn;$jbXTHOHlldC+rREFFXPHknA7?(o95&aQ%gu%6Ec0%2qIs)%oq2_M zk$H}Jnt6hGlzFhZuerOqqq&v&Z?msvpUmEvJu`b?cGK*N*#)zcW`{v%Y`fV8vsGqG z%;tfHT94USvtec?P}-52@j>H_V%Bcf3>uteAPb*mmI@jz5ujz}ZRQFJahBlw|9|@@ z-$CDG0C*4lZJ|5@?f}<;zg?6wz%gJy@VAk&8CVM}1OE0>W&=}z@xb493IgZ=1@O0{ z!Um{7C-AqaQV&!D#lYXbN;;4TL<4_YD}I0n;0XNfuKWSLm2W^F@VCM89C!fS0{-?` zdVy2G5#Vo|WjnADSPd)%=7UDdOkgtbx7jirfB-G0ki;hzkg!oz~8P* zHjoCy1AiMY!GI6o1~>p#p!xFa*AHwE_}hMY4Lk+z12=)oz0|C%s+z_|_B0IUQS z1M`3x|7*pJ0p~El2&e%mzy}z={=Xs94$dZ^1}FmxfJ`9ee{Gp?a0UY2fGc1JSp52e z{RF+4zs;Esz$@Sh@V7s61Gog71&#v;f!)BC|8;3rfO8Qr2bcy-{MnC<0#LvJr~ol& z)^LHp?HUr$1~dYHJ2oXi9)JUqfEduV2?GKEPrw+{lHFOGq4skah3rKf!V+mU_5B#j2!CZyuozfRDfQNXsDU<8l!@<6TtuY z+s}E0RRYC8?odnTC6)-zXdq;$tMdZ$0H+gRJ=EBFj(z+79P0<(4)u1PVGqH13%L6I zZ+qt{b{aSW>>KLvJi#`Cb2YH^``;$dV{9fc85lRz=Xr!d;M9Unj~oyHET9`Sdx$^_ zPzO|ezmF9H*+3fT_#^<4KrrC@{VwJXH~?1P?_j^b-N6QdPv8D_er{vWfcwDBq2|vm z>^wM6g7(khq5jWJY#V3*Z2(pQe_KHFfEhp!Fy`BJY#3kyG((M`YZxD#OwbCV0PR3C zXa>~+Wkc2KyT_#AfRhIr zMU0_N(MgQ(^#s-gR1Ys4(`Wxf$q_kq4v>UZ290`>>psxPzPxbHUYGd zMgizh6KNNw9NdM8K^uuX)JNKZkp_2QZ9wBtD``7cGPn)P18_s#q^(#CIKx0cDPX9f zv>9_A+>F_RmXg^}PiYf2@MRMyOrrhZw4jRzg3kwYz}6`20Z3QPf-OroJK({haVWf=w@rN;0>ji#ko z<(DN`F_1gdYg&vYep!S?1EE9hrhhPxFAFgzz-Fl9v;h0|c|O(;y!-sO=`;^}_<1gN z8@M*qcbbEp{yZBy3hWxFuu9N~DjMoUO~BGWPrwpEFDh!N88r^``#cWw0PQHpp?=gD z?9ad$?AyR-tPglQFbaDCA|vmTIRzx!p_SD>$7ioFG%^-Hh^Lp>`ocBNm0T>wrE zwXFo$-hKhL9W<^s4t1`0*phxOHXoQd)V$(gWBb|IaL~SjhWb}bOxDl91ORKOg+<3Y z`e|4TXkyh3b+Nj!!hQ;t4Wtb{tHq_B-!*2HBu`9rZp{7;~cDSzv+uPTSZ6E4uHDRmz8nGpyvo(LHwN;Px^wnWw zf#E~ltr|?zSA)s=sxd*|-v(C|M(L}>I{GTG7ND*VyfM;Oh7|(YeSh0rC0INV*;kAO z4|TeVFt@%!%mMVetcIFh`Pks6JnR$jW~kqlgWdm>jok#UeEQq+%EV3qhd<%4y+d8E z3~b}4bZph9G;GOG<0}=L`6&hK0j;mG!0=B=81yL-)BGPtciG-l)`npicXxM(GRV*u zcc{C!N!qx(+b%G;GeF#$)Z5hE-QC^YvBBY``@{7oo@1^1{NsL6K>O>UFXG(+U#~y8 zyqk8w_W4@8+v|JvPv=1sY`5>Rce{NLzT4%y``xq;w!?S*pH{rv?z;%I!nXSUn%e67 zWonD>yQyh6Y?E*QpE{>D`Zj@v*m~cxsr9}EQ|o*)r=~rzHNLTbGES}b4FqkmmA;Cp zmA-GLR`@;xov~%Ux2Kl*3a6I(vO#lfu`h0Fu`gn3kuL=F#}@e7O)c=Xn40f<4YbJS z`kGG7@jdpZLsQc(*(~3!Q!{ zvoU}=ISSw=M*sxqo(%)8lS6?0kPe}6g#dT2esp2==t+hiB80kqLN zfyI*@z}(4p;P=F|lhz8npJ)Nb{xkrZX-z=$L?ci;(EyZ#ep)?{HBkqoOw_ zT;SqF4)8zFVaoyzPh)Olvd5!34e)L3HSlq4+K77v42``6y2oAst)Lh845%D?3KWk$0dhb)?h%kM_7I2~ zdjN!jj@&&!J$4t6{^=EH%H09(j@<@;v0DHS^yL76I3@8We~+;M6VRYz06WL%z~(U;uom>_D8Pa-GB9h51pFACw&@7KoE@ zpi_qd8b;AT)hG%m0nIuDkTD7e5=VW2Xwa{N0Rf{>KsyQnWT0i|2|OM30Pc^v1Ghle z&J|#ex&Y)+X8;QtcaDJPr~}|UY7f|g-kmLQb<_qpH);)>0_{6X;NYkQuzS=T*aA9u zH-QzSH-JT>*MT{piFXzFJaPqiH*y&m1%14WK*z`hplRehPy{MM|J@hKyz;gaC~GtaCl@Juov|Awg4MOHUq0hHUUdOi*Ez)dw4zYb$A`{ zVR+i*TMY~juL8PAQKcMeaAHxEyU*MJ7#n0UePhNBR({gE#5tpCEg0!gX!Xx zLuum0L#g7qphK7}{xX;(em|HX9s^CnIC0ltthjkFMqCT}gpuOH!3c5opi!I(T7_Za zh`~QwK7+wxJ?It&iY0>q;unJk@uR_M!_ZGG9@L4sgIX~i^bA#E)Syxf8&rth2d8aA zsn~i@BEB*BR(xr2+By7Jd~)!W*ktgfct2Fn z{xmRcA>I`a58M&=4%`;EgD#@4xM~0pmkfx+d7zOf5GM`r#W4e1aTw?&vc=i~mRLT( z5WfcPM4I^i09AZzfGie(jv`S^86b#p12{1pG!-#omjSfcZU8B^0DVQc_`-mX*mM9U zJ_cHg5b>S?Pw}<^5Ag=jU33#K9&i!Q9dH)^?w>Xo9mOB|?ZxB$cH#lhW3(2x^jnGR z`Ypv3pv`C|&gs7?PVK)Tjt8B_tKyLUD`G?cC9xVb8!w1o_MaC&?msKO3;KqC&b?U$HgA~$HY#c>u4f2>pvpC+<#bn7Bn6Yh>!N~7a!=~E8YcqkGsWd z`*(_$_wNud1ntMI;-7t6#Gm^%i{JH4JCGa1eSPc29er!XO`r+6T3pt*Qe4otLYxWu zkW0m}eM`i~zQy7o(286jR`$&ozv-JReh#{kv&DD%W{O39GsGOwko+kk^!*Sa`@V~y zpeOl7InMBkL?2iReLZvFJ8vR~Cp^z4;|UjI+ocYNN=XdwKqd#51N*#qHDd$ zq6@uAqW^)uWxVKcZ=7gvZ;WU=XkA8$R`o`Rmh>7$^Fa49RP?PUSoEINN7l&G#7DXQp(i;6&# z6DCUQhKdrpy+l!<&*?7m?{*Vux?M!lZs$K%r=#dew}a?jx1GorbUUp@%x)_Yx!Xd7 z?VdI~Z;Cv-Z-|_`uZe6y&-1eAYWF44`R)rMQ_%K2D>~GDMzp*8f1<6R^ZB=EW%o(Z z;_l<3xuE%ZRP?pWMD(HSuxK3gKM#nyy7q}$y7r3dKnrx2sHkg)D5q-NU(hTq5i&cAh2+jcAr|yY^MqcVIYO7tY@uD}v}Kwuyw;f}ywI5< z{2%C=CJGOA#tZj!#tFB9#%YvrRcEAdNvBab5A;q$h2J`Yg&#YDgcBXp_NhVG)1eo( zcIbrl9n%h~T3Fnn6y|m)gz2D(DiKC^ycLFZycPz4KI%)MyyLm>b;mQ|Gtf$XB)rw} zP$=lQFJysk>OVqU$88~^!&e9a4ONlQzC$3i?BENpgPtl!c)EinJkh}r9szAts&IP; zS-7!-BwP(Tt2p8O4ye?-Z3eadZ6FzUhA$-_=O?U_NS}zMZ?H7f#_VYplXt$mb z!rK2QbZ<8mI)aYt3E|E58n7#b6fO*`NozP#E7fUl`Fg zPZ$i^u(O1!wi!Z6+i$^3(24ynxZCzs0JMD(@IW*6qkz=*UVv$PC-4FN*l~e#+o-^{ zZA4%WTCxLz^KE?s)3#p0G0>Im6zpkh7i?>56KnvD*(Sk~wg$nxwtB(u)@g6HTJWK@ zQZU|HE*J#u*%Co(YmuP7wLnk_I<&ch+}3PCdTXX25j1Jj1YxZyf`HZ}ffn>>;{~r< zV+GGzqXiE@tJWwGwuTGXt)T*H>$F=NC_uLQ3!tqAfg5PpY6VuUYQc?GrQlMl;*V!5 z6P#?72uxbv2=;@v?JL3N))#`ctW8_D6j<`T|2?m78}9&7At`%XzH2?4z=76 z>}k0s*arH#mj$a@E((^koEOXkt=-dtZ_TEHkIkn96V21^?r}j+^Iw9tW)nd}^R&Tx zP*BpmUy#?lPmlq6yt@Q3%{v6)&D#Wl&C@pTCV`@PgWyf`I>B?$>0K?j)4Wn3YF;kj zfM)Mv0ik)J0M$HS00aHrIReM#Spw_k8G@Uj<@|F-j6n_BtxP0jpD&;f4X=Qh>x z)0=AeiA~cca0NfCsf-`cRKnLbP5ZzF{MSu+{AW!${0E>FoWU11rSaKKseCHv1}E~7 zP4RqaQ!L*NG=wAhR!v6!jixaECD0QN;-72^;F~lV`1?UySj*qsq~@<}Qu3EKO*_L< z{+y<_{9lc)`Cl5R&Ec2)vBu~8fySr&F3=x-$ggX>&#!2_%P#^g;#>T*Mu4BtDB?$f zE-{bq-^k%>8d-c9XcW` z*D&oKpXT>BnDV|gRy2(97B!6U=78Sv0PjnEAMbsA4{r>#mpgb} z^=-VC`W9Xt=rA|%it6ilIrTNXG|*%&=SA0-^1|wic>$o$oX?Zj=ki|HXY-zcR&zS< zc6};OSf9*egKl#i4__a{L)Ay|V4&d~&U35}>_+I)V@`%w3gH(qz2HwgOAcX+LJw|Mn+0Iv$P zp!vMKIxa7xj?GH~U1&NlypGBXtRwSupb?GZy{W_SUeuv@k3cWlhbOLs@wjym9v!r! z-FWCa7oK;W6VC&5r0saNbv8WnI!oSF(3HN(Gp)PMJ63mn4o#Sn&JHuNA zTGOX^^XpFXX4W0&eXpH%r;qR^YY*{;YY*^xL4$e^ud#L~ucmf8uMG64H}kS;H}X2bC-kObv<`> zZ7ug#O%?Y`&9r@8#vQ9E;SSUkal1eVJC|Emlg+KH$>bJ;CUy!py(Wp9Sd+kw27T;k zZa_^WS65@?DnKhcnESjYko&O4pL+*%vvpifjhaiZQF4i(p)KWl*Sz6+)cnhJ0zK{L zT(g=d+^aQ@xaUDz`yTgL%^mKcnp@mGptCLFZmi*RSJ!a4OF?s+$(>n4<9@HEa6eT~ z``ZNWNHvz*SB>U&fEKq8x277#Evtrb3qY6KjhkBS!i}$X;zoi-w=LIDZOv6zTXJQf z*L{QgwE7zNe)SdZEzs^h&t+Ag-*2cugQ_PD$lUPCn?9Kj9=-KH|hy-sc!WtNac}U+K$HRf;(h&@Jb29#?WW_bQnjU(hh8 za+sAQ4!M%R!GfMSnggjsa$GBYIQF1z4&mIW^x#~obmN=>opVQyNu@pKK&1_57igZF zbJkVfLe zA2iZ;agr;xbK)wtaw0%4eFH~dv5upvSj~}wcKR~TlZqvrdlic~zM!K%m&2-<#i3Np z;NU=0{W}|4@s;gX@gLg(^wr<7Z&XaOFISAQ&w|$aAp2-VKl?yMFMBuWu6MB4SG2NM zRy4DhfChUVdqzby`&)S>`(ydE$6mr7E-zyDmglqEL7P2`T~nUHE-O!E7l2NC0z0)l zjvZef&5i`k_HeeLJd~{|4`RzezumxoTCQV1DA%xWgO}flp!Y6hA1mjv50!J+dqMl1&fZu~VXrPHv6q4lJeEDH z9L4@ohG73!Hf_Q~*`sBi?EW%$b|>h=JF)A^?AaA%w(KI%inm~=m)&G1mR)B@gKqpK zc3|0gwyx|fTLBvKr`RvbPOu-9{l)$V^yCk*d1VLKjIzCK5@^fsV8hF{vAxPRvt2-E zejVGgYz_N**-G|B(41ewK3TSqZBjO$y&v@FXR)`G{bsEz`^j1XTJ&F7bIU%lewV&y zeJ!1K>Bm_UrK7B&(jit4Xw>(z8cVxb)ukP*QqZe!W@VK&uu@9vSn;4;U&#t7En^u< zi&+}bvCm`uTbjdqTAImv0GjqGEMaLPi(MMeqJh4B6bn^qWOR4An_g={|EtRp3mr7WNOJB40mcC-`D1FY_RQiOqrt}eOS?PV&!qU5}*`>ExKT81C zml6@{eF>j6R>EZsl(1OcC3IG636)h}LSj{w5LhK8SXN#Mij`43^QgVTXFFDIXmYilm zOHQ%eOHQyHOOCOuOH5cdOAfQHlpJ84E7{9BRkE9PtYio4P{~%-o|4V1?Ijyn8%x%* zR+p@1EiGBWT2Qi-HLGMX>qqed*5~4Rtart;S);`>SOdksm|ex+nJvX%nDxc~F)NEd zFpG<)n7PFh%#7kuW>WDGGp2ZeX)Nw#1{HTP{fax7s^V6rq_~Osvbcfyq_~!Ouegfo zTU@~u6qhnt#YId?aRC!ooXbQOXECA0=}focRHkEb64Sako_Vu4mU*Q(ig~Ws$UIdX z#ynOW%sf;az}!=8U~VtgF*g>gnX8MH%w@$g=7Qq4%vr_%GJh7mWPUDs#(Y=wm^oJT zkU3CvkJ(jphuK=>%d9UFGb@V(%#tE5Gp~rv%qU_olZ&X#*dh|sSVUk37h#$DA{0|q zgkVaGyqT|xAj~I49?bhiZp>Rn&P+j(1Cw23$D|fnGx0?hOjOZLCamZ>)4k{l)2Zkp z)28Sg)2!$W^J>8nR|;4Fn1K~V{R(i&0JHogSotDD|2Dd zX6Edo4a{GKYnfjPS1~^nu3(NAE@ciDE@Ji+&S$n2&Sf?f&SF*<{$`XG{$S)6er048 zerBW;eq_WIzGFldPB20W#~6mfVTPt~fFUdFWxOuzW;`qGU_2;nW!x!jVu%Xs8Jxme z2EDL~K`bn1pbJYFK7~aL&%%6$OJNSft}v5fQJBWKUYNqTSeVE-T^PqWSs2YQDU4(s zC=6%pDhy$4DGX$+FElV#7Wy$37it*u3YCl*g)+vsg13xM1+N*C1uq#R1WS;5x&x;0nXK;3C7U z;2h&h!D+_%0#k-*!AZukf@6%s1tyHW1&0_r3idNL73^WGDcHqWUa+09uwV;gcELu* zul#k4FZrt(AM#f+#`Bjk2J;s)dh!=A+VbZz8uMo{s`G!-%kqEH3-Z6wv+_UFQ}aL4 zIBr=QJ_p`Xf+r2my4PCu9*Lf?}g zNZ*!kpl{6gqp!}_(3j;a=?n5@^jZ0D=|A)SrGL(QL4Tk3ls=aCh(4HipWdB!m)@Fp zo8FKI(5v!<^wK;YJwK04&&p%aQ}U?vxI7X)G7nD=$-~n9^H6k69-J=EgVA5-dC{Nc zxziu!xzO+AInu>>c64r@HJy=XK_}(iq+|20(cyVl=w5jj>8^R_==OQ1=~j8C=r{6C z&@boxML(N&g#LHlLHb{L`{)PrcGLId?V$gGgy zbKlZ7<^D@slly|UJohPWVeTW^oZS1gUpfEKzUJJbeaI2hCUOL{p&Tx)H-|-Q&!N+r zawxQ#93rhe2S+Q+LDO<_5VW)$Z(3pwgchCSK?}=qr3L0V(R4ZXG-Zwr?QM=F?PZP` z?Qza^+P$1BG~b+yG(pZe8Y|~Cjhb_chR-=cL*@KMgXJ8ddE^|VIpyr5+2-t~ndj`F zUCY@@yO6Vyb~lBNn4Whi#jjoJ9TEx z7wY%yPt^ai-&3cuC#j>^W7PiaVQN?Q0JSB%ms+3QMXk(kr

5Q1h}IsF~Td)a2|c zYFu_XH6pu&8j@W|HDu>eHQCuzS#}2Xb#^NCS#}cjVRk(ApX?Z_I6IQc%MPb9vO}ok z>;Nh@TTew~YpIZI71b?UPIbtZP_46HQ*UO!q+ZE>Mm?APm};8+fO;(ZF7bER3^a zYbNzZ)-THCtnZX_SzjopvOZCcWxb;u%9^0;%^Ia_&l;j^%Ic@A$?Bmj&+4Qs%4(y` z$!enf&a9_=&8(q(%&eqLWR_8eGm9y`nFW-N%p6K{W+tUJGmTP_nM^6lOrYdu#!}KV zBPmIl;gs0S5Q;G~kP@6}py)Go6m_PGBF&Uj{>_w7o@KtKJji@Wxs&;fBFcP3;bz{a z&@=y`kTP#ku$f{CJX1h{WO693nM{g9CXHg1Nv7P)Bv7toVkze`krdNRAIh;zDCKab zCuLuz8)ZkP6J>LzJ!NgC4P`~9C1p{j8D(zfb;^v)%am^!7bu@H&Qc~b{znte75i%}gkc`aeCBrhh$nF{K zWT%W4vQ0(<**v3`d@ZAjd?BNpd^)3qd?KTOY?6^nK9G?`-j$I~-kOn2UZ0UbUX>9` zUYZd_o}Up;o|O?o{+S*~{+wp4E2dOLVE2%Z@6RAG!J*g^fl2n>DM#@hcB4wrZlTy=qNbzYMq^Pu3 zQdn9ODIl$mq)V$NDbp%QZ_`RhFVhN1Ptx*8_tLUSx6;x{!n70;J1vn!ON%8D)1pY| zG$Y9;ErjHi7D#eQGmz}lv?QxE73oHroOC(uE$Lj^zob)XFG$DIo{$cwJtXZ-yGPoQ zcAK<04Ir&e6OvY>aY>8QSfsgWbkdA8GU4BHS*bTjsi{{<@u`xrzSKVA&eSgAmeh9Qy3}Uk%G3tplGIw_ zywpnK%+xaCkCbBK=ahWnyObQ_SV{(QFeR1Po$|-XOo<~lrbH8KQjEm1lu%+}N)Rz8 z#Xw9;(Ge3lAgWWI5Tz*(iT|eDBR)&HO?;RF5bvZ2h~gA3 zk(csknmmO@B&U#xxD-4QnSvogQxHV=6mOza3WR8z;!ZSAaUotyaUfnyu_c~Ku_T^M zF(V#LxlTNoa+$b0oRAbEtKOCBUBlY0r0SDiwLCTJOU;; zn*dKvCqR-@2yV#<1c&5Uf^~8v!7MqPa5XuYa6UPJ@V{g~!ii)J!6aEhIFKwQ>`H!3 z*qZ#3up#*=VRiB&!qVjXgayfW2(y!Y3BQtrgfB@v!iOXlVIql67)~M+`jQBQjwB4B zISEOqOY$aECP4_rN$!NaBo{(vk^>b++CiWvZ6%PBHWDyN>j?0qRRl=VGJ;#uVuEAR ze1dh-9D-TW48qlcekH>c+25YR4~2 zYQZl|YQWD)s>T0Gti*p!EX99JEW%GF=HW*Yv+;e2>G;mX6nsl!0=_;m7GISZi7!bE z$LA*o4@;Eb0~254{Ssf`Rf$jW(!_`OSBdxVPZMwBA0&$L zcM=77aUuuLOJw31iBvo}k%Y%3;_%2s6dslc$Gay&@lJ`Jc-ur*yhWlD{(7Pv{!*e9 z{!F4d{_n)=_`edb;14BU!0$~wi{FuGir3u#FZ_zc!}!IC2k`R}_uywH?!Nf6?eCvb6#5}3HT2{hdAcoObgJP!9M9*vudhvP=$ zVYq>KPh5ArE3Pfx3D*#BhpUda!j;9F;|k-i<8tCJ|V;F99c;9}!X;UeNs;DY0i z;tcVJahmx3IC=bT+?)6vxEJwTaF63R;O@n*#rejs#0lb;;@I(vaJ2Y&IAZ)P947uZ z79Rf{3yJ@Xb&LOqb&Q|FTE~xJ&Eki#SL6G!7vj6Ir{g=YC*xbNN8=l?2jgq8d*Umx z+v7{I8{>ucXac{8YaWAn&anG>1agVSWardyvad)tBaR4?lPJj)K<6!;cm{@Hb6|0CN zV&BH$urK3K*e7v5*!yu%?Cm%YtSHU}%Z+ouGU9Bpjk|<(k2{BT ziu)hdHtuh%Mcgs$^|&M0OK}IWXXEx_PsQ!T9*f(GJsh_QyDx4Xc4yow?3TD?*!6LX zu`A=|W0%Cu#?FtMft?li1M@TX3+7AgN6d%VcbJLTam;Y+Fs3iIAJZAzgK3HFz|_aK zV5(vpFr~4zn1a|!Om=K3CM~uIlNg(aiH^;}gvX{~f?|^~`q+4kIyM?3i#1|i$A)5_ z#|B~^#p*G4V>KAxSS3afE5)#5Ut?&oFEGT|Cm2lZLkv9jE(Q{N3*#0m!Z^nAF*dPm zjCm{_b1jyPxfn~poQcI?{*Fap{)&ZR4#j$5_Qtwlw#PbQHpSXu*2Y?4R>YcP7RO%4 z%!|E@nHhT?^CRXA=5x#`%=?(*nDH1B%uvihOmECSOh?QvOmoaOOkK<-Ol8bEOi9dY zOn%IAOjgWdOlr)0OhU|TOmxf)OnA%>bWqF}v_9q|S{*Zmmc@*tU&joipU3p0AH{T| z@5Z#FePdeCf|v$0JEjIri>W{pV@lANm_jr>CKnBf$wa%wq@o>T645p>acJ|HDD<_M zaP-BPVDy<7fArrmI`m&LYV@HPIeKr*Tl9{YSLn?#&(P~)9-~*r+($2oxr3e`1E6Qc z2+%*HIp{CZO!S9nDtaQCh#ro{qWhwe=+0e`_Y@wx1-mg zMbWF#-00+VMkk0HqD)ZEQ3p|WQTtGqQM*t#qPC$fM{Po#i&}>= zjar2|9<>a0Bx(_Af7CqG?x7A<*F=3rE|2nzBr*+|ADM*Aj*LU5MMfbL zBg2s~k-d*pHC=13Fdy2yjbm63aqOCon7=SOZu&WhZK{28$p`6Xf{ z@?*qOq9@xKT< z;zR@)VG@By9Ed<8c1OSw+ajQdO%Wc5wGl3e6%h`I#Su1$c@Y+fnGrV-KaE!qUyK(J zAB<-Z6UI}BVdHT`pV0)-Wju&zHSR?;7 z&P7BTXClIkKjDGKuW&!(C%DS^4lXs0!CxDP;LnYH@JGfj_+4Wg+}GFy7aHr}9Ag!n zZY+b7j74y)F%OP3X2D^`G`NQ`3GQr+gWDOS;8w4KX25+|7TRfPa380 zqsG_pgT@!|J;o>S?ZyZ2&BlM=>x{nel|~_aiIEFmU}VB)8>#SL;Y9e?a18uoI08Nu z4ug+|d%_38UE$r~j_~$yTX<8rCA>ELCcGm2D!e%SB0N9*EIcdx6g)NjI6NWT1RfK9 z5N-_L3l9$82{(jqg=@k$!WH3b;cvrN!e53jg+B>j0DllZ2Yx4f23#Ee!-p6C#fKIC z(T5s7wQ*)YkU@m%YEjBzxA0F{>tZP*fXCm zVUK)1gx&L*47=?!5+?TP599fCg|U3v!e~B?VI-fLFq}_$7|N$O%*Q7$4C0d+=H`f`#@N&_nxo{@9kkF-kZV-yw`>0c&`l0@Lm#@;yphs z-g|afwD+%2qxaX)5bsZ+0p3%gI`7d?mG@w%%)2M_jdy$KOYf%8r`~m;54Zuj;K-Q?{Oy3X4n zbd|St=rV7!&_&+YLg#v444vtHCiExlROnaOvCvPj!=Y2K{h?#9U7r9b$yFg@nMG zLi}O1Av#z^hzeE`B7^0JyoP0kynv;JJb@*KJb=Z9+<`@e0I-k{0W2Vd1Ji}jVagCP zOd5iR{TqUYJqz)HJqm%q?uNL-ZiP6*gdz4YPKXtZ5n=`-hg^fmqg5n??JyUC7g*TaX7qLdZWsTnG@vgz$qX z5Oxp&LJPt`NI`H2HV6tq2Dw9ELCz4*AbW^QkQKxs$P8i~bPZx2bP;kb=q%(?kSXMB z&~eDAAQQ;(po5SjL3e1wk_*bAo<) z{SN%<^*!*T*MEUiUhe}(y~YCvy@msOz4`(>yt)EgyjlYrycz?my=nr>y($8Wyov+! zyz&FHys`pQ|D0eFy%GasykY|*ydnZay+Q*6yaEFKy!-;yUaCNumn`s&*XzI+UM~Wl zcs&k$;B`Onj@Ru#z)Kv+_u>Vzy;y;CFKQskix`OW!UQ6{5P{xa&_FLQk3d&1=Rij< z`#>8nt3V4cv%ni(R|7A5T?{<$btdqCUZ(<2dL0Y=%j-zsA+P;``@D7s?)2IoxYcV@ z;6|@?for^02Cnd08o1bNLEwC^If1jheh2*W{2uVl^S^*kp6>(Rd5#B+c@75*dG-bL zd3FVKdbS0$dNu|$c-98gcvb|IdzJ(gd*%n^du9h@d8P%Vc_sxUdd3FCdPW9Bc!maq zdIkmrcVhCoTZ%i3~t`dI!Kfy#hQvT?1S_9RnOZZ31jOEdtCvuLoTByc}@J^IX6=&;JFO zdY%k8;dwN`#Pd+VLC?Jbdpvgr?C{(Yu*GvjzSphRW zfBFCL`0D?~9&G%Yunh5sUtCH`|g=KIg|nC<_={kP$Z`!~Y}_x}u&?(YpF?&F35_hCb~ zd%vOGz01(#-e#zCZ!}c8*BVOQD-8wiC5CMG0ziC-4N%VY>0G^H-x!I83NtI z4SM%rgWBC-kh^OQZ`>7zm+lh76Zd}&58R&_?zlfPh~4iQ`0lq1EO(KC=FT$^-I)fg zJJo=2CmLYx7=wp9!r-TL)aZe98^w>EvDTa!N5tyZ7mR;f>RE7ixl z73ibfa`fSD8Tuf%6urSMUaxVB*2~?D`nPVu`j>A0`loI>{R20p{vS7~9&mfD=exbo zv)vx+X>RxRB)2M$+56;q+E+D7~4RxBjY|m;R!goBoWO zlm2fvTm3ONOZ{QDoBI83SM|nSrw_Jn$M6UjRTvweR(^ct5ah3YvU0?g5U0?Y5xIXsta=q{8=6c7^(G~Esapn72 zxU&7OyVCtGyORCRx#IjxT~U4~Tz&jZTp@l3T;2TkxH|c5ceV4|-=6(%o~()7^H-(urKsbX=E29m6G7M{$YN;a$RXD3>6ekBeUC<)YEK zx+rvxE)t!M%fC8vm*=|cE{}AVT<+=4y4=>8x`=hhUHG~qE-c*v7n*Lj3rV-l1*hBS zg3_&Z@zJet@zO1JansFranj9lvD5u@w$godzN!1@d{sB;d{H;zd{#H$Y^v*aKA~%K zHqkXXAJo-4@6}Z}@6?qzZ`I{HZ`5TuuhFGCuh1nrFVV#~FVGpC=jcM5XXyN$e`vMN zpS23-4_b-yr1q8bsP?Jzp!T72ul6734lUr^qUAd`XxYv+TAFi(mgrof#X1*g5zg6K zsB^m3-8ot7>>RJPbB@+pIvce&oI|u%oc*=uopsv(IjgiMon_ji&Tq5_onLDAI6u|y zaDJ%W?EH^*owKiYrL$1G)S0VY;LOy{cBX27IT5wroUqzYP6+Lk6HGhmO15PoT z-A)mj?M|VZO-_NDwN84?3MY+biIYMz-|4MpmeVWEPseAPFOH8iA06*$CLM2UMjXYO zen-Bh+mWqlbEIn;9m$#+N4%!o5v?h9glqB~p_)ubcTI|;vnJlrUK8zTtqFHD*919U z*XSKDYt)YCHFC$(nm3MrYhE}W(>!)OqPgdIKy%x1k4EIUL&J64qG330(2yP1Xz-59 zH7Li$8gIw>8c)aB8W+dkY6r*fYHP>OYBR?V>Z^{E>I;se>eG&c>c1U()qgp5st-A~ zs`olJs&_cns<${+s@FS~s#iG{s+T(EsuwtBs%JZH!CXy2nAQZg)_sn;fL-T8G!_3Wpc!VuvT{e24q$EQdSlR0lwv;2=;(J8;zD4h(g$ z14V6cAgDDC7`5C1p?>24Q@?QVR6lWWRo{1TRNr>6Rf`-f)m(?0YKFsAHO1kg8t-sc zjdCzmdpn#^dpaCdyEq(D+dJ%2TRZGhn>lP#Uv=1|zTmJO&6m z)q5Rgt9Lm3R&93pu3G2tS+&yPgKCMxq-ue~sA{&upz4=>uj;FPr|P49t7_7|Q8i*; ztLnF}RCU{zs@m)eRgLz!sv7%DRk?kts>nW3m1`fX%CwJErPzn5;_ZV}QT7H^n7vjN zXs=ZH*-KR_``0R|{R`D=`zNaB_77E$?C+}X+TT+7+KW^Id!CAI&r;FsX)2OENrkn? zsSx%k71Z8G-N^FOZMifbN1I&ruLUr$L%kuj@X}3?YBRr z+GT%SwbkB4wZZ~u=3ol1$Y zlPO_#ZNcT&3Q2 zrc!PDQz5hcs(5YtN%7qFo#K)0xZay^C?afbC_-$mDEw_MD6}?b6bc(t z#ao*bikCJ=6;EsqDel|sQ{1-Mtq|F4S8#1MD;PHG6=a*$3Y^Uf1=41T0%o&7;bAjJ z;cPQQVQ2GGZfWyXe#7RI{IbnE`8k_$xv9;F{J714{D@7De7{YHe3wm&e5*~Pe1lD` ze6>xbe3?zDe4$ODe2z_?{I_+M{F`-}{F8N(e9AgrK588;AFwvcyRAdyt=0kZ25Y^% z+FBzovsTCpttIjt>(}yh>lgAQ>nHM9>j&}(>$~z0>sxYvYmr=Q&66vv+48s6boonb zviylPUVh&iEx&Dzkc+Hga;~+foMG)MCtEwoan^Qnq_veCW^E?-u)Z#Lw!SR4vpz4k zus$unZhcCA$@;kbthI^!l=UI`G3$Nu!`8dx`>eOgcUo_jZ?Rr4UvIryzRG&Je5v&k z`2y<&^4ZpN$sksbWv*8DWe!$%WY$)I%*;wCyK2Ri zU9e)xPFvArC#^`bqgFWCK`XRuj}=_D-3lt(XyqweW92GaZsjOjWMwOxYh@*yVPz)! zZh1}ipXFuQJInL3G0W4kLCaIJZp-7cHcJy(qvau4jpaUBx#ccdk>z$-uH|M~hUI!$ zvgI0CoaG8xgyj-hh~+|=zvWz+)^esyVfjn?*7BS5rR9IpCzcl{Q&0r8O2bX}JYST4aHf=31bo85VG9vISHcXW=Q0uyB=z zSU5@jE$pOP3oEI@!d&{+;=1&u#TDseiwn|w7H6clEKH?BixX0g#a~jo#bGJQV!sq) zu}2EG*dc{jY?ZoMY?L}$td-hWtdg2rER$ZfSS-C@F<*MxVz%_8#SH0DiyxAM7GEX1 zEj~%MS-g{Mw3v{ru^5pow-}Txvgnn}wdj=mHgA)BGjEc7GOw3RnO93j%_}4W<|UFY z^8!h$d9I|vJX2C_o+c?XPm&ax$4j!!qa|tPMoFT1s3gWbP+~MUNP^9^61}-fqBfUF zWae)qugzaco|`|DJT!kS`N#ae1Tg1_W*>=g0*%nEU*#=3w*;+}H*-A;R*)mCm z*&<1i*?dW^*=$LM*$hdt*^jqzW?$b%n0r698W@-vL_kGE2|+|cknWsa)17wLvAetVU~!IJ$L{XdcP*YD-)pYVf3Wvjv)8)s z@4Yzlxqe>e6TL3;fnJ$;S1-xDrRQf}*Q1%2^}U(@>N_&e>zgyr=x1i0(pP03*OzA= z)|X@+&`-+TqtDCSsn5>bs^?^G(layH>60^8>*F(5=%X{2>ccV@>M5D?^uC$1^d6a7 zy-TK2Z=WgCTV;y$rkQ;G$V^QCi^J7_<@D-5aJuxbIPLnUoM!z4PJ{kGPObhLr&@oJ zQ=vc4nX3PrQ=&i4Dbye2Ow{k;lDtk-eqdL<`L zFX6=K`J4zn!U@&)awz%^j=#Q{L)O=EJoQx^lD?edtS{l%>kBwG`tck~eKyBb&*2#9 z(>MnDB+hRgjq_a>&H17W<$TZua^C8EIInaboM$>`&SRY&=f2L8b4O>wxv4YYT+{tz zU($VH|D$`)KCgSp9@ITypVHlDAJg4tAJ$!E@7Mjy-lIFm-l;pq-l{vw-lRLgUZ>m5 zUai~8UZLB-UaDKoUZh*jo~K*Lo~@h1*6Orul}^r<>qKm^j$jLPTsE%jW+S>bcAu`1 z-L0!-cj%_GTXbdYMqLrRPM6QF(T!zS>ay77Iu^TB$6y!f64;Y;RCc~Df;~%OzXbst$Fx;HF}?m5d(_mD-_-C=p? zZm>wYODt#I1(v;TkY%Gg!LraDVwvjpvW#>)SO&UHtl!$TtRLEytS{QdtdH7xtan;H z>y=i;dajkQ9&7om2U?VMSKG_FrR`u{*EX}RXzN)2YO7cmwB@X`+G5seZ2{|qc0B8d zHk)-&%VzDXD!h>u@-7=S#z}(tXWzk zmR380rPTh&kZC_CoT4@GH%g@Nrq8X{$zKmpT zM@E9SIfJI1nGvI{%81mKXM|}>GJ>=P83Eey8NS-=3@Jol-51NK%0BE6u0$=bE?ak2TNJ zA7~z>-__hrzpc5EeqD1p{fcHN{i0?t{etF1`dQ84^uING(@$!4q#xC6Nq#!S&%WF~6P zGijRB%vjAaW|ZatGhDNq8KT+74Ag93`e{}($(m(MPt8ImNi&D(tkEzXG;*e`M#Qwz z;7l{k0Ml60#Wd8kGDm0{m_OAu%x~%n=4bU3<_Gm;=3Dgy=1X-B^O-u6`B=?lK2Rq! z@2Y9cTk2@$b#)l?iaL;aQSHMVQoA$Hs-2mCtL>O4)fUWSYGdYM^$6yE^^deY>d$FA z)o;_bsb8dRRzFJHpuU^7Mtvh~mHKkpa`jN!67^u(LiLHXx#~k{v($UjwCWvcD)pu` zxq5AyM7<(SpkACtsOP4kYF*lZTA9|X7N>Qod1-BGZd$XtC#^xWbdSB`v)sEDks?Dk2RBKZ|saB@GS1nF`qnelcQl(3Mrc$Op zR*6#|sCcP&RY>Y>RZr@5ReS0cRb%Q!Rc-2!YI^E9RaxqwsxbAGDnIqODmV3rYIN!W zRYvMwRZ8kE6+LykDkgP{Dm-JY|EjIAyJ}AmuORxRe#jtdyln zR>~qJBW1oaA!Uv-Hbt+DNYN;RQj|)+6q(X9MXYp95h(3b2&GjDsx(O%P>xLLRsKxw zQhrHpSH4SbQNB!WR6b6gsl1mwLwPf~N_i!@LOGN?RXLbEMR_8*NO>rEl5%fyzH)o= zc;%+#T;-bNG0GLmnaV}UEalu}rc#^CP%4s>l%iz1l1PqI4kX7YyOJZ7t;yla`s5I0 zO)^C}E!kf=CD}(gDcMVzm+Y?0PIgstlAV-k$@a>mWE*8%vZXRI*-ROdY^?N8HdJ~i zk5H15e<>W3zbmYhzbMR-KPn89-zk12y;gipdZ~Dy^i1(8>9OKT(gVf)q`Qh+Nw*bO zlWr*fNxG^yn{-KWGU*@1;iU75eMx5&JCaT-HYc4>tW7$qSebN4u{h~~Vs6r2g)V8A zLXosxAx_$&Ad)sJxJm02-AStzZAmK?4N1!sHA#yV6-f&eQ=OEgv_CK@WJi3W6HzzEV&rFynuS%FBpPHbT7bj@s6BCs3aS1YcR)R#H zksy>a5_ocY0w#}1;L5`j`s9>^9=UHqr`#i9KM>JxZ>mhs!1OP&tntBc^lnZ-az-1&!D@>E9frr zQo5sjGTmODN4JsZ&@JU0x|uwUZX!>jkCMmH4djvZ-?9+;51Bvxo6L*;Sw^CNkU7xb z%B<+GWv28OvXS(svS0C!WMASR$lk@@mA#C=Eqfe)Lv}a*n(Su$W!dHUe`Ocqhh&5C z=VZs@2W1E2Ps#SgpO9^fKPuZ0e@M1Ee!py4{9f6D_+7Hu@!MtU_$@MN{3e+oe!UEh zUnA>{|4Y^pze3g&zf@KmzerXYzd%+NKUY>5KTDP$uao7*t7Vz-3R!x*RF)hsmeJw` zvgmk178;Mq0^+$ca(ti6Exudk7~d(giEopc#W%|g;~QnaX)|SCX)|Q+X;rdUwCS=Z zv~t-!TB+<7tweT(Rwx^y70Axe@?|Gz<7J0vxw5^qY}t0&XxT;@TegOlAzMyMlP#pB z$mY-zWf~e?CZom41hg0#MvId5(ZXdNv=CV{El5^J3y@XPd}UKp)^xjAk9cdrj3-j(MHIeXuqU3wC_?g+E?i)+9&Dn zxDV2=ac`v`;$BH##l4U|iF+!&7xzedEAD~xO59!PP~2_lnYf$M6LHt1hvF_v_r_h6 zZjT$1Zj3uGT^)Bux;*Z*bYa{{>Fl^;Qcc`psVwfGR1mjMipK4h_Qma#cEoLyHpOj` z*2QgrN9mc^}+7RIfT=Etp&=Eg0RX2va&rpGOiCdbW{(&A=GqvCYZ&^Wa;AWkXu zj+05<;>1$NIHA-!jwdyZ!=;9Ci1Zh=U;2gGD}7JxlD?#NNFP&MrFW@K(wo!<>1Ar2 z^a6E;bdXvlJx;BV9;B8_cT-EH+o&bd4b(#EU(^EWQfj_*0d>4|7ImytMa`BQ7uN_NIRmu!xGB3T#vNU}2azGQLi zUCG?o+Y(*uO^G7*nnV7uq@+CdxTHAth-6~y zA<4Md{gSNMy^@UBU6Pd89TIx%R!L0kW=UA=21#J-I*Cv0YKeR7Dv49I$?+Ieawvu? z*%Q+z*%s3y*$~qySsl|ZSr*eGSrF4CnH5tnQN`3rq%k!TeoU1FiK&qE#FR_gV@f5B zF(r~2F-4M!m`Re-n2D0fF?o`_m~oQqm>dZ^W{e~)CR36a!08#*%xgi*%56i*%WOqSrcs{Ssra9Srlz3nG-!iqKW=3mPP*% z3!=Y?vFOj@zUYtQj_CK|rsy}~+UQr}%IN3fvgoJc!stih3DFP4InnpTnbH4=nbEhz zNzvEEanV=Bkm2GK{vKcWtaKSk{q zzm3`}ejc@3{4i>V_`j%a;%iZx#TTPCiqA!@7oUn+BR&%Kmv~>)3h~aUW#Y|IOT=rV z7K&Fy%@;3!Jv8WfUeZi{grl zqWZ=8QN7~as4j74REL-u)hbSkY8KO?8pTmjGsPiMwPOFM8nIVYrI-{|A$Eu=7h6S@ zicO+Q#0F7?;vbQd#GfN4ir+@&iJwP~6F-d175^7GMtm)DwD@8qM|>_aLwqWdDLxXJ zD&7~FEZz~BDBc`N7q5+s6R(Jj6)%d67SD-{5NjgC#PY}xu`rS%#v%j6eUX0Rj!3e& zDbh<^7wI9cj3kN6B3;CVkxt?Xk@n)8NLz7cq_vnCX(3LEG!w@~nusGKM~QOQ4Uc?4bcEmanJ7SF} zHDZ-0F=B;?8nH|i5wS!R6tPg`8!=zx5iwWf95G8|7oihbL})}t5h~H2aJlGPxK#8Z zTr7GOE)+cp=ZWrzSS|7HtS`6#W%m zFIpO2E1Dl(BhrUgiIm~fMUwDx5ih(<#0{S!>JBd!wT2gp>ca~})#3S~^6)%SN%%NX zL3oa6T=*DKR`_U9MmR^563!CEhciXd;i;mq@Dx#Cc#?=5P8Yd_(?pKpRFQRfjL0-R zN;EP&T=Xj}RP-e*SoAK8B6<-PAbJ$$E4mX#7F`eX5?u`Q5Sig6s-s|7cB}i70n4V7HPvqiR57hB4OAcAr|&a*cbLg*b(+k*cA3z zSR3|HI6dsWuq^DYurTbka6;HiVNTdHAt&sKFfHtnFfr_bkQ#PR7!h_y7#wy>=ofZF z=oxlR=n{5CXcu-#Xc6|W&?xMJ@K5MD;kVE;!VjT;3txwx5-6Z@gbc1kd=sMy2&^1DR=wCu*=nA1Y zbeWI{T_PL^T_o%ZT_9`;ohPghog=Ic)eFl*wZh_1wQypnQaCnLE*u>y6{d%Zg~_2p zAuW_Aj0(ktp`oZSAe1Zg4(%6`LVJY{q1{5O&`zOAXuHrLv_<$Mq)GTGq(S&5WTx<0 zNUiW;NR9BnkSgJ|kmkLdXaS6VgLMgfSsO!mto995KXSNDlE8x`mL1jv-z`>ktp2X^5L}WQeQq zXRx#IbFicEZLq!YMX-(VQLvTpPOydWda#-BVz7zuT(FVwRIs7&NU(u$U+^Enj^JN{ zO~F3|Yl6QCmIr?kEDZi6m>v8-r#3~_TVRi#^8s78Nv4j z6~T7}Q-c2!ObWgw7$1B?Fedn#fE9d2zzDu1pa=gehzTANgaw}$1O}fKkb?&W?!l)8 zPQfPyHo?aQX2C}VhQWsgzk&`5z69+TybIbZcoDQ)@F-}f;7-tX!S$f6f{Q_$1?Pe` z3Qh&B7aR#%E7%vbTCgK%m0(lQ3c;G7WrF2FO9Tsp776AAEf8pe<_Tm$a|D8*Spqaj zC+H2*2-<^Gg2o_)U`CKkP!S{%ObHSRCItxuJ|hBbqdHq?E<%;R)J$sv%os2QD7R>AQ%}mQ}B~gEBH*Q5xk>R30_d93m#FX3GPs) z3a(R11s5qLf^(E2!70jQ!4XP_x4u!E8(*hCp8SVPGbET?1(7E-bVvniPZHH9sZ zQdj~$C0&3}(gZyehM`Ktqe@RtRC<1YyO z!k-oRiLVO$z?THRr@LdDX@$Cc8@GS!e`Nn~#`6B{P z^1lZh=YI@1%6}bjnEy23Apd^A0sgIkef%o{d-y{EyZD0vJNU-~w($=JY~k+?*v#J= zu#vw$U_F0Tz*_#2fYtnY0jv1BfE9d2z;eDQU@0FDSj_JaSjg`Tn9pwxn9HvVn8U9O zn8hy((D4fcH2etxDt=CYg3k$%^V0&P{KNn;pBf-BcHvs2*1fYE9050Dq zpr3CR(91Ur=;8nJ@8W;)@8G}lZ{xr4Z{a`kZ{pwaZ{%P1ujgO%uj8NdpTR%nU(G+_ zU&Y_&Kb^nBe;R+2|5W}O|5E;P|0(>1{>A*+{)K$C|0KTDewIY<`XZ82&W>(fksB4!^*k#UJON!O!w%@-zHX`6>P>{CNK)ezbogKh&Sj5Adh) zz5S_tl7B4U!9SXB*Vkl*ZQz_0Tg!LRiD%`5Z!$t(2x&YR%(jhF5Bg~#^$#7p)2$V>2h&x`eY z%M15=&7=6e;`#W!;JN!f<2m^~;o0~-=9&3D<$IJT@jcAr`5xqPeGl-uefRNNefRL{eRuP!eRuN8eYf+9eYf!@`flNk_1(nF z^xeo~`mX0C`L5-~`L5wb`u@cW_Fc*I^IgvK^j*et@m<2R^IgQV@Lk9=@}1B7<1?4{ z&1VkpgU>A9D<2*2iI0|d&qvL>;iKeT@=@^4`^b2weI&f2K4RW}A0cn2kASz?hsRs% zgY#DSV7x^>2yc$h08iu7&y)G|@&rEJJk+O)*W=T{Yx8O2HTbmhYJ8e`(|j6vB|Z(j z0-u?@aXxjtET0*?44-OVicb|U-e)>5+GiRs)Tf*m;8Vu)@+sxH`jqhOeTsONK7~AE zpGmwCJ`;K0$@#pGt$|at`knIh%KdoW&a=XY&3gb9l$dEZzZf25%Rc z$=gCs<*g$#cq_@tyv5`s-du75PfL#H$;mXHkWA%av zMjZD#LLBruOzieLNNn{wK&#%npj@>)hPyp|Ajuf;@+*Fqx9YXK49 zHIMN2noE$pW)luxvj{6M9bw|7B@DbY#1Bsu@ySz3y!Mn6Pd#PCeNPE-%Tr8T@e~q6 zo&sXflSdr)B#48a7_rL}CAN5SiFKX>#7fV8VzFm0G1s$)(0X4x&jRARM?UeHoV?6QHV;phMV=QsgBZs)` zkxg9i$Rhss7)>1W$RrMUu!&tBEMl`qI5D5At8k|^*9C&qe&5u-gqiFA)(BH1H|pm_umQ62$A zh=)Jn@8L^$diW479^QnVhZkYt;Yk>IxD$We-H31QB;vih3-Qw3nRx8(NZfUIAa1zZ z6PMg=iSzC@#A$bH;)uH?vCrLt*x_zYY;rdx*0`Gx%iWELh3=z>S?-2}%H4pFxQ`%s z?tgHu`!BrP{U_e){sXUf|Atq&f5oS|f5D5~KjHcAAMsrG4|t~gJDlnM7Eg44gHzpK z;SugH@gVmXxUc&&+{67T?(F^qw{d@jo4G&44c#B$zufNOU)=8E@7(U-FWhe958ZCz z|GC}7uen{v|8={DpLM&6pLDy7A9lNh?{T|`Z*%(x-{3Zc|K)Z8U+Q)qpYL`S*Snp; z6>fvL$n7+ayPd-O-A>}2ZpU#DQG?gH9mS`+9l=Z84&jsC4&r%k2k>mSeK^}~FV1k= zgVWu1;W2JI@i4a?c%a*Mob0w0cXQiT+EyTBw=Hu%~^YE3Vx%gtz9DELG z7Oo-baT!U63rJcVC8_aVk_vAlDe(r90BlrFe^L30~(~j90oA;bpFcc%kcLe1dBMp5rb)0Gx3qG9Q=n18~^0O!r!=L;Llu` z_yd54oh^gDy$wK6ODsOuB?i~H zMB_4-C|uwYiK8wNc&|$s-tH2LH@Jl0H7>#UG?yT}#D#(vxCG*3UHtLUE`E5ri!Yw+ z;)By%$as{CHy-Tbh5Na9;GQn-xQmM$Zs$V6&0SpaQ7$g{Z)a!xtFt5i-q`_v>1>Zb za<;?oINRdaoo(=o&er%jXDj@qvju+G*&N^NY=&=lHpMqOo8YURjq#<v#T*bvpmTnw@`Qby54+%W7yH}k4tC7xKWx9#Eo`ULO>DE%4Q#E`b!>&xHEf~N zRcyA?6-@1P8Iw9)!uU=XF~sR#tlQ}ytkr1%AL+(MNVh2e5W&5uG8OG zrqgMR>2wN9bUKMqolam8PRFqzr(>9}(^1Ub=?LcJbQrU7I)s@y9mEWs4q!hW_hX+O z_hD}x_hQc-_h1hlcVo95cVSl@cVhoI?!eACZpThIZo>{bZpC&xZo#%XZpPL-Zo*bM zZp0QlZouX`uE(^F>oB?FT1@D;216ZJW4(@lVeO8qutvv~*bK)N*fhuGSc&5@43xTK z;~bY@S&oabbjL+lvg1OG=C}Zha-5HaIL^cT9Oq)5j&m><$Jv;j<1Ea=QICys)M39J zwAfb%4fftajlFPCVUHY?*c}H2cHKdaU38FPXC0*2Ne2mb*g=f#br50O9fa5h2Lbk% z10P%Jz{BP{5SZQp#}p12CUQVA+yTM*9k^Jh!vNOg(2vyu(;fP-Qion_l0y$R-k}>C z?dJ$_61laP-Z_7E40tY^6V#I+4gxD z+kQNjYCjH3upf)X*ymzl_BmJ}K(^1uNcLke2m36{%6>FvVxNf_*mJP&c5Lh;@Y;@r zJ+;fg?%AbdH|?0%WxF)&f?X>1w;cmJYL|lT2X@*eW1H=gur+px*mAoBY@r<;n{5}5 zsR4-{4ddCxVO%>Z)@>Jywb;dAGwq_WDqyNz6jo#xiA}JJz;f)uF^*jrmSz`=H@ zAy~LwFh;Qp!hGx~n44W7<_K8Z1z@Ij{+NNCANIr67yD%EgS`Qs+LE#Rw%*t+TQBU2 zttU2Q>w*0Z9J6)D4%oV3yKG6=W?NTmt*r~T0$610jLori!qm2onAFw*;{%ATJ=Se& zhqc<;V)eE*ST!)!)*36awZigkEwNl%3oH{zvo*&OZOt&Mttl2^Yl2Y#A6sM0-PQM| zciDVJw*c#GzMv~?KBJ3lKB02}jm<|?YV!f*+q_2+pvUGN+Gg_>t+#oDRs-cWuhC+g zS7^S?OEeeAw0VItZJwivHqTHh5MlEa4YGNH`q(^1-2o??N2ra>L)6sf0Xh=+X?-94 zY<&-XYke1e20XC7gWk6O54~!A8yx}$t#6^nt#6_SfnC-&&@I;2(RJ3>(3QX<>#OJ- z>no@RkXc_w`PP?E#QGxI1GHKHi`HBJgH{9O)%UQV>(i){^(oW_Fta|1jN2$*BF7u8tpL1h5nYB!2l?LvEiHmjXz zz10r18Ys8gjuu;OL-T=LtF36J)fSWqBwB4osaBiN2q4I6BkE(d0d)tQtk$D8R_jnx zV5HSr^rz)o^t0s}^o`|e^cnEL@-OtZnxX| zD}Y6oOVBxh#&R(#wOoYq0mO14+GDu@Z3XHr=cCm?x#c{x$Z{^459C_TK{J6g%h_n6 zGQuF|@%R+)~wh*IhffW`abP+JyLWrsXsf7ULTkugX&~3p(TY-8D0<8k3THt6A zkZ*yZITk3&0n#iGG!clk;G*FG#bN*@18x@msG~(6Y7LlJ^r8m95Az=M6Y$!+8+{7g zH}67k0hi4?(F?%e<{juUV83}gy3@Q3-3+WXZ$*~_3(Z^5*?`Kt8I=G$^CpxFbeT7z zEx=6k2DAz&Gp|PrfeGd_(HwwnUWcXv3FftEED&Zs0}TYo<~1k@a4@e%tpF4ADs%+! z-K-M*2)s6%jy?hInN^@Sfy-vo(DT4)vvTw(u-|Mdx&zo`2AZpZWoD)50$>)PGMj>m z0m7^V9RRw_iqU4E&a4Qn1j@_`(aAub*<>^uU;zxXNhlqNF)KhrfdI3Ks5d||%SY`2 zOS1{6F)#x7W}1h70A87nM;`-sO~;`(fJ?wR)3N9&;D~81x)0cHnuBfxRs+jSv(fp0 z-gFGA1VpA;C=T=kou;GFCZN_d6P*r}0+UQR=y+g^DI3iIQcPKBJP-|pm}a2I&Ea7N$(p2>5N1hJFR!120Wd(MP}?;JOI|y$GB&NkLBnhk?B&$>=sLs0>M0=>o|XdBP~)Bxqi!Duls5g2P6gk}OvAjz15#sLvPkZ~aD3%CPLfQ@kg zY6gr1ej53spMf{PGb2Cr0dO0*0t^}XqJzM3;DC`2x(nC>tOZsWkNIQBJ4?AbCxAo19$*`=9#{n| z8EJyf1+;)15CSOB3$z0bBaP7-U>Z;YOa#UPqk(iFX`~Sv2SfrvfG^+yI0H6-8DI$f zG#G_`2HpbCfd{~C;3_Z#3-!v&XL?dxmF# z!#Un?7WYwv@^wFQY38=f}>XGZPpojW|c3C>@FGnCSM zU2pjJ?jD{;1ZN7txj<`r60S*lZVb=Z8Pnr_HKb?%@VuI*-M@$D#;od2yUgppH#~zS zt=s>SXZOkBc_vr8%r0*4S~ol!1kU%!?9vR++4$Xgb$H&zwoZ>BMdzX6*%8c6qYLhx ztB2<>z*!0_J2b;H4GKDL49^xA)!}>gX8XzEoPL* z#SZh-VJ14vHHX>cFkc*Igu|R~nAHvQwqa&A%)N%$)i8e=W=O*vXqe>;^O#|#GR#GW z*~T!R7-kH^oM4#s3-fwm<}S?5h1s_-zZPcD!W>zc1q<_BVJ0igRfXB8Fy9nrl){`* zm=y~1K4E4j%-w|9nK1tnW>~@;N|+@H^B`fSBg|!l*@`e95oR31oI;p22=fAA<{!-M zgV}p9KM!W$!5ll7MF;cbU?v>Qb%WV#FkcO3q`{msm{kVz#$aX`%>9DdT`+$OW@y12 zESO~l^Qd5^6wHN!*-kK@31%$8oFtfa1oMhu<`B#cg4sVXzXxXUz#JWzg#+_!U?vUB zm4VqXFy94cw7{Gdn3V$aPGDvU%pHN*Au#^~W_Z9H4w$6@^Dtnh1|y9))m&P z!kSZ9HwtS%Vf`ko!Gv{`uoe>5Gs2ogSXT&Z17Uq1tkHvYcCc0s*1N%)HCT5BYsX;y z7p&oeby%>L3f4oxnkHD61Z#_6eGshifpt2t)&|zgz?v6Ww*qTVVEqWJ0fBWKuoeT> zQ^1-CSl0k+6JUJ-tPz0s{P3J`6xW&gy)p-tP!3U!ZSa3ZU@ia z;Q1Lm1B2&S@GJ_RC&4ozc&-D_X5je>JR^bU9Pq3Ho;ScV1Nhw!zun>YH~fZ%-@))( z7JiSyZ%X)G2*2&%_Zj@gg5OE-TL*rxz;6!t-2ngl!~gH_KREm!4gU+n|FiHvDg0jv z{~N;pckn+N{GSE?E5ZLe@IMRu-vR$S!2KWY`EZ|ydpq3E;U4}MGV3$ktKt3(_hh&a z!@YMQm;MUwv2b67dnw#M69%}C;65qtZ@3Tl!xMee?!bNTO>glnxW5_o7G8(@m|0Kh z6}Vr)nOksQy589{1ot1f=fHgi?k#XXfqMwtH{f0Y_XoHqz5GQu9t9)gzF+)3*q_)*F3n+!L<#pXK)RJ z>lR$A;Q9pDB)AU2wFj;@aE*cM3S3Lz`T^IB;dKJ64RAexYXE%j;kypsZ}?8b_ZYsr z@O_2vD10yBy9nPu_|C!i48B|NeS+^0d~e{p0^bk#PQdp7KKt-_htD{CuHmx`pI`XQ z!siq|oA7yr&mes6;IjswFZfKs=LkMK@OgpH2z)N!v+xJ`|G(eJ|9-!a|NVXX1-~!g_Zj&Fejkw!;P)PRhr9*9H^^(`74j1NULenrXUJ3J3Gx_uggitZ zAor1b$X(Kaj89@4wZln`wM_Q03qyeczW*}9_bfg?9LrRb$WD+tF$wS5=IY<_giLekR zl8PiF2?!0LBGE_$5{d*N0f-+$Mm!NW#07Cg>=0|j0x?BKAqL2A?ho!)?kDa$?rZJ~ z?o;kV?mg~*+#B4h+)Lac?m6z?+>_j6+(X=b+}+&m+%4P<+_l_Q+-2Ow-1*$uTpd@% zm2pK}9v9;daC^8N+!k&Fx0YMQoyINY7I6!>dE8uX7MIOsa#OeoTq-w;8^#Ud`g6Ux z?pznHJ=dCR&Nbp1aDNVb9r!TtX5jh2;K;!Kf!zb!1~v|? z8CW^6WMKZltO50aY(O}G4{!&12HFRj2I>Z?2FeGD2MPwp4`dH;2ABiM1GItYfv^F} zfX{%(fXjg0faQS6fWg4e{?GmI`d{`x?!VW6v;T7cQ2${6iT*?Vd-}KcZ|q;)zr258 z|LlHszpP)-kM{TWxA!;p*Y;2EFYTY)pVyz=&+bp{Pw0>B5AP4`C-=McJN8@moAw*@ z|LFVF_onY@-~GN@eV6+#^!?p;v~Pdkj=oKOtNWJq&F|CqDf&cxSYK~ndtXCeO<#Fm zQQw5VoIZ9Rqc6TMx-X>9ug{~;sn5F4q;Evux8C=?FM1#L-tN89d!hGq?~&fUz1w=% z_paz&*gLCN*(>ZtdwY6Yd+U0q_fF}Z*qhtS?q&4SdLw%&z2sikUb|ki-jTiEd*1iF z=y}j{v*%LJ*`DJ)`+IiuZ0K3pv#>|sqv#RzaCjJkq(lb5rNa&IO&CPH`vF z+1Xj&IlZ%}b9^VKGr2RiGq}^c)49{Kb7beYjyD~TI&OCS({Z}vV8`~3wH-@3W_8Fq z@Q&_|#*WI4;*RkhoQ~vys4?aSNev@6_n?TPJC?E&rX?Y8a4?LXSywmojU**4U6vTa}6=C+k>^V?Ky{I=e< zrnbtqqPB5uthR)zdX@t=d*$YkzA?YjtaJ z>$p}{E4?+m)wk8T)uQ!J%g2^yEw@|#Z8_PpuVquq@|HO*vKFkRqouZ`tYtzArzNQ+ zvc<2(rNy#kM9atKr_HyT|7kwayr+3X^U`L0v$%Pnxuvkrg#u3uiSuNT$#)i>0a*XP%>>*@6& z^`7-M^&{&)&3rQR`pmO456;{&bNS3!Get9dXEw~7Ix}x3YbI@G&`h_PRx|(9y{mgr zce(C#-QK$Ob&Kj$b$DHSU3Fby-I%)Mx`;Y*oqgS?y3e&wYj4z^sXb7;sdj0tww7Pp zSv#Y)xHh{sr8ctGr`Eo9RPCo3Pi9=7F*sxYj14mu&rr?4XSB_znlWj{=otw!LT7l) zu$u9w=55Wrnu|5ZYj)JEs+m(GuIa6rSyNgwwkEYEs>Y|rzQ(ZTWA&rzE7hl~_f)T~ zo?k7k?yqjBE~_3_omL%P?OW|oZCL%W>QU8|s#8_Fs#aIct&&vrR?V!MQk7GcQWak1 zRb^B4r}Ay(-O7I|k5q20Tvn;ABr4l0D=Q~fvMb{%11p^?jVr%Qe=_~*^i$J!PhUNK z&UDfA?&-DDi>7ByPnaG&oiyES`nQVb6*npdEB02bt(aFKspze!tthIE_nwtCv^X~Jn;)2gRUn#P$HH!WbA)3j03K9)Z$zgT{(d~5l#a&J0l{(dLs{K@hsc*~f zlwBx0Shk^TL7B9yx2(3Tuq?BTRu)j^SY}xEzVu${Q0bx44W$c8rKP>4wWWonoYJ^b z|5ArigVMKC?o2s9W&f0QQ|3((P3f9aJ!RsQj49Dm$WyGR{3>}-a--yQ$*z)>CAt#4 zq@`qPNp4AUNk|E)#H8d?@x$VOiw_rXEM8bFE$%6LR45p{S%Nt0=xGpva-fpy*BE?ZPvKy9-wp>Oet9b75Iwc40yxrO>I+u<-5V z|0bWEyl3)Xll7B{$<33?CTCAhm`s`MICx8KjawgCx1Wd4>@F(v@-nG0Fd0X-pXV=DitzYy9c)JH{^^ zuNdDuzGi&>_|)-X<6Xxajej@p_PD`uJI5^>rySQeu4dfCacSei#<`9&8uxDO?XiE4 z-8pvISjE`hvDITIjAe`s8S66EaO|7ho4KcQx8*L*mF9NkPR|{eo0Ln*b;$jb^CIU; z&e5EWIrDM^IjuQmIaxVzIX*d7Ip4A$W)EfW&t9Fa%|^0kW>3ma&yL6@WgBI`8*^*S z=`q{KEFL2r(>bPMOzxP3G5%w0$Nb28lJ#%a!K^h|`Ybf7K5KGTdR9ahDa$D9?dY4M zPmSI>df{l%==RZ5M~@jz8|^dNa`czX`93jBn8%nKm~)sovw=C8$z+BxotYz;FVZfj9ZFl9rc2|d)u!dArKC~P z?9+axK29A<-IuyDRhin8Iz2Tvm7eOGYMJ_(ahEa3*v?qQ5HZ>qrHo8QG{c=?#CVf( zJ>^)+hLqVUSjxOxZ&*aC+L&sUc}{Qd&|-l4H{E#3zaWB<@RGk*G-QPMnsQok&geN;FM;mvA%Tc*4enISE+8 z%!G*vj08%8UBY+zL;5-TF8UI>gx*FkrE}KBiuv z?xrrKN~!JCQYwcUNp+zm2*UbtGzSls2j_sxm4!iWcP+ zWfJu^@>=AP$hDE0$iB$R$ehTyNUuoa$Ttz!A`VBaiBL!MMof>$j-W<(L>NW93cnJ5 zF#NA@Wq5aZd3aWMbhumi$nY0o7sK|4tq7Bcb%d3Lal#_PT*Cf@J`EiT-5t6#R2l`Xl6F$k~wXAqztIAq^n~A&ii~5bKc7!FPgB1#b$T9gGIg2p%6y4<-kj z1-}cr9&{vVO^_z2H>e_LOi)aaThPd$7nF;XeU#-CDW#24Ldl?nQXD8h0v`sR4cs2M zAdnYWA2=~EInY1QGVo)-t$^bJ>jQKF{Q;E$IRVrFj{w7f7ycLh_xUgPm-@H)m-uJ+ zhx$ACfA_oZH|V$3Z=N6SSLZjuFTu~p&&=vzzTLj%zL~y}zAnChe4hB6 z_u1*Q$VcGQ;8Wm};uGLw>GP3%i+qf{j;tm3k}Jq#$T4IR*?|1ad&qmY_hN6Mca!%d zZ-#fEx0UxNuiIY7z1Dkaz52W=yvBINc#*seyq?!nY^ql0G;u+v+>G{#) zrpGalwH_Le9*=1rqdlTLTs;1`KXyOwzQcW?JI}q|J>Nai-PhgB{hix2x5I9KxhdQ_ z-AdiqZeeZ?Za+x(NrR*Xn7hU(cE^`&Twzw9$rn*vGtzAF4 z+;%zcvd%^0((5wKWwc9_i;K%|=SR-xoVPpAcgCITob#ON&fd-@&aa&=JMDK`;Uslx zbt-aVIt4k|IDK}!?Rdg*y`$E#*KwL-mSdEoi{o#HM-FElwmZysz#VEG#yiA2csm$7 zyt2P!zt4V|z1Y6RzR*6^KG5FE{-fPZyQ6k%?9_JMc2n&*cHwr8c0X+I+x~64*>;XC zVq0ySYfH6tw;gHw%x1`Dm(3y@zD>PNzD=TykBzC#TkEUV2d!6H%dFe1i>;Z~LDn|b zpRI0N9k*I%rLpRON?@nU0v zaf9(h<0NBWV>9D7Mpuju7_Bgp8nqe~8KoIfjI4}4j=DMO=%_WLRHM2^m5pML0ym1I zz8T&%JY~4iP;c08SYeoD7-i^U_^p132p=3+PT$ob9cLDJz?E#U2UCdjkktcJ6r2n zOIUAMPFe~q>n(FFlP$w7%F@VE+On;f#o}g>mxuKOtHolCbhluE|9-hyi&w{7_eOYg zs}&&cR!W_@_tj^+7FTUk7Q%r67Uf}(Krn3 z(goSJr^f^5Ob^e(sl)iLnAIb}S_kVb-U{DYiqFSa_TsnjO@8s>*iv3`AI!-uUKZ~; z#g}2hY)gq8eBqI9y@nr@_z7=F_BW#O^k|OnJw0~db4hQHI-Vb4(yJTZJbXN5rdtDx z*9rM;JRH-!^issw$=iW0+RueN&bm+e&ZIOn-awzE+-{2LJy}dTbx0jq-acfWsJN35gNo~B9s4W}4 z?AZ*Tu_tRvHpHT(2Urmtlq@{mo?bg-bsJoh zrM)W3Z#Ozu>ej%uAMciIj#U)y$Gh09r-xkR5|w0^HEN z@Uq&l{<5JKYo@n+^1-Zf^Y9C6mbdJ9f0>qUYt8nSjZDYKvI8yF9B(-o4{V{F9E~;C zIc<|^IUH-Aw;aw`{PP}()mo=|OMlM8zw+GHFGp{k{r|Rb z1%;I@z$j4>j|AOtK2()oJ$1KK*(QgOyz=>CS!OZW-@?VpS*qkG^V1@X>h?gPtu{!cx9K))!tX{P}XqEH~xZa&;}`Z{bW>qf5_uzFZ7GRYc z5W2O8YrZFr&jSaF`Ngc5U%V+6s#OLZ+O>2sS=zH4)*>HDRxGltSDC^UVv&wsxFH)` zWRcRC>nW=%oLk1%N~N9KE!L!TP{s1r3f3;gmv$>H8!KDv*`jXP*K(MY9mFqX(!1@y zCd(I@#MUaznP$Zi`(rf~=T5U)+`JZc!|X~{Yfwd5cjbE6n^vVPmMX5_VgKE*Kvm~_ zIj8^LvB1(eo5h?*AlKCS@N=`|Ia|4X@!8w?h3l;?TB{{knr`^#VYzJ$UL&7mVSIu2 zXRnUA5Dlc7cSJoMSG z@IemE&9czh7Owc;C(rf0hdEz3x&PX5Yv=F%)<`SMSS>@IFY31jbDXbQcz1Jt!rkS1 z$>xf_icaTah;Xwsl6UK)vSln*ys)ec9KOD-hNOfirp6?tB=ky8j7*D5N=&sxb{>EnVijvCX}x1&#MKmWFq z+l;~dmWfG;C`g4z#EpqdjEql@iXM{?9vK^#82$fwwHEAq;eSDe+p$=%`LL+Sw6f4-`eg|d>S-pI;&pYdhTI9?rnW0y2ty<#AqM)#y;*DKJMPm$xt76 zU!VH!na+vfKJLwZ+<+HZBa>3YV!|WSl2TF!`?m{g=il0r91;_gW=V~kkQg216B!$x zVhIaN$1ZgYOS5zh84xz0>ySQSp+mcO?-?3uiBC$L;NyHtPjvl6B175nNUR3Oo0=A$ z7#S_cYzYnP-mBLT3l{KikCi?Dt^A~W=P}&}ga(BczK4ZIr==%{4QuP0ndzF}BQ!Xy ze_X_v(4_Q~$mlV>yLYz?jL2$TxEfi*@aVV+v1!iZ=;+_6wFR5RR+78LrG-Ri3<-~j zkG9BhIJX^@lrGb8*vDS+;S)k!$JnMdeo^FN71{aZAyeX_qT-{wg+zzPV{x-4tf7B& zqUB$Q|KBGhH8v?F&F5bW71`a^er-EiBAol#%Xu-LpXebyLx+U*>KfF4Xh=^>?}0;o zy8ED8`?hsH;_+j z|2F<@JB;;dnGl(rZi~b|MQ655Xp8Bz*z|-5v@w_;lbq4EWomNEDF5~{Cq5}WttD<7 z8~Q?&Ps<5WQ^HeXTDJCSIjD_K%b3KZmZ@neagkUgJ}x{p4*j8JOpNP}ZJ8Qfc;{kX zRCro=(dn4vmXS$`X(>2hTT)C6dPj)#4mtZNg@zvsZ-=*c}pLI#CcoCo>*yU?J4y@&Si8uEP3z^(&> z2KI7YBwX+bX|d0*x$`bD9i*$XgA`tH>6ZW7k*rmbPWEg>cy@Pn4e32}K+l0gTsxQC z9p}T6h>;MdIJ>YHzt~fYoU86h(J>(dlA_{b;-XV5Mebl{&wt^Lcit(_HXIr>s%O}M zpitc7-TM^16h&@?XZLnWcvM`b3~5EaG$#SWSa@1G2JC;2FaE7NI`2UlOJqH+rHb4N zvV>f4If!S+P-Rm&vaXWg?&@A64JsW z(59snwz1|DZf0~hxz8-V5vi#bUyKaCGSm0JdKoOkuCjC^NX&k$m0Kpjl1?4#~BqJkv;*PF(wJ8!1*~mA_4k=ao~+O8??HUF_{dw~%dBraCjYgZk81`Rd70&M@cCcM z)hqI4k&kb_xLhO5=z@Q)ms#IVO#f?ra*d|C7D8i|`wE}`wcI7lkOOqR%yPeC`d`ca zi5ceL@zE^z;Kk*nH0F(eu9sP^8dfIjGp~av+3YH2rk;N%rH!K3V+O8AEINf;59F23 z?aJ;pd|`c4idijvi)_Grl)8ZVEL+=O+-liWWQO_J8Xt;o_j+xspNQ4>O3v7K4gr~);9vnncv7N=3sqAPT#ZdhP<%8 zpNg!na*_2-d|`ddu|8z1&tB$Z%nR$gj`hj$$^KQvKXbepuJy_NB(IuYR?8W4Q86v+ zlYcM2u-u)pR#bSOzsz!T@d1}J*?bdS&T8poCeX@q@>=a$U*VL+vKGt9y=q=&7gk`o zqUZTek@F%cn>h}-hGuM$bsWX|wwR4!+I*C@NH@2vtzxyDzziSEZ-IZZKDj=!&7$i| zu5Ps)!94Ra>oe1)Ejr)B^4C){Ut0HPdr>&o{alD=W);y|BEOMTR-&YpN`dnoE(FyQS0%%a^jGoA1%t zt@ys^%N^0mzxThiWrkS*eZcCBX3PxPpMS?QsK#0ro3GJHte7tPa(9kk&*!-R>rR*T zNiTi=a(9jtMW_FLwcVX}YSHhjJNIAuXW>ikfafoF%Zt-Bo_~o??&uBgqLn`SI{sBa z|M?WHc{$hnU*Q(g{f23lhEYWm7-#76zX`Kmm?bgM3$vWzQ<3=S#cBCTk*_6udSMOD zZU5I^77h4a`GiGkOS`lgZJeu3 zbhQ#g$nU1P+BvRvsjFS(YUP^BauOp*>u|La3&`|0uJ*L6{n^!CcC~k0?L${99YlVI zN2#+d?P@EyT6xyX_ZW(uZ3|c1-_?$GweqZz<+5DuY*)L~)oygPAG_KkuJ){}z3OTo zxY|0nM`e9&Tx~a3JJ{8ZceP2bHs96GceR^b?N_e$jH~_K)!uit#W4)ab}GACe^;wq zZC_~-+YEHIA=1{jSfX9+L}~H+bk}sYYkH<@daz z>66l;zn+s8{q&Nw=+A#ji++ArT5R9V1OL#Uy`)7yt{^S?dktxEAJmr?#}OqhmQR)z z>z(JCUMeltztc6XrNwq6K9J=vON;HHg6y0wBQ3Vq)HU5sT5LDiH9b~ZY(LXAJyTlj z$Lp?XtjW1QSgo@y?P_IQlKu2?wGCZu3s);zt9&nUhO{EdJ?wTI$Y9m~2 zjH`8y6IjkUPN1Fcn*WNcUEpdLx!M)3cD1YB>}t2V+TE^pud6-aYCm_i$6W2VuJ(+p zJ?CmKx!S9)_CK!HdB0-+M8uQhMF{9@5%M_OimtYntMzfU&0Vdps}<2telM}Cv?7R0 zJHXY72q@Fxt~SoqCb(J=1?78*4W*sqYUjJ!H(c#9S6f{6-={FXlI7(kt-0P3qsz2( zDYvFjRb1b<>d?BaPmz~@TYvxdt=qQg)WOHc&pE&F-QUlzef#!4KK^Ywwr|@}z8LRi z@7cdsVP#&nCeOa6GQ2%|tty9`9zD3Nb52uBJxd*n-$&E8@49QTJ04W)GWAcZmo>aw zxck%|QyZVCc?R>7DxAQ3SnY2r^shMJ;P{#2k*qZG>}6R}zE_Q2mIhDnKY2QSr~7t4 zN9q1$T;JcgGPOmqZ@l`Ka!p^p^0eV^S3LWdbWNYX@@$9xhY#1E+G!yEReWNnPXE|x z|KE0c|DK&5+_KZVH|+GuRXer#%}$o{cIt4-PTw52)6v6rYR-1L_K}^+yl+F>I zrkxJVwNpaAopL7I>3XD{c&MH3^s>{d9qjZ<6FdD@#ZK=Ov(w?*`PBc{d}@0vpX__` zspZCevMtP~9Xa_lJ362C56q`=9q_MiJ{>5Id4J~7&hPT5%cptdw>pnzPRk=(OdgF4 z%A?aQ@~EIp9=YGlr4Nqhl4Dyg`M;J+o{72Cqkk@4YL-h^i|114#T@eC912~LL)X%B z=*qwx>eDob%35=%^OiZ~@0*+?V;#HXx5}!#^0y4?NE0gY@nnHs&OreS?Qz%ePp`#_I(82FBsNtFnx*nTB zHCt!Uu7~Ng>p(iynww642B%Y#s_FFQPib^=T^a?&q*0URX_WY9D%IVdN}WEx*dYB@iFZgowdhWFy>(B^pheoQ{gY@( z$|M@s0PS}ZDRBBk3TZu&PW=)`M;F9V>%cfFaW$6uFNr1huCdhY`UKkl<^=kx%LM9q zEr$FS$Iya+7#epmn%2&ZrXl{(lyfSID&<8{z4}qK?(;}mGBJ|=DHBPjwntFo&VRgRIgDs&`OxjKSM<&U7O3L_|T<8V6M zX*j)mbQrmX4Wl#v8A>lr8%mEV45i-dhfujTLulxMP^vaKlt%s>Le&yNXvo9CRWLzxvvSPfabw;=fgqNf(FrVUks#LAp_~;*#YDoIe?B_>rb93{ps+7epJ%lkB)lu zql$C;(obdkQnSTD^sq`04P4QOn$+$?GuHH`3H5r@vA28C-Uhv>Tfuj)pnYILLBZ+4~Y6}r;q1zqSrCA-kR8ALUoDtel!DDjq!CQP!? z^^1Y@&*(r}_FVw&?;Akr`#aO_4xMS{)=uDxChZNWNuTVjK|?Flpf@I0r_>YG=&moozxh?^{Ix37yH6DwvY|40 zxK*YR<0?_`o{Ds%az*l+T!E?|El=+@E>AyA^`=kGmZN~S!2rN*^gJ{!dsIx_#)W>Kpe&d6a&v>VNP^Z5Z@WE%?s^_0#M3)ndPUYRBr5;~DsiN%Pt3KtwQ}4a~jhfr$ zgu3?GG4)mG*XpHd6rvPYIEvsbztN=b>qi1>XWgnmCw(sRFm;5)v;fet198kl;zhq z)%@{G6#u+fy)kZ)@;>*vYCZZj_0Q?~DskAWYVLP)RdDbewg2cV>gPVQ)O!bKsQO)| ztG;_*R`uIYRl~yb)RCdtYGcq8^?P8NdZX23wWVI7YE^NPs_zl2X5EQWV}1))o4y;T zCLS2A-q}7vjaWTY&6yXXI%W=16QcU7YQaHjKtL~5qH%W>c+pKd( zY@e?>WSc*lZRe_gYTJ8ir>(`3_icV58*RtSuC;j`S#G;BYq4!&xB0d=9?!DHe=^l} z^-`KGVpOcH|FO}wZCwZ17Jk^x_D|#XwtLH(*=BpywtbT0ZF~K?yX~btHv%`VI2pJy zyCAUEsP%yzJIxJz+A1Q@?ax+$exZ*7_8)mO;AFWkJ0nXa2@M`01~^kLXph7Ln7`+H zv_BrHvUdmC&&vhvor!jHXwF`V74X}=WzlZ>bKBm7h#O{?`*LqG+VTDu_DURq_3z#C z7;!*nuYyi!M;xhApb=a6jcHIIF$VUb;JrtPBk}?Z%AL-TnO-2V367=U*j+nizx;Z^DUlzFi zVW({&#|tFh!Fel){M}A(T==n|*cEK2`GtbFF5x&*elL(%2(UKjt8ghbZ>YWhs030MvnNCc1mAU z(XsS9tnafbj!(bA{~7Ocb%(@PxQ>qVU)!mruaD!x5j!0j+`#eEmv)LuZ|soR3)kAQ z^N^jU6};ql?K3--_@$L2e7~J$y0>viT!#MOxLRPR_`aPStM}k~CImWyK0*ApkQ@@T zq0cy`?Ls_us;8se4qTTJDs?@&>=A??kPvj5Ig-{b%`Tkpq+|se$(-BU#zF|GKa*gxbGazx?}#B zm5w2V<*u)CqzB-4d8-`~%i`X2tZ0LNvu2&+tyYL{{nk5{wy;z9{&yS_=i>f#Bs4(( zxbUtcs4n_P>Sjl+ns&Gm(`TIv9DiTRrS!JaH`fDW5L?vCr}SseI~`d%#ihyL_5n`k+H%Zj3pOpCo2i9AB=? zr%!Ds9kbuerww2K;E*^Tblk(|@eit1Q|6`nVTnfvl(vvPbI*!Vx6%VgCrVYubx^u5OBsaiV z>bT!0pUP~$?r6{*%Xhrt=w-{NQ-^OlByYfY>qzj=r`*f894RgGX zAvp!cWJj;+IDZZPb~LP*PpLZ}I_{Uwr&qfEdY3A?cbhzlEKyZUK85F+9^WvJ z$}g#=&(+GKUq)BggDdCJrusFsNj;I`>r_9shGKV1cE$?sA<{Uztp$6M;_FLviryOai6 z@;5wZ_2zeT$>(W9J$Fqmy?UsTj#!#Yx8^n0lH1`~tnbdsrT3~e)!XxP>7VmWb$CWD z_1Vx&OWud)wcZ$=OGo`%=+0wv$>Tu_eQ-!Fwbw6c$qDgH*L%C?(#*cTx@kZzz3tsf z&ug7apZ?HFOTLKbzHVDDm%feg*V)x_>HDUw_3m=Hbo@qZEx9CO16|=s4(-fttNrih z(6TP=bnojqlv%vJmOK;jgC2S|hw3ltpa*=DL)V9Q)B#`Q(DvG$wB(?OG4wwl7B3SkeaDc{zqqOAhi1&2+Ct39QtTB4r?JTO%Z>-M! zJ&U5tjnk6TBPP_VzRjWwOT+YAhqI{SnDKf^K^6u2gloz75jX1CjaihoDMEK&i5ftB zq^^YjYwaArC@r-B#FlzRRu*M{60HX&W)bYa`tOJ=>eFR{mO26APu;qI7TrD^tM_%u zqCNBCbdPpflr?CgmKp+LRP9#>b%h@$>17qN$i5<8-z$#&9G9S_zJNGZFS(gXZ7wD1 zA1-Fn&P_?W?CDHu8lSAC_JCMdkKc!y!>!3W=fg}I{BeqYbyFs-%SzQ!mq0wM7rvfJ zjVX zYn4d_)pGPV^)u<6A9Hk4l}wtpI#)}r1F^S$?eP@yX_&9Q|C&O-Ue4FEf15(fHrut- zK@gwoF-N9Q+R~|dx1K`#9!%9GcTOSCQ7>z$ksyZGuP>WIvujP$hvwn?ylMKc{3&$j z{4_1~6U6ztMf4QvziztjJYotZ<9{pBrQZ~KEpmpI+6r<3?dv~Apsg)u>k@l1 zXz_yCdd2%0ly-BrmU<2H4*kx;3~Ib%j;=W)gYK7~t7m6q&}S)gwbXKuo9JGnGpJwN zd3x!93@Wi?o<2_*K{a;2sEo(`o14*L2Rtbb6`Q>pFN@I<3onT}$l< zxspDglTKN-g?ed1I-PrKq3#`)PJvGrYN;zBpVD)>rPCF?NY`$gPVMS0)*Bn8Q=WaX zmYNfCF8!8gIz6H{bg74F0Ez(XM?Sa$wsu*e&y`A}S!-A5_x?$xk(QNO>R-qcb<^{ybc0vwGsjYC zTisRqWlp7u_ElPHW5^}-hig;mxOz*|!c@v!{g&SUaw^q)@|Kpm8S+iNDI%2yIacek zp{ew9tu=a5cl8I=TAK$0YE7jiC{~S!AU#7gRr51I(bM6t*Njp0iPhR7{}?uWi(K+)}9Sjg4CB zd&r}8jSFbse^;;hW-`?+wMp09Kba~_+@z)Uhg@6VUo)95HQB6(zc!f;&f2U$$e&Da zUD~XrE{J?w)7Z%ru>L)r-G4G!-L~lW111xX-=d{vh@4&Du0ENX)p=igmP8#f_kCUI zK{93j_`a5UBJz4&{)c3Gf7w=TJ(Ns=_qXb+yHIBw`hk{OBXWPea$zzZs<2JROiiZF zleg)nNy)V7_%ZLqIa>W83xj&6253&<-s%O4Jbat>VeFz1U8j zdN+w~M()&qTuh=S2X<vPtxA^W9o%qNr); z?bi}%^yS@p_31=v-s2NJ?ej$XYuzVW>ZPcA=vHqhQvBFY^@GRVgu-_|71>TIp0K8rexj?YdYzjmzGO-P`mMXZkv zNuUikSxfB}wHjTzRRTTUyieDzl|Xe$?AMJ-CQyf{{aWg}sORV!7vm|k&H-KGL_7`6 zIiRl<#M9u@2ej0DQS;Gnz8O#ci$2rirpHs|o1f`A$?)eEIZdu|v9H z`*<1?aY%Fhc&f>VwA6}GJJM$!O`>U;pX(97PoicgKi9{;pG05zAJ$SwMtw=I-8zYG zUpuTHEuTcWy}!`?XHBBV>%Y)aV@3^1pBy)du8#Rqm+m)-LO=adcj_>SKC1kcmija5 zR648NB#J!tm45ZnMEaol5xwNfMEYwMTGXad%hIp%L>f;=bfNZD>4>9oH14$%`nTP2)clVVdhGf*y3y+!Ewyme)^wX}eE;Mdy)ZhCN{;$g zUk;9=tsi}>rB06en@(#IM?c1Yr$49=M-#sIPXGKkmaaAUUP}!fH9Fn+`&c@4_In-3 zvDCHwNgecFEWNYvq?YUg^M)L0tS=Lg+sQYFF$DzP-l`?OB5#?rh=r?u4OQ4iGTewaWz>z&cB?4LlN=AO~b-k(6bPo2?Hvq#NP z4}N(9t(<>WpPn>l<>inTU>Dy0ZDEEV( zwAA`hd(`v4kD=3%=k!q>Ls|NqcHbOB6{?@tq645lsfXspQ1fHw_2daLw7KceddA=w zsyqE>EgAu8nEJIwF?6fLFM4*l7#g(b7d_?gXj*^$7cKe$>YO^@>uB;@_pA2a9ZeG- z{i=Uj8%-;RUeKZ~pcbk}rA5=lk{5NUanbZJ@}mB*cQkqGi&}IC)JydrHKNHY z5lv5y{HCA$8AVqcUDBdSpr)#C?2Dpz&Ro(X-;1L3Hkb9@#ZeSE|FRan0(Dm%9TP=6 zx?Iuk4~n9(E3W82I!2N8&J`_M25Pf0TdwK_=OU@YsH<9Z4%Bb; zmTi$#tIRe1{<27VIp&()@Ny)b<7-+p5Y%{ePG}@$r~IKu1xC`|BY)^tjUwrG!|Ph~ z5!8W^PeoAgQ`dFQ&k+>q_or_8MFeHc`BRH_f?Bc8TpmF$2i(x!(;_JAjT?IH#0Z-3 z=M62o3hK%Foqz~xy5^>?(J+D@-M^`4m5!i8!T-^sxuE8(d!7rYK)1j2vP0o?ZPZ`- z*RA2SVAo$-^cd8o_2~R?+8cFC&y5ME?v7h}$G~tpQ2DkNtp>GgeW^}3z4Q5PjN{={ zqV64i@5XovpK?cwj)VHPzNE*~gC=+N@r~oD-PF5!`-1Tld-|>xjR!SwJ!;%|+BN&0 zuGeck9r@*+{-x!3I^FTU7X1fxa^2%`7@hk4zP|cf7=6*@fu40VjJ7X(phX)(EnRO| z8AcI({?<*Vhf&M5f9rJfr zl}CRthQ8WoWzoK%HSn;UF%(zTjSq*9p&i}axK*DqbSJ@$MHhn}!IvwIp-Bhbxb36S zwC1K8Xa72yj@58y(afM(@Sj^pQ|-y_T;q+=WLxFVDtj~yKkUw;r$N`?#9pH*zqSWw zy)>HU^zq=F3Zv<@R1X%d4cZ4!I6sQ!f9b)&2S?G2J09%+-Y811TZ~1AgFeD%(nnF> z^kTer^eB31Z7~k(Itq2QVk{aRG!#BqdK7)+Q=BK>8cEao73UJCM^e9x;w<_dbQW&5 zek6T;q&RP#J(6bK!*t?E>Rhh`i?#XrB?Z@~$UOY&n9weM++E zh0uL?>iyw#HLWDue;Q5$*OcV+{ln>lFH5p$iO`0)&%EI@u8tQsP99EM`*`uAA;alG ziWiH{2>pm(tuvhR4tsGQ_u;hrFMNMx7+tSfibaEj#>9Ph45MDjrTEg4VKiw)DbCCu zM)MAqV$mm|L-CC6!)Q;n()^^!F#57vX-+OZjJ}I6&7xgGtK!Zl(e5kFi$5JoC$5#| zi*F63LzT*~=$g>8I6h`5y%k%A-|0J)US3p&zxN$VVFhJaG*4(=T;u)_D(zjC{eK)n zXFHYUEOL%sBI_> zf6tqPs)f?m-+A-NM%JYYFLg>)jq2GfeqD)67{2h-u}6<9P~ zXoB2);$SLA71=gmFg1^@$i4jrQbt_P~HXwT3(S#23e85OJY>+=UviNLCSHfbO&j;hL{OG6LkVQmM}vX83roGJsU z!uhJa>%jnerFb;{k`P(&lLW6!}|Eea7whk?rn_uor9c$ELJBnhZyVc^aH}$2nakW@< zcj(1Dcv4@A{InLo(!Vd&{k0Z<+_Ep7^sLRI$wO1-M>m7WcSLQj@J$eXW3SEicLq_? zyR}*Ldg#vFEG>wZ-mA^^h6YjnI(4{w`yhI^XB`$TAKEmZz2Aq{yitdDo$f;w3hMC8 zPy0~*#X2lHKlE$%&gnxvTi4~UMq{~=bvZY%58a+xmxTd<#?4Tu6owv<`;U= z->vHL)C0Z9eRw?(2=u)5E zf9pxhC)DR!2Yb@w1@&2Y1nBbIVMb3X`%``H6xEZyb8EnDdi114%^I+<3efJkyhl%Z zoY8>qUhF}e-)g|$eAa^o9c;kDF+ktvl<7U_mGTX_Lu3!C(Xk=l?bd@fj%&!mIDi4* zQEolx{VfgIa-lml`nDmj-QS&-J!r_nKY$b9FQ#^Y(U^ss0B^v7xnL)zH0C*@yV1qB8uPKvSngnB z7N!DB0(bknD|Pp7!pWz*(y;bTc-ii*6fvd=3vU5#fls8P-PDAC9nzJ;k2T?IZMxEs zJ55+v46qG+<*zQ(xJy$$d!h>!i)qS-wsoQN^O~}78sHyzRzerbJ=K)Q^zTAlA2;RZ zExM4UK{FPH1B?W3`<*B*u^CS|OjP-eW?Xe6(Wjp_W8pi%QE)^g(M^x${7+Y+sm+`7 zYd%C?!OdCN53m-z=A5EZD=}T5XxhH!yl{o0TbG)%a3SC^IA*va?bm`2wNq4cSPQOQ zNl|i63l?Ss%m(j1VI$AaTkzi>*r@LxEx7G`8_o27iG?Qt*TIW}Y;O_}sx8m9-I#F~rKNcniObcI`+lhk1{kU6fC)zvHkC*i9M0MZuW8r1My>Jst zC;IM|A4i|VUuvuB&#U%yq)7q(EG!M!7`~I%k*-en=PDr`F>d;^U#pJP@2EcuX9IqQ zgRgd=g_T=A9a=iK%*G`9^4y8~8-_jYej_daXG@jmUT;7S{={J0(E zlxoYu^?>K$(2v{ErI5CKWl=kNEu$@`C$*zCE84P)`Qet|j4`vM^1!#*AxCxaN#&Pv`@TzCh>`EW8u? z2&1nM`V6D*5c&|KFA@3_3k!ul#^`H=KF8>Lgg(gVi-bPO!bzczGWsf^&ocThp${|q zGNDhiFjVN{jJ{6j^NhYvxCa>b0^y!u;j3_uFzyw?J;S(n2=@@3;Jl7-8{J<7OO3HL1H-X+|_jC+}IPqQ#vxW^gyI^mvY-1~$vfH4*j z#sn6g3u6RhtRRdTjIo0-hA_qw!kEIsdSQ%Vj5UNYhcWgL#vsO6L>QA;I53P+jIoL^ zW--Pt!WhOF%Lro{3nPXxjxp8|#yrN@M;HScV)XX8_|_KzJsw@M?HQFrF2JX9nWx#)M}G<5@y@rm(PVc*ZcEHH2pl!gl8DzSw?uKu`qCW#xb6Cgl8V(*++N=GMhyfU}03jw|;qee7Fk%Hl%)p2p2r&dBmLS9wjMzfh zMMkVah&dRs2O$Pw#3F>4goWcnjKYXj2r&yIb|J(tj97*c)37jph;bOP4k6}Y#6E-= zh!G1BVj>p)4>1xWRwBeqjM#|~Los40LQKWN1|r5{#9D-yixGPfVlYN5Mu^E6v6=9e zj985jvoT^fLJY@<i19IQRwKmxjM$%$12A#{LQcTKQzA!T zj9i0|b1-rbLJq>nMF=?w3x|mug^{Zeau!DJLdanl zxeOtvVPQ0p<1lg^Le9g;eF!-aBNrm%L@fL!awJBsM97&Kxf3CWV&qbUoQj3*M2^MC zwJ581FeCROH3UX2flyOmVP#QcVAL8AR}W>>9tbrE zMlFI+lVIU!QKMkgDhM?TM(u)7!(h}h2sI5B#uhaWMy-QT^I+6I2sIE!Erd`LVc~C4 zBVp7^2sIN%?SxQ6VboFxH5C>%7c~|}t%Xo?Vbop-H5f)MhES7X;dW7@Vbp5y93IZ7 z-4JRxj9Lz%ro+PYqQ=9h^$==4jM@*O2E?cZ5o$s#yf11*j9L+)X2hr+5o$<`S`wkA z#KHoj#>A*K5o%71+7qD$#i&IQYEmqmFltncS{0#Y#i(5oYFLa~7NMra!Vsgz#i(@= zYF>=m7oi5msD%+~Vk~?yYGjOB8KGvzsGSjNXpCAKp{B;d9;3#_sI?JlZj9O+p$5mO z#Sv<9EL<{bbc|XZp=QUZ-4SYdj9MO{rpLl8qsGUm^$}`*jM^We2FR!d5^91hJTq#9 zj9MX~X2_@=5^9KyS|XvQ$ih0K#>l8O5^9c&+9RO`$*4sVYLYA*G-{NLS|y=o$*5ft zYM6{#CZVRu!bqdW$*6S_YMzYRC!q$)sD%=0qAdJ0YNU)>DWPV{sGSmOsEk@Fp{B~h zR-?wssI@B8Tp6`jg&HiQ7OPN`W#O(-qh-`;6>7GO+O0wjmr=`AsOhpW*{Ja{YP||I zUqZCH>1|AQ1fQgz7=ZVj9R!tO`L@f zM~$3OD_5wQGiv7wHFQQTU7@DV!j7ZH&ZxC3)Z7`hcZC`}qZY4FlV{<|QKM(n>J@7C zjM}|I4WCiVSE%W;Fz2Z8Giv<`HGf9!UqJ(4XaNeE01J-}jewyQC};)@?La|8U}y;n zngR=}4vm4KH7IBf4DCTdgJ5V83Yr89#}18xp;aho77Xn|LBn8Z848*P3*!!rgQ0aO zXdVphLqP*!Xdw!k2n+uXjfA0PPwJ2yV4DCfhgJEbf z3YrWHHxG@5q17m8HVo}XLBnBaISQH%3sVn`hoSW-Xg&<>M?nK(Xh8~^5DRY)jfkNY zDQHFv?MOjGVrWSUni30(4~>bTH7RIL4DCrlgJNh=3YruPrw@≈akpRt)V*LBnEb zSqhpK3&RhMi=lNXXkHBMOF;u;XkiMP7(*LV(8w5CnSy4<(9RSzG=`R@psBI2|IpYN zTAPCA#?amrG&qJ9r=ZEP_yVBOF|;}b&5ohnDQI{MEl)wyWAO|?<6~%j3Ys57`%};W z8Csx%CdlF^fJVsB3KcX%hIXi+Au_Z?1x=B~YXFUrp*1RKjtuQlL4!nGc}hW(Wbq+D zqhx563YsNDyHuSf#WJ)^1x=I1qX3PQp>--~o(%0%K?7xIp$eKPi+=$cDMKq&&`cTH zse*>e&{7pNRTggpG**Vzs-U?tv{wZUmZ8NeXtFH62WYf7&)+C$whZl7LBnNexeA&t zizfmaFGK59(0m!%uYv~5(1H~-VHUpxG-8HUte_b)v||MgnV}^sXv!>J3TVs>tyw{H zW@yg}8Z<+TR?wtbd=}8C8Ctc1X3fy96*O#ymaU*^vv@F|aWk}T132~f~L;m-GIi<(ApI=cZT+^pusb=cm++K#n%Cio}tw% zX!Z>4UO~fWX!#17K8xoA8b3qpSJ3d6|0&~D%4-^;#28*D;B(V5Mz$h?S1qEh-!7eB;3=Eb*foWjzn1FF$ zunr2$1A~1~U?3PQgaQ-6;y(c+!C)m6mcc_CkTd zV6YepOa_Z@1&juR)lgtI80>}u!@*!V6qpVcPYW0i2J4}~d@$G#1qOt{f+#Q{EPfX- zA`DhUff-@2BMJ-&o;M#WFeNNr7%(Ob)F6CcruH>28;}Yl~G`3P;cL^z|b&Q8U?0? z#d`zBhQZn>FgFbLMuEX$us8}#4vQ}bj1Ggw3-4j3N>>!ZN@ zFxVdj28h7|DKJ4SejYGF3|2^i8Dg+Q3Jej0B~oCDSiC-9j2Ntu0&~P*j}#ar28*P? zB(eB_z$h_TB?V@Q!7eEJLWqsd@36_`y1yQ#o%GFVOprjx}}2F8=YdMYrV4E9rj0cEhD z3QQ=A-wcc>gB4X^Mj7m=0z=ARNfnq<7B3nYQwD3Qz??GJQw0W^3$DO~v-kzUh;wwgaSF^hgB@33$QdlT z0#nZ7B?M#6V9gbna|U~^z@Rf&bOk1z#b*dcox!RrFzXC5?7IR3&tTydn0OX{A{coFE3d%JGuU|rhMvLFD=_se-bFC>4Ax$Oxo5EV3JgAj z#aCeRS$vIP^ck$a0<+Ix_Z1j^2FtI&^s{&#!T2*+e+A~B!Tu|F02p2X1y2Br9}*q` zhF3trGr;f;D0m1MUIGPA0gG1>9s`EgK*4js@E$055Exzr1y2Htj}jgQhAgY#Szt9& zDR>wdUIqnE1B=HJ9tVckLBaFD@IEMbAQ)Z<1y2Nv{}LVvhF3ztGr{mqD0nCsUJ3JMD0o;HUKRyU3yX&o9v6n!MZxpJ@V+Q`U>IH)1y2ma z8>8TnVR&T}JTnaMjDm-T;iXaV)UbF@;jv+OZIDmpGQ2km9vp@jN5PZB;!A}`hvC&x z@a!hL_9+PZ^7scU*^jhS$sn&l$seW`hTf;YG8- zlg8rng-4CyRkOjf#_+D$I*!U`c-d_5w6S=A;c;Vl-E8o@F}!a!c;FabI2$~1EdF44 zN$O!IQ}1V}?hO;Z?N3v&ir++TdYico}Vh zRy&Kw86HQ5*U<*gBg6Y>g9nn~g|xvF$>M*8N0Q-{wAHFuH1Mli~fe!2`OX; zGQ6iYcu*N$R2w|0EIw^`R2g1X8$7EF@2br+)6Vd++Tdwr@o>ZA%J90{7QSp}cwcSs zz%snBw!N>|S^VAb$TGaLHa*|Y@Xp$Hyl!WBX>IV-vUtBU-^6}&h_($_ZioICVXL;v z&hX;e;K^n2g~OxE@ao#&*=2ZlZSe3iyu3DedRaWSKcknBfJs z!4u5lCx=IvJ1is{Ji`p{ux<4o?04TzHh79zyynf>&hQ%B;5lY^k8SWEGrY()c#;|3 zWZTihc7|8k_S2VkhIiR^;fS5#Wwyc7%;Hgp$C=@Ew!!nv@IKp?erIQRp>6O)v-sEH zk!EI|=XAUx{~ z?|NY02X=;+J+Rc@cH}t`f&0mHc+5XVzCD6sq^JHrbf2v0nVKflvIxGrNF1ZuSK z&IiIn&+yU*Zb2*F{fbZQ46l6vJogOmeZWDq@ZtxQeQIa%^$$b~uYLeL`wZ`Xzz($V z@&|m6Ry_ak_%pozogbmaZwdQP;$s&tIr0@kNO@N&G?L(Gj1FcvZwNBAyN8>?Ga=@ec^YFC4wF?81`^ z(=A-Ju+7333*#%Ct+1}bn+o$O+@-LO!XF9)C>)-!aKfVr6DC}iuu;M%2_qz&j<7Pq zs|Yh9+=h#t5Pm}#65&{cr4gP-m?Ghtgsl?3OBgfZ+=R6g-cOiA;U0y(6#i2fRN-KS z#T6b{NnKcKvr-?G8l}_;rB)~PGO1Zf-AHOTQa_OzhSU)xmzR86a$3nNCAX9ON^%^@ zGbGlRcw1s#i903sllV(wAc;dH7Lez$JQL-)B+mvJpJj}caZ1JtxnJd;k$x+E$Nc>V z^bzOZd652q`FqjloPW0gebf2(8PJEFe}_T(iu}C=^LG_+?>PT{g84fM=IstpE5MlI{JR9^?+=*2Ga&sB`{}@#=lr_?7#p2`9{^)$;okv3 z-xR+;#$>0j-}v{9Pha}2`0??~aQg0zzux%hjbGmQ;*I~^_}q=3-T2mxKON6-rw?83 z1@W63UpZn2r+?h|#El=^_`Z$5+xWPRU)%VyjsM#Ctc{=A_@<3N+W4T2-`V(@jeptr zl#L(R_>PUg*!YNzU)cD95&Jv+zsBcl{Jh4uYy7#!him+{##d|nv&JWD{IJINYW%In z$7=kl#+PdRr^aV${G`ZvoxV}y4>dkesYuQWbNZ#;dd8P${CCD@XZ&==H)s5D z#s_EoZpPPU{ALZR_@0cv2^s*2kIDFzj4#RfkBraA_=${f$oPYd56Jj^jIYP|cZ^TR_;HNy z#`tTDkH+|Aj4#IcUyRSi_*sl^#rRW<55@RRjIYG_N1!n}eImvWVtgOQ-(h?l#;;*~ z8ODEMd=|z}VSE$DA7OkD#_wQ!4aUDoV0;J0UtoL$#xG!e0fzrKoWJ4u4YzOj ze8b@z-rjKahMzZ_yy4*u_ip%h!?7D)-EirKKR2AY;mHj*ZuoG+fg9f2aNUOAHk`KM zu?=@^_-eyZ8(!LQ(T0CEoU`GX4YzFgWWymF-q>)(h95SZu;GCX_Y1bo$@dzL*YLVv z>YQAz;cpFRYj|42%^E(|aIl7VHC(IVR}H6XcvQok8otzUq=pwYT&Uqc4d-ciPQz^) zKGSfRhPO0arQs(HCuw*{!#x_l(Qu50S2SFr;SUXGXm~=y4H`bsaDayQGhCnH_Y9|J zcs#@18NSYNbcUBRT%6(G4CiKeHp8tMKFx4whBq@@nc>F_CuVps!+jaP%WzzV*D_p| z;jav5Wq2yXO&LDQa8QPKGF+44mkg(5cqGFe8NSGHM1~hKT#(^^4CiBb9>eVzKF4r4 zhPN?Xjp1huCu4XR!@U^3#c(W!S20|Q;ZF=_Vt5k6jTk<}a3F^FFkFY>Hw>p?cnrf` z7{0=A6o!{DT!i5t4Ci2Y2E#2FKEZGZhBq)=f#C-XCt!F0qx&0u-{|;8uQ$59(cg{E zZuE4cn;U)H=-@{0HoCUauZ>P^^k}0y8-3a6$VM+Vy0FoIjm~TIT%+3>eb(r(MsGE` zs?kr4PHOZ}qk9^C)99E+uQa-((I1V@X!Jy*8ybDk=zvD=GrFG9?~G1o^f;rt8GX&@ zXhttHx|q?wjLv2BETdZ)eah%iMsG5@lF^ThPGs~Tqx%?r$LKgluQ9re(O-IDr7cEx0c0yR0kg?(XjHyR+l- zo*&n#Mtz#ygtEHJZjRn#L)b#v_`>9h$}$n#K{D z#tWLp1)BW-O@96+e}0qSzR5q|SCKoBZcZe)1-Nc$43|$-mv?$8PdhH~FQT z{Lf8(<|cn~li#?>KiuR8Zu0jw`E{H8w@rT9CVy;`-?hoV+T=%V@|QOGMVtJeO@7WM ze`b^4vdKT$Hu(vg{DDn=zb5})lOM0iU)SW9Yx2J}`PrKMX-$5! zCjVHIAFRpW)#TS|@?SOisha#zO@5~)|5B45smWi|_c1h1YV2BMcGhlm_`O(!fJur!Yw{G#ZEyo(p?~NrF~k zAV|0;Y!ZeDr40sbg;T;jp`{R9Z{U`&M(8di)JYzNjY4lBxmM1F^+FFJrpCY>VY$#+ z@Tr!16Q&83RZ^G2FG5ctywbpBVTMp%Vc@OsKcThYT5jNg&`$_2GjLWIBczrZ_(zx~ zNFmOcZE;#2)xdm;Ww3#qZ$jTL2VW99i z$H32mGTXo-VWJS8Wniz+TzH;oV2Ti)A$>{Eq)Q(WMhG5h27VL@QVpCIItZ^*3``Kb zlO;~bNiy)epih+g75WIq2?iz$p7GLmgt#~ZTZDpG1HTCkF;WjgOW{Veflk81DCxJt z^GE{&gf|fe1`F@QrA>wRVRA0K36*%^MTp1?4}%SK7H$Md{}avy8c+mC{RoBr2DS?E ze$tMDm#=}Tf~k+Rhj7Q+Kr=yR#gOZ1V4dLWA$b?xewKU*f4Lhdc9ZrLyj%^879P1s zd7Y&Wg(xR!cj2|8*cT2sNSM9Y5uVyfecDPt5xi}r9Kw}P2J);8ED+vXiGAT0O9So} z(hr3{%_Y5=*b)9VmHUB-f$73sV=2!^19OE(M$*SW7(jURUh?QvbCSgz|wQhyJ{j&S9Hfsp%B z55l^8a(&#DetSn`g>APDyt^gs|F75(cHERYyCHq=y2J}V|0DORYm$enl3rN)x9Gbf z{qeH2|0M(Cgxwbnyu2VX=MA(G=AM(bI4k|g-SHZ^z{N`a}BFQ3G9txxY)B95L|VH>uCVaxEPa9m3RuQtktCKie;5-zR;2uYsC9 za_tH;cT3zZ={Gy24S$t3-XV3kUG6p80$$jd72F|RLd(m1c!;g}OHF6(cE%{g__xhCv+6n!Ckg~6kaxItp?=mUJ zQUiyV$n~&T+G3H^@j?S178v+6U+&r88wmJL`U6rQ^Q4c?m3E(Fpmw$a)whzzS#qBj z+Rc<}V20cerW@!rO|HSI(!ZyOt;y0BlcXFI<#&RdkC*Uq5X7dfJxi$tl+3Ql#fjp`Kj@qBCDlr#wBmIeMJ3^<2-= zvpG}G*bK3grY9m*&#M$Yhm!ToP7)o7dJ^OHe2CL?Bv#VL=xG(LCn{3Uvj{!EhU*y} zrl&SUk87}=i$Qu81?p)ZAToY>9{TFp;G?Inx1MxQJ+D3VvQ~tiLGF68T;<$F&lYEi zchZyWpy!djo;7xQI@sz7`lRQQwdBJ}PrZd6OLHlMnVx>8dSZU>KXh(f02x9gd> zO;5m9JwI=eHvL)8XJf0&+8L-q2lmDKIm(iaEn=`}#ly?&CHzLMYG zdig$1&mTSY6nB?)?j~jIqGwrWsk4rvtAo^6J3U{umArf@vaR$S{6bG!3q8x5OaC$G z7^&CsSgWIjM#mAAPQJU-u~?zQrd~(iIvrPPbd*==_+O=t&*eIXmg%@rqNA!v!U}b` z34r{hA7j@&FA3o~`H#+#1TX*%|#=m<>GF+5T9#Ouh3)iEzd$BQT(iU=KR!*y7O zifo9E?Lj(R19Wut*RkJMhqt$mUS2v5dFb$Q*U{5W!d-NDIO*u(sN+|A9rm_5zOa#e zSnDvd)KO=y<9jn5cTIGpf7CI`NXPN_qU)`W_HT6j^h(E@7dncc>6rLbC;Ob}kU@T0 zKh&|}zK;8MbtK%@(dU+qtv7YNy)I?CreoMu9lNhcxi0A_xFF}}#r|1|Kcge_l#YHU zb!<4U99MXqjaB+A$xUf+^yrzP96R`bSSs!825{mdy9^T zKkEqCsH1Vcw8u|6Hm#F7{!!|7wT_~dQuZHo%wI0;vsCJCv5ugHI%?-jy?-xlg@n)5 z@pQJ7bC$@@(9vnSj;T|1{5)C5g^4;ojF&WHB_E@8bQq;${0JSZhwJ!#sE&Jsb$lA6 zBXWSWb3YyJ`sx_bTgQT4I=1zYGIW#v(M4oB=?Ly1ZP-qSs*SY4mm=3n+OwsObH3;~%vgU#;b*m0G5*(9&(0mg>b?A{J^fn=f_sotEwMw9KBPm9-wV zRL+ocPm^*@(Q&9KJz7iDNNJmIw455IWyKIJ1HTqs1GM<`)AFE?mS4Zp zGP$Rg=H0bKchT~yla!-_l)asnmTe?`D=p7kYT4CX%Xou^My&=fwT6F`8dfPZ^sLvA zTBG4@m4@9F8b+0AC@>LZP;m#87*u7(@8C13x_@pUQ3H4PL0 z7MV*LE?&?u;+&*Cqv6;o4ZTlj@HnQC{}~Nm91&ZGG%P!yp=__@Z?}fAJ2ixFm%RO= zq3srl-=tyD2912LuHpPzDa#tk`%0;&6&i|{YPhsmL*IoO?7kO0Xvm(U;l#I+_nA_E z)1+>uXb7IDVe@zm6=O797^R`>2o3LsN#2KO@EN3G^#Bc-eZ^*P4a%NUuI?JTbk*>( zlZJ0PXs~Ik;oC1Y_V_8XH$N z-#Dvz>7b^Iotmqk)F>_095h$UJBOOpAJzE0SIe5UYTmt4)Afa#3s2QlK322&p_<@( zYNp;%^Y&jg?Qe+fYihEus9APNjoo=Qeb1`7d|FM(3DNbZ8pop&c0|qjLuzvOt68*H zjp;5m?S55rXq%ddEo#R7tmgIxwX8ELd0i{sY8JLobI+h6O{?M?wTj;xRk+rxXi=+Td6kL>*+dnZI2ChaRGg1g;Tfiqb!6o{P{m(<67Q{|(L?0jMYoFz z3r7`&b}GKMQSq~tiihSZ!cA1NrjUx+?^XQqMuq816`9Xebo)=ml1D1e+*e_JM@9C( z5_Utyf@>=NyrRPBqKf!)Dq8-fV$vxU+m5Ta^@j?VBPw|pQqlQ6)b>)*zK4ooT~*BKBsSWsIM7DLrB*7Q zv`~p(ONqBuNxVu)kwS^OPDzIvB?Bszj4x9{v658?x z_D)In*GhW45T45MV+nhpr0ZQJoo*?mZ!2kYP01Hmlo&2Z{?00?Kdq$Vgp$HzO0s@e zl6Y82{=tfR~or>v61!X8f86# zMv6{I9*&8f-z9H{8)+S*9Urbb?_Z{(MCl4eaK**`S$cA4m1 z+{nNMjbzZsi#d&KoYhE=>5W8B78?^9Su(bf=A$HU!yEZ?NF!qhHIm;?WP6M5o{hBW z)`&-^M*e8u$Tw{oN&TXc+szyKPOqRwt>8nWf_3!@TGlAAuTb!7se&#=3Ow@^9L!eG zJ41ngih?7F3i`&$ag>6?;RIQ~jO&*usppD6h0p@RCm3Le~2F!6?hh^q?rUsllSf`YeyDVTjqLBgM6 z_ozbl-;=Nd3TEzA5Vcdm?(GURTNK>iq+s}Z1+HrqtX!=idxe5OmMZvSk%GtHEBI!f z0;g{kESjN^Ygr*{pDL&xtKi%y1?|33@MMUB!Gjc7^iwdsx0I)cLe|?=5ZzJ1#&!y_ zT1)v_Dkw8Fa8%oXLfIhi;tl9(8n{^5K+CcQ{w`{ub$$cavgJ2Jep4FwBC&xhu?;kf zYT#U01L~j#PWU%aV|)_iIp*rEYU8*nmeVC=gF`7dgq*YgH$ zK50Pzpn>1-Hjwvk13z7FAn@-7reA81XFZWQ)4XsgL>_G5+kFif?`ojy zjt0(d62CA1duzq0!pTBEh$lM10nbknqv<6m9ZoqbY13kt_ zen&KrG_--4UpMfye*=xZB~8x;9J)5pty2R>+BFc~x`7cbrL2Z}GBx$gRMvC9zMj(R zdKOgF^Sq>9))A{`X>L8QGwZ2Ot!G(MJ+I>Gsg9~=VR$`Hg6k>vuVq&c5&+z;8{C2w@ryKR?uhz5Zay_@s z*AsiDp57PjB8d=ZTVf8qCT~As6dWQ6=XJgNL?sTokuVX#R zw)Ko@UC*`_l1F`=%qOj*K~cvyb#<(-s^eN&9ganH%{L;$J6*a{G;or z3a_J2NF56TB;2Qt#~yWfxYkkNSVsrDIwo7!vC+JabH;VNdtXPu>pDuFOWc2TjDJ|i zn!9xz{kM+$|I}f7rH<$eqVumhI-aUy%%62E{k@J|hw8YvuZ|bH>TudFGFwE)#yVR3 zR7c+*#m34ymMyDe`=UCIe_zMHbL)6Js}6^0bp%bSBXwLI6{G6V53i%kkUG8|SjWV^ zb$r*Wj@8}j*xIR%gYD`#)w+(qThwt+U&~8%EhdUuY-?+AtE|PZw3hI~THT5V(UBj>CH7qW!VN`w%?XzpB zNUI?#sfJH+HQbG=;Ye5wtAc7|o@)*5ylN^t%ebs zYf!AOAz*C{4_DQ&V|fkZ7uU!dLp21>t>ONx8n#TU;hRaKb8HPRBWt)gtcImu*U-6t z4T)dX@Upw4>nt+uYbb49gLR7$D!H8V@9Y0R${A7nMh)2o@B zTupUcHI`A;>#l0rZLh{m(N(hF zT@^nERZ-_##lN0a40Wr*&9RC#wpA2bR&my}N}k!OFnUwP%okOJJ*i^rgDR?SS8?e^ z6mCTW^ zV#)j}BIj1|)2u4erdF|IqSzc$#laDxe@GR746LG|PZcM7R-x)r#hDIOXuhoCua;G) z^_84fSJK!}$?=*>YRfD6t+zjL;$tdV8Bs}Ka3%BnD{=IyWUPB7 z@0}{?ZCA-{t4f-ii4LPmO5RAC7nMXjse}iW*xat<>l>Ba`@5267e)VHm1LZ#WceSJ zI3KQL*#1iH?y5wyt&-iFD~VcP$*i@adu1iiag4;nA!Kbkm)Q_lO=Fkex4y?edPlfD%R3U4TR&cd_ z1%a(AXx*ZM#kz8?D$DV&E2l+OIh2-jwxArB>~iYU%9)T<&Vkr+j3Ua(2rj3Wf4Qux zRn9fHay%SG#-^OnmgQ_WDd+L~azb8}qkCG;#7E`)dbgZMH_HjUT2AA|az>mjXTwQJ z`$svBhs(*^S5B8*<;>kCHhz}$Kb7ONrkt`B<@8)4d6{3%zPaVxn<@F3Qcl+Ra$1ir zXYBBDe*C(e6aC70(W@M1BMERK}LrGEPO5@hG?qYrisrJRrr(Qcm6HCbl(@U4gx)O0=V~d=7fZ4HtCV*qN_l*=lpBXiIlH%%-+nD+`_@u^+*r!| zb)`&MRmzZMVrO9~%_x=kwoU%CfGdOzu!hzb_>( zElMfXmJr=of>Uh?FDpv8R9wRDyb_jWmM}J@gwF9L)I^pL7gBQgmsQ3 zOtvYZi$w{QA4>>(TY~9}68?Tt!nXS*e0!^e9{)((r4oY9mhk3e2`B$3VfEn>zS&oT z_SX_(x0YbCv4pehN?5b1grUnyP%J1RWL^o+XO(bhY6){Dl+bZ>3F*U1uozUrnZ6|~ z=~+V0E+yo)E5W)|38$Ntut-x(XGO8BK~~KBvSJPv7Be-c7)@F+zKO-$h$&`ucriVK zM8>C>*Pn~|)w!7AcEuD~7GrKAY2Ftz_Ejr($-sEvDxe#RTY!IIb#USbY((l|@`EDPnwnkvwx1iGQJpDe*;Q zMiy~Bq=?D>MKWGjB|I1bH<9aDME5pDn6)Tkp01F%#zOYi7NRLH(e^E%;<3di{E5vZKkn2|q z>3Xq{XJLklSPFW^_N0uo&dSng1Or*#37%nJDMp@5#R3;5@00gVp|*mt{tq<;!ne7OL} zvjq%2S-`!c1?UbIaA1$5-(JA?n+ve~seoQ<3S{4b0*V(Fh)=5k*I5O8Jymp#FQ8&% z0qceq;4+|q0lf>j)UAMm4h1azvH-sp`4s<_&+Pr8duP7vHJ{Jqjrsh&HlKta@)^D)pFh9P$A5M{-KOWWePX`s*^`fE zSUyVzN%}tdWOmPIRHuB7waLe$MLw-{d8}&8<4H{(nPqu0e<)9U7kSvG=AnqsV|G*? z7eeyz^UI^PXC6yk^0;Z2N4RC4_{j2D`7V#!FXa4j9_{btvFv6Z*Zvmy^LaEooyVMG zd7M0)huz*h%6H`P&6Yg2tnmnSH=kevDJm!(d@mYCTOvxjATpm3~ik=~Poa>*5 zO|Lxix=2|2JQlYSU4~ptRk}^u8c+HvMV>22kE(ZCFW8Voy%8Yx$+*E%Wqz} zJax^**IvS{a_M23%iQ-O|1y_37yFsH#7xeWXZu{*kH}@@V6oXRSKeiEIo&yzhi!AQ zYMD!*E{Dv<927M|Z)XnAx8`89AqT4; zb8uXdgXf|g0>~kJRt|AfMDIAs%ZMEE2Io-JFNd<8IaGGep{8vPbuDvf&}E}&6l#Pr zp&(nve6p!a$)+YQo63l6%7U^f^2sLGJ)2C&Y?41^6Kj@D_=jx#UuEO*Up9{Sv$6a) zn-5pBd3GV2yQj1H`&c%o4rga1tveFd zadXJzx^*W1GtFf1dkK4yiSy%3F5k`MhZ~vnx{^ue*-T7MWOC&9Or{^mM7J{&zpa_v z*pSJpA2aE`B9o+rnY@^n$uBcS&*V(<#$;kNJd@pnG8x_{Q~oP5`Pds2c zo}R(Ei5ZL<0!q_4n4eD9%ygWR z(%Br7jv+Li5B}*a_DrYPIh~uf>5R2VC&DP5!>`ln_%t2M`{}IsH=WYI)A{FoI>Sz- z<8w5ftq0Rl?Mmm-FX>F!m`=!#>HNAP9nC@so0ra*nd$gVO6TV>=~NF(=i0z@`t?r7 zrfWJ2+ozNKh2%${hORMi! zhP`-G(N1Cv}@9^ zT$aYf1)^h48q=qz;W8nOS)G#ucYx zmXpe`v{c^2r_whvm4`v8bo5E(s#_{L`&5owrBZI3%Fef`q&!Py)x%W$ZlyBwS}K+o zQWT2Z1FKTFR-8gbP741^OTjHZg|8!1xEho~sdoyi+)}W! zPobw(3a5-yNPUySoM$P#dXR$d-xRi9O~K=Q3jI%|aOP+V$p=!Hwkw4PTji~GeG1Fh zq{x1&DKuMU#clIQcv@MyhHzl)gZ8D!$B%@fE%-ng&T%M6EW5>zzjGfGnLz8*j zKbhp7$@J@-%+@x^ylI|HwmONy^-1igNaAf_5?NVE3`|LqceW&+hb58ZpG0@hBvv~o z@vlu1fo4fG`;f%9FO%e2O~Ud{68Zlm(f?8s|2vb!&0|UU97+-&ND^bWC9!>DlFVI5 zB6xWcngvOWpDSV0lXx&83BQp^)D2EzSidCJ^+@7!$0Tf9OCAh~bWkNSt2U9{Wr^I+ zPsAf5QGAn$bc;@8PKbp2CUVC;5hsU4GOZG6Ws)d+QYEtXSt6$%B=YLtM122Fr0`rK zZBI(v?}@D5pUBZ)6M48f5r_XJ62CH$`o)R#_%4wtvl97naw12@ByxLLB4z^;3G9_f zZs$aFZ4&9-B9Y0O1b(PbkU0$roG(n^Nmc^Z$q59+B#<7OK&@W_Z9Ebf;FQ4RPYEnG zP2lHu2^@Z&z=ekiGRBf1|6>U_oR>5w6G-?yf&Bdm)cu-3i!BLs`AO2QN?`Po1ZI4f zz=Bx`G8T})rZEZZ942}OBygga=<1xn^)?CIZJxk?>Udt)#bZ<+k9k2npEBcdNQ%cL zI-buV@iGrNUgk~3%l_8!vbTFYfyVI!y%C-Y_vQSi#9fKU?`*v6sUDBVZ}GV8jTfJE zJhq$Sv0NLE$%=U1EsW>++;|>NkC*YTczI`t=dZ!>{Lwd_ecj{vr9(XHTE&Y$Adb0> zaZIX?V^~QXU**QpHZ4xZspBXQk0T=>jtI{(#PYd9TG=U zKauMZ$Lo%9Txu;k4Y4d%#xkNNmNuoal;p+|k`{|;d@TP&#Ih$amW5ui40ee{Zxc(Z zSu9TPV|nl*mcx%?S#n$AuEnB0A4}ZHSS){!<;wn8Hvbwcd-{sb|HYE|LoD`-V!1vq zmMt@4nK&_)mZM@x94vPF#&V{6EI)LJrGKkf`R*Zx&x#msRmJdgag40d5rZNn2EW)C z?uEs$#Xp9T9x>E8#>hKJ4A)I!So=0cp4(!`zaN9;%@`Sfk74%N7@8lCA^30%xA%z5 zwiv$J7(?2c7~U+4;n(>w44)lC(UcfW$HuUKcnqTl#!%WT2J_Bx-X?|-&0{D~Mf0IH zn(bxL49JfrB|Vx)3DK;MjHX>sH2z-EoOg+4hHW%eX3?0uk7nD8XnH-0Cj3@3m#;=M z^L(_7QAf)dPc-ZIMbmaiG@my`b7XBagI7coyC9k?bE26#Et>ps(LDSnn)!pGsrf3J zH(jFnp=~s(=Fu3dqgY!Pg{~|L)BGsbWyoSG8jiS;lN_=2Z z%zhC?_QNQy-il)M)hHs*MRD{*l+3e=!g+5Lo3_ggj*U^g_%Vt(%cDr2AH`p@qv$&| z3fHkwY#1Iz{eUR$_ljbC=O{wIjAD1QD4MAvc~KK7-%LajnH$O8v`Cu8NAfg0k_iEk z1bRfW)hUuX>qu#%NSR+0iQUsk7T=E~~ejmZY7ZC(Kj9~e#2*Ur4VAZ(@qK-$f`nL$8 z_sH+I2qHH`uyRcVVM`-e_I(6_vm#h9IRdZI5zHPMfm6Q-CiRHGqC*73TSf3%7tU9T zaPC%y^JP&u=d;3TNDAj*bT~P|;jH%wC(Jb*?84=FB%Bc+!g=;0oDPpf_Exxzg@m*H zT)6Dl5zcqNg=4cPoPpcIWe!d_n$_X#TN+Nncj3&R6^_-UaQci6=kFomRQ3&LWA|`; z+lMpei*O!l!_d@+v9lsfzD)^ZVrH1k4-7*a8ODyFFao{880`|qZJRKvO~Y9CE)2(K zVSM!FuMH|#*vj_gf9wXPRT3_J$I;EtDP`L)oz=RMwseMfF`M zi)Mv#Z&D~}qe2-zB$Ok4LviUAO7r%iENdAmb1XyT-8F3|SCJVI#Z6e8b$gmBe3grL_UwEZuH<#$84`A-O;7v%g@h>S;u@Xx*w0=9?HVp9nG z7{b|QA-H@WLj9}|CQJ@t|L71t3<)8lZwS4*hp@W6q-hy~mnIlRT`=RygV~uM%(L`h zBIAQ;84=8kfM5=K1k3j-!Ngbv^M!FR(_aU(_en5M?*tQkEg0qbU`Cz{X2X$SuI>%S zep@g(8-nSyCYW!RitKm6JeV1b$HZWYM+Vbva4>WF1hczqFn8JpjS2Abzw6;@F2E9=`~}`C$;r{|2GF5=8H_LCpL! zhz*B=II$~;M_Yoh`(F@IKLk;>Fo-sDgBUt32*w4mX?PHS4hZ6Q&mc@X2I1XG^ymVq zZU__~LLdVR1DTc?$cn^3*;^oxYSE{Li0jcl|m2k3R=5__Ot- zKdX-T!(M+TZ1ZQ(27fxQ_D8?ipYnPBq)zuIc)UN3-}v)xpg*^JN!m{S@(%CMYP}z` z6n+e?^rJ(e9}O9PWF+_z5aEYqfFBP%{5a$2$95|}7Jc+%^eaC)KlY>UmLG|K`{8!h zkC%V?ap922?DFILEq)C7pC2uM@FRDDAHK8wcsE7j$M~^zs2{WY`O&+(ANB40h;AV^ z)V};v>nn41e3_H$ORrR4s$zU)UX!ov2jt5sS6^1!`tpsLFS@tB#69)J^qw#0uKTj~ zqJ*FFMSaAVh`qkN+2+e18+=)?+E>P9d?}dci_>&pu8sHQr*C{2Hqe*4p1$~W^yN+~ zUpDJ}7}?-MeYp?b`9A!c?!)?cAHELvkv*|}uy^<2ti2BlEqv(k!H4+gKD>C~Bi~R- zy30OPoc6))s1GOi`!IWl4~C6C_^$Ec>QWz;eCI>knLdO~@Zr`7AAT4lI==EDypz~z z?ZYy?H*FN&1XOr)rNA39ywS#c;~ehIF@JByfA*%>-kbLp-fa2cP0ttJL_F~3>P>Iv zUiOx`ZQfWM^=8L@Z@$_gaT~q4w8oq1OTA^Z!<$z#yje5Bo0cQIaUAH)-d^7H?&M8y zD{oHgycpHsMRK_p|KxiyE!~T}I4|ypc`?t=i&8f)p4fRY-`tCecV0YwCdc=^D8KH- z-Di$3GL@EGRBj{aVJ(ZdUq_FgP+ z=|!2^liRhPvNxtDQ8}I*N%5ppj3-vXo-%*UlTv3-u7C368xv3bUVF0bi6@%do;tPkCnZL^aD(?)jdK80Cq_*Pg8H?MYE*PtJbn zNf(0$MhXx4_R~ZD`#ji^;X!4*2N%OVN6j!KQp@cGuBz3nUeGwr^wHI8~B;e9-qPSGd`A|nQ!zNzZaib`0z9SH|6)T zoS**8_eVeDz3(&gwtvQb!)Io${*1%o&rF>68Ov#(88PlN?}vS+fB(-s>He9{?LTw9 z#b=tS-8og`PIa+6d$ZliNOEUglsh4T?#%Oa$KKJM5mxTJFmk8!OLs0mbf^BNJ9{p> zlYH8pWk=m{+vm>c?e09^;7;4sqHnP~g>&8c-!yl8$GS6Nm^&}~xznb*JAbxwC#$(T z%T;bTRJ$>-*p2I1Zqy{Yu_@9Gp8z*TdAM=U!Hq@>H@1Fo!|%C-J#gdB4L52py0QM0 z8*WG37_irki@&&$`;!|BSGr-m(2dq}+}JzCjiAwPj2Pm^wLWg-cX4Au8#mq=T+u6B z*<9(0bAc<}Gh8_m?@DNxE5rRFw(+JUa5_jF}^M_0~&;YyUog+X;L{8s9M zM~({}Qe5~s+6B`f7aBZWnD6Am9V-`7ja>NVr3*(Ny5N4(h1Qo{Sbf@sXTQ6Uv)6^u z+g$i#y$h}@U1+w*g(Y)bxIM*%xX~{39^%5*J}$iL;zGffE{rlbb4cOLrwV6k@|~HS z?#!QY&NzlT)8OOGG*>ydamK;KncCOROnl-jbIhEv_}iJ{znmF<%$XeroO!v!nWT-* zbX()h4@;c6HqRNaY0fCeIx}gQGyD5F^R}DFv~{Lab7vMRoj6nFB;O)9k)Pp2p9CjX zhC6Z5&j|-NCkkyP%*=`9Z=E>%pA%MhoXEK9M8|VZ%>C1eLkFE?zLFCmo1AD|buNH%E52b>wn0N8U6#;9luKQh@`t=?-*^cVJ|g1M__y*y8HIaT^Ej zm^fha+5xY}4kX@kpyG-HU;O1j-#;9fxZi=r+Z|+oX9td~a^T7$2mYJmfcX>$JVrYZ zHQ0fi-VW4tmNZ{F&_i#}@CJLPmfN#1&z^Ou_UwqU=SZ+U=e+E>>15A;R`z@_vggwa zd)yw_6L7z=X z%NVyk(_7l}t=f)xHFkVoY{$YZI~FI}u{6St<^Fc8aJS;lNlmdOI@*?iAY0r#ZTaMA%Lhwa{`+9d&F8k9yKl?y*KPUrf-UP#*s}1jt@sgb z`DU{%J=faGd=gvgu_bT1EivP4@fv1}Wj|YY`C%9 zhC|=muzIEqlO~AFH#Ri%w;{2+4NmQBc+%X46Ut9ANAeR>3qQ&I=aY=pd?G6J6P7-o zxbE_a-Jd@3z40gdzxqVu!%xKCl(0) zKWxpxZq`g~YmLreMS#MJ+Z9&)FW-uOX;$RKSYZ-u#bGZiCOcWtXlaG}2P-Z-w_?G4 zD_UQ-BILXk{~otuRTjK2 zv|w$91MG4;5Nj99epfl)5U^Mtu6RTXD;7QnDeI8oP{~&lq8vRJJOtq z0p`THn{&d>oZe>UxVHmv4?*B7q(+YDMzc=U6 zOmpd%=0pxR=RkjRT6Z_+U0ZYJG&3hjVaCx4Gur2yVU%hn-@KTS5M;(-PcvFMn(@-Y zj4AKU2z_eC_Pb^@Ts7n7Su+M5Gs9uO8B4dDk+$B9-&UH@e4!Z+zcpj{Br}{xNZdd( zQhJ!NzrC6Gq0G3UG^KZyDaHk+@?2>uzByCYgqV`yWy%33Qxuk_T>fB6$LFRzy=ThM ze@wADXUdE}P4PZp%Ca4%#BMO<=T)ZUE;METY*VTynR0TZDY}8CT@^CXD#ggpUVI z7`nrRcNVZXx-CJyDvA7O-xpAmiCjQGpOh;(Bk=DafE zQ2nL_ub#BP@J`%C*@AHY7Ib>FFrHNlmM?EXrDY2qo3>!OehUILTi62WSGy1PKW74^1xSecfF%p|Gu(KKJP0jGCXvVg@X1q*k#`KtG zYz%6~RxfsbZ8KC?He>zbX4F$N?in;gLAx3DD$OWVXhxqzGsH$V!~9nh)3j;Ap_fhg z_@D`zH=5wy+k_fH6Rsa>!r0wSFmGu>bX61Mn>FD@S`(Dxny@0IiOmZ&;n=z+e6VkV zicJ$7&6<#9)P#;%O?a=`gsDoboMaPHM4PaGxDf-N8zDQ`hy{-t5qh%`O&1z*F=42ai_+|s{Uub|(R|C|KG{9<41N=5OprE<| z?S&0Yo1_6>;~F3z+JJdJ4Os2kfM|yXRM|A(h*<+}8#UnDtOm%cH9$|P0m~&>+oBD~ z9+#=>ddOa=$Lv$}SbVr19=q!i*HVwNs(SXWT958DRxY+4--7Eg z&buCJ>*`@_UytS1_3%PHVh!t2s9lfED)l&`P|wDv9*;!o@%d*RMt-V;{L4CMKB$B7 z^*Y#|ufy8TI`|)~Lwsu;`{t-aO+_7c=GEb7N*#Kl>u@8m4o^4KG2MhZ{8~{5F{?Vr zaCMkGw+>obb(lM~4%~z~Sc%ucPPh(he$=wL+gkVy)FQ0E7I9Z zP#aQ%3hx>euB$<|eGO8qYY>MTgc;VrPrC-5Dm7T6Py;)O8d!c^`aV6 z?pL#z!_^QwSB+mMs_|ieHJy}kx z$--)wnp9)voN6deXKhTX##d=pe^fOt|EWU9P!+bnu0qMjf^T0H9J;DNN2=KK zp$gKQt1w(ug@J-9Hs4=`gRxbp3$8-y#wu)bse;|gD$HA4g~?Qf5e8LwrNzokt-`(u zRVWv)LbPxdTz*sn?<=7)PzjO#O1!vSiF0QwvEz6pvfC@+yR8z|b(QQpw-TeXD)B0z z56t_yaIaY#aTL~reN_;b_#I;$K*rQsBEX7KAj;{obtc2pP3ViukfxZ_N z46aatgliRWJXZmolNAs>P=Nz1QiqZ|bj%duLz z9MeXXWAJww+P{<`YOoCSs0^Yv%h1n{=Q0d0E5pf!Wk@tB0|RhFXnGk=O)Nu_G&>$uhQGf{aq>$k;s;A%@~D*g zeJKw0mLgP83f)7cc-vZv?M=dsOW2%B3AQDbz$vl>WBf~S+`WWhu1hd+X$krklpuC~31-eNLBCoFGL=eTC|QDm zktHbpRSf!6j5jZeQF*@@7T1dLv8Na{CyHUYzZjpkv;F#FHeXbX_gSn=Vlm9Zi!tb1 zj3T#U%y%rt6PsdWniXTVQ88|67b8}s7}FGr(LJshn?@8v^1mX+nJmKUfg%jwEkeWP zBAA~o!t-NA$Y?8q=GG!ys40S9Q4z*v6fx{|5tf7$;oZg}RmAY`MG%`? zge{t^{*)qyZ!ALGm?9|rE5w1Xg;@Tk5N{qABK=k&ru7x#_^CoT94^F%U4_VOW_gu` zIGR_86)A-nj4DJ@Kp_-73$fR!5DS+T;+{nzf{hCys#}O!^+M<>7vijBA)G`D*_>hl z_@4?O^Rj^XMgitsD`0b61z2;U0Ppq{AYpp}B%$Uy*nR++DlG7sX5^N`8qVdUIABx&a1_vAc8$>!n9=sX1c&BfqQE<9f6;=!X_ zINr>~<=$La334Ggn2Y(XxoB(5#fr( zx5^xB$j`y`lpL5x=b$Yh2a`Q>kmHoYw71wfiyT~?p99|P9PCibfvi#v636G@wMY&e zerBWdLpEkS&qi^7Hhx{shUeLAwsxA0xoz2O9y1#wYO>*5n2oDx*)WRDMqLog^U8+L znrvKJo((2oF`UuNRU{Y+?H%S3WdChm1)LVsT-a<*mSS#2hai!)J_k%^aa znczY)QMxe`gKINEc5Hu9CSI9lf~UvIOwYu?#7xYSW_86f@o+eUVYM?@ocRpgxSs*_ zYZ+_}EdxCr8Ia$X0q<=YI9!_nvEmFkW@KPXTn4@bXTWS@1`5_@;K7OvHiw^qNYf0Q zo|6H|=^0o%F$3GAGVob61H9pMWPVD=wHN8^`#&9CSJSb#I~_lcr!)PKbf#^Uj;l54 zP%KJ^TY5US#irwZP&y2}(h<8R9fIZQ5VcH)jY&ERb<=S}ot0Hi$6CpBG>%Niv!7|u z_?QNt=V@r|Ph;QvY0x>FhM;3Vb&ou0IO2eC_ zY0$JtgV+2twCJSav1%G7DW<_mA`N9D(s1QRD#YKXV$riyB;85H@r$YW+LemgM^fRv zI~7gMspzjrg>+sjY?4!v9GQw^eyRAhJ{2=orDC0JDoV{#(QBBBe=}2IFfA3n6H-w> zHWkRF#UrRhUrVe_1+YS3Q{odUCJAo8`KW!#$L*_pNOkaG zvz3q3LOxE!@bT4?5A9`qc+BUcN|ldGaiuX4!a0f14^M=L zYa-()CE~PxB0fz@#FSBqSn@dmG4~U&wL1aV+7j@)Iswzu60jnWzJ#^LRlIEZ|W#l%Ok&_5rG#rtF7S{IA3 zj96p^$D(dcEZP>v;`HoT+*FLkixIK-{w@Zi?!-X8D+U_7Vqj1ng9ZE;hPR7>i+v1x zuEsEJi5MhG$FT32Xq3E&M%|TYY&jN<-J7FvAU_(%qoQ%jJsLf>(daXb#+9kjY%U=h zw}+x|_hA(7or}VQeJs_ol+IF66z)4mq2D43cXXm~Qy~i1grjijZ6wa$io_W~Bu?&( zWb6EqXitd54(~`b*|GRVrjaPnh(wxXBw~I>AaEc89+x7p>PQ5vnjlk@P2uyX0 zfRuFvgyu%z{Y5{tmaPvJOzFC5#?hNEn6IFhQu;g=GQRsP{HTNRF(X5o;X8IEDu za18tjL*J_~?7J4mo_}FT*c!$-dSO@;6NZ_dVUSoFhEGOexIQfm2gZh>>}x2(ABDo< zd?@Db4~2AHC_bi#;!;p3b~=Y5-69n3I-%exghF086rbLNp!a47S~^1zyCVcEOG2O- zAA)~gA-J_X1g*v)NK|9_5+RuWBN#uQ1f%alFw@`(MqooQC@UD_Lxb^fZ7_CQ1|wEC z7>kvHF+n64Pu~S$&+Q<@oC<jz=W4z$7OVPVP}~=p-+Z9)*av6M`(XWkAN;9haZ=KK zU=ZYkD^5P}UEl+eSw5(n-~+>d-ncaA4X^9o_}$@+lC9p*Ec8Zav^VTMyz$D`n|-r; zWBgQahCT9z{+Eq7dw(Mwx;Ns*-i?T;+K7=U8&T@Fk11=kHz%n(q9mkHpd!p~LCv18>ac;jS7S?$(Zlfo|uz2FAlPBgb z@WdW%Pt2I$iKf3EP#W|=@ih;O?(hJAiwC~vd%!=+15ej`u>ZRrj7#SMn(V>wzaCKg zKUJtTZk8QKoLqdK%!vDG9-k=-IuDfAtha1Lhbwfab8?HsU!NA=O z6*g}8Z>}4hC%fUem>ZNoxgxgT75%4OF@Lu!D#~3kl;{dOA6LeUam5%@S8Pysg+Rg; z%0Jd2?8!P@>Rkto1M84jw+^?`*I`!BI;1+SL%;bt=xVP+n%p{u7jnU@S1#aRb;0#x zF3{NQg2+4!&jm2Att^(HYf;oYCLl45ch*IEOf+a*Z=?TR1~j#~F6=&dC4ggbRaC5WVgM zvkoW3ZE?b(d?$R2bb{u3C#<)2LY2M~u1<8qC{ZVHA66sm&T8yDwHl9hu7*tMYPRmS z8Zln0v3nWIo3|QLDyv~Wb~QqWR-xs=DqQbg1>v?;Op|dHT$5KJZ__FqvtNZ5yj75% zz6zY=D){{8h|;HyIC;SlFAq3Evfhz#2^_IL$Pt-Nj@WDNh+8uq@k`bb)BZTX@}&cO zuQ(w8r~}%Y9dIMZ0pG$Lps>yX#)}-_tn0vZWgQsC!2!qK*yGL(dwf4(57}+@&?~gZ z(r9~Za<@mijXj#?+M{EVJ#LBGI`wHxP zyn^W(uE528D{!}F1)is_z$gC|7-L*)^{w0%a)~Z%3sRXFqdMf+frC9UJ7%)r7%%min$_7q5WqYHP+f$118o`Q?rKHIBN`kU5pD47h`wN zV&u0iMqt%qEK6PtolT1&VZRt}P1$+%#SGuK80p`w;QrVOblwU|`>gP-+6q@wtkCLb zg)|2%tmCX;G~Ej0C9UxC$0Bq-S%mW5Mey6d2tex@(PnZSh%Kf4gC%@$&s)3EUj{^%BWOo6=4lRH|!vcKESb#%83lQP70EXrZFr>xK%Pc_f zusL*|o8!$zb8J6k4$lU2OvyAye~>xKoXoMz+#I84nxjj`9I?Y@(0^{m%9^41kQtmB z%pjR*hVCFU#5$Ql*W3)xwaic@V}>Qez`ue2!-lcp5FpV4>UbHIUG_nqXtb_B9C&(k%ZMhtJPA#$n;G;2?)LbsUP* zIm{2_@Msl>G;q+;X zdGP+v6k<=E1CN9(v>FVWrnR++R8mo<{TVcFH`2jhcsFAB~W7*9c-=M#$S~ z1nCkZRKyxV+0zIOwnk7fFv6BeMojP32s_^!Li@HMc6S;=XS*Tx6tZnJJ6_N7tqswt zX9!JYLu?yi$h3kDn0}rCCZ8}s^%eujJ)F|e zgZ6kmRD7QUp~rKu>D(OLXqy9G)f{Y1nga>nIf$^Eg9pZQV4*q(tz+jvYDgE6_jPgq zj4sS}>taipE=DKl!p}<=SC;BR&qx<#Q*`l7Oc$#^&c@L@v!QruHez)A6 zmF~0g&3ZQM^=D(B@@%%wI2(R%b#U&64%ANQuy-XL+{@E}L4*!lm(am$OC2njt;4i9 zbXd%dSy=LF7PefOh2bN!7*Avtc4p0DoS9j0aGr%$bGENF3-&Uzu>F@dhM#F;S)Vpr z*VD#Otu`#vv>9GZoArS%KNC-<&4kXFnGBn!h13077}mXFjz z`8!QKxTy)1lbZ0}s)=3sn)no<2?JM6hRM@J$81gfmDhyXzZpn*HG^r~&4B398CcXb z0~uK}&=Wj^=^4y`rTGk`Y0Y5TF*6uGa60JObi`elj-&gh<7>@y%t@Wja9Y!`-F`Zr znNG(f_32nOZaNCTYM}Rl286pcV6sO8q2(IbnV^BEUK&tXrh#Qf8Z7Ru29Ako;KK)X zsNGSAlRzDL+tnc`RL7Snb!e<-d5hJNGe;dAit2bTq>jn2)v)ZE8WNAGVNbIf9%idy zT&NmM)~GQpa5YrSRKpn=HGKM|$~3Z7Vcn;S@B^x7s#Qf_sw%$usbZ=F%jc;gR9zLd z<5Y3>s|wydP=Q>x3e#a%fk(LtvJ+I$=B0vLOI0vzsKPYARIpG?1->7qA^-L?w0BO! zjcwELyhxr`zA~A`a+u6C9VVmAV=~kBoQ!_`$&AM_86!j{L;md~Xx*3uUdJRX z-#iKKxswnUHVNr#C!xY(61Hnk!V%d?I5#{IcLpZnW#2@6J1`L=>n1`bZ6c=mPlS%c zM40dfgr2wg=3Xm{Vz}U$O z5EE6vi1+gNds7}iPsroz7I}QklgI0Dc?`J7{a&nGY}^#tra zI04)0CZH~D0!sWRAj@F_5_uC4ral2a<0fF;S2@@{ki){Wa_l=r4%%gMm=Z6?^nT

8S&XvQ9iE_9tB8Q&0vN&=>7TY>xQL$MT>AA8950iz*T3M{HkOgVWLR(fAio-Gx z9gtysV;MZ$FN5A185~TJLE|PFTZST`mdXd6IZMMG~E2lBoMI9x=DaV|C|v z7;GC4sepr&CH&UN#n%Mq?p8Wh@?vvb^_W5OHe^!^@1pxUFMwCvOaz!^gnSWef}#j=^8; zF*qkX21Uc8;WRLstw)W<;QrBQuNjS~l+oZejmF58qjAA_G}Cq;4aYH~q5OFi9^V~> z&8J4eXU8aL7mdQls8QJOHVP3|qcBf*6n@H&LdRb*B)k*@T^7T?Lt+rriy|I0@NAHU=?N(9D-6e`oC8F39D+*r^QE1qR;;Eh}>XbyWT38e^ zuSeqI)se_NIud40Bk?P9Bn||Pg#YT1P{&9-oIVm|<40o2cM*s@62b9q5rpg!Ve2^} zco;8&(hVY5yhH?l=89ndL=mP5Dgx!VBXIfp2qYgL0fUwiERMto)P#({66X>4Yc>LH znj^4YY6PVJ6UOPs!U#Pl4AnMaT(1yDa-uNiY!t@hrNSsM6b5gyFkX)oM&&ypEW9a% z&mBT&*enE_Tp@f96+-hGAuL@Wg#WaJ&>}5_nlJz8L)SktFaAem>;KU!-G4Oy-(SkU z{Fm<4|D~A$e<_Cdm(Gj-CHeb*$g}kiwa5IS-;4jyV#PmH`sz15Jp7wxWc;RJ$KP~R z{Wl4H9j3)+hN+-rm~Ofcld|40xd{!^<}1JGRl_fu8TgC*xnHz*+%Nic|0m7a^^<~Q ze^R^kPx`3%lXM3EBflg6(T=6G(-GqM*W`Cs3e?HKe ziy!D|?Fag|=>ttN`9Q{FKG3SW?IBaK`LH4NOhA2Y5Ut(wD0&U>d1aYXPsWr#Tl>Y=J%KM zp!+2~D|<<=JzvrX{g*T({F45=`htEpz96BX7c_!ikf_898uj2gjo$T~#>BE@&Gr?a z)2LSiBzAa!My3ytu)_fTRUM#TpP$k9Q_tvg;WK*Y`ix%cJfkPSpHhF{Q@U33lzM%i zQrG;abad2H+I#y6ZQ1&Ss>7d9fyEO_k$FN9Pal&{`(s+me@si4Jtms`m~`JgqG=tE zNGj(M{d0OmA7(tF2j3skh3I<0+tjWqXOqp$JT=#=d> z%2mEbt6pCvm7`bbZN^nP=y;V9)UT4|&=rz6eT8lnU7((Vo-ExU6!!FUN1()c&)FsM#e32IKy-1@IF48&Mikt|;K zk?_$z>dfe)SjRpxQtzWLUoOy|t_$Q{bb(adF3^3Q3sm;ImzMVRl4wmYo$%?U@Oiy7 zQ>>Ss+&oVeo6nPN=y?({KTiiG&y&xib2M?!Il3Hoj*@N8k-pM7dj6`1$`ALDWqJ>N zv+tp;sy$@?xtm6u>ZbOBZgO4MP2#h<>Bz6M`=`*4ERsBIY!Gw>nL=@~6rCMHjs|&_&rPU8G~zMOUYGQP_u5 zG~whaI+A;eoYtJ8pPHwr=7)fcdj!;9CZK3f0V(JU=#Y?rR$l3(kM*6D=if=1rk!+l zOed|sdy;-_J4xjcCrNkVNjficlH8x3pkHk#s3h?O&0Kndx+b0=r#Bt+;b;e?Wp5vG{^BrI95_tVQVvt=io-N_>R~$Z z{t#K7I7F9n4v~ZNA$l<55P5t*NUzTxq@dD+^ws?!#mqTKfBzn!luHLltnL71Z#qEZ zj1N%3r~@Q*dq0(I*-x@z`>D))Kgmh4?W27pyJsJj#O)(#n|)NMxQ`@WwNuWab{dt| zPH8LKNl2xg;y$*~_mgcDlGjFW*R+wBRvSJ3v6q~B_R_Voy=3jVm%8-!(tM%4)OL9f zY1HqbI=?+6ZL)_lNAIEG+q)@v>u!1;wws(5?4~}c-9(RfQTv`^lr^ga@N{OJwJAke$NhSDBD3}JaFZ#!9E-cASVw$miP?UZi3oj#1(POENjqs}ecNF!_;<(Y4zA<1pz{Aeo)c5fy1 zxUH0Jy_G&FY^9Yix6t8(TSzH&3&q=Qp~q9VkokwrwE4tl8kxJ9yqq^v&y3A9{d)^# zoNb{OB`vhjy@fXGwvh1OW^%jOOebraN!hoVBIh;J4bf)Oz1c)LEluDaM)lFX{74Xf(e zbGx1-hU#d2R~;QJtfNt`b+l$y9qs;AOMlPT(u&GjYWAw7FLP^Y!H8Nay;?)h8fr*C zpoWr7Yv{_D8k%yqn*6s_)3NYs60@i#d+BOwdR#^C_Egcl_$o@ZsiMn@RiyZ;k~|Jo z((cqs`fgWA40J?UA1dhTi3(E8t)TVJ6|{Xu1%3EdPKIa8DXyfPy4IJIm~J`Q{wbrP zzB0O1T}DbiW#nR1MolBjXyAG&X*8FTPf#hfa;5ZEyp(3$E1`fLCA2rPggz`Rq1m$R z_-QfiZY!p@3B@#XNiq2-7t_|kA{sbcMAOoX$i=>hs#S{U*2hAU>MSJNyh6%YQ%GH! zg*5!VfDF3}m_HQI4)+3js#`!xfAh)iVm@WpWlEqbBJzI{!G8 zKJG~+`S?`g*`$((Vk%|5OrbpoQ|Nk13jJ7-LX)PZklFiW+R%|qnc2y-YjrYR)<~vL zLrEliI*AO6l4zA{5=GBSBE4^X3M=N*K^;DQ?M)mp6-gHNsHrX)$>>?Op2xRlVVBuSPU6E#!&F*Xxg41O%JuANv0=?tURJ9?r$Wu z)kM-Wqezmw5kZTBA}C5cf_7{Vr@I#6H0nth8O4W@mtq)|91JDFicos@E`$`bL&!oS zgaW&QscKy?o&Fg_Z_9&7PCtlvmjlUjQy}Gt1yXxU0NtVh8ouXGQ=|OJLe`%)w)s)E ztsm`rwTUjJZlVuUH_`YLzBJp(mzI6?p@1SE%AMsyJI{Ml&jxRLCge?j>o$_I@kTPd zWAKb|}$DNi=cPIDL>nYrI zJ!SrKqv{Gb+NJNt-cMcW;wD#mAm&Q%TGr7pt)nsbT}UCyh16wTNUv=zakgv8`qdh8 zNL@p2Q`eAhhckt(cBc3tCrU4LqI_*9DnGZH>O5Cd%fD5$qjnYTowte(+;F5LL5|cR z?ns^69jME~fzCd*r=B=_I;UVy=MSu;^UGO!Ye(lZ?dY7E9d!#<(3!O>=+uwpbh30g z9n)P-hx(S$KJR6;OJo^sYg|fArc0^%&JrpKTS7UKODJWREyY^dQpkV}dGl>(-9#H& zdBmEm?5&CSaWT!wT})~-7L)uLD;ncwMZ>=q(ff);^hkdZUA}BdotrFaub3s(w=87d zwUA=(S&&bp1v$!C(1N`SNY`coO?+uiVkzeId9pb@IA%sYj%L*M8B~=IO4b7Tb`#mT z6V3m_(bQ^=L=8E5dzDAm{CRYEG>>Ywm{OvdDS13FAU;|7m`BT3&!gExMkG;aL~myrQE!hSZSyds)V~I_zQ%xfMh2vKeJ%|J%%#g? z=F*O>`jld>Pc9Gj$S_8aBqr$5%l0{Ra>*PjAJirPG+kOSO_vl;%%%^kXVaM>9jYqS zp#W_iGCwzqk?G!3_HJR*FCzHa|$#n1d zBx+bSiQKag110jisz}=Yiu7ibBJJF)K;BF# zZTfwA8iM-8+FM+DxE3FXX5+S&o)ZmZP!9WU1RhmiV7!$RtmOzRr-LJ!hn8 zqnk8M9hRcI6;kZ|Uy7_QOVU4INjfYlNde8{NsSv%{dXm(FkFHbN=eYqUE^r4)j0AP z5GQ%QI9*T{r-Z{}Y0k>AH1K{5m1mD3D~&Pq^VDc+bs0@-{~JZ)%0|%%-BIM?j0TCG(LUdf@gf;j=O&5L@GXUOD=un%0_xFOF@Zes08Zo%~voX?mOT%lP9cQEQWcW>`8 z?(d7EoZ950oRz~7Zd2}IF8}l)uKnjh?)sdA+*j`d+=RycoYC!l+-iw^T-3sLt|G3D zJG_4{ck}fgZfM#bPTFZVH@k2bXWP@t`TW_*r5Wtxn*4TfCt9|1clx(+pQW~O;}&n_ zH27OM9Nx@1y>H<{)LXdhwar{}NfURpw~@Ol)X2S@*TDS=tmkC6)p42+YdKD?mRo6C z!+EDvb8*M2xWZ4BT+56~?vQH*cfP!wyLYjSdnZ!H{WU4&BtuKMX*-L#IZui>Gle2< z#j-+feR=^GbRwTi9LnSJX6A7eST=Ws%i72M-8aE*;m769=;bwkM<_vU_IogoK6&UfkrY#BFKACv#bW$vL{X;bO%q5EZbRmNK zH$R+{*dEF$PYB_rrv`EQp945@^XIHDZQ|@reYtfzy}6AF8@a&r4P4Za2bbvX&ZS>* zkD?mc$g-ia%?w(MnG`;R4DyO%B3 ze#4q;GhfW@ZCk|co@~jr=2~z&ewuSzz0J7hTg25{a9s61Q?6{P30IImpUWOL;!=DK zx%fMCxd=;rF5ti%&Pzp?TUV&VIsDP)Z2e|(=KY%7JgXVptV0@{s+u|{U#!ZB|C`4B z^PkFnxi^`6xp)$H_pmb8r>?}EEK%UvgygxVKsm1Xfee>oBh7^#mE=68kLOmFjpNKm zh;ws-$8b{~jp8Jhh;hTmMskBQM7Z1K!rU1VAdB`hryvOs?PigrVG62_;Wlf zr?Wf-gD&0+$xhzEx5s(O=Z^4}Z$8MI$lu2sT(g&V&}bJgNoEJn_QMvQ{Do%TldTQB z*5q1V__`_{XI#z`n^3~L@~MDVc`=vgwj+x-JuRL0!7YX78acaEsk2AKV+ zQ;#pHrhTUaO|LgOn)WC1Odq?bnZ7U?YkE`fnaQK~Z6??3<4m6S$(!7lv^EwJN`esk zlOE=yXuS0ai+6mqkL^8Cd4td5naH1%+{ee9;l(F+rSTE29d|N-VOK?WR-AMi&qvbX zwvz#88FuyL`IGIziA=-g=}C3jM1<}Cb@Jk_1Y}$p)4AIu0jXy4oxKcudU%&=r>1E< zTBLM4FYS)Ql|a+ZPPsUo?zZY25f;nhAUJf^pNoO4%lghLnHa{a_V4`9J{lLVM0a-Q zM&VRKO6REKkti+5>g;(G0o9snV+qNb^HrEDl<3b%ER z9utC_@w+?2z6If<=l;%yyMdUw@Mvf0{s7oa?(B3;^~Z#dXFA8(`oaEKZ|C+gn{XlS zN+(a?19PKWop=4bku-R(GfQ$KmX|!~bY@t$h`BF2*YG^i(f78qs@olJ)_m?%S+pK~ zPri4GcDiE5y5F7lI_vQKm5@NWY%RDt5y7S}&PcHp6WA|yLhZNFf*0kh;8!Cq(7W$| zd&c7h){6GHbVEwOEw#f;A6dcF*yZT|K0z>|aVbvm6$Srw*rI2|M1jmTYh2?`7I;0f zLf`kP0+HvIsPIj}MUR+j07ms&EwDBPtZlI05U}3@ z`%MA+ZLn()uxkOkCIP!P#%;3}uxkaoW&yi)uzL`&dtq_amJ8Uuf!(8k-7CXO+6&md zgY|)c^#xd;2w2~M^^t(}6`u_88R0ycKU#!$eAjn37BmWvoQg)HDWd=V75oh1_jI(iP@xp*(Na?6);;RX0rlj zyToi*z-*bAO$(T96SHvvvvp!NFJQJ$%m)O_7l`?UfcXZS&x#i?Um@l*0_Ho!d`Q52 ziI`6bm~U~+#{|sRIOcN#=6f9TK>_ncj`^g3`6kDFRKR?dV?HZjzRNKm7BFAtm`@9s zZ}XUs3z)C-n9mFT{o~^sOHWxk%TgUnek{#l>CIn;V`s^Nr6+&*2xI9F!?q`|^o9Mu zaAm3M7avM2dH>{N_kVnbYvMzJCHl_C+HZUWe&r)-h@~%l_)?Y!Yb@-?5u+2Ug*!_B{V&gu>DnITmL~^Ew|r3}@eencc%h*5(CP<~+Nu9zI&m@)2{I535srh?Fd`vIl!nZ=H1rZ+7}sE+Cz0vrB;xOhMEp6z%Ir^M`nZWWwIh+~k|e^bArV^DiFjU`h_Zr2m}V#9 zZfYX@5)<(?I+3jfC*n;&A{>1Zal|8$@v;)(x;hb??N~duiI7~xo(*P+us2DBw?QI8 zX0xQp_ElLP<1!e@vocbw>=;%@gw_3%0I44dIQl68tKKBAI7JDFc$k21w-exhH39c} z6TqEGK*fm!ygZbES&aMOvm*hu%?UVLlYnQX3HUEB0U{X*7|Cb6h$z-ZZ~`v-CSa#W z0%F%Dz}z7Lf0ra+pJf8pQUZpJ5>Tw0fXSK(XquJ)C8Y#pNhjd_m;_jlNI=c6cs%Dov)G#PFrFRHcn0z4pA-*exp>%#$Adp29-Dv0 z;pC?{Tz(aYTaOs$;#M5GFUFzmOdJZ2$6@2XIOy+)!?%Vw>@AOjYhE0S2O5W_7?vL# zhmMVLFj*IecKbL?w24E4Ssdez$FbPXjL)GKhb>C%STYWOMdL8(cP#Y2#DX^%3y$$Q z3~t6k^+GJfPQ~Ksp;+wS6^oeWSj?-8#hbiXl&8ePFgg|&17hLq8H*KE#?ZrPOurtDD#eL^E7lG-}PG zVaIqRe>J1gJSiF`Qqi~|!t#DZ;qsd(m_Lfbu4_>c?~a1|(J1WQ6~%O>qA;r@3NDOa zk{TU_Cch{gbd5r%T@(Zhqi}d$6t>KaLe}IccuGaVKqLyo-y(5rFcN|HBcXITl5s*K zvGPD9o@|YTS5+jQ=0w6iArc)ykx=%CM34j9UlfVI^CK}&I}#fwM1t{ zx?iw#CxU4=M_^}11oHMoU}Iwh<`qZaZwku~k3jIo2uyTh`;4FBU>bpeSrPD=!nTqT za1@R}=a+D%W|0H5`|hhohVERu1Te zGwu?r!?-J!Bf}x_Eesc5gdyd27-pXf!?hz}*t8=IzpBDm{If9pWjvP9O<{PjCJba7 zhH}#|Jl76`=AF9hD&r-yeciks)Yg zT$e`McaZ#I5Idd*qWDT6LQV$4YF8lSssnL1Bap>g352CbAU-S) zL_QY?HSIvOD+a%$ zP{Ft{E&t=`yyJ5G{y!dytU{!$va&~r(0yK3B_k1OkRp@{?QxGXN(u?t$_m+gb)UDr z_sYoLd++&spYP-G`~2bYdZ6z6y3Td3bDis)*YowR7Kt_gBCz~*1m@g~K=Sbj`0a?` zTu)|WW<=mX693zn2(<8yz!gLwrey@m+eTo%Sp;f*49C2?%)p!p$AmrMIKL_!jc11= zS{IJpq2c&2I2?_-hogV1a75aMW2#v=az2d1{5#_?=hQf)?HY&iE5>2K%yFCpG7eut z#$mtLI3&1?L-VHNaLsBQ;{S!gf_a&|;xIHi9EKH}!eG5943nmY;n9RJXad48(=7~F z9m7zqE^{;HVTk<{iUoH=vHcWtGdn|ZHa`?+GDC4VE)-jWLNTvzC?<3aMUVQSs8osn z|La&xeJ~d7&yK~--D45IVk|1m7>nHav9Jjqi=4h=QL5uugxQb9i3(#;_sbZJyT^RY zsWEu5V+?BNjX|%BF$jqs1KqGO$aEWn*=@&QX00(uH64S9x1-^CV>Fr^9?j#}XwFDu zekNr!I)shptf|pRa~TbLhtb$!Ihu1ILLeW8!0BuV3U-B{Vtxq1GD1L6A*c|*tW2*E zOluW_ebym7CmV%QFGj)kGP5y7qtI&gC^Vlr3iaYgq5OzZckdMSbn~~UO!i>#}U`)6a4B8irGAo18 zEi)Lg(ZR^~55}P$!6<3YyiB!VeEAuKFAsz8nwgoB?Lj!SI0$)@gAg;0d6_{$DBUFp z#`-}RUp@#nA4XvBjS(1la0KqJ9f7ggBk&}C1Ofs_;H2vav}`p38P!Li;^Kh)UAC5ughU4R#VVHh(7-|*`!?G2_xc1I6A}^_q+JwlbtXAn);&D%c1ynekk7T7>er)hhndOC~`&) z#Yp#|Xx?%tUR4>2RbPBC=#~$DkPjBE@NS7gaZa)N-%!Z)Ji^1q}ZZLXn8w~f{!RVee810#LsoQ-p z{xuqmo92VD{L#4+Yo9-ZlrpPTw~ z+w_NJbbnY3?hmt${qebGf0X>_hy5k}kR$scD8Ch5M|&I60v&x)1D&?d|%acJ;o{ed&X1#eL9ZZy!W0>VqB0%%=qOft{ug z`qb-#$bTNlxbMN43LaRq(gW+Ku!eYGv8xBt9Xt?T&I7%l_eR}Qz45ZJH@0RndlKFo zjr#S*m6pAc#Jq{kTX$?d?+$En$BArr&gOQIxc*cxOsU3f$;Y0!bg3sIxAjD+oSv9Du_tG1_QdQqJyF)OCt~0B zK*_lt>`Cr{xifm;QFsru?Art5oAkhM%-O+Syceti^hu`S#7}KjeA{ut* ztd8yoe$WkG2fM*JzZ+}~-SBZ(H?A?(4YO)>!@wUvr5lX7?FKlG1=V7Kt%Cq}NAR2$ z2z)DWm)Vb@8w5^G7ib?Uz}s5**hs*wj9@NIgPR95sF|mMr%nTdzXofaH8^Rl!Nbok z_9 z=PoF?+y%Xu;V7Beg}von@TGSbBsg@z$1+_o`ax%0rp{b%tuu0yI^(rZXC6;FBduy@ zoOtVuQfHmHcCIsm)18q%${DM>IiskqGfw~P#C3f-;o8nlxRBF{d7e&OzoirAHDw;d ztP^v!%w8Pmh(}90q9Cy&f`)WN^>!U`$f6_0zH&m@lTOH6?SwXyoH!rL2`*inu-BS7 zj87e~+VSzU!_GeKkmt}2lS{Y5h`Ww(+V2R{`Hnan<%pU69nrg)BYv4W zV%`0=@HDpN@uV%%W7@)IKwGSA-WCpJ+hX;DHmD`rAah|Ge2Qs#?^^g= zIk&4WOd{&SzgJyss#BM1HPk_mb9FGKpbie`>)`W{I%wFs4*Hd?g9&$QW9IJKSUsyY zc8#fxgQ7N$S=YwVx3xgW*|(op3wiOiknULvV;yRt$6s666x-t2CR=Pvvqju+TeNqw z#j8rTSoYWk9!49yn`?vYa2qu5X#=WdgZ>|DqWDxzt}V-&SQDOJHF2OxO|FTXaD`%_SWcB(HhAQ*>}IM2HwrCf%>5}&>!rzx2}P?Z>nQ6d+d)asgBFh z)p6USI_}$7=bC(0C_Zn6Qw3Jot+T>1Z!4rUw?aTEE6)6^hSFQA;aplZ%o$bPDB+f>QMz%Y^z|>J4?Jd zW(n`5me?6>2}=)4jJC7Ht}hlaIcovel@>@#w7>yR3w&y1frh^-qu-^bA9 z6|v-Y1q5!dfZ7=qaAkM}q_?lYd8+JPzgr$DJIkYPW_j!yQ69aW%A>eKc?8}!=k*11 zjL0&_jUaQ*+A+tzisoqWpd8Y7m&4<%a-6$c4s$w|!~Kfo(ELGJjNe@ro3hH{Sx{Nj z=~x#1Dwak3efEy;GJ`SG4A)1P;dKWy{3&mS^7l+(xziL?r<lgG30xbQK>y*N7`ynNaO?R`)Or0^JfHWMy;6V0 z$ftiq)$BiFcc(vM;Qim?Va9I}=J;DYyZK85O#UT~H~%FZuKW~w?N4#0;ZI?4_J{C@ z{UMU-{1D5Jeit(0ySP;SyC^Y!6SqUYi7S=9iGw@8iq*ruiWJkY!fWFfQFHJYaqZV< zk-6%#aO(S6T>tnwoqHdIX4(fauk{D<@Y;Lfpnord z8@(5E&%6`H=y#&T_MP}}@U8ee_N^#w`Bwbi^+voM_C^$!c_VhMe=V}uGwu8Rm8g^d zN))@k5*e>wineoKii@3JiZSH4Zd?v12Jri~J zKNbE#PsOaVPsP5CPejR}C*sTZ$HFZCF?+Tii%PE^iPAZb#QTnq#I@TG#kR>0#nh$` zh3EMPqDn0LnQb44eUfmJRbMA<# z9q)+ZlH0;=(rppsa9b=qQzA}IED`T(lnBeBTcUB$Ez#cWmgv0xrsy=_rfB*3hOk+5 zL;Tj<5H}uP7aONt7YQw|i!PUn#h18Zv9?yR70W zIG6u)J};i!IVY}7Iwz>{IgxkjtcZ_1E8MG|6_&fsh>N~w#Pr{%MVIBL#p9l*McT7d z!Y=ES*w*@#=z962ptzI5+4iK^Xgncm2AvSvGABgwn&YBHpW`Co%`qWo9}_>@9}{h_ z9~FVgM@3rQqhj^JBcf>35pkyM5plKfu(;OmusHwjkT^K!kl5gKNX)u%P>j(X+;0F>%ixvA}PS*!^p_IKOPSxR2f9<%3<~ z&6Hi@MdMxK?unh^T-Z*rv*J!MZ_^Gje!vdV?Zb9aY3_D$vBP#Tt9TpxhPH_>w%bI0 z(N@uY_*QY}?-mige2XyYu|-UKv{{&^Z5ERqHj6JOHi?m8o5YC^)u8Xtfw~Y?Wv@W|g>Ac9qCnyHa%My;9tG z&c4#=D@5hyD@5Mu<)T^ma0-D|x)`!2O}P7{38ybpMcsK*g-QFV;@+hxV(-K$ zVus}u5wLl(Xxx9Yc=>9QSf4qG{mhd@?USkE>=^b$nxzU&?-VgP%^-}2_2SJxov5zS z3CCouaNUzE27FEu100it+xSG$enWz&`8-~HXcR9F1;>euyjbB@5+i=rj1dKcqlJ4; zl(=_pq8MLcqWJ7KK}?)7UOYMwDLj8ih%L?$qHJ8a7_x1gSn?)J+-MdiDvk*i9aoMO zzIVrns9IyhB%jeDV@`;ec7Bx5RTw40+(wH2lY>Pw3KGA6j1b42Mu=%qfuh@{;o`&d zVPa9EVZu2mKwMbjF9NUoiO1Fa#7IwHaeeww(d(FxC^YdAWnG2{|AfI}&313`^35RO z&}@+K4;d)Z^SwmjtpVa#jRE4Om#27~)n7b6-cLL()lb}T=_`&V^bv*IJw)1@-on3W zZ_#v=yLhwAO>DT~DuS(CMHSCpVoyd-;d7*ic>AZjNOA5i%wxKV>6BC% z+f*2KH4zQoIf#Qz9mLR)jm5JijYRadhT^M5LlN7%fp|5EJ#$6&;^b#L(XzFj$QoNu zJYHT`bi7qZOtGpXPWP)VDx}vEt_N&I(svuN&e29(8dp<%US%z+-l-v)S=SI<2UHjC z8CIhIp=!eOXI0_RzN!!rRYdCoOJQ@@Lj19|5Vr?Z7P~VliL65vh5yeAqEY(_;(2&^ zv39k&2)wVNr$$qbCYVuBVWa1mm5cZYb9r#i+ z{P1(l)ppM`Jyt!@thIWqDKqt@;|(bRLjtr@WEmL{?BP0hmG>zb`* z#Tu^Ds5$xMvgX8)OPT}6E@(D8o!87SIID@PaYoZW?UbhOmlK*NA;&dqt{&Bl=ygO> zW#=Ky{)PuN!{?Ibdugee5nZIQeYj7PKX9+6?xEe9+_t+kX3KYICRlFQTsCagw0gT) zGiCTD&84#&G`245HU1mcX>x0=)ts7Mp!xQFmBub~rKa2U<(dGue9gpN%QPvCmTEHQ zF4km~UZly0TA)d}pR0))Fi$g_=4g7h%F#4jnyvX;VV34<(hSY&=b4)EL#Jyx9G|B7 z+#y}FWz|&8=xS3m){`b_rrb->Tr%o3H5Mmn1|-C5QU}Lq);Uhp9Jh$nl)MVlJUcl? z^Ri%+=E>wB&Giw(H3wb%H7jg~YLdQsYx-RA(p1~pUvqgzA5B)6yT-+>m*z=>?wV=; zG@1styJ&Xp?WF0R+d*?Y%2DI$*;*r;x6rgM*Hp9UQ6tTt1NAilOY3QNB-YlL4YAP- zbgZFSP`R4s#tRFL)$xiNkCo<{WP_Qez`wL+LF8YTTaCZFSl#{L(sTYRmvNp?Tr$eu zbIGF{E*s)6yKHTJ)@9SvV=k-m4!Gp_>~l%9*x}-Pe4|S{!x|T}j>}yxzggt6s9>&( z|L~bE)-|TNoIRWB^4mPl#V0Y;WzDkymv=q`T-qG(;S%c9(Pi=KW-iC9>bks~T*alr z$1*M+hu?OMTYjzUB7?E(u3@XXp6Qa=b)VzNu9x1l>3YKZSC@xp=6AVedFucDKdH(G z#D1WC$`8Q*zV8p~qchg~f3e=Q^w|HM^@6u{zw!$3@9zJ=di%|m{jXWCS)SVeO#Q#( z!~M!fz@NXrg!O)x3Po30OU_sqon^f~tYMMz81OL^6|tT*xD;(;J#Ohyw3hYY@*zda zf569Cl*791@c5!M)Q6j6?$0h-b={jSMSuRLpnk{QMat8_ZBlfDwd#q(MMqgPEKe0}W&JnwLXq-2aJvQZ$h@$njy3KkK!m=S9j3!EIaAf>l=dQe?&2*85k{&p&)#=S+j`|Tfx`Sc$f88Cwn8Y zwjI{cn8!Lg)xoG|={IeR)~rrd+Z&ZHgZqQ=JnLe=&c^kuXZ0?| zsjPojz^FVM+-Ho=tU)hbjqCyWpYQ9%Pj3Hq{fx@b!Trj(fVHl6ka0X~zx*M_UaUz+ ze2vQM!F|v8=0^&yR2*SE#QLwzNaH-#7K29{l@Embr?E3@>e6syMb`BP#~Vx78*=4w zlu>y^xDOk(tc_YF8vC&J9jGfAZg7{}^yCd;UNCw#vc%d(DpH_Leb3;Q@G%{Jz;PPdw4RGt*R zr;PPk*LKP^KK-16-KXXo*RviCSZGv!6~6C`j;!}mmKZ;OO2O-@%Z$5Of2_(gDlZG) zn?`5WswY<%zq7BUj{hp-Ue+eBR~wbjh3{XZ6RS&=b;eKZd2w4=Xxz#=pu+~^|2#0q zHyWGr--CTO8y~%A&&bOy#yr+2-8Q2yD~|)ls;nu?cN$N>OW{4o-NwnRGmh>tc46hQ z!uWyxGxMMCH?Cz}l58{%XU(rfM&+yF@x*xi4PU3Whm6Urg@+FtTd{5!eAK8sH$3JT z=df-`Jn^63?=$;wwk|zwRDK*DmyF&@51uoYX5BLAf^i#rbT&P{XjEPu9=nVcSqsgt z8uzkqXU*bk#t_z(Ew3AukB7%Mwd}-C#w`z1@V(R*qbKW&xnGUSQ^aGkF^l!|o*%|$ ztouEF8IRxR^C|glRDL5Kw~c@Ar6BF!KjR|SeJ4$12i7e)rR4d$?DO$2EyuDhX;?;@ zu+Dy6MlQU=KflXVwqfP*Umm~B9wzs)av1B#D&^$I6232PmXpfE#Loy>o7E+}yxek& z@5c@mWDnN*e=5jpH~ILFSCnH}&9W=W?>AELb!cTdo%NZ$g|ubmXN_EUJq0JXTgpzX zd$m>Mv0@(QdR3Lm7sbybdH)*so8oFRf;BGRN`AkZf>EK>&kO*JwL=_go5EwYHZ*tTn#bOXbnxXQ&*>`Z%M3e0YY(^MMUzFzfbO zjimB#@pD!NvKlrvmbXu(ASBK~`muV5CQ^C3_*pCmvR1p;RGvM-?X$3%bZ5O4+*~T( z7eB9M7uNhwE#&rN+|P_HWpmb$v{q7i!uXjkZCM>^wvpLKQn&_Y8)?e=Y+YNa{9^pv zmv0YozwXjb2D7G>X)muH-%PONgJ7?>b85GvoP# zOqP6~PI8tnjO=^s(^(E>b+_swj}`H_f4hrp$NGD9SDCk;pDU3rvI6VojvA@_X*>^+ z_x7e>#7QANSUcrFZr_sv3;%9XdDnQZBB$(5LD8%3^5ri6o}E49K-RJPo>KYRcs?WR zvR1Klm6LaHJ70H|Pq%YFS?(s4=Z)t)a?`dH3~$%_KYwr3R`!)0^^nRB$MYiDo^{ob zzH;tnzAx+blOH$nefO-NR9-orJIO5@*>9KVDJ!#X={`V?+mHfX1uv<5bUeS3^;xZ# z4wU*ro-c$9lGoSq`L*(v%45fKFqyfQ`^SO7^3fVTuZ$tGE9(s}AF2FzJWrD^R`a;{ za3~isWMAF}Upa3TkH0Z~QhD=uE+++Rx>BD5sycmM$1JDQ_#$0j8tAgo?FV+tOYq^W#W9kzx_kypsGHjiV=$ICC-DR>_`L3U>4d92jU zVqfIXiIQgWeRCvAny{Y9ik97H@N;!=jGUas&-=Qu@^B`PYfoZjDb}T%@_bkt zGWdFSOOQp=_}OYZ!+J1 zX?mG6N#zwAkwBIUt(*&!TjxjpFCapLDr)BKPy)Y4Y*}_DCL|CjX4* z<7}QG9at~V%8*`>{CxP7A(bbS-zntsaL!{cnl4X_wR~Id_9WKv&T$n!MbzJOsRaH{Qe@n zf>Y3Y!Ynx2u}v!TcP2HCHNM zDZfuiGuB-@=E>TF_`a!`D;)>&dFXPb@|^NJm-HWyg2TP$|L5mV?a$*=_r0z=r1By2`hXl-n#WVqozkTg&)Y(GN_!KYADrDOl}DM^5ahEz z2JD@;OP=~|z^(7Qd7F7H zLcaKH0PWfE(^m)O=n_7^ z0f(gWVDlP_G`nd)W1GYB>U9G;>kiA6#q8C-e^@GiHm}1-m#gfRUUx*6zhc0YN=N0@ zOWbY~k4oj;=Cv9*?t%fkosY>5=h@4>^qBl})_`J@<5Ky$c|AwYI?W#KlgH(dQwEf7 zbwbuT$={oELMqQUuldMz#|&uhck(}e$MJ}P{c@+I@`LlbklcIF0N)p^C6&&KW8888EB+S*d*FyuKuhb{nv?{5hGli@n{E z=VZs71{7X8CzZ#X*P!I)Z3gUEbY6ySW$*Z(^Rm$v1B!w#Naa80bt<`FBWK<>yC}Uj z7;tpvMQOgC&-24Ysl4gDmL=oY8gO#oCE02XYu(H8;cC`Nm!D|a(-Nwnj8bB55FN_WE(K)&<&}4^1S{gG1GwY z({IWbSq6l>xhdyl8sI(>eNejIJSDo+5ZCY-hrFW%wGPkG6J*j;8ydEfX z6AYMr@}6{xH$dO=zPuL8^#x|%m&&uxYlgB~G=IPEga5d#{uB7Vv41F)pP$ziWm<#* zZ=OAr^~1Se^?f9Z!uYyuc_fwBpVuDcyDVA7%&V^q~ZX0eNuV` z8_=ZOQ~6|s0hPj^N^Kz5FF5~HDn@|UFy-n1zV7p%NoRipd+eXdGrk7s0-sC85AZst zd_RQme}@-x@?Zn(GGEAQ-pnbyc_IJD77TnT+j$wd4&h6A$diBH_LcPN&+V>%B^7tT z>!mWhkAZ8Syq4d38&J9MwVdK^!1GFPq+$|yO;s-H#kCf$zL5=k^6@*rm7BWrby@mW zDqextT_p(v{*8Jk-82SVKk-hU>uTVP^7m4)47@fgZ#o;`_vyV1?8MyL&=2yF6JMvI z4^nXsynZWRw&VUj`J;?<*o?2& z&CgQt5xfp8-#Hl2YQ+~B*_g*Q)35SnL+;n1U!`Ivc&%7IvNv#6{x=zD$K%tyZ}Mhc z1HOIxCcW$MeG~9qo~va*)`9QR&6dZ%hCd|L@KMjTqf3!uLwGHn?BDU{T`ff!Z}ezg zwluwarAGzl(xkW%UT-Jkb3G0&DNXgCF&}cSG^IabmgHY)QcMZ2$&=?pJ(`UwL)-4_ zQ98E_S>4m4 zD|#GmXhu~o^YINaBgLuk`ahjI&*!zzj2fNOqxLH^N;#wF`Wx9~m!%{!#W3-@yL>HwdAQaS2QdSq`XM~Z#ny#{)?`zQRHF|susX%24^f)lT0u5Nj?QyaKDb|MfKImz_9!*+S zq_%l_d>USnl9%$&WmhD{;qd+lRa(Rh&!>tsc!3`E8&{&Gxq9}xRU*ac@E!^^o1;hS z{z^1{wjO<6SE3!W^suT|nH0an`z+Koi|d1Q_a$4xlU;mos^s!EC_;=Lg% z8_NA{bXC%f(c|p=suUBV+J_U4m^0%2Bf1-;hegY3WHo~Mqv6%aZMYt@va69|ka&-Y zHu~vN=~FejJCtj+G_s;9K6*^|u_DDM@jetq4Pu6AzZEU_(&Nx8E4tvRhoNqDQtT4% zRZ+{ndVEW*PJSMGY~Nm;(%iWpJ+4lQYvTPZy4_Qc$L=+#Tn|0+l4_7+H$8ke)F8z? z@tzk=b@ld=kM)jTa*m%vF+}rChs$5NqaMYt#=bEHgDc(Dy zU9I$(wzMYQXuvEn^A zI#5r~b;oS!P8~h&2iVfDT6)ZxX-kT~;(a=Ds>$c~-j)W|;LmGNiz2P`@Ecr<6r06+ zd9>0}kD@)b$XHpA@E5h{T17s-+OTfE;#X6F1ohT2r8Ecer`wW+&9j=bBqlkMtXmji+{th!{N9;)PWxS6`({Jh!>0nQDuIpgsYfp>0e$U?N z_N3S|-s_}wmzW`YV^5ne=ul9vKJ7fGLvOG8q_{NR4<&huk8ekPI(R~dwomHQ(PKJX zwr)U*S>ruZI(bNk8p#dl|GDhbQU{+q4M_29yst{9_UVw@ts$M@0AX1)1gYaMkKdzO(Ew-v~Lr0Z{r$~;^26HmbMh?F!fv`DqO3B{l7-EvOou8 z+s33AIo`vixhr(|IJYrn=Ib!ySYw*BOvkln8k6GZc%PRd7ja!8e+L@5fPXH_frjSt z^^p#w*gD<|CXu7Ve)}fmn9aQ0peEFCrVh`iG$F;^@qRIxO=kx0Srht_uETnpru1a0 z4(QXA6qCn$%5*qYhtN$;X{$kp-*=nRGMx^yt286U>+!xb#V0ba9@C71)3*3 zjM5=sR0~oJAn$RL&j=k7j<=vL!*wwI-h%1|=#bN_B`H3T_rd9*4rh$OniO-$d+y|^(V_Oe*8lPNr911;v_~6KJRfq(*NFC~PzZ>aD zVfOCqU1u@^zK%Xpf~17v8p` zsg-r;Z{MC28_8Y*s#l(`%ar!?qAc^5JKNJvQyscJZBL4uWWNDiB{{!XTW+pSJ6Aihg zMT0q=sQL{pa*uQ(#c;Amf@WXQBH6*2`d`xG^-yOje}VbU>CUA1PWDmIq|;h-d+khJ zPcpw*w=;b`riJ~0&h$U_Gqp2?9%62DTW7LAphd)^&b;HI#jWaHNO7U;#~`=8TI@{d zLce!uQNOSYZQG&6%v)VZF{A9+pjunB2+?%?FNYy@y%wF9cO}J>vaf?47idwrj0@$i z(jvZt3%Rb);_he{QmiR^KWOz*KEIPLrk#cDJGUZEi^2IuU}Yq`W>uArzPEK$p|gxp6$-}qZaIYp_~5vxovt-yf3#$ zP!F>5(c(`|4^k{Gdt-?AEV1Qt4|?XQMLCC_G^w8!BZl@Q#o4ldhIYAYVX?m_dAf2t zzv@X(duTaVyca13mpwLAU2s22=|vm5ay_-Jy{KDfZtsV^Nb$Ms!=Z5<`1{R3h@0pBU;aklYJ9xk+)44k>5T%#lep=6iEJ|r%Kk}fa-;&{6 zqYrK3I&lWKKBO39_8`&Dcgd(w*oQj3NydO%eQ5v7WX!ABmlS`@J|&V*l2K=TU(!5E z#)y3W`~76ByvTpQo6Mg6eq=03hC};))a7O}#)kBxJ;ljbm)nmNx6FPg+IETA`&Imk`eT_Kg~MK_3G?AN%79?n<9fuMvcjy z^ksiCymoj}_+Dn3AA6Ewq1jtSK0A`}&usvm*~;gaIDoJ@8Bv7;NO98azoN#4%uQGH zq6KS`VXN^X^VNKw@|D6$R{%yzW#%FUYv~SS%auWS~B(<2a)2k*$+m4Q<723 z&YQ;QlerFqH=R#TM&cxIQp`4c#%O6A*W`QT{a^0N*on+-yA3AAbF;6E+J^ISt{Y7A zLX)xW=3x3ZIvKYs3?apOv-gaOf|AiDatPH49I?<0NahgUM{&GR9}h_i={cJ@uixUW7`#UmNnO@>m0TQYX|4kg8pv(JqhbWg^w z{XoWj`O2T2mbvvex#Um_SBJM{bXp({b_2wWGv|HPsO#9v2&b1DPEm@ca&t! z?ReIoPFW?x?5{uBR!xRon*dTQJA3nJcg183%n2aV@_ZhL187iLKL1Yvq&Ro>@6k(> zWNaNWj5_{J!twNBH0f6oZtodJih*a3AJzDp1hZPhDex0B@O_8Vn)gX)r5jF)k7pks zb$pcs@4LfE_nbL*%RoB(Bnk1|0!gv+>=mT`_mi-2Wgz9;Ny54-fpqOw684ymAe$Tf zeNH3D|5_5Rju}BqFDK#Qf)RA*LK5Dc96^e?XU`!8o=$>!i=hAVc5WYK9)D&KDITAF ziR61AiR+aIQLZrwF80B6d0!G-2L_X3_1U{f9y^mTWJfSf*_MQ1kAq2WPQs`fBS~@m z>~EyDg-Kj1dnARfNkZ(pk+ghO5)yBYB*pl%2a+o1B_XxzDC)U{dH#q|l(;YnY0E~D z;{VwvNe|{EA>-dDsy>_RK(-Ab_nEB0A*8Ya*h@(prt!}m38C9llaT&7gepx=!qmp2 zN#zEx-;%<0Nia+sO^cH_H(>8*IvLOH_hK}uOab;}QiG@@MD!g)p5v1+MmL6%!;>&# z(-=~D1MJ(R3!{_ZWjU69j7&oBZeyuIP!bR|mQ)r2dpjw{KM5_bjHSgxlhD94lnxC} zLQSVoQaJ_e|D?(TlJIYSD7EXCgij|z$;TrJPriqe$}nJ$C@t%mgj4=ubg)|z_Gg9B zLroGk7{f^A8?cX*8aXE+v)(xB<-~ai1IAHEyCjTF9Y-qrfW4-)q9xbOd^nB{G)qDo zt8lvQkc8U3!b#;KupgCb)aQOy5Ke9Dalb1Lr@pn5aI9PesmuiStWrviBrFJv_%CN^ zt0jN_nFvyO3hZm8d*!({XRAp1T9*4~U?f#C<@1>pNh)iBy|3J_6LI2wB=z}~hz<3} zQ{eYR%o;SFR1O3CV`<9AL=4(Fo^szMqWzQcwB~gps#{MWmC?W+S~~HRYj!3~pyEe~ z*uHK8J-MIA>t7Q{1N(K!_edh_4o6YY!9;xf7)88Oi}MYmNo7K?rED^RPRbQnzt##ItBpc@gaUrHl>y^Sxte#yZY~NQ$BCf<(lwk0F&M!QNn+lb;Bi zO0hI|X(FDx#L~P)iP#s($~hD4AEvo;6EXBcEalAR&ozmo?3sMtZR1E~P_W0CGN*BS z&55J*sfqAE5=WCK@y~sZBb86VK4ePJCZcFaJVhlYA}u|h#>FMVb5A^}>}MvYQHfmREPBx1rRJ!St%fPEtaP5j9_4X|=lOe6Qfb(k1jH^#r4A<(aAHd;sSFYJ zsMCW(2^fDrmG%(lnte~DnMDb(syc~Oz6kr+$!Qm7h;*Ms<+mrm+3DNmvI!3oIS zH-%J23VZk|F(3g=UrwPez6qFEdMf=H%)eJ_DyjSw_W4taX99Znol4#M@^u+Cl}vgk zpjbPVRJIDU0A%Q%fRK$-$whE`9Gyx(x+LJ;?Wv@4SC|)|=ne@;uAD}#9TRY%aT>j7 zm4GrLjZ`KJGX)gbBmr6D)2L=6&Ui^rql@+lsFt5bDzAmP1469?EVz(HU#+=r@Ut}9 zWX0FbB%M^23$qDiQ#k>7ZPV#&c|M=s>6BVF0d~RZq;g)EU!bS|xQ1{}IxYGgk9&pb z)aOS$k4NdGGGLf-pp75nvGij)1-y&LtqRkq;_GzTJIvS5>t{J2Ohp_>BMZ^fv8|$JsR*r1EH(%b;&t;<>(S1})wg zkJxt^B)C5E#&Xk1Wz{gdK~q+8hK=)dYLp)jFR$rzYzZGv=yXy!Hq3XBS#CT&ESyfO zbK>E!Z94Uw6_0>Z(@ACAFatt{Y4JGvV>;EI8jo*PGigt1JX$o*B$a=|oCv*5ibsxr zCS}BPedg#)Y7i5TFPWL7vT>Ltp}`UH@GHus*P-#qypl;%Msrrqt4vb4In0~T*1&kw zu9HP>0rBYDA&W|e#v{337O6}fW>Tokz0$nb zjx>qKySy3X)rhlv_ROFX`*`%aFoRTv4>L0K!ItYw|C>R{*6}!4b0(Qu#p6YrnWXZ4 zn4_WUmEzGkXeKQ+k4JFgOln{jkBr$fNoD^qYeTL7#-aG&Oxp1?4!>{AB=iN7>7+i`SZB$^@VELq_T#X{UPV$aj4oen|2(IWBxOnS|5mmcT6^^ z93tj}sKH+T-c{MObY~p47iClRZE?7CC7V=65i>+&x;_pTrn5=ACJrs@%%%@3;RJIYbNVI-t9KIZ#O?5K4_V%6GG&4O8 zExybqm3zdz5=}^nLr~)!x~q*tk|u}xC&pp!kQ`E(NX#@*^C-?vO3R@Ik#V@QEQd_T z@#pQzA(fZJ+!Ng%8HdJCbI5%J*ZKaNL)!x4FvxlisVpUCqiE{jIHb7Ep*LP}m=`#Q zhV+la`uI7da+a8%qK0m9TwiStP45whXEcZ2i8%Z!o?kEi>ou#XS0H8i(?}^GIbrG4n-R|HPtE#=QUX zGe>`oh1fffR2~#_VN~;7EQUUxM-yJfVx&nf9e);!@iw`nvZ9zBqnP`#n9@6!PTh{h z%%EJVcQY0X68YabM~e9}I&mo$>(}K{t@E50bugDAPsgI@MlPw0DQ3{9>XBHSF`rK( z55#g^^ZB&BC>A%J=ab5xVor?)?u^CL(D}4{Yb;);&ZoBlvu^>ZyesDB=u0B&iv`prjcshm7&Fq9#!tg zSzF~7QQzLN_-nt2GJ3`0hw~y*`C82JQE5#q-i9tB(K!|`QWsH@6W57fxQJBt7PEfz zrd2HG94?|J%{iCr{vrx;h{f^mi%8{iF%L)=>&0Ss)5TP-b}Tk^TTGgou~_Z9m{evL zGlNuU8H?E&i~q|_t!5qz?cT+t^1PTUq(qZgjDEhD*8h%ypUD!s{XGW#ZI+PA`eOEw z#D^Gk=)Hu-zllMUpe2;|A_lgJOGxE_F`r1k9>n0!+9lNVZVcWYSVBIxVsP*J5>gpq z%rMgC%P}}mZYkY7AA>D+OUd+14DvcHC6yn>oFmWQd8K;nQkrytv&2%C^0*QM-vvua zWs5NjN#A$Gp#6!ZWVba2_V<>O>&6&V`nHr*?illul)X9zj~tfK&gJ}lVi{du8iV~l z%SdICF;hu(b7L?oeHkGq28nsgC}?I3f_Ecba%r%cXN5^3A@I3Mv&&MB^M=Ixx`AwQNCI(>zd9-e13)MfD^}3O$I)oIZv|by z9}SaBD@bL$F#}6aZbW0N$x3>4H5$`wR?_>6(Fkn2l2ra1bF%c~WHc%St)$;aqj5iB zCH*_d8F1MvNoB(^OG{<;@y{PvNv6A^(f;~MGTRo7vhP?qH;#E*GA)e8rh2P*|2i5e z9amAQ710>zxr$V#95cD}dto#_>sQhDdC@qQyNW)~j>h~=t4QU|F}F)EGosP)&MJC5 zm9yx+tfITA(YRV^HK{B*W_#&EVl<*$R?~^tXkhSaqKVO{6tS9AP95{Vv>`MaYnH60 z&YG=BRP zP^Vsed{G6|q+2v*O)nsoeaEaZnK?(J-o66*+&&slE*8+kHqqGlyns|L9`nd#Y!Z#m zHfv~I!)WGn*3ewLXdHE4LnQ>Ajz7*@Q7 zK9`P$-P<*E>u(eun5`w1wa4r;t@+9sdQNL;#>XgrpIA#1-$vnS$XZf4e9T8vr>9XE zGjA=`ddUC3aV`D66NSe|){@HTV}_azT#G{Rr?r%SDGGKK*HOy3DBNzaj#PdhbJnCe z#<_ii)=}+4QK&X<9sMvy;ryg^q_X{(#is2$Ipc5JI-0dL3V%4M(+jC}Rur^(g{1NV znfs=jlcVtLTp?{X@b5h-q{+!q81$!*RF)vK;nXZT3Pml~)33-VOz5?q&V@yx;js0j zat4_nrwPG)oLTD$!=uo3)q1k@i^7}z>q%u0GGk5~z5b7zoCF9V5D0`2 z65{UukGm2f?(P&TQtY9)OMyb6E$;3xgS)%C1b4T0&WE=j`nyZ+-Lq%q%*?rW_quu_ z;mL9u5YrQyS}Q0#q9@jMSV4+UDDR=uZS;h0yifbtEvy*M-p7^ctN_yL&C#*WJq-|}5gYCAG6!TEt zd8d#TJz-tE@;^TI@rJVe^p&J|i1J=Mb^lg}Q~Oqu{--+pdTk|Ld|M~aPp>4!N|bl! zDeY+;YP+r?gGY5}>%EFD-L1pU#8sp?it>IvC10&WlVPi<^~E}@oVAKho~c9P+Et_& zi}DUWg&nEG>|3iy^FSSZKdz#kyX$bPCucjn15YObEeecfZiI4 zpCJ9RUPFrMC`8+6Ye?}Pg&RQqd)1-E)-_~VE897> zhAvgq$@>p$NUX1V$AIkYg-7YMj?P=v zp>yOq8qlo{>+{x;VowU|fcAB&!{tfqsI+|@DwnJyZT&iYr*)*bl)^)x1noK*x9jLl z<2resaXn4bl71PjC&jE3W&)l6T#LMz_5X3v^eJT{QxU<#jsEDqG-Q^^M6 z-L)7#cmws=SqtqyHjrXu3d4bZ-%tyq0~@I0np!NnzJb;)uZ7*a4W#&)!g-*p|J1_A zbR*ULRf|2|8%b++EyBBRB*oSg76h43u0{7@8)@sfT3np9ks?RcB6ICV8Mn0%UIdj7 zu0_GEjr6I1EgpQ>NTd4HqO|2EQcO-^O3;F;T2%UNBFC~?JWJk0I}2-3UA2i6uT!`a zbS^{wJ!cc;q{{c}H&K0}EPr$pDVC?ODdd=2JiZY9Md z6)p!gKURaGW4F@qgEe^l&sO@frv?Svwvu9%3cG_IZIyQFw^H`T8m#}hmCmlIfr-I3 zQXEs^d(e)>HTV&_jU4{1K~?rP`uDFI84ue?F;0a6LL;ZkdJDGEr%5&Fyki@cjjO@f zv)f4VPlXdg5yNYctGS)F{8odb?YEP8{~EYBZYRY?6_yBT*43af#-wSggV}p;6{FNV%|so|?#Ue71w) zjA~%ea3?8FtME@qPrnA2oOe>MRyA;s+DYe|*I-8ePErh4VWiMB%^Gx{yp!I1tHzoo zJ1OB)HFS6L7jGyV!sM&g$7=)hEwz|x^Sr) z;|g|>!?|kQ@4t%_7gl&IbmxfhUzhG8uLIRmfA6BnyQ>j)X%{JGtT0>1Z%Z}aHlqJL z2=%L~G2fL)@nnVTLQ@u2BeIa_{`_jp8$jeSry6gj5GmHIuwUrflxob{O=LHr8c#0~ z{We;*`;tg;XoU|$MnkG`+lZ-ZKs6lQn6~$+#;_PB#i$jA45d^F$95poKc&^EoyzpQ zpc=cDF)4nnaAs&kdNtB6Go4JX#-f)@?Gt4Cjdzn`+X{<@mWK)V)@?Vv39QD2nBC;% zC+!vOCdIuKUJV^|sm8{syGh5P8sC@grbKJm|2?}&F>!@yLsz?02gYmn+;Gy5FK2uVeO5w`SGwDB43M4dwU`+(U|`D{LHk@TCfkmhU064^@cR zvxf>_S7H3+J)}6h!q1_bkE+nR$zC$NSB0d`dnxs1l`!4+l49@*V~0+h7w<&TUTSi> z3Mm8kQsA*F%$T~D6rWc(JhXmK74-J(r6)V9ka&5o{GL*Ui7)q(V)qKGhbFDALetLs z=)kfngt+aaFAJ+MG-e+uuCMTXsBlgdJ`C7LfBaDer>Xns$doEnEZawl`76vHvKw86 z8<+O|=f9XVxC*h2_sesVRS+%^z3g3uov!<-b6pkQMDM4V$|`woU_U8Vu&{$@Nq!Zk zP1#T9v#M}->3-5k6P_^dC&dvKz7VCxRiW_3ei|C7Si%Qrd5A36=>RFlurP?|o3}8B zqYsdodlj+@4p59!6(;mQK#D&soFbZSQH5tq4iI;(LPtJ8_l>F$dGP=#HnFgb$WFfs ziy9uJgjQ8J+wmavYF>q(&Id_xi-mVYTQsWVzQ94c^0gAfe?3T_KU8Anq=TfG#==A* zujiG}po5fFUkR%V2dVG9N_2mAkQDD&xJk7BN+td^JVYnYSK_GCA$oGE60af-kzyeW zTZv2#R>H5}A@bQ%iGqoTC}n3QMlCu-ijyq-B^tH95~t1`qQ6&F;_Z_|v}I`}+G!mo z#ZdO_aF`yBU*vrCtq7nTnk^cBF&G@Af{WOly;%Z?v8yq3UWfmS39W1QGiO?f-A*T|LvyRZc z^hz}BeS{RVS(s7uGrkgD{~r0zd(u9vQW*P3Nb#J7D@6{zm6-SA2zhx_VpH3r6znYR z*&ZdudKUH+rC3(tOU6;kF|CB|FGs1kv#_DZ93{np7CsgA(yv7PmZQ|aRV4~f9;G48 zE7AACQBsU(VOY^IbQ1vu~+DSotYu4vk`3f!qZMl&8&;PuF3 z^vB%_Xv~vOVM_}OOPa(~4Gu9s`#j6(X7M0Gez>?d?DQ{*4 z)_gopX;Uk(x#bC|BP$?mE(#l6f&IQG$oGHZi%B{`PJ^Z26(=N53D@;Ue9omS1_2x;xAI`%aR-owRrLBq^@8@WiN{scf(5 zDbnmL+c!Q%Puoj>+)t5WZVPjasHOC`=+u9{n@J62f2N)y#p4z(8D)Pd$L8IqDENIj zR$n?rR;@8tu zaJ(EjlTK6cp>lLze3}&FTNr56a924z&!49ITgqYm^fc{TUye>%XGrnCg_A}@mX_m( z!x_q6P>vU2XUJ<_Ic{d3A;kt4mKwdDR*s$H&d~9RS;ko^%`2DpYtEA5jSIJp zTBnxdz`V0k$CqQ(CRsjO_V@T%QY>;|yHQ?XISRgFRlUc2aohug{ZWrVF!<`t2`6nehesf6tM|_A+#gy+Dem zE?herxkk9@11?bH@-i%(a)FvJD#O5~7f7+zg?&fk|15*$#S0WOqYU4lT_BywWjNR1 zA}J2L@bPHu@3OqpMG7BUhWLn!)M#KCy5?Ra#b_6X9u2N5!=dpP$*ZzVIMx^GeQ_Bo zwqGR0Zx_xUm1mZrdHqE)O)bOK9~bFbLK&8|y+n%bE-XHZ4l6@w@Fi*xScWzkmuQ<$ z8E)5IBE@|dULSRHDwE&!F40w+G6ZkBL=(-+(DL{tQcQSZ`qBH2W%&2=C0g3943)Z< zDWi26TrDn>;>8R1k9IXK!~W#URIOQtag~?J=vyhe55G)`CEtGbWg7UpRL1pXvU*mE z1qUzFrH7>`y>XcoXI}V$xdQ=!G#zHxHKLQ}GoV zwWk!@23;Y?ou%kM?FuPAy>JL=*t$}D-hG9vR+eJRr7LuLv2g2OTp`7-7giy4np=w3 z9k0@!KT5I6`6`u6DMdx(RZ?7g;Th8Ek)^oZ_bMe0E5)1%SLyA*Qlu=rN{V?e%tP|% zS&GAFuKwq@`n9AKoEH9Fm`6l+>tC&kzo1|w;9 zEJbU->omJFrNp?ytU1qra5E>cDkUY<^)m z(z=%=82;uug+3{PeX|>M>3#{W7~dep?HAr7eY+xmkG(+?&X?eF;SK71sszIZ+#tpD z7bYb6?JvREB{%3em7qV}pv-M0=yKtP{N7Lk;YL#5)x!1Hx=9U|l|Zk3@a#6d zd0Pzk26srg4uri)59*7N<#>m3?iEXXzC#yp6k|yC9a0_y;d9b~v&Hyl>>ctsQ4Gg_ z?$EkJ#n`>&4k<^1Fg$7Q&SKoSe}{Cp6wC3rLnGFSJE8Smd48-I!uh0%#nKM$()GWK zF(>6N#my;(dDUG~ZUte1lH=rJc+b8|e~&H3{xx^0)$hfKIe3?pcR_fe^sK-1@9ka6 z=v|C^&F;~m8re>ld!(EU!W5;y3yaYw_8w{H6yrDau7BtJ$En01kL-D>?Fsj{e9YQQ;doB_epskgkMS{yA)%5 z=6!ldLO!C~J6da=6*3$Hw&s2xS<@ah36=Y%j<>F1gvXc;~H&u6!OVG$lhJ|yL%5H2ef z&X#ujKBOJfir_opA?Zyl!m0%iNx3SFwm&2uUWDmGp zm0DL7A;kI-6_*rYUBDySk|*o+ctpx^Aq-f`Oew~@kI2hK+HYP@%8el`Svqe~1b2^mGU-}`xv}+B-AVSRsGgKJ zLwK{)u(kAmay`Xq7r}l>Jg{8rHFflxE%bLCf+E7N5*41e@Q$Wb&pB8ID~CW*~bf!_}63l=U^dLZ+J}icNaqY z=wniz4&mQY`KChb{qUGptSLmN7EkEevO@GVeL~9NA&gwAo>vH~geSCeRw0I!JfWvk z3vp%86HY$1+~eoD$2BFtVg4Jt&{rl<`898(-6h`zjDl{$xe4deVjR^Z!o{N?3ls=>^mpVPow1t@fU zPD`&8U|HC6QvMR*43p-`0yy`2PIiY2mlKIa`xlM#cOsh5*!2kGjy0o?c zL+?H(jTHsh^XWM$?}_k=DPevAg1Wt+UuPF!n9mEEKdk_}6JL;Wq6pKNo{lPj@8B1t zJG=n>r@tV#K?Tz97o>bC!ab%zbp^1!^n(7bC_w4+7qqvi0RJ?2Ny?=nY-DPbUI2Z^ zmt>w)fS9nC6dqfE5m_%uc~*p*DgUx9wZn9+8hbHg8F} zX@q4>M||_qDeWztcF%`r&0D(Yn2+QUZ%KJ;gm+DM%BGA`MCZ%ri#+7_lh67*^qnBz ziwj5C+Vt*v9_DS6^)KdO-Klr<@^l{dJ$OgTlOz0Xdb~dmk6OQ{2b70T7Vqiy);u)z ze^1JxBaCjkurd$k74PZPV%gr%_jLI0JmH$XC*{`>jyG+ao`e5D9!`DuK+5MMTyc8sl81|3KhkZxJY4qtNT)3F za5e5DDc6s%$7y*-`5f?({%9+olRwh`TFK|)kEA?6*LHrSj0SnQa`q#Ie9y(D`j2G) zF&F25e5CfTb0G|K(tMhW6V{*T@%>yJ4){c8ZsuZN>L=QIITyk?r}<}dv1Rxt8hJby zYiE6;%7eLBy806-w~(;V$!&WsW?ub79X94-;;T>eeN`?-H2zG=J0!ex+V@W`YMejQ zqB*%Ji1tTJnXGU2@^K>kBCdk}%$>p+&AZFTcohVY&GD;|r}f%*8GJuQXae z7s7$3?3TG$8Ss@{no7H=U#W>!F8Wn{mG{_kAgp*={XPen^_7Ob%t6=HUn%)<4jS$M zO3JGwJbC(fJqJf#ex<_~bFjS8H=1=i2V*;aBjsEY<~(`q&p|}^xBq;#=eEfDy}r>u z>vAAmda7BG1D^MdycgwQ&c<)lczzE09{onj)g2_WY9xnV&i!*YtWBYfi zO3uNg)6z~{4uq3W@56K8_U$`u3(P?iy&v?OPY$kF{2;i={`mbMEr%QoNcuthEOQW5 z{)2w+nu88Qeo$zq9Mn($L5L@GDJ4vP()^x{dd;6i zAF{FD;3o}ym5tx*ev}Z*W~DTS(q59$;!heegvNNC<}4}hyCw}ldD3L?_bTri{6^799`m2 zV7rr9m^)UJ&m77^uNj)$druZ3|JG#X?-I`fZ`+t9&*N!w=ISgQ-L1*rmSkc6F-=x( zFL5!j-<&K&+|lG4)3fA!YVx3oS$Oq9la=>Nd=0#HSQh@!(c;vBStvKq;w>g6KQjx%W3^cM!o>T)GvcyfR;a}e5m|UwEz1RFVgIjM zoad9J+z|ZHH4B9kwRoa^7My2maW~5>XfD)Z5B0N9xnGM1w9JCn zDJ@nGGI31sKbl#>L)Bu}ubG(tQrdr)iK;JJto&r+q2MQvGSNV{0S~y7iIav6So>Ng zW_N4A%3UU|3bs0#345Ogy!B8fK7}^musxaBo6vxj*GzmCoWC&>$t4Z=`KnA9^=!cX zmt^9>zy_?GXX3oz$$w^|&y)uL`KcF9$V9^>4Oscm#EZe3hh}2R&Ias1AQL?fHQ=~ox$fzGO_eg1J20HMD?2nd^bk4*fzlPl3HWOna8uFKJneu#6LstGZ@pSOl_Ojn)@^8INOzI`y zYiA;1uq-cbHgS3I#~&FuGp!-_`ILbv^BVG-*BMAy){vFAO?)5x^nM0TQbR7inSlvM z8uHys8HhgLkd@O-oFIJhXa){GZpaDyGce*^Lq4)gTyH-cvhux&H-xvX&A@j3M(nga z1AUAe@zMnuaI$X1$^|EG5uW}>29}}`H=CS+f~ZD3cuWS2QW~-H#EE}|O9o|Naz!J) z(kBB^eHw90Z3Y?)ZN$nUCyo+!D9AwX8IAbw%naE6-H2PKWZ?etMy&jD;xXY@;TcHU z-H3AoGlZ|!h);TFVE2VatlV?rI^kt@vfk51+|D8cci%VS;axH?Q=>5}FP->MIK52< zG}<-h{W=-g)TJ@oH_kx0O=F(*GhI1TSo3o_P6agn&r5#xX*%3e8?*A+iC2aHxtWgH zm5sT{<#a^%ZOqkY((!F*V^*#^aj&rF{&eL0(U|A%N=M6o8nechbnuGCtUP$)XW>K3 z($RTOW42n5juXck^SHU`7A%CxI!cDzo`Mym!-#HyV!e>CBW&gpRfrwQ*hNXN|;O<4K* z#5=>a&C_AOrwJcukd6z-ny}&bGz_{Ze;1dZxM_Ib%QPH$+JxIZP7}YMv~xEN`kGBy zdH%#-!!0kQA*Wqa&O4cg1}05;-Jvurv1!W60Vs|e?!G+@F9VwLKO538HM%LkTA3!t zzbPv}pm=b2!u&K0sBFqtXQiQ2-==IaH4QYhDJyrNxN?|Bq(S44rmQ_U4gdVzlvDeq zA#g=gR$f8z>F|^CGz{C_lwAtb(B)WD9+Z^^zR;AFb5NW+tP`Jx?@yZk=cAt;m(f#*ZF|uV}_YKlZ@m-pzQ=s~+;cW;0ffL!+_HIN)9nY@XhXhg|Q0xcSX^ z*M%Nd6ObN=ky11FX=XXR-W{}E?)6OZH0<~+W05BzqhIqxv&0iCnWSvefVk;EOE z_kh(S>0g5$*z&qL_xYBJ&~MFI`5nch#HU`QBDb|Re|?mSXC1ZK;!Z01n`^UjKZ<0o$v)b=7s z=%*_86W=aQh4FoD*2)#%1IF zbXd79#YM&ZF$F!w>+qFVDY*294!?Pvg0z2hSa~nSSH)eg%lDgg*!zNfzgveBPo^OC zm<}r^rZ}zmx7{h|ep`p9ZA-!FCpx@zeG1~<%M%zYQk3_KPcKYCMDrGW@2?ab&~L#X z{zyTfaSMs};?T5e!G>c};OW|eZHK2|gMSP58<+z7$QG(m!OG7m9xguYCZ5i9E%>~B z3UYV0;F}h*-v?W;a(9ZWi{Ere!QN{v_^Y1u<6#SKsFQ-#uUfG3dWz4B+x$qz%tkHQ z@MAJ`bX&5?t7Hr{Y{|;`Db6ppy_<|uhnDPgEg4t6TC)53WW zOAg><{9D+PgSRF_zosQCSE#tdIBa<`-Vbld;R}*cJV8F^CgZ|P`4o?+_{BJEVlpQv6_@rhsI{ns)_kBsih*7P0%iAP8o6?Gv?^L{L z{MUmdsiRx*L49?(ePR->50&<#lHfB= zmz9@Qd~kfyCkdbD>+&YoB=lIW%YWJ>VbexkR?b#&#&NN666%iVa%B4?oH(b;cCC|O zbyJs>&sDr~{8lRoci!mog|FS=_g$B_yz7oxOZy^4E|`#lRY zm%BsLsWmGPtoZ5pt+}c3)H(XDypY90muE)w{D{ej>q1hdGOY}JT zOClV5>ap3|L<||I$I5dn{yyGwKM@@#>+z%;i75M1kFzg|?{=XcD+jJP{`kY8M8s{= zDvN*iuwm5ATxv|;7y6?Y+z zHB3Z{wQV@6O(GJu%lA5on6|$SE03@E4SD4E1a!F4hC@CiAoE@u)_R$MxzF3Ma{P(| zkq6#RfU%Z7dt6CCu8uyxIg^0D+v&6N|B5G(OZUn5Hu`L`GXXhn`h0a`f;_*i&&mxf zE=7)BoB+dQeQq#60ckn;&}QuFuLhEZ#;w9G8Illlt60JOL(G^w}mL0U7u7 z`I@+h#qG%Bof2^TqdxmsC!nELTYlO#0X{lyS$T@Z|Hu*g3F4-1%O7-Pf2`Z`f<_6# z2WZR6VJwbF{`Mgr!z0`B(wFhrlGK)y>f`Y&yDclfv3MkT>6Lh-{L+@YpN+@pL2dc# z(Rl0}*_M_2SX`4Fvs0Fv)0W?Dj7RdKwmfH5JVvf*%gT!^K1!~i7mvsL+VX^%@#t`} zExSyPN7UuEtenZ>tmHw%;>GRUmW>C*6=#+Tuv1-T4wJh#S9v>Euj{fb~2Jr}wXvfDq;$=v-W94BMKPES|iWfd~J6>cG zj}LY2IM`77JFp!qN3%FId60HI`b=ua1`TET+3k44w>TVL(2kYASv;Fu|2z&IwzlJ8 z591KHw;gx96^HWUvYfb`#l^`nr{l2oc00a*I1V?TwBvz$;^aMzcC5V5;_H-r9*2Zx z2JF8g4t?7g@VNzXm}6wX$_Xt_PyRMN4)>f4c=CieH1RcH(~+`Xm;ozaw0J)`qM!Jp zGYt4@Z5*Z*8E|D;95&U+dU6~ z<%<2W2#IaauXe^FyGMKOvndw+^4qg=UW@aT2QQAr(mw53Ykn+t4{6UMXU5|4nD$cN z#40Z;j~g9}#`D^9i(#=aTH2l`_K$_j`u40`+2T&+$rZ84IoO_c3uDpibbFqZ8H>?Z z+q3d$i(i$;$HZdYi}u_+G#2|mwdc`((!N#)R*r3Pu<|hbSm8K!;P2+*-!|#M{f%Q` zV$*?@e_K4QT%#-fM+dHN8jF<34qTuaD~|RKtlZqVgieoZjMu_$ZC^AFd@|%u zJECz=t0QM_luwWVtRKdBk6`o^?llI78ZT?a0b?F791kI#RY1(UF@C zk?nTx$YuScA6Xq)dCEik27BQV>J4m@5sunE-qm1trLyX z`i^|OVKj2zbY!#dQAqvPk(GB{e8GI~c@%!tq|6Sh?KAP0V|z zL}BfyPTXc}6#kvki3^8EVcMKdtUT}HFJ`S?QRuy<6DL+ip>SI#o?jS+qOEpBnmB_%69ysln0qB-J($cqZ4no6OVjTBi1mF!X7;%R_=Il zCG)g)QJ8IR#MfI!VT7X*cWV-bT5ls(UU~5;^Tv;n2#GV|uP-BEpJv2C^^q_rFk

G2$LaBC&0Z5i1|Pc$xXuHu2N{WyD?AN1}F#5f?3w6z+@> zD_6a^o4NkaNSGWjVykJ9Xne|uE5=3Q>188U9((aS^OJ#**ziog?;VMmAB?!HDiQ-V zI-)gCC$4#MC~=>BjsqDFS^8joBk>3--(YSLL?zANw=PkN0)`TnfHy11kN3Bm69x*>0KA~NB@yu{Ejqk#T zCdqPXUATT!IOZ30;if~wQBl=}Eq@J%Ti-4mQ5UWp;#^V|j-z9`NPGy#v}s*C&AH8!Fu0kUu=U+A ze0DJ5fU9BH>1D#HXTy~DoGXupAu!g2hwcqSgB~V4eR~-8=b1=d5vJVeykmJ7!g`zV z$$!Jpc(4iI{xb{*N15=OsbR{W&JD+fA#{!jxBXuj8ZI*7ZUe)xceM$-^$Jstbq=iz zga2L=PA&|?*JCDJkQs)p7fiS=DGcIa=fTloaC~gS6 zd96(tI_Y-h9j0Np)S)XM>==g0rd|1Tn=s{b=d0Rb(DLZY_Zoy@M?hD8_B9l}qPp_C zx1q}U&flJf%DlKMH@F{)*`-~%`SnmF^z6#5&xa~6JR2Mj#m*63xzqko^qkmL>hMsQ z&+5wN8$*>lo~>7g3Xi%g+bs;0=PSFi)7(&epswsPJyiMS*=>9%vd(s8j}f70dA%!p z4hqHY2VL2#cc^mEvsYCpOh3zKQ7F!7nX+eAC`Ra*vPW{L^3=0iOsH^1OxYzQ6jQBC z*~vE)fi9+O?;5IH_VPPhDE2e+$9Vp{CsMT?mrLn)3IjA^0)Pl;7VA!Lq+h`T4aFxle1#_s@mk+gek;b}R&o zx0~{reIbb7Z_0;ugy7=|Q{K5D1oJPM^12lv2)|>>ix!07#S>GWJtqV+-kI`*X(90W zVah|th2TyTGydg&AsE%#jEe?_z_z0qr}hfL88b5uuM9ySdo%VZ41uAi8CztAU{|0S z8zhAwFWQV7M~9$6iW$ETl78fv@jdSlM3kBF8Rrl@>1oDf9fENK&3HvuY4>+Co@p3@ z;}gyJe|jOPo@FM#Uxz^FUo+0o3c<=1W*qV*7*U(d*#1p09+Pb6NiaqoHe-#u!RU6@ zj2~YKmfw@4{WHPHePG7hjs)Y|3p4(EPcUYEGUHL(g5j#wjjPuMiniU@ z^PgZeH15Vmvx70;vKwno35KV0H-0cW7-xOD@!_Gts0{7KD}D_|gZOSdp)MG6(zaP6WZGy*Y0@5QH5j<~)8^5Tb0% zxoA@muDF`B&#EAl`I~d=MM3xwZqD^{gD@h|oOewRLhDR(o;E%R^NP&5Y=pE^W6r*V zg0Q8ZIqUWgLhvwizE>H9lVi5)>oNc3ngl}Qa--CiM zY`eMK_mTeXH|KfIL6~~NoNKIuV0g)#{kjI>-`nP_Z5RaWC+2*$br9CRHRmPGg5dGp zocm}7VOL`d4*DF3U|kDt`8p7XJ6Q15`ar~*TJWOVfjDbx!F87dk?L;2KBoh56&Bp+ za3HcHE%+1%;&yinp0yEK-B+g!CU?aMA>i)9y~D+ zkH=YX=*U2n&#>U;gXQ1zEckRE`F^Pd&!`T>qjeUXUL1(x9Tseq9fc!f_m9VacBJ18{hr zCBOb70KQ8tdD+AOtX(JVjtqe54omJZH~=&ETgrY1pxH@F9$78zUb1B0;sCt3ZOL!4 z0+9Q}l9wb0;PhKd&WZ^@;CD;b4GF-y##X%FCjch8R@~1e08=_xv9(PAG)%4dde;Ed z*jn*K!vNfHvtsB4APQFes#yTGMp()HVfhaE6%wM zTcE7t1`n7xtqD`mN_R$NdByliOA%`yd( z(9)XMb_cc^SaWI=(8Gu*`+;D zm2S-!TLC8utohd_fPIxUcl_y(iG8ej=LdgzKgODKUic$+v^D>D;E$D4ta<(oe`wFK zW?b+``9f>HdE6g|R$23J`~A^vi>$xXAH#QB^R^BCxOv2yd#vz>&pB&;_pd+xxNgl; z{`AM22i9yiRoZ=N%}2)gW639LE*j8h+=i#! z@k7xD8x{pLHt)3IEvNm^^q>t#9QH%{DI31Repr6lhRe73;maKx{=C``QBP%ii~TVB zoedkz^F#f28(uua4<1cy*>!>+e%H0-JtO>Zu7fSd4e~=5Q(L~)%MaDIwp?22hiz`Q z{Ir_hesK<^1HnsoQrIEiKib1Rok+oqaP0RwdJiA zerPq+mII9a&|{1(A8zM|zo*)Ad`s!a99zEF$WJ`Jww(3d7kyXT^4)j7*tJEr`^*;& z_So{Xd%lP~YRh%kd@<>qEx$YKi}TlQ`PZYqX#dcbzwYrx_Dkv4HedYx$(A+N`3gVS zj)yJvg@v{qH~8CE{C{>lVx})v7};^dNxpb)F8?0s3wuZTey}fUz3g~+A788uvSZC^ zU%ZO8;~_=9a7eM^Z<+Fajve<;^2MrBJN^*mi)VFq{7aB8tOwZf3ol=k{?CppoP4ox zydB@S^u?VScAVSA7e@2#_=OaC1HUfzobtC1dRf`?;h8>I=4{VClYDT~$DUV>^g)|Ydo~{IgYYQd%m0L1N~n1oS5W;utD~`C&~xE{%+3>LDJqtd!FazgR3*` zS=-46+W**de@h?uEVt(e#y+UrV9(tReDLQ^d#08?IC8+Ats48_<4Jp-{@okhF5C0Z zciu?4W6$N!yfO5NJ)gVhja6^$+4q_^u6(oSMQ6RysIddLIO+|@Rt|E1*c+Mc9r(sp zZ;Ui?;E=W6SZnRT%a?fLs*3~b&i6(GKL_snhc|4)9QfJ;&p zfwy>goS!IvPxZo!nT{M7C;jfgU@ug@zZ- zy^;QZ^u(jDj(q5ar}&JVxZOifv})l|D{fzs?iCg*dV6GEaG~(20ls?TLA*PJC>pCsyT3dy_n|tISFAuqTf9bmA4i zdE(jtCw|x46OaGr#C}zt_%PmyM;3ab;U7+XGQ$(C=gWHCJ>~aJC(e%agw;AHUKk+# z*zUwnJUkJw&xsu!JQ01|iTj#+%KQFKyu-*7xi_8or@kl39yxKajwgD)a^g`9JTc(2 z6CeHJf#F)t+~SP~#%eor!eb9i(Rb#lw>>b+$eGVw^1wWEXVyREfkh6^oN~|u%RQZW z#x4)>s5 zG}M_#_45!fp)>ER@xalk&itd;1IOk#vv;-!jxTiPKFRXA%9+$=EAX? z-7!2~mRseH0ckG0exW;h=DYB{IqoQ{aAEyv?#S)s!l7f`kuu1I`wVlJ`vxw&=vQ|H zOmyK3weE16>B0?5-C^~&3p?ky!)Tcc=cTwqcfAWwjB!VU9WJ~h*c~7Cxp2L=JL->1 zyUy;odclPQtlV+zrVCefamUU_E4T4^5na22s3x(tykRO>fp+^PP@Ux)0G<^c0-FmSGHp}e2#SGq|I)4 z(A|~$uX4lbOjn+_&`q9)cjbL^+_0$Hl^;!Y!=%2htUcBZ{fD@+!!S1#jCSSjzq%oM ziYxc2b%V>Ft~|5E4ILM_^0sU@XsvYRtI2M7ywR1vM!VtEE?4dp?1oJTUD?;$4RcPp z%K3D|(95no(9#XXcU<{TV>d)Tk^Z)GgWX$KzSzPIy5C&+Z9_N6e=PqG`5Vi3kY!kw zg{&j-$Q9BCOIwgOS=xqdgJoNgZL(||(g&8lK>EbeH%K2@`U>eYOWz^;z_KrpePY=+ z$Ud^{D`cNp_8oEzSdN9pjgd9_rV+%RPEXNvh%vp{- za?V-KJ>(i-xfUST1k1Gn zxkgy7705Nia_vB_A(m?ia!s*ZTaasv>^$TiDy z?aF(B?kv|b=`Y zEMp5Y##qK0WX!RQJ;)ej8Hc0fh@5Q5))ZsBP2$$#7aoa zWQm=S7|Ie$Au*LDwnAboORR;&T$b1iiNP$f7!s3NVlyO0v&3ph%w~z*kQmMq%ONqH zCALFiJWH&Xd9Ei*?1$t4mRtbI2`sq*k|S7h1te#%AeLMN$w@4^36i5&a+N&4xq zvgAfcj%3M|ketbqJ0UrgC6_{SDobvKcNRDR7)sURc zlDi=}oF$h-a=JW!;wTTFYD|_|6H;@s)Si$Ul%*Dh)TAu6DWpbasZ}90 zD@*MPsbN`aSx8OGQrkjmT$Wl_yw$QFC+#6MFiR~Asfk%?V@Qq6QY%AhW|rC+QbV)U z(vX^(rM8CD*z&uBJ*4Jlsl6dJI7=-KsmWPtb4ZQOQmaF1c9z;5Qp2;<@{pRIrM8FE z_$;+Pq~>R-{ULJzmbn0APQWrZfXoqC<_eHG1Iye2GKXN9OF-rnEOQIU9D`-90hx2K z%sn7;5SF@_d&s%iIh9N6}fwSzUKs z6crP(0}E_yML|$tA5cxM3CvcL3ejI2uQayY|<9Q025m=dF+OFy?^mxxb?d; z%*^+kz1QLlX3k>4narHcxZWD(tQMTv%-JnC!)=ByZ;8O_--I77PJS9b(wN^`ah&Y0$`8Js!I*)uqUnzLwdCN*c%;EZa{ zs==AnoLz%6tU1dDXIgW%4bHgctQ(wp&Dl3N1DmsOa3(fqJ&dR}=*_@q&GqgEN z2WM(?whqqN=Byo@xy{)-ID?zBcyJ~+XY=5UZqDk#ncbY-gEPE2%LiwAbG8r8_~xu1 zocYb!KbQfSSwJuoFtdSRMqp+I!OXzS4uTninI!}>1v6U+W(;Q55X>CR>>-#zm{~+H zlQ6T1U`AnP6~WBH%r1f%hM8r+p_iF$1TzjZ>j-8ZX7&-xK+G&8n2DI#NH8NYvyxzD zVrD1748_b+f|-h$tpqa`GiwQEE@t);%wWtcCYZ^X*$lr2%gkzmnT?s<@N-CJmJ`f$ z%xou^@t9dpF!M39pI`=LW*Dw%+`V#o0+x2g$*-%3ubU;78lIq%xo^QCWo2T1v5J{ zy9;J`W|kMs^vrB8nDLoeA8D#Ev%g>lXl8-2^x3}%RCmKe+w z&1^B4F`8LpFmp7s$6y9&W|6^6(#$4<8Ks$3!t<kMX| zX7(A(K+P;Pn2DO%XfPu+v(jK@YG$Xw4Asn1gPE$Ctp+nzGi&ANa4j=?W$sYR%wmI? zteMRQGg>pN4Q94xb{oua%`7*V>6+PYFyl3|-eBfyX1~D<*vx{1nXs7+2Qy;w3AY3@ zV>3GrX2@oi9L$u>Y&n=Qn^|)(b2hW*U6>o7r?Qqc*eZU}kM**TD?i%(8=- zwwY}QGj22M4rbnF_8rW?%`7~aiJRGYFe5j!@?d6eX6IaYZ8J*`X6k0P9?aOytUZ{y zb6pkjDAzW#_+Tb)X7j;}-puNQnZ23a2Qz##%MWJyoO3G%Gk!Dc4`%*m_8;s3%q}3< z37FkLup=>6Aj~cz*h!e(M6jbUyNY0E z!T0@}gB^z1Wdu77v)c%E9A?)M>^#U<-yG~f%q}F@iJ09;up=?M5;zhMncYdSLovIQ zV5eesE5VM%>{{T#KV)_|A2z$KV8>;4UBS-F?7o5>nAwE|J2A5x3wC5? zR~GEd%E#*#!nWL9-hSc7$eE80-wq?l9OPnq6YBQ#8B9V8>{7 zjls^*>>h(1q}fFVJ4v&f40e=eR~hUq&F(VTVVYfLu+ucV&0xoAcAde_)9gNj9jMub z20Kx+8x3}(?00SqcBW=`8thQbE;ag%tYdbo!H(7JT7#Xd*}VokShI@_cCuzS8|-M! zt~S`&n%!-%!!^6yV5e(#yTOjv?0SQpui5l?mF0En_YIW(>A;9V8?BC z-NDY=?7o8?xY>mVJ8`oc4|e2cS03!l&F(zdp_^TLuv0g?^+8V?9J{z*x{R9ez4OwyZvCtZ+88`&fo0*gA9Pl0tA@=lMM(m0wyaE zWCl!jAjlAyEJ2VdFxi42V_>odLFT|@4}uJW$sz=q1d~k&G72WE5M&lib|J_xm@Gq( zX)xJ_Amd=N4ngL@WFLYIgvmnS6Rl^m5kW@6WF>;kgvm|>848o72r?BWTM=X|Ox7aE zT$t=dkijrnj3AR?vKc`}!(=sr%!bKs1Q`yK<$&K>&wU=gF35P8tVfXfFxihF17flu zK_VIWgIjAcMkQ?b;xdVzMbgM#W@R zg3OA^t^^qtlVu4qEhgI%WL!+vCCI#(>`Rb=F&8jb%NAtXOtvk^xS6b5ka;uNw;%&& zvT#8r&Sc|)jGW2J1(`XMoeMH_CQBD&>P)sS$k>^zU68pm*}EWvXR>%fCeLK^f{dQY z>IIoSlidq4d?w2mWcp0DFUa_rtY47%Gugi&18A~|>CDG+D?X6KS%MK}OPKC4$0PvY|mn)MQ12 z%qV>{KK>Q2>jG~7!y_hJ8e~jO)-=eRn(S$iK{Z*_Ad_mcsX<27WL1OAs>!Yf8CH{J z4Kl4J+ZtqCP1ZHYyqfH5kbyN>Sn>&tOg1*i$eOHdkeM~vS-w9sGFjRnQ){xdLB`f( zZG+6M$=(JTT$9BOGPx$38)S4%RyWA(n(S_n;Wb&_Ak%BIy+Ov;WPO9ougU%f8DNtI z4l==a?taXsNHreYSgKe_dK_=T|vxAJb$!Z6gZIj&>bK19b~#qwmZmpo2++` z`8L__AOmi);6WzbWW(V^H8xrCATw^V<3WbpWXXd}xyhCX8FQ004>IQ_dk(+7vB{zb znRJs)4>IcX;I9ZW>n6J%WY|rXJ;=11Y5K?dGr;e$-P$;Jm6d6Sh7 zGV>-oA7toFmOjYTn{0iMu{T-!AaifB_dy2VWbx^nKWei1K}O$X^@Gel^UZQWhTmlQ zgG|54_6He%ll2cW|0eq%bO1~jAm{{`Za~lxFkOM5Ghn&{L5IL}34%_6=@tYX1JgAK zItQkE5Ofes7a`~*m~KMQQ7~PFptE4Q3qgm$bQyw9gXuN|9S75O2s#g@`w(;>Ocx^P zM3`E;9-9n;kbIy z3l?<3*vnlKbi_7E50G}A>3I%%ex7If51 zS1stQneH0Dhc`7{wxH8yx@|$n&2-&@&YS7J1syokg$p`yrW+S@HY;BK+^>bI)SDe7<2?pS1{-dn(koGAv9gWpi}6+w_O}`3{BTC=p35vVbDP| zT||8E%}h5j=qQ@5V$fMM-Nm58Xu6C+r_pp9gN~!=ItHCb(|rs&kfsY6bRtbRlApuP zOjk1KOq%Xw(4jP4%Aiwex|Ko4(sV6@&ZX&I1|3Y(#SA)`rkfdbG)-4C=xmZBy(s8# znl5M1=``KWpyO$}o6Qi^ zQ`0pKI;W<48gx)i7d0rrnQm&(Q8iuFptEYat3ij=bXkK=EA!C{gO01|x(1zB(|rv( zu%-(ebYe|6Ht5Kjt}Na>UQg2tgAT3f(gvMc)2$6Uwx(+vbZ$-eHt67*E^g4tHQn5x zqiedlL1))=cY_YE>GB4hUeoOjI=Sr`JUFD#&Y`V)qhuL(QgHE&Q zHpiTFbJKMWI?ty29CV;f7dq%fn{G7uljf!?9dxEmcRJ`$n=WWDpSgVt z(^U^T>!!ONbl6RoJ?ONXZhO#iH(mFj^KQEDK?mM+;e$@R>Ba{gdDE2-I`gJGA9UzV zmp0n@;+4Fbl2VI2g_1H(QD7zl=i5HJx88zEpM z7*;~SOfc+(fT3Vm3IS8WuoVKvf?+KL%mu?<2p9~mR=I4zWblq#%kuk8OT%gim<@*A zK)$-AVL1d$2g7y<7!QW^z|ZrRhW!vQAPfs4U_ux+1oQBgh7}PoBMdttU`QC21pBR) zhAj~=CJbvLU``nJM8KdhEQ)|hVb~M_qr$K%0%nC_R|E_T!?FmN7KUv>AFY*PT?EVv z!@dX@7>0!rFfj}pBVc40Rz|?gFzk$gp@e((fZ<_S9s$$Cuss6ChhcpL%n!r<2pAxS1rjhp3>ze1gcw#xzzi|$ zkbog#SRw&a#IQw}C$uuGk$^d3*dqah#IQ&LCW&E_1dI~HDhZe+hFuacObp8;V44`V zNx(QUtdoFwV%R4E1I4gV0w#)KqXdi;!%7L5DTbXAFjNdnC19!;whD8$)`qnbFjowF zC19`^7E8cnF>IEA(PCIF0kg%hTLOj)eWP;%ri)>_1dJCrY3BsY7sGxD7%+wf6EI;6 z8zx}H7*F0Yk^IbO>~} zHf)`Mv13>}vAs+i!`=xPJch*+FnJ7{Ct&m#R!_j}G3=gz;bT}n0n^8@eFDahVf_Tm zAJ6>ltZ3e#jbQ-=OdxXNX9bKPb8rusL53X^FoX~fLUbNMR*X}7?x4MG%{?XfN^A4M*;K5u#W-;l3^hQOeDib3K&U- zl@u_O3_B@cC>fSgz*I79rGT+ySW5wO2_Dm#0fWh~m;xq~VKc#FYGYVU0kg@ln*xTD zVL36sZfn?10prQAo&x5RVLt^7D8qsZm{5id6)>U|1 z!U~vJhK&_4vJ5LLU}hP1R>06QEUkd4W!PE)W6Q9%0_K)sZv_l4!{Q21Ehn0ppAJ|BQh7yzCGwiW|L1tKF0h7$I$;h9yGpsW9KJ5&{+hbIq{V z_z!thsn>p48TMVkz%wkofQe_=cmX5Nu<`t`hCLXYUub!nWf(9G4cjna92(YPz&teU!+?QkScvSCpD=91fRSie zi2*awuoDA@qG2fpOhv<1q?h%CVJ!yCMZ;c%yZ(e>F$PRV!)6Q^jfT}2FdGfKF<>|v zmSezlG;GI!@n~3&0rSzY9|H!YVL=8=NW+E<7?Fk*889OaJ2GHM8kS_hlr(I~fH7%U zlL2$muqOisrD0J9OiIJ13>cM$RT(fV4ZAX6SQ?gPz_c`M%YbodSeF6w(y%WB2Bu+Q z224!D#taylhLssGGYva4U}zeaX28@mY|VhNX;_;9bJMUl0|uvIaRy9I!{!VaorcvJ zFgp#qGhlccmS@29G;B|}Bu^UFXTbdQ7hjhO7@&p)8Zbc(8#G{q8dhk)3^nY~fFWvF zq5)Hs-=j;xNqf?;Mg!)kVUGq3Qo|w*n52eH8Zb%?t2AJi8g^;GFf}aGfN5&jrUB#B zuucQ!sbQZ63{=BH4Vb8gjT$gg4J$QZrW$r?z)&?T)qtt$-anlbj8$*`;G|%#`j`DD z1%uUht~n`~tbTgNNx^6}tX9En^}E?81;f>_Tm{qB^&UPc7_aVq=SjhQ^}5SX3I?oU z!3riUpU)G55o=hnf*EVrv4SCMSh9jCYuK`aF>6?}f;ns0vw}fuShRvkYuL1cQEOPW z>Rr8qVb=;rmbPy3dXHr-3sQdVc!Y{u3_N{Caz)Q3P!GBPBuyzG=7w*@8g28K8yn@MV*t~+#YgoO4*=yLng5hgezJlp%*uH}CYgoU6 z`Rj^L{;Sh>b}%ep!2~vJV8IABtYE7f!4x)ZVZj(StYN_%Htb=+AT}&w z!6Y_pVtw#W2g52B%woeX)_rGX7?!b~JTJqrjWz6&41avdKU#NX1{}}7^})3nhJ~!s z6*CMQS$Eu-VOYs(abE^|+P{^4Aj7bfwIDLwJN>s{EF0FcerS|o*vq=;@eIRa7EETt zW>)(S8UCp3-|Evf!?2q*|CtQKa@OA548wNTm&F+_zws}f(L2MipH*>ShG9Xg{_qUL zhSt+#GYl(QLndb!cC;4F%rGoz?VX=t*wXssxeUXa)_*HA40~EvY{)PyYE{{qVc67a zwkyN1ss*#!u&XuXwG6|u*4#HUyd(2ZZGJbyu&#CJXog{53kJ4fVe6FdG7KAA<$lUA ztZd!&M}}c%tImHJhNUf-+J>zy7~6)mEtuPey)78rhQ%$I+=k697~O`|EtuVg-7Og2 zhUG1o-iGZh7~h8VEtuba^^@OqUA>Nm1umH2h7B$l;f571nBj&UE*Rp5B`%oahAl1_ zs&C;4f|X$ z&_=bfqnD~Z`FBtiTl`ok2}44clKZ{tfG2F#r8+yPq^|e<$Mt5KaK&1`v(_ z;|dVY0OJl24gup55KaN(77&gB;~Ego0plJJ4g%vM5KaQ)CJ>GS<0=r&0^=?a4g=#d z5KaT*HV}>j<2n$|1LHmr4g}*u5KaW+Mi7n!<4O?D1mjK+4h7><5KaZ-RuGN_<602T z1>;^24hG|55Kac;W)O}BeqM0@uAPm$K{y;5e^;W(h*J_X;vvk+{kHP)VO@=@M>u^jIDU-lM>v06bl+EMyNv6(<}00C-PO2(gd@nff`l`O+{Bl{A!J-a!YO3jLc%d* zTtmV+WZXl-L1bJ+!bxP@M8Z*ITt&iJWZXr2 z<3bWnB;!UBjwIts63!&!P7)3!<5Ch%CF52SjwQJ3UkK-taW4r6lW{Q#CzEkA2}hH0 zH3?^vaW@HvlW{o-r;~9z3CELhJqhQNaX$$MlyN}`CzNqR2}hK1MG0q=aYqScm2puCCzWwi2}hN2RS9R6aaRe46;t)kgwx8nt%T#sxUPir z%DAtD1IxIugcHlSv4kVbxUz&Z%eb?IL(90dgi{NS#HYfsWn5drxn_ z<9ZX$H{*U24mjh2Q_X!m-}sM&BhI+uRQ_N$1?!Gp;(}tTXO9;jl9N3yr%_I1G);P&f^Z+fXh;T-duRJ0g zlEx(|oRY>ZDIAl=HK{GtyYoID5e`b@q7+U_^&&PwC16b?({vJ_5B}&QRkH6%JA35*1ES;}#W;QNI7bEu5pqJt`ce#ziWeq{dAu9HqupDx9UpT`C-= z#$_s;rp9e59H+*0Dx9areJUKN#)T@JsK$*d9I3{YDx9gtohlrvtXAFQo zS{2S!<6adGR^wt7PFDB&{7vC#HLh0SY&Gsy;czuBS6$euhjF_K$E$I@3g@eFzX}Je zalvZqGd+wORybmfD^@sTjXPF2WQ|K!?fUXM-#8>3v!1r)kZ{f#_pETxdi%&j!bxk~ zw8BwqT(!bk%lGF)!eMJ%w!&#^+_u7TYh1U&d28Ia!hvgCxWb8R+_=J#Yh1a)nQPp+ z!l7$iy27bz+`5``xQB7=3g@nI?+OR6aq$W#uW|DVN3U`93TLlz_X>xvarp|TuW|bd z$FFhy3g@q1Ngvd6XFp?Hz`_Y^+`z&SY+S*@8Eo9a!Xa#2!on$R+`_^!Y+S>_Ic(g+ z!a;0Y#KK8z+{D6BOh4v;a26YPv2Yk0m$7gf8@I7=92?iMa2^}?v2Y+87qW078#l6W zBpX+a4H+OvT!UL*RpUf8~3tsFdG-Ma55V=vv4#USF><78+WsC zI2)I8<({ve$VS}^Qv%M8`rgPUK{td za9|r3ws2w_H@0wO8&|e)W*c|5aA+Hsws30u!FjI;$F^~83+J{k$bUsRxQ&ZjIJu3R zTR6Int6Mm`jk{YoyxCX1ES%oP?JXSN#`P_n-)_F;Wu4oor*VPnWRsr84K5tv#uYA{ z;l>><9OA|$E}Y`VEiN46#x*XSLuYc z_s*i1gyY<^JG>;E=f-`mf2Q{|E_C5UH*R#{NH?x@;Y>H~bm34pE_LBl_loT=3dg!} ztqbS6ajy#pyK%7#C%bX83rD+gwF_svakmSHyK%V-r@L{x3&*>0y$k2NalZ=(ym7(n zfggGrH@tAf8&|w=#v6CMaL5~%yl~1Jx4dx7`{cbZ2ZhEN4;^? z3unD?*9(WeaoG!}y?2b;FC6#AbuXOvexmb!-FQEb+i1W3eK6C1-?v|HMW$c6dcT&{ z$@G-d_p4vSOn3QlpISYZ>3fds)9uYO{jc|_R2y!$WS`!CBGVJc@6&UgGTkAyPpNL1 zzNO1PHSU?|pBwE{`P@uzue?vk3o||V8cJ@-Oh0fTP1vg`Q!@Q~YOlJ?%=ES{dv*7`O!sTNSAQ?ebe$@DwSQ@* z&nmxHV^?Luui2}%>oYy(_#R!qIn&MF-J@@}XZoVud$ewMrr%z=N2wPwJ$b?&)qXY8 zEz^5+<{P|@u6y+Q+nIi+@g7ZhFVmB%>`|+unQmTwkFNYY(-)q(M@PTT^nv5MHShaO zk9v2vy8M*s2D^9b#@{o2`m){n^6yOVny_1oPiDGTdbhfj&T`eRyLHpqS^lZi^X@K9xhV^u(k?Z-EzAEc-KBHy z&hmx{yY#|+S$-zHOZ}>4`P#0#^gzulUhgjbTszAns_fFTdRbQaUFy^*%Ris7OXZqo zdC_s}K#MH5dDj}$Hp^vpTMu-|;`^}mL+32#Ot9uZ&Euu5mYG?8ql-B+Iu6cZ?dJoI;cSlgakIwS6T|4!`_$=35x>F;j@ciR< zs_M)v&q?jn7jv`Ru**)3Uzp|J8tqigrCFX^d8dx8%Xh7U&#u2!6AQC_-#uITIhE~K%5BxA-r3GL zWvdzt$o6mFY|*E$Tip+vT@y(Vt_pz3$m98Zs%{^+s*cCDXJ0Uf~ukn4Rs+ zC%5SC1=&7PcZ;?y&i1&wwy6H{Y+rZz7QMNe`<>jZCpTpK;bWWi_2z89^~Pr9?Z|fL zEt~cC?ri@wf3pU>knMgWHtU>MvwdE{W{p3X?OE+NtK8e!zOBw?&3Tvi@s7>9;UgaB z(#=}(X|@mkw@G(=mF@OlZPJ==v;Eb9O}g)RwsSXa(#Bu1{mE)`*}IO`(kc?agI0svr!u_&vDH!HmdT~Io|u) zMy>3DfBWh4%6l{ie(Uo()-1>0uX|n{TID!v=JR^1U5}f-r{-P)1BMbd|uCH<}j~#UYF+O`04YW*U+LIfBE|c{h7>h=Z`n2 zN1q%YeQ|@{8<6AnYc{Ci&>SD0wn3Xm=J@gc8+7xy9KYUUgCVP zWzWuW^&2+m{rNfGP-cVbEza?szpmHXWjS8-;d))QI>*=SU$4RIb3AF~di}U5$7QCh zSL^LL9?*x9@~#~J*=@Zl?$2>{ll2<&a*jW*x?aD&p5r#xu2;J^bNt#_-0pCWYyGrN zH-5nLythunKF)E)J?r${=Q*CfY@HrEmg93LuG5n#hzdLrV_FkRqx{0-_a9ys~bzG~|O}Q@LaIN0HHP<65t<{}(<@&cP)@sPTx$b!C zT77(fF8ua2s#-nQRo+^oF_G)J+t%pIhjV?_!ZoViAlG@L)@Xd=T>d|-;rIAl*M4%1 z9&DNGrFFS|+gx98*BX8LWUfmtTcgUIbN$hY)f&<**AIWaT1TGA^^$|DbxTgJ%Wht+ zWI?X;=dIRDCAmI4Y_-bu%JqYJtJSSvu4lJhtqp^6UFxCLI(2xiJKwgN-y?Iq|Dx5J zIX>4n|FcS8PtNtw&sXW*8M!|8>MHe`lk0{XR_TQWJkP9Ey5Kop_uy4(yFAxVXRXrw z)wzD5tHq_+zC`*`Mp_AFousmwA6)T&WSS z=hD|+sRM^{y<*x*U3fUxXZByI7Vq=AdaTssqq*MRY^9ETmg`F&T&c^y&UMc9E7j(^ zT)%kEN=-eU>uY~mp~JuAI`P2@UGitH5AI!|$N$ZB#T6?wwp5;bPgexLjSY&-0B(mTT6{ zc`osCy?tArUwLl1%G{mjtH&)@?fdeaomj5os(E(DX!$&StPNzH{ zE?B0yPv!ZBCzk2;9(m5GvrPYF<$2p3%XDjgp3l5=nOYU+`SJgjYCtLvkIz!A>XYZM zUth}q+dNm=xKyQw<~coQsqPw?=Y2z#s`c1Bm(5wKeiQTDvh`9enacfQsot2G=PxTR z)gN>7e8&Y#ReoWf^Z#6;I!p4r<&!1qu_DhWURt6tYx3|SEz!CSyw2%Mba-=~5ASefi}%`JFsJ`@wTM z`d*&D*!!IR{V2~jt$0pXewOEMlb%!6ukyUO*K=y|ZJxjC`kZoq+y^8{aDFj^|(CW!!s7E&sF)}SAVf4R>=3syBBN84f%ec++uC7nD2s8i*@k!e6KjR zNT1!E?=Rn2q+jpLclj-gbb7UXx0=65m(|GknBj|5u~xqK=PgpzI{E&$?IP7{knj5* zTBH_@^WEdNMe5Qt-*Ycoq}&$ye*5o*>fI*aXMes>!=K2vUR}t3EZ_O-7iwPDd@r84 zP|LgL`@Mk+^?YW&&&^z@ow@mr77O)aVZQTfEY!h7zMs8up^o(8@y=bSqy6&fX*{bh z2Ic$ykDk@H!}8(eJgeiQ@;zncv-))$uW$0R`g2mgf9?IO{+*WZ8@fHKle6;O?6GHc z%KUuyz5iLAwkY2#%Rj5qOY{By8PDqUmH9s7_yV22mg_mPK&7A0cLy)fXVti1W!_`iJbX**vl ze$Dr>+VeI4&wQ7?ZN8@bo9}xsny-hK>zofut4xFcIH_jf^HlEI0%uj9r!#LX@R%Fs>Gz5SUR7qE zzPP=>2Y#8WLw6VW#}DRe=Y0h}Z{J)kt6JbYSIpJq>IH5*X|DQ30bJO*>iKYihjpE+ z7WE6fsPSB>QGxeXo~xUi6!_z-=jy!X1^&16T>ajvz~z3JqYv8^_`Y}MXm5uCH`y^q zOF9?0$D%nJ)2+aRM$b|HGh9c}9JR_W@a8Ay=z;tKAF4Y?R~Hxf+dJpzM6$rAT{cIb z^e*sKCuVDRe;)6v*_uDNz>gf5t^UIc+-c)%bsSy5TyM5wJl8j5wyv36;Dy<<_4l*_ zZ*4VOM`jiHpk`~syaIoI^K6Y>Sl~a;o2_S-6!_dfW~uIq0$=;_ELB*;Yq;wTxQ%%z4m2+uSm?)oNo$TvExi- z|4_i!)lBK90@uE0rpo?S;77~N)Q5i-xNWJKTJ~>&pE@=}iBg5mePf2|mM(O9^9)^d zR-uQ?o1u@&6nfmS8CrUNp=adIP{GB8Uf5=aYF=LGm9=K*%&Q8$@s=5SqkN%vUNA$` zt}pZpe@<7&n+tv5lj*8>TcO{1X}W&6v(O)|nXdJf3jO)C=}J~9^f&#cOAi$K$L`a0 zYRy9b+H|`1*DCa1)uwA$okE|ucDfohDDQ}oXKLjU{H6b)Nc z2;X9gsxK|{&(o&p#}$SCzTXthTT|$-x=&HF4Tb)s=@gy1xzO)bo1%5w3jOA_Q`Fgo ze)X&=x^Qoy_x^7(keotqdv~(3UMckYU6Xa?fkH1^GFdMkD)jtulU49ep{FJ$tNeR~ z9^G-WUjDGq0~_%1PYRv9XR@yOqR`ppChLW-3*EWYWaWHU=+?(3>GI=+ZuG_^?fkjW z+B`{5{a)xw^Cqdx--W($*d(p_kM|>Yl3Jcp_wGAUi*G7& z&!;DtEdx~78!bDwDxyaX_IZ<1x7Ww?+6V#$Q&wF@+j;qLD z@0_6F4;A^X#S?TxJ)UpO1Z{6v+=^}T$X}og!7P)TO@j5Y}$hZGCPNRnu`GSwe>FN>+(i+t#~HQKt>+4bKc1^MC92`Y1tk_p>8l|Q; z7W?>|QQBLv*!zc!Qq|jwJtKRRmfltD>{g?6)xE`jNTW2mO0h4yd6Z66EB3c#M=85T zv3LA7Qb(iM<31XxM;|VBm;EEPtzNOKtQ@IZA1U^klSgXmqs4x=*GQe#tk}!Cj#N&I zVy7C9)CaAL-Kg?N)oWkutF9iYH64om-Dx9rW#?jV`)-5=K2_`yZ;jCR-HY9J+X%JD zEOy0bM`&A4v40yeLf01*<5e4>Va3HB-)@9{OcuMtLnG9@cd>83ZG<-UD`pQoLRSqc z_P)P{tItqg=cmK<>4;*t2V(W`m}1|&cDNRfFZNH z#ly&}6no;BVLEebvD+07Q>PupzOKVCZQWJuuj>xe#rulA^3GxE`C_s2FCC^muN1r5 ze?xV}fnxvn#ZYoW#oqneQ0;r0*Rz3-zgz5vvxX}BgJPE*G*r8f7W<8!Lv`tAJWunX zdiu*^x2ir=TaFdG+zmrj=KEs5f6h>~KVIxvKM&E0pNswE`$P24Z^f>#XNVs8tJohe z9ir*~7JJ_KA^PfMu{$P*sPbtguFz?S`khhYj~fipYiE~u&OJj^u55{)EH^}5E-3L; zrG{wb#U+04>%sc{vJy`{I9PFIiCb8mw>bEU|AIth*|eI8}DA@++6P%5Q_Tv1*Bre>g~gJy_yp`v$3oO5AnD zAoZzT;%g=ilIxWCaC(qRH7N1eE`wC7QHdKg8l=9DmAKS>gS4|*i8o(4NdL7caqg*u z^kAD3-}3E1CE9a6hX!gxhZ0ZTGEo2PRN}_-2kQ2xN_^_@f$G+s`{fSQyq+b_YBNyp zXP5Z;S_5@)euS`B_4JDKn+ZkxYi#7v^8DgUylyZPkl#q^wZTJlsIvEKh-{3 z;yUm5)l;9Ac-qpw8umqrzf1Jh@~=x=vq4`S_?FMh<$ZPhhZ2AKRUcjOQ;F~0*hiIq zE%AWCebnra5+7>ON4bCVyf^mI*#AnL^Gk27ES2!~J-zkHX$hY_p|`$1Bf(yvH#v%g z7u?fZ70M?3!^vKH@PdS^9qgr+7biSmPA}zLmhh`ty)^8KgfFStOY^Tz_=$6SX-kEK z7k-e|q3aX=ZdqE#Zc4aPDy)i>TaxA5q_a5eeaa*QTQa$0aH>ET}2{-vQshPDC9=A8C6?GDRV?t8f>nD6c=cHbHgnzG;)CZ3y zJf>7q-!@J7wSx)$*_`W{o6za46Rww?&_(Td-8B;`|75~D&rRsIjtT$uL5Zq#N%+3y zC5R0Y&PtW2VUL6tH!RWPnF)Vfu0-u~62AOcvAX0Z{Me>qJyVqM;337zOC-FlWwA=q z3IB9sv3mDO_~u`WG@yUN?e-RF$RJ+Ngd&X?n(*#UMH)RK;a~45(%8}5u2hl6k4w1q z!9q=($aT*t)TAj1Z^`1%=?NdJ!N+GMT<+XLO_2~WB^Pt{*bcGv~|aO<-4@!3f~_HU+MIydR3U(M8-^ONp7BU95ZN_uLK zO!d7q>DART^;Ef}_n(=mMpq^M;o+XTr+m^sE$XRDuS@!jqMrKehNQ2m(^DVboMf)s zQ@%Cnhdz5o^Y2K)oq0wB@8{mYBpb#G&?XG(XKZIX1EZr$~D zvm|_g?%LfV>FY~(*NoOl-|^PdDrlGV{R^H}qbHM&yr*@2$D|w7dRl*VPP*y&PwU`Q zNw+!LO^doGow2f;QazLI)~lNy%T7A8Q8!(mmvr8h-Sk^Q(#79ArI(76PHlclGm=U7 z8TyoZ_DZ^ctEW_>Z_5HG}sM#+jeb((A)!~(- z|NSdNi+MNuC?+>{rE%DclLTxi~q;h zXQL<8;g_UOzw$|4`a54|$DYuufAV#==?V4!hvyse1Yg%luW9*&zAcsV^c$bhoYPY7 z|4Vy4en!gA>}jvkXQ$k3e0yyylXA6=?bZFflq=lbURPY0^64kqk&8|F+t=DDd0EN_ zXSUNVSERh*nRYsSRmxKzXs1EtQ%;}NPL-}pxxa^9Tx2OEYMQt_mu9WwE+D4TtrMz%W8+~+NioRwW4Y@z%&X2XxT@P^oYuf0Y>M39I zeQWhn%KvO_t?O&2d}MfQz4&m->)W(eX1$chR&1>c8gd=Kx6+12Dc9NGO06GDx%{M7 z`m1Tme|B!Anaxu^RH>C}v`TqtsaE=^4cC9LrFyqdxy_uGy1GNkcW1TKwvH*EQKO~W zc1iieb6V<;r&3<~UJFg?p7M|-Ep$)Ml-rfG&}&&K-&L=Lp3Y7AluKLa)Pj`X{=B(n z6{Wm*U2|1Qq@3vATnADqH*DHm-Fl~dWrgNC(Ua?|yX>9?&ZUpnA1_1Tf~drcqH z8M{)RRpBv>*^_d|A0O3a`}sWYcvQ1qNy-^>8>!~! zDPNt<-@i=x-5QNl<5MDHS!w??qJh3UC+)>;8>my+wAUpO&s0vk)5Udl`2MuZepW}d9!Pu3 znmSruJ?*FZ*3l(O`+~>nsCTWjw_aUGUp|tH?NZJ{# zA6EayJpRoO>+8qTUj6GsYSb+4R(l`Pn&xT$H~t}A+$!y7J3d6tH|>UZKSa(b?H~WE ztp}e>d*W-gH8Ugasxxcr-%e@Hy|wj3*R=aqtF3L_(##`j>&hN!?|Y|~55C zXQh2sK`q^zoA%P$wKO)L$GxDIzAa4q+oPenC20>|8Jd?&`_^8eztd^I_(-UEAMSre zXhpxYOCOU;4@`UhMydT^mi~jKbwhc-n@eYnNW1uYsl%wWFZ!vb){jYhrEBWU@o9YT zHPwD%+Mhj9Q>!MY-Rt(6I%Qhgm;PNt&1a;&>ZKZ5I4kXXQ)}qAIcXn#s)p*$=kY4n z(Bx-%zfY^7FBb8B9ICE+m!$o`yz1(=jIW#Q>UwuP%RP}-@Rt7+U@ zyuZIy)tm36J$Y|cUGgrUhY3~H@_nwaV^vN5FzpBLuBvyAroI2a`*q2uX*YfCel`D` z&)}5)g@k7&K~D6U}bcQe%uJ znrNcgTw;tdF406|5)za6J*T>67)4?L@qtckI_yGxWCeM?<=59h2<5 z*_SceFlNW|=NPS^kDb@E$7t*N+WE4?fmy9G1}=AJ1_V)T2lww`K6blwaCGC zo_TMyW=pg4Ptv2c>|v-^>u7D+2s_{NeU!E>-Ol6RiqiItvh$}_M`>s8u=AGVqcmll zotJis(prqSb5l(hj7K|Pu)m9T$7DOdxVDQnH`C6?XLZq5XW99oZe6s;ve6!;i^gZ5 z{vUMKKFfuijh(e?ciZ^`cX!szv+ewk-kr5pd3Jucxw96ZZ|7fp(n(7zM89n7q-D;x z^Op-cY4eNhJhERWZPg+>FA3?SZM36Zr#ospopzq{Oh;{RG4y{=NA1`WJMS~NqxQ|c zsCSc&+E2^vyy3SUG@q4r?tH0(*6@Bizp%7}7Wn}BHNAt@?IAmV&C)^BO6|PO_wBVI zWp=*m&Gy=uay!3%e|v4}Iy)bCXM1f{g`My2*j_8zVCU_BX{RmTXy>cnX{W8K247h_ zt!%TMkD1y|+pq<87TZpHbeo-9Znf2(eB93OJ=|8?@uZ!9yP>W2;?s6M_s#_X6x}OQg2{B|Gn#AE_O9#m>uZ0EaHTC~dJcHUsD zMO*W!ozH4-(N=zL=Lc@I(uz;m@qY4F+Wb>?eotvDZRVHI`{Y(y=2vze71K%^{Wa|F z_mJOD*h*ohO)DYR2zTzmHmIKmK6n z=Qg#_&R)0k-g8=LM{gjWwZQMEz#rH`d!`2V_(gNA@;CI)6V0{zez)_}^P6i0f1;f! z&9zC2gD-8+TpMI?@Z(=K(|VX3yu;3BT613qU+8S6`IsI2y|iZ96@LehXx22Rv$>QMq_czgs+co5Yd1SNIQt-6`>czD-&Yl`y%g=>NAC*PO1q+dy~DMc-5fm2FI*eY z!@;*7Z>+WM>EJiEG}dm$JGeE!v34v0?M-g1ZBKOY_k$a2_gYcjsYcp(&B4b$-AL<} z?BI_qY^3@1bMSKm8fho{J9wwYjkM=d9DMe-4(@sxu@L|7&YEMpe@COcrY6a6A z{LsUp8k-KiXNPLOISxLkN2vBeu7fXEL$!zRcJO^4hG>&!Ik@^rh}L$F1DokWv`cvo zeotbEwlm+sUonShg@q1&{ge7y@A(cMv#q}N`vM2gEvS!uk`BJLZ+&gaJq~`letoUK z!@--J4%SRA2T$J~ti4n0;P)>I)|M?nIRk?=+r19F$1zwlE_d*r-_*mp*uiJLP)~EN zbntD9>uE{%JNU`r^|YGR4&I<;J81Mi~@)D~624kiX_v5&w`qXM<_)ee5=Zvond z&7_|IZTJ@OJsg1N*J$6g0PW?+9K3Ch04?VU2Oq5lXc13APapbghn|KWHu`J!XB>FX ziN6-L1MN)o*G}$q@PTH3ZPoJ*Ui67s>;0mGKfcwhoqx%}Kgl<1Wv@86PhYc^{Hg=r zUpH%)Uvu!xQ-0dRZ#eKiYCo;-TMqulLO<;?ckqh?{Is=u9K3O3KaIWZ;Qh||YTxXG z9X;=>t={k8mBqeVj{^?=&M;r?i-QjSLvvrv^}d5QyX>R2J&bYls*iT?0|%dTpN}^4 zh=W&*_R&H#>Ims?8kQS>+9r4Xa2!Pn4LV> z{||QB-^qt;`<>k#=;ZhH{hj?1Z;Mzp$?@PF{ZKXEvjalOM?WnO%x>;(JCvvsvw&JbLp_?ECgkKAHW* z=5}=A{?`q5y_1vgo_B-gcX9F`LP1A4d8=oCWOHMjeAwV0+4o(Y+z+;?Gv*qb)XT}o{rCg>Ji*DAKJ)|2NObaNy8OTnCpr12 z?|#oxnUmkj`kuX|IeACrdlsMUXrXi|mKdPCjw(1vY66+BN9{dw(qQ|Mo3QxYLR6 zD1Xbgjz>Rt|CWVJgg!nv&+eJzWIOpo3(m3cr#t!M4bHLAIZn=Ze9d0Zg}#P-&062>ndjvF$9~1a@|}FljWevUz{&3_Im3<@I=Lh24C^@`{dM3=R=&W= zAD#9kyHVuiFDPHKj73hquj({=?jF=T;WP_&IQh9_r`X+2Cw^aZioNSXKh-+=Bgj*rl+ebC7l@A-^fe8|aHPW+6qQYSC{^;1^5#>v;0f6C64 zIeB%rPg#7qlW#lx30v{7lRusN3HyAV6Z;uIVVx?R{H4vu*}_UEf0Z3)2RAtRo1Y(J z;Ty>wkFo4WUXe%sR{#zU1Up{)gG?FFX0e+YYfmUUBjV z`yOK2t4_ZB)cef!nv**hzR&pUPCl>E`|Qs*oP6eU?=kk4lTRJ`9=nG-`PhpG*{oJUf+uLl;aVJkZvzI;k3H*?KFFW?BlecTKm-&2-a$nrTdVb;L zzYpKTvQIeq`OCXm`APV<`*yRpPdV}3mEG+6X(!*xIcs&s$sfQgjMBbByMK9$6`jTS zDtn7<{o2V>y1vCeJO}^u{+sOAZ=5`A#+xkiTPLqEyvfooV4Obk2Ag*g{has)+jz;z zpZMf;w(qi&ug-s+UH;C=^MYSzp;zJmo_dY-`W|+g`Wl`3f6agYn<)6*lWv=y%V{Z1rzw z--MUh(>I;`i<+0%!QY*H*V>oZw|_uyu`e;xEho=E^dhq;E*v{VKNlbP^mFVxvx~PL@EkJ+ zxcF~pce18|F8+~oC+iyI;!j5GWVU)PUi|V7Ha6JB$E5FIGwZu}^wnpXE5yZ(tDa@0 zp)US;yJy*!Fc*Jz&ok`B1}?sI;xp`>hT#8oJ3HRU#k-VmXXhHb_@A-c*^l8ae)Q1O zOl|7oTXUXf^&?z-zUgV!ycz1V=_%H+xr;ZoKE>i%xcH?{pJaVny7+4aPqIO+Tzpmi zCs~HY#qWIj2{xg%i+39E1j}yY;x%U)_&lT-nA}cXZ*qgxgq2C-Ak~#@2Rr@ytD2*}5(+9yM_*tBi8-Uuw3ns%RJA zyLJoP7~|rrV}V^=eDtA5*(0$o-YVx&wy~RwUobw(s=B-Q&g#vqvWJToC2eNw;#@rW z(@kt`PZ#b3ZDOVIF8*QgCbqg4%6qDstw?a;_s7+2NpI-=>?6#c=;Gfx9%1v6Tzq@e zN7!tui|4(xkxgeV-gD$eHc@l&U%#tjqx!h`8!M{V;A9tfwXI^weO&W7i^_>H*btWAN7Z#lAz{RB*(xs1JA=;Eq*8CyTk#dmDE zm*vifp8DL&dM`lvCzdjEk&Ew|zm$Cn%nn=1wk>q=&}Wyhf<-R=)}SRU`5v_Mo5d{1 z?&6IXFJ_+s_cUM3wm6`-UBzsc6Z#%i%zC*{&o5m}DR%Ks8@t#+V3%P|R=U{5oy#0- z+!Bn>H|(s{QWtM?;~sV%SlHzr_Vm3j{?61zEN_{MH>zC7;+DJkw4+6=2Ka)xh`oLv z>Yu!TIaj#&@CEZ(@=6!4dUhUDSGoAbZwlF7V9yqXY{~ubC!-2j-_@|k`}3Ld0OY+r zm%Rm?^jjXYKj^~WuX(KZL+Fp3IqWB3!lv2mxf0mjr?c41QWxJJJd3qo>FoT($=|_0Akt^stL>E1kh&*1;YROlRkSos{XU zVmsY!#l^clJ(l&^igM15VHbg$n~q^?wz>FcBko{HkGXj8iqY(AAig}rRz2?G z3xCdF-JXEIjm}`70?$rMXO1V)?^PpN>!&d8KOVvM1MLAL*j-P?5GMZxEZi6aMq&Kvw@b*kkvB z>>1$wxdYhX=V6bVQrUUnxldErk{4V&q<#u(@gl}ks*Sw@oZ;xtM!tmc`C>nI3HbWu zzHI5s&|jOrtl2AQ*PY4id0?;7K5Wn~=<$HYz69QPi?MmHqJ8m<1-$0s$7fmDBf#Ic zCb90XL+>XO**m}i4HDUyH(=j`d$Wtc(!~jE(VOr?yLz#}w=ge#AI~-be{UbpI&;{= zq@L_mVBhjMHefgAheJKsG2k*|50<&d#UD%T&aMLY&+Wz*?uDH^5z9<(ySU$(uIwRT z`|z%;={^@v85YAH1x{NQ%{ss1;!EC$V$TDsf9%2%_q+I;ox89-z%Md8vjOkA_|NM* zu|vSHBOTeu11=up*O46u4$?ZXaR(u1UVC;D=-l3pO?uD8E52^a&H$f}Xv;F+$2b`o z$<6}Lt!Trh9>P4vTeGi#jefDPDTgs1$5_~Dpe?%`7pg)#0r5$MEBC zH)iXAeST}if{$Umb!)_y0<&@&vKrvL>IQ7)aoG1KVeAZWUA-`t@d?JUEtI_j+;vX~ z>-8zhd%iw<0{Gd*VAk|A=+_d=Rsw$>Q;*dEeI5#8Gd_3m2KxiqabW8|0$9Hz4IT;JR6VTBn}D`sc*&*8RZO2HmuF z`U>;oE5BOr2Y%76#(D*KvFvB-u(Mcys6SbE0Dbd*wATL`^*?>hIvZ$7`@wn`81>p! zYnOBIV;!$pR{;AzeA)U9aG2?mweL4BJ~sb?bt5qI%z0}K@UCIsSkupAT)y$ObvtlT z=d)IyZ((Qa&sZk{SNMKueF^wb;VEmq3z%Qdp0H*CD@J@_eHHk~Tc26$U&MSH^{I6l z@UhC{)?L6S&Bv^Pmt6em`5##)0iQW{#QGd?NBW0W!)2^vb|1E85XKy`ZY8XG&w7I} z;Gnhtci<~}*SZGy%=ve$XMj(S+GmZv0=awlS{DHyi``@058Uzyw}xHCcnEsSIuW>G z(Hqvsfe&AJ&3X-3ddI8Q#P6}L+V_fe32=G$m#yysU7KFChW>zcRPYPdvB0_Z=d6za zb1&_%ehthV`>eI&HRx;qcI!;w@VKX~JAtW>K56|CXbpM7+Vi@LcXvK!T>$Lx-B#-^ zVDme-SZjcx2R2(1euSOHZ?Y}`{<`H6>&w9JLN{7(0Kar?uy(rv|97RrIvcoe{CewC zz?Tm`Y&{QryjQuk^-s|AwleE@;K~MTtmVK(i%YB@0Pp(#L96f2Sf5UOz^VZUy??)T z9x$QzD(iM&hsRe~&jK4ay3ZQ^i;J6=OH^PJWu zHCU&OyvI5i*fzSzdJph-^E~Tz;K%3YT2BC<+CAGE_$%hss=KYdfp-+;SZ4scjLNpI z1>Wj9)w&1xao}X@72spvj<+`b4fDv`W34t|TJ>n_Y+#Ff(yi-&-`_FZx(B$sdz$qk zuq1epHT0&7Pq~z0O#pV?-_JS;_~+(6)_Z}699HX7z{+vGtsek$dd6F?1AB({ur~hP z#SK@wT6+UOI1ptW53JnU$?5=R7q_=Q0*svyX?+WLvzNts8u(6w7S=z24}IU%+UyVX z_xp{ly@72WZ(tn*ytE|5S^#`uQa$TKzTF(HF9#*Ws0b?_6 zCN=mIemUT$q%Ocgd#@(-2OeK|A?Z%wlx}B}@_?5woJd*@oVV$C(gxtIF&`%F1g@xm zFliq!^xeHlp8+eJZzNp;wvK-}=?~x&S9T-?--2GYJ(<)B_|k+eNwL7Bh8vUm0QbEA zaMCbf>e7;=iNN<0S0&vI9C3YVQW5aUjC+!n0iWADJE;`-YPYFLRlwbwMkhTE++TlC z(sRH=PHWQZz@t~XChY@$Iw3OY5b(tNjgyW6&m;yUodCX@aWnBN;D_DLCVmS%UjJa? zcfgZZb|hW{o_+t}#GfcV9#$1awIaBi=-Up1$<*8kUe&ifQjFbkF*NT-SJga{5)3{I0mf4lZaYkzDXtY z%cWc7$xvsbIf_h5B1jRKPeA(ZK&1SsQ?2YUr<5&J++!5*zvJmGcew zmMYg+l70dEseo{q*Bo#+kxl&dx&{TLP~N7J3<=mksS%=3Lu5l}g_PkJLgh8{e@(Ab zUw@7g0*5K4{;~>6zzyQCNzxF2clj!&6o0)@CS5PX{{YI>MD0x&Yn;7|WH{-%7yXJXb!P`(7To` z96`Z0+{0F139%uwdeo3v%cr^d7I^sjC?UJ47RLfs*78kv^F4xqsGLg)X@s!)P3N7p zY!ABG_9LLzPE|r4Aij=WKC9(>$<24w!{?`j7^v7TQ3_NiTYJjQ*BEiSyjDucYT}ED z?O4m_gJ2W&X*AE&!e7{y+LX+uDcMR>8hf=D_#PAS$JvkB8NON(O_Znjt5V_2cT0 zAzmbk30=8FMN_*$OxUU=s$vKz?T6?Fsye6v$!^$M8PuR_prSOA`A~5K7#g=nJk%|c zNwIb7XAOcjeFO{i3dM;NW(`Dl0UbevG_nzH0`MI12&u{lf`K?q%8%-ZY6=lE5^(h# zi3q96NP@m1ID){PZKPMWk%;#kG)1aPI)R>Tq<6M-uWad_JP2qaTLyu-^yfbtc@?xtANw%ttBG5(0RwF2m=D3oQ zbv28C$9?Kltve;USS9{;bX9K#*Hcs+h{mbL#B?2%pE}k`or%i~9Nw9Q} z?G`t;#{|Sj&z>_oJ32daYVL&G*;zB^P0OAzD>Ex6cXsxFSgeA&>;DJoEW2+crW{fdBrdy=3&=P43wA|OKbt~g!i?OF=xp9`2i18L<2a9pO#TXhx zWQN7q)zZeeP!MA*#x52!G(LTLVOsX=eha%RdFcp?GV>8YRSOC;XJ=(ob(MnL8MCve zS+a66^Oeby=b?rPlMAV#f9<5Mf7jTVb7s%5h|9d$QWh=O`lb(^Jhbnqfs->v_wS#Q zks(UYqSEs-r{xxrzPu`tF}Z(g>L{gF7K!MeIHCX0j6oUtb#g{_;k>-bcf`dM70Gy8 z#)!#jxl<=(%$b*;l|5lV|NhFbsc5bcLlUy)6il9;nN>I^zhH9r*ti5GuU~FqdiMNL znNw$GE7aC*@o4O{IrE6lMeR~&X3j{Ldg##|X?dd-w zdqK{e{6b3|ChwXgbnD$+nJOxhDk@j2tWhZ$qb8^J9h5dYJw+LlojW6^uwb&_A24jR zrN0Gs9}_1mKeku*o|caJ*)y{<3$i;|#zWs--NPd~ZgN8ORE)8#97}%o{M-VJFiZDt zJ-Ws9nrMlhm6bP-Wub=IMbWe3Ko{oBn>7_U9r4ri=Ep@BG7EduV=VTT}V_Y#< z$23dyjA;up^QT95w?q%`VTqnTdrovgVSa8FSZ3yC7UaSZqNh)nLpr)3TOZnpo0eIa z=}k}1i_V%e8*ekuDr9q}Pxl@~b&MjNjG|EQfDwiHu+>G`G@$ezmffanGCRK@TkpKO zbggdFQictHJ*K3m4^LM_%WBgy1`Qi9I<0SdZOpK~!v+mY_4I+T9#4;o!2+K%b)hr} zx0Uo2R-*TRol(#?eZc6UDZ@s|;`90=qcR&F5Sm+*?L9PgFCvUn7$7yj|D5dU=|ksC z%blK^ov(NeRbjrhLv7HVDU*i|%D}kmKTvO?5aBkYZru~=3<;v$HHUY~ESy&$$|VOt zLtRF>Yv8GX-e}R(y#8|vq!GJI>DjHjcZbUMcn<*La1S;`!LUuVbR_#8B^*8G1q+&F zNs-RpG9rIYR(3%F263nVzyMJCCcxij(rkgbh+J=feJl)(Q+(_B4fQt!_=e$cyGClb zv5DGLjZm8zo2xAiZQ#|h`cQ7+z1SI%kFqL zGxdNw&YM@b8h3)5*;{}&bDa|1%u)i{Gc9}Sycuxw)90Y6BAhvOD%_FYT0LgwoGfoL z6FzH3w$z8t@zNZ`OG z2C;Z+g)s5ZN#*GaI`_&=Q4SzZBoN|o%bS8QmFsTT0m__=Qyy+U`s1+<9~I!vgrJ-6 zf!p~8BZBS*$ivOI8FU?acOs%#G6CFtuOVEA?+dR)uiyu_^PNV71*bgR^1cOKN8X>r zKr#B^=A)?ESm^IhRT+c7O5BG#?RP|Y_eTl(BN?4d{ei#fL_0{OLAS|kWilv(-9nJ= z4z|3FFBi+hS?)wHz6iv5mwTicmiLIGazk-aJE+{~+vI)XYfvnRcOOU=2i+?3mN%t^ zL3A6*!(U|{dC9lQ`x)}Qy4TYV>uvJ#yyP|Vl9zs)JYPS9axdcChdVgzHhIO6NA08f zh2wO$caoGxqp|8f+*MctCT~5j@X`zYrR8o1^`YBmkPLIMK`HYpz#Sy?8ivZgh6d#b zA}omSf|KM?|4^CU^45kMlot@^KHT!$v>UzSP0F=f?s!6DofZ@AT@#|cOC;K)P~X=c zCNYl|dLrCf(j$!U!rt>Nd1dm?;y~xC9xts&85O_V`2B&Vm2XyP zg&+ufr%jSZ#!{&Pb>Bk(JgS zxRF>(AcQ-Fx6w3GYY(H+RMemBQ$J_~)E-9Vb~>Uq5g{Y2f$qqXjnZ5h2K(9!bRRM5n}M63Zm6m$*gZvl3sI zxL4vqiAN;TluqTGlXywu4-$Wt_`5^{41@UnB{q^6FOi;PQ2Ho|SrW7kMyE9r@nzKam{mrn@0TSN%^ zTtW!DT}6oU))B&9s|jJJj}yY4cM!tPUm-+03?`i54<>}%PLihQeCBT)Ema5;t7R6z%=_uwKokCwU5Fwv90UhB}8!OQlYx;+$ z`ljy7F|0UJV=i8qnvmK%b>~$j;MOmH-fEqinA&4SLMnxOuE<~EbFDZ+1F*R?RyLrmE+>{z~^NQTBrhJZ2P;)iWbS=bWyk;?O zyB6Ye?r8TF*3>oTAu@L+a&JcNucoMp#%m!);=OisaB6IBZ&B{R)WN7jUlAUXT6RTQ z6uaW*tIDDoS34|H6a254{fo^>E#5`^y{SV}o2Ql|wBYKDMQ>bFgZ3d@e#IbYpKBJM zeOJ^)jjoskP372-)<~w?kap&1w-tk1hW%hP_+L(LYP_t31RbFgno1ruk*G7@sf&IB z=Ss8RwGcxX*FixU1i8Q9W^z8^KI0IIHzBId=a&@{}rPrXMga0 ze)P=?HA@vflE%8|Ba=#hPpS8VTIcRXFT|b(dW844dm8B3DfTqn02up|vvTig7)lmu z@}Y@JEQ&pQ8j>i%?6VRH*wZi?P`jtWf;8i7h>?35&QorEPeUZdy7x3p5!EqkRG``P zy%1%}MWoL#M9Dn~zNTYH@D+O!{Af?YY)CgZ#ie#nf_b;#ckf9s(|l69C&8ResU_w! zR6wN3{5cSN5~x;&NV9nDiNDCa+SvC&4_ABzpEFn4>7KXHSCpJf$}AKZ87m$RKkd)uyQ=L(G3t zYJ@11_9Xb4NEtrlwy`H+5yGfbUw;?4{Jr-inBON3&z=M`J(tIx1ieuvT|cR^5VM(P zG3-fjSAmxD*pom)p#i-LgS@I>K!VR;s@PzE{4J*hsPiE}U5VN#${KM6NmF1Twj->f zfCVW*G|8*?pFvO~@_EX%n#d(M>)}S`gY=wv6VBjZN_*%Gg6i1%PZ3c%W)egw+lAHSw`>KbY`Jy8v5iNIb+n}Rb`9cfsggc?ec{cg~- ztR#o3BM_s6bOv!A9L0hwow&eTh^wCdDAEIvqf(|Xl(LktXOR+z6g(0)=&?m2*Fwbm znrM4Z1FBy`mF{Jjh6Jc8mDA`9k{eMa^$=+RJdKfLy6&f{RFt>7hF2%OLsWUXu0j$ep$TNHVzY6L|M?eVH2KevnU3?L)mD<%hWwpeOyI zeM3)uu$RCpwh%PZpVc?6n}V*O0~&@mb_gWfN7zE~?xP_BcrH&s$*OXPJB6?@PCTL~ z*e8PH2o8u~20?S=F)9m-swqGM=!yTxYNU9MAcXL|o|NHqlt zabgDm0j)DtypRJ>jMJzTn5rpouTGe&DL@TJN>DWg*62h?H3c@~RFw?UzyUqpR84_H zf>>y;rhu-SaRg^Y{5(@N1+MBuP&Eav>%`1z(wPOPs*ENe&7pz>aX8V{_G${~DqL9T zQI%US4bgLJ4FR`qMMTm=9Ao#k3zat2q^f>6A(ddTUYfm{0;F1_GOwtb0+V#2u$lt- zI+0gRfg?DP9anL<%fr25w{W3760dhkfmw8lUKX@R0lkL`LPQVg1s60F1?$~a&_r~X zUW`fVKHV~qKqvpGmJsgjR9icNx)bvbyXW(Vm+6x6w>H&TPWG+zl5SkdeQ`gxOAU2 z(HJ(}xWH=kw-^@;7S|YTdNIzk8iOsAA)YSA27?96jv?qyml<^FRyQ<+$R2HD*QWOE zgv~KT83U{W>P;6=AY_VcLn%UpjEe+oE=4S(%U#B+iUrgE|7;fx{mq#*D{p4eH6R9k*Uo?tpD@PG5=reg`ox%WM$6Ow-)_NJ7el>g!zAP zm&?DjrzLOdJZzKsC!4bL(SFJ?@1DtDr}mp znKn}Wi+fc>bp$V&ir9@t5@9Bs~ZYB0?Sy<37E`O#t2H<{|7Y?>jJsAdciAi$~sl2)pwjsJx6s;&UJFw55pfmiN1* zR$e`%x$9SfusaWe%6`a;cN>XUS~ z?slL$RIcaP3VHOmg8QJl(Lv~?E+q#Fp%ptl6G0XsF9b+sddvF^4AT(jKHT!$v>UzS z{}cNTs4lgKTPu1D?KAK`XkUQ$LC^iY4|-1Teb94t@53l8qc(<~lhb2@+B%TNYY(Gx zJ53s_J?Oc*e$PYyD~FzQN7g0_x!rD~>CaF1LFEo{6F^Z9?`hWaNZdP8O!T!YI!f|P z`$TwVa3cP8sT+Z^0?_dGglOU;gpCyCDMB=ev`)|CXwEZ0g=Bk#U=awHCZ6xLBLoxq zP)hG1F+pOA#59Q`B~FrCvy^^LeMfEu%@wmjF zCHlaKDZQb@NQvDg(v4Y4A0ctF#5oda9~7n2z8}IzB|ax{x5N)6o|bq;q7eg>^0ku~ zC$Yc8bcvY~Y5pMoKEQvEE=1E*4ak<0?B$i6tByp?6 zrzP%?xJ%+265p2iuEY-{ekAdP#4jbDmq@pNs9o12{v`2tiRA1lUF@R()|0fbYtT(3 z-CANhiBS?`B?@~7zu0#Hq`N#McdSHV|DeS_3?SVm>b%L@{m<|D>d!k@&Ji`jsk`^R~oyB_5G@OyVhtUrD?m@jHn>N&HnJZXyV|z7nw| zP|%?gBP5D_At=9tq`OEI;}!7j9CukRpTt!XACy=w zu|lF4*O2p=q<2VsLE;+{cS}4d@vuaCc0}c!ktp_|fW9ngdTvVTH4;@Cr=aOqmxT2E ziZD!KGl{Jv3V(ofdKO50Jtg***iT}r#NiS%B;F};l0>X6i-Ri|of&($l(t^@PE zsYg@Wm-b&{UK_ABXl-Tc_!@Iiy^Z6r(_(CmIcju`**dPqWFKE+nxKUGhniBuLW69E z%aLJQnhZf&_tGzFOd%(0OtBqG`h>=SgQfPgsh1-|?{1Q|E~t7)jmf(B!$%`>BbMA$ zQaYAj4qtrJFQs#Nr?MqC{UW~)FTSa&UDkD6-?=)f^i+7)@&sGGjWK11!jl!q41sJ5 zYGIA4j$VtJq+$O@P|U`nX35H-8k5p}eTV9_jeR1*LOZP6d%1O3Ky~*u^P4UHFzw;) z6&)&@g}!~cZR4~J0X8bRqFJmgJFdK&SJ^$+#a6~uCzP2}PlYGi-i}CD#w-38gA{XR zeCeU^wDrB#uDKAPbg1fG-hE@NZECaPo5qyG7nPJHH`N)7Ay-|WxbE;pLyEP;SfQ0J zLF#YeNozg~Ppq_7^jY_I_=WHQTTpeqioPZN*K1YD<$gAEH&zz3E~}ZjI-sgvX}^u_ zD{Skj)F_*uP3=7pIuE>N4tx(94Z3Cy3Rp`!L(J>U=&1noW&2XsjhG!Nl_RRwD5j{C zHObdg7Y|z-yS7d0rqqcmhigJg57z{3PAs*S#+SyeiLZ*^sBJh^b7ptjoLM;?)>hdnQd^~VFSo9@ zRwPy?Zs<`Jw^7L%loOUSKBr^JSGMi_hTA%qMy-h{L!O<<*S{z}RkOP|DK*75Bei|` z$<$$~8&Z`s?bn{HQA$3kQHoF0D6uSOZVvi2+5fURpoJ|XwTo>-$RWfp$~l4lJX~Yh zl-0y=8JqMj2PnlzF)4b=fy@5p%!u8W4gQdloR|~R%v>21F}m4%myH1(Dg)MD@L0xgv6xq27QcD__4!`u(!c{j-YR9T3Wy3FhT@+Hf45^1} zrWGTlh*F4iLdoG8TQO2r2A7=*4}*S2lmt|E*wB4_{c`keMW8?L0P`j@eeH8wFI3yJwuCZ@ARWq>URLzJ@t=B}BMN~H5&~9xT|r|h%ce<4UovkkDN+TOPH`8jq+T=l7%&(L!}Y)Y(1K<|f?_FvzxGPz3a zb-=d77HTv1c)VZSy2Ic(OgyCtWv-tuJv*!-rE;Yi7T9T6Y04VY=V=>a%OXsH z^uwY~%?58wU6*8QVH>>Ra81!tV3WRfV~6!=)nTE@&4j0|=uq-= zvu2^C7ZxjN50jt87+I56Q7OE9H{0d#Sa@0T^yKBK{J8RjvhTwWg`WzKTOVKAb6sF+ zY;{6K@AAZmKwGWPP1~sZ+wN5zDxYZ9#`e#>?c3qMg|o5`!>t<TbaZUUhB{C${T1lQ) z`rXZOW$?8an`d@M=X5CFYTKOJAr)SBLt<4AjGrUL$vOTx={e1ErsZ^pr%g#2ZtGau zc}-MV%v#;o9xskvzc)20bqRd!;hOcE{;9V$w6Hbscw6$d<~56Q{_1NpBaoI%-gX~+ zZ6ds~k}P~}lhMt{&yv42N5In>_t?nS>VDR*j6Ch3@bI;rs~VU7b1!T8k9yftHB;c5 z+@7|smu(?DEBV* zu+H`KwP%N|PpK$2!{#~;D@iFeex6ntyQU=do&T73HCOBYwU@1_tw*x}SR#CErJt<> zJS=(C3|ne-P}$%Oqix|f@~F2W25wA+hwW*rig-C2rj31b(P#>tyi2~xh3b#3wg3)gvI0gHTr(h8U`^}=@!*m(y!WA#^qI;F7sQB~S zY@%J5*pw@73YzIp5yhu1E~a}`y6@pbf8?81s&tRT*F<+Jd`(oaUx;axnQjD_=}x-o z4l_j>A{BEpBFC5?6QsdRe>{qconQf@C}As=5RJG1s-C)yZrNlJN%u(A z$0)UgNGef%oKj!M88{o8IM=I0QZEM1#wJdk%po#2)06xG=%Cz8PddUq+`NIgvF_ki z%66BV>Wa<{yxUFD-GIPCNUWe=hAD>x34uCkK*a*{J*gH!dQ!I#S>Q>%B1lha2dE)1 zYmO&*sZM*+x9Bt~te5pR(FM64e)`=8Xb*pL=ohqy-%4~*rlM{THD4gescv$WAn~de zJ$1Vvr@2W^%z+D$S0~4VtTza{Qa6gs_2`E)?(i~n znmfF>mM8cD;(-w(YBur*A0s}U-cGbX^e*Wih^Ct$l5U8<)r09Khq_56iy2GwZpyz| z(618x4$+Sax+VNZ@OwmW5%d6}KO}mqpjQxmh05Ee20`8@M88jU)oIdP@Q7OaDy5&J z{Cc`C?$s*w)y@>t!w5b_xdT}e5Up0BE+NA7q3-fPnBKGkCM8X1eas`pX{B`;&Xx;pES~q_^EX-dI1_vS=%wMO569x0v zsl7yz`L_{X*xnZKUeq#lu;)N~?+`RmEg>a-{Q1D%FB z>*-fTb~1mR?hs7k$ozGBfKGe(XAn*1A1P}7s32j&I{A_yVZu83sUTs(I(dmmGJo7F zLN5j2E>GY>f}O@y7}YnhRCd&zYGiWmtkT4dRRCA_JV&k^6TcW z(>sY4=C9K?h!*Cr(@k)nN;m(GCNilBMDK=iU|%=UZxSuczq6p*go1vL(z^(H2+9qv5~J2bPNdM={Ai9dgKSLm zTQ~+Uk`q+52}x^0qoc`lbfH-bDgWKK&i(s))ID3hZ{L(2PC7`{l*z!$~ z16I7zEsc<}K|~s&Jx4=?u+g1>Sd2>PNvE3^MVzDun4SaHPI3vPT$`I0a%~E# z41#1497TXPB~TGtT@(nz326kY(NYmlfwedhPq5w{Pl3nucmi3~tuA-*sOnZ)+KB^$ zNIdSA?P{nOdeTXOHM+zjo_5{F+!%R<5-31J20{p^!qDRgLXv}h>;xTgg8hh-0`w3C z6(^wjf;|~I#X-{U#A#4stBExoCx!J?ti(V+ffKUMI4MA{7DaCo*dQxFDSg7}i*kIM zR})RIZw2oYo@U%uUA?T*5rpS3NChti^tzAqt^?I&wl43ClLAzE?7AjJ+h7ye22U_S zn8(7}9|@R|&r21nz>X#lq%PDYz>DYyxrsJ7p&SBwI1RNDP=3_yGv^Hid}*CgyVJcR z((e_lcTfsF!c~P5g-~kw%Q(>y1R-FAlD0!hpE-ToR7ZjCCo-oKP&wYoZWW{K?T*io zcp4|96HsA@-|3*hG*Rm4WHd_Ze7i%GFUzDKqC!^$ML0>GlLA<-AwHd;ZrRPNucM46 zLhM*?Nu(qy)=2>=YqyXkm2|;LIqAt2_Sw605;G|Zzh5Dsd}Mco^vn__s+T8*r< z*#IgekfINGvObSSwiiZ!hr5{{AWAx%oenRDv(uv};)oTQMz}Mbug$c}JJYT@nNETW zDt*G^x=7M>oKQKz&mx#X;I4tU%iHP6N5x&znF%EGE^p>t9_Fi(!)rAChA7N%crI7E z%jLUBX_K$CDc$M9K%!U@7v@euZGB~$yRqaNh^HYn#g`;Br{UAQbe97XD21k;hKd8J z4oY=Uszao@WyDJv?s6c3#86=#FL_%z5YmQ`iLq9eT}HC;3yK;R+oLmNrBEd zF((qp#X>Um79EXol3CK4h*(GAynTK26yi|NGfoO@#|i&M5Q8dvuaAhPw||58Us@lX z$FLK;6rf6DPM~uIcg9HpsyxajMaQAVM33N!Fp9|a(vE>5Vz33gf^QCH~_ zJd*{@+_YeUatJ6BD)bK*MYJgi^F1w3#P6~H;i8CECElwZ5}qtFrxQ>)waLw^-FijY z+Z~@Ekrqa%6G5Ft5$$flLajYoA{AY`D55gSr$LDXi*S-WCj~Z%_;iB0Ww-H^4Q1Xy zadLg+E&;J*C3KK{3r+~#>7;-xVYetjs_ueVPc{_Q^emN#xh+npj)3yfQi*W2h!(4D zvM9*bmrC@S84M``stV#SINWs-OnRLZWeRf5#tE$uQ2!!*yJuOk9Fe462qTc`wM!+c z#KWQzBMDC9tX(R3tyg5m+NF{c(jFFqM-a&Lx=SU!;B>EoYnMt?@FSw&3<4_Hd#R*n z9p#m^cB!-#jil9q*H5Q+BTD+7oenSGQ@d0mj+P>m$NImh&9uvt$!m#AS!jNMLTeXF z6nPdW7D@!}LcJYc?dph1I3t)d2qg0^Z|2(7(RsqC!=D7pHPCHq z6Spqp8t5OaP3Y}F#OW^Q@76%Km2=x#>$Y zSOZajYA13~z^W57t0|znzJGfSWP!066|8kAa26-lIt2P4mTMq=Eis;ee9b>z18o(f zU;=^8`0uWPbXy-spbPjPt$}oD8MV?pYasWyxqS^p9YI6m_B9ao$pxJ5H4ufVpD`Y4 z#|tL-+CMGGE1?xQ^^X@M>S4NX<2i7v3CbKnKnpsIBLd>ozg>WU=b()6Tm<+H24y3# zh~Q{~ND&-CpbHyK&|8lsaLcWILqZf{sgC+;O$0nov1q|X2j%iU=&uMm{x02&+8LA% zFrWViet(_i^)ueNJ-Xq?6=?T=^Q!=ltEv@0@|)h18H-*s`VTfPC^7o$zisvxzl!dm z;3vz?=psVmcg@Bkk<{0d)Q&>>Z>bCPUqpvmD9SiTFm@DSDRzOLqEq@Wqzm<^COSx} zo?eUDB2t%7PlUzqu#-rnD7G_&BI(kFF0JSye#70GLY?ShEYc^{E%E^G2U65j^Yx+wL`B*Q4cx6qg~+-I5GvMd)>K3c zB37Z9T6K#81S$GKR9Glp@HO}3sI85VDC{SiQbny3C?pJG5`~NlM0JF0!D*Z?Dlm)^ zcN>GOkuC7go{-#m`H9wpTDKa~8VCKvzc2=Y7RI0$<2;1gQkxBj=wb{eYcv=alDa(* zOvMJHntLBT>)cs zF1>2H$Ps!}A6;@^o!W;tz(BariO%+dOHX+l(&B(3#`Lf zWPZf>9X{~27Gy2P5KW?0<1+O%!W2Q&r+UB*3J^m~j8@&N>ak)(8WX52)tIh>KH!Wo zIyFHT5~G7mlbn)8=-888=hS`6NL@yAJ+m-Y-Bs(Rj(2eA48o*U-N03&FgXvUduwB$ zkU_?y8W-ug=I9_)q_z|(dR1s#>E#F)qj#ZdtS|U$T~FP3qp%UxC^}SiQ-OLJvPAj* z4>5YxAykT}kZ^s*xq2(Z=#3)=JbG5$-{5)07qji+zng7Gkce9MEJFX`xmLVP#VD01 zM!0IMJJ;%J6grdhkZ4&SsvDX5Kb~+!eTB;x6Na%sC`Jz zu3{|Fh}Tyb!iYqEks#(XG35ys5%+g2B0)4z=*ewuf1P`44Z!&C&9A}^lB56>)OaJeasWrv=P&4ft4oM<`@jc<8(br_!>;}f|7Ht z2$Qm~Q;#YkRzU{55{M|$kij@pFHugh`lP3)$SU0}+%hQ}ZPA&<%E>^zXArZJnChS= ziqL1dg|%Vojk>e0tgz^E%%}hPSyx{=p`Y~X>a7+P%cRQaGptx7>l3t?-HiphqVLw# z*;0q8x`K`38@jB@6$GyT?`d1+V~jABT;E3d0o z_y)bMLcT6g+Jasmqi_KRqnLRN#@&jjjm{_>ok7m5V(q2d$8$8fE-@}Nmv~L8?n$=J zb_IDEjjJBrZ!=sqOMW(iFTF<>uOYuu{wjCM}?+UxsKKsM7nRN^&Cch z4$zf%8>=Wl_!50k=_TqBbM<0%pDn5?rW@}>eQuOX1UZfBe+7yZz54o}B_pXlI=`Gt zLkD-PGn1ZF)YkYsUE2YeVtW|p4aTaV&(JOg114MXYAE>uFVD+=^mi3`z6^ywo8^b7 z4RUB!BYECusUy&s{6Jq{lj+Ry+e9Xd^oEpYx10Vg-Y$` zy6_&O_&ECL8+~x=uOEw}?_%lSzEbisuzwbpZgj!>i!!kBbm3GXPLxcq=qj4FaGKXA z^~4(z>fROjZ@tBFh+Wuu8TnbTH*g9g7O&^fzqMF9a7gA~UZ=HC zx1s+%Ut$Zw9Y*i>W3{DQj`E;8ka$1Vz2;?p%YEi z*TgLhNOw5<28Y~hT4r4SZ@*{D^G&zEcrfaS+E2dyCE44-)%`l$ZA0jP{Y$%=LBF^) zihJk!5hu|N`W@*1{5!j%P{8fw&V)_458T2R#}Hh-`8I)P?BDRszm2aZ0FPjF5#s8W zmk$ct*gZ#-P2a`X6fvX&;xpr1i<8QAA8~>Btq3K^!<|+F+FPCt@;*cTNFK4fa9N*6#l~Gm~Tp0Rl)h z;y~y%K?46HXj#MlM+rafw8k4&mT&9R- zdp4s!_T9K2H%Yq3DDx89c+9T|$|LR8mxwgyS)jf&k7pKa?#Hdq)h;9L|B5ld%D5F9 zx@*N6eV!Q8eU@J&;y{OyV}up-ch6d`f5ZW5%Ht#u@%d-Q42y8b{7af2u5o?Z57%)1 z$7j}fq{hJ;@nI~k3!u49`8~-o#2QQU`>+I-zqd5M_ex-SuLRwXnQ!#<3cktEyJe$k z{q8l#Su-NPFJ4j+BRV^KwgYd@x=cFg_6XU$T_Q{hQ;J zR3Wh-JpVJlzSvT1E8=u!^0_`(Zh$yS94Af}XNxzB%ft=hJtEJqtZ%FMnz%>YCms+( z;!ol)A|6J)+Cb2JU5g#LQ0)AfkuSvfl{ed)p z!pr62PqbM6kn~T|ew-v|FDWLAnPMMtxX92SEPt)&jzh*@P}2UexJ}$G?h|pjXUg%U z!}5t@P&Dtj!roH4lQ=-UQsgg-=s#avA>K}6dG8Y+7he?L5I-d0Z^rRK`ER82lz&3{ zSLpywNi1K4MESDP7f4r^t|Q%4`eNz!(w(IHNM9~JQhKcPROzdwZ;-xOdWE!!r-k<1 zLmlVw+%G<){HICeza;%P>35|+lKxWqTWS7Yl*{YGK1Y@iD~TOM#$9E8mY6GEBQ6o| z5VweYmy>>PiJyz#i>Jk6IDxR-g(6?;q`p|}DDwSI+DD65i8qML#Wf_>$GzfX;x=)Y z_yLLfK9xQo{hjo2>0hMdu#EIe*akj|!gxHQ7#al$azDPS>#5UX@ZWK+NMdUv!{fub7k6`CZ?(~00 z{8;4gBx&c{?c`DMlz3W<<@W^g;*jdh8XMhc)n~CPS1NIE*Own9_z&=o#<3+HZ9MN2dK;I<2S==J-6yFp% zo&^1W6gi#*by=~2*jVKF63jQ(3t*P?C^1KzEM6_n5f_LHMRWatdR9x{CEhD?{0h!* zt7xttpkI@IOElLJuzw=`x%iFvo%n-zT;xMC*6$Y!i{|hnx$BU)K@?x@BP2@lxy#BvPOc&dWUBw@j|hxSW|2+wiG!43;nx`{lqK8;o@jNBl_qOyod6%s(prEdDCS6}9<=#S&s^ zkplzKzn0iQY%Fr1Am(2xb`yJv95{&iSBg2}WO1%IPrO-NEOMkF`fn5;7oQfli?4_u zh@XfYe2D%b@wj+OQ#bM$|kpmjB{M8}{ zD572@a)2W0$HX_qcSH_Y#QYN?2P~pa5*v%nMGj!Z{6XRi@uM-!FOT^XU zI`Lj{v&aFGIKLOg*Th}o9`OV5bMXuDJMpl1Ts$TE@eGIc2gG7xNwJbxRjeb{7n_O~ zi5#$r^>q>Zivz`RVvcx~c(up@p6I_wTq|x69~K`MpA)xwX+i7$vd#GT@sB5os0ycTSJb6shk&tdt4)My7kyxzoZq9HCr&HBOV-_ZD>9Q%1# zK2^_YHt>2C^?b+U$jwK8v-|wdJl}(ErFw>u&?8k(y(W#D1|vS<@#z}{gDJ*t|JP4R zY23JRFqoQ>l4>3Pe0=(C>?Fc1U#da=`1H%R_ztDT_!rL)lw3UDQ({pdJ-uwjJlWs#Z+za&SjN;oE)7S9`n{#4h#M_ooJqa3t`gZI5I;n$a*L=C-aU{9|rA znS2b>@gDiv47u}?9Ndrl@DJ8&}Tm!2o$v#Xs-IMMD@((y|Y zF7dZJShn3~C(fIlj?wWkUNZ7xe`$BB^s&YXjr|!1lQLSPuGqB!jIWJlN%yUNDjmT= zv25NWey{(C-|rmpJ71)~ff{_b-Sl?Jm9eY+HCi3LcXsi`zQx5die$VHz}oY6IqV6n z^~4=HebG~%#N|sopLj~FOSlc|2V>r*ZY#8?*pfF+R7X09>AcySJw=zsF3-T2*_CG( zUh&z9;5O8{F8=neCt}xkJrT1gExmO{n~bg}5-{TTdD~)FluIAcHa@-WN50$NIN_hY zIo-2wb4JX_q9boTS^Cs_CrkfSVPu(+x1B6=Z1u^i$JvtQC#xTi8x&0cKwt{|54&fyB7N&C~NkEeZAI-#i7 z8*@A0Tf%=;2O3MyVnZ5hI z$B^T7pgx4%&vx^HE{#yyziZv_0UhckH(lWnFViLsdn5l-MjIC%s9d7O`**LhUz zAB(BOf3uv2i6H-7>%0oYnjt=8{m&sCml#vQj?KJ_1%d$@@y160zv=MAR1A;Jyalz# zR0@yHe1N&h;jx+Tp{yJpoB382uA-_E0;8B)RT5(}cR+(50nE0 z7?sJo)rfGjY3o)?ZZ~t;`pRuV*sX7bn@wA{{&IVXbDJ+W{x-wT&5jjrSBXtqw;Sbl zv1z2%B!8lzMn=2p+|x_uwfNSn59c3;A1$w~0jIN|%S{`qkZ z;z~HNDpPlrMK%wqL>?;6-Q1deD9@vt87KTYO78v6JC@bEmRnX*@!#}48v^1eB3USV0lVZoyDBuJ;xn4E8dsJ|4$*EOT#`ABr6 zqg$X1d(a13N3Ih(<9LiUZtm7qRbtz?6sa;N_uUiXBnq6tPxxA2;JOlvy3tEDCj9qH@a-1TUqD2f^IBS z&doM%W%J#hfy;KfB|Fa*bgM--H`};flJ7>BSLjyRVgFD>BUz}Nn{C{>SvMXFblFL_ zYEB(k&6Z%c*%Dbulygg%Ein}qEFQn8cOvm7J!?B7=)lu2vrBD5;zlIOxh2YQthcqW zz?0wA^m>P$b)7rt;KRx7VJ40v^Ccw8xh2XJL)Hh@lUx6NczsOIR?a7M;MPCL1h@XL z^mI#@t$!XmFfdPUeR}PsXB(#!tY+(1V}e_s9XjRQ5@zdPW<5F2qwqRL&wdU&ddxhB zF~NDV3#Xi0!pw7}_2fM1b&{R~ocVO%9=DkZ&hrI&x+Tm!|86~bK=PMD+c6C9Fa+|U^%%x>BX;fXPxsa9e8BbL$=wTY4mhUnC;oydUBrh;xCh& z`9%OY|oX( z^L%cVWAG}A1~?x(x6pxGWiu1}%6T1$(#$nmWUuim&#TPe;N?XD=X2+8EIa`=W|v|B z&?88cb4!%D8Ww+1vy8mZq*p9G_d7mVOWg}w879^sQ4@)BZizCF!E&+nQ=YBm`SuZdrg`6{16!MdY}48_B+9uZl6bA-41gbx z68bzrzjoe2D0Kmk5@&!pMtaf9%{RvgyKUgd{q-qKjGF6YdRe>KUvFT7`zyO=%DE-X zKKo$4C%v}Ov$OYV*OUD;#`9fzx+RR~0qeK>vxoO_I&hz5w%KP-($g)G#C_K3 ziXXc0D0u}wJL%WgYmSg2xT`luNDzr~Zf+8f5a%*1;Drw3jyp~L_>bR&!LuO>I&WQo zovL z+L|_{;7yW>ypyr=a!TIHSh>SU+{;+`1to4~tO}Nf!rhEj&p}l(w=?a`!XKqJ_cQH{ zPRA3FO6G>9gV9T=%^gjq(a%%wXFD%7x)4rxmCQX&C$rSOsLf4{)sv{rU5(YtsLgGS z)sI4-&qJy<>P%t1Hgp7$*-C*^yHyCi=J)?a{w-}o?J2X%Ax0MeZSM?rf6rOQ0J&G(;&{oJfiW}Ed{4vB)dIJK=O*9yHB&~u@`Gd+3I zX0|zLUqVl}glTFw>&Y##5ME2@xx{}1J-H<&(34x@T6(%A%$8VgJ^8@rHh8U~=PLhp zdVUVuCVK8cVk8(lWh?SB90f^IBS@FwTde79%dvYl>E`0ps_b_Lzs zY_m#p^4;k23f-Rce^}6sg$mx}TxZ?5CFrt~ZqN8j;7nw;1hdVSSV2#>gxM1JTTkAq z(CbZlzTodjPu{99+uW)=Pfxdmxm9`Fdh*MdUhmNJMgKf{^7iOUdh%QBI6d7G=JqH) z31vOyx%J;i;$wR5@o%FixBdmlHd{XhiTs-!ZvA%FlUtu&d+GU}|0F%R_50D2TYoG) z-4bT&Uu!)%&!g}B%E& z2t9dZO{S+?!fek4)|2N|dYPM?i(-;+zA*E=ou0hxdzhYX33Fb3*?RIk;NHSGZDM-S zlji|uoAbbj^mI#@o%T?^r+W+Iq{S?9J%4jOS+3wsPK63)4HdY_X&gE?_{+nA`w+9u_8d)5w}jcAH&{<@Pxlta=^E3Lp4^_R>B;T+ zAU)j@W_#{3p5dFE_S_T3#^lnITjg_la;yA?L}})lEmHhKvy8m#b8lgsoR|mc#mhcs zo6Ek+NaWw-@UpLo_2h-0dkf=Cius0~ygkaKCvT4~r>9%O+#Y3HPp+L*Ur22bW51E^P~0TJl$Iu=hm3p z+8C?*8I$eWz`^eS+Z zvj!H-k7p707RLEBraBKt?yt`x+w8Az($g(r_SwJZd%CwU&b}CP+M(x93idf!<+f;^l@|T zjnQS8Suv*$JRH7BZO4Ndj&e>T9E8cZD;dDVJXjLnL>12E>}GfbvNBGl9`*s1Lw*$- z&aY}^*x0dCtvM1-E1Tnn^J@WFeL37~I31bY%yDY6wwnCvtN9%NRWNP%kB0N}6>VO) z1w!9-C>bow*m?2!arN-llY;XVW~9D^x_Cf>!U)Xg7A~T~(UJTj4f3Pi*LJI@X! z8St;TA_HO;lqK@#NLlg%MDFY6^o;FOxUXs6c`=^)C6oBHjtLeiT^QLoSEfprr3)hm zx-R7kV}+K$nk^rZ6T@XaKcaSHNHUeg{T|0I;Dr&J5 zt+0|7OENisC36uf+rWhNOR`Z_B7zrI%@1B!tw8X?>Qz15BsId#QSic=e<66`KJ4ub z!h;*(6g)Y2Vx^BIo+OE4iU0kPI3`|@(}q)GPL zj`I7Bj|pvHo=JLo@!QUPPuO@#=DCj<8v{=EmiG$K>&cx#j>d!_8^k*%*_+_C8fMEk zR(T=h^-M4{&-FY#c~;|MM#R(0ghMw>UQhN6vX`l#7h&hno5;cB_2kSTCu72liFqd3 zhgf2geYva~F|jbY$(VZ)@0esn)3U=?b6(FxbA4vlNv|K#a$Z&-a1;?RE$$WmV)6{& zH^M$+9e_&Bhs~LZ2}?YKoQnyqBy21DK7-_TOe{fid!PhYlNm??3wbg;<6fL`d9PUz zbJ90Ys60G1n-3Qzgek@|$%DXX>rwhCOo)&{G>0R0!DZpShiixPXYuK__yUxPh+xCY zV&TdXQ$3ZKC6D7*rd*=TwNDr;Cdzq0nGvTm5Q`EVWcA{nR8Y?3GJh?8}G z_C!Ckx0&p4QzEhh%(k1o*O`@1Oknm)#yhsiN!P^0Xk!W=+ca@I z@v8|ipDXZx2&M>6%5i6!qADAX5}Qn^@VT9)C`X#294X&7j^T#UWE++fZdeX%(@e4O zB29+mDHS_D{+ka?)^kGGb0%yHFhwlVTu6PrAZ0!@MODTUOE5*8?rGX&OyQ+u)wdZ_ zFX9LAs7hF3EvATBv9hz6SiioGkTM@O`(sQI>w%^yXPTbD6y?lP4`Pa# zGfgbXivhrVHsb#im?Bmp7h$I{h1UhWLYVkn4Vce%{C@>ggeT>jXPTlaqkPAd3fE85 z`^FUBS6I(UW9o(f=0j7IBTZ3`EO87|#L1r}&SDC|%(aFK2BggAWBfmeDPon=6y;3Q zS)BL6yblvD67b)Aj^cmRQqaV2nlrB~tc#r+uOA|ofDMSMho(QShYr7Bir7NWqgs1) zH31p+lW)s*P3DOpFG&#W%e8Gki)+3u-}M!gi#4u2U00gyTytELxz@C{iD4U``0d9O z(O{aQ8WM3m<$AhT1H4>dHoyEMFC93euT90_EwdLgYF;!&&5I>;I}klD99Yb?*BO1? zT+W4;brJgjO}}3UbEE2rxQKJBJ&97knQ9AM2}fr0b|qr2EUhbbw-ilLTPETj$1O!u zlp{@1j+DBKaUI=_fUU<|E)=eW@-Mpc^ZRox+l3DAUNrrFg|0(^3L~y?-8Lkl7GCW} ztcd*C_G7M{Z9mr`2vcq25Z+s9`u#eX8&wAjS2cBn_pVit{7%Q6)Y-oJ^Rv%-U9lFP zQMa2L@+&;s#X>~(*{(!3!g~{@h%*XJQS)F4UOl1|@f0Rr__(X;EY~PBZ8IL>iynGL z)k|rweR>o7Fk!vqy7h8CQI|$EMO|xA+EU>SMN`y86HQSKqO=#{;Wp9~Ro5$LmZB-D z6q}64d1(Hbaf|n%__;?W;X`LFR!7u+&5 z^Xp{+ridG?xsZJN5%HXWrd7rie*VG|OA3~vX_GO9Z{u0@ZN_x&k;yYy4}3;&?vV*r zf_;v4?vV*r#CBZP*ykSM8!PiHB-UIEhVN}&2^Tx}$i(bG`M2?X&pk3RYb5{2Q=af{ zlfRaFoqJ@0BTCO;&OI`*dyILg@}GZXf(?Q1!K*Rh*_loA&L#X||1x?BiN+?`gJ4Pi zrlV`PgAxWa=sP-=>0bsD+=!q__9T)`vMXUL>q#`TR>H0KvT(h%VP)Iw!yS__H|I?4 zvl+(A=GeC+>Oy2->gF23V>oG_z~nxyb+cIiKT@84?tERc)$YfKcagoGrkIo0IaRcX z$H51An4Gf)-t)j}|2m8tI%d+aEYHy91G00*kH{H3HaL9Ln5>Dx>QkFGt}$T5xJkj> z@#Du#3?djyFl+3PtYO2lh7Cxq+cel9rGDy!h67-)Gj9C2tU6hPhm0C9%2qdE?BJmz zM~(YeSBnT$Ib#P7jSQGrzfoPhZ{zU{9iNjmaOl|Xqs9)aI}+={GjLee@WGSDt!NnXGYLhcrAqq(HU$1`=*+x-EQ2@J~n)(H8#eJPzZ}z+wUcOHS1dK8-gm0 z2g`6u0cNv)uab&#zCjS~b(U7G`8vM31&A z!F5=ChQnjlp#zIg_az*?AbIK~L;DAkeMK@6d%9ws-V7%^t*(uc8^6dj(ChoiczJEp zyuPlSjklX=gV*;sUhLuWdVQy61`VG#v-SG0+$ytXmT~b-GZAd7sQh~~gUWxv3Cgxd zbu_gODHeOp8f1+Z$s@yLa5=n{ z7C63dJlNq(>Q%?BZ@yNBZ=d4s)7t{>KD|vL zY+@hZ{HUG!Gf#d5;Re3RnTUt%Mi3r2uzUONJ=@f8?8(WRh;zT^tkHuR6BR`!)Nh1< zwsdKoo(_#vr=H!@!OOb0?sI0KvHFdEC#*2y1vjvvTot|b?2(1@LkefN8I{{DYjTgl zL&jv8=(`LeY-Zn@v&S-E{(lfuI2;@~KcFwZ*4XgY-TOp`7&dW>v3UHxJ0qkh*1^9b z-f(oFVK*>se)|dpxeW&#KErAv4Qoxjn&!vW&ZbgcRMW_y`!ZdY)DI!zp6t{1a~ zO+eysDCVsha;>P5R?)#A$J|8NXr?#SF9&j>C2yMc>MhFSlS zv5U=7iRX^(($bm-t8<0+Fc+l5$L9oFck2{vtBcZL*PQV~vnEa)pEI#W5ErO*Q_Ur6 zN|OeSg4J`f#$*kim{lX#A1?LW>)1M}1Dnr8a)cA412K5`(Pi=C! zr*%_YK@a9tEiR&wj7b}xgV?=wI;DDIi^O#*#Ao%4N3P6clz zT#WL*<@aI{^YZT1m?F!ahl~~y#PCMpPg!)( zbAKy`iR*yn*#2dh++{-2lY-1a6_~OgH*XPSWPK^9FHqjr$9mlQ)+6ouAn93D+2cuz zSY9{pk*IQes^W+E$@H)vx7>q}k@Iaj)#C}G9G3%c0)^-MBGRr8lAg~x*Z~ii=Eu$3 zigaXseO9AB*jOJ%iV4^EF4C?KlAa>yj-AbfK5pJ_=*aq}qP{J#u|AAI60YxSq+K5* zJvXDiINa{LA2)A543YI!Uz5MxiX+cm&qtA_PYNb}mf=S*pSn9EH1jz9D!S#e@knt3 zZ0^S`7mEbkvt9e&QLdRQK$hc&KMr@()JeVYCM6U4uzmdSC-#xc(F)7KHgLU^#^f#s zmnovzo)xICTEq<8BpIR_dqkdJY3KQld`;XV?h_A)A@L{i7m*Jj>Hn{aMSPd) zdtLlMa>^`7RDMe;7$VBz`1*Et;6X$mf8jEZ0u#AHnI6I|M#UoCoz3N;*0f!?7vFK;<|;)#UW!^ zu9R3)_IlC{#fxNbCw-|nNcJr0QKE^#hx)IUo+I8y!oFI1ooHeM!~UrBlj18R>~D$h z%KoAFciF#_c4PRRmOX%L2KpBvv7E)l^0HTvt|7LRJx#iu*j4ua(gVd@*{_mzWBkpN zeX;DfikoDANSdSGvR%)~{;Krr;y&5GlKxgaD*La}4lXKLPa=usEhk3D?5ibvW0h|% zc96ZB7#*u`nC#Fm;GL8jxuYOSN501owC0vejxjPX$}`lzhknW z7X7$@p*@B1(5lyT=%laWv?#Qm;EAX6B7^ZWhXNI`ifU5e~5Uc?31OZi3?<3 zDw-I0sL#Z}13By}>)oRAkBKkI{)YID?C*;v<{kVFN{2)f>kjrfOsqG7#C#IPa_JKP)~W`!nJW*-b1v z_?cLC;C|T;iHBAGN72NvLpo5@&M!esB4Mv0a!^&ar>@vU_BPTPqKR1tzk$jhCi_Tn zg6uP-XN!wuUn#DY-NdfLeD9b23E7_!cgns;{808!#jj*PEd8VC$2Q>d6%k92m``cZ z#IQrYiCxF#mc6CQw-Yj#(e7i?Cq*A_vS}|$qCF+VO0w4yIqE9&Q^kvAZ!g_ZG%@i|UzYMm%RWw= zBKutFdE#xdo7i{ozf1Oe#b?Cl#hoO|nV5Irhq8Yvnpk(Z-u#go*B~dvUr3aXMINt* zi<8i$r7KFC7H!|<}s{=W3*(g#VD3yJ=c&{%JUNZ5;rrDd-uT}5mmdn@U5v6Jk5qz8yOvQLqo zE?z79Ez(QHJ7wQ2J}mp=;`6fqP5KS-Gugiu56S+$ctUpHd3HJD#0y9)e2Xtcs_~c=D5PNR~GBY-cO#1KQ5!p|Qr)Bry*L+-_1QN?vM*4iQmh7owGubZ| zGi1L^x~G^W`#5o;>{GCn)N_IaU@UxwTNGx{|v9#oO|#rtG`M0`^AXT_Ife@l9g_=W7>iAQArN&HRrLg-TE$X4!8OSIfRmyjS)|rJodEm3_DPp6nlq z`(@9QJ|a5kP~~#Pi^WLp=VFrV)ud~QEo4s@JILNi>?QkP=`3-Q>@&q{WWQcqB>QUV zb>c&^KP7IJ{Y7!7?C(i`Bz`OVQIR7NbNNn*{v^Bn#Yir z&;+()x;R&yCo+B>^H+*@h6~szn4Uxm$($Dm-flZ|^5&2sU=4XnXMTQWheXux6 z94qFErhg9QW=UTo-YDK8-X?Oy6xM6{^T3VL4~P$oPm5c{UE*%>6Y+D=^aG;4gVLwO z(_%dP^^jjwH2s9o6{Ty7DPj|`g_tRJ7W;~qizCG`;zV(ZX!;*9zq!&T1}5}kX^vUU z_N^Bm6`vHJ7fpX9$}#8&%fBJMD}E?)=x*kJAs!S%;;*8^{z8-shzVjTv7A^_tSdGW zn~81246&1VnP~b&F`vt&hl!?t6!r@#b+0JF+8gaeIkdw@ROx!BID844{ z5n_(e%S2Jw$qx zX!>K3o-930WMECU?`CnCxI$bn-X-2IJ|r>{C;fMbJH-U#HwOV zv6*3A=w4?q=hPY&YS&=a< zscVT0ZAslyWME6`o+2YzQk#BOkO3{Jr;GE%1tP;+GXHjw@hqv`{#Ayxq-NMk@=fs_ zkwGqLH~p(1qgqm*5E5gDSA`QMAC-xQknUbHhbC0R<0?k{BkO6Io^ z+lX$zDZ^1Rp8+UI#-Aj|h^D_3dY1G&ae>I7lq`R{$S9Q5Tf`^DXGI35Wd2(s<4;oW z7a4|<`X|w^{zJFFw2bumVst+#V@uM%wa5^Y)IG%hqUkS%odGAApDRumXNinB$^0ea z9pc^MW^s%7qWH4NxRdmE`$-Q-GrT12N5x|zgHh66NM!U$>LigtD5>j-jm737LsBxo zlgJp9)PqE~e{_sALsK$;mUz8*qsTy&%y;`q8JUv$Vex5ktH^+r%-=13D1It3J|*+N z7a69K+ROe!kU=WRQeu)A6r=k~8BUVr+ldTAN!?Fm5K8K?Vy-wEF+#TCX3a?x?%&dnRv0-R%9d<&gU|*r|9+r50V}sUMZUXVfam! zzFM3kGF&O^T_&y(*NgXv_lu8+Pl%?!82;O(qx+5Dll>!cpZKNtop@Meyi~Tw?ME)k zepl!cVmZiZ_Xi#O2~@@h?!sY2Z^R18|!V1bhdbvc(r(~c!RiDyj5Hyt{3kU z9}pS2m)pnmcZ07=zb@_(KM?nd`^BT;G4WT?Q9p3JSX7Me|E?^1b+MkP)1{bC_{oWv>22&pwW7Q8FFETbT^G$y@ z$k4ykDIy~PQ@j1#jQ>mBOT1hhEHVHv^CyYdiZ_Ui0?d53pPONSsTmuS+$z2(GWIX+ zABqRWLn34TGXFP`5r3&mi45*bU0r0NO&R=Te*gYmhN?ske)apiAxcTQg)X^*3U4e>LM;GQX(EK)KWvMaIjeP8As~m-qH_NV&}4ExP^EUq~}TF7uCx4*P4N zV?@Twr7kNnKrVGHk#TaVFA<~rqZyx)`NKs<$EBVoGBz&tLXp96sqYXO6PNmNks)uX z|0bILXK2&^3^JZA^S>7v=$6{c{$(&;EGjbEE$x*=hPS0=gi119Y%em1E$#h9#*wGJm(ofVR|MhzG@x$T+vm_g-kpP`1>i zL`Jlwt}Zg3Ep-c#0c@!|i;QDSJy>LzTIyVp(Q2u$7Z-|4M8>XV{ypM@;v*u1*E0WQ z@m=vl@pJJD@kjB57#Fnug~jq>1+j`)Lu@KuBwi|Z5w8%3h@-@@;tX-Nc#F7HTrI8> z9~2)EpAnxI-w@vx_laMM--(CC)1t4UmRl?)GSn^CXC;vlZ>bxJjCV`jUhE=v7l(=? z#L40`kr8d_f3wJVw$$szd&K+2XT=vp#!3TrA!yt`XOZ3|q_cPl#K^7sc1aUE&_` z197joU;I|g6Mqy>i0JMz?>yo0ka-S-%OJD7*ey&u0AojYsv){n4DmQPzdW8F;dF0w zP^>JbkXV1IVpH)VvAx()>?-yU2a%|Mm^f1QF=94}^_45Ob!_<(XfWq{fc<&M$L*xY zi+gLce5lXNAG#IoC}--2Hua-?y(Z1-2O~c9Q|s4n+#t1Kvqr&Sim}`O^;1$BH*OpZ zHg1&C)D|BUKdWuW3_BtuD#yn`Y&|q9{Hcs*t@y-noiOfRIZtU%;$sj0G<#O%j&rkj zWIMCd2Q}H9@L^(&8oOK7DEsz>m(H2<;+$&+d4jDTx%`Cx((HC9JHGgC{2y58Z6~>G z<~4J6%$XaJe>z;!pIqXM+%7-Po>=4zYhrStGi;t0*ut6ohY$A^zW$Ie{e`@!T(O+VZs~pKFa$J!P{HaY;SMeUS#-i>FV(| z8P5Oy81sV`%@fxj!avD*7b@<4{PSPyYy<)rtBC(sBV8!b-y^UNGX4k)^a{}EP4>i> zLUsP$fkj4oUG+d;N zr$jP~wC!VyGzUEYbaZXMQ@Ak0U-PkKY;}*XXcGEy;z}byD<2{Tig^l~P}zk_MwE>& z5-!pdEiN1xv$=zbRNX3ed7A`Qn@}(=bP>grW^8PD7LAZNUWyeAm7VA~9ZUe};uR4a zx*pC$CGrbglE9ZKOWLT>SP9tdX0qeGe-(;X$o{B*boGT@VX6(;jqHV zUbbj}Ek&4fFiN?NP${+|$Ce`464vFmNTt}MdA1b6X0eppJe7hq{HcJH}(=0n8@}|Gg&Vw+8%YnaEG1z85D6uP2TF|Jo4C{~aSL zpD_@$8Pz6oh~-h^M&%Bi(6GK8XZeg_m9Y-P!z$wx&v9}ztTNWC88rt(vW*`%FqflU zavWx}x;5JJZja+D67*eFw^AkFv|y!bzKX*uRIKRh5%gUg^mWd>vT_nK#!$7b;=4T4 z$RQ>(H#3DLI~g%Nvl0bHYQ8uaz-iqMz{ycH(SXRoHuHxbL-%I`-_=_J8*nly*~_ zK_fN#YIr5I?$)knr?#DY3~bx2TbFL0QCLYCV+N1NU)fxle=tNT_aD0{vT`P78P{;# zom+SA&^aT2J9li`xg9pQ<}@z1VFNf%95pSAqmM_-gtH6}-)c5?^uSW?&Xiww_nv8K zZM%2Zc4rM7K-DaATJr&Eow|4EZvPMLo|QW(dtk5Bx>Kjhp5DFdz>cGa4Cp?7QqIt< z0T@HmHYU92T4@tUjTo0TEciPu!d^XYXqGud*xWOB^3Lsgc5IFF_J8phoxC4&KRoZZ zE{Y3h8tP8GYAjA(U~Z1(NH@jtF){q);M~EUxXuye>#b*7pnQdkv1PkL$p#Z(xKElAbnL zAil%me%#~)7~C}T+M^``J239Y zP2K@RWPLqQAGZ_Rho3}+>*H-4eYj2eIgCP6-JJ)Td7PdT-Et!n&OUzS%P0r;Y`}az zLb+zH09hA5A7OIS)aPL#t23bww+BD(VTxRi0TJtk=NNap6-PRv*`A9~-`B9YA9r44 z#O~oqDB@*cDBE+&-LVWPM|h$$irOxb?Z(Wu)EjIda;ylfD8=OdZ)0>c}}# z`^|H={5t%e3n5m74ena924DCr;%aX3{15H`@&!^pv!~{p{>u22oIlr({Y0MSSzolq z%8mGNJj+VZTt{0laXiWv5&5jQYn1+@>*xGID9`%caMo+ms4G~rF1={>8qC*=bHaM@ zF7aM*v&eH4pEqK+_IQipIfw{Xqp^FMv6iZk*avINUSH(hGX2_$nPP8ofH+Fb7N>|a z#hb*%qG>@n}T`Z=H?M2>oGryO3xj0z7QXDT%7R_Ba{H~S0 zLFD%X>*MzcdAoRrX!cXsH%mV+ZWqmVNB$eqJg>4Io`=aV#c#y##UI2|B2Q>6|7Y)! zR^;|Txhi6cm@2jqFA>{`mx_G&NdFSfNxVwr#U;z%Al@P_6<3RVRLXLj#0SO4 z#izv=#h1n1;=AG};^*Q4(LC)&{pRU2$WT?BpTqqQ7fwo0am?)#xF zq%RTMiG0w?^4-K;#_f_c(b@zTq)iz-X-2EZV?|7pA}ya z&3QABe|%v#GVSq;UA3P04Z`1Q^ZS_Xt=F`EvtYz0+)tDGd;K)^8`$E1-cM5<=LdZL zclFaW#S;BP{WP{arb;LH73{JZXe_47=8S%t`?y&Hap^#QKTQ)TUw{6y{WRRCe2vLrPt*BaKh3#* z8XOkq`e}FxhCUx+A*TPE{WK5od-?xvKaCp?^IzLf^LBJUO(oM$(>>_h<_Y>P%^YKT zX09|6JvIGpf6P#uJ<)d6Tx!+Oa9<5v|GcxtJmx<0#<>1p4Z~$0r<=8MMj)y)pJV@S zXN?UOXS-~|oiXP+YY;E1&cv*tx!}ZLo#A{E9;t_C*BLr~Ty73}vMwG!d^ke2g?ld4 z?{N0s4{Y6VPs@Lx7su^Q3D2`YZ_Z!p#R`cf8J+v!Y%ke-B-iMyZrcr3jLM7nz1*NuMXVQ|W8D3Z&&(rxI$EK= zuVHgP?z~9c<%T~TLwgX6f7Vx%eXg$t>$kY+E5f5ReIn2DT>sJf-_}9NZYR>i5*!|#te_u^% zlZdXG;Gg!@G)_S;4nKe1S2O5$`)X>1->FI4T@3HkG{8GG72fW0IHy|`^Ina2@HK-9 zzFBjgd9x+~Wrlb64Za|A?jR?bZ`kCQIvsw$rpw{cC{qe${844P9G;AvV#wk9HU<5= z93F?fLdZ*u^1@fdS>Lzmjtd=ot>br&qKxCi6;k96ndrz5-nZ$1EOY%7e&1#)GrTd+ zp$6YuxIzlQZ?l~l{+Lu0N5{(+szA&b&MOdC49M@i@zS>{|Jlx)SC}*}*}##V4d}61 zLj?REa}Iugj;YOmG3qvN*09;J_oIj>_U|Y$E4CBTGh;i$aCPj(NY98JgtF6PKZONv z*7StHn>Fmsh`R&X{)G-381VmQ{x8D+Lg)E!46Hz9@w~S5->g0vPdvN({R;!v!Rk%+ z+76ssBz^HqS=*w3>7&M*HCgms97trdlLPUMDVM0Kg!p-sOC^iO-$l7Bz&3c36FqUb zhV}Sw4U~p+z|W=>cGzc%4je8oKf5eEP9p4l(WdiVC>DgZ2wQF6tw9G4+w62@lT8PX z>Cd^0l6}|3+OcR4*2y<;Jc(TVibxe_FIN7GHpa^-$yp_`jqHK5MK1J|;Ew}hT3iMb z-oi{3F3a`h$Xv58gw0qOSZ1XD}yjW2i$y7}CT^FXhVL}GcFPy;?f2V^C zVpuqXDgKZH8N|$R22)FH2C*uf!PI7(L9lISzGxFP1-cPzA-iTswok9UFxeiHnAEk$frDRLJkl|m}~se}}| zQ;6D_*quV=FNKfEbWA8kXeoRJm%_)T7->rpS_)smrSNen=Gsz(mcmzXDSTXtwYC(& z*0WvYE=+bQaGJ{hu*rPyg{+GSo0_m~O<70wux5h02TPMzSTn)>#JrBkuc zH4?VPDeK5()=aQzEKNRW&BQL50rN@1f3HdTtpWd8Ch`-hx8M}?f47@wc*6$&j@NP6 z%~L$+n^HG9**7Ja>?;)X)f!%>Ld8lK`q~A3Z=kEEO{TBN@a8pBd?SrUU(bL{O1yf* z>`9p|YG3SYWknW5JzrNN@C%tgcrEA5UI4vufaN^%rJR4D+vZO@Y@%=DJ>$n^4Y^9M z)0lTd!o59wW#ZhcH-Ffh6Yd514|Lju=k-@QYtG!k@J<_du7dC4nBB#^x)ZMbU)-Pb z54=!jk8!gP{@L3)XC4v%eJ|uB;7tE}eLOtz{~P*vxC5N)(!=~(5kT;vzD`!!x0_Q+@K{`3A?9}g?LjVzK1{R;~9_o65Yx`w?6*fI$MyPW zeLM}(h#Yt4QGKlbIitQYJ$;q4aP$1@f6eH~GsJ1;U~_waCh-9a$^Ss%~6=;P^smii)0Ch5+H;@|Z? z&ST-3x@*ZA{+r&%;ko8)@8fg~FPn~&-}~;z1@s@hkKM!q8+{WiIW>yhu`JVoMs zz&<;2nSjX`YYSZxR$Mi?zghBF|$ickUe=yBfp6Dx}U>^nHUXe*^!a9lk_oyA z-}0x^{SCStd@ax@BQ;}po~QYqJWtJc@;sv#=Xs`;%yY^Y&vR;)$a9)^Mf$uvC-dDr zPrr$w>!;;}HfGij%^h7o<|9I}9BSormIPLP;&Gal zaQsXC&JIuPV(${)(wJp0Wn^UFwZN6$6cE)9BOJbfg?QN`$MR}gg?r42Cw0H^DG`2>+RJ1%d^mS%V==#w)p;v1*3f(hp zQs_XxNg+ShYI?uMq2bL_L)T?a35@_>hJ8QE-ra9#D7Yy(G-p-iP+-%r(Ch_Sp^B@r zLUU^-hn(g^L+hJY4tX+%g>J~K67u%T3f<9fa;WO)DOiimL-SWn4DDz>EmVC$Zs?`V ztFT5Vq22-M8``F!tvk?8Z=SPiJNA|q=~$BsUPP;#r(>_cZo>`LFN znAQF@PNP7|&237juSs8@Ug$`mkh5sku?Y{wt%_f>)N@w=YrA&*vbd%Gk3KsQ+|uRX z>v3%l6ke0Cy2wiZk)XF*ULbQ%p2PLfd}*F{^wKmh?I3A~mM&Wq8rg`(w-&W<~3^^?{1pD-L1&&9Y z;dDGYNd0Gz$2~Y6m!5Gv-h*X65OF+SZ}z&}P-UE>%rS`LwF-|_p1*i3Vj3}RXlS<1 zOS7>aJUB1S?pHPB89h8Sd-RCV>}gK3HaIqUy!!IY@tWzw@tT$wz%gr%R~)nUc)iaY zuK^ve*^gf{)t}+iDv}Y%7&5Zr4R_9u*?s!>Z>PVQ>ePzcoxOEgoUw=Det z%K2(G;s0aQjk_|rkI6QpY#l8LC%`u)@xzAeO^yD(FviqneG8o$NXPnlXBO+#cMPb4Ul|x`nySg+~oW;Y+z;xLFfM4Mt%jkwih0EIcX&;kK2mEuoa{)QlYmpQr ztlUKTP&k)Sd5g3Q=QhBVZxQ|y-4>oqiA>37D3dWSoBJE(+u_1(uu+P1#6mkgINy1c zpD@?RM<~At%XnOR7daG`jVT`s%Y~F9!g4nySGKLH1fD<^sm50I>NgYWmKwEMQp0V*^Q*eQVm9({aEMIMxjolJ~s+=8WqDQ7~DCHs$~@FH0m;=P^VE- zjA|@(yHQP~c0hTGIz_nlT5u2*41t3M{1#>>1FNc-IbJXF?n6d$F=%tZUhLff-Jg0P z5>88#KZDvFvX_|r=b;mMmcWUZOXFSCs<=6X+Zg#XvZ1j&R#(CO95j~5>bBJ8D7Jcn z)#38DTOBUHmD(K0Y2F7gyKkXOm?PP0q*2zUi}P4cH^mC!k#Gqf%vP4*(d;Hs-X@Fl zcy4RTGg4h~9?(_}pu`bv)$3F^q^+ughsGt%G2Ou|aaZaTt`Mu2QJbUMY6e3q*)Bgn z2@jJ?n&aB$528l4>wg!uIkIj3H`M0Pwz~Ft(B|0AH1p4u{}o8#MR29YXh4sfe~p*Baj)jdi>n?w9kGr!xY%`x85=n%Cz$gNI6FGET0fR5EU z)aEd^nn8q0n&aGRetDEM2fEcAsm+nz$<)7)x)JNM`Y^RQ)~#kRoRa2Xw|X13Iohpm zQy$tJ?pAN0HphEsvx9d%A6u6Pd>1pjEF-aFSXl%=ZYiFP9mC2yjKm&fWg3>Ncs34D zE59-lN2ry{D=-&_sFleVQsNl3axo=O3SG^7KQa>YwX$N6xtOn&qm0CSt$f%>%-71F zjl_JdY+aGQn6H)pAA4^CUqyBI|IggHxw#1;ghd1la0!cm5E4K{iyA@*JA@Dv5QVU# zEP(_>L=tdmz@-7A28afiS}QI|KF@DnnfpH9vwY7oXO?s3n=`A7hdOYmB$EByEz(29!eN8J$T@Agwjc3MyEFRp0bB@aYIja<-pENlEqQ#Xshw}9;9e8xgcY{WgD0M& zwDPuDa62e}+$G}tD{_at6}jX6D{_bHuE?F>Uy-}1-OP@z$DLSr#qCB|P&EQanFb?w#~5QsLr_4lj`VfBAr+07t})b8~hQrPl6p;BBHsZFIU>e&Vz^EFf-< z0Uq{1S}&4lT)HD9^wP}*&CSD~V_kIw&e)aBbTar$yq}nrJ8-=GtoI6X#%eti>y8=%B`UYu(P$P~X%VPkp>~mFs~B(G4dp zvKU8{pd&JiaW!$NI|kiD@7tR*Y>^nW-&cSW9;$L(+&zz)Bm zPshRsdg0VXvtERcBwbxgSG*XDJIEimjT?6`seH|=a^;)l#bv&qV~5@m{C7!(XM5qy z*R1kyRg58(ueCQ8H^+eHS|pS@sdc4I&EM!^j(qyLiP{U?=23fASLJUOd$(zz=o2f*s+5zk-eyu8t98 zg{#8~BF#`&#}LxhQS7NOcDIkZItEcklB;7d>6T;h3hLKH*v2QLn0yAHoEV@ElL zP)Dk(V>l@tRv78b{{*1xlhVP9irJ`R2X^SlrH-(xV-)G?ShOMu=_1$>XE-Sx>^^3r zj>oYhd=z!Ga&?R$rNe50bp2f&V@T;paW%Mh$Zxwka;Sr5@6b1zbafQ1ppLGtj?tua z@Zx1QmSYcgrlXEdu8yIkbXcvBF2mI^ij)rCSj~1jexJq8y0RU0N{>uMTwWpJKh%xs z+7rL-#vRGHbKLw!k<2d%7t7Cs-HP~=R>NA4bTteknRAj=97JGo3lqby_XSt)Fkcx) z^Z2O@BmHsTaN~|)+<9&p#*iw5#WL{6Ekl7@hEb%-5M~)#)hPq}#9>!&F3*h&SMM;= z)mzMJE#gmV4SR)3Hry*2dv`L90$OZP5>kzHH4G+Q4YAfqHLW8Jqdg7mQ(t0-hEY7X z`nnoMkgkSeR%;P|Tn!W4x{V=KHwG4`m>8bkJ#c*B>K)BC>*4AhPO4-~W!lWuo9F5s zLDp}x)aYf1{Ws*+IEQ_1f~$8ZNxiKsUz;tCWsw%uz!v8f3^mSWOHXz+3?rq1$=n+I znlDxcpN8SokmqX1CD|{-*0GV@j*UWldA&4+J~3Tsb#;B}wv##T1+K0kU^1`9>f2i9VgS^w^y9oR-5E9V z9@fx1jPFv@K~ih_#qu4)ysj~M9UF0y>unA;U<*fH1@c!P-5A=dp)IP}qSc!wRj++%JI zIS(&%nM2D1hSqDaJf()k0Cwma+70J=S`8)L%%actjFscYG8f>q8cK?l>(!C5 z_;BFqO0A)!Si}6Wc>6{yUCb#d)+m3hEH~EhZs?=9xW!@(_Q&D_Ds+wE36NStNxC?5 zW;T{9&y8htrPfeVtP%cL6Wmy)RnuxHDb^S-7RhJWlMQq+NZoBlyxWi%Lajfc#ilxO zr2C+Wis2|7O1HDrpU^kbW%&0W=~5#`y7!xruBRR&UDv~(#YsoHD&5`w(%l^`9dB&k zG1A3cj=S;k^Z<7B(*F}9-8v)e|9vCf8-CD8_ul9c{mzl@4W-{Q(p`=YhmkIEJNEA} z(%ts&8tL-h62QI1?QHHym(TI&Zf2C)0vAQNPZ;U)f(QR0q^lz~(p`=8d@@G38QCSd zI=*$JD;?31E_J-@>iFIxUFnF9bgAQqj&!9XI?|<%SKM-#kv~VcsMpCxx}$m7l#V(h z-N#)WX0)8*>Nwd*cMM0m((&IK=}O1<8tL*zfqD%knGPe_sdz*#PQp*@X_ptHA2$Bw zEf0E!k*?k!I{wXbHH;*sfzM`Ugjcs@Z@6vzFN}(%_un!q=FJo}9!}P8$=KM2{eiau z#2m%*W2DgY(?&>+1cM5j5|O&>J0t??I`4*jQO}93#m3 zEg35ruLvRcaq9<-m17!wBi$b~R*v-&pN9VtW93-Q*q6S2tbCFYZSYIM{D0$`6Q3#94qsZ zaKa=>+Oe_S+Qr()m;VJEJj}z6vF!yK1#09-d6h^}> zR&Vs_4Vt`xA4l$K{;~4tZtg(Y_%}ROZut17nQ=LXDA%a=mV`BR7X4b-ggJefFp$wUfJ=GuTyW_dB7(kdx6WaltcPPh$sBb)PT)AWV{y~h z=)+sCzbB?*)bEysAv3W1dtz$rsHeKI7(*qF&NX-^Jxcs9%#@hZ)s&bIEMCuX`xt#n zu%n+wUxK6}6E~D0DodRi4S&tum?x{b8_Jr`!G5xuyRjHUxkX=KuxI#7?Y0qpmSH#j z-B)lolp)d+o$u%mKMsu0g1-47p7rP%Lr6X*wK~}~B6>@v9@YkWG=oHG9(L#%LArVx z?vt?#BlYl{^vZ)9IV7G>&@+_$w(`Vo;M9|c-7AkfCsgF>8A*OydFtxnIS)OWTcX6i zi1G|0>zAia&#luwJTsw3vrm-RkDzB1Nj)j`dt06K>`Pub(#%X4dj`@EC%>&6b=!A> ztH+ch)y#q|bM=fN-EyFm{{9m!2cITzA;a!2V|AYEjt(Fh&JihQ!H9E=vw&dC6Bm_Y zLd+)+u>N8)B4V8531eSoby^RHmAvgV4|InaQqVqwKYjU= zY5bR_8zdN*K=b3YFdn@a*o{9u>i#&bO}O#Rhz4PiBf6bNE?mh3n;$31_#3w=f>Ga_ zNsP-`;HGQoVzG-RE-rJ?!N4v14A(2sMOzmOT`Vzh^sm9A>r;?aLnED!DQ=5J) zPOOz;Q5-c@W246SJ8rW%B@rgN$kaU{J?;Fq9ou$1qvPaoWp*!aSD1h%CXy+U$;jXS z#%a2C0_xRo$R*=cIL+(Og| zcH9PaPIc4Fcd^XCJ$UV6Zj;{l#ww;B)xi{Cm}v_)T_=;yL_D8?^<1MehV@$Ke7Q2> zTxUn>F`aTJqw#wCcG6V1XVhhKsOM+&n;#uM(^9U7+fwSru9w^WOyfDehCHcTZM($O zaAdS3rVyr$jVtyu+W7+iY8=8!UfyZDJBZWvRQI%Pq0`n^Xtz_CI>tJu+Z~f*hoHfe zwv7olN5?31kF$E2dvZGNAvHbJJyqNanF51(pS13wbdQfYW&8c#6ZZdu6ZVGh zeZrc)=AMl1rRw{fuqILLM;GsyhjGQu!kDX}bJWotX}&qBNAskPX=+&Y80R^=?rB|< zV5hZ9Yu9-QRsihnEFJD74nKd?8CY=Fwy&5zY(Z?*vnja7l?(G;Z;9YhqNK zIBovi1xt!&SXUGx{={jSy-lp>w{)(U2JdNeOY&zf&BfP&7B05TLTCCako%n=vk;r_ zlR*<_cv|KxTwD_2qG&~f7S5byK6A6UaK_waeWy%YQc^N=@vM1QnAP3*wW0n~O02n9 z&@Xph;p{rA`)QHC;<>XI%$yN1-*RGgOgY_k15J^l3$RT<_HJFHUR+w{gpB7dSUPiY z@k~>I*n)B_yqnss5sNjUuxQ?r;_23)b0!ZOHE!5A_jk&;nI%h#rd-fBec3Yk=Zwpn zGIH*;$>SC-Sv-B_b-;#;ZH49CxCKj4wG2LxqQ}}2E(}>yTI2064n>W*9 zlbMFE6D9iDrUn*38TiVyY7EG(YcEpibS?&~#k{nhxupO6+&0 zpR=zT|7ASSCU_ly4T_j(3&bp(XS(PWJX%F1i!-eW)7TwnSQFJPCrVz%Q`kbMJ15eW z&0nx^;k@F=tc8msXza*fHFhL#@xtjdi;EX7F7EbkI6l_E{up!>&P1bIb~>DKgWN+k zs;?Dl96u@{kQizfY+;{bpX#)-Tib2y)0|YhT_6o(5HqawuO*n_8^3Y*mYp2ACVXxD zb)g@}l?T^2YXjHY*~$Im@{;57li~^z2PPM}%lvxDIMiz}O;%i9N?d+&TtQOY1xU6G z38F71;pWhBU~BU#fFDaY`mMnHT$8(_@mRRZRAy)dd;$kbE9_bBU zVR#;VOR)a}WR^FKYVv={#3=a>|G*Xg%?e|Cyn(~ct*?vduRFB2tPb#DJdNB>h{rH) zoI1b={yXDw+Ms^E>{s6Az3}Ipvp?R`h{L|*ZC<>k_2QMpTUM4A3H0JEh8zD072WPf z2JCP6Z?!sWA67#4>cq%9q3;b}LNBZWVLor`Y3Qp!TZR<+N= zbJ8xsb2DBF{vqgrG`if)3wscvKi`6Jn1aLqy)oZL*u8w8gxgC4r}Y^Ah0lL3dtr|u z%&+fmoWBwHQ6K&_HmdJcxVaN^&V z@n0EiFl}DgyO90*K7&5*xS=Vd`aXr5X_yzczu^K>>+3HJvPSDo+5t{>Ohh^4BA2QLJ5BDjuuPI{Aui^~k}w<;%cxk^$`A zcEd3DUvJvL!_$`nH}kBc5B;>%O9XoQd|t-s_y2dSrN{}#*ygp0>*H8)W?nKDj(=wK zZCqQiZhG&k@mg_%$a9eT?h<+3r2HFkkNCW}SA0$U zT#Unsz;rFdj-vTTKKKumoF`5Z7m6#ytI0Ua;<_2+^&~E^H!HkG^4*djl+6DGXa0{# z-Xod+xXAQxiU&k~c!d68TpY+#MSkst@|og9@mkTWJBRQsk{=LvkjQ_RNnR`OoS zW?ea?|BK|06>k1}3hDVSp80>R@Obol%1I=`TS`7na%aiiCHIwlw&X#Q`MQSb^Cfew zV#9l! zFC>2@IfP3h+oKVQ@|_~NjpR;}yGiaNxxeIW$wMTMm3)EZsgf6nE5x;8m3WW1Q`{r& z72g&=5x*3<>J7`^QtTw2L83l=NIV~%CH_d^gB6}9dA#JQl4nXTlDtH6ndECF*GPUy zd_w%4_!seS;y=YMxPY(VsVvt9f^9ZlYEQhJ0#yDdAsC?B|j$t@*!klaObrsRH- z2TJB@H%vcP@>Fr5xKg}PtQNP5kBZNWe-u9yKNsWhz{T>m5Ic&!#ew2b66MJwu@{IF zNTk0^EFux_O37s;_Dbs9v;H#VV#$|_b?*NN z-yr{6Me`g0|GOlc`#5vPk>tc&rNidTuN#B!1LkBsN7hkL8!+r>M@ zt>Q!C!{Vc&d0v5@XC%KUn&%eybGs+C%i=5I8=`rxLHfgzKNY_ezY)!I4dNy8IRR`YwiMfmX(E?hW4wOid7^o~ zf&XyHqeb(41Al&dg6XD-v&5z1a&fhIop_VDUfd+!E}G{d=)F(!qvGS@v*HWlE8^?o z+v2<80r9Z-jmWZd#|k)x$)b6lg1e36G_i}AF7_6)#awZ;m@iHeFA-;nmx_zUrQ&ts zT5-L2i+Hz^ItD+5^opp5$_XsiMvHE*vIs*if@Vg#gD{K#BW4CD>EHe_#<12 z?Zh;(yO=I!iTwUN(~T7KL@p6X{{`Ywak;o!G|zj8S0%Yxyj#3i+#{OjJH&rk@+;yS z;@ct@A!PnxF-2@4riu~KJhvhKaLM`N1>z;*G_go55xJ}(^Sed7UA$AgPkd0^CGHlD zSsK!FZjyQqh=)b<+z0xL&+P^|xcHX1U*u|!Oy5TAA!dmE z#Q|cDI8@~FkW9Z^yg{rG?-uVBw~0H&H^jF^t}jV_T}7@iN%>rHlsH!8nv)DK6}jpp ziO0l$h&JXT86GDli_Ju?$I0;1#dNW^c(!=1 zm@5t!xqc_pPZ4K{mx^4^li_9JkHzc7O0i1(srYk|>whx+9`SkcCGij9o8o)oMbaQtE3go+7puBVs3!E0;3kzO zwm3{2C30y~#-A$A7B3SQi%Z3;#8qOsc!PMexKZ39-Ysqw9}*uH9~HT{D$Dab@pbVH z@g4Df@v!)*_@(%b7}w0zmmsEyEkrKg%KW;C8Dd}YTydbtIq^mD zRq>DFN8%^qXJW0$7f;MDC?<(1Vk>*}|{lx)djyP1z6AQ%2;#9FnED=|TWn#H_ zgIFn6iChkt<$qXwT-+nRAigZ_7vB><5s!#mPMG?V#g<|lF-`0uri;BrEgW?YHY4JI6ulTCS<(jGQQ}Ijj z8!?1;s|@EmR+7s(lYPYjVwN~m94T_SXU1PDt`t{`YsH(yYH^Fm<)N8=kNAT4viQ3A zhWL^AiOA)onLb%;DYg;Q#4aM2n`Znxae_EmoFUE;xg0g)uNOCow~IT(hsDRmJtCK{ zX8O;>uS6QC(7%h=UF7oC^e+)th-Km};wEvo__X+i3i2M zi3u>=V0wNjf$Syr5xE38{fCGX#f!zu#Vf@d#dYFV@gZ@a_?pNy&8h!m@eA>|=(Kag zNr~cE$ zv&D183&o4XtHf0zmu+YIo5i1rTg7L@=S8mT&iH>84~l;izYvd$9U^Z0&SD?&Eb)AC zkT_SIFJ38@ia!>w7q^SQ6rU3ROZ=Vqd+{IQ*J7g%Zuy#sr;4YE1I5AOIPpSpia1?d zC0;9T5N{Q0#JfZ;U(fb@NqkfMi};~WVj9qd zW4g!Cq(lAj_-5kwwcU6JIq#2l+{1Z8FC5RjMnC2^hB7|nkY9_CYjrp?xBYhd zgbs$|!bij5@BsU)Uk`rfV{2>N(XjL0zCbl~XRmtCN~p9tg(?%O!+lT1Zz80YmC4od zl})O{D4ji^8GeJ6@ztSCuYPQ;2~<~RXMNgb)k|>aYf$42NtJ*8ILW3T zQ(9gBx|iwTw{=L)JAcf}otVqCe@4D;c-E1>mSyD*Grq2mb>ywGmp)Eelbt&vm+|Sl z``68?cWzHOYUOxwU#iV3JEhV~aiq*2+v=KiWKUVkYP(0mUN63v+x=xNE5g+Yn_A>F zuMAdC-rhMkz8WoJGd<(j=f3w*z&^Gwa9g-R|4?;ujdk;TRwJ~mQ)!_+E3>U5zbXq> zqg~eQ+8%%VUAd3ue*RIQBXg$4H_%>z+(x-xd;R99-RJ=F_+(#V_31h22iwB8u41oE4Sqa?G5(}R>$o}DQ(xM|6aTA z{n_X>0qoAF`;JG-KHw30sWz*uDSAOl$Mzovt7mMFAIuHN^tH5={R(eD2a+6HYr z``A7nhj3M3Baa2bX76SA*$C^n--MeZv&KeG?)KrIKW@=6`NN-P|8}nx8TmmXQl6gU zppH)E6(7h{N?#-O1LHoC$-8+Dr9rpTLzz+4|J6Sut1VQ-v8ovy zek&1-YlCRclMLuT&G^J`B*Jm#-FrCxG$f3DeeGO?Ij>Szzw_v9%GB8xx(V07KQ4$o z?}q~)U3-*TgTbywU$7&hhV0;c`!mS#zeW@*{yoGfjmIR3wKD!9_*@lFi-8sKQxW&d z_^aW++zQj^FSx|s4Jn+CpWp_YWlsnPe;zjo3KIF2J-9XQT6hLJT8VfUVFmA(7)YE+ z@c|Pv&@o7pJERHIqB8hkToRCE4@VSxyeSx5Ru%MdvrmVkF>Md+3+U_#zsAop;KJSz zsW`a^|MFu`WHD+WHo1(UlPGq;-h`{t+ZR!sMKOTNx#Bkz8&jOj&|`n^vBbG$C`5ScVpxvku zzanGf4j$jta*|W=dIeJ%PO|rHnFRm$aT4o(AE%M`5uGIemtuxBcRy=$OLh{~Hm>`r zoMe5tMxV-QqEFXIO!0rKrm62+HO;&LG>-dqnig)JrzZ_--q(Dc=9H6soyI&FSyy!; zd46D>-f}c)Y-!owo>5U~E>m{tafG^(f zn1?ic1|q6oM z?56B=yy6O#rF49N9oh04l4J^uGSblrI}#J4jdRjHL0lp#Q+k%El{{gRzCStR8#g3ebz9urdN){Y$bF<7*W!p?RisS1&u@bQD zCS!*(VvdOnWhHR9Z5ma^j>cY-Ffy96QvrUcH&3#^O#_q^Nu>&W@_Po5^YT!7vYQGvg7D*!4p|p$2wu1$I0$1o) z<6Xc$c%ADcc;fk+#yj)Ar9UxC9wnY>bd%=4Q>=A)%dq3R!{f>0gSIU0xFVKeH&N(t&&P{=m$hG$7=KCrJ>B!8Vb*0$90L|;WaJ7 zmgF%r0yLN{A9ZE_30RrY+ZEkj_ziIQj}{M&>AQ5?>*hizmkM*;R4x_KtKPGU!DG%2 zcnz4u<+NYLM#ukELST66kF5JnOwAZ;q1kQ z^CPq7&YM{r>AI|cziyLfFIW;OG5=hT|7eSNs~AkiVh3iagGGHN!@uW(g$ri(=iqz3g(}bsFae}jafHNZE zoEhQo`2+Ht+g85reB>}!D!TSZz0z*Vn2|B`bmr>(az(n+eDy`Wx_9c;&1qWVGHJMT zn==bbR5?#vm5xPLFnwm*MS1xJQ;KqmORNP;<`2T^3KmvYm@;Z$!O$rq2ag^C49?FV zlW)1pl9=CqeWzdnk?C`0TXh!dXy6E0SQw;aNwHOw!?gv9#$d6Q`Gv~{#nPFjI-(gC z3?5f7C3oPkk>m3RH?Z(T0}Ftd(qnjKD)2vgeUAAv=NHc`v3zUNoVZ|(jsVVgoF?9y zEdBb%j_APrA>&649$lbgijj6frp4dhIKG9m%@Lvx4ivo1(jOr_|EEZjUfQ}w+! zyqe{m3eVQ=)>ri4-t95L1rNsaZua%#F^t>k*g3fPu6P-UQ$Jt-lY{qs(F5`DN+i0a zV7Rjd5=;`zGYI1`ztPyeGQerQhyw8O%-g)M;qdV5+Xj7n`l3Fzfv0a0++G?utu#zm z@&ClV&2!F!hv#NkKNO}b3#82pn*-UO@3IcC|9}VcrN5W&m2i7$;IuBmghzx9ZC=>r zkp24Z?e0#IP#+)%Sk5sV@UNw-+%zytv+RWB9MI`{SM0vf;Hob|W5=7XfB_ z2=UJL1kfw{t3Ee_KSI0#bZBGwxb4O6ug6|ryKrpl)dMDy(LN8S)d>}ShYoFCzND|Y ztRpx9x4@IHn!ktcwZ zht`wF*OR9~W}EZc#kD_{)(bz$;Gk29)oBKvn9NFEQ)Wz`Uo@K!P%&}lqL?^i?$Ver zf62U4KjfCBH3g3&O3?3JTK295~>YRbc<_{bS7~j;_+g5 zAMqUVd~u{WPMjd}rpR>j#A0!kc%8UTyj}d6_@MYp(TugB?*++w#n;8R#COGy#KYn- z(MJ2RTrI`UqOm1_|8U6{iqptA_YD(yDdj{=XDEE7_HvfZ+@UD{iYLoHLk~~my zuH-z)<0YH_Jx2Wb@?RnHtt9o_qsOF8O!SK*&XK1!n9 z`6`s;JSfw1qs%KJi7so%YY1gt-^o;wZx<#I`uE_J7=}N?v z;%ae?c%#UPBgVf=yia^kd{}%`+#^0K{!aY8_=fnl_@Q`E{8ap0{HN%!zn~nv9+4>` zU#LfDW{7-;P5E-MOuR3+ZxL@7?-U;tcZiRRd&F17@B6>> zUn>4LB25xlUhjYC+e_{!b{D<>p*L$2!OyHs1ZFGT`(OGolE;ZZ^ndABD&1;vjd-JY zv$#>bL;R_Dzqn2OmG~R+De=EV?|k^s6n`#0AU-TUDw?&KkpDB1 zUlhIn+5dy&H^uiv?|=6HCi(B;m*O{KJmv#fzeZyH|K)El|Bhn)|K&eR{y!44#axkw zGt_^PI76HxE)lN~%fxHM8%49G6ZG6E`5y5>afi4^JlX&Hzp3!Qh#!at#J`JQh~63i zNf`9A9^M)Ntt6uvVKnBBu^7&c#OZCAsrwy<2xe_T@A;|M*}XF(zU@10V>2_bRyDWp zwv8=kCO+HPRv3lAHnz!~+Xj`lT9;HlaE?{pwxU(l_&HhSE!S0Nx4-$+imW4@S2Zth zyYc$$tRsx2|$-9@lPsPK))~?W%U1kvlGDpluy@ z`mEn^YE|&&NM@_sI;?vIQ*7^9DZR7o*J^{?PTLTvOkE#W(QaMi-1eJVR(04IIQWbc z?i0?j(wb~&Q<1#B#b($j($Y2|H+M{~b%u51Pi57)EvsLuE!Z|L_u||=xxdYwmD@h| zwOVU;;he~vOXnP%_~h}VtuG$8*6cZMZC!OdV8pOF@CI%{);{F^jey|F$Gdj#25B-6vX>)fUx7P$WQgdW( zw;ZJ1y85`&F|KOZoJS4@kb{%(?%ccP+ULdPY?=GwaR+5c+WPR0)yM6QPa>`tC(_qS z|LMLT<({^&&23|H|CIY@)FwCg`kcMFn{r!kdS!d+W>^W^ZF9!fhDW|xYh{eB4fc4m zHfTL{JUDv~w1zWRAGbO_+-CMcC;sQzyN?Ig{66QSeaD*oO*VyZe)8092j4GEs7R`4ye_*o zJfO?oRfyYcUGsHs4r+2+a@FA4;DA;e!)IovHo5uK+eXY;zvI5_-|vM zs+JqG+pXWxc73}|-E-FOXtzGHsqJk|b6Tz&ynSIQhI|ccYtL;xQObL~>5@S^3+IDPL%)ge;9$YO!TytTbg;#IfR8_7S3?R2NlSr;*CFwTqwg7NP$U?6`+nXyASZUn=_@!f%#Dd-;7*6Q_!Cx zhu}btN*qqt1xJ~INHD%T3t)#G_`xRhZiK@ow1l4FU>_jP4$Qa1s7#0>dn@z|{7OTY z;CE%HITBqJx*6^jq2>6!GSnRrms|0(scnh&~ZSc+4zHZg$A#dw^y?hWtJPt>z5nbOo>W zcD!vuxTGID5g*%IumgpI{QcLBMg3NyA2WBktWx*BCT&WTGyzwXb9G@;Q%W7>)b?9Ao?9I@v95VVeK zO3LPPZ`PQWM$d64@~o@)9BIx9n2g@b7L0BwaKV6v;8}Cxm+Ux;f-l(-^AG{nE02`Y zvA_sdJyJ>sO>|5M9n^z-9*NqoAgTGf04%A_gOdrEPks$ujEw-s@irEQ)}!QV>~V;k z*D<&oPF`$anL~Vo-LXo-QF|{4DK)%U6k&(Zs)mlW*pY&`#W=?kToxgR=yv zB0&=>kOXPcjA2F~9(sC0xo)yavm|TequqV5Kvrg{E! zP&fR&EKGb)Kl(?^jJF*$<{0JU36>K!Y6V_-VI^1KDS=U$ry^i+6zp!Rfhz1xVA|$d zT=wa-t^f^1Paad4cU6{#`lr@V2q6R4qi<>rg$Q=^L4vm=l(e#x)tTh_6TBBj(@zpNs1+vz`}cKXk#ouyt0^CZ2T!JZw~<|A z)>wU9`P=K`#z7Ix_8flS!j4NP!J-5(%S$p_xKq6B;Vv?1@WW&Wu;a8Ky1G$=QtUP+!{*_2%wiobw1UvF1 z+@dToMH!8_=vf4lCU|;cmjfOeHaF@PCRO5AUWw5xo8Zlp&1c`uR3qI~N#ryWoKHwW zs;2;oSKJBzoo*C@%5d3@wgk1cGr{8s79-BRu+q8KgiO92a7)2gPiFIKi;A<-EC^c) z7vzpX3d^wL_}l}yDf7IP8R*!&EF|%atqkBITNy~L@w$9nU+?0T#M8DifGaNJdYU3| ztj11@PLi={mg}X$B`?oAlNkq5%*MDpmFPz@K8|XI|N0TL8;u~wd9LP>qe0~|(wED3 zUZt4JZtTeA-cma9O!HhoT!I~z)wa1EUE}(*-FbsW{9UEq8D$b9t=VRvB(t!ij}R;j zuIm0W6~Sw<8-w8G%&`)_j<&+<&`;G+dt{~8{6_G!;9_|s+S7T3=Or95YW>k`SNfvY zMx&>ql!%QjdV4WNFkbk15xKvDou&8yySIG~H~-h{8|(onV7AR%MP8ITdd48^XYdj;>rkcPWl`+_z7mYc<3)KnE`t`gquUb zx0g7KFI#qwvn=AA8gb@DI`(SY(U{}Tk92fWA{f`&q4dy1rwKmr=_HgmDZ`!1Bg0@H z>ntCh=PZvnjq!oNbQ>$5 z7Db#k5m?r~Y!B}Mv*7J3(~Xec3&M_-vu1XH_>vuA*bWm0A?p5}o$f~K*tU1izNfYC zf}(fmb7tF){YP{@tq)4=e6zB|sj>$+FRYy4JZwiWOJ~~{x6#mXQNKR0xAhwy#%u~@ z`WQ2ltYeWo1qO2^##%QPfd-BLidkgT8q%2BMlCF57Af1|fu0d@wlRtvXnx@~=D(h~ zWSt@!wRLw*!;rTnK2{FIu^wLqwRr>F|}v19krb`&8cGoyIy15 z+uNExZ*I{P(~TDLbfv}bz*w6#VCEg`V4l$`nmT`G;XGec%X%06sqQx$jgfB57B{M@ zp6#)E!$1oKLihG8i0fWhT#H|y&2v;+U6W$d(M>UAg8MBt%5`(VrORiz>zywDIVQTs z2EuQn+bMc?a&NT_d^>Pp^1ZmJ{Sf=yI<~oW8_;iF`=4l@dm7pct$|^MyY&@4c(?ox z@L)XL#>`ef9>chujy;V1yW;ggocj6FzQ)_UrJKY<;|i#-2+u>U*T6F|n{Mq44zO}Pm1`qQC}<>SV=dw)G@ zeeH~*M(fcOZeOvjd!cVX{JhP}i}W>@H53ot8Sq4O*lfD`(4;0$zrJPYr)R<6+dO@q z?9uQ4@36V$6j*HYTE+F@_w@XmgCV7VJJIHrJu|jBrf2zO_Keu(phwe2mhItgZ1LDe z8(RN%;`j8LSrJ5Fn{YTqo7j`wL2-X`&0tS*gEiMZz9Tlabd6;j3L4u`kZ+K zk$Byrjc6b79PxZ{q&QZ*M4TyJDqb#fphkT+i0i~^@n_;r@i*cg@p*Bt__p|-ctAWN zelC6`2GEGi-@KgyPm#=bHuN{PZ{P^Ylf+BKrDCO6L!$fCv0cN7wq4=IW)1Rg$uE$Q ze<%4*lHZp6k>o>?zmUwaDa*%kDbpKUHI`qpu}y=&vHgU9Z}}VBPsqmh6XCh^hn%Ny zWBUo&*nT3M<9mj4{(|`!8&Ghq_Gfx1yr{qkL z*G|S8AdVLKii7^VpOP1gvqaO+;a@D-^moW*lCKf@nv&@^id)3H#RtV5;*;Vt;!EN_ z@hx$`_@Q`E{7kGBZT2JNZ@$wACQEK6wierpokTOki1?lj$(iyu=L`I^Bo7luiBrWH z;yjU4g)GMku}tJEMf!WTqU$B!BHkw6AwD3Q^9|`9k-SSZ=NtTAmi(G%&O7*jDA}_O z{ZumNgIJEQMVtK>a#PWqcaT#hN5l-Vub3s~h!e!g;&gGgSR|U)`_O--k(+2C%;Pm3>#=DbDtA0@vf{#E=?#g&& zpIGO7M)+{~dp4lsB~KJ*iI7aE4gi8KJ9oGSJZGsFR6mN-((6DNyP#d%_pSSDU0(!zlGRg3qF z+r(YsZt+ENulSa@U;IQoB7PJ!~&5v5!5?REEX>p zOU0|j>&2glw4z}8yTtp%2Sx9@N{>o@QhY{yN!%yW4uksM7e5h?h_&KZVi4mg#`kPN zPm$bOq$LN#)5SBzv&DhpU~#0FCwjJ?mq{)bFBd&q&#NVSww~U1m}o7+{O=I!+j#Dj z|0CjV@oDk9Y&>ayLj9g?=jW0=+s-&VN;5n`Oc7g%o-OC;lD+RT^_G0TI7l2WjuvU+ zLj8qev3R+-M)YhqX$8ahTg6|9zY?DipAvs7{!a94HUBF4p!hejR{Tn&WexLdDz+Be zik-!7Vy1Yec&=!^%LzR+&7r>WV*T$q&6WRrajCdmTqRyB-Xwb8eWI-o_5V!tzVoz0 z@~_3m#AihFolm6OEBRHC=0Vi=vG}RzeFy5Fk{vwjF&>SE$W~$pv9p*in(u=m9=e+q zKwEpycMwf_T(%6M-q3pvtpEHMQFte@tJp)V|2)`N&jT$O4wETQU$3+Ko)z(J-)Tde zadw~YYeRd4gKFGj+&QSO$kVlXm*w8|Zh^-51IZ(nv{ z`INF-%iE7@-+D)FX!p-*1G`UM^F{s_t#;HV8tK+Gf6KS~{|$1ok;`_Z^d6LBb=|)& zz9v-l>l`~LZqxGZ2~`P4gU-;LKCnMcEbCJn=rO!3*yrl(4mnr@bo0iX#H0T_r_s?s zqxN5}{j&X+*B^iMsMX|G`x2`fZE9MRKd15fLG4Pzn|Exou4rfX*=()ZVP`hm&~$VB ztZI55!-3J@uk`UTbi$Lw4q5&*D+ zjjeJ}Q?t@-T!mS;wp-u5Nx7k_xQ*Lut%_~1&K*;}tu|10Q~9;!&mS+}`uy=5I<`6< zU%Ra~RI%e=I57R-N5$J~LuK}W7mxpV>$At#V86Cw>*L{n+`S{5x#M60Vticu3{r+O ztRAoKi>nD&g*L{s9c~S+YgBXV_Rz+-s!`>k^32-ch^+F^I;4k=YdW5C+&cF3@v^P? zr%gZje(}CW0}l+!8gt-{v#g3S2M%ToIWS_NQxU8RtouuIYoq=5CV|9_5wxa#YcL~F z6aV)nPNX(8pgcQRv1VU#P1CBz8=Gyqvfbt#$s3w%POfosHt%Sf(_};Abyly^&lWtC zT$Qz>h0li8b6ZcCZ)ch=8MLp(`Ct#iPZ2!wjA!fz7O!UBAQ<12r;Q!rtQjm>KfuGI z^99|VnFPkQpV5bFKn1!?Gd}U0Ov36l@Hwl5KEb%V0p}CC`(I~#;@dIKaJolT@i!dD z#4@mTCc*8TIhenX@TcE}{N=#Z890~DbZB?7ucY%{I!E0IXCN5A3Qx(l+=v z=J4O1&f5GEuEreA+A}D=L-9F^GbzU7I^MWFBhR9EKEz~W-#VLOAw@2zO5q*~#-!DV zjd62m3~z-lrC3fyb9m(Vc-VLV#kmt8^69QIr-WQ_0PZSg71wz@2=`JdwCwp5#-a_9 zvGS`CZlQoxsf_Sv3Ns|6Q+N+IV zB1TiBU0@U~t{#R2ebXM93%3!x4hT%C1s6sQg<^X1kk&;|LY*1Y05%F3(puUOLUz z3BUga70aL|4($TN(K#q}33jv?!AVcl=I&BDUNQb-Iblfy8dy=@4O`Pd4TT_TDvzMC z4`y+t(<^x#n$>5U%EFgpx2=i94cHyn57p3diz@_c=(yVz!Zmd4bcLiEI(EB4N(~(^ zV~24VVXke~L}EX7$0}Y~L&rzhVIfDblfZvPO#w=;YTj$AxfdR&{wJyxY|2s{|n!0oPgh`if)Pretp-}O!;c>#b0@go2q8=*Uy zWEX_@+rWP80bJI|_pswiKzx85-YdyZU2puFZ8<7)A9mR28nVLtHwltge7IMTYy_;5 z>s{=F=IZY$DMO%?1V||f`IM}TDVgA1TXAtRw~!On6d85wQT&e*l9y$;SCDR5##7B< z>?q5FMG1kc&E?IXy2Pcy_Wx z>sX-M`CoMF@<9nhCi*xpdMX_7!4@>X{NZWlZB&CTTL&ftjiv^C(2%rp9o318?WmB5ZQD;0Y4 zoGY;GYs9-5C{elGA%;IGxg+3nQIJWH=W`oaeAI zd_sD=j&0L=rgiF>0o&GA1J3Q);ld8>X*fIL;(=|?KfCj37oXqRdHt#h&V7LhX4#@P zr$ytYFD@*ZKIh+Jd^%-H{@`&IZ0j=n!P4*FZHl@m^Gs;{R}4~JyFz0&XbcEV@jNS4 z*_OtZs-@xV_p(;~p0l@f^y=EkV&%AKZ;Te;WcI3RjXF#AqDMy;PR7!**#*!D>)Fiza7$Ip z7vV1SgKbrdkm%oHtBO|jEd~33ZB_rz*sAj52;PRLF0&28Z-U%JD;UFt5w9iOn0Pby z*)T}k8ZQl;R=*JJFX+(bgq6BN03q!-M%UI`8k~a_n9j zIIV-2xr@-D%?n!!*{_e2E-CP%zC`SvK29ThY2d_56U&-Phc+*44P?K*6zJn3zws$K?td^q$rPhWjo)h*D+`cYppc2D0{xS1vcJGU#FVOF-@abx(y*!}U&fTBfA zpp9YN>)WbUBi`9wB*mfld!L)~9}%xV9okqvZuM)mI-B?O`^=Jy&S8OW<@5%PV z&)ZlwZltfdtZk>E?(pPmHB{ZS3!2m%3%|bocv?RT{@&*4^JI^H|Nm>N+RTceVb~@d zc%0N$)jSWK+*TD=Zw#h!+|Yq}F3={B$D912wyFb_E?4AejCv-BGsR2A%SDbK8IR{F z$x%DW^NjqNxI=tQd`@J4XT1I5hvH%JnD~{Lh(=@l6tSh4DyE5D#dOiw;vwBY$;S2$ z@2| zJlj=c8;AU#QuuQUe?{^iB)=p1Z{k;C0xlZV&zD+cN0G1gXiJ?*LO-2=dCj8SN;H!Tkb6qb6nTwhya8g4I8@9NIX%jFlf|iG zkys*LDVB=sM9;RhTJje0=i&q6uf*SoFNmDLV*am*e-hsj-xm*wN5y}Ld{$t3zKtZ! zOJ}f^WOE)t?j+fqN050hVEn$~05MC<6FG6ncvHmb;-%sO@pAD>akY4zxIw&Cyj#3i z{Dt@{@dfc^vAzxKyYlCx9Lx7N@$ceSB5#5WPY@f6Ek#ZwG2EP&U}wpke4@WOKf$vl zpDX5woEl@iv7)gphkS`-zKCY{TyehW*}8J3p5d#+YsH(y_2NeHHgTJ1&S#|mjbv|~ z(`O~WAnp@i6U}*zbni?4L_8vz^Bm!P*kJjL4LjIKax>AK|L|`s*|UW;*8%wR`&Ufg zUo_VP$j0sg94i0svVrC5SJbmaTqzp64EWc#iLF-n7Ll*qnf}+}lcHw}`;z2+BHzg~ z{`=w)@iUPx=^2g>!x}ahPZisXd>zJkXNbK-zSXDyAaSIaC-OBv!)J>1*HOJf{#S|D ziEG7m;>{v01*q>n(OXaTVabn)Pl_*yFN?2oJ79SIz z7M~OMim!@qihmJ3+uF}0*SD#yzpiR0JQ%Y4T}7H}P|gxP+t~uiQ^gr#kys*@iPwk~ zVx>p}5bD2Q+$nlCvrkBVO8l+(JMne#4e?#^1M!e}RQ!kdwHS!Ee|yoh zr9DHkXG_~p@_C}SJ}PZmSikXNeVf|3@}Dn$*E*>*i=n? zeImXsYV+DV63H&TI^{PH`&Ps-l6#vIs? zc)ATM(u|d@%XTbojelWD%d!7l8{TbK1=nMh)HLUa)96hLYp|vyRE9T7J*o1L)n?k^ zj%y=_%Mzy^zAJH8EBJIr$T|HFhc3-H9KXENVSDYe!#`Wz;qa<9GY)rNTX^`VZI&M1 zf9cLvjDgt0si))Nz}n2i@omx$ukOy+(+=O&ed*zME}ee3qtVpq@HNZr{xc5$ba>~( z!L_{)+X#L4(&EEEJ7?zM&XdY^P}f<91Ir_QrsXU>{NANY4&Sxh>Uzt*;O5pj&gS2s zmhJXVV*MtqLyoB1@O{X2=HcKu_Bqf!oSLa={f>TzJ3>=%dAJYtTz>ec%e&=R-QU@_ z^l%qQr!NmwKYz%&^!Y>f^6*it`&l)8PWvy*Ys&^F91SNp2cNS`KO6N>+{SSAaIE+m zw?4EffE8au>#a?3RcSfa`mWns=Z30#e`syq`Qg`C-8FIBW1j@BcUOC5Z!!OqM28i$ zcjDL1#)I75*z0dtM)fQ{|p#_ zMhnMvqZE$ka5%Q8D<9Gw+CDn{1~XbPK4P*6o2TV)u$pSaL4NbX*pa@4NFhG?TA_y# zR2stM6zoVph5M>d3j9}u_1aGpt!5t2MgkRW;-WHdM zq=|g?4A#W0f+y`oyHVUCF_6eJJ$OglXC@T(qF+d^9&BX8QuR2cNVX za~i-E*FsD##3HK~GLYlxWG=^Qq#l&G9IKJ|2%600SdDZgr9v#SI)UjPG3h*s|0tEr z!YmsZrdI^g@8Mgr%vl@Z_-jj^QT8(fQ z1!LK2L_S6|<`~Wm4dJfW_*^Kkr|^*R=8WFJ`Sm933E?1r{|8x%p2Pw)j7q|ADMBW? z?ye-eFBTNr3ukO=11F4;2!@}yZfc5&FqUXxoCQRh(S`Lw>5$^O3#Ilmk@E>paXzQ- zqZ_lNEep96yH+T@2hK0C!zhs8%mmC5!!>l|yFyA09h_@GNUIt;mSabXmB3rBvjqyq z;e5S?PdQ`6y3nG>s}mOK3$juyg|~nx-7E@M&;#5O<$EOx!H8)I3=q9SQRYghEZ01f ze*wYbz(R&NVw__MUdqBS>2nu0rNpu#Bd^F_8IZ5pTH=>aHn1-v+FQHU-AF9}zrD;%>Zgl4n{fzF#L6Qk!7&p>8#K>nPyv@euDaVe5N{2=l zDjkW1O6kejQW$^|d$Bv#6~P)hI4c7oYz$=GI!`p(@WXOYDKgCQ+JSB_ybI%?K(H#@ z>90v_Em6kca~>L!pfW8U>glVumMDwLV;i#gc@fvmG6$@Rk>s=3!`88p-HwgwmR3WF zO^eV`-ZAr1GBvk`G_s2z&1kQyz@5!*GRO7LA(iWBl2csBb#%95V~{H)ORE|bwfx+50Yl?5dI{S#=A*lmcY&6nTj2WhmwSMWa!unJXy$Rl1urqt|apPX(r8FkQ5jT7U$+WBk)N~9| zxI}@ZTi%l3EpXo}e^N@L?b}cfdBlxBigDS?P@o^w!vb!aF|2Eb+&lm*BXo@+OI-I5 za+my>ANv>MoUCshKsdt^+@(U7S+TW0dA_-4Y(@>qvy67M-r43~?~~!II{nB$Lal90 zAogQ-tYxJ&bTBRa5yNcEq88q~5b#Q;D^iZ{ij@z&DHls3=vN`(VH*rJEq-1>}{ zet0YNw(fBMue3m%)u;D=%L4I5JXAWZB2H1nNr^a@MS8dI)z)c|j&&}brV-g6a^=j9 zSUGb7R>|zy1M6aP;mj_*VHgOD!%QaydlL3!?D+$nCh2E%gMT0AlmVH}wDevGcb2BZ z@UU-BXCXMiISmmPrDF|E#C0xD|9{xK68I{L`@j44<>lod35OgC_z+YO5|R)R6%~>Y zZV9KTRBjB&B?Luo5iuTZxzuoIs8wsNZIN1QsRt@m@G4kaZPk|cZ>{1{C>{}P{eQo+ z-+6EI2tw8NQ>*iN^S<-@&CG9SXJ==3=eskDj1-aViafpqnU;sQ74y8Ad0jf=&By}p zvRLOqoxPtg&hs9}!VX!nfml;Bp9^+g9_!NCMCZ5d+|k4GolWyPcRj9i0oKMWI<3ya znAa`t?v2j#e(1))l(}wv9YQUA7+7&K{;pM>1r7OeZo3Yp{XTc%YxMDzC(R37^}L#f zgOqsZtjyq&`9^;25X%WbH^~YbXJhWEhdF#GH zr^Qj@v3kR=?n;=(8f{OSI%BN9AAfYOXZk0n$!1;bQ|q`bFz#ghN8vHV zU|f;Vf=%Z?m+(=;cT5+&6|gr91EIHhn3C^zG_l45aeWcyP>*#B@JzT7X`4cUu@rLy z!gBHPDrj#eB6mS&osCO=kC1DzRB`x3&ZfH3@+Efhg}Qv>!g5ohfszeo5H z>~Ttqb=Dr=ZwlI50DIg&mM;t5+Dm?q@MIKjMAC7i&HLer`S5fL8z0?!gzq99M;WcN z<>Px*Hq5y87{=&s69HL1y5#o=mj&ttrsMn35aB?voe8kF8#?Rkwupi1a>6ap4xnrX zy|u^V!@3LFD@8lyK&f@so|P>I_5Y6d2+?evcJUpswd8O8%d`e2`;f!ESLk2J5Bpvr zdvntt@jWb_8~n~Rk3W%=6A_2?sJ@ThQ|ZfuLxp@?qMfnA3gHalLg7;3w}m$eZxP-u z+$?-R_^@!B@G0R=;ctbn3f~ll(ZE=)#=;YXg~D@${fH@!bFOd*5gpSg#ZQuaiDay5 zVdCdWUMBfk$*Uz-OTJC=_axsdnfwRKw^g!v-wE6Owe;pY>5%^{`E8}!C;6aco}{$H zNpdWAw&WI)PZpjkH18QAoq2BwXx736n)j1{^OcT70_~aikzl`CvUv{)^7ka)FEsBH zBK=Oue-yq(MEZ9n@0Uy#hW6=L|2#v9rkw)Ww@~JADA7E61KUY%FJzy|__Kti!ahRN zJ`sPB!}9 z6s{DS^9c4gNWMe(ec@)IIj@k86d=p9Lzw(NA2~tBzbX8?@B`tI-ruwD?VX5=IPE0A zuV>%WGw<&rewfmY6eh1(IZOJ>grp&9*M7Hro#b1EcM9(oZWi7zd|3FH@G0SQ!dHa5 zg>MMo7P4dE_QS$VVUF-fYgl$uy6(c{_w`0fKT0@3SRo{x%Iz-}UL(9-xLSC#utxY@ zAqiOKe^9thxLvqY_=4~i;cg)*TjqaH__2@=5!6S8SjEQ3$!lD8l)kg@G@<C>Dl-4{vf@5FK>_JzYFc!mSo(yy>wwi;W5IN!kDmw zFjrV4>?S0!B*QTrwS8u=?d_PB?jGg_<#+A8e4yg@iM8~Y(+@{p&_~9;Z?G2@TUy1K3z0~X3 zT@KzoiUd~3vtggG;qHdrwfJ}Wh7d1$$qp|b{g&4xH(H7)ym(Xr$-9h)$9`k_Nj&-b&(= zN$T173omn50HWc4;va7%ZB6Notm%Jdvd2=chLUe39iaHQ#87%JGj2;sXOTddrt1(g3-O?gX5B+%G|@qvl!%vAbfI2jgyWC+wPF3|C3!D>@AG z1VmQu(`FNlR~SplB4N!bmgcv9kigP#8L4uhaZFkW4?_g*s9q>Z>^;XljAN`{_6rD$ z;K@1zmcbh~ngv_s>l2lI{zhnSGuokqyW#PYlN+e)_%>J|Zil2g@d0>{=Y$904XMt6 zzkefbDTBPcHG$o?DI?B&G?kX7b$wcOJO<0#;IUf-TBl_m$eq5L@DhBTZ(g>9A_UJ? zZXFW^T~Ic?vSY?)+=E#SK!m!c%fN;Y<+GeG`!YS1v&K%Jo%pciXI!D@Y`2gs_4HU_ ztJYrQSb!IgMSmLsKiy;4sYONLzp)%nkvFls*QSz0`Mg+hEBtxg`jr=)=v{;FL4JfU zN^@pU9!Y@3=4S!8A=T4e5Gk5%q z>1YDuE6iXi?!Q&h}-1U}KDLS#0z4k{MIyOq)KNiyQf$ADldI zV&xSxC)!n`>aOd8PcIreH_q^yw+`Y)aJ3mr zCMSyeC1j5Manr-CKf~U(9`3l0xdHsl>(9g+&zGGtb~p=xmz;<$QAI)v{?*KJ+Caf{ zco;A)IUVEZPKJ-dA1PfYq)Fax@XBbfpM8`LU|c3LaUB8c>~>3`ARlMl_C~loBeE$J zDe$z%at(vGc@Q+;t=YwZoQ<0V*@hYA!2rKuWu1*12SsqZ8=K(H66v^IZqIIa4#GAM zf=+8Z%f}dyvvHR~4%+L{ynfEO3h8Vfn&4c&90ufU+%m{Pd*uOpnTWIHTZgdCLlgY& z#?=9Z4f19#Xm1ScaX-1gyg#@0{9Eb-7yN4^O6K}$^ImvjK0MuDu|5Lpz&gg!Z-Ga( z&b0cGDE#SG05T1of5+{I`M(C~x+O$YK8n0;4DLropk5jy&hAG;gae1&c?R}ghR!;> zU1FeFIu*#s*Hy_GqbVADJU-lJ&|Wnn`8;f$wP$6ELH!rO8T-@jtaa{f!u=;WVpMma zy|Ts=?r6S~X#1^~kgX0!9PgU(5@ua`I3B|-vA_Ew)|@$qb};5OKsZ=ZDV-=Lqm}e>70?Foy2I&nqhIqq;0nPUlq5rzu8Vp`p`2{d#7rU2J<4o%MDwHu>?E1}5A}S1gLtNJpwJvw z=toK(C7dLjBIL*u^II-;nPm3Y)SKfByiu|_-jHvT%y(^=?#IFhgnWRd{&C@xLUa6~ ze_rzMgooo;_bL8;A&16jH!8H;s(E(+`s1WOUU;&wqtLulfOK6Yb8wCJ`UwXMO*?|# zyjuXY?P;pwX9`U_Li`fRHwaea`cYd`;qXc!k-Jb3bzSOyF&WkN!~3q?F;(9 zN!~By7%1&WgbjoZh0TR6g(nI-2=j$S!ZU^E2+M^1g#0!!x5qJAB8MD_Q-mBIrF@xi zq3}xKbwcy*0@B?m*{-F+F-zwEq3}N81Hx^>?ZRIPe=X!7C-c7{GCzZ$Oj>uV@T7a48bVuea+VRE(T}hFF z#2obN%G|0gwV`~l7E6k&mT$VgIJ9!qt}V4r{_5h9yF%;MMlqAzb5{>{Zg$)a{qcpJ zMJ>kRt3)$f@C!@eEegXcLe;Ne5$TjQWGuF3g0V>ZeJ%F&t-j8m?kz6MEc41XgBkfQ z{N~!wrna>y!0@J%YrRcwcYI|Dn#d-6O{j2usnhArT`Bk~(~8pOrS67N_qHu726ItZ z8|oikvVL=WpSh@BQku5UO$)6%{=l^#t?ae^sJM&u*l+j8sQBeLXvq%Tg;_txjj}8B zj>li<#A5!3Qf4E)H0>I;z?2G|OaELy`rH9Xjk zTLE{P;79^*DWN57hDYi}H4O0968c2JM%scU%`#@mE`Sd?^TOkReksdsDM2CFGLp6+ zO<{{knKOx5(pB)5)?j!YJhHN|yy-!$+mdiQ!J-7dx6%YDo5PcQ0T@T!+3=V}93rx) z;xcHFhm2A7&|#OMF^(zyof%Bvy&GmF6TSs+zIwruvWUu?y;p_m1a&rKM-3}G-Rgn7O?L|o*n2|Sue9VS-!YQhb^ zIzqhFSL5F}bN6jRVQKt=#03O)2L$sp@m1qVKIfMV&UVl7n#R0}yn>eaaDg`klksA> zD7%qZbbAD|`p)gE+*S7&~nzpj6PK#5Nlt2=7`HD~gLaVAG*K}=Iia2WAJ z!Z~*FV_bKlUR<46gWr5;p}xs%X61WJp(Hj#>va#hrAm?r5-yw{Cr{#w@PC&1c=b{x zKGpZtAxtvSvmTBwVXymd<4eB$OZER(@g+P~*4gW5A1Lrl5O+-=oD_SFy5M%XM(8zssF1U9;~)pO+Y$rOF{Et@eH5PiL7W3`^C0M~ zN<}&bUb!WHapXKGr&GZy6LpdjkUYc;49ZtwY%6p^e92@7n=|4c>&f zpuJJB$Nl5}a@fJz;|(P9>ljDB1s>UFTK#X3?sO{v znTGB;cpIjigNMs*49Ky3biA1i?#F~cy`bsD_oE@gfnqy-VDDwx z&W&;%jyEym+=zbw4V?VPLqy0=O6DLN^=8fx@b8j8R5}+Y9pkfw*u6UAujnR>%)XK1 zvdx9&i4Afm$?T^X&#^nA2u*u~%n?fJ&AanJ%ai0vZ+Vh#l6wk!3GG}oj{DNi zNFmn}pgdl9v2doaQph1urn^S?ZQ*KRGC%TD>3=TVD%>V~R%qv@y(IY+A%|JHy}iN@ zg_bAraIs{(ovW55*{(Iufmz0%EbJ`oBINxTXsK6&+%zvD(fimA{{C~S76l?sxN7q<=Se36b4}dBRnGd& zXSZ;>6tuwL$2xzW31^uM+7oI?#)flDu64OCZmXTeWg{`ihQWHr436tOC@9HP{Z3K%{W_>cISw{K8}bN`9rW%8VL%NXQUF7qKq^iG3vAVU7^lD_XDcm;eGFL-W0 ziloZT?2`VJMnKBCn2`fmB2Ed)YC^*UDK=$oP7MPa;Xx`PijZ-P_4o8b!VU1KH^K^dGdG2$^a+Xb#G$(2 zN6>D9$5sdrz#9r@3j$l=p~t^*ED*OtI)(TIJV+SAGw_C-VSqacy)9*soJp8iIlv|b z3pBuIftZ6eakv_J9&s-iB{r?KQt znlQF)}^=ei8FgSj}JZB@E-^lo4H%ih|cBg#F9ce`Y>P@KR_mn0-(NTpZ$# z<2*UGP=UBogfYw(ckeaA7$nm2y3faG+Ka*ugAdx{x8rs}XPu3k1cePV?jJ}uijM?x zHf|i`;C3Hug0Tmr<94|{yIqdA**pk3=i?ba#(?A-aXBaj$h##6*<-z(Ary; zWbeU%y-dW}@~sQxLD0Dt_Lf;Afw-Fx4wmm3*yDb3f3x7Ny*m+R_I!9ceoKV!rdr21 z`g?^oU1JoAbzq%M$GbvgpK0~WknVIV0GW>NId~hUycOxXF(AkC(LDtp+>aLm_0kw| zc0U>-94NL^3wuYyudG4Fd=%tJ{K_`8(_C!Bx?tI@ju_N`&95Z*l{Zi~_3$hHO;&yL zQP^q2vA_Fw%tzrf3;BTygkyyj!pnpllVG|kp;@aCGS4sSZxP-u+$?-R_^@!BknNfI zb_#zhG~?~izbV;_qeC|H4S;4YJkX4f1J6N2qa8b+;9Sb+K!*@=p>o_4fiXVPZ=ovVBtvNC?T&4%r`~Iu_?+6h0BEIxI({DvgJ_>e+K<+ z(kJsN=J+E1LB&5Vd{W5%joW)(_&cFF&d|Rud5>_P(DEuDOJ;{cJEk1~n@MghH0=WV zQzTm+rK{vKgvCNT4~4^Vw0nVYtZ<_6Nb^trRX%02?A|Z5Jj$bzc@MzyJR>yi3GyE$ z|5f;waKF&-cS!e%WXrE`K#}&E36uF1%c~S9zK5_>XkM{L{y~yQ2rm#O^C{D%xARc0 zkZk9nER$R%Tq(5kP;Qremyn~gEdPDNUkD!&nlWs|KO_0q!WV@cC1w7%g!_e-XGy`u zlJVx--N1&D&4=J1+qM7r;WVbp7ZwTaw|jd??k(&uH2t>jb(o)y$m=!nQ}~gtg+Ae7 z{*T0ubjv@jtDpSH{75yf^>ByqBVI*T#lVWvisx&?TYpkqwyROa>f(}JB~@6PYf1E= zS37!7bz1wKeagm`ol@4etaU}RifazsdGOb@(Tx{XoX7A7H&;B0nJVXwx#qy#2mes< zB6SDcZjaVRH$7ULxzXE~VT zJ@DQA4`6kz0g&G_Jcs{9zkh)7@Iz0sZp|))T@Gov?DT%-YmD0df#W!qY2D~mP=VuM z>+*hqQ^d0z$5upmob}+@b+tG%$>S26Ubkt?6;9>IADE9Nhye4!8DEKMD(^GlkErsO z*gB8Fp5-+70fWWkd>f-7pd4n}RW$qr&(d(16P_`Dh2LmPaZ{$@3y8STuSQBI!gsCg zYFjO!Ss3A&xgf%JH9t~~B;Z5Xs8i;+9O+AChn}*`T@Q$c`Bqn2G-YebHxNiaiS{3h z&sfQ$_;`HA3a=n3+frgkX;#~+pwTB%PJ*0Kj&Nvx$h{M3yp7Og&X`$14HXC%+Hiwb zP=pp5y_4nUBcEGh_6K@1qk!o0OVioEW~h|G7(&?{DE6Yrdys5iAl$NT5SJsA(-Q%= z4-5A_ili^yzNV~DipH z(F<{n<|A-E0*!5gCcNXA28}YZ9A(T{#jeO?thO2NVMd$4WZas_crG#xVa955yC&mX zHse2;(Izk%8?poPi^@!_dUyR*He)-)nxd8<(AXw08ONE7$8aB)BGb2+@nN&IIW`l& zuie;2noK`6nb0sF!4{gbQAWf3|8H3Q%q(G+a&l(h#<2_+k5ZW_jz=0Qr7wgATH?$I zS$Xa`nf{7rOy1CKM6se z9V~uOB+W6ww5YAa%uKomwFfpQ28cV}EP~7++y?J+T@2msM-Z6rP!cT9Bp6JvIS1D; z#N+{r29kMn28+c;Z;d6sZI}ryn>OaZ5Ehu=P{MLwOW;ETX3H$7VPGRXQgdT>`#}ON zC(&F9)58;{htTwOCf{&^Z+cG9^zek~;ns9;r8VAq`$Zm=usfJ`SqLm9hkxT3%d?N4 zmm`{!#<^fAg4`>7NO1v?rv$=tiR`EY#1Jj8-{IUD;s_Ic9xbr&A!p74yAue{g~~W) z8vxJmyqyaiA>j8pe$rWiq_YA^`9_^_?4JDG7fNF~9)HAX1c5uqnj-os z88WUN{+GZ9zE?(7d-xQrpjLQd4TCH=2rdF^5p9z&6W$PQw7CSHIl3HM!yqdSHVLcX z%`$EbY=jSNYaPT5MpaJW5hlTPJMd0lP2lmXLvXPmsvU%Um(b0&D${chfrNQY1QrYJj7}lK^5yB(*&)G1!GQ>F{l~? z0nMwv1I`?N^z1-1w`3eG`v&9NI8wt*Zu&g?*z|pa{?SZ21zMUUOc1XcbDV4zB9EJO z=E2)vvi&HQzyq7*|N2fJKXuN8iC>a6@$9-`qi4?M~|O2bn>(bc@?PF zLn%jGO=nk505gPmRHwL=3O_Z@E9Ai$@Py;?198*yjz0k;W4@Qx-OCv1o!{^H}b^_DN_hwuR}58)dY^lRH0(q4}-f1f|e%Z+s|=-k;GmSrJ|&1=@g*>k2=V(GMEe3uFfjum66H|&8~M{V--o`ueg zIh6(cD`Xmcz$)?Cwol6&9OcT1b91K^L9VQrGi@Aj67-X1URIPlduHwgEK~puzhss> zcHHE%D#p&55X-%I!sTOUP0B5d|xa*=bU8(uQV zPyXwCrT?Y3x?e*}T7eITtsqh3Br5+k{?c;TI*17dTXV-oj~+a9c=5k$wY|?ZVT?sr z!=@cmP5V<!kxXZujav#u(B6cAJ)SeReEyx2 z&FwhP!rpz>2-G&XCdpnU>~a5CzASia?{CIJu7rXKTgR{3q7jV|zhW%GE8+(X6@G z0y$YH>@(_coQa#Wx(uhi-XlHxx_<}1Ihc0A&s`)OFPtg7T)0ShgODS9%(p?v(MQVn z34bAcOt?e1Q}_qrYr;Lky}}QK9}7dMINDDW9wQ_tPrcIdJ@*AEB^4pR>Q2as3e6(QtbRzQe6?V!TtESvma(l^z zl24P|Q*xPPGt!Lw!zG*Xa>x@T8(sPr~-iqy@;yeA3U9ZmaN@ zL|hwo2%ne!Rmq%k!1%q=eiZUQ@}2cYxmTM$i{3{xrp(DJ+$KkmRAl zanfHRhN?#@Y4Z@qH-zdC8`tJ)jOOIw}?6H@jU0ezb^8BY96Sfm}6m}M} zpJ%$Wgr&khLJlD?-kf*9iIOJ^dF^GqIsbsXc2d4hXwE;#mWMXyA7slvZ&tedg%1fI z74lj_d%X4#eCY6J^B8)| zKlhW~^3UeHM!e;pInK`Q&lFY)&6;P>TmJdm(vwYK`gOuvg?9??7AEu1WJs9L^b5dU zl7Az7MYvn|hS2m6NKZ2>I-dGb=(y((H2k}JX1m%@$M-FFpE|R*xO;@m`xU0xVfRg- zOFDulW3mHxpUpPoMmZ*J)|K>5EJhGCK2K)v3Dme}*OlDGG-vSdv`I`8PWc+o)ANf9#fYB$<3`U=K zi>bVIO<62PpU=Z!^zTcVjX*kAnoqeuaYjFcFw57^jn5%P`UTLjnS0LV zi)t8H0}nk5bgLgEY=p0eANMypoQ9XcW1=R(w>KwfZ+ODqaBB~=W*DiBTJ*&zZNlh5>FBY$xF| zcu~X*E;lhl3I2}Z17QdoN8We^JdQu%CV29~Jml+qHDM!s9bULA6lL(Jfw@F7umMs% z5k1R9_cPJu_&2T?|Nd@_B20n@Q$Lr;;v+m0U>uFJQ^bZA5E&oXP$GI(AUeJwTK98| zLddwe_+J8_=FC~NCe)){kCSRBvSOfGAQdFzn3@eN4UJ1tw!J}>oO&5j-T)t10ktK> z5Ih^absKF!7?jx&hQ3mKmy0HKS?Fa?>H*DNZa-*VSd`c96t6Yt*#|+-Zu?Yv)+gBty83jiS*y`sp3^63 zK}iLf+IrUPJQ6!=DyCjuRuoR%uV!IgsW^}P^DMPw(?O3dT!5dmt(_0d#e!{gU&h|Hv@{Gz4wmAGa+=emkw|3El1eqLD2aL>@l5n zHf|{tL3?2k@z!1@;;cR1P1-!P@i^?=7*N>Y8pH+dHGw_uC(HL~yzEF6o;-kcv`7DA zVZI`M0G{Jgg$Xv@0|+DgOdHh_8{>Grb+&xZKw-m-8;Nv9HW85fOSc_9xF0P8^+J}= z)=NW#1I2c3fIW`4TW7aL^lu{lnD#Kj@p3c=@P@uU);qTuv^Ns%v;%b3S$kHt7}S5w z%QkXapki1j8{rS-W$Rhl)9|wYnRPw+AVa=zvT(X^zL4i6622t-qwsa%d%^=kRus2qcpqSSj}y^fJ}G>fh=y-?7o_{6A+rGCHgW9e}ijh=lHLtGuRNLw-*3i^7+Me-@hdjdXvLykBVAIrRUOoWk}4IZenxSW{2JlZB?8BVD0n zj?gmQIl>ZQKcRU~0rBR10G=;BM|GKRn$Yr@b0u>`mGPF}X9UZ`k4EX)vQ3(a|j_;!*lpJ~o7=q;al zrs9i*=Di2RoAV2Jq4eX07YjLN&F#+5snZh^OO;`%g@BK zVWrT2g=Z@&Qt~6um;D(1AY6)nZ{&afZSQ?vMRvux6}`Z+{i3+PVcGhCWlOC}J?MQn zde6<7`8&sywJ9qs>sYq>9rpsP20G=}@8Ba(SoL%DJE1A7uqNo7cPCAm^X^~gJ&L$T zq5t(e-jwIx@#b}XxA(lupm)1niByk56P!8wBDlBA#;r9!%>-%%OIpy%7V>Z4#88 zIXh1(H=5LCgmB6(M%>TSrQ2kqN#zhFh_*tSiKcRkL?8Drl?7>NIHE7RRBR)j2Ra|5r*Wk3c_z#M?aj_M)-Jmco@`Z{9 zd~3-)k0oD8aX4c~Qe=11fX^-N`P|zaq(eoX4{cU&n2m<{|KGr49d?2yr*#G`-A4s9osU^rok2^vOZg|8)$*73jr)G%byUo!~5qVmXgXD-ww+#5*}qANSt88mxhT-I|xDJTI1iZ zp!1}0s5${Y1uxHGo+X1UIVP$SCYfM4VII7hXGx>i!7~TuSu%J7JSL_R*1=;X)5SFm z@F)Z(tlkFkcB3jMFqVAU-N1W%HDMEc9X_ok6d`z?1lBQ8&;@04x97yrhlGw|lHd3< zM$Mcx^f|H088fENj$x=aW@liH!bB}IP3zJwqoB{7 zK4bdC+=-Y-HEOayMR3%#vEwTyPyeE)3Oa{OMYPlN%p^a5!6)qSXIw_~X|O_ALiAFy zLRnyiIH#|lHwtt5yt887<^9TwI(nDqc{zExURGXNp*K9w%Zn8hVisTDJnt!IQjc*U zhB815-H1=Ry@kg^?@06Z0u%O*FikH`GJHMvZu;k&dv^p%&2L0ULHm5(33_qDL!{4P z_#K~5F-QHVRu>IYHeBcIKQj|gTdl)3a_jZ2Kw1wE^uIYbuX&(rX3yL+D`#2wYHxYy z8uU@0Yfc`k_Uk!$wt9J+Om{MT6rMNIbpErYALhSJ*Gb`sqL?mt<+Rt=vOpdteGQ(s z^wwE>#ZX`vE$*6Q?7bV(@!lSf>E?RPat(pEc@Q-389&B=oQ<0R*@hX#@49gfEbDCC z7$}0CoAZO!}xu3mgz&S`md%T6U_IT@K^C0NV zf<30Q&c-c;B3M2Snp=CBh_m*p5w>|~V=3(M6tT_*d6yitmjip;Kb9{G-rBnzVdlw) zr%OX7z7c92$5w;evXAI$^xf~FJS zk7VvAhB1@h(SV$-7b2Ql+&zelN5lQRjR&C)@mzI}K|o#S*nG|XB)FeVsH8)qAX$ZaH_BspL5sglo;Tq^lo$*49{59~u&ADKe-r<7yDcEbO54(6*iw`@M! z367KHVwOw3PI!yZaxtczBE6k+YT74cj?&W34&k%HSA~BPzA1c1_z$7W_JsUt!UjT) zTvBh^C$NiT%e9zx34Mw5gM}PBX1?UPW0y)lN4QXUrI2Hx%y*-ZgQ1k~68=Q^GvUL+ z$AmkCoLInomeb_OHs!wv-xTf@z9;;L(8YZL({uEdXqJxzayAI%uO^Sg%G#HOYQh_K)MB2_fzSt$nwxusk=ngEXG5r_>_BMm1I5utips9s z>+}p)??73Q_XBrBq-ICSa>R5fOM^C=^KwZkayY!dvYE2<4^NZ(!D5m&mAQ_u$>XTqK~*` z?wP%6!^iE}_7swVViNIq$@xIaaN>f zC{(+CDzBv;Ifjs3KQ$9MJd!>kyM8LK!``o`8Mv4!qbXHv(b3dn010Y{mm%*7{`pI( zj%KiDIWu!Ekykv9L3qs6s>DB5W;HCS8@&lBG3&~_BM}Z4FfJMqKNU7vL!pqz{8D@79zSc~LiiS_Y z?xaP-TQNZk4;;D7@>t4xBqN7ZPVsSxq4cY0WLt_^dYT*(X`}EHDZG8ia6iC5mP)k~ zt42Vib8khW%u`{=EoCqly3CUp(TkhDm|~P-8Oz4;_{?`G_WnK+Ka7yRN5_r+5n|RV z#`dGw5k8CGg>?Jh3*|J3+1E0508P0=vVK4q$haGrbOFV4SwME&Ig_UsfQ(`x5G+(M ztAdG)cCR1P1)P);6)D(o8WS09!&&iQ*5&aaZ!o|mv43sEdX0wp|7D|7m~f;k!A%i{Al|2-7#aqT2m&)6 z%1xbMatQq%%(;W%quC*%F(CA?a`{lIX6h4BK5pXLEv%uJAZmtKs;Z_)+#Q?WL zv7b?~k28*0&W6v%v;9o;MVC2w?Oms7;~FYi^kba)PA1mWT6}VyXq%sn;a&J_jH6V7 z?3rWpQyE77X3om{7Ds#wbrLW#0^cH#VC9Czk$??Gb9Y-Gl7tCoIVY*CwlFOb;0evv zW*yr=&;@04UHQsXx1u~R1|)_VMmG!VWf=QZpO8pzAe^Jd0!+i|K87G(q%G$#gr z#~YQ`IoE5KcVcdS=fd31ZO%CBgj_E(=2gb{pBD3`##&=mkvA7v%zwi?#$_V~rX0mi zF7&P#iDYdlrsw5$?&hVBJg=aWH@cs9a;)R=-Zw^i?PCR0LI` zYY_8h=Xp&)FWt0wBwo;PT}%(@T7-2OXID&~RGFCAleCbasg$x=W5-uIK9`VK8uHVq zkU&)?7LP=z3zv~B!V;N*kKR?zs2pm_U?!^kn-+`w3M><852(*RndxGhRTJQ&;slR9 zLZ4@q$Vhc9XcV&EEK6) ztB-x+%sVHrEF^bIjoA`YiNb#QrXumCAho=Mc18+Q zFmNy7-x0Ffiuf0B{)HD~B+xM(ZugB#PRBU9li{QAM@rWTX_B`)(i%aWz0~urDxfw` z5}RzH0&%4XV+bj#7#;{*A?R$57o2XaYz^3?p$ne zg|^Fj;C>M2zz4UxALAx5=&ZAGmqHP=7Y*1-a_XpD_;T+})nw+xD)y&&(x z^Tw8M9l|ybZM20wKBie`gEv7DwAUWxCqd=PmoUIjK^`BTHvN<-D zXs@jCggcrwB5l9L{=F_AWxM9Q@lFyWWn;J{^8}2B%X5Gn1&=e4^+H5*a6%dQZW9rS z*k4iKMRrI-6YdZ`D>Us1@&6}zkB|cZ%=dxNv@ggmj|b4s z18N|-p|H8o48kBC2M?Lvez(lDGst#*Lo>(;nS&KfXXgQ#b_n@=>AxZ5=p)lzDx51^ zAmj)n<5vi87OofGCcIO)S$MzjA>pIKr-XK15U-WAZ`v!+v{#_vN`Yx?Pe98(@!o`T zk&t7_lm`l@2&W6bDYP7t>A!FfVcQ=Lhsn>LoOW!z;_{Nrz1RsWF*?h=bUVF%?xkCP zem9dac4Y2lXG50aQ0`^*8ylT)#m?IB)_aN{+m{_WKWP=Yvvy|gi#k|E&Kpoxj@9GJ zYr~@k?P=P7(4J%Z-M{&Vn~yu_9&CEh{ovSx?tx?%>Qv8P}Voxd1-%PKte+A?bXCvhZf6C=OnQv)eOge|AVTncW{H za0fhyU<|69mJ|)i;SR|zg4R8kaa|CXeHP;ek?~jqpJf;iLtA{$7r}ZMaf>fns^eK- zv~eWpUEA#nmfQEW^+|xU(83yX~=Yw;5$I_(=KOPmfufn#F28GB z*w{2;QN=c$O+=;m-S6jOa9Enq}}@Sky1VHB84k^NV1_pCZ<2$aHJq z{~AwwJ=4BK(GPGy|szujjt`yO^aFlztW?a#c~b?X{|6_CfUR|RMcX)(>#)%xLK59`lhoPT%qLO}MC0ch1 z0w9(MPr>`d5<}1U5d`KtlyTxEPAlly1c@0=h%@(Q;7fQ&t?8jP3^93tNXdf8ZX7dU z2sglE+RNM;2C98wX3cE~+yjq91l~t^&VofX4EXj&A!J;_-g(Tm9UcqtB{s~BpXU#{|*8vvBDj+^Bf_YFr=u^V$Ym1a`9#^sZocY8d9G z5Jgx3-`JTsZ;e@X?ox+q&$VVc=#3kIf8Uh(m>m172=0TKgkcsDWg*Da+{2pUuKK1f zAk2i1;Ic(i4BrMH_%a%k%r!~om?R7@fyZiy_&2Ty|Hbeq0D(EcJkBMuFbLz{cijM` z@W@S2(glH}VLzcC_jzh8P_2iri)Gl_8h9=-NaW53ml$M)9-)F(C|jUHXq8PN6;HZm z6+wiJV+5N`Dh^$p2)4|v@HqMLZyZl7KKM370hl(>D5&PC))?p9n!~l2mPinSXK!I0 z&rR#NYi!lry-KSD-UZKX+Y=@bWzKCY^KF9ASB+t`>k)oNhH<;&=3^R}HzS5`$9c12 zm`+CCFn#1Tox9}cp3tf@rj*UXM6+0am(GRW-0oeyEAme5lw0VHztuZ+WX}#KE;Q53 zez3To;Q@m*M}oT;UQ*I)=+FQ;6Q4pxmS)`4OG*HvM-S;Wlpg^zWK-e`V@y(V#;B5k zL;DW(|3?p15)eGZuv28Gq1VZ!adeK&THwm4xNB5 zI}^!+JYfv7b-X;(!xMgB3)^TD;$L+Enn1wh8K4|az=|~5ibvEu&D1!EOw)V#XX%AWA_NoxJ zc@T7VAhHJoayD)mHcSNkCJ$jDQ5N*09IY-A4UX64|!x3&px?me*`RJa45AH`d><5yX zdLd(F_oE@gfnq!FA<@gwS!e5o=--z5F)NP2K0(k};_p!Wk0swH`C-YAOMX`J^F&;8?ED_H zmKyB6srYx5zE<)-mENwUmVwTL<>Sl+mfw6s4zgKO4Ki1SBDdW|={QWybj6Yf3X{JD zHA#Ao?=t-y$yX9l-m8V*lD?XVbhk+Up5z}Ak^Wxc7R7H<{0_;#mdx>5?$4hkzd=O# z-;w@9=|7enK}X8%(s4WNSBboq5!uHQW5RaAj>67DUOSlXEMcjT_Z!r6h=#~fDB?un zWT82apFqb)%=JAr(I4Qn zF!_hE6n$kADM%Hn}x;W zjDJ6C*O*-SMmxu=D6Lpsd^)&yjKd!E_AZaM+gX5BB~K`8R<;T&M?P;>ll11jh!rGb z??$GKdH19#v3FDFUHtBndG6^~A;sfJaTQjPd>ko4`*QFFw;XTxuC8uT>8YhTV9`@| zzK1mKMfdMJCai@<7-Fq#TK{R%)dl3Gxkn&$0AWCd3tv+ zgE8nD@IvMe`6vEED|%$|vf~b&ib!6_eAat-I?VApm0iNv5fq=N$OjUCMMqvOvPUr1 ztmxQ+B3r({q9ZHJC%V7E?Xc^H2%_7F_xK`+ZX<5>MG)Oad;wxMPcHW&=6!==o4A;R zf@Yr-7u!+f728kT4I(;%ivc;kk?~8olH|Wc$Of2I?zvrO(%fPstux6-OOPvsrSLw1 z%Fr@Dg1~%-GOOlTID-i`=inNKm^?6n5910>%&3MDCYaz50v~BWR1)UGdrswo8U~iY zL!YoU3<~2CwuZ-`@NEqxEP)5pl*kij;n-O$FtO$MH;yXy*C`-*u(%<{T>}!*HC7mvHas8fN@>%FWmsCoHG)-fmU~RLU*p!wL~Cf zgn04d-HA=Z18<$VZTpI`VE#%s=wCh~3-)Wr#X5_5-lb-4oIkcJRMba<)S0?wX2&^(8L7)vh#-p_ zuR|Rj73*XOum5S1DL}-C$*Vg#jcXnS_`G;sCXqhziYM!6s`k+OjpwaP^u*PlzKG({ zFQ0fss>g5jaR&3VkffhJX{|n@iWM1Tc`YCMKR%fay(@eDAWy}Mmv!ubzo0c0%}^(6 z`D=d4uU&NO#(f@ss!BEp_A<&F0c)H32jMxEXq}BKg+jwtCMpxRY|W95_cC~#H1>Fx zzv>bj&bzK{M2a}n`9kWXVYzg0@-I;{ar|R zH2lTKMgG%EVp>-@D9Wl^6oO^K4j)tFl1q4{GvEct% zdjXXR2K8U_Qwe@*IcldKe#*b<);EWZoi-erHwGs(u8r|=90q^fUwE{0*m^2`nUD`Q z9B=2a0CBW%s?dzBKtE41&tsObqcir-fLwM3j~cL{$e{m&#nDB18-NcXg4!&5>2y<{^E4cUxC z1I@TIupv%5+K&lOB%<7%B^OCHB36NFF5_)lz316Q{e8*#~o6GA3*% z-ovyHZ0B;>WBaE4>x3(XHwrfhHwu$^ko%;6K$y&fJTLukg|7<#Bz!|? z+7HTM+7Hn3A(sE(U>D2DAuVDnVS8aGVKNVLw)B<{=`VSZ@B-mQ!eky~mh_hi&7dQ; zf30N8e{7JvZjDJbUfi%i*3pq|nnVmh6BWuJaLJqA_HvA}%V{4SV z3r)ZCDdXm!GVa~2@Lw4B?si%iB|q}GceF9~2e(N@2K;evuKTxQQ?H8X%IJokRc$fu zJ)+{`s>qGk7iX+!a8v5dJ@&3z(y;2v;vRdywPZ-u7T|SDs-uJUT$34IF=)?|8E&^F zn={_ZOmp3|w=zRH1gBHV-l_`!Y*)su zk(#XPS*=%X&RCVXE@SN}rK>ilmS(Ps++1*P%d*T{HvBbm3ro5EuhFs|n{(o;{UyR? zjYw0+n*YWj=JSoB?jHv4(M546{dzW=Pzq<#dK|hA*){(@K)h#2D!b<2H<=@x`Whp8 zGVCwV7ftC;A)0y$ATf^rB9pD>pTE%GRop_)aw^aS2y<^2r9 z73YP6)&1@SMDZRX?$DxG-H()K`mY%ESjq|jSN9{mh}HdkF_gZ8vD;EiC({?0%6yz+IYkcbW!^+_aC3+(UxTjLsymch z;bTaHGbs+EcrJW{9u$XDj3U&4J%T%e;!K3HX3hl%Kxs3j*>k3W1BgN7f}st5!L;Xd zZ)Q+rr|n)qaXrN!P`r@hix9KM&zK5|f+ESgEWFEUgsv2(NSIDx){M&~-T{#`KCZZ*&Cw(**v(>F#o@7OAH1+WR*MtEI=@zrg5n_bmc&{LaZFP8_@}eXI4jS z1LF@R75Ib&?tn1P1cwpKI|Nw!j@Snt+v`E(d~Yq(M{`sob=>74gt=b?yS2J=zgQfu z1xTC@udh_CLC~BSPC0>hteEN*u3_LVUx=D7YVjmNOim30&%tBg2)suH89{gr-h3a6 z0TNfxv*;{PJs-u&LJEG+ipV_=IhA4Jba?FP0su>gV4{$NZ6PCguw3ArV9NOzQc=DF zGQ%tuDwgn`2@cCa3HSg9TZAI`D0rB{cC(R%5^EcgwxU@SR=8jCg*_tZhvb?A{Spo* zuoLi{l@BatfR-?^jnLid8St&2XAdcw$^(n-rcg(AOGalJL5!?>*Vr|7?)&`D$ zytLqQtO=^E1yJ_om-=n=_ua^A904P4i8-&=CR=;ij{3W1@j<@ad!8y&jV~#F&x;@0XA(6 z0Tv8<_uyh%LR991@k%x^HmivV<~<1l+6#eI?Kjm>-Ig1&8Q7Fq@HB30O=zyuvc}d@ zKxI?M5TH$d<126&%WWxfyvpr{n8xO_$BsHy?Z@z#6iEo1J)OI_h5_11nk?BGD%KPm zB%>J)Z0?A)X^$l8Y|~;M!cAt|!wFm9afZ9*G~-h%TJLj!7mOY&VKVTF(U%kcVDvNH z8ukc$`aq{)kGioBm2rG>=mC#-0;>c^q#s~_uO$qFuk%$jc2c*)OMRPo_Je5ImIU#IwJAbxHzo;I;5t72Dln^6rTJO+>M4FA647O6||dn##74{O!) zof8=J?T)Z1*zMXB=+YSE02jI^o1!HGAtS`QB~v*zp2*6w?w1IMoHqRb3VaQ2+MKDC zpL-q9U5c;Tg>AJXE~*6sN-M z5{rjn(#)(nvu!|8llto8$+#M2ydLT>w*S*S?2#w-B|fl*P|rji)kB%b>+cJn+^1vR)A8r_8B#Vt zAqO^G|6IOL;bsFTyrrP6%FghkUerHYtT_R`L=*NnZW-i3+u4pC$bP<_`FcIG#vt-D zuj?7Fzb`u_8lU^Z$5gr^AL9T1b<}a%K!d8p4TkTM(=m?jWO&};9w}WXq+y=mc7xYs zd*$w}bO7V3kcq;E|L3`m7{QYD3vf!<~ zI}m1`e0aKlU`S>_(s5(_Ciq~wz96R(H;H~6<9`m1?5rN+wjkZ$-LvpEO!+;e z>&Ac_%SX2ZKDZy5*bmkp_k%;kc0Z6k-j)$`I$?l-5A)X9Z4vFc!no})#AoSd2y;w< z_Gq8m3{-E~kdKj+UlZ;T?iGF@{8(t_^B_G(j+yTmp?Ly=%m;Sr4L=1mycBSX^p^{l z645U%7hXq117D-~TP1&2vf)D!zghBwihoqH;X@I>Q?lVhA)EPo*#4VJZ|3nqu9Y0Y ziO21lm-vClQbv3`={rd7BH8d%h%c5rSa^}pEN%xo^CT}OBE6ZH1O2xoS1bNb;eEo# zggb?1-VO4-E%|^jijIKgrei(wEF`jDCi46s;!b+kBYaW#vhdHs*M)x* z?iYS6~!#yVb6GAd) zO!u)(F2V{DJVt z!bgOU3!fJLO87_N{|Vm`{!RFa(8Kc(w@WsZ*i_g`*hWZxl<}tu$&gYWAUsdV_e7~D zXG)wdyh6B82yjAp#F8>e|Svw5qg~nQI%YuELune_GPGDy{k|gkD)P zv?^=u^$5MVB(r+Zo|WmP&Y(R@GSl~c(#75DWvt(v`BpgMcFEZHNnt??@1VPH)n>QQ zgQb`7_4M$HlvRWFJQ~H@Bxw!Sh2HAxZrSH#AG7m}vhuQwvSX@REg4?bYUqtsooc;u zx7%;3-XF4LbF{Do?}hB$6<+UEA7AR0{sK8Nc3xO^2EOH3h*gcFOV)30Q|fg5a97IO z?9#M-Zdzvb@dvK`=*nKt?z%GS?Daxf)!s_?^pe)$Ro8BI&sep2{pLuuTd>1%3*9a~ z@Yc%^=Ryn}q_2ps%3htZGGpDVwcR$pTHAiptF=WdhB%Q`snwCSy(+wQ4N9F;M(%8a zuUz&uZ@+A+b(Y*)>ul{^b#B%6gEzF@R2zmI-umRh6NA7wPWw?Q|6w2YHjF}{Mu0eYd1e}a9LZY!~46U)mN78%0O+N(Q{8pkK+$q zci?x8LuL2~$Np^3UD>fVbS7);r@PXsGuNiCD`~xcbK2^R^=Z`^rRz6mtj=D4Y-#!` zr~L-RC*E@5J21ce>p$?tOZyItxi*-l5Oz6F-ED}!xlqK6GVzDERL+Ei*G|msh#P55 z$&KLY)!ysQJz-Za5TKbD8p;1jE1KH z66-#nf;cC#8@k12t>;CNTx41pxfhxRksAEZk4#3%Fwd2jKD+KS*)qHCGtOow`CFG- z_nCKlfpwqx@?v1!=XaSgus%J$gzKp-F@DufUvvV%k_T5Hv+1+}ehwbIsV6{TR&Qf=%1`{sW0-c3jam;U>!Ws-T{oHH|L=FVN`o^#Le zc{=@1B*&2CV{rNdB#UXq%{LzDv`2DFXt?)0$P8oBVmu{t_h!yUG537tjv;v&3r{4; znNa3Zk{6K7M=FEHF&C2JF3k+F>ZCg$^gfcmVzZM;zD9C4$tfi1bUKq?3A-#H{d zAW0J`pX`afl=+W%?s$^Jp3PxGVso+@hY3i*K8BFxOM7S;6Ms_a;##Iy7p3C0 zkmzD6mJrx4XwyrH>=unJZ1>2wy$c#)v_rXph(Q|%(pwR&9Ry{t^g%}c_vkMf# z3p7^L+_?;vESxQ}3((yY@(^Lz6RKsR&?myROz9!j@E-~4eI&kb9Q=sM#G%T2O~ z;BRAy=3G+yUR7LdML8ClOyF;TR?GeX4Oaz_V$s&$k^g^3h=vUPj)p zO@0x99mW{c>G<2=z2g@l`29}#NBrWy3W9ich2SuNxEc``BLc4>V26n7eKui(&xXmm zzX}yfZ$|P~pB*9cI075LCeV7xykmp$dQSed*!GehE12@ga+QU7yO7RKV-sG4Ui(#JQMg~R3dyPUJ+`*;ZGfu31 zC;ZX%_<~sbF5dcOgS@{u6<$giY>)C<;m1oa?AxO6Z@$*{bT7RE#Nd`4Xxr2>yH~IF zZE||`_R?VM6l>c)x2t#IAg^axUaOII*Sc*8e7&X3U`YQ~(r9JuVy>tns` z&zrGm(u_H~A0Cp-NodH<4x?+ox&R2>QFVfq9JEg|^&5 zn8I9Q3n`D~9!5mSxm4s_9s3%U^Bj>bp_y6wCK zdA|nF2KJ4C=s)fn(y2Q6*zBLS;5a>Q|HKhbgimAt#A`+a_D>DCEcfl7aLqQ?oG-%u zX$ZPZyO;tYuPvlGgCp`9LYyV!aZQ?2Dk9HK;%XtMk)-bw?hx|3Rq~$^?h(E$d`t(C z%#r2q7yYp4ABlcS^b4YYDf)M!4+xDt2jqM#I*b#Ja*aP?v}5c#K(`_vw6Ws=_Ex!p z;-4jYxad)$%S2xwnocq)XQA+F;aZ`w&p>;(i8gjnptpDWG-0)Hk#L#tY9a3(l+Sw&af@)P@H@hLh2IxGDtun}g78;d|&tvq08e3?NfI}H1>bMj-tB?`w34IQn|(QV}<6;3Fyh9`Fe}_vxL>cMM87F zAb+{&^+J2z@Kp-y-zEI6@IK*A;V$9R!smp)5b|9Z<@`bTrf|RTJ>lPk{}38GLexv; z@dj)xGg?y^_SnnL+Xkm$vs!Qfi7S0e-n@YYp&wz_XoAV8{wU07( zhoH^*2Q`d7+*K)6%5OZXGvPle{ZM0qNlS?^V$IX^+aEqcGOzTFfb z6j;xkr$DMJNt^Q(Xmr@XPU2Hb%={eT0O26vIYQcvvs{^QqOejpOK9z@E)~60c$M&a z;a7$A{f=)Df2)uhS+@H<;iJMI34bd5nUE@5mj8orpYYGZzY0GRdbm)re6o-_Ueeb7 zidqrUorS%GeTAnB&k|B8%$ z*2AJ77d|Pp_E>vFzbt%3_(!3&&pIIbkdTUP_CHzJNZ3?(imagq?)Fgnfkrg=Y$BJHY;w2qy?H6jlhWJ=Z+Z3x(F6 z>q^nIKA^mtgtrQB7k*3l9pMAQhlRU@PY9nC?iT)1_#5FLgl`II?!fjx6w=0wbVQgb zY$7~G*jh;Y2$s(go+dm)I7~QPNCOI%zd%?noFTkKxIlP?@Jb;qE?9rPaI|{5be+?&*+!?UbKq+==>?~3Y;xn|0;j#Z zK3thm>2&H-(5B#tkCNIy_f}T>#+%aCrQY3@ zY3mMmeO6A&y0ZMH1x}Bhds=U9a!acXTk}uYc<^4daZ!^STNm^zC^{Uz{FTGbWT!(r ztpD&NJWaW$wJErM$0-F*sRVU6#Do2mEy3wC2_w}&tl{m z+!Mg}{YsTG$r+XJS86QDQ6z6-xp6U&YmoB&N|p7108Z=kE zk{^(S>6{@N<4J>lr3^8ggt4PDB(2dg*+e6T{545B_j0F2(S-tB7k$@O)7hgHB>9}} z8uBiZKaP`6k$fvo{)r?XlKsL_T!%9_xAn=+Bu|c$y!mEu?GQhAEHB#8a0@X0XZ=e( zivfq_+;%`BWFbjI9{}?|(Z3Yc`Y@arOf-{Ac#k4JBR-KrU~Dot(SrYC6_!zaZ@}Vg zqqvqS7OrO~$BxkGfyfsG^7zDeUVQ%q(+@&xM3{b5)iTk|=Mx5*WD%hZ5r#WUYMJ1x zC~T!|^C)hl{C3ySU(>Z{muS$)>113MXU(exZqs&1BYb=B8)r;OZ;wZUdF@?hQPuk zOt6!1`?T3Og$nd|^D_3BEyi&fTFYj|knsEL+mW#==yQ?n63*55X%XC3yNAi+F6O{vga{l)bbiCK8YEUDVrU8M z0gBkYj3f%15X0|!5CjTr~(qhL5#r68m|K?X3}OI*XqNQSc#CuZX~IVrzoEeH^SO{1OE2lR7@7cyKlc zldhbI>=x2hwuL}`IFQd*qbBfpR{dxopL^1TKz@24e~Hbf{6`RBLPy{kfvc*`HPVpO zq<#VWtkgmD3Dqj>Ih4&YUW&4)++8t%1e)} z>DjhtuY7M&Y%*g0_%`F)oN;4|zAZX-Z|zkK@>&*pso68z4!@v9$Cho|v}x&O-0HiO zI;(BV4sANM=-aPVd*fB=j3IPnl~?Ay=nV2!FDvs7z{&OzHd&v~1nam*sd?qI%BRdP z?;1NFra-;QXHPAkKD~T;&)i7^dQP1O1D(p)yz+%J=FgZrC)OvYZ%*#17sPtbo>sNs zjA<|-Dqqxdb}s1Z$_2Bh0xQ6;s9KoYbADCN={fz$nKgGxb%!&nbrd6ZCp7YBM&IfP$lM>FBG<+G=KiEXfWuV~N)YdbPN zpARZKe*g7`SS@ff@o43GpiKRCgZFm( z1mI6AP}l}^sIwIgo^AIWq@{{BC0}k1e_f6l_}yKnLZ$+%91s6tu%yg>tqI zMJ$IrPH}Cpd3?$Z%KKA59;(F0g->d>4rQ!I=5GQFo7{xFpuEG7$NgR34(o34Sf@84 z!(13?Q7>o%^B5lx+H&tUZrBd%hbV{Y@h8p;n>1{PMIF8EE0WFzlpDZ=f<3ON(+_Tk z(>^iIpJa!%8}eSW!hp6dA`Z8Bs5fK=^_1@4^tqkL~bl zZ=$hD0k#!ANO;^Q6~+e_4C6Zo<8wVucGAW+1oQ^c#wG;xouao9K|d(^`=a?$n)Qv( z9OUy=I%%V<0R0Ei#%B)b_eB4d2-?NPkmVyp&{?9fTa8YTXLLh4LtJhQ-^{gfPwOc< zN62d>>kSf8l|Z^!NRYcrf{KfvG7XaHNsWG)xxg}txv1lMc*O3SNMRC>Kyim*Gb}wLi6qf z^j^`g3-<~CEIcgyyU^qDhkD7vEMYSt^+n9@Dzr9QxuORN2Mevu)(FwoX6roB)HqSz z#lm?)YqMp}N90?ZtyRijEwnaTw~4-6c#qJWkEs8sXmcKdrVT&a-79=uXly0H|Fh`B z!oLfRS`+yxJRgBggj_P7v~lYJfA_A5zY|K z7A_E8CZtl1<-aPtNw`V)4dI=_?ZW$o)Z(%J)56`tmxT3gv8d)_`45HE^pQS6*h<(| z*j3n5*iU$xkjg>UA1NFw950+KoGzR#v^H3aL|YrIt3_KIEbIGfllZp_?+{v>s~w^r z5&lqUZLXdXO?4&v`&;3g!hJ$(V|7^c7wrR!`cbxTZLG$K9xI$EoGh#q&JxZSUMgH6 zTqUgU1M4pFw+ZhTJ|uif_^j|H;mg853EvSO5_0~-V;kfD;gCXyvXB#XVZ3#64Oy+dZ|ON2`An*Y#(0 za1R#P+ORp`&uZ!s{;Wb9R~dg+QTelaeh<7^xz3u=Z?8^sZcg0*A6q#ST3^3oC~Q^2 z8*bi_@M-1Br&VNicx~FcN#eEpTlRk=!bx-@{ir=ni_ECE2_3+09&ah}-r|X-0 z+)Y{etMi?kr`?-}-qVv6JaV(4P^#g2c%>BTPUWF{L7k)w=^Y|M|qS3I&8GEQxso^BQ!7_zRpIX7+a8d_e zgu}@{Bo$4%4mIEni+Ae8nr$s9W)6S)oyz)eGTDDPlf316L(Vs%lIdItUaB?|qTx5# zZaBQq2o7`Auf&>d&!UJE;kOgZBA7g5%{JcquZUcT-zAZ9l)XH17x?f}H35XRt*HVF zUaD3Dl9w>OyzZK9_xo$M6|%~MNjIZJ2y3<#ll-2@P%39z@KV)--GfzcGNr*wRUgo4 z?rsq7*tl)YD_}CXZ=qx9r!h5-Nj@Q`b9(2VN3xpa-$<4n0?Fst^c#_IjWG=$OMNd@ z=f@x~3o(FMrY!A zA8x5g^0tdNDj=tlG>f!-z{1l=4#v&I_fj>T0Gji`#N8@fT+0-z*0Z1KX6ls?*e%p6wcUfNztr}Q zeA_wlQQQR1n+BMAy=#dR5TW`eOf|_;!djn8VeCfGZlE2+eBM4l1TRh2!&5gj!M}6RUiFVjIi2js8(I5kgJi)!W~k zF?Mrch+;R!x|XurL;6yfKyj0{AX?W_Oy7Zss@$rlO!AXlOYta$|D#0TCZLK59N#SD z;+W01`-Ew`KXCl!tEe$fpd{p%5h)J&Wki-IKTwaSmkDe`^@;-ZiUReF?;ws9v(T_h2sMaiq!Xu1iQPb#o?89zIEp=C zY84SQEOq+)0{AcaMF<>~I#xm}A&DmzOzRBZfHbbQ1fE}Dhlp!^Hi4%Z4e^K@d^Uk< z9}3&Yp7ACOMqa6(A0n!3Bv5wgOz{0NjJt!-!BP97XTmB+jmG0YOIkP^?VfKyhxXE~2IyU;c)iu|B`L6LN(X{M#_}AYiZ@ z-e;IlzZ~-zIwM9Ak5;Y+%G7T+cuTi8{t+q%FoAlkk8G#FvF)CNG+(>e@cPM^mZ02; zVBlQ|Cfa_#%7C^Gl1>^j_b{Pg^Jap!X=c5Ga<}l^h=R?l03B?1Ii6i&V6a_|gKhUR zq-`A}oy#&%jtK>uM}2Hi-qwzI2nUbyQW34ZRY==9NIDxKkL7Hzc`LvO%DX=xkLQk+ z$H}OzLmA(Kyk7+vHpvIgpu8s_kK4)qWg=R6cO%U@y%8C%!aI5T9k79Uj1LHHxxeAn zBX!d@*m6Gv1J$c6e5cav4l_@IHjC8DoX zxvz*eb_|faNwo1XgYw@|x$lX;Q}mOfjc*y$`?=^}E8o~LpgsfjpuBDodCewf32~V* zw3#x4-&1ss&>WxO4-!30I9!N_JyU<2aFTGEuv)lCxJ-Dpka`vNXQOb7aI0{eaJ%pk zA+P7G_neUTVA3xOUlG18{FCs2@R0EDLS78axComGTMA>s&O+nE4DIz1-CuZyaEOqq zAj%ypoG6?utQ5`?RtpyiYlO>%>xCPHTZMNCkNb4;$J;19G49505BT5W(~0Up9xo>e z`6W7O>)WZTXlfV9=NIzCGlav1BZcFI)_!QZXzSZ)uITx~#X{O}Q!bY*BCZs!5#A`Y zzMSq7UEhvqr}(>s_3emW5r41nPr`SEhlGcP_1DsCh6@|}*IXDAb`bUu_7)Bn<_oQT z(HPOxp;BIj@Mv~L_1D&0t$OQ)Hw&$ACu?71eLLN!{O<{^eUbI;^tAZT34bB9_C~)G zZGAh{w=?48h1(Mra=t>^`gUqAx}~takl#zNTrXi?;pxJ&gl7xS6_yCk6H@O?ITs77 zg^PsO3Reo(3U3nLD!g5Ix9}d}gThCIKNbE=_zR)+?esg*e-!Q)THj886a5ci5+3l_ z{}f@Cu$i#_T6|r^?;)gSo%PQW($6pHLSeCRobW>7RN)NaY$0{?tbdhorSJyfjlzw> z+l1c~ZWC@7J|x^J{E_e{!k-CW6w(-g?Y|-1FMLmEeLMYA^wE4eb;6vO^12E82>T1` z`*a#3{#c>)?KDO7(R?~xuX0}%qMM)9F6>kpdKoLQquGTG=$kvh6pS6+E-VXkScD_& z!d7k%tqE-&vZDQp{7PqiXfwQ^te(E22aNrz3WVP@m+Vq zx_3j1*S+h_JmKVy`#VkeIdXo`ynO#16Bg|6yqMGp1^x0D?7wqy=lz`weJc3wfC^AG zJErDey8pVxS$&-@KZoU&x5-~CF#~HQu6fs4{N6k6O!xFoC~@-+mTQYO6W`kt+W6Kx z?&9b{81`&Bx3bNLD-N$7=IvYIZi5Y0IA3g%_mAT4z(z#!$Yqw(Y$q z7eqF!dDGeS+?!GOKuQhxK(c8L{&)Et%>?`)eHXv(t$4t?!si&a{ei94ewKBkQ^10O z)=W^|Dn5=`KS*C^MmWhlx`&gmAr(y;%u3PZ_fRllmBp2Yy=n^Rf2OIFe5xxtI<5Ux3OH9pI^%aqg#KVlZiQ6@rNH7LlP;KJkZdOEM4Aw7H^J%kb?< zAA+6c^7WoO%4NqGsvwTRSiGfoVQMsu-#FVy=L=i6h~y}e=FQKTZ6G&;%-|xyZV6j4 z{)~(ppHh;oAk+8xGnOO`+A}61;f^Cot25)z=sZ%KMfv`W%D9Pt1ex&!D!AjhaeQXV z;9SX_K$51^m{EZ|pX9wDGiS`nfkhVU{@y41h&%=NU*z@`InXC_Mb02;mJysvQL9WY zY`I80LV~`KNW4eF_k~2VE3SwcG4#^U)q@|q+CXT5S<16W5Pl+GJAryAg(qQnE+vZ)!qKol8(cZ+G+?pf*nT78|zMhv(vFSo5PWU*n!&`$ zh*0ehCQ@S!tAW8p$|E1ex@6ecbNAjJ?e z5n-*fq?U=+K7TTR;_LYy!jAJN^H`kHZcoUmHvW(Nwv3ygB`C)Bu+@YoOtP5p3}OVj zeH!5~y%!Pcf5Lu~EN1684@TW?fZl$RP=pwT1CTx)=A$;LQa_WxVN7JQ`y4>IEwW=- z&utO!c+E_!r34O`9XQ_x;R<7ez?Lvnwn5rputl~3HlYHMY$Dr&HQhtYY@;|}>N+#( zW|}M_a4*ulfv5wbG;lzaQaI({fGD-{&`>Fgo4|o?j(ixz5ZFZ+#4HI6&UiaGhOcVQ zwMcN!M4Vf34e-GY4GekQ8#z4{5Ga$qCl&0s;pNflc~HZHRTN5JlPw+&~_CF!V6^ zyh*PfMSR2OM~OTVQHC#(ObFBqv%a6dI=&GcP+#smgD-%_fQ%&WMNIOKd!$UDIF2vb z)lNGmC2^$5$4@tOo z#@vj1;vJvQ;W=!Q=MzGvKP7}HqA`NvC9H|hx5sE;nL?WIl$qQj!eo;iGZir1=Ms3t z)UkVN$+i%AZMT7if+0x%0C}PRtwr4``u545hF#}OnqFQpWx=fKNnDR=es(1XZhrN2 zX!?=HLyT-mDnXgSOfm!O?Qz^e-bpd~>&c8^Nw>ajdbOm5&m}RhQOub2WSjNe+RT?6-t$hZv~8O+IwJY)WifB$An$8v{3Wd0w#|*fJMgg^@C5C3>Ke)P?c*4G z9N!`XOJ*&Y@A$?#RihVFJ8^RlV~!CwWjKl*&T)&I1yg60J4dx%F~?%uGfsST>zU)k z_W`X?z7R{Ce_?s!8)ntr(_gSP4G%t9lO+s(>KoSR2(7br8qV7~YY^5qxPhl5`8?HF7HoGQ*2al}XM@eF0wXAIdaPkvo9j@{)}f3E zke9`Tg3Y@cbWmP(EFmu)dA5JlmD)N;Ix``UdT$$SlDgHPyyY=}JGs4?h*sV=k!GFV zhz#8^{pT7YHZYHIyU>;!gN^5wNF5`*iY(<{a{DQr~ZHV^kMrPA3t!!65-RVt;TCe1GYEjp`jsn zKDdUPYY^=-cs_)15Obdsu?r32ly*YM>`26M%xf3(`w9mN&k~LhmIx;ZrwA*B3x$^p zR|vl*yh(VAaI0{K@FAg@+M_>Dh&HoS(7Q$dLinoiEnygA#qDS+gz2iGjr{@mXNfK( zCOQ6k;J{+isak~_<;?pL&=;%x0_86jyziGE)As_^&9 ze@FB|(I1KC3CZnCC8B>P3%dx-dvNdzM2{6t70wl!@0C%`_z8i$uZnN<|Der>%*bcp zIPvTun&Sz`5MzA4-k9H9~W|g8voKUlZOW z+$6k9xJ`JU@O#1^3!fIgBz##&^#c22{pEZh`a@xe#~Jb?!c1Wkp*fzB-%9kS^`A3b z^+pP*-(Y*@_y^7qJzKayc$v`Ho1xq_qRn{$dX4CfLhDE8JEH9xXAg-sN-Wg-vFN9T zyM@-T&L2g;C467_H=*%s1v%D_P6lqY+@8k5lZDogPDjz!{-vL2YyVQ;?q#gUEV~Q|Cc%twWAvI(y*HhR}c$#pCaF}qU z(E7z0FZu!@Rcw@ZiO|}oED>FQ?XlJ3uNU4dtQFoNwDv0Zihe-&L*e5>y9U{FqN(F! zfA$LB6z&sRdzBAFTYD83^BLCT^oMrI_I?J^@G;B=vvu9#vtD{Mae^c`4b`6s`@xUpcYoLpBGG<;q-#Re*`t9C|{1thX?%K_Hg_WVTH3i|_|A-CV zkwV@4*HTxUyJB752YWW>9omD(xdTa8h7Z;ZbI{6_RP(BQ}f?``ThNa zXR?%Y;2SmXtHw*HanWK*JcM%0&D!nVJpW#s&)laT4dy!suB}PBx$nb}W?EUY+i9P) zE_GjeD7<#`y#ou*Er3PF;_GN#G4LC(kofDKjs+zN-Wfg*W4Dp(Z(Wn;9JsP(4{MCx~kF%+9e!GGf3;O=c5*7JwzioL#@?V07pa}f- zWNiueb=R%Q_h3ijo*o|Pp5@@N&s*oLU3RGKyGb{{icxjCpS8zs$-q6~kHUvuJ{<17 z{$BK8vE^s)3HOcc{R?_wIqmnjr{0aRn<mGkZ8W*%LC@#pTJh2koi`~=nOrG10`!Z>5#hW|xUfJ!$o_fQ%xg!7M{9E}rv^e`+J~!A$}hBIfiY2VEbYGxw%pEm=;Q+)rj{bPc3Wv@i@xD_Jd38dgfVTz*NIY z-cE=nRUrdrAT%>in1OJT={?LU#tg*!fXTe`{EB?SO$x)_#F)57!+Y3VI2<$b!cp`+ z;)Z9thd?Lain2~J*J)jr%!l5k$vNO$k<7O(OOhv}?B&Uuz+db{&jA6OkX@jn>yZtc z5YAmv!kp%&(k5g$5@}pR6gDB(APY7jX@f~_5gAJ3EDAOu>Fg40LZY-fflUb2K$T-1B;aT!~aBUVg$>gJPcm*=Q1~x)Vr_L2Sf1 zgnK^8T9Phv4cQ5)M(HFcGMCRfjhevYsY+9Scw8=y6?A*ffBwAlVt$V3>@E8s<|lFEN>G4C%NR zQ7nx+8=Org2?_%YhLt>VQN)U}W>vb!+C-_ZT zRv8lg*-1ngj)WHAcZ}P+v0D^c77b2Dvb9l(25nSQtc^-)&_*S#u8m6iC)lWD)U{EmZ|tDM zt}ydZbI*3J=s@JzafE%#Dae3Qme3B-w{Kyp(9a;;ZIWe#Ga-ZK3dB4_zdTcv&Kwkq z2VeM@pztxZ?U3yYA44z~2CTw0CT`|}DK*~Vuv^6h)~4Zxt;aMga{6!V2AFt*$B9!y zI1wE&d?q;82cO_~eNmX5twA(pm{^V&au$VG0R1t7w6_?@{VY&Qv8 zJh&bB9sD8$_6^JHm_BMy27_h7-S~YR5f&YU!zNiw7-hGH37P?*2w}QOmMj9)Ao`s~ zVy)qiA>3nx6jj)v9CKe*bHLZ3C`0s|h2dHzstteqQUEVgC_>

jPdp+ew{-g7QrVw~07B0X6OCk>0L|QZP;T8FClu)f@QT#@CpL^H9|MD zUA=3G{#kZjVqn+g*MQCIi0hn}I7;FJYEObs*v~Z2X@`#UKxdk0UTnes<~?+UZPM0? zjV@K1jj}cJQQU;YxpW?n+)_mJiNHO9s~CZA#9$M+%=jbouQ0{D5X>?~#uDb4A{YlI zYJ5KTHP0LfByd+jAYlul5y-?gpMO7qdk{qkk0Y8QO!%ipF*k-+5(p#|n`AMe6w#Ds z!aq`rd6v&X#C|34G1u&GCO8z}+fm@?@wNcLg#D)NOPAF$@t)7Odk;ktdyJPQ6L?AH zQ4(@;YHdlTmF?6Z5!_Y&AyLGl*P5;rC4?5)N*_X?zaMefp_ISx5}v7Aq9E7^yoLLL zm(ySf(qZI+EZM~|x)z!h>*1Y_~OQODlZEn;-MiR<|7GHHOtuw6JBL;k_o@-FsmBR-L`{ir>ufdTnF* zNOr_)cI)6?T|0L5nhY|~vdl}PmD1>*AcuL)DumhIu$b2`=A9e!&Wd^8Sh~&ogB$a1 zSz74*$upgZlts?(*{j`wq25zVvU{{^-*y0mHm)|1j*?y(45Pe9ugGrKIuyo}aaB=q z>7=Us`PB)hKXqIY`8FzL(<(1Y*e1~~##%K6M%FF@C37aYB>E(aoIphwh|Qj|XlSB= zx+XE7!T5KAMl#nCcj6E})7360%nv4;v6TE#cF&RO-}XdUJ2A^(*>BHm8&GCM3!xh8sT z@^z6FN!N#0dS40M;10<==Tq57!NXEE7W}KuZs?-&UvDPm{HJ^p^~Sv)PYveXJ0Amb z5$ikxkcrR(F=)@S8y(I9?<7P%Ofcfry)z1t@@#kt`@a+~U2L#XqXN!@u-w-%m%D@&6qv`j z3lY_;0479X>~fkVfGorC5~59$&PTZcOenB_47(A7+rb6HIey#@bRoVS=r-Gphb55r zyEv6-i){vm%Q*)#=OQqhgU|O|Y?t!cW>DS+9H+tl1^bSo@et&H5%yHv&O`{CiT>*N z2G~*ZOL+0K+0xwOiGa@&5(HA7!y`2jJcmbGB6$8=YjBHNeSz-1nffOSo*0*{A|9&$<{Cl%e9F66c3-)VbQM)|ll zlnZ$sB0XPtrSMwe8sV+NJB9ZM9}w;oJ|pDuPr26C%Gkt!{=N8r67CniFLW`;tk+W5 zT{uu!C_GO%m57)06+&avl8V=7%3n$ZeYNPXiry@|P5f_*-Y)tP(R|;|{urAT$l*kt z^vlXOwpXCv6#b6!KM-wfuaKXFoH3A+iY zvt@oi;UM8);n~7-g?uN+^5cXT2&V`ug|me7g_jD=D@)YBN;LJRly{@h+KAmI`Yz!% z;R8Z*zM|eP(N74C&oc0TCi-RJE5bhr-xPiz{7^_uE&F3_#;9c`-CRi3Eomw!iG76B zVUj*eI8;d8F8Skx)>o3X8Kbh7`PIV9h0BC1gsX(q2D5yv@E+j~A=Sgoe@PK3j0+X%G+|TWNkS@=ncrR5N7!FT6*KdP3+u0?RxZA^3A1acEfD_-;gv$_s44G8 z;Vr`3gx?Z=NBDs7Vc}!K9}BH-qdlU3C;X%E9pM4tUxgnDt#6|!`ow-&-$qSEw-B}w zb`o|I_7V0Mo*}e0WQC$f3C9Yp4cQdY<-%FQD&f&=$*9+7zc&f%+lu`_{Ktg#ZN+{r z{;!0;6Ivff?}|Psv^HYaw~<|A&H6U7Ypk`v10VagMff%0O~OsWZwT)c-Xq*0d|3Dc;S<8AgnNWP7rr9gD|}P9 zPk2apSV-dwj$4|riSR^W8)18)^?j5rx}WegA?-IPZ-lT^SSF-N2lHnMtA&e%%Y;`8 zR|;gTda0 z<^S5X^ZNGdeat?R?n2)X;)_&_UWZ*Ik&Z+0~H=NX+ccF0dMWmuh=9wUxyaII+_FI=zjL~EH z_FH$69#UlLC!42uH~Jb|iH6NwARIp1NDJpeb`lk1SOsl0AQJu|ev_l&T}jC(AEhcd z{CLteEZyFTmXiFD$WRp1X(#+d(laJE>?HAdCj4X)r#mSwp0}Y(0mpx55xN4lN}y6p z9Cs)aZc!Tbwr)O!yJOO7$s1;f;xtNj3nx3X}CUXBX?gD1anNdCIlD;{3 z6@dNu8Qldu>A20>w-1G&*-9*tk$B(Wx1bO1KjCxnKwo?X*c>k9(BK*xMsZN*lko<= z#{W|5ppH~N)ftY2#-|Q@&d|BD7R;VA|H$Pjw7cqjj*jD^p6bYGjK1hKCxTj_Pg-u` zzi35?BXu}@zhHy8+KQ9f_twhofc?I6Cvgo4fE5ZW}ehG8ILOeomADWHSxF2QSMzOQ1tY|pm42x(gf zNv9n0Sk4BUR}Dr`-l~8+-a4(kl}Ot=8tPCX$NZm=6(VcJ%c&yd=mfT({8&GuU zp~PGh;%hfxyxAJR9p}Cwo=n8a(2Dwgck~Vj#J(&;e6qh!fS$0+4JD*UzZEundDi~J}C#%zz!=q-}`ru$zW?d@9^aL_9q{wX^S!Ak;qjb{ud8jQe)G6xol40M zC0|8|&-ZwRNzC`wpkQLYw;YsbCVBp1+WypUxT&A~6lKQedsmPOhiP(+*`Jy36(Nlk zu&)8c=X>`D=6eq&t!8OE-}|1(P_&R0A4<&kIJ3m6*So<^;b#es>tCsPZUpChXKB7i zy@WfM!ZF{&uj39eL~$A=yLr#>_xOBo&a~d#;o%Bu`Y`S z^zS?@7rxKAX&|{9fo24R&G zvtwV5Yx2I>DcFB#X7_nNwR@iLt*o1Dd|L3^Nx_Oo-Xi(9f{!yFR^2eEQXZ7PX#64hqEiPW-#Kpz6+_ zuKUyY_;k{Gus*K4n>2e$wg38s2hTBoV0C;hhkFz5PoHHjSHy}6HaQeD-}%}wSntT2 zfx&ye)$NoZZR@b?DiGgbLc!*hgSKgA^}@Y1#)N{+n*uu6?l}RS5}%-LyNi&vbtqyq zW6b%iWDM zL{!V3{Q4+i+ZWhrLt(KHISFj@QtCo9>S1KIeE7gj0l-Li4Q#@-G*? zLijZy_1mm}i*T#(Tf!%VFA9Gzd{1b;wLtv{4i4(nQibh^;P(=mZzx!f^*)=f?$ie7 zZeTWKn>nEOsj%8)IJ%$54LrdDbGPO=W8mkpkp~ZbBP;VOUpO4zbzfe=o+g#+@`mmi zx?=lbrzZN5cX-m<8&bOLKBr(xK{t5qYh8I#<#iuk`_YT=#du-mc}#!s^~%TKxpCCw z>pooh(Qhk%N#2LB8t zEKAuc_bd@pz< zFx!VhZsZh}b)&o_V}7|6g}ghki#$8OycZc>SN>T0(T`c?A(k01o3+BpwS;KW`N+Vm z^Ic>mW}SOk@E+uZeN$3?dlep1M1lM)BAhqXmoX3o`eEDvN5l7`7UrVn!-%Ny37F(2 z&BjWZIAGSHq!alOlFNATI7=gRO>#w~9e$TY&c*gz9=RTTtP{BptfU3*OQ4eH;3sLh zdov&!Zid<^(WG5Tob9G^t$?J*t(G!1o8*tImNJ!E#-t~bc;Vz+HhCz8KAF@BblOzp zh31FcJAmF6aMI^i<&Z-L(tT_?qXlY(78pKO$>W3i)Jb^gZhwlB1c+&vUXy#z|wL!%tJ(5^nX^n0pm-OG(~N z@B%0a+&FH~>HaMzyCK3g#cpY6W zn~EE3#cix;3z&+#5*0_GlG);~7ut&ZY(;u4ZfXmdij8qOSBtE~p?5c2Z7XthZqwDF zNHnztOhqohjaw|Yk)v<}EABMiTzh zzroM9CZ<^tGl|~+Vrh0MOxi4)g*EL$n1;v<+Bw%-Koj4z_)BXJZyJi=kf`g8uyHGR zBBW(>S=xBhNRuQd#}sUu1}}w8Fd)rx#W^8Z7Nhkq7Te@G1;>Ojj;jqlkbo~Q!tIE@ zKS8Fp`WXb)J96R8Y*Szi!PXp8%M^(F=m2$0kINwW8@$ z5T#AvBfQ_`i3z!5D3_gZor$KD3i0gYYKTO0(l`^YLXumB)jgLGc}gI?h`0eU;7W_~ zd7;5VmIlX}?DHsroewz+me`Fzn)3}4SZxF%8V-*FPWIF3ME28lD98j}bNr(70!8Nq zit@T=0*m^!&lksBcuGM)Ab}gmks|sfnKGdRerpf|s~nQm1u=;Wk9MqO(jV6G1dbw( zO#&wrX2C+rtU+XrzNgeO$w7lm!dgVLq9POAuYtBUf!u6ZMFj3)I(pj*yu)V`xc};` zPsomFbdd5xf;Zo?%$2(s6g&5E*hdkmN5Zq1UOGaWiH9zB$k!FaK%&+%j$K?uy{L@?*-~Dk2!z4yu#}q>y^{1 zmp3{aqAHN{xHkwnKU`AbrDuE9*>f=fXrK1rD| zXGr2bu13L`yP!IUKYj2`L|zVm`p6b((xfp%^7DOfTKE)VQvHP@r_Q>Vjd8S!fW*S(3cFKFl^Gu;Uy!7lny<|nO8m^Yn~={jJ%^k zkiP(^wRLLfRsX;E=H6x_lYOZ9YK3}l?9E41 zcn@#h+yhId%&vmvqVwfgOfntU>7cK)n7yV0d5LdeEy>TZj-4V4v{b8bM^pMGW4G?G2lcGAw7qUL<~sTagVmFAt0q%LLwkA|9ns z4uD5KPD6YRIiE{x9VDG^BZHcL8*Fkq7&gs3epmmL?NlIdGSb0zJDh^=Sx}bkMiFhh zeBKMnyCv0eV&K_e^X7sPlvmmY6Fl%J4^`swu0`6`LDKmFGFi?Bn|Bo$L3z^y@_5eJ z{`pT%wl@4xK;HdU2-r5czMi~l$m4dhf0>9@-d3bpr#B+Qm1vBnb_>>tBZh{17L5*U}J$g|r~Uq7%D@_t1D z3brkxc>)r@42pr?VDg)mCWw@Ws;14rFgPnPa9zQ-!OF9=#UTHS&<}7M6Tyy(&-r(J z+mmRE`!UNLFB}g))a}i&tQ*PiaX2QtX4LuCCvh9D>(k6$vQeJboVe{5^g`UnTp!YW z>jR{0e&f@Th~u`0^7{%03eOUb5RMUED4Zs&5?(4?DqJO8Bit_#}foyr0=-JK@r4BXX3>1( z&vCd*NHqcF>=OQ1{HKL4i2thS-w6+h|2N@3#Sh`aLHTJ!$URZC(K~?ORea;)2>GWf z|8!x#@<)s2iZ+xtRs4&E^?e*&A%1<|Mqd|yi}0I7$orPi_&7p87|7>UhKN(jAkTl& zF<}QG^`+$Z67o7v`V3*d@EjpuCNSTecffMdGlcVn=KMoG@0~2aQfSUU(EMJEd~^N* zzb$%)@Im1ZgpUb%FJZlBg+CYaK0*Fop*cT6?-TuJp*bJHw|c$|o)4fK3;9hkY5UDy zd(oYR=DbCIuIST+<~#(9K0t z=fZNvTMMwSXmfo4eU@lyqgakg8KU)>Rxa8o)WEM2T`gQ9tPxUe!}`>&5vjK!-XXkK zXnmvY6m6~(DEAZ5);HQqqOEVVKZv$I(e{gePxz6L+C{cYMG>)y@MK{tVMn34exO`$ z(YZn@lURSakUAyOe4ZmxqeQ$!xJbA}xLjzjAJj3iyj@3=swUFgg}a1Q%#qLMed5oA zzZCvPxKH?JpYrHu1R*s}q`L@v3v-23L^1zt;b>urkZLLBR|u($B7K?g zO5rs^>Zq8%QFxp1n?h==m~VZendg&a|9O#o1|o_Xq}>kbW~A}F++2Kob9-8@(aZZk zaUV0s1N zJ{S#!4@SLb3W^U$)5jc+&RYH9iGLq@IQney;V|g1p&vQuref{BXI<0?p@xSVZ$N|p zbjry5(fK2&!S_;jpZd2@_kMp1wOIRM~b{x59ArGervEJH-K^?KSOd^gon@4NE$d-M7rX4NrYPN%Okwk zL90()Gqn1AVobgOKS|4^)#scTTK)Tz<|C2Xg2f(8x&tNf?Qv>*lHU^7gX9 z(_^&ySCD?h7}%#>gEm74-JM{W5%iV%2TA)neUr?f!9nOR{ zo;B(S${osN45>zZR&eu4@+qJZABo*zspubX@>z$$ch6?Wcu&vDVeUC3c`MDDMshew z-ube+qn2C9ZM==-Lgt>!F5OSEh~xJ#vwwhNtl4> zIg6LoGQn2CCoD#kikQijCZ~kpZ`gdd7HJdK;&(kF_CH}0BK5-D<+u850{dM@FFX*8 zLPU(fBBK9Bl6^8Ekv-33j{+AhDA!zXSQe%NgqeuY)Gs2k`$$&-OrUTxC2}rVLS%kG zd!NXj7s!q`MCpEwiAb5S1i#A>Q=A1$*M|mo7~H9rBnJkpC1Qaxfu(B@Q*dx8i=#c zvJEQsASB+ONDn6RD8DOtm4D}MQUk{rwV%@#6KlEnhMsO z6N&Gw*dbqopVL3F%uF%>q9H~i2AA4ud1_lmAy&?RIM}SRLr&h45v(;Iec+Z2o`iY=8 zH>EtzY5k`lBoy9)EY3k~u*vCQ*fjI#*S)5Jb|)h**lsQqal1Gb0-x>KcKL2NC~qAy zW8m3f^X7sPly~S9%n8Axyi`Oh?^>j79VDImAdls2uz6R35tJ9k3kNHY@5ik?|6$nH z#(F1^ccT>owoR_DC$AagaXZ<+OhhYhE7Gjf8$NtdA z+ikFI5&efqKc@?X@O?QBhfmbYmf<+;TrsaXL)M84hW_pCWQ1L!2R;BfMP5bCUVj3%@ShEHru{*5G)?r$H+mmn8_{NsDbPlr0~{;y=UYYc8A$WmMdWpx$m=*UChQ>OyGrtV z3IDI@H6K;Kek3%jlBctYem;TzqW{P?H;y?=JOrp>=Hg9 zd{($y$XDGgXZ4x&&$Ie=4}894`4fa4gk6Mu3(owZ!eXIa%c;Je(%f%8lb$U%r|+lH zv*qUY_KP3=d)dF^I*3q5&vxK`ud-3)sLEl`vVA}AT%%<>2U@n|70DlYf1UL9*VB9N zo?Otjpie>ff_3k@6JB`No%!Os4$xV=?%mMLweN-&FWBE{=7RlqE`AJokAeT}J*PT_tvn-O+-&2V|cyx!*+w*7$utB7UYh}qR{^laon-^K&cGiO_;BEw1M z<1LhIdzkSgPnQ8R3@7<2LNv)7>d|Cc3?-Co`$2g%tkQoNig`~lnP*;!hLfp$gF0;- z0pAKzW;Fb3P)Tlhw)-B+N2vFABD_1=uVb5lWA$jgaCBWBnS~r&p6o%ZD;g}lN{I# zS}nO{e8yTsax8PlljP+jgYy=50=G5`27&dC)GwJm z<%}WNnqz92V)1(Vr6z_|Ot8Wd`lVEGdzb=a2{k5J!Xs(5NscAlis(THP|L&}KA(-< z<0lD}Tu+OX5Iv5fDHHGi2|VASt04HI7Y0R-ONbt4MF$m1>8R#+xilen4CVS=D^1id zwe{JxfNqKP1|#zOOCl?WoYf-$CNRGUk)KHtOZ{{@zy#)>gBa4+my=C;^(cS|iTd*b z_2<>8KLRDw(f$YFuJicQu9h6X)zzbklM$oN`y;x(KMJ{|)X#W3>_ZtM`aY64-J~xG z6IFIJk|wmquRlQNiQ|yf4l&8Ol;2r0$(}>|M5r*yBEn)s^PMGyu0&)Fd}qnzDnxvk zO4x+xIrEnpO(*w4;DgoML2fmyA_8-%PrDnq&1Vy~Bi7NUwFD!C$dkYZ77B(SZJzdw z@0Mfv$nU@7n?Ae~_y3P@^v&tD?>`I|%_F|)!??x2>BD7K`VxNAXT~zgjH~x7zUgZm z^Dd!QDAU&pr4)J>;F~^gP|Uluuqd~?cWE|0_v`6pWS^bmjm!3W#&Y`LE55>PD1s^m zPlaMAE!N5V`m#aZTTl#n__8woUb~J?Na`K)2_CgVdH4`-NT0eN=h^S_j;i;Wq>WF! z_Wum}9&};|)J^z6?dRL>wdxdo`8PllfT4kNCQcqMaQTI`f`4o*F11(=9PI!X4dlXHQu$M z>u`rx1hN(L69N zICSFMQD65H!#k5-QGkMNi-^N59(JPQvFLu@!9=KQyjI=52iSGC>A3DEq5Ij6LHd8} zoe6wY)!qK@otaFA>?|T6VhB58$Oc73WeEdB6i5IuQrQtLVgy7)WD{)!wQMRvWDpUN z`YKgx-4|SHaVf5~TCKGf6-f$;8cnPJ=Q;N|GdBU1+P;1NU2Z-n-}5`m?=1J+WzIdz zLEnD7*Q0~y}Zwvs!Nkn<#)Z$^+$mRv0V(VCm%PwI%K{@QVm@6bN z6K@o65=}crcsu9Rv`@&7%l}v6^Wt0LAH)yEYVoh4%k~64jYRWJ6Eb@)>2BI5SSZJ85ibxg6fYGQi|h+!c>Arzep@l$GU0x={C^=nBJL1>B|a~{ zCbDOndjBMTDDD#vh<_DbycaM$dtXVjd?d)3Ae4_0JBge;LH7cY6H6$Y`?}tPDDxog z^?ID@zZu;#{d1X$3JbCmM|>_*(V^!u6&3Y7>~Abfao@oa|Hjf1Z%Vy>9*Qm*?^YZg zO>tX9owi?p{?*r0#`k*I+#gMF?JvO_6K{eI4}8RE53gVm3)K1qc;oAWY1M%w^8qc8 z+?aJ6N?MN)!CD6BHIe^A$*GJJ-)iD$NQsXayr6?YM(N7;vEV9N`?G@%5wC~Fq!1Fi z+Gq&zbq60+PVyvv#|u~BAHGK1g$T)^$M8Rr7WyQk5kfRdrq`z#ms3|er%^H7LZ4-r zJ59S#qf;n;E-~VS%P7}oyoAsx?q&$?2>kQT80oUGsn~d;l$LC`q%i@vjQUTaNR94D z>i-c%rss~LxEUs$E#PuEWk7FUhC4iPAsmuJ%xR{(f|@qL!F98Utc&<>J^sO|vD+b| zX=*UzsEkqJ#%`&bg+>=>@1&-l1V_}CHkmgwN4MPENbg;*}lkRkcSU_=a-_<@uW zxRju}fKw466){5Eh>5QQa5N#%k812254d3zVpwdd^;4 zM)7(VE6OnYV2V>Q;QT35r_M6n<==V|(VIPE(iHZ;CzdfYJ(T9(!99oUE&Nu6*tC<% z{*FC9xbWBP3ETz#JNEcMZ}-91n_2AaFmi}?o9Ki!m8((kiIvdKn{wW)DYFwBPW}t+ z48l94f2}e99gKGLXI>Us8oWHffkb~xeh*Q{&m-SYd31yEUKfq%q~RTv`j3QR7#hkGVW`g@Lt(ku=U}a8!QHQ~8T1W@ zC-w1N+3K4CyNv^@!!ekL>f>6}ARNcI>|g{PR>yqE{&XkfonRN-m@eIIx<7&4#(~vY zhWGevT69>y<&gdQiqN;l*9_{zOI2LoCfIEpSe$x4g2c^H}SRS^_#1VAZvJywoVarGy+=DU~BJ0CDSmTK!Xjb6x%dEk~!F9~? zA+pZB`VBc}B)mPnhxyFM6E)FydN_{;Jztsk6ug<6-{EKze0H&ajqQazLTpK*dODB@ z#I{I(=AYybIC7vkR4fz6h*QMr;w*8oc!ju9eu=1v9NhLNX*wyWA~0Zt~$JY>Gpxs zR@6F=RYlx2OQ$96&kBcnxNC>)>3h_wXkbNoad1@-JH5Puk*;g1-FdHI6zm#|czvZh zRQ|K*=;~1K?$K+josw6p-I8mo1Lausd>~AtCQBPt`4tzxjK1Sc44QQCChr%v|HAxW>ZRDP5YFyYc7Kc^qyK1DVbHXxumFO zX-P%R(v(g$+gf$1$tjsy_BQ*9#G@Q_WWB>4LlkjQiA@ZQG{QEH0T>vw2%#P1oK% zYJ$Dbu4&Y}V@*!^teVTgW!pN`+*IDXCTZKOnq~0oT+*>7SU$Vva+Kq?bscJ!lwVwP z`MTLPx553&k`6VS%8P1}VBcEaq2{u6J!%@2FR6BxEva@>c2oyamQ)8@?Whj5T2h_V zbw_o$>yql^-q{6iuZ0Irx$}(T;5z4>(&&Kbefyov?z>*Bc3Q1O&7WO!Q`ea_HzV&$ zdb2EN*R)0cb6B^%XVon2-3euxS`##N%6xUKxyhH0CFN6UE^F1JrfvBSoJr)PcO*Yj z;GXd77l+`?{}|`}mpJb~#(8g6l+`n<$3y$wGTp1++&3`O=*{9IzhNxGV$YcqBMja+{4cGp7* z7N0;k9&R1p6u9MV6)nfZB{c|(dm|N=Q;bmDK#_B;QU~Fm8@nF=dD~CJC>M0@(f1jc z^dyO|=pR@0d|_ZEuVC{AVIEiBy;@JQ!l#}j)%%$S(xxVO?Xuwq!o z#QeB$TE@hJxNvI5goMw~j0p*!Q_|;B-&SfEMfF_S$P=%Im^L|og5%ys-}{YNV8t`g za^O2rzI8?{u;Tf+*?NPcx3LZyqx>fHOWsBq(X70a z^0f@V&xGGY`5lJ$EZ`28mQNt9>O-;+xzZ%O!1rTi-OeQd(dqx@rr z_vC9R-_G!!ya{qvMINf+6BGVkBeSMF`87Okvnp6sp8P-x<-)kU2yY=-6-9A*E*`B} z{Sxt;r_(bVV$L02Xi3^8Z zoU_KfSiXP%vcF?FY&({d{T<7Z`W?%SzOiFDrGCdU`F@g3hJSz?wMP zz=}?3g7=7n2dDF`8vW9Q4N$)?y0ZyTN=#$ZbIJ)Dwtn}sr>xActSsKK%{(f#$*{h{ zcIuS94ZI5z#41EFS~x5TLL^4ZNhU?!p3OlOzWjLF%Bk%oqpj2nhSLB`YZ!EZ6D&SD z(L*F7nep+oP=C;wQxT(uGglzYj?ohJgt;+VN<0B8Il)p2g8}h`S0Q{cGzU{vQW2XJ zJ_9hJ0vPOl6pGQ((-R^wT6%jzT8x&HJRvJa%W#wG>}D}qyrf3L*&Ns4KWh+!$%k`t z4f7BCKzW;ubL8LmvxI-t`cH%94H(2JCV2C`COgKMhl1$S+}# z%AhdL9fabW<23x&`58>I=Chmz)f}TMYr*sJ6*)#%=E(D5iBTEMON_2FV46^y z@@f6(Zic)#D@KwjUakh`Byz}xV-8-=%Ha@l2aMN(26|_rFV92?S`dAhQW7>)*`6~mEW@$HNTHaF!gwi^c`2Y#n>I={NP!9F z#2Bg+#!I1o$XU~E3SL--Ge3Hr6;X1@Va8*)Yhb)qG26BZ<)>jP3~8o~J1d4XPt-Yo z^_pWe{;SSQ$V98~Rb7Kt;VZIf70i*>Dp+Dv2J;f5>oORxRe1TdestdggW4@4+aPB= zm$``?mU#K|CeH9B9nUplCk*DhER50OJynLk4r@Z!|;nvR!<=qGsZh&z*)ZTECjVs|xX%=;-PS-i&3h9fsTP>S2P+=2Yo5=0cvzyz2)d#b=OPA+KIK%qJy2VyJ^uDWIc4DNa39DK_D3L6`T=5~H*Q2D*ljI&1Q!^b(90 z9uNE&rMF=io@AL5zLZ+UT})mfb%bGfQuX6K=}rBd6%UV_a*WcsUicD{*P^GNzO0L{ z>bX$L@akd+$(P4Ocx2EVzO#qBG~U(xXAdqcneXhug?VRQuk%ua3)82x0S2WhA(cD% zGIzY$BYnA0>IlQ|q;e-;f9_cKc+8+B;`w4|oU&FVAHQN)$^Bnjs=b4{tYryF6I zQ%e0|ke4Vqx}GnkIdK=}j?w}cgdajG@6cxRo`Q4WrO3Qf;=Kyt2b0RX*T&;d59V7r z#T|@!r^K3rCb%%~l$1NTFz=K$#KSOsN?Tx9v!rr|@bvu*F1!Lgoy;AjTrYR#)l9iV zc={p>=3wr4S*b^{!>K2UUDd%+@w* zhPnAN9*QsRUWMkw=$hiCSWL2pJzf4#bnPGa;j6t@!8tLymck&FD9I9f@%^Fbx*+a@ z7RLA}a88V_*T68BBunqb_lII#u=YJ4)LlG2UHM~%@k!Rt!J$w{bFfPY0dR!OfBrky zb2y~j0e%7RUGYD9ETlJa2q)ot&R&nX?%0mOw*t9qT66MwAr~s{j^pGLyLayqZQp}- z9ytZa7Ig1gR8Y_(SdnW;Dfpw@f`VYtC!tQwm!Sfg`GZ*vXeZs|b zJF)Dy85>W|8>C#qHeHbW*8!v!Zynv_4m;eVtv zX%hPD$IO5O{!R2&V5Z}DX5pL}zA=&BpvuJ9%Wqjb*aV_~Vpw5fa3)g5=Y;PyV9{$_ z@j;(vT;}%~UFjd=IA#WNgMSn2&GJSjahmvlq7xta8BaJ~^m;C+tFxy#CR2wPt@&>~ zhL`7bB5KjJGqfv>AGJeo?NDAjA{VPPc#Aar3k@SR-wXWXNb};)0q@Chh&^ljXY@)M zo{?0VmNYV@Uk1A@|CaHkhcmX6H;I4oDfCC7TJXGxj}GIvcmH7@x^3aeaQHZFj)vjr z$Dfo3yf4Y@j9p^FhSTbFvXVbj`b{hv)r>2$T zWYeO<`YnO%*EblmqoB^{O98FE8(_C_V0AKZA{ove*6&(4`1OtP>EqWhtM8|<+c?zG z2Ku`A&WH886@Gqw)1Z&#WO*}StiE5s&N%iu9fal2(ru%VAN_YU2sbkO&|^iPML0yS z0L<}J_Myj${vN(IuO?ty$0;@z?;rEW<4qWUIVybh!qaTafe+sCwhXIN41IfP(P7gf zebwdc>u`AU=d;mHhgoHy)#r0ER=@i{VytM#dI{KC@f`mdd)jtEQi=BJyRhJXID6XK z`v-p&#OKd{%UDnE<>j!3h4QZcy~ltSBL5uo*h^$rJ>{WdnOH846Q_%_#Cc++$ZN>_H@Su(o;M^;RZ_PZ+ONZDcP(e3we^{ znc_tXw^*|IO^ddXWP|5Wn5k{^`(wB%RP7%)$&2@+Hb0l+qG2>q* zUL~6A5AN4X<|svm+a{Xp5AwZ|9}piGpAugXUlQLGe=mL@?iD{3%~}`G&;D+v8x}b- zk#bA1t!R39;Lf3n^gmwgCk_-j^pO5%h!eyq;(6i);>Ds}TYzH~8GogCgLtEOi+G!O zzxc5Dl=v(0kK+5HT^Icm$qo0HZMc8z2wr!{&nVICFAaIIdzAU~e{$6}v{7B?*P^SO2 zm<&5*jOsJ&Aa)V+#UA3B;yCfg;&O4dc)j?r__+9?SS@}kej&ES?+50mgE&kq6VDXK zi5$<$@Uz5AM6Q}l_iM!)#5={i#b1ffi+>V76!(jtihmVd{C=T+4xlBE5L=7cVi)l^ zu}JJCo-7U!hl;~Rj>x6{N#eQU4DllI5^J!KAnp`j5MLAD5ch~R z;%DNQB1il(zZqh4v6aXX!1T`*IRcn+e~}}ADUTL80+{l-B1ZsIULbM=Fy&PuM*vga zB60*U6z7PX!9f3Y;#QG!Zs~rHc%S&R zxKn&dd`)~${6O3%9uPTyk9sjD!7xK?B4&&2#R9RXc#_y(}hB#kbBwiz~ z64!|v#M{N~;v?b?ai{o#_&f0(u}1t@{8Ic%?-yW`-mmtY2sLMyf{sq zF3uAdh*ya##I<6T$Qdcj&%NT4;xpnd@fGo1akqFttQ9%Am-<3t6S2A2UhFL9iJZgF zc>Tqw$hq@$A0v(zCyO)1IpR{WQd}Xf5jo?A`tA_9E+^&3#23Vu#COE^#E-?##IM9a z6HiZ;*i7V%9_sHbo+S1cOT^Q}$>KDzLYyrw6R#0Bi(AF*;yvO{@dfcc@dI(6ctGTQ zZRR&aY%g-}I=bhHMIv5@odDkbaQcluV2Ga=hW2-NGs?IIY=1`g{2uv**@@%3*I3Kf zl5F2ScXvGAU2uHAHP%w`LvjgzR5v^@!SZW3*I#3e>ylxD<>~zK8Avw2$wNsOGnnbe z=rs{q{>C-dDj2)}>0ZPoP;Ay%`wagEvF2o& zHP+b27YbxvPF;45wP5CRM${T>A&FRH?UxLll=%|8Q(XSc|L!%`n7}_~jWtgA`R^KQ zJTw2+Ype}Ng9(_qwEuZ)toasK>sj>Q#nq->IAhZ6bIzY}+^i{vv$BtyIvE?Q`{jn) zgV!6N^1ryaT09*y{KX9W=~;x8*o+t-KocJq^nC{HXiSN3jMKsEuc^h@QA<6G{$cB; zHEfIiAw+g@v}xzhoSn_FL5El+re6I2uA`RAhU?@`oHffEzVc0DUFuiczxYTOd^^MQ z3ODqB`dF8|L!`_1N_+6#lSelg?^V!<&hPLW6y11coiK)>p?oF`%VCe9u-xo(uvWg5 z`StO)E}v*e!kzEIR^QpM+c>a(@ z*liqGzj6JvrSS9X3*k2m-`}YZ-9vGG>tXln`=<5Nu17e(zGgms=)Q>S`=18-xPBVH zciY2SZ-awhUwi1Y=M6t0;`;7~opIP6cx2%B$#T@8J?KaCq-ew4fZr<@*g*1QxaVPz zr3&lCzHEM9wFkrS_ydf!Q!Yk0wl#b3eDHV+#$S$ZzIx&BA$#87TyIQF1@zUx%^o%_ z(pNlZFeNBpQnJ1vb%_4Dp?u2-gi#F&`&e&r^235S2i`e~hz z9P7h7SmTM~aMn-jir}nsuYN<$DT(Nw-tT%ce%r!n^`8ZL=z976@0w|v4Ty$pzT<=c zT{8{WKJIUKqYaYZ)$h^|4VU2#(eF}pe4^VW`@8yG^7DK2@H$?;yWgc-D|3O=>vuWs z!+pb!tIk?}?e@sZe$zs8Q`b~Qveqn`mb}8!$_NRwq}jsdm<{sSebwsSbU#raJuQn(D~2DOKrfnpKA$Y*dx8=9Leffmv&@ zLdw2=i<{gKUinsSpY3neW^cT@+Nry`I`Gle)uA`H*9`q~U(NI{bFf44sJ$&u8L+qI zvFoax1gS5Yh~Q}?LFG)D~O&TeJzc?`ueHw=tIP1 z+5unMEmBA9Jtnn&+AT~vUOv1uJ$p-~-@>F{wzsv>-*2y%ej-0igXw$q;Me1oJ>c5B zE{a}>vNHWdUi(Iem~#2!`O{|{um1e$hvGW@VZFQsT${IWG*js%@|G7p-j|*&BhLxz z$xFk=v-xHkHXhShUhRCeygKma^6Jp?XFm*InYuqa6>F*W4zF5x;G;WkL@T<{w4z}< z_tl)g^G38RY8Z%?6p9`ljjV6HHdq{4-8AOBlNn3f;N+I<+Fmnc+rFA}whi3d;*`jZ zpMDVd=?Ju&(&(8cueNR3`m^rL%Lud&e?CXR&1*|unc3b(piSC1OQOqBC#~zn86G`D zZL3A<`yT|ZbWeKt#ZWXontp?et0rUJ4qP+IRh^5H*Q8Ws6{W0cg#V4!q*l3oQr84_ zWmZMj^xu61)}qVeT68}Nah!{}tV3>J&@}`6{BI$~6M?+Fk$9=<_*UQMh+S3n_< z^gG^@0?FNpP*NK>22Z2iu0wY;g-FtU2FX)_#5!~w4;j3a|GahRINvS44&9xM;YNN# zghJ);LT*k2lFVz?YPSp0imyZGWSVv8Ho_mhqgOF+Sch&GB8P&RJB=8M^rUY{BG#e1 zoZd;9yWri(-3>wO&^@LXEtgBhnRV!B>5X8i$Kjv14jq4Bq;kffw+`Kv6rZMO)}gx% zqHi5K<{+KJ#=Ldt3SdiT=Dc<2&ZNl9dF#+|Igs>i6wNwxTZyqH~uF`UI_feb-$*eZ_u8|PbNT=ZulRk*)oAu-F!ec3& zuU($l6ffEtn2qGPZ+HR4f_E_@GU|!TjfliO@lzurZBLwpmx_!EB<+bD-;mKS9+$%k&|_?xs)>W|$ylO>p#Q;3uiF~n~gBLB1X$&F!8w1Wez6B z)4+XHNH2%OiT*GM|K5UdyGV>eG~tjHqfnA?Xc41uTEZbaMxn|}lR7%bAe&d=ZG!UYm5J>Xn2z715cq+w^w>d+ah`BT^&{qdg_iCCqG zRkk`r>21UcJ0n+zMy(Ff9ze`Q2ujoi7X(>>Fh&*ru{g_M;Byvy#;p!f^73%0Asax# z7oO%|sg(=m-JV>Wgk1}4%RxkWE1sz;MJz{xXL{LZctm{NA5q>mB7dJNA}VABYJ}1& z^>Rn)A+MYYV`Hy_-OJy}I&r6JZ*+!IyA`ZF= zgZtY%3&Q!WV-#M8!DEEbb@oDM{vhB@7a06So?NJq$9 zDv1(vUL=F++` z9m-6{x;01%&D)=n)tc(N?Bbb^J2EYnhPva9{>0*rOpTAX@h~XY*n?B!MULR{yKMa8 zjyvM2j$hPqM_iNUuE}h~9dQ-MFXFf(L-M35vtB}6(25Q`pYf0^mVFi@v*lerrHefY ztQuw(KHfbco>R}opUp%VHbR|v?@k=gU?Pmoo#$e+<~{G27IQ(#YnEs$#>JOYxirk_ z5sBuKsNclh^I-3K_fPAM)cvt-fe!YrcMrARXchk0wx|btoBOD3tkxUNN3oF$EUu-N zgvDLFcB^xg6F*6ifmL13 z?HGJIko!pM;EB2Yf_E+KgY{gxpLR-*XhCEEmsiP~cJ`vnmkvFb|AQA!UAi>bXlgy- zoU<=m8k_@<8IzVSoyI7^LAk->BTI;rvfHlAn>Jq^1wFK2N_?LB1wg*}^N(-HM#ZoTeLKx1G%{O>WpA{Wh;O--ZyR}m z2K>GD;q$LxVwTv^iaaJ)8j<2HjH600`8n*xZG0D(Z(Ivj?O{tTaQ>B+M=|qo{p+Lj zwRcaDH`D$Z?Uy#XJaR?ykHeKoSB91amt)7h{uz^#hPO;AJu+$J5lN$)CXH#FRGyhM zHa+RA)P5Q0EBRa2OZm3__-sZ0t1p&~=SeYIVP>z*g z7#jAD@%I9pGdwUNPo^j96GEY2Q~Q9t!#&M;lOn1ZqvOCb{hv)=X&%zX49g>`YnX)*Y^P`ir?C) z&p(EQzt3zOSe;)$U*em5!fzG){Q7Er`Y_BPp1-ZI`}O@2`kwSTSnK8n`XcC!=XqlO z{9{P&k-j{T$MPdE=f!)QGBWkiJSy67C!<^KP-94*K{%ZD3cwuO5$;f9NPY)jn^y+h zi*WJZhmd(bc)Skdua_*8gZ0O9G=s6{t>GAwzAYW+L-^anrbYUS=QP7-7>;2=^4~g! zWHQ=4KV#U#>a((?-~Askh6Ks_4qGdp(?4SjNe+@?eR~IMJaHV(7?KW&;6@J~gYkoU zPljQg@!s=I>#o?_eSA2{xN#GvOqh7ixXI^TI2|v55++QZ{EcHZ`Nm+@YDj6~tyIb} zCOeTXPC`#d$vwsX zaxW3f<$kU>NAA3j2XM3Dw*js-!fTVnt;GOMTEbML zo>(bfEv^-B5pNgo79S8F71=JB4(}smt@y99*3Cm`FI@9wr}(r5POPdtQq3lF;s))K2+p4cq&OqlI;H@-xYU@HR8u2-?JGm zO>8By>x}N5M6A zUn-s@P86q$72*PMiMU>jiT8;QiLZ*k6+ad~6EpEZW%^CUZepI;N9-#O6^Dys#qr{F zu|ixRE)lO0SBV?MO(I9RFhBQ-kBU!-yTn(-H^twJABcO!PsGnfd{Z*|Ln4RKFufzi zHe!x=tk_-bBlZ;siKmDo#W5m>%90){xKM`Z%&EnnSFT`Jp z&x&t~zZW@@i2A+|QyO`4hIowFPHeaa%n-SsDsm_i^_?xw73Ygriz~%V;ui52;)CLI z;x6$I;-AFNM7!1t$38LrW@3)mQ7jU<=_12L#S(FhI95DYv}?P}m%K>4MqDLs6gP_v z*L3-<+}{#w#lMJ0qQimtI!f#*_7+EpXNa@Kx#DW^dJ&i5x6WzrqvtDs4K|q5-Yf4= zW2+0Zvpsk3e|}zG&z?QAv%$k2TRprv67$VzxBF3ZFY4sEb|>nHcA|FtJ5i^7(@xZZ zlC9i{+U!6*VOM5|peZmXB81Fcq92fJn!o?WvP`yp?}e#ncl7jnq%g>3edF04ty ze#keKpIzg^J!tkw?uh-Tr_^kMe|yMFdtX@74q=vHALzE&H@Tg0?^v_A74}Ik$**bO zst9{b_oxY#U=M5Tr5w^;&o{N|P;+zn1vQtqnvMOHJ0kv+nx*yjRmT3#y|KS@Nf!2V zzWGJFoAadTL)gvv$X)yQx=8hAlUgU_U@B6Wg&cW1Hs6fhqL*^_>GDl`-4geN_pv*3 zprjIY(X1%aGt$F7nR_x%d>?xG7ry%6s2DT?;ALpHaMV zu>8#t9|vn*{M<+jrXLAiL7kBhe}yC+jensA`!VnK_G8{iuMgt;G4n@I=)?Ga%v|R$ zv?sA2GuwRVBkjjL9D?1C8Hw?5`6I=QgQcY#TvFG=;*EnnmEvZG+OQMX(ECgXvdSrH!sdy5g{Ltt;j<18~V1olWg zC7f{RuPE8S?Ow#b&4;-cF}F3=0NKXhFe27G8?YBKX@2iHm*&A5Kls~QV_@lh@EF+6 zCcp^72B<&mHOB-fC8j|Gw;u*<*!tTKd&js&oLVh)53EDArhmd z$P?0HwDj_XtQak$O{&;_h)6T%opy>s`URCmT#=yc`7yJj4rZ>Ww zRlzD%*g-aIe^{uGyY`SvV7%>J2YY+_U?U@Mdsq5g;e{+AsoC3n6?-b#U4Xdp6(eF7 zB}U9KJ4kLpNN@Ai`XLj$(t2STZW|2pGKhQx#!Er_rww9WkOI|s`!pd1hT^^3OQC+q zS@9iCqb4^D_W}%ShJ5=l<1ySG7;k%5v%eurto$@gg(34$*R0cCpm$ZS7y@T=@Is0`*MM%Udi-uA9uKCK_!KZZfB29WGiKU6rn zoA*iV%T=7neF>b+!DbkNJMJk&3XIwMl@{-c9?nZ|Fbpnkq6Efl{YuNZp1YJ`K%Biw zPv^xt)&#w1VT_h(Cg|xl=vY`Dfk6TKlWNwpt^asfSOF{`DgU{!nqxBl>#`}9lc{>S zMXejFS8nmkgpEaR@yl!~+|Gr;fH7=qhgKh>q!T-koEi7U>5Eai0tWeulFQ=0IE7|w zR;CQ!67r6?FE=Qo^qPE0=EX~wzS)r4$6e48Vw5_=K-*xFm%SIBzEEHemVo($4>q@B z2`Djdo(pqL>8`j7b4uv}80scpsOL-RrML@oN9he1gdajG@7hj}dGF@s4lc|crM@r- zA0?G{`9gs?d^zqN;_bvpJYkB@bsnhTHJ+an$o*4EC;D_BR}+Ixp@ooG|+`o5e)T{D!0NzfjL-i zmCSnt_|J-W%l4lY@7`o`_c3B3HMlS}O3V>b8^FA<9VC2htAKCRB#VDcnf2;zIR_o8 zcx-G3SLTU1C$Ec#;!PC=;IqMO{kz2rHHc&ld%FCg==wn1hqqqDM+N7Y?G<;z2dNAu zS>s-Oe<-^08t{D3!WbW!&56-<4-9ijvh)XsVqLKIJs%_-k55-VY#5*9`8hZg6r1Bv zBQ$wu_8)%v5u^D(d4y(R!QZt)7Dj0HiEAJf5{)`d;*4HcOih}hD;2Sp_*j+|_5ty@JY#dmfo8j>(Ejp}U1!QZd z*IFnUn4&;Fzv;01(|rj0vJHm=(`9-#UH0kv^}U5bh}m$nhxNMz4t{-Uo%mwm>0|O% zA75W>99W&dLLbA~!}?tV2fx17K7DEMv-&o}ZsSl#I+X43IaupP`1$p9gFcp%<;{Sx z`nJQ)IC(HUevLs;hZ`4+@t32>S1(QBXUlaXCmvv zJ6Pk1<8bz?>ww^_6W;5;ecYsZK7Zpzb>7%Y?oj95i~c)q@Be;}I*#+?IJ`7mP-H97 zjLS>+_R*xf8J7o{_j$^L#WCVE(TvMOxVe(~MU3P6DkYn7d63sizEw2ilAzb@K?R!e zNTAt+3N+)7Kpy=5%xj!v>nGX1$rhp=kJn9dp7;at1o2dHgg8cImmKxY5NC=PiE7e5jYh_&K(jmIsE zz1;4S{Gj-#_>B0R_^S9@@m+DZ_-FAGkzX&FURcZ!?YKRDjii4^(Od_R3ncdzPZIgP zlHp6ma?y_CGuH+D=gWPmXs!>q-y!)f@eT29(T>a8BRLBXIHuQ3>?8IS2a7|++2UN$ zj-%Tm`3{lO>ZzAsT*;?JJFe~}$sdS&Mf@T+;lpBUF`OTT~ z(PG0r-}nuh{wIq322FW{$Zyb;r-=LpP5EMxAE7B#3w|PZJ8m!uKRBqrk$9wd zl-N$}B=!)G7YB)_h-KpG;uP^5@gngO@iOtpA_q<|KR1bYigsM#kr|Ya67$6#;)!BE@pSP_vEg{bOXa>;yk1-{-YniKJ}f>i{ziOL z{G<53_*c=z4_M~=NbxAKo!Ci4^ZuUW?|SCv|1IP1dKMNQ?%Jl?bC4RLxA{=!-&R&wT{=xozKdxDPLbQ1_C6=-} z5Do6f7p*>RZk+6_k8~(bUVZeg7Fc1lY4q+|=bf8i?ye2I)3!FS_wL#d7y`p!c(2ZDx-wSl8L)CO9*Cw%dulign{aXt`f zgsnewcLj=u7T?q+3=PZsU-hWd!R-((+S0%CqXYN3NrA3w;F1KJbDXnp>*D+YS0?w} zw|TMCVNKNSQC1u2R#qEoT?{j2U@;`-BeXvf+V|qb=u1vkar5FM_XU$1?K&YEi1tJ- za$rm@J{shV+q2efw(BzJyJm4xm%bk_U+m;Gi#pKY7A)&Opf)meKy7F!HGcM@^U>o@ zi+#aBa91f_2D$EKtE$$qVS7qaUMwD2{AlF)+M*R1Ycj8Q_SG#)UY{LpQx#nCrqjB( z(dx+h^tEYg8tsoHyC-B;C0(DoI=m*d!i^@aPmUGVM$(2>US0V@rPJNn*L`uDb?)`U z_BoB#M0ZA?MJ<&?{}8>u)>(9aZQ!x{YeN-Tb&IUg+J<-jx~)bnpA|JBygp!rIXE z!rJgv?wW8xC>kz&zBaOAcr@vqhweJ&%d2XS`SQxo+-nPJ!?zdIhQ=cNe1v@tajKft zr8EvywW^Cecm(qQR&8ietGck$sxG+%?PBN=bz!(CJ4e)|-LiFmD5Y6lqfrm+4`ep0 z3pZ|t5}=e$;M(R<ji zuEkzh1-NMAeHaPaXIGo5l>MPV+oStNopz|T`T3|}lw)i@>gC9~aG~2P0RJQELWS=B zkX!v?U|q^bja+wai=Q>BY*N{{E>QT;em8B{o<^>_KgkRpTN^lG7p}3scQxkt z(4Pcx2S{1pWOtqwpsUpX;&HVw^=tLIw1Pn_w%E{XtQW~<hI})o$+VZQ{O@^-0O}1k%*J}OZu-h{*x(> zqI`q#=g-O1D;R#AkvCJ`M*sCD{F9XLp>L?xfoe%#HM(9r&nC;xLb@^0WsrT$Gz2*E&WHHgPDrw^K0ZFjWed)t>zS* zkHPh68OW}Cn~Avua{AnSEZ(}!JMlQY2D!<-G1HjJ73p8!wsZg{4BnUKGL>~){Bfq5bCFd>gZ#d#q; zIhPfg#U7ns#6#X`LJovaW24iPohbA&q{ISIX; z>bmrA&MI%t*591<;T-8+1aJ2~SY5X{(R>O2{S5!$)Y$Ei(KI!faa6{raAUXBWs?iE zcT!VNf+Mc_=8hRVn>qv?xgoiu6(waN2(I*yo0`g@wOqtDxiiAH#>tB)5(eDjqGd>0 zQgYps)4YMWozjLhZR|F2`-ZRYZ`QxX9_9Wax@q-C?50EXjpxlsh-e6@C_)pL>1U<7 zqr$W_PDDq&Ub)0Yko>0fX}WBQ>jY9(_D2(LW<5}a{;c&eIl>G&X8K6ahZ!zP>tn7> z)EcT8x9v*}QD3yTCwU{n+PNRVnm9^e#TY*#0)KDZFl|{d@F3X#;CawC)$<^z(YItF zwKg&OMi2$YdOFe5Sjz}=DLSVok~qCHvu_Q+3}VlX(K6i=X2xil0fV|D*hh*$Gh?*y=BzSsitYC(Mh{a)AEV`IPna8{Wv3_1i_!9eC(Mu0 z@|q_sh|#hS2HE@=2%DBx5ikpDrg%aqMhh3Wz{ufnj25nN0U;8jh0~>RhuH|+Wvu1I zy)Z#%=7Jb4&l&ep;&sn`e(ZO!ykp!)5S-ME*#iOJ{oo8Xp=PG(3@6yKamE@n@LVqd z?>wcRl^6|!N(sbh8RH3|7%k%a z0x=o}`CbsC}%*<7-{n%xNSY%m_V&p4MQDs}`bme(aid{b)gnAFbXceRK~ z;!IvOUczTG;ciClnF+OL+Vk~oYTq+z%Rd14sSY=+Ws@!HiR+FRINZJKZdS;5-OUP{>uxrDaUY1pXqgX#3!Ej`V65>M3l_{lS(y>G zCYIZO{T0KTsfO|X5H9FoRZJUpFf17jl7;yoP82!8oY!o3DLr1c~i+#2|-w-TSyBVKAsSS?i*F{`vyu_WlG4q2QPllp`dll-U$$sPvd~e z{Yb)l;-X47Lb%Jgk0G8h*5Sl17&JmR{$w@zWzn0MqKzbYBQcq@cNCN(Q6Xb&>9?u$ z0le3+_`fqXF`TzdRsft0`L4tuq<7OCZXfqpWPQGU-orlkb>xnhIMTC8Gp0?DuV_!h z1n>$#GEtmh^Fl{^4GdbBF9QK)L>ZWu$iT=)kO&h-q6>T(n3u@FC}yAy3=<<+0X8w4 zA-*CiL!ky43Nb^7%oEHfhiW9`%h3EphWx388l;AFy@Rbysf8P)7G`SgO=_cksfB&1 zEl8v`+E=!4gVe${wHKf<1dRdbVneEhJw)<84*Pso<13~bFPKmA+@ZeWC+ww!jsSH@ zN7$!h!H$HE1wI|~Y(Chv(isN#DC^V$Vm3??R!2O!V~kdY@`WgZ$Xft@PuNHuA$EgF zaxP&c>)baUvfMfijyuJFm|CYKRE95dEkb&~X3A{j58%WXs3f$0grt?BaDTEPTEl|6 zz!5*Q<_C{)!ao+48RdHm%V7`e)(39PwLKW7m)wed?t5Wp@&{m;1^+QEk+gHWIhpx5 zRsR9|rB6D4#+-2#6K2jnXTtPxQzy)tJ?{L9+2bzA@9}p{1*r|m4Z z;EX=Br{)Gz$DABY%MPZD3C_X)>@!a}<&@yOl3>>DXATOc=LXX~_uR;{!SqNr+%ijU z3Z}mn%$(gJcyabg{FjG+w~q^6ToP>ECwNhI_jYaD2WOALERf)=>|>4zW@Z<34<3=r z)KhX>cRdbTkL{cvydbx0@TlD21=+|%H~3%%N`c|1++e5d;2GJ$-0beb5xK$Ksfck@ zVK5a7gU`)Aby9wt$4c5Rt{pWt#lRs-lc#5&J;TtLoteot(~UVoOw_nJFVHfiRB*^{Q_I~B6|=H8gK!O`%LlBSSw(nLQ5 zojIw$R$MphXOA0ab2M&TztTbZiB;A)r(^bn3YOyF;&C?5H@5aeEmj_{w~+(OMvja2 z8!~iM=|Jb-dhU*y)%49%alWzoaI?VVmf`2)1k6h8OmEJCJ(okUwOz#!Y)cof)}aGW z8-!Llu(WhospGAH9``F7a@wF#L;IDY^Jh~3p;KlgVx89Sv>~TO*(gn8s6PcOF|{YI z2`yyQsRK_NsdO$V%tr%*)_&B=`Cdj%g9~Ly`M`0f4k^P`Ghnb;-gW9Z)2H*Uh<0eB zX!l@D6`OtGEYqO9W?f(+$oXGq`E~Yn`qy4>?|VG*>3GPs*ZXBm`ZsSlzN9bcGhCQs`8aVj%wTHeHaAW@PF)pr;T^KeFtj=}Nx7{`ppWhbP z{rc{KKAtD)WA)hb-U~bRu|4pJVt!PWZ9I_aNAtL7!@Zk*=y^ap5f0JgMJ#K3=y^bI zOCMm4s}Qc26+q^X#~U#Iay;a#=VtJ;qvj>B1Bo%bWw3GXeO2Q)Ad z-ROm+dyiE@<6->jnyd7|WLBpzB9DBOIxFP40jxR2!inZngcHuFFbE)Dk#mg874N+RD=L^NaL57979vPHGzJYLN{{b+C*B_W69w{Cr=7=3d({GLN1(Ht?&HV)KQOPA@xpeRD43@$WE5`*Wzp98{!_ZMl|;)g#SV^ zU&t6gB$^?vkTWIon+yHzdhl%}oBJ8u*=tLG_U4i&iv7gXL~~z*|2WB$MDF{+cr!!} zp`(0>xJ0}{H1{|7UnluS@g{Mrc)R#>@qUrr@znpc_`GQDe{g?8^4sG3qPY*kpS{hD z&mL#e)qO8X%nB1S?c&|yFT_X09pba%uf^BIH^e`R?~66!$6}rMwP@GZPeGoU@5bU0 zVrwy5>?9s57KlAXJO8eq0m+YxPl+73&3gE) z_y^I>1GM`G?326QKL8UyOuRs{$FP_#HWpimt;Kd?Coxwn5RVt_{6P*RXZ}WrXNW%( zCyUd>^Tk=>JaK_|xp<|xLR=%>DBdJ)6>k^s7VUgP?uEzv?G~%W{o zE6kGIOyod$`gaz)i-lru@g#AeI7BQJM~e;jEtoF%3h`p`QgNwRDRQ7b^Rr&uByJJ! z5bqN27ata%6rT}a6kip8C%z-TFMcF`B7QD@CGs}|^TnA1q@AzWMskjLtk_-bCH4^q zigv$*QpuymABq!1PEBBXvqigq!Xn9>qCo#O;zn_^_*3yt@jme(@d@#l;>)6)|M<4# zcg2syKZ_0bU9j^ZlTy5VHQa~6&W}7s{+-2cVxjm0k>k}_KD$4|sgg&CW5w~}+2W7H zIpREVv3R+7mAFE@LA+74`!{Tre5ZJ~_<;C`$SESs@5|yF;@jeGagX?k__-LuZ$-wB zh?!zjv9*{jb`$f&ABZQ2#o}Obm{=x`6~~L5(!%s-iJa0x`3muBaizFU+#uc}-X?Ar z?-3ss9~YkypA%mde=F`5_lTd1bz%TNV41(Lm@YOJTZwJN4q_KEPb?Bo6#I!K;%VY2 z@eFaII8{7Pyg=j>Am(qWc$K(9yk1-{-YniK-YMQKJ|I3KJ}vGPUlLyv-xB{Iatadj z^Qrh((M2Bt-P6U!VhfS8Tj<|j>@4PqMdAtK$>JdK6tPS^T|7&iD4r|M5SNHoh}Vd# z#0}ym@iy^)#Gi}zi;s&>iO-3<#Mi~&iJX$favu=?B69gBx~GX*;*sJ}Vmq;u*j+3X zdy6NDQL#ki6fmYUQ9M_iA5p_9{q77_ZsccqFk5 zcoTH&IsiY}enbECXrtBPXy~P5G1tG*jg8`S{adZ&T>tFiFy{In6Lk+~uK&rL|Le{5 z53k?&(Gw2m`ZqFj{gXAoOlHrT>qJW(_H^X8+sJGCvJ_TU7Nnb z*;lXbD}*9C6~S2g|+C#0LRul-`o z>5sJ9up|0Jw10GS^xiK5759GO^t~60;XJt~x%l2M!WED0N$%UOE|k*&^YfqD6AZSi zYxdyJzHst>hOkfUNgmLl&dF(4=WKgoPf}8cx@MIf>ayS;>ie@V!o#23lQa-m9jR_x$noXF3QJze$F<}#~gjkOkZ@< z(aBZrnvu~}SSKMnn)Hsl>Xjp&s^!~=^j%ceY zwxT264@3(wFaMazBNvUUJbh8D^7=);ulx;W?(>S^m9hWD+21g8|C-&-qh^0ObDs!d zQZoA6et>^Z!r>X?nE1ze`|!fN{aQE%cc6bWXy@&ln`a>TGWZACks7q~_8(->68^LE z_RV@-k)(}q!@T`$#7NBBpTYQC$SmZ|+h0$sH*bFmt#;miE+U(G``5u0^Y+)VuQe39 z+UN|O1cci#h&S&(%v)}fH}5_<#P0-=%keMpxohTl2U*}o=U3#@WeYrDFYwt5tv$s& zLcTCzoXBjd_*yFF#Z`RmQxUgAg=hCvxMu1!zBoRIe7j|ci=p=+{)c#O1n(g0Xd79B z|Hr|k@tcY}ig`PY;vE!6)0ZDn(=LGm_jLNMrHF64jys0FFHkgd{?DLDlg7_CZaJ+N zAzJ#o%)!`qAzn}M{kWI}Tl(I($X@z%tec_0cf*!37t`2(_%5P$M^|meTx{TEq%lUq z{!K<&OzC2TJc}W>83`ec^f09K^Wp4{V}^E71RZxgMRxF}^XcwRpvd*F((hmnCQ@8S zk=bx3QS5-;kqj;eFqsn9aLV9n08=QnK#gW%F@UM8q71ABU@YC>n$C|=o>+;Wzv(}q zcs7G|!LPTB2{;>UE(Q2$k}*-jVhH@UW;)axp970~wmIi4TjMa#g(p9SfQ{1=GJn8$ zlk(Yx?!`Rc#AH2qF+KT*2koOz4qF}IeV`s(?a~cyg^IY?;y27 zE)0GHXut-<(Tfdz)<(x8=1A*TtAfS(tSEGCh|_PZihLwn6{pi+6+>8s&uUd%YE?95 z(JcrQP}Xh3^|lSuk?gj?`9Gs?TkrfeES}3ljinz$2+a)rnhh8W`$42O7z*PV8hmud z`WpJIjV2=IPplzm%%Xg@^=YyJH(3KdL9%Or^Z!oY8sPl1>#_mtM3#OLAv7=42{&fe z1Ggj9df;9f?19H&H1t`m2X?RqR|Sjn!CL6n&{SW=yS|FAd==0O2pamVRz-8fU>jJJ z&*L6IS=WgRZ5uiw*=>XK`_Q*-aQ;vhw@zf~H`stBA^tFJop>2itrKsc!A@j-4SiPY z#D%QERl(vm<7QdtBpggu#ads*W?#j#tiortDt22Hjaih>4zEF3w+$<88$Ly{+XmPd2II>D51k>QLcEd~`~-B-gG`A0%7i{BM}G$wGYaB2|RY)WkiSh6Y6zMPp4( z-J@9{x_zEYle!1eL!J0UeJ$FPL3IzNH|MFf`DgsN8y`W7&}Mu}-J|&y#?R)*1NcDv ze^cEfUB@HS>v+WTLn#%HyxNr2$bx)_1Uj&{($zO=CzUm7ACp~8@&mdyURflJp-7Dn z{*yjPh0ygHA9CwS^23Bg4yW_MGPy0F^1*csuYJA=k~GK&I$LcGok$4Yd+DZ_#wpp5 zBPbh!UF79JxIs1ni9D)?^$5H4x^+lRxT&wD_lVLU`W-oshk@ll(^;?y#VU zVEXs}zhE=VFo@uLRG8w%$HL4D6OqZqWh^FqP1XOoU@lTHH;QP2fC--kq$@Ynmt!adXb(?qfvrJAudW%iU4ybHohBomCg6U__c+ADK zem)3KmZ$TQOCz||m>yk{@SD$i(_5m3#?u;#L&q&_+)`_3rvw?p(S_-@*#KYKf=TfG z2DFga>tfmN$q1Y^Pu`D!F7$0hIku85N}pGM__dAX+TOEzN2V$m>9_5ND;U8F_-+W= zNc1ps2*EdcF^UMc5rYUfse43fWg~w4%7$}gZVkhUOAs(mb$uy~09n8=@6_wd85yA1nc3j+F-_YZEj4E8zGCh{>Oug)0rydJuYLsJ=(M*?fxY8eMJ z|9fT*y4InNIXz8tjIQiu4c4ar9uwCzhbWJ&Kfgf(G9mf-^HgV+sQ5A}AhUbRu~Y^c@hj zQ*RLwN3iXsQOh|{XMw?25s?y0(BRiIIPnAxcjg|9&9H^T<5&a?k2u){0lSUnkemfgccvP|GgU98pjw)}5zx;B z_panDXtERH+~Cg5kvBEWOmm2X38DhT=LjZnLBkEDA%r{n1`&Mi7r6;{xTOhP6lu*m zd%lSwfs^ItQW}j>4Nj$-P4a=x(FoXbf&<1f(l`+TJzYdm3)*)hK%|1;FBm3jLE{k@ z?@uIF{u#va@`U{UDrNEPXf9=FAO}1)fcVnPQN$qxR2@q2Y@UaJ9ymO+;xbOm zF|&wRh+xVVcfeR}4p!;6AMH(Ty=x)9L`fL5XOK~AIgb%r*qN#>oK{^dt-3I)Rdunn>Sm_bQGq;JXwuR!HG>j# zSsk{5sH~n!H;i_mK#2;Z*R|Z`4l9Z7dITKLgzECCX?01bDB`zb?%Kkry%v=mh0JlFdM-x2X;I0&%_!HdWa}AKqg^cIawQ9Xl#EIaOy*)E zu+#i;Nw>yHin&-la`_{UF6+}5oI}-9>1vqNJRUzml51D;t4*q1$u4BB8asEqx|Z~5$Izc8M?_#Og#(l6<8Ea#W>Iw}#*-e3p$rDnR1 z=baBXlRxNiQ`499?V5x7!okUC`H$4Rfk=e=JL{^8CtNdbd~or}qb5(8bm^3_6Z0@j zbNtl2V@rCRc-*Kqb@x;NGPaKzj8ArkB zapNx;d(DJtqo-XzdHhtwp#!H*8wUXh*ccS7YvR~xm$}>+fGC48x;qF(8uyA^k;l*4 z`KLu7^O8M0G7X>A)o$wM-yCU>7nzucPs-iA2eq3co!U*~X{WYq6KN3d-@HrY+Fqts zLphi__;1LNnJLLXF&d662=$MKBHzvI4|_fyeuW~lO7mfV4VB_hWJxLG{|Z^dP-J;& z{|Rv3G3UOS`H{Z``H`QN_6K`K>Qd__J3c&8a!KbFoqKj}*|B5$vpaU|X=*lSUl}QR zgnBpE=e48W4K#Ne=e54Bedpu5OpQE`ns$Zaxh8FM%-LtP?_Jm~k_ADV@%_ly?IuuU+{KJ zvc7WIz6>k5HxFNgXlU_i3*e{M_X+CDLn8ZyZ-@By-3i;5ff>wh?S96m&Bdp2?sceAdVCThZqWW1wB_ve>83w+$Y~-ejLN75RF4 z2lVaZ6LN1ec?0tGprM8BIi%i?R zU?T>25h9x)p2LRqv3{;Iy}khB6uTt3`1+C&GScJ!75XqutF6HIii`Z8(1+o-Aohn_ z*yE|?$LPbfLU#5EuLsnJ!C{wNSZ|-Cr}Z56Liv4Nm}(b+YS-bE9t?leryfinG~nM+ z59W1jAN4Xg&dI-u?XkV|dx(7Zls?a&B;RG_d;7PDw~`p}%aopw&u_KNf4}?(vD}te5}vi}hsU#6drs zgx^?xTamv|Fx~WAaIrX5`S@SA7=Nz(^X2o0eb#fi{7EFrl_>tFik~ZgiTvgA?~?y3 z68rrD@kzzMAigZVp>)%8LH_p@e?akHihQWU_SO-3jMG1oM7e6Z1&Hsc_^zV;zh7+E znJPDcgnyoV(<^{~sr;)+)O(F+x&)}#bP2%Qm5^0ihRGB`FhCjC7wZ|{Y6UW3tsfc$R96%vixgF)H_}LsnTu!Kk8p1e>DmJ zF8TM%-$J7NW8#a7w|V}^|CaoBmHwe<^ZSu*^ZRk!1(~j$_WynnpCkWB5`Lb1`@g^N zJJCluo4=3kD^R|(ly8Xq5z1%(_ZRuDP`u6Chkv8e=aBFhDg8G2HZLFRyIcMPN`IKd z`hTbR7Zm?T`EQcwm%ZZqia$W2zQ4-njXwQM67}VfXovmZU&QChZ?AlvNz^+?wE6YO zf2;DLCoLU^lM%Q0M&1{&9Pi0U`z01UL4IeE_lr#LC7vtt=WE8FFJ2&y6E7356K@b_ zi*v-~Vug5@c#rsN@j>ws@d@!Ik@v7{&u;N8@iXyr@mujb(RABTt{$(G;1S}HBA@3o z{%EnI*j2ROaFOok>7A|kf#NW6gm|%dsmN&*te>+m$eQ;JoL9m4mEv9EJ)+$=Abpek z-->qsfcU56^Enpl`J?!U-cuZaGBXRmy|FU9 z5Kj~Piv7iN#i8Q);w9o0;#BcEai%z1oG1QFyiL4Ayi2@CJna1vw&zKuzaYLOzAFAn zd`J91{15R9@mujbF%xyOzwm!1jSWS+uY&FGr;bv52a!`> z=6%+cN}nWND^3@GD&8V46c>yCtbWrIDz{C1Ui3OnugHHxd|P~1+$Y-o8SJm+SBX*G zzr@A*Vk5Do*haMbG?eWw|A+LO?0yaT&sYA7#7o3U;#6^lSSH>g-YRn98~3B#zk$Dy z|4VVBxLJH$^tw&Y$+!DDlz&*8MVJ@HfVp!lu$otVk{9@Jy^d0?*m#v*6tG5t8v z?(^Vxliy41EuJZ!Ef$NzM7!@p`HSUG5GRY*i*_G~d^gFTEB;(uBCZq@qTLsw+`aNS zmyqqZ`$F&;`F4K@|7H2Fi~j!bJ^BBvo)c#)a(&H3&Qqk%$vI>%vA1}pc(yo194^+> zZO$vG}R@rC2FO za1YIX$Q0{}xgs^vnciCTx=mf>pDdm#{m<5jh{3 z_1`Sk)N@*)_*G&}J*Nj0|B%RO%dGEt@eT1!@m=vl@hkCLk<*-6zLD5YJXY)|b`|@G zg(4?Ev;0``GI4@^H2vR*oH0%R z1(DOF>F*IaFPgsBJ>tA*`jNVhxng6nh1go`Bz6-ykDBENiZ%6&E?4|SafVnXa;7!Q zuM|1qn!eX9;=F76Pl}v%P5%{<)2!)#C~~$n{clB1x~5-8&UhBf_pBIi`ouMj!4n*Ogv&Znlo zP2?nM`mc&_ihIS6#81RZ@sP;5)GVJPa@I8cwj$?N(?3x>T|7hN^l7FK7e|X1i&u)1 z#2ds?k<+bNeu>EG*7WZdIbWLoZ^fs?=fppXFN>T+&HVdBPNJs&H!+R}s`Rr(+*SwF zL`8R4JYdAvKO=5~Tz;|U?|*rUZzpyV`R)SOQ}g%0eu^I;7KuZ|G2%G!GI4@fBF+%Y z#GAyq;sUYe?}cj=zfRmJZWgzQkBQHTFN$aCcP&13t)Z`VVo%e{avw>3tuFtGzE+Qu zx;QJ$eFJ9XxR@ido)&p-gY62UE?8 zuU=ZX&2+Q==Tx)mtcb3xSJAW}OR8BH@2G34S$~0QmQ&24dKOf()~s!j1=Xybg$0F~ zds}@w?<;6nm50iqnRRH(Ca7j@K>ks0&wY@}R#mmyG=pMR^Qw$Cdn%(_n^ncin^k4@ zhicXUXlj)=uF8NyRz}dMD*lTN2cxx`Kt<~jsAWM>tIZKm)e4t4tjZcf&8#|w8xBSS zs%Aa?2G+M`O<{*0t(X;AzNa#$Jhrmd>OGYmwq~!`)qvVr;j)Z7sG~J--@cQnqecC! zyvhjFuRiLQR~cIq{i0qp>tH-9uQI!L=;V08cGM9m&sbdg@Dx)*l-(4!hqu5JFRK>c6dW4Y+Mg8)RWwg3X~kAk0d3&E zce~a)7_LR_ulp*4P7fBmw6l?^X=N?H?89=XoW)H=s}7X4;!xJw^C6DMKH-yV74WE? zbRZOoug+b3Okun{wj^g!c46KJA*gLNENn5iPT2)>&na6q_h)5$=58-@YFpG=JGiqy z)V5j|Vj^MBW@RJF?kL+`#$)E|o#Q?*ZDu=lL_??HycK#0&V>l&7Mc2h)>adE(Av5h zKQl+3f}PabD&-H);ml)DKJpY(z1G%Z=He?zNv*9$JU7NO?35nQY=@+j)>eq+dGeRm z*5#;5T3ff%^jcf3;h5HzJ@Ai5??w@5ZH+`Ul(&utVrvlPwYK2l zRp>mX@&Q*ipJIfDGxY%7mG}smxEBBYZ8mP%B(60GZXG@%35{ae-E>c(djZ`WVc|9$ zuIXT%fS<_g;LFxm^C^ggSgmXP)!c~}iT@3CTHqYEz=$5*eSP+CR;s#Q2y-r;=;9{07 zVk#BA#&MPB#_2)P%e=Ah>eysVQ{I|Jmk*RemvFP^V590nRO@oS*LEqsFV=;qmN^f@ zVdn+>uRJ+@U_eWTD`WLJdsu_>`7JYtlR)J2TVqg<$I7B)$>CO#O>rfizZf}PN$2zX zUr_%`e9XqC&Ee)<5aL6QT#9NPf!&i!QLW=?#9;gcMgyOy56;?$f7F~$IXBTekFS2d;HIm&nIDZ>`+j{4}%Hs7Ys>RZa z5uiP`oDHC;)<;Oq9SWn02Gx*QUjv`D;Y7sLt&19hMl8A-;k9G~CRzjdCD1j%`TP>- z8sL0>sdJsk(sv?+ri7Yea9Iz$h*ayuw`s5wKZnu4XSE*4u-$H*$l`aiifN%yzKSMD zwkq1wU=^prXyCJ26@#pbMl5#FE<(Dw3t=TMyimEbV-&%}P7}5tg^C^TnI7PVTZ?Oi%@Lk6>-}z19 z2lYDPUL|%S9ARQtM>w&oBTVe7Nr29(g)52p{%yprC`d(ZshpIO zRu}`TeocL=T(57{!0THz^!iqfQuF20#pWSBO7dk1C^sxO?JQ2G z?dJ+d$<+wZxgpjgn06KozL9`<*1s7cS)R^T1QX1n@f-p&5^4x{rY%kI={B#3;IRb- zhxNe2&LsFMl4-=y2-{v6#>)00Bzy5QTgfoO$#+0Kg~nHw3F;{{zI9G4K_hA-2g*1! zDB^+cCfG(a0_(DcO-$Rt>@HjB6)@g(jj4t1YleXN(?l->Z2a^DjUwmFNYJ>#IZohc z1{~}^Vvd5IekdzBgQwbY@!eQ*PBXewh;1c0?s zZW(2n{}D5XZUbDIsWAgFfC}F;23X-fPGHzaP&!quxGm@9-12vGN5S;Wg42B zEM*A60~9MJ_&cD<_|Vwq;)!PvB;!N#O-mW_Iq;QIP%X`GEv1;?c$16|O%6xM`1Er! zKJ?Ph&+bG}OnhrQW(dLShDrL+;JZx_Qz06fIf!V6fWtPFR4&QJx|$(CZI0loal#xz z-jCgm9a&LI<8uU@{VGiNhK?H$#Y7$gbP5Jg#)oz}0%UoJ+Yn5~hsJsr&oQ*s;!zz9 zZXNPt18ni<%S`OF&h0ukPqvk*+-2dQvt4ZL^)J}uM^<6h-;{EFww}EDO(ybIrke*jqdVaJD9%FteE0ihy>lOY6ho)`9q# zj_rBaHf@NHnhn<-9z{Nioyl>}OJr*N7jgW%0bfLHLqIPQZX_3RB>&xFi#Sl&)$Ym& z={(=>XxZ{o_WWxIxCF4XU8fEvI#_?;`bDFYbD{|v?u-caFB-1zas8q(00BoH!3zzJ zys%wyxEtU^6EwylAQQpYJ1r9po>VOpjVaEFC1`L@p#)Lk;=>6VYn&5J&{*f3Sc1j| z=fo2<9!5a%)P5bo{d$${oGCLCG^Qb-2Z=HlKO^CHGP;KQdcMU&Eibjd(@v3twj%jC z1f1_b0^IRm#4EWw&Wi}X#%SA1gL6Y|duh1C9(_t9&!xl@G~A6q@)XQlv7>Fz4kkE2 z&~QR$2HWA!*!C}4T1w+hgc#-zP7T^5Xul`_TKKfTls^ML?QaoqW?NbsV+=i>LvWZ7 z>_v>mBGTP^*=3fSj{&tbZK#iAcW~kh`krtngGEMm5t>bK`&c2iz!r{39vo1>GA?#@ zl-y+Y)y7@Uj*=X~RKp^7BjB`pnCil;meru@7`e&ptHb0jXU9lYH#5DCDTq%~!=lUT zuqNWA>Zx>jBp*f%i<@_qOY*8kbY~*qex6WWJ~gebnwmyjGfx`WHG~R!)t$70HPx_K zkgG~l!=if!0vbW6uGrGBiGQWlRa1S3Yo22Ti+z7F>S2pY?gmCJw5a4rW}!PRDp`SENrmMeL`!9sUiRI(t~cAG^d*T`IlDOjUjbQfE}k-ia(s?iAM*i=2& zYPh<0@&%cTjeyLNSHq&qoH#0oUDZ?RzUHE8s$sD%?wT|;EV|neu+s?DAhl#X>Gua;Gt>M&GA$B@b&x)#w}+a&;wl8rSv+LYf*Da~-B&jdsz! z-wGzLu#Bp))0pF#>bV%T$)b{bn^84-f>AZv#X>GuvfvZRsN}$8E;b@f4U6t>gtU_s zbFum~H7vTU4?RKbs-8+$!=&c%xD83JUCEnlR#2l0nX5)mqzWc?8gsb1lD+yAE(gyc z;Oy-OIqyEVB1pfACUd3bcm=Mzh9vun7p4~xGJ+e@b)|THaygS@;-h3#@@&GZ7IW1Q zrMeSQ?wXW5X1s5VMye9eO3iQDggliF|BlsmfZgyHc zJBJ&_?}6NIzof^#krvM_-iyF(`Xnu$_v36XfAL_G)0g!2twNb_zz2l?SBOhZnKFLD z*lFWOr_WZ$Ty|{!zffVSSEN;bWNcofRi1t3N9yIbjWnNqU8Mf-$fUeT{k-^}B6Z?< zP?T!s6s2;eo!SA4QsFkCl%!NXB&D_mNkOT*Oi=1W6O>wOf>QftQc!APh=NjwEPjE6 zrc6-k8>cP>8K_DKO3j6!R3!wZa`Pk8^SVJ&YFebE|2aK7o-m+e`_3IYc08+J$BwNp zh?K0Zt|!$X@64i~JHAQ~Oi;QqPB=H}!`b^CQz{Lv$;0T|PCqT3*tY5?0gmBgfa!oT{P7 zmjP8=Op`4hM7e-2HG*OzV@5!V3o-_EY!R~YP;PKP0nLK(}xBQY4#TN`N8a?3h zi$)Eebj_5D$B#O*Z{Hv(CFQiQI(HvEEs*|@lc93LQ=>;Gm7G$lL;pw$>OUEq)pU;1 zrL?Lg97Y!kJ=Zn(x7L9&fv}{^nC%z8Ba+%rPQK!BeJcequdL-2w36Lwx>_kYv#U+y z47pDqF#f6_xo;<3Gp)~rNf%!^`10vc#JgCj^yiXFRO$Ltre+pM6QjD6SW@at z+G_uMgr{(I;WLiEV+jS}8Fldjb36Ec;RWYE(Vi;#?`TgQcCY5+6rVqC{6*JXI{Naf zE}0a_9(&P6Q^sGLE>DHMmhO(7GWM!V$4^a<`hLs=>K>}bsneze`4>-`IB`5R-cBz* zCx7g;X;Uu0=$dKOYqx4Wt*PDK$;O}WVARnfAB$sI?;E5Z&BM_K}f$QTvtZxI%U^o(vWr7x;HVA%teK(=L zCVT>lc=my>Z!BzI24=wjjeJ>Jgg2+w$j3JmUgwioEk55Q`04AdKnIpLaO-8fU+-+# zz6`7QU8^9-qoKv8@#}tieI5Fx`UNkNB>xKGuAddZl zO-j~x4{TosW>A_J1Z({uNlUv6c6xo;XSw~v`tXWCvc3mZhU0-tUR%7>QKLSt?+FCb z=Q|R=CtVHSFHB>276D^#vX5VYe23GY`m^%;e9s|Y5AT57A6#BXNZ*cz*p3{;aXT6! z`2EIR?#Db#I}koH!+o%AT*$P|3wE@}uaAgqg7{nn*2ns}&h+~7Fiw--0+8nGgIR4! zkN;QbPqnO8yYCej`9GmQ)f%f}f4GG`o?3p4{!}|;XP@xgLj9@JQpK&_0X2N7!XEBa zj~n-P(}H&6{y~=N*I}?o||E~B~@&6Vb zs*`a*bNdTO9Js~e7?ICD89zfb-3Ry!>7yJU=rG;B9K*jyJ|6`z{!!(7TK>!8U&IfT zen9?T<^NrNHclk0r>WSI#P~Xf#QM4@{v`Q*=|+fLJ?f?bO~0{*j}#kZ8-M(m>aQ^W$%^r&E; zLmy$7;xCXtR=k2l`>#>D=_A0uS^j*bFO#1j5$+NnRQzM&)8Y$Ce@T2@@$bn0K>SMa ze-};P0R3TlREYCB2hDJz<^FF?BK{~bpG13mD*aUXXURWTzUdmE{Al_pf3Y}0>3p}C z^_#8%>N7n9_zRSNyVBQ^DDU+Q9#Z@h;53nq_(Ae7RQjdzrzrh8`LpGl{s8J(r1%QOn;sR` zzd`;c68*4CH2naiXX9GPc5-1lhP4rwJ|nOHjORTPX+MI3C&=$C+I11}z2p~){YASz zBAwqASkI;6mEsifT9I0?%r{G%C;m*d>m}0H$iGLtPqgbN(znRpCO#u>7k7%g#ka%* z;+JBT$Y=pZU9sKM_wC`DQ=U`C>JBfykGI>0c%C$7K5a zftj2s-Ym`&7mK%vtHiY;pHr~>Ch<}6cOrk#XZj1`Zt*Sgeeq+F{|L|a5*h@S^JWI6eKI$JPf3$e9$X5lpe!Cw4Z|I6}NoyhOZ0wEGT}yGFj3pk# zY%3lk=8Ij#p5jkL&YxkqL88}*xqOO+k2kC>p0hKU-a@RY4|S5_?Y;+g zANgJ_5wYNA&ka2j%}&JS6f9C)-h5tS7b*{r%B#@=p-EiC(w!H2HnS0b-GOo;XsxNc4J8 zcE5yn+@Sc`;vCU*JdwUw{z@?+ZV_ z7sXe_KZ$$A_r(3;e~4b^>5%*k+^e(wS)$i@YAnB%*j7AV%ok4*PZ0~me&RrJusBK_ zBVH~}6t5Mhi?hU=#f9Qxaiy3L*NYoOulw{{`CG-O#6O6C6yFfv6yFs;6c31BidEv@ z#ds~(pV?vq@d&Y{*hc*C>Oq~adM*$z5w8%v4%Bt>IZ2fJd%oy(pq9z65Z8$7#SP*^ z;%~*L#plIW#XpJfiyw<$i&Y}O`>{PSv99QKpPI_|x=%;TKVIxCb{Bhzy~Tdw0CBK* zp2&H!T>q8gRPj2oRQ#!UtN3&Ac5$V6mw1oJskf~E5pkRNjQEncOWZBKC4M086TJ@9 zck=7t3o7gPx=>BzHy7KBUKh&iK=oJr`J&f_8YkcDLR}}{>q2p!FW2XFp;pOXD{d6M zE|k}S`lI6C61^_e$MQcF4~cx>!}V~cFzI!nIANH+*M;J|Vfv?woHb0}>q2pwFnzBJ z#o5C2y)G0d4b%6!P@FPM-|IqgPA`403$;zY*M;I7VWxXsC_a0m?{%R#IhelJh2o50 z`d$~x>p&f)c&`K1L;jhf*M%yUKTI4idR-{519g+)mxx{$YPI}3#RtTPL{2JZ`@Aj` z=N8lVx=@^AOyBE5ae^^@uM5Q)#q_-{6ekwb_qtG=UrgWYLUDF6eXk3}>A&>7E)=H| z)AzbioK8&N>q2n?F@3KK#d*Z^y)G0d57YO$P@FAH-|Iqg(lC9m3&pv^^!Z?hq2pIFMY2I#i_#dy)Km3ff}HAuLCt&{#Byag}Pq;jp72aT;yb6*6($pIGLEf*M;Kr zVftPdYOnnFL{1%M`qv`o3e&G8a;`A_7UHpD2az*|nSPqc8N>98Ma~nZf4RsR!SrW{ zoDodl>puOndQZ3w{mi>qI zmBt){mEm2`ZiZunra|N2gpUslT(+@JVeKVUtZBJ&>>1I*tp`4w_2T|e==>(3w(%vk zSLQBS8P8l29Qbrr-ijuL4GNch6O5@_w&a`8m~-(N9f`E+OI z%Dm;_{XY!{`+py)y`uhsNGNMj=8kw_PC@QBp(EQ?hL4=x=bN3iSGHOafo@Zf*Qbzb zM{Gl@mDvaJPvLv~Iv&~IJ7}__O<|<4XW?S3vt`+0tn)&AhR3YNXJpJ)M6R{ji&)#i|NT4T1>Sojw%TKWc0pe+4Yw}i)m|c;G43{mGO!(g?lQ?wq}(7 zIjAV8yCe>cp59x>1+|toFUVfnsv>J8)S_y|D?+E#Te2?5U0G*obV*TR<{d?q@m@tx zl)`i+s4?Zuf+AEjw)B|7yo!Mbf~=*5FBJZvuzw-S#>xtZp=E8MRMfgEdhe6_B9XRL z4Ie!Z<$u2~lyOv5!==M2quH&if;Mfdf_smu%0XJRIr3#4SCw-X^?EW7#xtRO72CbD zZbi(FDtv6t3wzD)Z6$Rk3^P zV@;8R;m9XDqu3*RDvyQwQf&FI`r$7!!_6kwq5jg5&|hj+`-@EIFJ;z>R7N*ODzn!N z-1l+A=ogvMQ9~LOM3-c&44sm(r1Z;9zm8XA?=OhtqNV{`v#TNntybnPjqHChsk_u? zM{THZl|grDuymIqrn?j`-(H!$aVOfG(p@@bM_vVWmsE`^sjN$M{Bxqjq} z%*d_KT8gja9;N!y%7Q<7)uoC_A1>lJ&R$%Yw*qQtTRC=WLwzX^>Px#n+;A`)t6Q+T z>A(Yj?}{V3aAmwJ_U#z$@5Dj6uXj6C~p7pp%UdIN1elja7KGWCjUWk_%kM)bO~dk z8TK%L5bYi%7L)k^lj9kW(TivDpF&7#DH6@Je*w`BDbeGO!)KWP3M$&Y4^94ehv?~i zg+9EHW}k^LQKUPNfm2kRKl4Z8QNDT}iAI0P)Ohp^AXWz{8Ph{6Y4ZgXC@|ekn=kr}ve2b;U!XgT zsjKL&gAqE9sqfImdm}+;I8&P-WRIeIKA-UPpv#>W8bOy2SL)nKcN8-}P8S}ef0)Ww z2Kab12wh0`b^M}Qhwt!*Ml*QU$~hNKonNy-mbL<4Nu4g!IPTpZ_=Z*I_iWI3 zmK+YZZb>(2Epd0xX5y(VdMOjju^&w*>M}Nu+Onn-W!@v^K_|*Q>cpD7lX*>XH(jqe zig4-;A4P?Fg;t>DIfbwbkeG8ajPq#Z!?+GceV;YA7%}q^qbgXOPq9Kj3BBp7SmmqO z=&Rs;eSM$Rs^FbH?r&N2VFdp0-|%L{gig0{#~b~Id3T z(zgaUeoETLbG|j;exzCho}|GBu)g{}t2N*+tikOEKIVIgRSXZc#(=c_ z@Fh!fKV;^>;C|rEe|?|TI+3^ks)EILv5FBP{_`xWg5L(L3Vsc+DrT|@pVg{Zp# zviNJPVpQlJR>7WJ$CB*H-_YQOyv8bgR@;z|t%?SGM#<-s@1v~i$+6ax)PQw8>HK=Q zH+Mbh{CxPXCt3O(gwQ1+{sS#*0F_{^0hEBX2C%;RKC3lgDr*QDyoIBNNA@t3bq$zr z4VZ&u*8u0QV0ON77L+A(F0h=BCUZLfCCkZk@7>9q3oYmSNU3Gx)A>OIJ|e_TP4G%G zXSwC9OxEfA+I-is!FuGpAAzEKBe|q zI6X(&1+{CRTAQlVQJFaH;mbL7)MLt-!JL_lqY=*!S@{eq_T<&3=1*1zE`O-fGS*6I z3gNL$Que3zG1>J)xuM>%+xuj*Og74>8I&HXqf%G}-MVmDquhEmg^6;!Fj0LkOqA<| zi6m9TbwI4hHPuxL$s#9v^#3Knq7N{JoGuY9r%PkA+4=4J5{$_~V4nl*636HU-~#5u794c;0eTRcJI6$ESt!8e3Z6Y-ggCF1B;#I^+Z>MhJez=`Nk z6e9`|Y^^l-wu&h_(74Ds@dORNpMny^6c-<@scgYlRIDZ%3w0nux6~ zKAfQOlyjm98qYZ=mY`wZ2Drt3MkD<-NZKt zQ4=v80ozfUpfTUYvnlSpQAD^47OSv@JC`}wu|AGFn>(6{U?g`eR>0$%yA~!f!pxC8 zhSxch*lT9-7*xr_hgFc8d;SbecTf})ZpEDv|9HhCx#D(i6~uZoM-ZR5*i^M6SuKyZ zbTzZXZ_fx;+uYSfaGP){UQkNIoyUd{Zulae#t;PTNWzU|=(^CD;o=F7{V5;>aeoX7_i%)PqVR!Dq5W?-F^SMnoS+(c09XxEH zj+I)&`G;Erha>M#C?_@pN@KM7O9+lef(K3v8^k2rV;Du~DBQbf;c4e+1ok<3EJ6md zcR4CS(;a_WH-YYE7v-Bk zm!k{?eG}+zby2nT}|=L-vD9El$UY<@e~7RLn)0n5pV<%8d&Q}Qv++b z?|_-uq=ykOhMxeqg)sfe3Z~Dh!{6Va%YD{+k#s)-wk|zNB}#k=l%AZPuC4S@ ztl_2VwJ?f5(&5sOo{JT-S)|+SRK+a9AA`^Zzwj zuIm+P_{eo8UiWi+7xs?+Njyq)kn zQ!9GLl#8~R{p`&AE=YLDoL5cW=&n$HG4zf8JTt#DQtq^rP0%#zIy;i%rHocbO7hQX z-|4JQ?K^dB-|2)-=bhcYW5=RM$s^UZjB@kZwCMzep%D}@>eMN+xO7_NP!P{E4Wpya zKC8oNXSR)G_39GI>OUefGB0v`{&7TpUStCVj5d`HkJQeKOzYJuQbqxzuOVPmXLjV$ zJkv1BqlQtP{K&(|xhB-BZHu<8TepU85^g<0A?m?&HdUA|fs|dGa*zqiTy6S65TEG* z8KIQgOj6Y*UGYcaHfhR2UJl9CKX%&1mvyNz8{Q3!z=$C3 z)zy-mu#slbCuNX+jHXd?cwT)HHq-QQxV`@s`K9XmJk=F+re1#ORpZCynG8>=>B$mQ zd`b%UREzZ@K!=f0vdX+T5ZL)dH2mLMR>^vlJi5~uv-Wn0ihr0$_YUX1amtzp( z2tSms6Y|ttZ~Fa$zxC*Ve0T*Sx$H#*zsgfrhItsczJUn74KPjDi2n!PFFx&TM5Nbu z0QFsljc0xA179ESIei(J!A?A*Je;o4#2Wc};@ye!a#_MHzK+Y`rmuH+*C1Ha(5;v8 ze!cwO=gY8$@>W5RM?;HGD}kS0U*(ypenC@{_5B>SFT*M}qQ2fVwD`1J;iuOZ?+3jd z#IawnNy+-w!uDlg1_w~zVn0aI()fx_dVRxDANLdMI9KncW6Yu>IhH z&oqWDqR+SdsKe_TJ&AlMJ{hnj>*&Ml8oi2C*6Wu7g5XbGn z?n`b5p4%tKJj`GQ>U)QV7QZest-FGL?SGuE(Q=Ga?Be9&>q|z+NRR(l=o&StwgTTP zF7kgu*NEpQ_P1NuKfs&OD?Rpchb{(stXe)Z;%eBXryaEwJWaI zGU5{qY8f4i9r9n%GCCgRsr7J@c&gY}EE3NXM~Rnv&DJh?P7&^kGM&ETzo-% zS==rDMf^zoRQyKFz;?6!EkwTVM}LfXo48KAkHot`zZM@Pao|0!^k?Ps#Yxuln*2Y@ zH;n`2-zT5H39$S(@*_Ct=*LNv&y{bQ2Jl?al;QUA3{ zzd`;S`M1iyP5v4Z>t82sR{Z0lX&0g0e^B}##W$4xuKW+huN9A913ym+$W`-%g^K}z>?`Y%-c<%*vu-l+IFqRrh$`*a3{A0p9zTa|8F zM(}sYe^u#w50oz;~2x+C|9! zx%|H=e+2im%301DXUe}>wCgD1`Q3y0 zZWC9DYsK}VT~Cp3v-~aM??k)4BApWeSRdbnCGGkOzAJy9XxCfBe=VO{tjy0>?nwSz zPx2jqvXR(QY$F~gdJUj%^7+J@oG#83ZxL@57mK%v z3GptGj}F)_K0Y9SBieNxzFpVB=M=wF^jbiCn#yu}#gD~L#jixWz9U~m*S}1WuOqQM zUqK*`6#e!7X!*yBcHKw5ljNT&_7Tq(2a3bQ5#q(-rJ`vXqP{8euNQ9=Zx+3_VY&RJ z;wo{i=rw@um;W2_QSmA9Iq`Mz&tlE{gaeBIQv913LYvuNwM2j4aD;rjZ-CuKzQ2Ds zL4Iekr}z`GQ0y-r_I?6s7b(5weZ{qkH*G}NKb3!rST6eejFs}eR^r|A?-d^q?S2FH z4`~J2eFyUWN##BkKNY_eD@D^%gdO4a7|a%PM1LRBLjKX>@nTo;B+)b#QBNQFrmYD7 z9QmA{!1as}$BN^{38LMnARp%>G5=3RyHA1dHG^(fyw?m`Cx5;8fN0u_C}-M>;5NlS zFK!n(fr0CLL;Q>QzW9lFK>Q)?AWoZNeVn{N9xvvL-Nl|_Z?Ql;TO2436Gw<+#qr`q z@oKR|oFV>HyhY?ZF1Bl>c$et4gzlH`H5`8{|8emt@j3C2;>+T0@hy=P#kjuD#c##$ z#0>nX#`G*PM{Fpz5L=7XdT0I)Vt28p*jp?R&k+ZS!^KhJb>a=;Y;lhGGm)=oa=pvN z3bCe^&=$o%CjMT0R(wg^C3;PvJ@UP#&`0vUrqCDizZJg|IoXcw@|r>|<+l-!6HgF( zia!xKKab^$#S!9#VomL!X^JlqOU0jx3&e8qcF}7H)zl7pQ0c!BpAff+&x_l|*Tmi8 zU&QytAJPu0Rm*K}U9pkaRBR_6D|QsSil>Tw#6jXv(Q5>am4B5uMZ8|TQM^fSz9GIT*3=66tKz>A1AI5+`lDhUvA)%)l2+ zt}jdcA#I;im9LLDNE|9&Bwiw3BVI3Z7Ax1cR9q=0#Jk0N#RtXTh);;y#OKBB;%nk= z@h{^0;wRz(@f-1PVhrEG*}ht0eX)_)T+9=X6HgGki9N*A#J=JH(Q62uFaHAZ67dT0 zYVjIzrZ`*VJYcqWnOIX>=pM!2Cvv7R^FJXzEj};q6usuqoAURHoLkKDUy3!ghhlZr zeOA}1;{ z{SuKgiRoW2a%M991tMoA(@%(;i%fr$$SKM6pBA@^J4Mb*X8QXgCnD3Y6geN6er?ff z6dfVoYZM(X-)j{8M84N3Dw6LtiY}Iar8r6CoMoGPjckeshfHV~VMEk({>W_lNqGnVO}A#&m}{o&#mah%B6 z%S^vcZqroT#DFK!SyX_@K26FF&_{w|SImFa&hazZlwLn0?6)2}CT3Nrnp zMNUDc-%~6Q`-%7(@c*b*QlWmY;*-KK#-RVbvt#Fzx^zuR73KY)R?$h_PVDp}wTf;! z3M<3QmE8;}t)jIXL(mJV3w@OhYdWlGvSd&}-+~o=_Ec^z&nOH&-!i+&$_M-O{(RQ# zu7!;Xo2+iKBwW}W8alz5q0{o0mj-vmdlWQU(qc!`!YFi%pe3_+9m0c^;l1rD!=F4@ z83m(Y42*pe>PaOaDCI;y-r1;P&Hkr?@cyU5O;$EI5Q#KilCh%;RE+W}!%ah{KwT*B ztU{+@v^k!&KQlOf$0N=A7c6R-ff{b@v*35ZF`;8(U6%DZ_IGC<2xW#lEJaKvte|6X z;I!Gt^_`d5`@ku)gVr|{Hu!i}5bC_PPZ;F-!w2KxFL#b9d@sl=II5trX&ZGd3>S9C z+S?%5+MTvh)M*ZPXmvM$K8{SI|Ows)n}F@f96b4cyni z*3N<<1;2`Kubfccd})hi!GXE68m-<_xuvY}%B-bd1?LoQEXX<-&kCK=qT-0#wpU(O z1|6jGrb`+w&0UsX*kA=zZ^|02yk>4^s0ckgcS~h#a?n0Fuys}w=*k3bw|^W)h_;QD z=PwT}TU@xZaL>olc^jeVbH?0Y*;7>u<{=e+6dF2t<$FF3&kL=}p8I0e&4>@rW8N35 z=G^yU)h%r|6b7qYe01Iem0`3ZTE_fOSItT0eY)zF`{JuMR>rnIV>LukLwH`W`dMEe z$~;qbQ`@Jj=C)(RSW0-ajvZ$tqT1F3Om7zRrAn>Ic=$P6Gm9EY&`Np{{Za8yi&*FFAII*?*c)Hn z>f5>BwEA|zp^cl6x`BF2Xu*BmD`OM7S4L+b_k!oKrRa_O(3<<6sagO#3_Aw940h~3 z)chEFX(P*_N0NEBn(gvFXLjs9=qGJNKtIfF`)t*%+*+(FJi*oF*D*J_j$>NImvf!r zj>v&M7P~LMklU7VFqRQI7z?dC7>QQAareP+7L!QZPuxm_-jogHLy6Ezez1R1jO$;(=gp*4(XC zv)YDN58St_N9fdk`}+2y4pbc55x%W`W%!gAaUSZusrAOkKRWPp>Z&!VD0{zg#c>~U zT|C~<|8@lCufFGl{1upZhxnZz9uI}J)`dsRZB=&O+|gyX&rOuQKKE@?R*Q#uzBssZ z>-)@s>2N)(YeVgR|L=Lvd^nN6huV2M8oC+RiVz<#%t1sCIO$6`o@wu1L^Dt1B_$MV zhSYE<&L8?CM=|QCBF2O>viOsAICB)^q8TqCGSZB8kI77rX7+~@vFByy%w|kHqXh8U zP|OtReg;3gqM}Hj@ih53J#x-+Z!h#iQ?7bo391hWA%^u~2kks20|f zc{IErvjH-eWUziO?#mk3aWhZ=}E4d`dLenOqWt66Q`uRdps`AB5JJ%O4vk`?S`!tqwGw zob@T-kdFbccE@9g~x@MWV; zNta~$Q_fGO^UFw`>skI6R(=4s5I)kKUk;xeZEu6*jAp~`39kgQJF*eZew#V!@tC+7 zEp@rpr{!|?cb01na`C@OWLsVLTCNs3C}s6IKdAQxa`E|*%k@jk)hU_F`9ZxVXhKyo z*ZY>MFLJrIIe!@Zp#I(X;DDukRBos^T!PO*;p_2P6zUW--~l|?CB;fG^|o_6BqJec z7#fcHqi@v?g_z!mUEGMHy%GB$XdD`k~D(L8=UfDc3+Ru?BFg%e4a$T^HI zPBc`zHsx-pF_U>LG-mh;Obpp>J_+zR`$Q&~8WaY!eA?T#p`4Exlo4N+Xevbf;cJ>qG=35PWFl z5@_A#5(w5dYqRTmPL;tTA&aaT)4EbJvv8 z;LB7d&q3n}1e7fxn_&Hz4N9~@FjXEJ?OZ%p&u!$YNWSc3mC`sD0dt9o;bx8?mLo8G zs;zFnATB3uYk1zUh2wBC+KY7KLfeEP1UCcG{n8rUkBxSX8=2NPYl~~d$h1ai6;8Qe z13c&+5FeOXgxjy6uC1YEfX9AOLxgP;D?AMgW+J+N!Hl`wC2|5dT zfeHo@e18H81n~q7zC?j|q5=W3LF-Cm)H7(4puf%~6AznNL~KJq4J8R0&pBs`Y1F&| z2W=uaWe}OBC1}8+bFC>BQIE)q(_4>&WR^zR3e}_cjYbwj6dQv1gvgm zg2pEnKZy9&#m`6_f)Ut2D=#79n7r#Bc;i!^}+37~`B7 z2^yCb?WsOi{Mh+N?cqIwyRZ!9g=Gu^?u0nF+zDqWaS?)vO3}E) zIne}-E1VNc(3s|&c!Gwz6DlTnq^I3pag{tL;7*A5*lQ4Y4&ZS<2U~^{4#ADaiL%6` zhPd^J=jG%DGlvn}osr<0>2|8W37vqI5bi`jEbRiE!?SSMnlXroBH*kYPM{gKq|SE5 zsk0rVt5RpXsnN8v-PD+!?XE>xJFU`in>3iX6CrJ)KR5VjtdU#EvBLgHKkNCG<0`$S zGzOU+Hi2hTTzrWs2xu)dPhhy!3?ddFxH8b~p;L~4Gdpny0-9Eupz#YApSp<{!hOv< z*bJ!4pfF9|OyGu=;CCo1OvBw^3?}%Mn94zDB29O{G2~pB#Y#b4G>0Le1Be-^l+>si z!coN`gDoT`BiI(wa3g0>>Pk0cHezo=KyG3_0&=IchIl7-ldWYni!!ZP|<#ZbiUOBluP>hB?8b0i`#T(r|ZWIP=hO$HGva z1PW}-4*#J6d2Hjf*u6cQg#)ZO=9YT#yNOYXe;zZXj=Du(FS4()b7gnFzi; zh>LzGc@u+72keyH!?t4x!LtkEHk)#3*e>WmGgG>R;K5W!JkEAySeds1#?7upLb_wbFV2HoxLY5i+ri-=k=8H!>l!yGe@Bgs(Ch$>JcmMyrb0?D_ z2}{BjAiyAqYzZVFB1U8#b_oFyfyx>d%TCaUm;^+PRxJuD2spT-(iRo13u;vAiWV%j zR>e{uS5OOTH5ixQ=X37o%#10mZJ++1|L^&~{`ZwL@AEy&_ndp~y=U&+mHj1f(Xancy+*{^blC2oyZTO;pI4MtRXGNl&3AUZ2d5*55aDknJU$a`5AgOg( z$y$8%0!3`+xJ$4n*cW-q9%8)AcsV=CODM@pd16G)w%rIgWg+X4q9;82fsBx$R;#9* zt7RSxg}xAJ{xLSDT+$!Dv#pP}<327nJ~%_eUx=hX#LM4FxGPU`w<6(=S3S*QPXX$4 zr~5M8`HZhRcl;`$o;M4gcuXSu;NQtEM>dWc>yS0dOj7&@at_9oXHZF{c>FRc4gaIH zZksu9g%!a9H(EBJtX4?8w7TRKEnvj5V8@Hef5KF7y4kIYE;+ufp0X8LMTEQkHC?djbInH z#X4+@>%g`$5LzN|U7`rdKKKR{eb^-pW7GhFQ(+T?Yy=K{@{&A`2hHBn4g1qSsr)jt z@07($7tL8ZeL)051|`cPoyz+3?mT7A!sU_DMT_Pyi{ORJNXdd3C9`Ig%$m|GuTP|) zM}Ds*J*OZ&cj2OiCAlTjXUv;2Z{f`O%V(8LSulO(+<6O2od2v_2l5*J-*CSjyvhLO zg_(;Moh-Ve<`InSuSOr2FSd;0SErBh2UTwJm&Z!Y(}Wu>#A#eg_A z2Wu~wUOE?+8SE6ZZ+bU)u9sElEzC2Y5icv^Ei7a_JhCHO=eNJ>Sb3fwcZPL%Or2WoT@6)N44~Taf29&TE~2rnem3h!p!ajPttY zdq2tZI!4;%bn~X>d5~#grMv=fER2a>{Ya~x;T1#Ybsafp&d@n?=HzxCddZyA+n%0# zgI8Aihtu1&>C&NlcdkTMq^tkeE zqz>}~Et6zHogZWzNBbo{kmHAp8$UHVVECxBiiiAvTl~dH1T9>?plA^`%rfj&D@r(# za2krvn_pV8bl$=_(d7$gmd;zWa9Q_%Fcl>vVdA4WYRH*Gu~!Z$E*?`XwV`<4xZ!6G zJ!{l}V#iAH#BcS<%-~y-p}x#f(A73?}y|qyKq72^chaxveKnK=h|3lNm;3rH*0$7bSH1d zvSp4Dt6^f^-`hX@BC|?nET1!V-on|7P}{_(&zP~aG zHf27)hUF1`bn<2{TCku5^GqH#f8O-c(xvleEHC|`m)STCC`lTRAB$2i0;d`{oAwv~ znJgKAf5wOR{Sjw5o(OTNTaI~LPD0?7$sa4%17+&An|u~zPoTP?9PSCnmyE7BlY-S8 zfn^xj9#3>_9}so+U_V%5oh0RrK|I-C4*YFJXX%e)VEvgJt+4HKI&RgSl+=KYECZwC(!xrZ4Mof8cUL1V04r&I6ly47)^IZfE=B>)HGUuHSqSvU-G^-^``gvU*K9(vS*$;6TPCOfC-iLit1q#zcZubHLeHixn&Wu*3r9S$ z{4;tsC!jdTgmVk^Y)(s5H-3lJvH#Jpl4MPrzx~;A+%I2qrIWfg6VZu(N7sh)A9V_P zihacaVpJR_P7zViR z!4qYlEcPYw#be&Pho3RD!AZ)Wru=zIUoKWE|1#zOTNT)56k{iHm@3Szq0Sa^Qsg3d6tOX)Z}xfW4R2Ga}aIL($O5Xk&hVwHH6xK6xLV!Ne`?sRi4S7TM+v5A;ArTLf8^2~A;<)MfH4hQPHacBk6MI~X zZN-ja7cpNn^A_qA%I+@?6-SB_#VMkhzfjNWgp?}1Of))Q$iGxJZ!mFO_&*fLt>Wz> zpXy}#uS7ogK>Jbg8Sy!Buee_{^Bv0nNj9&zvp%o7lYbSDi2=@YNas~^vZ2^m%n>7E zXE9ea^Cjx>N$u5Z$LuZH>dez}J@?NpIh`e|p0EyUI$@2)VP z_c=+c6LPX_-WX*1KyjovMw}>45od~X#Ph`!;%f0S@oMo}@h0(Rk^h^N?cXcz6dx9! z5{(`i;{2V>@_WTUh;NGjC4M0CfpM0v71Kk$-B8RHb432DQkL%~o-Cd!4iT*mNU?0I z12R?iOmUI8Ok62eidTqNiyOr)BL7t>`*V-@fcR_i8Sy!BuV{5Y4$6L4G`eN*cT_gs z8Z-V=#7wcNSXb|Z58Sgq{lqiHVv+xtl=)M|x#E1Wu71a*O20z9Ufd|&D&8snN_;?k zQhY|-BkmR75)XvL6(GOizO^cyK)riXVuF#m~jB#P7rauD`Kfy4X-` zCbksYi6@GAVu5(7$m@CZH&`4d7K!7<$>LOzZ=|qZsd$lCAzEFHt7Km#e^aCPaePMr&irie3G?CXq+5RGNnYcnM7cUooCSE7rAl@S0AzB@d9kT1{aXhQ^7scO;e-saj?}~@T zzlb&BH=>6hfLxDMv4NN+wh&v3eD#Rs3&c~!)5Rg;aIsjNAkGx$hzrG~V!60lyh6NM zyg|H4yi2@SykC4sd{TTy z0UKx`_u5Zj3-in(IG*hefB`D!2i6^RqYDPoB@Ph28e9g&M=uM+ucApNZuH;Y@v zZQ^!ur}(f~E$$Zgh4T63z2#D91;jS-wy-|IrL~6SjwaGh6LK zZ{+0sNMecWjUdt274bjwd-UktyLTj#-}{t;KBoAzw2C34qUM!r_~PO^oydL!3TZ{*afXserZHm0r1A3V~ijg)Rpf!fHotI{?N8q)u>1FHr>Z3KD)m1#zA zd#z+uYP*FW;MAcg*SEq_Xibchq=%21c#Nr#EUp-mt&zXwc|;e6lY!)&>eA zmpj43&jr$A&5wAg;Tuy?ySf$XwV=+&B?GB4GB!FQ`u$hmeV?|;JL>dz`%FEw!A(2d z-^tz^jCPGSWLuFFD%TxzBQx+Bh}?=#FY->MdxnR$g3vPgWM9hRRVmKlr>FoDPTQMu zIP7}SrpMf_?P~&EuVyQUhdEOZZFGG#k@8h3o%?@w(JJSJCQ=i*av;=1MnO$vlvNXX z%4u=L3wV2rF=?=OEn_*G(+)?|P8obVv_$%Bt$$;~_0ExRD^HE4#tzh!Rfact*QVj; z&G$~q+6Eiy-T3fe_q3O5dQ_&b3$2IFMl@wpYOH5XIAc`R)m5)lQ6nXP)tDnry*4*F zH@+BsDLOoQZL~Q0NR3nZNKK&nk(%J*Mz!J0?5gbA;A7dfDfcv~&B)BI4RxAQ^+-)9 z(zG@;Gp9D?v7Fk_JzJ`BYMrWPwW*Ias!hG8d2R6WX0?ILMzw**vTB3(WYwlDbz*N< zxo1%2glp&A_|m?VP0*UC%-DQwbkN{%>^A-^>ppjH`b~i@{XhG!%APgB`8{hwSFyjh zwhr|i6}|ey%J9Bu=%8~0G(L{B{rbw9wqO73%YvHF%7U8U6qMV8^4n2w7y6LtZfIT` z#=HE@YeQ?%_ZIHP=Cv6^p)E72S#3(TvoWVOh(4z{O>5IGpw3DCwg<4@f!t=b!E2k; zrq$ba)C)DKO)q7?nn%5(A?#71K=tcX{dh5YOSCW=DC|`eID;A;L#r;Wdb-N(ms9Iy zHpUn<##lA34Q!+q$H)7;4JkK;HocJPexB;Oi-Q}Xv(akIp+haxKTm}&$4AX8Yup`a zpQom!ex90ISrgd$+~RP4xFFcWJuP@`%5~n_(7K8*PWV;*%?+`Q`&0%GUmgq}elA>p zJ@$agoXt&+c=ZPEO+#LrLvZ^v`13ll&^gd7Z(ret)UK&EZj8}0S^}j#Us$`s+w)w>O!#Dr*gGZumHa}|i zuJjMaM%&ypGy3KSUNnQc7ll96y}0!K?;{63csPjp$xItThzej%`3(%-EFESN6CZ&& zhzDBr!l&nkx*3GO=2hzfobpZ_&6Ge2_BJ53jA`fbTI?yanGsB>$CTdu=u>7=QfI^P z!YP-~3a1VStoB7PwU`B|$KZADjEulVEOhcfMn6NF-hj!B_F;j63z!#7<(U!3|5;ww}6cF{$tKSM#N zVekeW)G+wH66Qtl;0hzH5atbCC}Z5obY651u5s@}yk3ys2=#*eKA`XhM)V%nWushp zwV8`sfk-;POWb=QG9Z179&qDsclnjb+hOTlnEwlt{~T@JLvVj-^4WTN7W02)@@LWJ zce=a7|?O~CqkZ&m)vVgwrXTc z`gR^{rxC~H(|E~!rsNRhWE!8o?KJ9vQrXz|{FYxer6$Jx`8K8VoQ7=m6@+NKbh^iW zQb5n|r*Bh0&&k@15AM??2#q13aUnj(23Fvc5*kf-x081=kQKVnNN6A%8BSC8CuqY+ zXfVGScdlmKL7TBHr@71f=I$$qx^6R~+132u;ee#$N@yhOW_SrbjsHs}G$_VFsfjwL)4CwH`(f>Cz`HdU74KlJdU2( zHzuQSd|?r!nK4s-JdY9O2TA3_OJY$z{ts_FA2VZO8HFPR{xirG2+$xPx}iAUQ`=U- z$S4F1HNk@j#f!){O!6dp{@72>Ao;wAsme$Yoqco^xSYj1fLk zfb{+VUuSonvx%h$aK9qPi2n}p(v{{N;yeAE@)#q#5YQIEuYFWb8n8yYFc|*3lEuVs zGe}DlZwp_CUTrtMokZ+3(IVne1iUdBh%r*_8^IVO&-z9v#>i{F5soo(5CQKy5+9pr z5%GQf5#{*skq`f6R_J=r;FrG=f-xGGB@#k08vam@OAI9xAvlz2 zW(dY{MEL+$2>%wm%sC;(cuPNvC@|3?f{$n51>v$7BisTomc|%~BA|l=H-|~T9}$0) zi})NCpM@|I7>w}L%ZP6<^1g3`VvKz18{rrupCQ0)CAI_~pT%BE@SRp{?D7~R+f8~g z@vxu1GR6&AZPLdQ+?aTAI1uBmf5fC05#0GP3Dh|T(#+vdL^MFassv(;H1dsLjFBwg z2*nuTS1gK!V~lXZNqYCt9u@U4xa-|v9foy`*<%Aq6-u&42$IT`#N%Wd0+KFP63xX3 zsZOb5JY5FkN`xfmG_UcKAeLrI(d4e1iZ^Oag56`2s@eS(Nw!)ws&J=8Qb3+)?(vg6 zCDA;Hkc!vUjdSkAM-b{c%kA3H{K8MNYX{3LoIuzed~w)bVI73#G%@cnkmF*8Swaf(c7WN2EK-^JSnsMZs zh2M(Yns`IEKi}48oEr(VE-?eayvxo=nV(LSBbX|9!JKh!Gt4{N0e{8E5?no`60ab5 z&IJ`QMh+q%op=|4Z{foaqa0_vsLqK3M9zhLKc7*5-WbbygJ+z~K^;bWAz=C=I3&v9 ziuybKSb}eXVqPNry&Nxsvk@+dZ=msXa0G`ZzD9ObFv6cjn1^bX-0u?vaL|>l2pA}WQ=1VG1Dhcr zne$kGKT2?l!n@bRN(2@ruR{nS&R6^y=LBZ#f}9xR{$yq}D9n#DX9D3*Sm(P&Y{;Lb zrV!f@Fn19<%o;3q;}a8Gw5x{h*%iZ!>vo;&-UbhL3c>DQ5uZF@lqY?$F1y%#vCc+y z>nFs*mL` znqP{}IRs^MP@od)&mo};@OutUGn*?IS&D#hB-Yq;My@pJ6N&2(8bcJLe~11Zmz&Qvs0_s`t_8QdamGl{ z^nG%o@00CU3D*uoYnHlwf7En%5}&)|GnM!vI|O{@M-!_tDX|)pxEg-X&mrzaz)BF$ zn&>%1*z{&nqBoQNnch5a+AZctvTaNwi7phg3;p~S2yRhK2gEN;^lZXE6vh*yOc%~c zbm5%ib%A>r-=D`SXozrV`4b8zSu?Tlhae6Hg2RXXhR_^yyP0FYLwlHGphwo;jnQZV zmr4l4XhaeTUW`U31aqdrh~L*Dq7nfuk0M`1!0tr6j^H^LRm2$a&z>jq%$KXjj*>iF zu|M2ikvMKAbLZ9Bvt2)Psc9%J5dwm$ww&3NBOM@ALU6tR;U~1@)CAOY&AZGZx$XioO)Am z#&=4`7^B}HB$dcOg;AywFRhw|hZ85a6z3vVvdP);l03^XO9V-MP35zbljx796iJnN zN$Cw!a-1#sJWS62DL5fUNk&;J=?f_bMbQ^5@hxi(EtA9#6lX^{_i;V!V$(Pcu-A5B znMO*>NlIrv4_UixMxz0zD>tcIizhvB^NpJo!9DK#)&F5FiT}4HDo*)tDO5ZFg^GrS z-jY1(Ml6YV4I|!?LZ%pniqX)C@Ggv;Jh@-Le$Z?1nml^JP_IGWEg9AJxR~&h8(C;6d0bB=baSs&WU(EBDs{K=rNJKTmb=yjBp<0Cq~cgKC)Z)6S{Uk zr+c?SURhy}UY-9kvRym$9-0*0y$dNy;oSt0iT52SUR(%)iXPp%LwMpu@4AXY?^ApM zk$-hwgYLxI@=kShCn6A_DDdiy@WxH_3L@T_dEP0Inz$8G69XVj5yAQ#qtL{g<%J1( ziOa3L#Br5HPH~PWJMrHYoah6+iT_8GCXRa~{T-zO?veiuWs0d&sh9EpOHbe>`*|}< zbEnUrH+>oOAtJf6XGXB#oRX{_@xN1Q!fEB7Bbc8v9Kv4wNLu_; z8OLddG@eh`GmyIFn8)QLgfPO7mFs~rtYc3|=`ZSouxna#riupsSct}BUCC#YQRPp*C|K&c>X^w zyV!E`k&xUjUsA2cjWV{&blYwP;OTTuRhH`zZ z0kVHw_9G;($FKp3ac+VP(?PU75dzyx z_V;in#~F<@yI6nLwoFd{PiReG^Cm5JRQ#m>39Sk24rV<37CGXH<)6`-Xoun)lL)#_ zt%*|;)s5e19sBQSP4HyyA4yH%JQnA-b!DF5djkTsCVHb2|Blu~7u4sw@TZ8pvPyf9 zSR|e;@)9ib=ZOo&i^SF972=KJX7MiZe(`bfMe%py8{(hE55+IVZ^QuBoBauk4a6p5 zOR=43-aSWo^Gqse-Zcl$RsMM-p6FR9E+uiWtW^HxvagbTqil0!1%B?5ypTjf`& z{8kaWzwrmtkmsxP&$*rCd{3IoMPRP%e39Qp%r6uPBb5?>Yh ztN{CYK>V|KSp17<<_(nlT6U1f6KpeYfX!vM5>F62ig_Z>(OA#SAK>Y->uOf;JD26g zi?hVJ;$pE>Tq9PAYsK{`pe=nN(6ZZSEKNr6e&FxO)n|T!c zG0lpTG*5OFPZ3WO2a0@zll>Sijuj_~=ZbU0pNdPx^F==3Nk5l}SBlq&H;S9Y+r@3- zed2@S6XMh23*yV-e(`nj&*FRH$Knz3nE0(2L|@ros(q80BL3N!v8hhY^oV$p*i|eL zsp!vgr;7u`5h8W%nSZu8S)3)#6_<$1MLtE%dR5|$;wJGP@t5M`qSdCbS`_=0{%7$$ z@e8p=OvR6Jwr8~{>S|DQRepD|pEyt)E1o6J66cD`#S6tM@hXu|iL?E?#9xZ{i;sy< ziqDIC#NUg56yFiw7wc+F)F}NM(P~Z9OZEHFNNghVsde`6Br#7c5PwXA;#`%RAfpvlj23CzasuoJRrU+ekgt}ekFb<25>Qm z<5FMD6tl$~@g%XUSRh*MiqmBe5c%{!{aWpcpU9pro+mC8FA^)n%fu_i8^oK$Tf{rW z`@{#uXT;~kz2bh6ZzHgOAB&%hUy0v~9?oT1E=_D8HWgcl5wU~VP3$2Siv7h=Vv%^Z zI9Z$_&K4Jm%fuC8xp=8~g?OEKgLt!et9ZBg3z4s5a6PNV=fs!9{o?E5pT+mYPsPu~ zTJd`^gzJ1}9L2_BbCK_VFu#jvwJv(g=KCPbA0ZZt6U3j0)5W>sd~un0fmklC7OxPm z7VBzWY*qU0;=Q8PzTo>Q?B6ruOX6?E*Tgr(Ka1~)AB#uCuf$q0h~I4V9~K*mjl~=> zBAz666$gvM#Id5)zL+B0YG2He{Zo_ z;>+TG@pbV};(v*U#81V)ipNC0AH@FG7n_P!`ywK{gVTE$oH4n-?bv&U!r}RXtgkYCEIFYJSzJs@i*ct;;Z7H#QzeHh+l{< ze(STn6wzv7WXWzJwiZtmJBvNUUgGKE0CAW&N*pgv6sLdF;mPIbHol}C$Wdv zOFT_HLmVoO6vv5Yi|2|n#Ph_3BHwRge=ig3YG7FHi(8d{xA+UuYF|7e`zi4^;vR9Y z_`3L($oJ{k{ukmmB5!suJwt3HHWyoo?ZuPC?qW}|uh>tFiX%k6zsGiFi06q5#q-4# z;%f0S@fz_uk?;S}-<{$w#rwra#V5pP#TUg_#n;65#X}-r8KnPj#V{_6nQ;>N;vns| zB3~S&T_EyxLE6Jbz8FY*ipUoOX)hA_Dj@C4M7|10d!u-}xJ|@q_`js7QTKXYMAxx8 zh&@E!=VZHeukQ_0`Y4;P>pQ&T5x^K(|IlPOrB5WW{Fo*~LH@}-dz<1vuF0@C4~=1p zWFPV9snfz~=Hz~KWXx?lHV%X$!@6KJ<<&vaCU{?beq}2tFL*~G1>G-i%lXcx@X3R- z*Jba`j&_bVj<&68SUI(-T}@zR44=W3f5K;IrQ65D`~9~Z4ZEN2%ieUy;b&3;ho1?w z+SK@n=e1auvKQ}|w>q&V(84|K*uGXH<9qz~TM z2D%D?D+gZnBqVD)hI(!u*y+jW5jPabU5}IyVosiOr1R=_gRV&Jf8@l~PP;YHtd9mb zZvNc^JuraU?8_JXrbRz-x()6$7|IMO_4Wp!=zur(TT%Uiy>Jc>adw4$RfZ<3Q@Zv4 zEOWJULZ(z1Zlx+i4pbR(=<7?A-t9m~B1x5@)us)D!$-fTW<>C1s4%pJCPUe(>@5ds z9$wpR(0&FMs6BdHJI>gy4{uKMD-V+p;rn_jGaYG&JL+J^K^FVsHeh1b?w_rjsHG;dR2!;7{1ywKXzb&nkjY<=vQ z)8m;#X(ReX3!*R7?v8kDr+vK*;hSERmDc{nL-p#VYzW@;LhU}}r`{ae@IvkWP(Dfq z+{ccE);@MD*yyQ4^@cZ!qJ_}2wfnsm(OpN~4D{4ZIT}t$KN?QIdtd#H2WsZ-IDj?y z+2Gb2TWr3Ux)0r)BbzF7wghtff7WN!Y0zyrttPbRw3_hd@cJuT*E{%fO=RnVn(VD@ zzg}~!?blV`K;_}D2R?G{g~~(DTUF30$atV8T=_!ns(aDvdk=gRxc8~rs}K($9z=W% z;=y|#s7c%La!oeccJAF%TNy9=8x!}-R@YXUvIlA+P({eDeyaA;IlF5s=iCdqQNP7N z&To?1*=^!}-S8H+8tC+V?J91adoyv2guFYBdTG>%*!=qbXm%9+X&*Qh>JU4AQ}uF9 zBhwdXD~t(UAKbE|Ca`u#O|bGeroaAr?5@4SUk~(~W4XJw3jO(6dum9$xeu+hhdxEM zyE(AoKuyNl;7wx=y;V5s(BMJU=?7|>R5w`H|IqLuucjYtJn+z{kz)>h-18{XCsso> zVr}ycjjkVXXy}Nq8$)d(Kl9qg*EL-i?$rSMXaBV+pEnHD`@Er>_IX2(`%=bHsDsor z%1KAM+vk}>fkC5cG74X=8MgK1nxY-loS0bMd~L-SxBas1#%`N)x4h)!3~oKR+xpz= zp*^t{Y9-;}dogdIv{O0e(4=~4M_dQT!Pel~F^8^5e`7GWiocC_VAOY_TzG9@zv@UhZe=29!8TQFuw;hDfZM}-rg;w4#l&zmtsVM&L{gq8^Rll1_w9i z+~-u)tE#SD)!x}M=FqEs+|!308Z?Z06k)8BbA8vEz-ce0kk-OT1~PjB?qNDqWl zcrU}dnaO8%Mv7ImSb&t^$wOF|iqydYd=|!|*mZE=Vn&~4bo6RQBlrlOxgMW^VCrBX zC5V1bLxDgzX!NFo5Tr2Hc;trgG>ensD^Y~zAU(xbq6iH|jg%|g=a8KW4;T_YP!UKC zxV(|%U5}J{ix%fIWfu|cw^RIvvy&QD+%%k>+;Gc)iwb_jt&$qf zNp84xfH!-bhAs!)J&SRNmuI=SHMmaGXf@K@3B0wHi?l`yXr9e}o=NitniH9O0Zsl_ z0{0x|ZlHJj8@SWip)#82 zp5xA-`6x}Eg}F0n@_J(Ci(J)NG#g=q63jHuHuCOln zBgwd+B4D;H+LA5;7f0|98d#HWdVC*Wg^SE8>_&Ni6@2>-w9U%<_956#GahBE{XT+Q z>GIY@bN&yHZ;{*l8AP&hqTBq}h|piQE!vXDRN!Kq0k>k!&k!m&WM=R$GwoA3&~M+j zsTk`7}8(1E!u)(_y#@rE?B)IUEJutU|kg8=rb;cGC~)V z5XrVhjf(~52yN8`Rrv%?%S`idXpl2G{AJ> zcYB|y`BA*4Z-?=~mfvmPZUwu^R#f~T-egiibI|*C9tt|G58@-)J*)d2^Gl6lDa-{} zK}uNrMfaPY{4`$Fx38pa*1@;8z;058ic9KLWQN~{UvLL(r}e`qne3kK+L-?OrQqyC z6nP@2v5y1ts*aUff3F@ zzT1QUf&Fc4u9UaaU6=XoIjOei)ZCtPt<%BXjJW$QqORMXXwUbz+VlGuNyin=NoeJG z$r?Jx5zbL|%5bbhYC|VIosn>!>ow?`ep<>&8N(Y#(y3TeF9kweOk#dobL6L|(_~(H z{iM7Mh~C5t)_2|Ejaj5YJ7;*~?)chh7?-$7KPiKXIsHR74$NQ?{Ig-xD0&dUF=xed zWM;{&%*F{58_5dpG)1cEx9_4^Yd60!+nAVsj_GLg6er&}&rZj(kC=U<=1r8Y5b0*0#N`>(k+1()HnK z5OjU`@JwRC9^~M~TY~w%d`}|Ve})Qg2j(EHKldbOBLCw9%ktgeq=hA*AV648#qn1K zS&lOV-sK~Bri#~OcU3UrSDa`onsg+`m-q2~$oFeWdS*O%;Sr0pAW5|$y!5-KBGe}* z#>XC3`jvwuA0xo))x_Hfp0lDn#>hcGo&NbGLA*YVFa11%>y7t+%VKr_*l2P`)X{KK zM{zX!3p=+BAEx|BQcXGdT!d5KKu%@(^rE#;>%QjNG1-$vB6>)U@kp47)e{D=W#fJ5;VI zXN0FIFpiWn(hR{4CF5GjnsTlrJ7D(-+Xrj^JKf+32UdEL=GWHy`W=IRp|QffyrC`$jOv2oE0Q zgkp?vCoshrX@h{toakcH8R5&{C=`q_GT1jlF-Ev2paxNH(iaC}j9lp(!5AaHe$(QR z(Qmrh&k4sE;f{mxu=5eNIj5mp&GEUUJjMtgFT+^42qTKM5&`L%#F@1jbx%40b`X=YfB7yabn1^|0jkVJ8)vivHuUoIus#b1i~>! zCYqHRHw~yX(PDg>h3m#McPM4CJ+1y{k) zTSooqW;~~x0_C7jjP^#rwjj8DSqC|cav18FRnE^rQeyWyi@O*19c&?@BLcQiMT`-D z7aE&5>c;b^>x+QWM1KU7{-O5NEYpke1e?YH5}Y+K`)#jaq*>66=5`}PMT7ec3KAm_ zAW{R9Y8(eRIsNt|`B zLqI!(KeM78t{>-7^zZd@M);^M8YQ-ybVz*JITVEw-`Oa{73Cwh*enFs)%aoLYm+{X z;AThq4qlZv3s;(7s{v=ZAy4}d58Bhe0AxmZ_Q%mcJV^4J3-Oi5@e!ae`3NQX2qgIk zCHW|~K3I>h4q!VFXQBy6(*@TDDD@Ph$vFy1E0vU7vD#D|PpD$(Z!4D9smL|w?=Sdt zltuGP1ROzxeA(QjPLv(T7hiyYuYj^>a;30A2>G(PNxoLp@x`^k@Z#@cyN>31=y6Vb zbQ)%h@pnrb)U@ZM$>|M{jtyTEA8;0~yC;|PZ|Iw)%k72ZL$Z!{$}KQ z@axLjn-RY!$>ugHHrvGiNzZMxJ;_dNBR}7cUSdGwdlFxb>1DoS#uEGr4>&6q+Zx}% zYZH?lKQD7&vKGeMmSX#?nZa-BaOX3=>fG_Ggis%SFtH0Q5@x;^IEHijDu3TWXk54&)C z@g_CDCmu%Nmqay!UFzo9bdJBhF~DtX7mnW!1RiI*5ULTLMR*?JMT9pH-a>dA;UL2M z2p=PShQKZc5i$~8HD_!0AdmhYMWDZ@5$gJ5{Vxz|5V)1>!n*7a>#{$r%l_1D{|9xG z+W$xEvLAl_-a2qAa^v!xlH0ruLN^4v{3E}w!tbXDTqo=2ggW(Erf&PJW5zd76w6tXE%mw4-Etr)zmj}?)StYZlFP~pJwe-TpCCiY8v0hd>3t~TrV;m_* zuwZ)WT)#Aa@|a`7d&_aXW`*8)5q@UmjrQtAy!46Qa(qT6cR&4fZ$+WkX!~T!n_b{F zj(7|5@ELx|tN$+2T8&ue)ql-vRywL%53e!)!^nk^`~vU%!rX3&+^z-sUug1wM@YYm}@V;?My#|q1J-v+2yt11|x6bc6a_*)%bGOX8WNyz^ zr*;1c67yTnYu&DUw~=$b3-fvz{j=tU^IA{tdPeK^<4^bYlt;XsZlwLGXPkOL*Wm@; z3*~vd*v=$oI5MOH&f;>nhq(i8S_q`JALV_Nba0j7ffF|JGUT`JEkW@ycRCX{m-a< z`Pykl^XrFVTBZZejQKz1Xe}NGi7kK3%)oI(nKsaBWyMpCqL$ehgZfSxG4V1=O&v9F#*}f3mM@)IGG*wXL3Q-MrcNDDJTxC$8z{gQoU^cG zR%9l|BdI5G#V~d$E&%p}RLFx3q&(P?-aWC8_`Adp3K*BDZ-l_W{N5<{Bl>lTDaYS? z%qp8v_<`$LiX3Cx`U2zk*Wb}0^Y3u}_q53De2|BuHg8tRjOBBt{_hkaqs9bj=(YuY;Poj z?E|7tC48NnRMF-QMP5>}Qv-in@ni}8aSW`#vk|v-5Ow&D%D$uo8=Y6D9N%&Ht}$!) zi!E0IGr8Rjr{R3DiQg{MZM$WN+dA~Hri0@|7|~+$N?|AaD=SKj3!a3C`}-NFj#uB92#g=;<38=o zXe)v2AD5RAlGmdV)}s;9xE@Uq?0RG(p44q;E&RQWG`rZg$fV(S_(APj$?5+I4Kl7{VzHy*r~FT7ka3(j9{%#f-uyEfWGzvVW5VwP zYLIo6CxU+a)Up5Ol<#lF$L!qygYQ{Md^(lzN6oQ5X!PIF9OHaPZ6s`N!@lAGF)EG| zdBua}r;77M9ve*OH7oKGajkg0c$av;$m56QpBH~89uz+kkBDE1--#a9oAn!ttwgIW zHdFSU;#(rs<5|yWc41q!q7AksaWL=^c;@$%&Fc-cdA))8e2AU)SlJU~Pm|53>6yPs zcB$-g*;do*YT4H*pVz49{}$Qz%HAQH57aRKN!c&R{)70Q__=7bZ%`g@L6~|?Nc5|X z?Dn#AWf#aUls!Q9NZCcQC&`{Go-bY{8todivq|<=5;m`iu>ZdncZ)x!?e&Su@wx>4 zd@I{%eBld-*KL^IoP_@z*+z>7Hm`p$-)Pam9zYx0dx&@ziS%{8Pkc!EkBZMI{YBZYh<_l_f1?$H{(T_(GZOY!vI96*q@6*c|3(`I`+G#` zokgPsgL0?PMt*;#4<%7=q&S{LyHk}vOZFn!rLrqz8x0uvyGH37m437AyJi1U_9L>N zAW`o*rN655KgfPZw$XS&xlfc{qx5fOhjFsa^>0X`oY8hc|Jy6Q6A8Pg>^`yw$sR_c z-dLqiQM%D`LB091m#W+aDz{qcm&?9h`FvcG?cJ^XU&?+&_LC&W`%mK6$~RgosKOQv5OKI@&R8A#Zz=MnM3&DLdx?C8i|J>GgT!KSg2-3>SZ+DVp;o#2=OYg!ruZqPS1|z4(@RQ2anVEY>}L`c~=CNigftK+F zViz%AJXx%(y*Ex z&lKl~i^Wp$VsVwow~g69zPv|n5@X_B;=SVi;zQ!&;#1;_;w$1G#5cuvMXT}m7ui#ES@S35r>OK;&`#Hmfw7(FBUHlt)|}^ z*;V3NalLqlc(=Gi+$laLJ}Evg?h$_{{y}_Od`CPi{zd#ogl$|Z+i0#Fb z#2#WV@pRE@_6?J5HT%wzeUA9AYV}>JdRK^6vv0j@3L?4qN9hHY&lmfMh2ltYj7Vt)mOoEiA}$xLCSR3o z3N*01)!@5d_Cw<1;#1;Yalc4G2iE_K_?;NQ{XM4F6RpOc)zph9osthMXEpS!X5JX3 z*VW3S`~%A`7peC^`)aYSHXhX8W6P45Ge&gyI7!catK&3a~cE)#FwzfC4MNjRMkQR-^wMBbG zBKX7Nf9Ch-(Ytr=NF@K1J|`EL^dHw2{o+J4f}ae%3=-O+KZmwx!)U#ADbe7or$w7a z>&5CBWzp~ZYz_wwhnxe1?M4zSu=}u&6UvI|>qDEv>soAb3sE;MZGHBp z`kPbNdF%H@Q#PMd6D~Xls-&Z%)YOcust4sp=uB46iMHHKMMx*II(kVo5QTHLvBX5+NLQJ(7$%I!4ulo2Jh)s+XQ*R9F%h+ zwM~j1KI(>3kA_o2@bt#M@Rsz=qX&mJ-a$3b&Lw-(HU_Z9Z&aRK6P$lCv^-BnOU~Lq zMg!O1(i*y&mFuFNqNxYn4Zpa52huLPzwOtTf722N4=1HG~_<>`lRSf(Lf>8UfVuU<5WIS6R3_=9jJ2qW!JhV zWY%UpmWeu+p~I~LpQi@WKTl16_5Lx3(z~XAQ2{;8LoKT_(>_m4 zbMOx-#y~xF;2~#5+7}h>z(eU?`k>T}-c18)f~UECQ?ETx(`YUJyY?4(zv9;N4zKaD zu?4-uyPbU5Qbf4;9@h7?)AaYePNVJ^|!6tqu01Lgpv?0ym`{ z4!bUtG3!-jRb|!&dcK+IeV*#2*SM$saR`+$U)|Tx=wXI#Ui`t>Xv>>sMnCu<5?vkT zKGbqE_o7Rp#nFrpyl4hBE(?FCak=Gv=SlN_LCi58boqRZ%ZE_-g)_}0CO!gxLfmV` z`M`5SeNfbM!#SLp_^O9@;%H|00+(JOwVW9bG2@ik%m}9J0|L_+?^9+{Qu+9d7fyMI zRycJqYFI_fVCpQ^?}?mX=g#;H+|1mQ2QqpCqXQ;0I+@Xd3lR0Jnk71QEmFO3@Orur z25)0-I5-{%y@8LE749a++cPd@OHQa#woDE3TQ)UVgU>Jv2EKBQ(w8?CZhdLVuS|lk zX&I0AWJ!MGr)99#F%x&fSJL=iE^dvx_&&)+JPsFr+;`y`Z7(MsQnA=BV^G)sw|S&H z5$9(aJn?Xg8X+eav5a*z$FdJ+(&XueTg+VEFwR(lh&ztC8))KO&vC~y_Z6ByrFm8} zn4i)#x|0)Va!c0d8KHX)O>PMM{I%va=vsraUQn>)fV~n#=63dWG9B}Ikovrt=$i}R zr6GhJr?3wVAna%&{0Bbu@1{dzZo+!i=f32dyfoZ^LXkhAL;ll}1{8`smtA=XR{ihk zergcri!_6{#pauRaPg}??=br2&uKP@n|on4pd#ipR=pkWKd=aLrx6+{CnVjAl$ zT1F9*c`4Yq^)F@jrn5tZG~3Xe!QJM0ninG7H{Yb$IiC9|&AhnDt0awh097II)Wto) zeF`1Sj3V9ynVEeNIf)S}Bn(9)%NB(Q7#{mUid?YzS_HSf%NO8`iv`vN|5br;v6U`t zQR9ODeE^NIDo>UMqHfa)q_`)U{geNMplKKS_3b~>&QI7Mvw9;Q7_7a48M*GI>;P}I ze~;Wu-h40zll+{fK zSo?Ma_f$88-OhBN9J!_g*D}Hm&|j7{KMT%Uo`VPA2?_OnHbV9aqaT+7sl(Xr=7Bwy|^j&ZyS$!v640L~MSL7lAV!jI#9?6J3xO~wy5dA9D0BPJ(d;m#uuB$d0hC7`}PVJZN^!5YrNzVQ<8^F zn%U!g+iBJVrTE~LzcNcrDIQ6_Ki}SL{0&1%-tzNHE;A*0koo?6+iAj^|5XTWFwyuW z?=U5wfDhlNZ||ee=49`t-$-;?VLQpZNC}zqO>Lud4 z?cdW-OcoJLj|&9WRYlDBp(=c^xPS@lDxDEcW- zP^2CrB@F9oC|YgB=2p&-g|d@$4qMm^Y=!u0#B~l^`8tO=|B}uj-_-P~ zDW`~F{@>~xwloFC5*>L!IcM`NVwOb|iSflRSWH+?#j$uUBDj!*I!5P^M-6m<29tih zvu!;lBQ?I5=UJd^NYXFz<9UpXN2ib$BxfUd&V^+$M%EZ(d0C8+FKy1J*rC(l2C@n} zDj4bO`wWun5uoY7rhFwBxMJi^Kb?3K!E@l15%njS+#yy*f5N2lu~YjC*D())`J_1y zb(RK<>``ANc+OHNgdx)3H=vk>NRe;&0!x)J@S=PKE2LEqa|Nr-3Z7pUV`LA4>r5c_ z+jQz(G(muJ0YPO1Xa%i^F;e6kD`Skz_l@!xBP$Rf3_w(x==h{D3-ej)l?dn$QI3E$ zNa#teKwsA*aQl#(P2Y=%TM?kH6o@gh%{PKEMtpotTSY+F-;VZ?wV4Qa>jYV`Mb~JP{lG z^gxUeo=TfuF|yS+LNP|R`9?U#$Uy{D?~AR%hs&^I6Vv>SR32l550zo#5lj8_l`(GA z6()Tw!3}Ff!ni~8V1Ucx91|GGN0C`=3KS81u*|F^BhUIqFvbXF3y>3vG4hIUgky~G zfPsH(Mzh#sq@J@3CuhSt4C@#_Qjk=kBzwFdsa#3@Q9X))q>GhAlj4P`5C}7#7Q$HS zm$A-ip6@5Qsz#H$aVlQAGS%$PTMvFz=2ql$&qb20W_M&H1yqW=^G?5%rzD!(n^Vyd z~w%Vh@7! z*BIq6!_Paw`zEK1YHo~vV{*oF2H|;*MB*52X@;Sg;D{(EvCogK#_Cg81C9xQC&$)+ zN3(QOO?=zZ0rg+-CA7VQk&h7|Pv$GI(cmnL1CwZkfbl4z0vqFfOx8IBPXlch# z`$eI9W)E1?ialg)@jFqJoi~}bi|3+WOA)XNg#QhC?am7O1q0!?YNYQ*@SL)W7$f@; zkj`23poxwp_-zB%4_7eK00A3_;B1M~gg-gL3nS+vz-4)ikxB%V=e)Pxj}rdecD|dW zb2x<)+6)AYDRG`zp~Y@|4nr4iuSgn)hb!zjK=6%2z^7udwuDAwCx1Gc#qPgw&Rw?` z0%om>_!I;KqKioF@8?`>zN|<2#!4euI35P(Gw!#XTTFFER`}`oG)n{{#^#fc9_}L? z_kh#GoWc0xT+DIim}2K3{GpmmZ1+?9!jE~D81=|C2qsnu7z)>f5yS>sEO@CRGa8ogg-V# zbQ>^kiwKSnh18Mxp37ZcGU@w{$KPuvcWfeetQ}0cV0~2B3h;L; zI&6QwVpMEFjyOjs;GADZ@;ngnmE@}k*x?C|8j?$GwGblXP1?1FpJL^30PU(^#GjDH z5`7V{ry5>m_O8jqbqJ6FuZS_?pGi-)17qAI4!!ukV$vT)d499dr(JfU$w$rL7TctU zVe%njh_@hIb%|t97*(Lej`G>7Q&P;V`}t=*({;egtr| zt4$m6-JL7%mx|9EiKKXcS#hta7$0{g{ga(zlYSfVW_cRJub}_K-kShcQKakN-RGPn z2M7=rAwYmb0tf;jVOJ0Xgs=z_ARr>j4nYx+WkkdTa0AD20tpfza8Pjt6}Qn*M^RDH z5e0PIMih4e$4eA75=X!1sebCDiF$SB`u)G}-v4c={OYact);7%(_Qs;9IkXd+eYc- zLG0U!Jb-!DkHh5;Dd^<^>>Kxdq~)DCV)f*04KHDF_z8ea^fHz2z)Zmyg&J%j^Ot{k zIR{_@O%B&QpC=>ICCVLj8QVy`&A zmCdl%U^6VKPjFs@e`}?m5loD9hv~2G=l1Q}H+V^(V8chQqP?(lCj}QrdJMOLn_)1l z$b(5yJ-QP?DJy{N47JEn5a__c<9xzTPy}zqS_)h5v2i zzpEg<3xt=A@Mu9g{C{!NN5K@>lLhHC81|TnDTU>(t}B8`>A@v1%#|3P5nMbYvpN2? z=-hcsW{1uhojPB9dgsplf{Rz2*|`-8ZcVdXmktfqkF@I4xyzW&Ejwofi*ZZ(4<`bq zi+zH}aer1bys)6{nL|3BF(@rqqfeJ$jiJHw#s%9&g5%PI9V5XVu=|yseoAm9SgTKP zVV{=4ygol~>}&q?1+d%Z+5GaXQ_WqpFhf?q;O*kzPgh!3>J_u>1mVA8?8|2l%d;|; zJvs}PgK$vcw%k;e`g*GU77i-tz-R^555241-gx8-vBhRs72aV;DtLXS2Zw*azVUua-ezo4oyeb>To^H4<_=$l86 zHXC;}WWTo_6wR6(^m$+%>%Eq7W!7%LE?)mh2O7lEA(+cQ6Jx4+xFfLKlNq6 zacj{EUj+4y1IE$aFWPjOt$*6S*JDVB?6D@^gmkAO%x=`hZ7-blQ+^xicoMQ3>&K1H zLH+I6?(64NIUJGd73*8;t zsJBNlEaty^@|{ zUvYq#E1oU#S1;4g68Q|3@@3)*ah14E;@~&2Rk-|Ack>y7v z-zA#wa3lRr#lN6%V{ZfL-<150;y;!A56Rz1Hg-0khv!bVx0Pt@X+Z8q8T$Gve1PQP zl1E9NAbGOn3nkB!yhQR9B=*}i;yQ(I5$_Q1R{VY9qY8gk@(bcy3jaX-Otf}1zEZmH z6&{CE5zDvsHR@AF`;2`Jv^Q09ClYcO$)`&mL?Zv0qOqrebkh`nkvL!RzY_};ezoLl zMSOD6l)qW=H%m75G@#em6GQzTSNv`g<AMwF4p*ug+}XT|ptPgi_Daj3#alDJVC zPeQM?D|Uh8MM`&>(p{e)ncOA_g=J&N&)zf{EO*u-Pl7$%Cm<}n}dH^>yRlZe|=6V7`f#`h7= z68UJD;pd3wiPOY<@ey?v zTJd^uv&d=XtjC?=-6Frp&G1LXUE*$WpZGWN9r1n9+OztHWNXjLTt}goZwjeDUaT$F z6Pt=H#5SU}Z`DO|57As#p>KfXVPdX$ws@{MMVuk>wIb`o2|(nf;^pG?;u>*-xLLeK zyhFTCdFWB(KK2+90{8}*y(J2+kPEOEZbX-!O5DBA1%wUVzF z&GjDXjJ;6sCWZ5bEc4$Z-Y-5T?i8OF_lW%M&wOu)?};CYpNn6JmEsQ~Kh4AZ#;z#X zKyqWTg=p>z5Z^&^XR(K9?Qac`Z0{4!k~~T@_Y2T7QSuD&0`X#Tk;pIQv3|?MYsBA+ zC8DuQigf>~T`n%ip#J^hd!o6YK=?7q6=DLynBLw;So>Qo6y8DXEb{xLOy6G|DUK1R zh%>}RqP>4uDVbB{si(S~Epy+1@cR`1g!r_$Uwln8_XqHoOE&ij@P8*cPS?>IV)gq4 zYd_1_Aw`~!N|zz_6nl&P#T;>jI9fFK5zuqKWG;YVJ1-XbjEVA6kxOAH7l~!!7V$Q5 zoA`kEu=s>%?3F^#%aUIa-xA*ut-Y*6k~w*vcT~x44@)ohWU91Nb{;+86VLc=HMRBkAU$u*sfO}llua?+QOcq;- zZN!dZhS*c=Epqu7_2r6Zi|2~d#C-8$agkUct`L7O{!zR^+#ud8-X?Ov8q0q~-Z;9`TABmrdN5yZ%N-0Gy{v|klf{-|n%F_?EcOsj6Z?tQe%3I_)_&H7lIM!Q6PJj~#j8XvTV(y# zi(AC4;x_RfkqaA{{weW!agWHQj*LGjej*+bzYxC`xfqh^Ylzl9)=83^i><_VVn>my zCz(G>{3W|slay|nI9r@2ULsy5UMa2=|0ouVW#Sg`HgTKyfcUV;Wo)ePiy{}RQGQqC zvNXzHh+KR|IZouFPRhw5*LG6wAa)gdid^!^cx(TP3qC2IFLH$^Wo!S63q2`Y`&ZXV zE)u!^lkr`PFk;^?P9~HU4lX9?*N3Qdv+(>L8rixtb$@m^3 zS7TBhB64*nDc>w^ z6YmlKBt9Z?(J0fuBy!0p<@ZFc>7;y2r_ zM9+;{iy0!{gR|V~&&viYe3+Ok=82QUX<|P;ci|hZ6YakA%IsK{?N8GWac1~(>YFU#tH};Ru>9TR>(OD~MHVYo<9~f~o zP~$+w%AKv(?5UVklvw^lFDKGf)>=}_x|YIP%K*3cxv;jMoZVq>*Rnv@wCu7Lut5^I zssD9PI48R&$9LV_zugmqj=Bkf_9X~OfY0gd938Tv+kmYJSw{!1a9UrNQ~%Hk$L%(4 zU=R!-H!P_HkL{bB^So0hJDh!zvFQ@XNz3U0n=!N-zMUL#tJ93 zo@~0@)E_ooQee|1h1zJ-W!H~vx~wc3p6#AK@$lN3X>0dXlx%U1{&9Ko#wM`&vEHcx z`!5I3>ZV2KIw{3xWXXv?__L4R;-JcvYzNreH2dk!rRZS2$eO;X_>R-oJd$p_((BY`QMz!EZwu z55l_5gWm>{9{e^w>#4(Tzo!p}vSEs0;|rBfPHmY}v$WR6=PREKhKp(xKYzGp&EUpB z=?j(ng7HNO#gBd)*z)MNPR7%)bxQ~7tU-am=p`<4d*BFwNgA(GOt$a1u1XfMlMAX}jD-Xxj zDi7DXV_&272P&5CIDne}KD*WWW@X!GTLxBbHZF^73Utc)V&L-L6`={eVO^$oMYt?n za&7Y(2lrG&w!ps3mX^n_{I=!smEW~Ie(hHW4msPpRK%yey%Kg(67R1FFMGan`8L#g z+kr!YZBJHS2Y&$m5d2rdAKG?*Ma><1Dw0vQv+c#oWwEr+7{8ZxXXQ$h_CQ5s2TI)e zWaU*ecU3N%xebQNy%GZ{&-lvOW&B>=@FtcTXt%p^`An8qFNgMNZYdAe43x(Q%HDW2 zCpic8Nei61qr%zo%u3i^F?E4$ml5%6Lz{L~1d4W4gqA&H>g%;*SLG_N9jG_^a#!U_ z)aUnUPIfP~*$G!8-7%>$`5;137r)nPAuAG+M_ApSd>`<vuwoS zF*R@;)OssB?x^cap1EukXV$ten~ciNx2x5>uDoaE-PljHI@frXqGGmNF2 z!0ZfI%6YN!nl!f$t>Zjfc@_F8jvR~NO-q_4JP%(RF>ra}j-}Z5CPLuU4?d?x+uIe8+t!6gQ zYjcmfwVG^hy{1V~n;e|kcBHPpF6WOQ1#-H=mQKr+jh9VadG@mC%5}@$UHSSlW7o;p zv?|~Cr;lj;3f6W`J<;0E-j8nO?_zUa4Y_B6?iY~waDOqJe+z^Y%)9GQLQOszcH_;H zc{ltN(gpv5pkNzw?FhuRMYcd7flty}UgpN5T109oCMZ;7OFtK8=hod6AZr-$n&F3tg$ zFLQ!472?_6NiarnJli|+V|pS}GGWcx9i)_GA@Y2l~8%lYIrtZwgNK7u+9IOK|HWMz1_YUqk6i33<T#8&uRqsZM6DaZ>Nj**|aL;QBu@fGl z*ZUwQX5tBPJ-){9VjH2h_5KkPH$kj#%<@pvg}AM%Pt!UR>p)s&B$(DQ(j7+XDrr9@ z7zCQc%JX4ky+O#~iF`&@ZyAd)v3&GYf7Tq#lb?Jq67OLwr*OGbn3o3C>(fThR2F$0 zk3;HTiXx3v8$asn@y(1ojkSwVOlL9EDbloa{mG7-&oTEDg((u^@#Dr!bUK2rXxNT9 z&M}5UsIZ|~|KZ6)k+9+GRq3{W1G};VFz;rnZ58DQXYhJ7rCEX6$6-)D#lqA z{PohOH(5BV#`^da>%wn>xOhu=_xr-IqPql!ZJKC5B`CMFsc)9B%DxCEZYHmOl@Eke)+ z2ig+h_-epw!&RmYHzC?o*|fov-TKJgjN^d0`9sJpay#R>xM{<1#F`3Br-v0- z3{MJ^nZke1+)h)TeCxyU`xsu~zc+<5u~)b!o64BNJ^4#!Z;*>W#mL#b9h?7Wlhe!P z`Qv$XHz>lNzr^%EYErdEjF-}rdzzGck@AyR$|p?9v9Xk%JjCymEOV0pNOJjg2@*U!@^WtQH z2=Q(PCVRO%&~?TD5#v*Nf=lHoFO_FZCk@9Xy5&Q7T{o3T<JlLm;YYz_te zwunN%l>ws0Zm>?RTCg4zN0UCaYI~-H;)Xy-lp!G_)OOt=4Va`(D`!XpK5eZVv-4Bk zTv5`A=8Ec_Xs)P!m3^WBMtB2jTd1Lup*V)0RNZnBE`Xk$qQ=&8QL?pM)Wmpjjc8hB z!l)VZk8;PvkE?Z#X@B`s^7+Yy@^{ter7?MyZ}XqqKj?o)K?1 zV9#hbhCtQUg*)EKB@W}X@7Xh=4vZR?KPBxFo$Fj^!qp7nISAh9>Z`=EGeZYG$bk@!SdQd8by#@5} z0v+$<7KcU_hv;Vyn3U{-QY+BI-yOF8^zX8f>;&ZTve6UrwUquzHj*CBG`4E!XE&Gv zZ5xeXkEMU5k-XtW=7R>y>+q7wZ)|G+2_u>+2$81fOg zc=)M-eqQ--2f+d5UF4wMUgVg^ZoF)8@6cpeW@}`&5hNo5PNwOV@1co)l06f2YWxsO zJP9r0$s3I)Qq16(K(vDkI!oOs51;c*cpkwSr05EQCnR*m8wK=H6XQx0EOab~&n3R7g(-`V2-q*xlZ>el)?WqPf?gr_>Wd z#y+3d`?%Mzy>F7S=Xr(1@kb!9mz^H(?f|zc^fdKi;-mC%pCAXpOK8xU7l_g`$rD1x zjNfceh>z0a?Y4R0C_OwB&U2i)3;({nWoS=!FL)_$rFOAxriLBhGcbagN zT(w_ESDo6?LX;_nP2yeFytz1y$`lm&28ZEvjOVUQ~sxXPv18wK5wA5XW)=CuH(5&mSTYi2r!B z4f3dlKSXlC!M{{0%xIL3fKNxfPe;I~Bi^T@!0KSW4REM2(Hce6a2AD1jA5%NMIKrR zlC7)QiHI3_1pR*bE9UPR|>N7}}ejBs}L0pGtZ;t%oy4^Y$>u@Hn zrjkLrNw8Ucw*xk4`;SvGs9Iepa-W}Y(qv$@GJUr#wg3*BU2rup^wc*L_rqay5F9|h zSUa8&RDH)#*G@P@*{-L^QgKuf(q&_Px~lIOrv9n!t!hG^Z32TnHD$zZtXOaVuNj+^ zyP88A9rZ?R=h#3D>gwrGZ5wnDSwDlb_pdgbC5NCAhGcCJcfWUSisfcdwK`Iacy-ww zs|y3G?KFGn*n+=6k_pIXWnQqkV8Y5g&9C&y_B?IlZ7r!seSsf8+H9b&FBnvyW6!v9F}1?j0t;wp_mMZ}tG2K{cJP0@bUOf{LIkupyB)UKs7hzFYyvbNKaeYv6dkwOjQ#8_vG557gQJ zc4G%EgX1w!1a|{mDcnOVUW9uIj&)(#-@$zk$DLs})}1<7ch-e@SqHYkuj75l zAHyAn`y9@04?x$$aQwOQINVck+;#rVzaPwEFXuG${QniU%I43XK6~=Q=@aM9TS)5$ z>A$JPvNs(}plF#MoE!b!IYv)g7s$v=R{!kEBx1B?GIt2tf^R-HSZnU5NFGd9c`^y!<0 zOlPGAm!!Aun3d9HaK{!I87*40&OnovL{d9ubnMbGV;H>sgU`eI+Cy#x92b1X4fla@ zv&{wF&m7VrD+h+nP><DM$arRX~A6i{ICHMmB zzHkN1!38gg1Z$wLSESLZ+LH9(DJ!bkKg(V~D`BID59>E9Tc*zDjh;Gx^1`Y4&LUVh z>(T8$wRJXeA`^A(f<*tLjdb}8wRxuDtd+KZ(>j|m%x3!b-?7YQOomOHyJ*Vn>CU1# z3ueunGkscQYX0Q;*p>Z84a)S;1(xZmVoaVN+Zv1QzL*|k(r*6L{LD_VLVk05f|aw>LygTYp?U%)s@ZJ$LGbqh~Fd?x;n`Xj1$Cs%R?(WF)7U3?YiqV{qJ_PqYJ~u%vv(HN)0uun{K;_PUy%-P@_$sW|2D+l zq3}@-rWeJwk}h~+1F10_)6lWJTsT_?c%7vf19vh)n~fU=*{^Ra^v%tq>E~wS=J@;!Ka8n358*|(-E6uG5a2KO0nGB+($FiH;kH~pGq!oCh<)O@luEbYZ`6;+L)8P4L@1 z@H#`~Z{lpxRzrU%6 z4+qGJ;%xC^k&ky6e}z~it`%<+?-Tzb?iODW4~mDxqvAK>_hJwo&+_Vu&BRXPRPk2v zZ7~T42=f`cW!P`cD1)3#P5VH`&I;nYO6CI`rtdF#kmQk)$4Z_gdAj7ek{3!YkbH$? zGtV34t&v=&c+M_ndD|rKkj$?Wuztp#3gVxa{F36|ko>X8cRoxXz=2LCiN+oZRP*e^pmo-P<3M?y}Le3ImdIzek#HA_`1-d=cdb|~mMXqXw06sONPa-v zMWUQN;%nmH75}dIslxw5@|WUwBS*h^V;s!CQbT^CJ6@I_uhs2#E>TB$lq5gX%|DA+xz=Sj|&Jcoonet47lt`M(Re2L;W zDg1VY-zE8B$&ZuJ^PIx>EBtlI?@RuaM7nZ?|5L1qYZ${Dkf=us67@}!oG!T=iT37+ za}|HRh%pk=Fo`^J$j=@fnGsRva@7tIzM>KE$A&->I>6wh5DPAbf z7k?-6-ka%`i>t&xh-Kmy@iuXr_<;DZ_>}mpxJTS4z9qgRn(HXaKPH*85m=ue#CTpG zA#;)oSzl}<8at#2ZzY)vWtgtJc)Dm7E+L#NXBa<5tZuh$j>6}QOGG}ZXTGaMeiWH9 zAK8<9Y)@_yZxrtq?-Q;4wkIS%E50D|)gAS`BYq@W`)x-h^93Q(Rf>2hVB|2buL$QW z0l=zakUwlV=Upyk(`<+V3KZwRYEBxku2TbPu0BG)az&4WGi}rr!RLQ?&XN@Zk zsgG-<$YtV{;_t;jiZ_Vn{s-x~Dv|l_5`W3A8rLl{{cGX@@jdZV@iVcy9kp7#KS2Jv zVk5DsXziz+BH7wc>n=G<%ofiSM~Kz!s7+P)OwrsQq5S!hFBg}KE5+-?b)vPWc9Udl zPwigG4~kEV=DrE#RJWt{mg3(LKN1g#Ux;6e=6(u#T-_gqMQdNp+EZ(#@OENHvAcMx zm?I7qM~Y*_$)dHZHe2#Mak02mwD#1v&WiiBSX?J=5x0uf?Wl1zEA#CW-xLpsABl%V zE_Y@6@5MOWQ&O%WCW+QwT64+PURpcJ)?Qjy$<|(4mgH=4q&P;LBF+#m60NFQ1bz+gYPPF#Ywo1NTtZpamafLr6 z{#ATgd`)~y{6Mt!(vC_#CjOG0w3G0ghyB+?OcmRT);?NS$$i8uagcbXI7%EVP86q# z7l?DjOT^2>72?(6AH`yEgSc6|MZ81YAwD2JDn21TE50DUBEBwKduks_{)bpD9v8nC zxhUO?M=@DU5!1wz#m-_^vASKgVG7R`&ljhNv&4(UMdGF6GSS*o`-9}wVyS5DsogBu z+Ecq*@_i!L*|UAmiZ6-##ka(F#E-?pqP4H~wPY^Ur@opZzqdoVk=Q~^6;Bb<#UA2m zB3JY?|5@S~@f0r6q+3Gr!hzxbL+vjWUtF4DRHd&Je3wXr0+e@(G$BCw717#5`&2T`2Qa=;OsMC{wZz6^Gx21x zgV><*80rQU(r;D>h+9zQAQjz8iDF0F1C`QF?;yvP{;uGRu#h1mu zi|>lGcR>B$h_q}#neWud)?z!6_6!)_Tci~O%Hu^^F`#^rNXrD2uM=sRfO1sC&m0)w zsd^p>(Zu8Dt|4wy4RN|Q#IQ2tTT1GQh^@tTVn?z1^UExSXN$RFo;XgNAWjmeiTUDe zah|wPTr4gXmx))3MPi9qDpr5)xmDq}i`&H=;sfHt;$z}YahJGPd{ulyd|Nyyekgt_ zekL9jkBJrHcOqZ>azBLZ^FT3Cq&*A9r-%`;wb)MVC}xP=#9m?_F-y!A2aCf*TE}2{ z6U0g4G%;VCEiM+9inJoc{0-SYoRgE)PEJglebIu6n5vgPw{s-&OLh}8GkRwJTDytI zIMD&8lx_y?Q07Urn^^aO9bJmLly%wUtn6AeE&rbUPxCWNI?n34DZMDJd|6iJrpP+C zSKN_hPOGBROH)_ROxac5GL*Kab#do)86}vkb@b}xUDrp-nis7K*K)V#G|z6fw(F** zt5aY{Eg09PBxP-Cv{mWZ6`|f)a81{@DoR~9DTnq0r!S9e-cu3UIX$N?Y>_!>?ea78 zXXigz>7>oezaxKVWhiY&{%4?@R-W&k5m%lR_awsN%ah^{?Q=_;m9^QF5*>8!sX2KS zq07cpgf4VXeYP?o?VEiWWu2ofik()EX1$-)a&_zVX=UlrrUUv_ggPK)@3fK)O;=PV z3~asny}EtM`W+q^{Ex=jh-cxS}n4=#-_ex>pLCIgOqvLIaic4J!Y+f$KJbmdWJz@tarFPwWg z7)*YmX--Z>Qpf(xT~wpQ%ey9L#NqcZ8=7CUxapBV%`=a@e;KU>zT3Fgx?nVM-H5|S z796O^SQgk2Dvm3zU3>-fJ$&SFOyAH+EAm%V)<7MKsOQpa^Xn8R9|?qq9C`mz=vjrD zEeUQ+Dh3xPMfX(nft9^5tlVWUTM11MNzqnTzG8CJ$nwdTXg_^ zx#v*Zfz3+YvNoGjHl2Py+YF;S>wD&p#2#>0ufYBt?Dzq5m z8n*nFh0A~Fes}n!y_p+=Ihi>P^HV0}?7xu*uolLEo=q+t2J%(AX- zN_KK~W(jO}2IG-qR7I#6#<8*7*^M^(>dqS!*6SK!j1nMpV+(MGm#_^h#LuV*|D*GU=AL$z8U z9Q7GNghO|+lA#c%8badRiMWCEU+LZo#C^@^RmN6OeCRMj5*h~HPU1;2JdFz8N!rNN zX-*jDJSXsOQh*uKLSgeB0ToyIdR`H(}zi6pynA= zyU%r*HpsVFwH7;p{Vvz7JBjWc`0EZwsN;;q9^vM4N=5C_j(Zk8oe)wdi@_sUl_eB= zQ_Q8vJy)j*N^nO~tOr+zGl5{_2wuJ;tJ9saqgl0YAl7BG+%b$zLquIR+8t|RDYBLB z*(Mfc*X2txcO1pbASR*F?m2A7PD=9@JMMVK)eKRB&9`$YabiPV&a!bQQ0?aw&taiP z{1}&%B-;FQ&tnhpD<4VI9rt`{y$3>FzAthoQskF4>NR4{NfhhOX3S)In`8gi&5MbA z)m@kG_1q~eaR5aSw(BTf1+hM_c0=K~xzEI-`VIJk(P_vCcGI8W+!tELB1{gx6XboA z`%i4MNFKl(E|cyVd@%ZkOuq!L5(W2PZVpW!zdJEPfi@tAX3X1hJs0_u$KYDFlG^{y5*SoOk6nrGMUgek-O2BXw$Jkb$+Y> zdYA`!L%zHr-;Uy_FdOeso5EpN6WqsG^d2JF=W*Dl@o6FMzw6*IHV9T0_9iM&-+)(6 z9?3HV%q4}Q^wji(aFm`po{$)&hcBg(EGbG)J2>oLA_ERp&Lg{d!357DNWL^mPaiMb zb~EZzwU;@G#B6Mn+CRb9{t3SJPf${)Ej+w)cAc|{sy2t|Wo`_RBL7}5GJ9R4tSGjV zy`Bmqli9NHSEIhf4A`USET}3eq=&tQy0g`+l&={kiKhZnt>LMvQKGF8I%%-4U4yBD z^_j4`&82 zJ+FD;93K2dh9R;9jlB{ME!+ukgtLVOtTJ~ZlKA!|vYU-%yabbBPIX+|9qdt+!+RqIFD(ajXfWKKq2%FzV(lNn<4sEJ2?<1Kb7wzb6B$EvCdilyp{I39O6 zKM*|ZaF`AA9e%@DKOKI+kPgf!&(H01g;_|9i}NNqOnq)cyYH<qtNuRa5LcM!Oe%uMGtTWl-+n|_95J7aQuQM<9I`8H{PIif$IS`6pnE`&g`}Y z{y)KSRugA5`8SReyO~+ouoj9^+{!w&Vdm3?A06PhKe^b=L8$kC$egLO7fqY)Og(MF zy!mry&Yyfy1Yb3uz97&zQVu_QHt^FP%4i0m9Hn3l>hpazgmcu8cFi7<|QX`?LzyjszD*I;Ezjz}F@? zKN74H3C`;iOp0)w@l=Yff)}R;>!i1WH=Gu%Gs7h6Gq7uWtjEo4o|$I;2Ny(wwfh7Y z4CUV%kuwIRb$|}6>}`|QCb%e)mN^0ol-o5=J2jY;9-J3RW3nYfXJgGTQupnc(V{Pw z9RD#ev=vqfGrw9B=ikSqy8|jCyND z&9c#X1Lx0o=8Zz4d86k~b-Y!#u{Ee>{ppn17Y>-S(E0JI(gpc*=P!)J5~E~}`J7p^ z7fzo)YtGD^MRTSuoHcjOg3c$7D4*oao4a74SMUGf>zeIuSvYwfJ5y_Lee1dxdEGG2 z?6v`m<|EMwJ^M2Yi@l}8wo7NtS+H>OoT=0KNH(@Yc;1Lb3$aFd$#fpD-flF?xWA^v zRs~O;J!{@XqiwFq?JYf?I(1^c zFiOmzjMd3_)It8G)stt>%b)z;XsNJSZ{=Sr+}d7BKweq;*NI#izAEAB_-o=;hE@fy z4gB8iSBF1c|CM#Z3#Tt$m~Qt!cY8W4OQcVmK4sC&iL>U+nCr+tdCHXe(|_lW#jf{@ zljl#KGjsX^f6$LZX7hq0jSCjechaZMz38Ip7#ZpPMh#D&yl~*>ZW8g(*?7E!-SGGEjLw$ilNPqmT7E3(n?&*WveJ`}hK^cT%-@2>e~W8 z^JKtr8-=GypH$Pw_-%0hbf-em#mu0MadZ#BVYkmyuyZHUooWS;X}Il%vwq4SB3&w|%NJ7v(k>p?z#{DSghBxJL;2l8Jf z|4s2`jSu4a%aQ5L+8)SXO0H0P{-R`j0*QFOgreL?azt_)$(<$hTSQEErg)A>Gi}t9 zFZm+Lmq@-^EEY=@f0N|fB;O~RH8?2eNy&dzy1kO$lKigZLz2HB(T`t~c(`5*W0o?$ z>t)zlnqU2pJ4wzIc|K&iKH>mz zkjQH!egi^F%xMW3uGwBA=wN zyx)n1;uYcv#~IRXR`^ZgHt`;@`kK1u6mE_?KM+3=`9hN6b}d~{ z2(K&IuBGD}OQt_rOc(j2hvBD*eMP%=Zn$JV1!B5!V)Zq27b<+NxL8~&UL~#)*N8WW zQSoN+PVsJ$Pn=l(BceHeA=|ZdFDZP#_@-#r(tRlTQ}G+IQVjCAguVpP9@h;dr->(v z>0%f0gyS80%$k4jEXAKKo-0lh^F_WSX8DEUN|E=<46nY1Zi~XVird6{#GT?U@n!K9 z(bxol-ghN`BJyivEbmM48<8)n8D2-MzJ@MU;cdmvVpp+`m?he^b;Bj+iQ~lTYwTt# ze4coTc$v6Dyjrwt?N&?PAZ`|K5$_Oxn0cEyPr@z1T^l9d72Q32w5VI8YoW=8ETt=ZX2^Y;l2jiC7@65PvWJQM^Ii zAl@S0Ay&6l@E3(YDee|u6kicv7dg3s?K&)$i(iS~i+q*NballBVpFk&XlxiDT?fhC z#9rbV;sBAeDX7=jGyrExwrl$?k$jn0EUptd0fYJP7atX$5T6xa5ci3H6FFmp`45Tw z;2Gs(;y*=vnb?Ha6zhnb*TM9y#OgK-IJ1NCgT%AMQQ~;-?d5dUl93XtVj2?s-hXKhZ}s~n{6seO>nLW3eCEM=SHFKUzXK3H zO!2v5o;XgNAm)p+#d+dFahZ6f$d^(qw;^TxaI^J|J&A%%Q~#XMo~K4484+&Y-^`4R z9zA+s&S+-09^Fj%q?&~Thvj%LRiG4`iy1d4Cbp%}P!S%Tu+5x}W9Nhx?Wj{!r>qX< zgigz^TU5KG-K_2Tcde?qw(h1-NnE*;U3*jfYPV0^k?c@hNt3dKH9O1ey7e-`#kE!^ z7QuA?(WjPe%ef;5sY^%TtJIhY>W(=4Lhuit)_0P#H)hu;iZ6@X)U6`WyA51?N!;4u zIggZMTG7#umxW4)R((rUL@_ zl5nIV&;j2+?j0`L*fhDcW?91OjrSp}cZ14Md2-Q{U%s5_)vI(_sBCCX2xX+9b|6$5)EuA{F5YV^-e(ZD7*<--hP-W6oQ)7UA)e7?z;ao0k1;rQ64* zV$G?8UkpF6j9>YFXhynAYwHQ7|BG<0NOXkdQrlDcIxTRa}_u(x(8zJDDk>fh}N z{77tt@`Bs?mp;+&sOtvO@ip^S(Cp5-KkIOuyDFjmKFFD)E5gG@eBvdxo?8)w*)ZTas=2|AN zOjW$v=ll|{?mSh;tZd#cr1zVDS!g1iozaTszBfG&S%6nP;g*#5zs$q?_!LJ8&; z*Ns0+$qmm!f?#|63D|EB^HwuBfFW(C@NXdD0jA*-r9e+}9ERdJ;WGFpkG)=3Gdz@V z6Vp7xkm02a;RP9wc0zG{ULWki^xX$C%{BD)IGbMH6bJj68oWqv|H~M9690H}FhdFE zcdP47gbatwU3@6i6)7;2@*U)f;|U~G=*^^@O8=E+CS@FrW`$On&kVV$4jYR$T1R^=|n-XYP1UMNFJL zms(FtKvMpwcPCJsMzJ+>o|g!51;yozJ)dHJ7~-s$co{`LFm)$BhQBnIQ~N_C^FA5; z48*#hBK$MBRJP1ayS$4P{EkWYGpP}q)<9TYKHBL9$Da&d+TBch8X~>4MjUR^a_^l5 zN0VV*+83C1Ni3}q|6tOdk91SuZjGgVk!c@^r8OcKF*|h^BHdEB{jsz!G41hKS|f77 zvXit0>9)do<^P@OCL+SCs}bij9p-Vm*gf?)r2jvi$9YDgnaNpwo@T8R=V{_YFkUim z+Ggz&=V{hCah_(~s&8y2*)MU{`xVnJdDvmT<3V;$Y%?Rtn|7ImK+F^&ni}sIA{)6d z?PMIu;}0_d$C2i@cC~4jy-c=|#P8rR7v|x@JFy3t*9cY#s_}3kN2XUNBt!DpHVr;a zyyO!Y@)&zZ)Wh-LS*?KS?R8(!yg)sJj zS(}6zQz3Y3Dwu2mXUe8WWjoc%Hhr%BW%e7(Gnsq^R}~5$D~p0dzDkFDI~qrmxAA5& z84g2*XbQ(^nN+5Q@?>!xQ48^vv^waFibIc1(3c&CJGzG=f796Keki zU;8Kc+RuA%vqkW?H5}ScRJGYm+hlGG*d6{+xWkM>4Z0n%L6?Qx>?S0Cz#JwonEeWY z9`+bIj~zyx@K*J}800cr1b^ z=LGA9@WoMjZa3kh2p&{sETSZ{aX)#TH=ei~4mBhG1ZO^Iw-cUSaGWYlz66KPBD~sT zerHv;jA!lhO^JELVpHNm*VKglL^Wg?90o1H>mJ6u8+{3$y>M~PC7c6FuQy!Aa=7p* zD`W7rLV9_aK>^VR&P?#6hn1Y|N>1bd2y66rfvu|x|LkZK0*G%t}pd{mW4 z0jW_AXx=-axcF+tEl@yelnHnzghcwrQI)1xA|8(%`^}t1)f3s4n6IUq-r_zv2=~h~ zSjU=FBMF_UhWXA^!?=$)pm60Gh9qXo!r!ytaF7zpmg~!w>&uplBxbYwA9b>O{wJze zhckn#Mo!e`=1nlq8#rUxpkK8sZQ`?#m!}$EeyaP$y=?RIW|=$Fm!Il>aRAu-Jb|n{ zG5>EjHf$kVQ2-Bc>=_&MFAbX%#?!5^NL+&g>Ix z5*ZPk!Wq4tgBN=fd+VARy+v~|Dfi4y8ACEU1s7ndZ=c}&p-2@>OwZ&r-r5m-ET?%| z+qB>%cpRA7AuTnnSq6Y_4{cd=X5Wryo}LO9TpVdPGkD2D%$aq})YT{ zfp>gf_QJzKVu&97ZvUBImj8x4u{P`)f zX0oiA-1w^|&*BqK_y)@_O`-jT*|BB^naZ6o^YbUB+4`Qc{_hl8eTt{*6Fa}{Oxn!u zoJnhj0%)eHo;ah{`)HAGCM~}Z#2K>xJ98E%-^pCF;JE4V#tp!H@#%{@4e#c}*G?E- zBTzHGeyE{)lG`|#>^5wHM|72)B8da69&8f{paW^@X2L@a&e+ z!uteaBLwgXH?y!_-pw35+W5YbbI$B$%bJ7$>u22N1lZd#kMk&1#qqbezubeZP%hH3 zT$X3ctv+}5^!knyLA>2;Sr;O}udfIlm4qn%c@U*8VsV>?;DI&fCs7WkPb1CHC&hIs0WeP=hu(QOlL zx`~Z{-Q3x|NcU^z&L-l)P%m33$og^H1?O+a!@hoLfH>QZdhpw^46l<7eSf1zo9!3U z*F5KK++SuO5Y_xo=guZ#oVK#cK&#IeWW4_H|D8KqHFuWhj1%Y1n!BQEb7yg?#>R8a zZ#j21hx#x#laKMpapH9G0`U@YsklnKUfd|&Cf+C7xwE?^zakzKKM_9{zY@O_T?`u5 ztG3ug9kI;%}48YY+4PN%EtT%^W=Be?juAiZ^rckp2V7X6_y2FC7 znV#1xlGiyBr(#2#Y7IMynIg~oOxH&oAPy3FFTnUw;&}0VafWD)W29Rmnb%b2yGmRo zt`Tn#`9O#1ZWgzTJH#i&XT%r9z2ci9=L=BJ$Kqk}8?jOh@wh>{uvmSLFmIF@-&W+C zYs$UF{$h^E=SYk<=Lhf{$@cpjc5bkldyn|}innuwS4h5Eyk1-*ZV)$%e4NAb?iL>x zpAz}Rmhmr%W^O)YGrs|RPvQ3a8=p)5Li}Fj18VB2Db^9q`32!kC8vpY&M@EQGhc6U zfH+7TA&wT!`3C7{N}eN{^A5t7NG=fV++g!PFT|H9+?p)>H0LSk`C9T1qMa+8$m108Nn#VxoUahh*$s?0=P9tKImf@ME*{pTubDf4azOWw&E$Goh#f^a+a7a+PT6bC65=+7pIG}L_1e_ zq2$X&^W8DjW2NNl#A0!sXy*#wB)R%`$o{18M?}s-Vf*%o_WK-fNPbWJNc>DZDpsE} z91mU8XTDPg!tRri8;cRKwfK|YD??l##hdSz!9Pf{{eH&;$>zId@XwSyN1QKSCKig< zh<2{<8p(F9a8&Zm;+^8%qW#{-pCvyfJ}bT?+V6h6Dfxg{ea^6*EBvkEdBe;83yJ^g zoZ&9Y*F!vA>?aNuhl!&_JBN6Zf0%r z@1a3{Rq{dcL-9KiZ{bY7+G0Jig_tUGZWQ(R6?4R);z)6f$jMVopD)f87l@oq#rUhm z+r(|+i{f6fT>MIGgdf_>-&Ev!Udm^PoSsG5elLUbvnUse=6hz4*GOJ3ZW3=1?-1`5 z9~3#Gi~61y_lmEIZ;J=TPsPtf&iZ10{_rLf#9Crgv4wb=*jMD#FXpq~!&oA@K;(2U z#;+D15g!*h#f$OwI~B(ze=k=54n-F{aAEo$B4>9|w%?E7^e)Q36EVF0(>dH7b^n1! zAt%g%?wr}Hn`h@XVm50R_h;uockhwW%cT6}InYbfP#7M8@%fs64)kj~1{Dp$4Cp~+ z_vDX(W!&!T#zgZqeSR$KO4TPhFk8rdJ8l zcI>(Kz@c6PS5yYl)+7%&5)9UdHQKmfkJYrIit^pe^&N{3H14#P7Iza@WNhkQR>#cA zZI|CFf3C5%JIPqvO-S34{~yNM?tA%eU(ecZLRzRiDRgLG*V0_r2OfBD`QSX5%W^iIR_vU7bJkOsQ{8*r!015OWu?8}^GiFfA5@mJc0*HGOzq%) zwG5^b2Ch55X!5MAFP~Wcr{hs&4d>nL zj)#sV4rp4^DrdlP=jd~dcN}@IuvyV5MIF{TM>{Rg+|+;FH7H@gx(^3%ytH3_)}7s> z8KvFVyKA31gas6^r;CXO`GGQ8ABHX8WuB$nF!rpqlv}g-Kt;Qv8f)KfOzXpc_F2pI ztPj_cw4Sw<6DS@X-83pXK1ts<>z!SRXzF>%+Z@LL1_X6N>8^>%)IO^63fI zhrK#jE6A`cEPdDJC!MHoV|~~SKD4BMG_+w)#V}b7uF~aMA7*>3uA&@R7cQbz;}`N9 zR@2qUSTqi8Xaozy6J*P{$^x-#ED*nv^W+Kkhh1ZTc<^0k-SZ53@^!d9hmyB--JHAW zrktB|0%cuF2g43=Xj`CYEJkT(*j4^@Hi!coInLeQv_u>zKDck__F;FSgl)SHIj}_> z+SYY_#)fViVK2B=#+p#3+nY9tyRPnr+SI-~lrwQtUg@BybL1)~uV^vsFXt`qv;NPM zJ{7=)`iDjzq|XUjLj=QNy*v#aVY0^ zA1~;C|M4qg$6w!%yO(8@ItojIPoJ3Yu9@>;$V>xwxk!>f?%yzhRevxSKNS*Y z%^wGX-W++DG3JAa5T8DTQgRvZhWQv07LEDKE%X=uX*-J%fdu}>4!y*Xo}4rv2*o|Z ze0-D_>h%W`lECM3p)7_BH;)X$akDA#XH(oM1L=Jlf8u)ZxkQMw2jlw9qxT+q`>&uk zhiQlNAwDYG5#gxQ!$de_o+^Yw7kCm)`o@{Xrka0`EVOF8ABgwn-$w#D_4t!KypCB0 z*SnV~VAc3)ibLupBZ~9yhcbAmM9-@6nf3Vmn)C0^M|}dr>fLIxCWYfE4p-WS;ddB( zmJ%n|Se)Sm@Qn(SHN}ZDk7IJ{wSZicm(<|j0%qAjkiYk9@nI)Io&yrkhT7ok#_!bZ z$LhgYGW7)clfSkxmYfKmQ?ni`kQOjg|ASMIvi7VwPM~#wiEB?=un?;%0&G~VmQ2{z z`0LDt9i%{euc(pKF2DIbeToUMGs_8hzC=!24|MP0Qpa!G>D|ZtiAylCZ{L zBt3jsRgX_*-BB!fKE*efX*9*16#3l2&7;UCwe>on0Cx<<*D2n@*s<(~N$}O@-f_n< z_Bx8(JMK9Y`E;*-2Y6gF`+qOQ23$sPE+hHVvH_P77^#917aW+i0O_b@eU1V5JeIPW zVtwj4pCUiDT%T`XJdyX-^|@c&iR^KH8n}U3axjVFF^X7nFq!?Gi`&2k(h0O-M_TZ(tbM1I<=J_nsUgRx~08**u}JCkDl z1pIOH>E$=e>K|i1Bfd$I&rRJ~Y}98IX<^m9fMObM>`vlP8VkqGeIfzPZo~)B(-GIG zE<88W6M~1I_2TOuCz(4g6-E!5bcHAR4E(tQQZm=bd`r(5c!uC4(v(lUroeI9WuS9_ zKcpM+Df)6mHnS1QyAe`?5E!QAA+Q530wFLsz+cvlxFnvRdUBdm-TMgo6fV#;U{rlT zRW{J5;^&#TokV4PHqLXH`z(J&8(nP}ZzAtQB+oSNo2MhP1q*UoGFJs6QrJ!JjEzN@ z9D@;9#2oL>Ju#vL5w|nq_ zZ5{XjlErJ8$VP>=BEp!|uC2urMzD(`j8OMy4Pz&rxZnaSq5TUk>YupaqQQv^E*e(F zVjopEjNOQavAIIHaV>WYklamj6M8V-d=|6gXv({pU9^$nQ)ObB`;%hddnUJA`a+G# z?T9ZQMz-0oL-8u~$F{b49>i)3j-9HF;}%o+h;-u}Lp%!|WQPom z52voee(q8;hxIJv#dP8_V;Y-+s$5p+t8$sC@gM_vnu zIr*U|J=c3eI7-hNPe_c?Q|1XtQF^w+K^5@;995AId%*-vFF@6=w{Q0*As0zWFi(l%7+(aK4q{n-){tVO*w;@xtbeZHGF0 z`+w|<@bXe?l5kkE-bO(AW@9-Kqc4x}%7H<9dOCXHe5*k9zOzj#^0tM;2qm-+6RYjR zM7s|$X7cPV#L<&yyOZIzCp9*BJ~bPQ;0-lQF%!&=w-eTHHy{$^UQhX z-jf(0THDXhzYd&y=bin`S?_!1ox%J-G4=)DEs0z%RoQM7e<2`}US@86Hdlm$aCa;wfv0*O=9yRoxSv7zc3U=dVb5j{^ zgjow>^!R7k2zv}nB6}x7U zw#G8__rO-)WazdlgZWi7ezn_l7Rb#YX5-!WyyQGLX1gsO zU^CmJg+2OqP`rvhh#P6V)wJdt26jbTMRKRK@|#170i{r3`bVowMjfjTJ?XJWkZ^HA*d*l>p>He<_y?Pcma z`KezY*frn0h~y@>V|a~8HZpK1Uquz%rTTK%c2^)58yrEY$F`6BV!xPeeon3C`*G|r zHa?Ns?n-^Bxj(Ewk=oYE-C~=0p^8A7djXqu{Mk=+%LCXR500P68Vb{Az?h2bW7e~f!o(Rf%f?NdHV|{R&-{){E4<{meYmPXWwce>{8nwl zEu!JmqWQF>!rBL|V2+g^o*WJD7Y)xD)ghb~#p(lX3p%z7XLb&s@=`c28a`!m_@K_= z^iijsbYxq9O@>xo+pcLl97a|H#`oxQK$o`We|T=RA68N54x1}2xKP-tpf{w}UAyFA zy@mX?g;=OyM~Dk4TzX!#ZJv>$UO0TK+Zq0s=Jy$pk5wGPb31pB&C2hU-z&UqL9|o& z6PRdSvY>O9@V}hO3ufgXf`63ThCfyW%G+^XW#0ZLADVXpOv6yrrJ;|wG{Ua)Snj2v zD3@0Fw-GKdiz@v4yiwt~eZq~_7IZ~z1#JqDY_~fIsVeL=SH|_ zezeO0g9o-nz-R7cf3=5;<}b_}t-y~EIFR-H$^@cUj$qnch8-#T+ zT7}Q(6AHuL&0ij1+_?Tj#$XA6)25eAikgZ2{e=g5!DcOC5m(FTOp87kGdO=e3C-7U zP0!4kU2DC8L`j@_==-b*fF(})opbc`vYDrygR(XP3$Js@C4n8f&U=o~H#EzHMd~TzR1$le_<~*Qcm$&}RBZyHGoziaDRN5WrjBw;!ix8Vz%q_Vu5R5r&+tYBhREZMs`rEM8* zy)(-uPN^6-kKcF*AyF5u!(HO`mAV%o!8QX3d&0bJoF8tnbsgyIJ9< zpl8>^q8+eoL)rLQWd}!3MwTvi8K6$x$Mxzo0ShrqERSOShAFeKph~oBVYkBWJx_7^ z_QC`9`x)3#p|B_WI=X%pBMs*_wa(Vt9|8D47I&+lA|Hi9njwVA zSsvTPmvNg1UgvLV{vxUL)7iMPfS=*N#z}UJK2A}#>Bhq!tam4NtUAN5m-X3tD+77p zbzW-eI8l1!Y zH@1DN;kS9X3VO$?v2n7h_N7o!|ERW^0&R}^{J76AMgjr|Hv$AC{{D-iy z%e4g?+FtPk{}=01uwU38zGIIkTtn8U;CBVnC%Cw4+1S}zGai+-4ee}%f3N#bZ0-7@ zZrVaoTSW4nLXHu~iBrWh#rfg|VztO?iuu=xH;5a>hr}nu=f$n!yW$RUU$%Bsp|L(= zV*?gTo+!=~&lh9jE#gDspT(C%v)%;CYmEzm<#!j0#1lpSnrD37dFf{{92dx9@nWT; zf`#F$C0{G~M#xhHXq2BC3!y*va$U@{K1mDlDNKlkobarw8DppCy8Sf zUnY5$I8R(GUP_`oegPrZDf|Y>)`sIQh5ugRkCCYVd4<2GaBH)%UEv=o{4?6 zawo}!BA-)ChewfNfAJWxL>wueB90elif4&b*|EIy#f!yDMRVUlJfHncw@$oXyiMF7 zZW13CpA!EfzAU~f{!@Hk{7n2(4D-H$dN~4$%o20Ow&H;dvs5bW!dia%2}}4(=lRi$lZ`u~anoW2BoZnHpB+nan1&| zlP^?cs@Pa;ChjM;6%Q0UiG?Bu*Rh;FqPd?#Ha5#(iNei&9r7uX$BP`z$o%Js*7k3) zT<@JR9n@ip;HksqZQzeB8R^B2*5ks5BMYa%um+lbVD zGrsORA=cLKSjAggzY`>%Dozm35NC*UMDtug`R2I*UZn79aiw^r7!z+4Zx!zp?-e(R zkBd)Sy1;*H|1;$7l>;wJHN@hR~yB8Snk-EWB> ziaW*6#oeN{<%>X>zCSEJvE^ZX>7atP$wT{TEO1D+C>xpca%yG)>Hz&nsir7eOA~qMJ zV!qf(EEIc*eZ-^1fg%S&v%aySwGEsqdA4|txKzAETqWA|M1CvzCUK*9kNA7>G4U_r z^Wv-GR*@sK*}fVv0!0Jmbg_llTI??N5;>Tg=|_rV#ZvJ!@eJ`Sajv*nyhyATSBe}T z&hl>**NbW9_Ct{8GjTpweD(kVfh?$Z(?403w;vr&Z@i6glu}B;s z4i=9SIc}ZhO%SJu)5NnxYum_y?M!cN8#%I_^3~#P;s%l9+Zq3)$N}z@UlTdPo$^lc zb8)vAh60T7DPpGBMC6co#vdeh7OkyhZ^=iA#o{1wxOk$-Ve~9-idZ35idEtwv07Xy za`Zj(-yq&j;#|H{^1b523g;kwrvHohlK6_aUEC$sh+m1B_zlARO~iI$d$E&PC=L{d ziX+8Q;y7`lNJ9aZf1!ApxLVvG-Yq^R{z-g8d`qOg0n7Whn1mlplvBlQv8lMf*j7AP z>?9s09xl?1f#nSqM~b7w@nV@cU7RV>(t-IGi?nl~yh@~D1La%9yTtp%N5nsfo5klu znm;iAyW%eKQ}HViBX>+X8b>gFGm*v+ln)lWiakU;PR#jce}6(W>G67Fh}(-Hsxh?b zs2gOtQ88caAa)cB#O`9<->*dqA0XEK{W?nFW5rT&l2{>DigUzyVwJc^tQJ>_tHi6s z8^v42_2OOPCh>9c3Gr$1Wzqh=wZA`e86H?S3O3U{zLU*#kFEv&N>cl_neLvC%J4~} zyFqZ>sMPAzHK}WzrPIpqIybXAaj~Da(_0IY(!# zjjV8wO#a~Lq~yz5u6cY{W+=OR`trsrX#qRo{5y*`6eIPT*K6tB}yTV_;DewI7 z>SML86xWo>#F|n=mp;Aw!aS}h_3Nd7+`TyOk4v91A#NY8$ixt?E%olRXp>3)sa=+iYJTig#B~M>cFZ}gWa_))fR}=FUwUvwK}obmhj!K2B=eXie9e?5ynF;g9-#{Fkne ze)>(n1zl4&y1PTW9{Kp!g$Vz+|Hpsn_SmQ2^k2{|bz|=Cq))IY&#uQm{!4epZ`zgN ziQRBL`$uH^VuVyd~qx zZdeHn$LLV^s4t$iYgmoyxBkm2bA&p*8@}S$;^ps#wW8H$?_^*_tHbxYqSe#y9#))s z<(2QY=lis|PCS=7ZI_cyO-DeH2~7M+*wTKDz`fbhQpMrDfkfVc6Yv*iwH$ipy~jW8 zD@{lW)lJ?P4C%RqAzsq$%9CU+ zO8tLQk16z0)sobg*18_GBuV{#MeoVX=G*6bDaM%Ajl6|uSlIp%@gdK<(3hxTPr8>u z3;Y$Xo@DqUV_}OMKKvKC?*YkPGc+)zMQDEZCU_!7V^fv=C#Hb4?FQyLKf5=g;?}kc zCHmI37i6;lTHDT|GGdVobu%LEC@xmotcba#E>YrKV{Ln(q-IW1go&4C7on)QwJnvA z81#g<;g9HhG4vXcJ{2ipZA-tCX6C3mF=W;<3!jFz8iU%CLTr+6P&+Ebwl^{gpwY(f z8`O^VOIyJGliw(tPBGy$sP%p6MwNf6U!M$Wk3)&j@uDGgZeB7J1~8~Cp{El^-j^mYs5Qb`3NWZ0&zQ{=Xi#e; z5AXQKpmqY|@*(BC&k80{98YmwTwFkr=apN=*yR+@qd1wZxq)IMc-+${{t7S0IW^2{ z#H%R|W#aPZ5Xe{Y9P0DjDHK12n464TY1pX7${Eg_53>(?;w?3Yw(Pz*2%^)JCn9U1 zbN>uWM5kF4op?GTo8`iDJw2)LY=(#5Je?LDA!Xu~t3@w(9;RmiJWVs;p<;GAJ!9b6 z2v5tWQ8v}xy|9HQg#Lvl?e{wTt!!Y6ZIIqWQhat};unz9=uanynla&SM76SkCh;M7 zQ=!YHn)_00gLrVwem>9rJQDH#ej2fa$#XX%-96aOil_Yt)1DJgYs5=TS~g<~wsrBe zZ!_)v@w7&K+N9lzbZ=whbW(mB-eKA=;%SYTp2aqNhICYoe;H5v9@8F?Pr5te?hgn2EB)KSnKZRo9EUx=goF= z+)<6F_%sfuwNsy2F7KwW1lsDS(qEqJuuLI%3}J~xV0;O@Clb6_!aQRD$u}M z7>*=yHxoV>U=WM2g`GL`WAym;DWeEpl_s2J@LRF#jLJb#EG}TXflN+6Y%okA_>mps z<{w-@Pd_7INj7>4Pz20c{3Y2aY{6!d(!)xy%MUJ~=XE0>A3gkB9nVL>?;RAxs;xT} z9t`*=coW0^7Lgg)*l9ou1(WTunH8VtVOwCVV%BG~?P7l0Ec9a$TgAFJ}sLkXT&eRi;+PDt*dk8k14@6==BJ{FHa5mn$z;+GJ##_zV$f8V)Ez{q7 zJjZ=^EZ|>6SgDYn8?nLca(;}S0+fr>_dc@{AqDmnio0)t?K1Q+dyMtM%iiG8i|3)h zelaB`I_L!38dDZ3GR{_yBf`q>!G`lZ6r*R8FL*I}p74d_7(JVPArhnK9c<_#Vy7QI zKSs|det0!bPks?b4QXgq4mPAF@=YVL=pjAaQ-t%p)Uic&iB3?bS7xV(mtx+;b!Db}mTYY8^oa0z7_8^|^`kZr8Zb~!vZnrvf;CyjR` z@f3;i-AO#{9>A6ayD6*(M=!5e>>lw1Hk@<|V)Sqy5uP}nV-lz0NxW8(6bX(eIJJ;5 z^QDKUY2a~jEK>4{#F;N*$ZOy48VpAM2QJUB6c*JfYblR z1*|03RCEGS_in~YFTsYi*DaujM+7HI;=qjHf#E)yB=oR++ybsM6}@d^==l&EI+b8W zCI@mGXG;tk&a&u_uvx=f`cVMJ?_sU6k!F>;61z$rpIQ7d5nq(93c@06t(;1;P@G+w zt-|H9ajn}M(_*%YeG#mcmC$v-=J#?zjE^DC1A)_qyT^kGuf353ZT*6|_`u}T3eOhv z@ZMK?o~JxaIO?o{jf1zoT)bQH(Hz3-husJI*>1XHv9ay`4YwJ+OR?d|6`)Yo5pvF% zZ%bAxBrvWD1^YLuk%?xE48|@+iomJK4D4#$Hr)8_fp?z=u7E-Rd1b(ViFV<6Vp|`+Hrmj|s5nOjLI*zQn42IY_`8UMnm^yE4R+CEliQFW6^K z$$)inB8cNWjVs1q9s{Hzc$MJVEg^Y2;igkU@^~=Z9+yC&_JHE73zRT2P=YxzRYLsC zL~_#r{IM5EpitXVvvyzNdWs)HUQa`?Aq&BC!ar5A5*NX6dx|K=R>!F?{FtrPqzx8uEE4h}Bu8OOar{FTqfm;i z1@0KBpV2D0FrP1AS;_7ELmOjkMKBA6Dr^ObiqpRNX1{uK&ve?**7=hI*}@oe@ydwT zZrdBYKbU?&B8HWKBTa_1Zx+mSTE{4i#n!?>fWHf~{8cVf|A}haw~jHEU2`x~>|vkk zWMT4hY)3FlyfgQ>Pw^Dor#7};7BCfCieGQ*7==054oEb${+vw219@!2s;||h^_RG( zZspm-ZnbAoAL%=6C^{hdnzWM&HYR9)j8Z2%DUt)a?Wcy%YuV zF;maoyZIg-l=0oT2l;rz#tVh5p+Pr!n|KTI@?IXu-=O=y&Hpy?zE?YcgB}ewKVSCv zo)@T}#eI$KKYwc2O7c+wUzG!Q-W-SxexS5QK}ZkhnZNwQmnG}?K9P^D1GYo3@qW?| z+W>65byZ^HB{vUS6*hZr+Wcg&yxURPPtYpet_K=e?-L#IA6TWo=(v5_hO?tIOBdSa z!5TSS(HVc+=7-Cpw3o(up|DJ!+=qYD2EjJH%K^+48482+{ljO&ETC?rVd#D+%+SMU!{9xwPxzc@Vb`wvx61FjKkT5d2-6(>{dv*W5Uvc%!6QgTv?aL7B%4J_^Cl&!b88ZKkN_O%mV# z(!9Ksb@ub6fFi&$Dy>;IA| zx4%m2z74t)i?24+w7Vguz~+4a+59`&Y4YTXP7`NLuber4V&#!DCQo*Z`L|iTww852 z4i_d3m|IqPPDPn-k1wNeYXt5ujTxG>$UYR#Y6HxwDrbe_|Y$@`hUsRJNV9G-;9pIVZtj;+zr9;JR~_T#^d@U z2p@UluH<0HDZ;0uW(eUIC6*V##^39~@;H8#?@`uSZ&{smAEn{#JIkg@lrbJb!FsDZ z;|mnhv0m0^>#c;}mJP471sxxyN6yAoKn|97^-=y8EtZES#LK%7ewzngXD7;w|Evha zT>yWuy!9xr3SlfS9h+?*?Y)BK72zdyqyLhMm_!`y!-C}%{GwsD-XG!X$U+=D>sS}J z^0V(ZO&Mm@IP^(?CD+j`@k z4gD036)sMm|FnJOF(#XeElG^cIFLl5jtcK4_7$n}V?N$fNDj{;dG8=k7ta>wi5H2N zidTwPi?@jz#fQWv#OKA=#rMU}#D9w(&Of$;17ApfKq8xqd14oFkT_bTLWt=Xiz~%z z#YeVwzx1@&f((G;>qF^v4X_Sx>B4&;)1zY{56SkjLkQ~*Gj%o@wZ97 zSMr0B`8k#47~4YRH#Xmp&6pU-)LAm#tRo274DW(mqx>P9V~o!d+la>I8{x)Q5c!PF zH{>G5Lms4bW}QIDqa}0Rf5vkLI+lC3xJWcMfe1IYfZ(kPH#Xmpe@_|tjmcPE zrQ@uyOlNKRJouSEmBfZg@eMH@y$QFrdwB})NMiqbDE4(z2rYjwzhiDQ^xkH;?4Sd zNY9ab%x~7;gKTZ}zEOH(vxoQ$+$dRo6B6?Nl5u-6<)T{+&3zPk`Fvx2EkvW|g4{`R zq1a38BlZ{huE+et#Npx?@lGsS(`xL>YxSBUFGYJyqc?IH&NQhr!`RD4q0EOOZlru&=7(W{iVi=T>L zh5dW^^55$ke&%|#;jvi)t9O*-5 zh)u)O2cRyaqVvz%kZ!6L`TGJKRcPBa6c5k6D$St7^bGQG8ZzeIAixLRBz zUN7D(-YMQIJ}H{#9?Jczh_ieHE!Jr9z_#$vYELToLXxld3}C&^~+6UeLQky8M({oBO4>)e{>C*mX6m@ZpvDz+A*Vy!t<5N4jEU~k3u7mpE3#F663;yAHf zoGQ)|?Q@mm*4eI0#FgSI@oMopv91lgd7dKfF~!%lf&Z(*|1O&6Dg6JE{F%r>$!v$q z=O&mWn&&Fy9Lf8MZNvjbYYYEf*R|zRI;_vy!jG3+CQcPA#B;>+#6{v#afSFBajm#c zwCmg6A^9Hh0r3&>58~6JUH|s4lK(EgExsqxw1E4wTco`#*7Df_r;x}wT-8p2=hn8EHPK4mx)uw3X!%ajK4sn@d@S2MOvRwzD0am+#>E0KNXun(Z}@riARXP5KF~LBF$Nt zewlc+c%4|UZ8_3Es`w|x&0<{}^M5G(9g!9>tnUla!EZLoo|rCXi7mv|V!qfxq!kVG zA0g6=hVn3xmNS&6i?hXZ#6{v#@z>%Ckp?%+f3s+8(s6CvBl!XG5fb6F%VGNG#J`Ky zR{b5x+r%%$uSHt&Fn<%Vm3V;IQ7jOLiNnQl;zV(^xJJBLyj`Th5bJwXd{VTw<$ss_ zhWKyM#cw+1D-gSjv&D17CE~^69pas$o8gy}B+_n)<+c>tiU*3l#6IE}@l=uKPRu`3 zoGZ>3mxvdO%f-vZwcGvbTl-$a^HG5?1m?WZVzBc{SKiE?8x zS8O5Dx{C3gMOsr)?km!qitS!_ z36j=PP8fgf__xMC^xn?%S=j0PT}O}Oxzt6t{qW~RKZK!ihb4ab8xucokfHSv{Od-H zwmFn^1S8h)mv#G*j0mM%1%!%^ghBYmNy?xtNF~g%ANlXb#`?w3@J& z@&`y^{)P`9!XptL%G^B$(z}bHeNU!$IYawRV>w<5f7vH_Xw-G4K<`G#ut2V0Y{cX5 z<>a&A_ZGPufE4dT{EbAt;_UfIn9ASn-mzMo*Gb)v;=t@0X3q0c`D@%8Br%ePY4W|n z*(?B-#;JFJ-jHmgVb9A-eE`LILzOl+l?o|um=d>0!`iLhagtg)$y8f=CE3*8G;;B% zb6id;2=y-iz_}dol@4>>W9f+^q%m9S4!j=TAr#p(cMuzT4n;QH9ZZp${d6u|JA@5= zgOOBjxI-U=_Zy0AxI2vPJ^+o(~OA%8hCcXvi(oTDy6urH2V@9-yQV(+mPGiRJObNsaEDA-lv8PR+9j!F$6JYpE)GjnI7V8n1)df6he)U!lM#f({%{#d5}uNNzsRyJ)`StS+&*~>t}!0@klN8%*e(`q+%*$*T! zgV$=0dNZBR+=+!sw4zC!139Y_>vWWvl|}r+!%Wj>Pa8SDVpd`uoA0wSPK8$AVM9#| z<83l4r5H(r^McF#{CHL*!Q-aZdL+C#T2};5zl;`(k{2f}@h%K64PA|Ez~`FEBd{UEhg=pQ}_@US53~Glp&a|eG~8HU2{zjXc=7m$PQx}n5H|$=V0mAmy!()m z<*^TJd1C{4;C23ivN*=WI_sT|0PAPmC)n{{1Olx0bi@Vgy(RIf>zHT~t%RtuJuXrfG9kw(yll6o! zD313WjsxK{EQDWzJda2-UJhjcbDSK1a&VkTN5%8!HPam>9xVP%FWKmmAP<*3UR)qvBCa5D zulbF5C5db7HgO|~a%d69a5H`m@>7zxDE<}6?}=ud1k!yj`75PM#zo3<8j+~i%W5&MSa4#}DK=L^&$vi-(F`#2#XAafnzVn&XFZPL@1TJWV`Dihng0K=ZS}kW_%>V z&2@m=h3!8SXVTmL9jf%a!b3=8ezzlEm%_sfdPWnjuzO))kFMRj_1v@GvAdso-+D*R z%L}&$y`yuqd!(;-JY9OnhrVc0k%8K){rUU62(EdBWd*oC!(!E#W0y%?Q5T#C4A=7!gS_ zXLTfn3uPp9j~r4I{)m5k-Q$<^9@Y;z!W`uj?lF?y-_UDykJMor-QywfK-;(hS)h9? zGqw1-N4CgY;9d_%_t?Ul@9Q2phRCbZRE17z9>w$Hx<`&k^%mCBJzfykJ>JJs7fJV+ zk@^_w^%g5_R_Y;)U82OfM)!E3q-IX?8H`;j-6Q-^G9tU<4B#KQxbAUaT=&S9x`Q?# zlGkZtHqBQy@-l49hPy**;N?|ibdN(ngzpVTwq)e62jTsOA{*`=7uP*@fSAxd7B)!t zI0z*sb*ZI$j9~|U);$hv^8Iv=Jn(zbJ@OF?-6O%2d(}Pi=MQy{q)pr)-J>!_f*EV; z9vK7OBjLB`MBAczbdQXp?$IW}?ja=M6z>J%y+o{DE1YGKKs;{FzH1HO6ogA;;l2i4 zQ2r_F9<8195376pOD)}FX)WDjGIWpiytBeKBcYKD*vR^;AU9amX!gf9#Z4G+2K22~ zi-qdqy0e6qDIP@K*3U}F|Be#Uta;o}C8Rkvd(k)6{t1Jl`ok(9|NquK@+SCS(>>x? z{MZd-|1aqtgAXiEPqL06^)S}$#P1INKA{eaX}IyJSc1*GL4tI1ur);Y$RGO+(LKI{ zr)^H40_&ZQdaR%I)<9v@5Z&W_P>VD~_t+D^uc9ni&ep}3-eA8(@T1K33x6`%eyN7v z=3x;hp**Iu&c!dK^;EJm|zq z#1q5`;uMkhE2jHd_lSPLHTtve5&eLB_>Wlk*zLQFdFVbvhWB-^qOEoQhE`Qq+c>Dl5z%+&@7$` zDf~G9^q@i^+>^Qc85Osef?;L84)I!ephM(Tnb0BfW(8>=k|uLVqj#xG?OKYr34bFk zyqxUr2u-EF-^6PQc|vy zJf2zi%jPq<5eH#gEg|=l&ZWAPBNPYH!&k+|Y>PXHO<^xJX65c+Hsx%J*q|k(xE`CY zCENtxW^5U&nRQq-yrE@IW_$1jgk)(%VirdvX2nM&a>ujX-psNNDP1>*$YCux)GQ+C z$2#6HF#He~KxSh2VOC)HVRqd?g*kyih3Isg?B|&ip05P(bFigj&d)jn4E;faB?O}b za}Gi>pBgcwkm{}jvDqPoO!@60g)I<@A%z5sv*H;n~}B1TO3}3@p@39C6$<8cR$d$J$Ba5x--AGaUV2}pOvU1 zf&Rj{?xKZFSAYQe&G7)4F8E-vx{Hno5B}nw2VH~J!7vTC`gCVg5zcSW)>-cm1O&@l zg!0M}*&N|)i!E;~{5B7~4(FfvoE|wF$KRsX&!`iy<6kNbVdGARKUl9Be~3ud%WzvS zKd;$5@H)pKB1(^(jjO9W`wGgNETmz1d()lGKzU4Ooh|PY1O(fco|7nVZ@M$ihcMa} zf-`hezvk@ zF#NxvJG1qWKPFun?=AJ|%IY!n@SmuA8kfhLzI0>lP-YqiTk^i~pUhR)oB45({X*nD zit-3?lvpP6-p2S@;`!ndahb?#km+s^Zx`?rb{!SJ5q5u(vSAbgl)qi=*fTJm_YOgvjOdPk&NDB1Ko7vB-LiRQe6_QCEyf=xc&yO_TR`wirMs`fh9haXn&ST_Xv ziY5QAwXr?CTTiK{_C3~3LucdqrWP213LD$ZCF`#&4p)cQI7_|i7i+w#7i%J$F54a+ zblG-q%!}KT=4M>wE_ZfS6}i14A5_tddKDJ_*;!NNt$Abnd4ry*$*sC0a)i6E*jp9( zAe=gJKxjpAapV1+o#F7+#m?#zYP^npYrI2G+i}C(rrX`Q&a%UHoHpj59Vv6)*gk!3 z&mBo)oG#AJ%~gfP6N-BkFWc@MvV6PK``PX8>CbI<4|#TbsQ2>iq0^t;9v-uNdw6cU z9pT=ScdR>o){cYb=IvN=`dK?}IQ_sK7tTFvNBg;MFLzg#dp2T1yRt%mdp5LcVDX3z z`xWo{&^>+qhwj|=NayxG8-G82*1h5bglxptbH{0OXYa_Ld)f}~ba(lU2>Byg$~K)} zmA)&>DJ)Lk<%RkbyI4s(%V7;HJ$t)1w`69gA%liTghvadnN$Im{n%S}t# z(Y_sV@p?-Usd`-`KzVw;oO7puB`B`XS=yA2CN#;6vrxQ%P1VBB5dvvUp$+<9%C6Z zD~=goTu^-HyQL^)^t(mH;VYhb*Wo2$9>@mC5Irc?r=p0W$SeV~8<2uJKjEE$evAvO$OA(dOIgVm6natwr97ob? zb&h{xDQ@IFBI5NTJdgT7NRyE;iI*NUj=b`dy@&BPg&N1MNEqP=;e^JK??w(Zj!yzy zn|TOwL*wX+W^HD#c{U5++RV5&Qsd~0SzLYDYbhz$N#ay!&^T^EqBNKHQ1>?c!RrIU z>0Fw9H-g6Tc6xY|OwVKR9juJ+mFe4=X+6b1QRJL)?gokz;7e}G*pA@LiaCyZA0Mwm-s zk_66yl!@hyA7(PDb2HJSzBG^$7dtj_vw3KfJs!UAuNn>7U?*D}?3ADlHjZ!52Ad|? z0UPYJJ=$P5s%?W!lk9*EcH{1~#EgKLhMk1SN@TE|6%Y|?oO!Is%-TG9ob#e2&nsw0 z`GysD8Sug6nmEdMPaxWul*>kvJXw%yB-v5nBufjd41-)wDK;ojiAro(WOQDPo{c;Y zoD+ym*i5)B4&jN?jz{9SD}@glR^n@H7~MF;&=fX21Y}`jFxdfH*qJ#mMh~YZz#?)( zlDoH#(Xag(64;+1Y(RT#CKEl{xglf$Hq=e{y|!!!nh{nu+NeaVNVC{0uv^7rG#x^AD}3LooI8=&*AQ-IC|I;8);j`;;du+yy>CQ1mE6~ z*Nf5fxGzLv^gQhg=`nivGKpkaF?!y^hAWBq%nzRzqo)O0j&OpD8KDL~1TQz<65_&K=_QSbD>O>S_+*bVk5F2)v@asUXL>(n8zrZi8B1R9t)1m0n7(L~_FeygQ z9A7Ap(X-SSrpDN^o3Ww2sKPkD@OQ+9Y6+c)qXH+QIhS=J#*gzNr1d-WB!aKsD1mqh z8`|W?w!-r^He8j&N5(sx@b_(|8%uQBN!+)NrfDMyzsZ%ZY4UOtK7zQ~c!v`=V#8_f z#uDeui9G#zZes_D&rFgt7sTk{`GjyH4O@~ko9mv^n{Hx85Y4b*ZQ%tmdi=9*MB-qb zgvJ}k)4UWLZVVoIyQy;w!81GT%ynalY-4z+IYSA$h^Tv2+s;fj&uG76A2+2}A4fjz z`-hTgC>~#+jw5;V3E}R>%Yjwc{77aTk8LS78=j2x>}TX3#?~<({mjcY*>ol|{?yHH z@AV2lz~ zT?)hLox6mmcMdn}98Q}Y?ma4e1D45Z_cm4!JJer2tV`jcJ*EsEJouO{oeJ>p;C|t` zgWBU89~S01G@KD_-SxPm+jd1MpI$SxFg&;Ol*Qr7h2h3g{C;r5X-suY_*$&q^{z8H zyc$LC#zgb8xq4S#cvdvrxbqM!#C32uv-+rG!`q$C;Xlqt;r+Q#SGc@0R8g+|e&`Rb z*H^^Ex2lSxXU=rYVoMXIp3&ca1FQY{%Y4qN74-l0XG1N@r3oy28;5!pk*d`p4fsaq zpK*Km#OQzI?LT`ajzF#Naa1yz1+g0T5fZCQO_m)*@cUz6c9QrsCI6do_qBE=z9ts; z>c{kPF&#J0;I~EIyRGBBwB9wV_%rCcd|&+boFMF`ANyxTtmMfz1wM{_$Cr(uvyY~> z2xPjjBI~AO9Nj_Ks3X}|x{gRwx8C4$&psWGQ98i53N&c7Z4^Rmz5U_mw;1a>wnRIS zt{DQLZHRyW;m<9bhiOw0xq}`#8&?L|`Wf{((p^Kff}D*T4>?$GcXVh00$4Bmf%`%7 z9l_>-*I5PiN0c5p8&?52Sl%R@%vlIydHjKI%exSMn+IO!K9t9F*4elV5D+Y{GEg3` z8(ZFL_-!7R@dV1-8VIo7%MceVZxPDl{;_=-*lc;fg`ar}u+iO!?_#U!95=?V#}-Ui zlvDrr!uyd9=Trq?+y3@3+p@O9pn&+0@)I-wT0wc`ToG2Fv4w4~HVmI$NHVEra1d#P`BnTd<*L zzDIYD?||(kKT+6RL5U1uENdNf-yVB!RZ%uS&$NUKn=>USXPNrhKfdD;NVxB^h86E2 z-(JJYf4bN6sn9&?jFJoohOOjybslrFsfa^V@0=Xn6yIAk-vyCxh~yC>f5@^t-c!h_ z;w>%4Ue14(u{^B6ftYwFECrLh8oFtZuXNt4M z`Qk$Hm*THQeq>~O)`>TXb`77qCEqVTBK|?-S4rmoo48ecTl_%$muT0#`$}>cd6_>& z%n)IoV8UC82Z-&(L&QSyF!3m{pEyt)DvlJ*nt1S!ms}=J6)VKE#dAfoHXi(TO`l&Y ze1*7HTqoWn-X`87nzi!ae?;;hM1Iy~e{gIdxmA2yth=^Pjl#bY!*~&6z7(|gzH&l6Pv&1QX)Fo~k7u{^nr1>$`Vf(%Hy9R4 z;Tv;eNXum`F@stBAuXFJ_bow=@Cb(Xo8Xth_YE^E*XQtHM9Ub$^V*rBy)qVt%-eB1C|&#Go>Yf<+`)<2BsrE=OSZ>vP#qVCNs^MVMAy75Tl z{UhsolQzpqz8~dzZ)d#+xsl6XQSKmw;5!iiz`1Whqz&C*dZGwv%-Y={to$g7W|pg= ztel8 zj>i#Sy7@aO?wY}ePmKhl>)6yWDL+^P2VkR39m$m6wyEQN0;4Vn7Dt;pQW+z`jJ0j* z7=tgrHUU11Bfz-&KDV**pbN_8Cx-JA`rKycF#V5Aaz&?!Gp1M096z!0$QhF-+p+9{Z$;n! z1h)6@T(-k;sB3*4+rvk%#Bs8dd|}Z7e70)Xr1!??ZZ8u}{cpZ+{dm4&QP&jwhQ%9~ zb-Y3K&1i8!@}i{0-jeWz|M{Hu_Eh-!`<3luyb&085dQLe27VeF*Il%*=?V})Ki`4r zn2!2D>-Y{#$1wku)QHXidw|>ug*l0)pkO#Oor8H03n{ZF#?h-{yhW*x50ibvEuo1O&^wE>Ip{BW-zW;J0~L z#yCV!pJ<)+u0}wxyt`1IJ#OgoczHL$&pZX#=r-W@&Utl?8{_Z77EIR}g`LR^a*X5l z5H=iw3I#hcq&wUSAk)x2i_Q8ezl?OY4V1aRbkAT5?#F|He#u3g?H2^c&v|&w`k&PQ zT4(Db1H0#JLFX1BkZ*YS)Mm=#@nN0z8iLo!LZ@}5N6waKWy@grf8#rst%v+y*v0Ys zV1M|IJ)Uq4nZJHNBxj%S8NlyahbFT7tzk+54HPm+QS`>HqxHV zeAfUcO6Ez;@UzAF;w9oT(R{~1x*H_(+F?Fk8|35SQ=<89f$+ad{z!DuaZJzgf@CN0 zNRdBI8Gby8>-GeZcCxgCj`AeB{KXITqR6Ic(EuJCH5YH0liVMXh;-%tp@jCHF z@ea{^heSL0+~HcUw*3%I`|SSJ(gWc>z(;A&v`NEj>_T4N1=B z?iDv4;8tM{_o_&&O|d_xJGDWRORuX*uR6$IIr7{3AZl;+tq=0mJ_nj3R7*89lKUP? zF`ojZ54xDAMT7N0MhSFSPZT575RZO?^g$h1b;Q>PwSynCv{wUheb8?M`k))Ks49x< zgKn&?54x$AKIrD!`k-6t=!0(kwm!%{2==HCV&y!`e<*!Wdz6*X2NmZ3tPg6!59!}W zA7n0SSUZqBj&=1xQG`JsL@>IJK8WWX^g+ad*z6ojO!;knP#cqYI1$B0eGsXPW{xGB zv9>;lDKy8D--f;FgP0`fg7QFKn?F5$(D$3h9JkvLJ2DJ?kXb9SPX|nu)Mog}d4<8b zk`l9#*M4`wq?N&$#^XAQhR>JuQ(x4uA^IP4XzLp`y_YGL635A^f^e*mzF||3|Evmf z`H3j0Kjxh(o6~7%cPF`V%FxtMT5^t;>o#?phg-NU-TmBF;nr@O5C+HaeQ-~@Al{sQ z*g3}i-v>CLKaXWb-_qfpZ`?uni=Wl;-?82O;P_vgt^gtQ^F5f3>4ItbsHCf_3py6> z!YrS^5t)V?<-yo&+3-5$*cze>DnWS-(FM)GUAiHYe_i)uRzVqoBKN5a;&>9Kv(A=RR~K|+pgjCci?^??F6cCrH`Eq_ zbkpcek;P3bDD6bTeERVV;TOMBs zZ60`?Bk_LrIX!YVZVF`UXH<9Sd%jc}!p4=sAFOv}7T>q_t?%iK21QwroGq`ez9%?V zrxDWH{rDyPHV=!S9TBRII~!M5-@~ywOvirVyQD3zuD<6~L~y{bb=F%~-}5-iv&Rix z9xv}E_?d@q8FaVecO6IDTgNzVcZoJ#HVQk_CQ=;J)z$YbM7oCPdmco(?t${SzjV)F z3m&(p1O2i$ea}vm*ARUV=Nu?P!}q1{smVzE7GS%$ul2cL_|N*D@2cXC(A*Klo%b{a^ zycWrHk@qFaR`0=azLYzPyhl*(DIOsjeHy}tNv=D_XS~A8#Iwb7#f75jZ{b6_v$9N1SmOJAt*s=aD|zU$02FVsY;R$}hyjH^;VsB*3> z#_*X=&d%4Wyj7U@y8431es1aqq4a(OLd%aU#*Eh?=dx>x-K&nT@fr=l_Qv+fbKR8~ zz_;^}sy@X<#rqep-0t+Q-tG)~0rOjL+3xm!VS8v$HRg(b0d-VkUg*3X-k`}lu06dH zvsmZXo!|OMZ&#Mb`K>tqKY;CQ%x?WY zc-oG|bDcxyZi(#5O6pS_+2uKH*p|5`Z1?<`rjO!G(@BU;!c5jHF+25^?G9SRR{Aqp zvu@62&AJ`TXq}5$tL==|4qBcYn9&+@2y;g3tICSAipOkV+g`9UTK8f-*CFKNXPq_f zktw^p6wI%k?p(IulZkg^uEKoQI11?N)Y5YAsxr)E-DJz42F+ru4fkO0mVla z-~aB>#eIq=zk6))bN(FGj#&rKoDQCQ4rp|HU*lq~>!91?GakCV8NAd(NiPH8ZS-5+ z-elx~ZjWa7VRQfJHNk|Wj3gpS_b_oJh2y>wy1nyQ%%}Y08~Yu@+*Y@D8*{i3j{Slz z?-auG4mG8D)HEg)!e4v-YHIeHB4Oko_><7=;n5E9tgI)Q8S_^kP4R4r{`}Q*vK}^( z=}r=7(tu`f3*&C=DwQo4*jLR^$}b_t3+8SUNv=`Ey54r}#Wl`jba*pjd=I z?)|Jh4H4jBQ-^8pqV7YC{e&W$>OM@7lZ`jNhKYYq@lJ>toTPda zC9dp}!AYu(#5IyLX*c+Y*{SM5joBaWqt!^sHC7s*Nbxa>S5h1bk1x_1I>Ss${W!C} zK@rnZ8=)s|XBn85+6Wg=z_iqVV6w+}qf7Q^pJ}@P`&$zJADVyKS`=d6g7Z(OVISK& z1Djxv>CB@}Bg5DWP$5Q1o-FY9VjAl*;K3*{qP_8sB(|EA%SMtsOvp8o^h;RA%O~zQ zqzfa-h$jNLgpAjz`@5uzqGxI~!v(*%Ea-v|&51lCZ!ZPT7{FHmn{XGZ(YbDStVe!@|<{g_kQ#mg)0wy;wu$xzQKWWAxna3t2IG9><20gy5T+X$3v+`Qb#3@t!mm4dBBH6S5QK z*vv%jXTigP?+E9jV8IB~zmEy18izA4ev7xoZMr_ze z*UZel$%GFlHXE;*VA|gyOfa43sS(_vWYeA#3BR3Zxu%_^CVV(C-FQogv#^v-Sxm2z1L%d!7{PYc#kLU!-iYhf*3tKy>ROyp2nuhr0LykVnz@zV>6RU)3d`5 zM?;O{sqSB?ClFPLMQ<6hMS(-hU}moIgZ=D|Qwk3|&raG*|JB$y3o?15?;lET_5H_@ zZyW!)^LQ1oSeqZg#_>3^MK*jZ{OoC#OR}p&xaRFuMZayH&4VPy)h+8~gz|nK!o8gI z+cI}fL-Vu#RcJHYlBmD>xIN`>ZR)}w$KxO4*o{FKlsB8Q58&UQ#>~#Xf&%;dJwGY^ z&P?jus#`cM8cyvKo)RrQIGhy?S9Ipz)M&VTP`Jgd;qqv>6~s}T-Z>+>$ElsuqFo1b zcId?u^QM@Yov#Vb>}=+LJ|=uCW_Er9(>7nTU{H96v$k+dVm9YD5&T!q<~+D_hwzNf z_{r`2Kw+eBOgedvG4-hJE4sFVEO) zwHvjjUT*kzE}NYiJ~K=BkLSZzI&O=>G0wbuTgSWP4?kx!JLyON$?N~re9gh9nSJK< z!$HL1i#yIyNDYN`HjY2Kg5M^#;A0Knftw*5zqHLWGy)F8X7j-7EJj7|&?9H#N+DZ6 zqs~Af#t4rBoQ)d`f3V(7En(k@idZk}<9?7cu-QEDI@58&M(L5Wac4jdmRHcu|MtZ4 z@cTGk-a`0o9(bKgQC=23ayD*0xRj`ibq03NnTif6LLk2x+VZe# zrp{n_w<1B?dddp~8EZXsUh<< zH$_r5pZAbj^ELbLN3}m=@zxDTWfH&H@H*gpzdY6?%OY_p|ET9_Zic?#e&mUVkhqU^ z7Q2$TsSFT}aU#->kUWZnJVEkllFdj^%6hICYF)HSZoy0=1m)J+- zs9xqb=N(ugd89}kKI6@K2bvEgp!sGBn)wsJ`ATQbKgbtJUM^lPt`Vu}XSp|vw~PE1 z!Ep1<6{LcMGBqRQ3!*tcA#auZwrI{%gx5&^Ml|Ou!ns@*%i$D^WK*%F*iPj5XU2CC zyNPxl<|4@hMSd$``jO%&ahy0&oGMm`XN%{Gd_J?BC8Ak_74mAySBuw){7%C3_lggT zkBU!174dcPpW^!>zfG~d zb{^(1ZgiAW#4ORy!`w>p0b&QSqj;EjxY$oD7LOB0h-1Z4k>A5u|19xbae;WDXy;+( z2Q#LRiPwuaiyK5c5A(y49~J*BJ|n&$zAU~e{!{!=+$nx8?iM|?h3$!mnEleon9kC0 zKe3H?ka(!rL+mZ~6^|B&h$Z4^@f2~AST4>I?L5r$B`*|zDcX6M_cj0W-AaGIxJi6m zd|KQh@{=X|<1O)D;>Y4{@f*?3yW9vbTFlo(Y%U%k=860Y%5+DF$B2W)5#mYWIB}wQ zhB!myhg6n#p}0c)jTjTJ6>kym5FZo&Bt9?xReVEyOZ-6mmk8kVdgA>8qG=CKFT;*{ zKIBryONf2{=+d>ITTe6Q#Q(FeF)D@Kd-U=LsqA}vvgqj!7HN6J5)Da#<3++&hOvmibxo1c(+^8%x$--?ecE>w;WLA9DHTo<@+yd zU)_2|o3%|>y@Zi02dpls@lNJC-x#5CL{pTucz4MCr2LPW#oPKOH@kdu^X8W~TUGVt zwO=gUotpP-X5Vf7lV5J$;_{Z&gNl#a_WrEG;`6^;{Ats*ZC4f7cw^g^d);$aF5d0l z!u8nBB82j9N|f*X zt+`j7v@BG-@XMti7nC1Ulhx<+a*V;La;lm0(ae6^`i7F1J69yHdUSXAmZzGhtYH2r z<>#Y?TQZBb^><%x9$A)JeLnKfET35FEa#Y=n@zob?lk01Q|?A4_f55Or!Q-4a&IiZ z*5ppF+7`&2f!rC&ooRBvUn_TZb=I=1!~Fh<6jyz@bl1-EH%lMf<)){gA2y+PIC3U= zS61?ZPtLj{Z*}h4*U(4%$1(;i9gur@yH!qy-dmn|-?`II)Xe|wv?73CdPAAIGd z5$A&oye3=PnXx)e%l9umq5PE6%gWc3zF7X+w^p2QJ)pxCIcClIk%7@VhiJ|Dp2f4? zjTArs?nS&uIdq=81b^MfARUga!UQJ%U|`LSxK6`f5-kKmUdolcYTabBXoVZ$4@nH# zp*g*mjX&Y`=50TeG7b?Qe@TXWvPg{IIg4q|Wm&xznvj%Zn1*k;;h`%T5=r7u9u>Z2raaGtJE;dCHZ)7w z`0DLvn-$3B`~7UQ{cP#(fvDOoMtThEftSubA4j(_h7lb@PbY+A{D!HH<=*huSH>Ks z8c6XyihN^t2eEzpO_IqZ?htm*g%mjez!yKFNY#li@&!Ee_snY&^L;mK{KSbE#`GD| zaQTkRA|@Wjl0Tt1jfss|f}@yKF{cnSkh2+$&`^k7B|d7zGbF9TlO(I+EJ;IBP!Nxn zTf%ZbrpTk^9?ydM!kf8-)tEKS+d{vQ&B3R|NI~b$;_GtG90dIWaZRSe!v~PlbP;?T z5d>u(kJ=J=F2Ux`K9L#jKoAXIbNDO%D|njQ1Wmb)%>nqGjf|}6NqDv}<5DhAVrm+S z*c{fh9G>PjfvNGg2vLn&;duv}d+`&t#`~C&HU66!Z30tcRwE?!_l^7Aff+CVx2>@Y zVoi-F!jsELQ`;1i$?RV{WNMGiUB&fA%>K<|Cf0T>Jk4zaQ`aBq(BSzdeH) z*^_TFBlj5D*ZQB}71w9RaZ< zKrkpvNWvmU5)=_FY5nj zioQP2=WSo-laufHpXGnfoS8W@_ssdv(Z1y(aweR6_Z_yhbi|s{Ccx9wCNQNHn2e@0 z{M(*1r#G2Cn$c#3DDe(=Hu^G>n2r_kG#^+3FA2Jh5Yl88arZ&=) z)*B(%5<^#_gy!sezI#qv2PZlCjN~9r?U1IiC3Bis!uOxkmhJ}Y_Dw!L;iQyd4I{}e zl+?yI?KvSWff|#u950?iiuWCR#3i4UQr~Uh4oJLdPzv+ZQ6AJHkcj@n_gQ?1oYTfa z6q^dsH{-2-Yd5puSa(9=q~yt_0yspOMh$*fWI}nPWJKbaW+}J{Gq8A@p(z$afQSc1 ze+(M)1SZe1iwruKvVVFTfP_9yA_A_OrPmYPQ{_&Re|Yfs{wO0I+M8;*LXOD+G49! zmc<2}jA$Xa9S$j}k?P>3MyiANb>LW4b_b{e*aV>OV>R4Hn9`g|4jJ7&)DQqsYhXIO^ z*KFJu?~EEvY{#y+&QyXU_d%?O7iG(F7g6Q_G7H*qrV!j)Gb`>ccs&i^AkeI2_(BWr^*>^n2&nB*N

m6*`9 zC?)UwC^hw_pUsLx4n4>cujY6ZZMG)(-vth*KB2qSB;Va?lFfxnbP_M}kKmA;_ymr@ zMiu@wgX<25+d09rQO7Ct?Pn&tn%J31f!Dk_GvgQkcwYS5On6Z!O3wqH5RTHr{s0ra zQ=;@d=?SS(dc2NdEb$f`jtKEKoH-)&aDNeQcQxoNDvfeqxr4sR`fN?FCmKy{Oz!J5 zc*slO8evlH=NX@OE;9eyjQYHDr_WD|GKSY&3&nb;Z(<@-+BA&69Pau%tj^NCC%T`X0w+zcG(}~73DSg(R&y#N`)L9?N{;<1mDd3y%1}g zKEXUHoB}T&6>JW6?+lCWL#W1mU@|>S*_^gV^6dkIJY@?#H8t0g$ui)4wXF8!vJ`1kjWuR6JxSV}zQ;g+kf&^+r>5o_Gv_=wUyZ9hRH?>cUyYa8 zLU^Ox1Q)Au%273D)E0kq=~2;sEqaKxK@`2NKXw|$l`Ztt)VxDXwhPX;L&td>v}GMa z>e}cl8sRt1u^j_r*ughbthuEewHu60him2C_)Xlgsr;oSBDL@2qR6{}FDL?$I-B7F z#4X0?ta*Q#k~P4uB3ltXdD{{hJitpqu%y^yuT9em9)x4VXoNQQu6E0TXDHlgxbbj& zis60bLb%u!2S0~wLU1W?sc?210RJGk;cz_V?8ae`a=2A+Jm&t*U;ZPgOTg)k6elOYGKj*3ySjQMrO^PlV2P;c}eeHou^(fZ(*cl{`@(`5zLZ} zE-u!v_UGwv%&z?HlQ#W;P-i(6T^L}i#Sgf^Z z?zGvni>A%VD=C>hBY)b09+~MFd4%QT{G$A6GvQH*f4SsYf+$$m#^dRm*4GJ}gs z5cIA|y#c9fGsT-G^=6ZLmq~q}KlPtY>R;Q`&zaN@n$*7!K8~=XYjJJ%Yt7!5wM?_9;|RD zwd~lk#|Sh3Keb}S(BK=mio=-mkE7BnYZ|8Qk1NS5$#*W8v9PGfi7$3HZQ7WD+1cN+ z#NBbH`Olh{zof+RzN>W97n^38A_}vMQRt$<^YdrTDt68~XF_Cf1m|{omN~mKPV3$? za&l4rocz4v{LYc{296!s&0Ydsv!?a#I=v`w-i(4sQU0RY#aM7I(mk_BX4YxvN4n0P zQMj-_PDy^LdTtivl7fYEr-QQ)KC5t1R@dUft}`=xF=WpCyppcCcKR3O70rxvyVXCA=FRU~Tv9Z929nH~omV`2-USGpwQ!zU;m*I(-FK~gXIj%V@^MW8 z{1f{NFH)l%)oRDF2*Ah0(8@*m#S7<@I1769z>&lu8#iIl4_@ic_vtN8}JLwEaujv5)WNTpW`S$jI5&}5jhWnY> zvP27;t_uR_PgDfc`JWl=lgx0XQ!?jdD82?SDePwT@fpXwCsRaaN5|O-CHxW2}|5T?p^Grh0Elm@TGbCj9<#C!K;H5lF{!S)MJI?})8#c%5AQ zo{!L@&Bhf&_Ul{K8_!}0qdrt2rtfO_Z60`?a_B3kN1KgX3E8i&68g3vjQV)(*!pdN z-{yfAFD}r2=Apw#vA9Zzetkpxc>76xY#ys`GyK$-0mp4;OUL+ zHFyN+aOh)?s}a1KM$xg&)_oU3te=rnkq)~Y+gLwt&%^omV>FbdB8>ad5YFyLefaIU z46k!N^zETXn=Om!TT}U6yXivsE_(treEJooTr%xvzygtWlMkfk6~-Tdc`-} zDqhI{hHXI$6vg)NHnw)6bHF}};eEw{;!tsv$lq8@mnY5=d2KU%iFk#`YnkCUiM$pm-z{=r zi1MT2v*K>?b@A`wUU9$pxyaX()YDGP5YH6Z4>JBd(ahb3yjHTY34r{pl5^^)ittFo%xr^jpl8x;E(hre5T=C;2n>p3c zTcGeFg)f%8TyljN6@MfCPGrBwdOa)oCCP6{{+s0YB_Afy4xf@ZUqZOR&Hj;)n@Ub2 zk5zAy7MLHiACZf@ltWQX!L4-yoam zY#^TzSpGfY{o+I76XGAmSH!=F?~5ObAB(2HgI?YssGnn6WU^RKY$mo6JBppf?qV;I z^U$d0c(yT96`w0|1efXOh-Mxj`7jF{HY(|80t`6hx7Vi@u6dx0x5T6lW z5MLEJ7E3*U7ynEANc>FvS`4T^GyOF3)sfstH2pQg+e&UPo+5JWljZdkIfavQb=#N; z3ZE?IiZjJRu|%{sF`Pk3eJjPQ#Wms$B3~&n-6rvF@z)|>Z84s2wMf(7gD*<{vuOH# zg#T0W2O{5MF(02n$ge~`;89Kzlf{OjxgQ|DjbwXYur@O33ODx$r0XNOx~jDM05W^e3j&{M9xoT zK5GNhOmZu+qu5!jZu>G=;b)1}??cw+B~S4eiu1&U;>F@+;!2Uf(^mY*y(5}S$b#ExRR*j=Nt#VKNe zI7eI}mWo%1SBacL%=&E*?+`bO+r=H?!EuJf$C(aZL#Q9>exKvywUMc=uTrb`#{zlv?J}&-2 zd`Wyod|P~1EZr5F`|A>Jcy5g!sC75^wcE50KBMf{uij`)FiK>SSnQgrdG%Kc3c z>xvCT&Ue@lo;jBB#bP{#B7P2<6Zn_ zAvwFAY$Uc6+lriD&-fl9r`c1UB66ZV<+&oK)>AGQIm4dv-6H4LQ+`U%0c}0CpjyhJVoT3e9HaBY;mZ_S^12gDlQV2ik0F9k(2kC{#lVz z_bKlYIbomjA(8X;DYp>Yi5*4G;%9t6ajFjU-q9J$bUi zyNDSg$MRW^0b;f|R2(5r5~qr};!LqnED`PRFH;{_{Mh=yHnUg8_p#0F*|XP)+Gbv# zhQiUMai3_=Vr?@kwj@=A*CZL+%zEo;t*u)TGPaphjcw*Ght`?N>n?BAJUeks^7?wW z)LuKxNvWu_CShGtWoUhQL1tCp)bK5#H5pZbmTpB-Wsffc=Y`k(p`iYez@b{(?%e-& z&j#BPKCYLLaKt?v*#D32q4j}}>jm0X1-jh#g_BylGSCC|dmlOLUTKO-9jdcDw84qG z8$*Y~DdjmCtNK-iTh;rr{EO5h?w5D&-`BI2bk+L8-Ty(KS|8V|)%MG)zUWdF-jKJd za1~QIC^Mc8LwEb%&U8Pn=U%lful&I;@I8Sq0-JX3t3ABdwtC2!n)A#)ci1yWo((=w z7232NUr>K%Rf{9Fj@0||YLvIXC)0Sful;4M{rh4i-hq@4R3&a|aU>8+YxlGEmx2BJ zx^pkrZhNP^c}|0E4}KBKc<_tFO@BbS)EMsd%)Y>|Kn}`nx8txIPR>ce{$ig)Nr%Hp zm+yAhr&K0J-E4P_v);{i)+ASE+_$GHRK5o`k50Q~Q+ijq1Nwa7?rd}<@yia|dYL`; zY8m<@asRtnp^xi@LPt_QTibl_{=LO+@6xeod-t8)&iXo))R&a)RBl1*_b+#kBz!s+ zss35KJ2~-YSj`T2qhX+Xa80fCiE9&Xc0R5b#F0AP?Hj15wI*S0*(V9VO{yGHP`9$) zEmwvU_76_%v@7v&IFN8S9Najl_v1GV%6c4wvh4!ht|t$`s++WhlDzz3w@u z=Jd%)UDd37^r}ha6{{-CcddH8-0fra9Nzurdv$W|#dp%pGoU%wLvB9C1KgJ(%!ONJ z0^|Q+gV`BU+y=8DM-SXY4$Q;!k-w=!wGb5ScrHT%2^>WYCEzDuu+wZ4k~9|4p;U&P zb_qj537dh?*Z3FgeT@l8N@tq07&0=-kZ{5@AhZ_Bg6FUTA*v7cWS~RSFbP9&~}q! z3JLoqhQl0sO88JBY&Y{5eW2a|1lKa3-bf0#??Y4Y2tqs~%%lJhjc2cfn4C_P;f(jbBa?lA5c2Lu~D$W+5AzGGt1$;OYBDRHi{Ei&>)D7 zjLqjno<0vSb^v3~Wh{TyHoTS9Fd`T9X=H3ZC$Y|n*ei&z`847-Bf{p>NH?I!Mzr}f z(u6P+@hH2Ksh3a34SAH^DO7YS9yS|twx@d@#TIy$YcwC<{&c5u2L@AwqVw4j6O90? z(`k$-WrTKe2jqy5-MHkfw>B!_A86ys)X!046&$&(;HXmn(j)veib<3f_wBKgLn)cgC z58IDbXu)Kr{a#^ir}6WM*adfQtiC6i`X-~RZDs1~$!*y6Hs;XwTX3((Qg=3~M=zo$vTE6~&D$UhSh#yYl+ zELn|E*L8lT zEJKYItlyxvxizS5;aSqQw3f83lppn{*>3B&h;zwjmTUIB?Fm@Z@=gV7+P8T)V;c`H z%t?q;<2BZ__n4$>9x0>eUN7GxW%PJT5EIh?4=-?8(@uexc6H=bIGDXHGv;gQ$PBxj z0g2sPMd_zzCbT8Mo^SvQ;PZ)1M?VW>I_QdRY4FL8mearyolTw$hiVWkfx#qg!4OQS z&}?6!*(~%mI3_1qU^Q#ih$(LzAq`V~8m9U*OpR+8hty^}1OM3^Dc;^+9~jVKK&Pl} zpju9Gse;&E%WT4|RtmiqA=}_!=CTWT6Rs)Dc@_n{_!6FoJczhV3z^! zKHy8w%c`Xw=K5V8@h%M<>%<6xcR(j9F24+c>Q8c9U*_myW{o zaJ3v;@#u>X-}0xSaLA;wjTc*KAPM#mraV6QvE5Q&{t(*6-9(Ke_%py*wbH{A3s$W>w{{rsxx|ykJBHvpL}NBf53dqmnY==Hn)_{%Df6k% z+7h$&R~vcsy3m+)A^P9(#qWim`)G{Di-0f@!f zi^QrzP0YqAa1po~%$C!k3Z{eG%joG1hhuEjnD83<1@7S{qi!^@3KfQV55av4;#fs_ zTpxf#-!y`J9}c}W!IRT0t6_`r83nREN5G-vEoJnKHo}5sQF?f7!S2zVno(N`lXMee zcviwndTEp%HadjTC_UH0!IYX{y%4@6RzcVfvwnQsqwO%RnD&7vrH|lfl#7t4t*I#s z+RgUub>$@!t1E>~aIw1be#h0QENVY6W&k5`WPbFJt`oDdzI_QYQ zkT_8DF0#RM;R5*BHaQ0l*Ocik=-&i~eY&HJ9`+2ddLrJ2gH>q2bO+uZEee@K;qB3) zM6*Xc7|22J7#L0Tu(yRduh$_*DRD<&&g+Hv4p10}hoMIuqB~-@c-DU<9L{@UwW$_v z>-6yaLAX7Q_*DQ~5&BsV_DV^-3V9AtU^Qwfz*mbT)B>r}qP%o@4JA@U0(;(2q1|{b zb}(g+CUje#2T^nDlUgCB*9Li-;dRR#$Vg1-&#&pFy&x!0j`AZ+h#epb2J3S#3 zrHB0~ViJv|@r#}ij?&|GtYhQ5%O5soV}p8io4~qxb(jz@GG;?-&u1J}o0m6`R5&d9 z#WT-4;ilNwL-3q|V3?_zuiW0~`9tJJ&tF+-FIS}gIC#`a6Y}?`3z+9J_!%|9pCMg>Yj%?&RrcbW_ug|^_1oXc=pDu z$Z?N7BtzWs^Mg25O2RY`w5+8z|d?-_tEvXeeNP!I_TiW>WZ8x4| zJf(S-@>H>#KP&~|GvRnX*p2=II1b~mz3oQ-3b<8pJal$TL76S!B5>>+Pl4+K=imJG z8jHC9KdpK*d;Yjqz0WzY>TRALEQ!GOwtaABBv{Au8Qb1A!3F8TdXco?l77L(FtqJ= z^2GKTBim$Tz~aMot+U}Jjoaj_Y2mab!O`+!TXj~1Yd9?;BYZL_>N~<8>|(c6-*5`fNAYs zEUmTe(&53E+~F`LhRJQPBpp+zUDp_EW;zDlWvxk*NMjpXJR9LNBQs!&>Kw<|Q?|Bo zd(vss#ts=rOHX5^8PA1~A7r0dTynu+WHpMY!?WQvrn(Ce7kTi6Y+&hjsqwlHQy96Jo=^pvf**Z4e7VkXNl$Hn3GEWBgJ zzSE|S8#!X&h-}AX_SqN5&CJau;Y^=1f5t`QW-rZ0y#|gwE7L=F*1}vO|4zocDY&&9 z&vuu0ni_3)bCK!)-gXzq^(Wh1duO)~0Vg3K42RceX3G*SY`QK8pg&O&O!t=WNx?qH z3|BfObNH&Cb4%@J_2nP{Z%bp_4pbx+%K76r0gn1uuZeIr54=uGyuzWagx##S00Gv| zIL>2xzOGFbkDG}gf4NV0MY%}Fa#@}&cQO2aeV4UxoCw0~X5)$x;Me#1>ClHT>O)my z`n=zB2+(#r^i^5`wE9-U@7MP}^zA|z_3_%V_1gfy%>%E~wSOa*eVgHDo(wo{6`0d8z@8M48Ao@YXw&VAoS5zIz;-8QyIYEMy-|kUSU+yh!}<4P zC-%d(b3?@0{iqMWuiDOb=;KTcyKx`5k-p|~xK4Qn0-GYd0UY&FKg;y%TY>X56Jd6< z`mAi}5C6$_w}FGx$+S89_?m5Z&BM@fYFGvy8|&;sTKa zFATq2tPpPyZx`Y8`DKj)1kipk_Sm1A$g4C^Cag=zEJXf$rnrJ z6eH?eCHWf3{5Cwx-5~ic$;NgI>F<~Pu;MvZ$n>v>uPgi=$?r)%ESVQF)7KNtdPR^= zm7GDM9J5Xl!q1dEO!4PPo+SAK(b!rc{biCX#2ZN5%+`yylhAM0A42-Ak{?z4@5N^o z{wj%dZ%F6$YfOjEpBUkLG;l8tRHWNTYB zMCpxJjQI1F{sPH!m2QE!RPiemf0g8QlGl@{$E~8VrGow~ioc(P{J7*NCBG>7 zRTB62JqmwM;bt8n=cn)Rg zn=Iy&aI?iCg>u-`jAd&x|WMlip z{Y1xT_ER)APY7>A8R^@Tkh@AYwoZ`yNj}QP3FR5vCghu;cw^fHc>!g_FID(*5_PdQ zPS;X~-t~&#DEXI??Rq}?-p9&3Ha%ka(0Z94wwCjutsU$aLq6d18^cNW4^BE?y;GBi<<9EZ!ylN;LNk zl=Fb($HXVZ7sZ#wcf`Ho0r9YiDcq*s=Dq^G=Dq@QM3MW$0cetA)?`but$31ns@Ow3 zO*G$-K)%6}$BGlh^Tj-Iw#dadSl&YMVsW{6g?PPKDgH{lSA10bz4(gw7x8Z*hm={K z`4$Bj=6vv3>K8E-_$ps>(u`=I6@nW%DH1{>c+x7CUQ}~VI z&EhY_yG2e)re13!Y`#GO+1%H_Hx+NcMX^uvLGerRYY{7E7=3lc&SF>5-oJ)Pu5R0F z*Rz|W_!4o6$VGct-z&t`VuiR~yjA41YNqG(Rq{dccj6P`@oatns(8D;-CoK2#E-?# zMNV&JIkm-xVpB09b`Uegp5hteAn|N*lsHM8Dw_Kt%DX^vp;#hbB9@8Qh-<`K#oI(q zG-v%E5Ubnzn)@N*cPW04_z!WPXzq(h_qpUFVkpVe9~SG2jm0)%npoY|x0k~EiUY+V z;uvv)I77TZv^KtrC6|jUL{6>e{#zU0+a%v9S{vW{B|j!UAwDC%AigHPDgKxEo_I+7 zL_8vXBXX@R)+a@@Hot8or;FXi0b;gD;{fKLEar+cMQh``K=Kl?R9qph5-UV&^Lv}* zJH_qd4)H1R8S&5J8)9`^-cJ->C33KX^$&?DVyf6oY$ej%f$6)6y~Ms^jyPN#C!Qfa^)Mf|Hs8xzJK6sy}VSGP?bglBrD&k<=$LV3POV-m`jiL@V~{7aDrB$OW!tJ@ya zXoT@qBJD&dw-ae7LODwuES@EvBaRhmNy7AV#Zs|cyi)wRNZSymze}X`2<3-F8j(=m zExs+jD_Wc6PbAasgXuB%-;lNwl-r85%%I#|q-h4_A>s&ev^Y(iAzB;dWsi8SY+oF>wMgYr0$<{6Y{iC2n07k?@K zM#OFJd)Ycy|9u$I@1+jn$zm6=`tQX73eOg+|6ZJ=@Tp>fI7ciLOT;B&sklm9Eq;qF zbnhND*+Tb>L_8a5?|)`SMz3DIB9W|~J@B8~cdt|XB>FmRF7coR{0f5OJlt(WD7 za_VNg<$uWC=A4}4wEO1sufNI9Eqv5@{C)o3GTB1z)u3A+{~CB9CfNRi>F7-Uc5%b! zAPDxN{Dl^r$LyVknUJJ;KoIw5Cve(%{2xjfg&e_hrs+M`gd~~v4JVkNdEumo5fzH9 z63X9@L4MRK*y{|c;`a-K19_x^ISd^%-P7>~!V^NMiJ1fx4w>Jiq0k`4hC`E(G;t{W zp%v~eKvL*6{12ywKB||FjJ5dHs?aC(Dww*x_nsp3X}x!h7^=l@eT6=g7_PM(!J*G3 zrZ|a9nYpUo`v|V>-iEX;e^}$T!GGA?ry(Z8{Bi(25rm|$Ja-_A<4&cp0Cy0JyNKd) z{Bs9WyaNswAH-~mfi+H@Lrgp5E+d8N;w_Z(B0}o9V?&Fa?j7p6W892-?&!cmL?nf{ zbE)nH%(4Rku3Mj|e;NO6#XkhqcRSW?m>jIzvhIY$`tDelFYy9eClJ?V(7#S#D87DR zLOm=ch(`6V9GJu~F8CL2=*BIdYQgf!EEPDcVQ<`MY9H6Q3B!E;_5D(gHg2lp6QQQ= zRhMCJu%I9I{p!nHSjw&$gkYIYaaF>slz!-kVKK!TnJs|-oTy9k;J}}1BJ{5jh^d7H zqp<*vA`F_CpfN;qIIJUL$dn=HV|Ppxp4ip^KFqTxsE*UCNo5R^Hsjc%GBO4e{QL>V z#S*kKs_>5^#oDOGzxm~JaNq+@7yfsT)UAW#@4^rLj$7l$#s5v#Y&d4AiDTw~%$_&9 zB)*cvF$*`~1c)u%fH4Z+!VRWf6L^9+!KWNI(xYWCITBnP>D2zbKmhHhDI)P19yPXO zw__))#OmWsMDZq+96kNy*oi?kOaqEdBl?e?4>UJ_ZgD<8`ColvmT$6EY;sPl6**<+ zcrAatxo5~@rfwZQ?if(Y!lD{AfAin=1^@n&hcHEieYbg!&Nj>9Ki_7$Ey(TQm=0Z=*{Y{w9JiC; z!f@Y}E(2+*mm5Kt-R#Y%3j(~yO)n+`-}|9{&dFdJI?ChVY#rb=x7iPU0oKcJbNlu6 zhCW&eQXhXSSbco&Z}Y%w)?VV%nB8pL0t8q;<4(qoKV=j7;`mtVFLw)`5_Tbs-4ynyk=9Ek?RNRsflX+Z%A!PnqAw?{SJu*1Rb6k@hu2*iM9~g9^S?lk8eTq9PF3b zg7J;(2c$t{oA5rsIYy_)qdmRH-UDNgRW(mMiuL_^pwPTN{2*Ze@k7=T=)rur$oh(B ziX+4^;?KkxB2RMWTP!XUSBq=J4dUJ6cJWd1N%1-HW$`cKMh_jBnWb zBlxKO>!bbW)eyiX!@h&{?$$jsGcyw3GP5!>dv(w1aoYdVm`~BSjQRWmbv(f_A8%-< zqd6KH{xP%FI*sRk29mBMH0HCOO<~7;I6i?7gVi|Z^BW}e26}p)hGZK4;gSCKF`u<8 zAQT#ERC{AStXQbbtpH+UKJR&BKAg1{`k)?%gJNSo`(k50cR*KYe{9T$Q$9i;#>afj zfYAYs`AkLRcaQn7Ja-_A<2jtd0(@gWEZ_%?`DE5S=ELjqr!gNKTD0p=V?H<+@K@tl z#edkCkG1pr9~$#925B|6<8j7(Onp2fGjHT4HdT;^lY6eBn)mq6o7}_Cwg(59%PEw^Q6Mv;hx1$bO?M)MDJVv|07(;RFcP}f-G-o~ z&`$ivjGq6l*9@VxxZYgon|fC;wVl!9q&{!NP%Vy*gj|W?S~Ls_1teld561JbAZRMb zR%?5+XR6KU*@paPMh`s^Buim=?m!l2Mt98c%ODoV0mu{<;0~t9@kDeX5VK8XFr(*5 z=x~Q{h$^tgo6)laA;+1~!<|cYIcn?PPAzVIqW)t33gFjfBww=xre>x0j&#q+%v#W6D#E+Yn?EnV zD_`#||s}G+QS&DMsJz@y*sbwteyHj%{1>G@j#(+??2mjX7N2teyf)ONnq^ zP^@Y{WWLV#81VB>QI=*ZVD^LM8;_dB|4FQ$#&c%omE<|;(~FC}2|C9g&*9nfZ~p|c@cZ@s1^OZgvzv`8MSx%5 z2uvb@N~13swEEV;Z}Y%w)>~&fyVh-&JWu~LhX*ak z7LRZLb8~pSyXLpd;bGtZqmSntZw?RpHjeX567$75VzIbfTq&**H;Q+Q_loz6ytb(S z_u^aPe(_6@OR+IsbFq`ymBe+MDfT3B@tZk3;0UEN-*JF^o@A~K$8;A;E|F|(Wl)Zp zxdGn5aOkHc4$J38nb#hfBC=nj91%N+r;6P~{vu|&LE$IB2Z!k*Z zS!j9xt({iyKE1tw6R^|j-4Ko7v(vI`R<7K#HYZ_S!p-iQ;Hn`7&MD5Jzm<>Lx2_h} zstk!hz86R}Q$y8${l~lvxKmEbVmg&QppH zUa++1!S={|(uExkwi~|q;1f$PKj2L1b+E&QSqGDrzIq@q{Bo4n@nG7N3l83OVb6m} zQx+Y(^TO*71eg8+<#$55P6w}C+UsD#g$ajK6Wqh8?r8@Tmxd0fhJuGvgLmu>-jbiw zCcAC+J6nI3(66Q^1<%V zEp4+~XaD7ZbKz45oTaG2(uWSawN68cL$E4kDCJjZwX#p9{dNypa!5hKEeZQC4?T3) zsn=*%JFLYxG^cJso7{5>ewKS}!N%Md3;vet_GS%Pv%|Y_ESitZ9+7>@*6~%L(}%#h zeZSb9sP!D92NIU@7~KAzcih(1dI{?`@__#eHz)7@6mq9Rb~*OL4{}xCFb4Mvrge=W z5ys&7o#$XL2H7#V(~$?0t*&Ln7+$+}46ZXH!U+c$7EUSx;$v{^6oLbdE?%ejd@%kE zI@hR5dY3ueFb!fb0>}F%M&NK~q{NxO3G8w(0=ET0iJ`~vKZzr7O%NL1j`;Wp9G^wd zfuueQa4kiS5n=?+6T@M4xfp@-M69LAX@nSo+lAm-F2D2Qu0)9AutMBiesiTZZ0fG0 zhYu3Tzh$ab)WCi_`5dOYisGLr9zjO;>I!%d!KHA7&t1(54?{#s8|F14zj2eoaY;|) zAY>i0Ea5dw%rDHOq%rTcR5h0(XZU&IA0gH;%MxD4au?va2qIPmG$NlY>l9*HLN5}X zX&o+0XrxCWrLe)=3hHg7PS$bPP!Ycal5!7=Sxb@6&2=uq(u3<*C4MBT&P6E1Nc<#5 zokfVdo^fN1gg7J3f>d`=4@q?wWyzP)kp8Ra(wbuHA~x(L#x9+} z!er(Ga4zK_c5JKQk#I&6&%)98Z*-JCCPqXoAw0d{upR<22#$;8klAoppQtoS4{yU* z-eW{!R;wuev=U`Pl4>!1Z3Ou$oJ~i+SKJtAh;6(x!|ae?ZY*~Yuh*1VDtJ;&!f`~z zc*hbdd8)7EskUU)Xevv6-RK=lc#X4$-Im!_;Qu{v0jFYAU&Nc|5BR-U$H|3f6CC2t zCSUdZ!^qc-zc_R<^5wuG%?NV1@h>PvwArr5|DAA%A4)!L{0j?rf#x~NsTfYaYr=~S zKQaD_5oE~dD-Mw@jK5;!AW(JXBZ=8~l(=Jw&c+Y}==XG1oI`#EhdK-=!=9cIB)`;; z@N;al+5AXmwrVZT6N4>F&O%nLg>@mkLFZ!EoK|dggnvil+X_S5XjXO=oa>xNq!?|N zxKZwK2cvB)(aU(p5wsM=3F$^xz~i0ZlZg#*IHif(;jpSxS(KjbUO4fX@s1^S!eQ~3 zvM4=l0i27rA$)7Lu&NVH^(GKVg{h%I)QcNd4UUw@anptG)fPT8^YtI z@L|$y)k@)sV@jciM-W0u)E-I*OQJlMs!XZBGIOd|X1FPIJmFQQ#9x{57b2YV<)Jj> zJAy~mjE4vd?GQXF*af1C@lGWA!eLpS(kMMVtB^Xrm!{oVU3=KE%2iy~c;;-*{akaedn~kSw2RIxxf~RLK{K&sPQ2U#2T10s&zH4;yzHPP!`0qQW ztcz)FTPds=RvKl)EHU{e5#C-+SOKqh%8e(khr?=Yp(s6-o)C`G!?O@EDN%av@`ThV zJvC zX%q?0N$<$zLBbu{w}vHogGk;$EDVwsOpRn>A&|^qN_uc!I+p|~!D=DtTr*^Gdaz~s zshPnB3^Q1o9>gEyd7fO59&DU`YE}?zgOH1uA(+qqS((&k^o)kmp20iIh6mquCQZr6 zJoS_g-9~il8oW3?m^wV8OYpO0>A|br^j>{}hvB=`oiwlj>v?nzrfy6d+B5h%mI0YR z3D!}rwRblQW@Og*9!!gOoY?EI>|!jcuxRl7{8_V#o&RVHb}c)hH$L$Bljg@zrpV&*a>P53evv3I(ewnebsHnRWH;(t&?Z@7`nNz6y z4_dzE#NVcwl~(>8U#Xcfwd1X;!7jPRbv5|2mZ9-e`v_ovlwZROnt?DPLR;{1~E*ZF8F8@eS#kAOynzvG*U| zvsNsb^G6i)=eTIb)Ay=7HC_6Z-h@X*V0U5&?dFANuqmOHAJe_-!8Q zFyC;ip`9xc=hycY^szpy9|yQ>{Wil-eHn1v9z^70)$}p`J~)56g?K@=fElzgj*gFy z7zip*(7(rwR=+0D*jOYW4B>uuQ+c-Z)P)5oR~)scG|v{}?v!tXF&sIXG>dw_}CaR`OB= z%@q_+9mM*k{w-+EfOtsIoT+}9XIgv;(g-7A_vBq?@jRou}Vxr+c3VV*g-s%ME_=N+(Glb zb96T5yL;epr5jH|o-BEW-nOd&T>d&V1h->7J1M zyyE{V?h~uTL|k~(n@mEl`JOrC7LqwVm+_q?o9~%J=IA}c`DH!weDNZ21qpq8F~InB zl5draW;N}`tEHy*d$_bsxcT{rb~WbR*D2 zCIiy(r3UqF6(17K`HJwTBtIkW7XK`A_BZqYL;OHIAbu)-A-X)zklwsT0?m01+VAx9 z{R898c@1Vt?kV;c&3TUaVUkCR6U50PU&~P60&$60Dw^v7@v9_XCz|U5;b#3BaFfFC z7R@>~2>B)1n& z63sd|$e$(obkVGbgYX>5!^Lspx#G{n=^|fbu|5mMQn6gTO1wtAQM_5S>j~T`*{&zB zMe;+UT}S6h$xn-XbH?)jD!wD`75^pL^#{I^%!eQ5t0nS#N|c+3EyVWXNn*O#UF;+F z7wvik!zJ7G2qsAWnK)gv>+0C`2uc-RE?z0x^$6BVw(Ai@CEN7~ekJ){k#7&VU%wZh z7M~Yi5&t6E^$FgQ{DF8t{7kg#6}Zq%{RtvpPf~6swiV5~Jn(my+)L#9OQyH$7>t%Y zUaY>Z!G#K+CoU8(7R$vI;?KqF#7c34c&GSFahv#n__+87@mcXj(X8VG{~MCu5%-D* z#KR&Vz_`C5F+@oJH;ahZOj zc$fGqvHCg&k16~K@mcXj@ip;H5x|51?{^2w;YQ*#GR)F_pb=#}9NXs!d;_OX#`l;{ zliBOEUcF8F@3w~;(2=!>fA`qVr@3p(`kZDJ%{G)5Y_Ce$nOKof@M=}4JTkk(s`QQZ zuWz;?sUl@pu7xP3p`-E6~U+j7g3 zDuV@UTfW?)*8Y|5(8s4|H(%qVJBKzcPsuqOGi)YRr8$GELdkCT=l2Jk4THjupPh64 zkk=m%nMPHyvq8|EOHf=%Mer+&>n${pfos*EyW(a2Cqm-F0r+gPbXqd!SK$@((lM*%g(|1~`J6z(_^Q;YmmNuJKc#tgRce<( z1tSY?&Kb4uzb;`Ixa5VZl=8s3Js$+xk8M6Y_p*X(3gR)1%0q|=A?E7bCkkFLF;kkm zXFQu*NgWq+29a&4XLi5vL4&KBY}kWxTip5&v{ClXx|N%^vTdHo*^x7$Ds)jhw0`)4 zWzF2)eUbmY;%tO{w0l?13m-IU@3mJd+AC>2(w<(gGWCYBEk>hN>s7qm!a2OYJn#pA`KzY2(VR%_~jIq~cs?Y0d?=GIlQ1&T-E;wA*W$E6ev(Wt6Aqgi+UlXcvE* zc>CX>JdC{zV=rwB*%qk1?uDu@IO?^JYMUv?w1&SOUfRuL8Fc@Vvp&03cHQ-pw}x~2 z=Smr+p6c2gX*Vwi@OP!vCoSl?87U%yb6eD_m~>skxQ8 zZ{!A$f-|D_@8;grxi!2$q1g-Y)vX+`HRa}DPW=M+^ilf;x`WUfRl7TBe$@2rneU}+ z7@5=ez3JIc@2z`dog44po3dg1dnuJ8ayIR~0euM`jj)B>bJ3T$7`t#*!u4jDZ^PuK z{t$!udbpctdL}n)e)t3uIDaa{hpJ$wbCC?6r|Ji7AucBvJZ&~ZLJ9m08u~kx^uEM| zB=PAzbRI)SUc-=Z!V)jyV<7Yr|MeQd|0}6};LqrNlHNgu^zvaVH1aZdVGKDK;h0bL z0TB+pZURFyJc+9@CU9seu)@6yF{UF8T;)Cje`08#`G1S~&)B3!fjJHM5;bg|LgzJL z6f7OX{M311zQjP-Jj)g~2p}b=UF9>?0*T@9ZE^J(U+ z@1-{ns12HJMNrCYC(y|F>X>C38=Dl^asGIyOYOBT;$vNJ)ZjJ*c{S)0t3h8+qxsC; z=_b^xK|iksGx6dn(BBJZQwGlP{ATH_Grhbt;S3D${HA6DV>KJ>)oc`YERbzd)H#E- z@%*sWOhAk~2>%>s2O_w+YjFfqF-2`KJzWt}pCdbNHjhOS#Xm6B5Q^(4PDDmGhvJJA zSq1kjwhhNM8t_26!x_s+G|+2#BoPZDnYV_g%>;SNSm}_;dIA6htd#e zY>-7gqbPDY%ZBq8mN@R{&!FuPZr2TX2DoE*Sh)yKgFMz@EbFik_xA=o)!cDB)3{Vk zgXWAK&tvl@#b(ImPGI7PF!&@y*NtCC&^w50!ch~q@lO0dA7fQb_=?_bycz#5f!KH>JP**b7M>5`F$03lIDD3d zA&+JU;TZ`J3gPg|BzPil?wn^>ND+cALTr;++_T10BsM+=p1lZfJP00scD6|`CTM;N z{wIEP6L!UE9D#ohq8c}X=XQ9SQgO3okY0z>jK3~B@@eOKcs9d>fgDzWGgdg|z`eH{ z&Wo0;LQ59klBKs~$)?oS^&zp;mMpX-OKZuJTG{-jqzt4oC7lmXYnH?rfj|jdC7fGz z+!9tEuLPUdlyHYF;mvpnxGdTAeD`#~_<8{$|2hH*KV&+fH#_j8lt{AM5ZAw^{Uz}0 z{+t8IX?;fE48WMc`F~n`0Nsc;;SZnxJ2SHuI2;MGZ(O$BpvR2+3|J=v=yk$0@e)Lcnw` zqK)y6Cn`dCN z*r-o;)v}mkc)YCRhn4q8@~(Zf{u|`CgjKE>$=H{}* z_F?+Dd$lDewhu)q_rifna@M@Pi~$rl!3RrF5YurXWB*r_(NkcA!qO-`+$9r35BCL! zZiP8?8;yWu^xRVC0mXK2Vuji^H2Ulg#$r)Lv#rMed*INv1jkx2D=-wLXQwBG zqx3xM2`N!}_^5+qsZo0N!l9Met{g%|T?js9nAuwNwD7`PU>Di_xy}T_OnG+}mPYAe zPl<4La$Agdax3iE$!6y!6Q{so5@l(W9<~pv%$?rhc~QFAc-;QSPCMILXw#}?++lCW z%!Eqby0F8AQF`w6gpw#dFM7g~C_V3cLTQwqui?;ML|yE($<9VP!?eJ7Vz?Jx8nrEB z%4QSs_HA;|!$C?2B~f}l^n@i*da693G)hmRX{_-?BRG?t?cB=?CwhC~rBQnLxN8ce zXS5NDN}}}Sdcu+@JseuZOwrOP`-K%oKm*aU77o)!?SV47yaR;+4D2?i`?bXL)8`qV zcV2A%w+Tl+@7$@RFp)uNW;5TSYvF)ee|OnvcyxPsx7zJtOkbP`Q&2@DTvg_~Bdqe@%vY89ZUU=(H-Ry{%-HXnF5Gtm zSXJh`0eFSlszu=G0+;IDz*4+9!Hb-Ccs1ilXSh5Uv3pbiE27)gq@A;}|{%u8CK{W8xV%53c!9 z@yLv(PE0f^*s8g3=!kgBoe5`aLjO`YMDc#hhK2VofNiOsi!E7G)ljP0sQ(N&++A0f zC3bHWrN9S!+|UT`9*>6sdgj1+x8clIQ3`xM$HZ*&n2v(baBnZ;{Z04(x0lhQTmIY2 zd`I=|*t6DZRO4E>1oRHwJ4Wf{Aw%^E-m!6)Azp+-r(YJO=a3i91N$``Gxul_rI)Wn z@k~ghz+sklS(Kg@UidP=o4vi}t7Y`Cqr-%D;v+arbT5n2)57f9M4}TMcCEaO9`>EQ(o{X};Y4*m4-mWFWO zo$ae-ytDnxgij#6TiHU_e=935dF4QK2tc)sw5Hx4wRqx97>o;<&T3pg23 z(z_^8JA3$$A%5|U#cr7`g8ywyTTWmPF~IEhxda~ra5#xvFO+98_Z6lBgtu!Gh)OS% zr;T?KpG&Z0lp3$Vx$z3brpL1}M!@0nC``=k5T&1Ydz=i!BokE}Vif(kCTcvvc0+PM_(Re53M1tcK=sF0VgnVcxy(?!T!Ck588J`W!aMIhciFU^r9N#nc zJZ9^H|K4-qm>hW7U!jgB3jY|(vT$MYu|5!`zy?g>Zzl#&*x^s%&+6^d_vt2C;6AwT z_oF1f6BD@;L*a~p4n4z-w%Dl@Pdb`O8IHq)|7Od@f3MR2>j#2G|F}N}sc{}0eh{nz zy!{#%Kj$aMPls`cH(M_LdkMeKQDd&}f7F<3IvhI#(yQx4*7a&Q)4S4hGaSyzc*Q5i zD;_&jbCKvmxSH-q44(t{e{rj{h1aAWn#~s9hcVoh+u?9~A$ZlGlfTFRv~rL6{Yt$i z#uk7bwO6bO=dL~g2TcSoH4|=1#J{EJ4S3)28J@9&$c00?cb74~)Cjm&(c>kKwVO?h zPLxS`*MgV*H~SEHZ9%*bdrt(DuZNfSB43&D*oln25zgH0=()=zjdeu0F&(ROEOYUe zh7#@m`wHh!10u0;0La_e6n0C4rvu!{aHqg^fs0+#@bkfnU0W{PYB>Mq*K-XD2{@h5 z2q$O?bj&B+X7rs}`2YTw=*$9wvt}1fD=y3{DmJU@d7qr4{lnb6l7jRCw)Zi1L1^;W zl9J{~aIzB)^`9JA0@Y3rUK}}z);Cy8vLwu1!=Iy0_j z$C&g-+jfg)wrv+}-?m+UxZr|*P!=r2%NOWrQIgm%u>>O+uS=7H|mrL z{x6K16+x7L9ZUuN*w>E z)Q)fSa?J5O&gbQ1%Vbvf?3D%eg)&u|F}rBSpoOz$qFHe#qD4V&8--q&XDc zjp3t*@$b_e`{_KqyP7sVuQ=a{EgivOEMe%{Pcu(HA`nkQtMRiwoK z(MDN?qwuzCx;c()^P>%)?8o^^@=EfD&6}COMCNXV?|&tU6QYM!a<=5 z`<=hop)sp^XqDKwLDby5C7ue{CP7`XqxD~H_G-s*_B^}dLyt@+woV97!i974iq2&< z%(oMLc2@BfX?f(m`p=-9ox{^-PX4?LN(!9#YNia#pEr~BHz)dH?N;Hq8AW*|GYW>y zb7pd%$IV`vZ@NTV_*iH+W&isuKk==$RlLX5Xj{b>CqKxxs@nDVZ*E%E5;rll1b*Ln zTb5{H?s5>?!7&}0(`?n#F^=0waACObO2_Av>gD>MN9@xM=a^gF@H!tt@p`;hwVRC_ zf&jdgj%~Sk7z#s46NE51^|4<3VQcfi>s*0M<-P#x<=l1aXSxKu-wQUN&)aO=42b@6 z3({e1j&v-S<=Jux5wl5}`+%jVpre*H<-wBXOR-+Mv~U75p|2yw1tcH`HnwkKN#^(dnchq>1Fw>NgUGpkjQRw%m5S%!G0VSO@>a5wn&biE*(CIhA`x$FAfRWi;unc!Vg;FmAuP$pwgKrk zQ%3%+3V&GqgZLtea$XicRd`*5F}#6@88l`;I*3^c?=7CI@IuKY;-v~-DdO@ldQps_ z=?@UczKP{E6WQNT?kZ-AytgpCpEy`NOB^kZ7ta^-MBeY2pU(&6rQ&jNooM<8#BY>* zyZCGIx8g&h=`WD}MaeIVZ-{%ucg6R`!{VpnH)4?2HS}>N2U%BaCbkl*+i0Gq@YBWW z>k)IZBlVppP8Vm1^TlG3Lv>8g!90?)BS~uuS1Fmpc?`cp+$?Sv`S{QHr$tT!pltdv z(AvOpq9MciCW|~QS{t~pC1cFO#3zgO#AaeEvAQi>cZK&7tJ}hH77WWBE1Lci@-)dD zeq{U-(M)oMe7WS+VuiR~G`68g$017QxBcpUk{=Ww6Q2-G|BCcx>M;14!rv7CA^ubR zP&_1lA^x`*Qa=?IO}`7h4JEe_P5+B?ZaW`-wxuVd7YEqBu>QAzmoX6Bmn@h?j{g#p}d%;s$Y( z_)GCO;sc_&Phh{zeFFTG!gqKns~Z6 zNX!vOiTn;d%b6%u@d1$&;i>N#ku%{b|4rN{9u&V6 zzZRR|nTP3Hh`q$V;$-oBai&-xmWWHlGVyZpYVlg}264T}sroGcQSn*vMe)z#8{#|S zUh!k`bMb4D-x;9ZWU-#uOl&1~6g!Kw6=1$I#9`t{alAN5oF>i?=ZJ;kV(}7jrFgZt zM!Z4XDBdpqQv8khfcUWZd+{mpMe$|v4RMdSSKKEa7C#lg7WoX!cBm!R5u1oD#CBpw zFRL?o3kAg#X4erv6oA!}?w+t`lz(H;T85_ln!Zhr~z4C&j15m&8{@n%JCl=!0fviOF$N2G}n^B)pF7mtYiIy&RSVm+~;NTVdicM`jbnPOk@43V}= zOg~1PBu*7+y~OzW;v#XWxLmwKyhdCjR*Dlsra=RfXNioalIijRctD@6g!HYMH*)@eLr!qc$RpMI98l2o-fjZi}?%1#o{I6 z3UQTqow!b<;TQAYCH_X-Dn2YeCO#!TBhpli`QH-X72g;CC4MY^C2|0Q`I5wBv4Pk` zqy-w&bruJTL&Q8WUtA%s5^1=`{P&3Wi4Tg8iBE{ni7$z-i*Jel6h9CTiJyr7ExPr+ za>HVZNV7QBr=3UxILcXKe{rBVTs%jlogCBWi3K9pOJaDjxLBl-9K){`*N8WWcZi$C z--`E%kBB?PKZ(zYw5p^2zlr}8KM)UzpNM#jH{)h#CX){^#LpK)JXRW_yEe4x8cB|b z9mJExE@JiZD)S93)X(I{xo5|_x^?fK+5LNcyP;=KFa39ayW#2fs0@Z$y?2Nwqs+!m z*AEWWTfHS*5yqDr?z(DE)%Z;vSGg7VcEiqBt5Ub%Q$9D$T(zfabVc&oiP;Zh&5o2^ z6LO}vx~XMmRp94csv4EwIOx^K`{4@O;0XyWqmIn8tWRW%sht}1Yz+x>=?tA>OhZ=Q4Gpw}NiCCBY|c=xn@H@m?#&Y>K9 z>0vn1)>+l~i1TUV|HIywz*kY7?a$n~Np2QG2wQ*vmqkE@K-f`~#du|v5J0vlVGoKB zAS@!1NJYUlASxnqskPdw?FW>$YPHf)e5i`Bj+-82SW3G4b@o>h*^i6C-!@c8UEzyET#qF7I;SH^7(1Mn+ z8_|MOO$$6@i{X{(bl4hbfi}1|@2qupzyianR!5!Xur9D_XKiT5xN>m)CYJ524ez+w z(6@n3-SNwE_bkTzx{US&Y};Pl=iZUNHDgQ4ou|e|??j6(FF{+}0nLv(6QJ#1`T<&% zw)wJku#|9mD(q~qWsu5D-LxK76E;Ryk(YkZ%}v?bE;edsFZ3MhKhhn5qf&(WkNRMrcjpz~ z$=uvE2HO~+k+GZK_MAP9pK9!2YIgtJ&~DcCfi{dWBVW8%#RI^?SHc&pR>*B6L!zV+M~M~+-wBwF@ecH zd{2f9tP$*og!eLN@06ho38lQp5U!kgoy@v)D6J#1^3GyNzd4i%r)&p!d->OY1^!{& zfQqWHjxdp2B&`!5`IVXXC^&{eefp8yO|tKBlFy*9@Q|q_xwsb|dMQX`Hw@vZT{ncm zR)Sft4u`+Vz({y3Am!VXt8)2fIwhS_SGhYuTU!Yq8u}jd-x5_zJ77qPM4E(F=B`Ir zy32H{aw)~nM4PuuSBMRzo0meXt?`6(v({H-jVGknvM$vU&Px9;vRCFB3j`ftJfS`L zHMystn2ZZaFNEoWED)JREUhAsI`~;Ip0Fs7b;^8*GK+nK22{!lEivI)#&|+yUK2=X znpu6RFVBthp=EiGAZ-H}Pgr57Z1cY8G9%$+Lg`kJ5i30CuNpElL`dZIe_`qeSZ``<7U*=7mVr(rRH zuXNoalBM!St;n3fDBllf!xf})Vc=jf(Zsl%eJ`-4nakz-)a=5t{aI|r~F!wyN6M6I> zBFh)n?j#DIn+o-D*3uMG#b{FZynx4Y_s|7mZoK5n~n$35l`q%d6E}{ zXf}`nEqmZU^~eKgn$whOKbKL4%0Rb)Xk|0cy9y!SMM&O_Aozrzw*>?r(N&EusMY!K z?(Vs$Mn0>N&no1z2Kg-AlspS5@>y~|3(jYW`7EuKO>atC&H`8xpSfGJB$aXiCFFp0 z4?p{lO8NPTO0nrpDeu@)n&3%NrL@_I-1+8ZDh5E?L2OV*V-Kb$WZG781o%9klH1;n zdWl~KKFV9Q-gOe*R43tG;GO3E@fXaV55vLiU!;^1Eymv;5*hX}HOa*Dn=k6~ZOEIN z_gsL44yBq*zWs6@+Q7ho{0BaVtDjkO+6fLoq8H zC-H#KMB*fN`%IQGu<%o#$%&JA8XlS;d~^SvA;*@X1{Lr|ub;#!pIKq_Th{r^syK-) z@X(wge8Uf~h~Ed|7bd)f(^@llRF4ofWC@`F9$)sUjFaHp31&r{1m|)vtKuXsfTuDm z;9@_#B2J>lgqQHn#P6NSsCvRh5RBdl6LmbpfnE<=!ImKWI+fb!fJSi_#QF#G1V{U{ zgn&8PoMm~miQk4dh6zaU&KNyRc*PH25q}%Rd+Z6uTMY)=TH0dLF%n_?>2Ox4v4nX9@ zk?0RVw_>^01uw!-E^Vm!*`t6Ry#J(Y+1 zd3YSKQGp{oDsY5H1rF+{j*rVht=2w8vK>X!SDs=MO$Jx@J z@HoO8*T03g$w?paqwHvgRI|kR9m}S+hY#k5?2ThLGjEvEd9X^KCL_;BC5-n6jb=R= z{{T-Uu&2@EgNbj#!z|C>ROr={=KUB>83H?kVzxtYVHwN{>I@r9>|&~wELycPQ+o}V z6lW!M>q+tqL%Rr^&oL?q55i+mSH(&2EJ8Tp1$ZWgZavB0nwSZM-@_aIT@wDJU&8y` zGI$)ON2*Bh>_RgLH70y%Rh)!>l1(7&fJgI+h!4XXjZzX%!=s}1>@#^rF?KkmW6%&r z!5a-m68<@M0ign(c@kH`n>VhU5hxozHem45s(l+ ze4@~v6q?ZUg%?ik_va+0d z{4;q9ffc}!sP{^a&yogHvGZ}Dh5<@^G8oH@{KFKAlV+1rahu1hscoK(52icujK`Wr zO~2JQjWgD-(G=Eb1UznPs^TO@!DH0n-?*gcc#1B7#~EyAERepK==ytSk(r(MXd18~kkmnN$+4gtoM;s3;4!`Ksd4P$4)^K2vf1x{gs*TS2rjKpU6 zV>)6A&&Q7Nb^3%E1SfV|-(VO-jAMcRsGekpL56b$4NJfjT>HdOfO!NZFrWJ{ivUSg zZT4eN)1^~J07k)^T9fca6UQtmI+miP@aWOxIX>1F!uO_okrPo5pPee>Z#@j?mza zgFD4-#9avFhR!rxoa>E1=2n)OP#!@9p8ly040#MnW@pO@%xs)pHv6IuMM+Z(A_V1P zqHIB&`+sXh5@qiJ`&0Pi8t^y*pEMD58emfds=~4!gh#C-tO{w0L4?3L%tqPy4E%~< z18s4EZedaeBZ#0}vY0B6%c@{5A44u=27jV~?;+?2d@5~0At`B$3-ZTQARobu;+bz< z7sy%H9z;iY&P0hJ2bzcBR(N**7I^kOkD_&T<7_zlY#01)c#bUV7`{W{?8iso*%Q_= zj_HDN>>lfEd*4SGyCdj=?I}Xsf25Ux!amSO!bI{JtqeTv(8@rx)hXUG7#6@6L!+(x z^lA+S{d;>vp?Lp`F;Opr`ugAM0h-kONIn0k>L3;1#3r+ z9GNg8FlU~zArL*U!+EeO5bbcfF(RAZOz$T+t2bgxl!*LSO~Zf@xFxsSXmg@Aw=T<~ zSpf*>{3EomFU$cX%?42Jv*`X$n>M86yq09^>K@ECevARfqR=@i~~Fv2X1LoSY#F zbIO|!!#bbc#DKAA@agOf*s2>%e%9O=82IN+37DZ>2)h(B@hwkbu5ulV)2*4ZDgnPRS^s4aYuNguB<{pjp;sc^h1JYTTfltT>0xUVV zj+~bT{Uz+Nvd+rQL_o0IvH}D&^2=p;YzJ`}yiEhrIjxoBL`lfmxW(X)$!`$W(GbRV zpsI=d)`PZbKsqCk-(C`OHf}BWV15w)bApOw$9NZblnl&&ucgIL7aS56VT_pPUVW%OE$vW~MyIJ{O?L?}l7| z5^{E2{TzI-9h(Oy`prB3|Q!sm#P`;B<6UXbU4Eal!6{}=IQ0RZu- zI4K#QNd(_iywPC=&lNJp_Y(G(+)(k{F2r=)2}C)gqYAuKJhucfyjpVCiZ?o`NO!w< z+Aw53-w^*T@!uE!i1?q1H@c{h|CRWc6#ski?}-1i_z)%{*2CzU0$Y+tKN?+AY}@Ik zc%xH_cw;*NI9}lw3TF@@e~I`?p|K%={JugSXug+-^j}rH`931}?}&e#n1=V2;(slC zg^2X83*S-r5#do`Dr6{!Z;lx3MnwKG@gs!X;>GY%;e3T#8v{2h`~ijU5OVVu)BRXz zzdQK6;$J4B|KC*nLGebH6zPtN=jX1NkNMsp`mG6hq-(42j^ewE??ZTBmFGo~LQ zo*yeQ?IA+W=%OOO3WYC~T($VM;%mg;LPR?A-9e=LroxTRD)@)QKPI`yi3opA;rqqE zCjLz#@;j*T4;5~7Tahjm$C&k{mWPXNCKPW}Zg6H^jdw z{6P4T(B(V|xfCH^d6DPqE@BH|YhfqhX+o1i2#u{9#CI3Z{iu{bM>s-wzR>I*M!dO> z0m~IWU$|PhMz~&hgV5N>LAu+;b0wJN@l^ovTf&{fhlM{Baw(p2=K2TRC;nGLYs-Oq zXen1KG}k@wW^*>M0k020^Aa7%*FEH;LUa8C-%Wg>aDb5e&naKmhC_+MFA!cNoFSYi zG}lR_UnBl%;SEA=CuaUzgyuR4{$BC-3wH}26#hu~gzy>RUg58W_WQ-=x`}+>R`_Az z2g1Jz&2o3Y*DBjre0l!i_ zw?VUhHwZTgHw*6)-Xr8jY05t&+#@vCX@qm;68u(lBZwLT<1X>8$!Uk*ZJj=yIg2(L)<9-HsKw@yM^Bn zn)?CJkBWav$X&*4*KdTc3hRDTG&O{RoF||PdHd;ZD@=XKSnr7SSp+;oGYvl zRthf{Rtc{WUMJin+$@X>zb1S@xI_4T;SYq53!fA|C;X-GW#MbWw}pQc{#p1JAs3(6 zpJ8F9u%R$dm@n)o>>}(g>?Is194tIfI8r!HI8iuFI8%7BaDkBe60F}>gr8*d;~vS~ zC)_FguJBRekAzPOpAqgCz9@W6_}{{V!aoVEEfC(jvYzR}2Er!7JYid52VqxX58(je zS;8XWFyR>CIAN);nsAQrVj;D5D1U|UD&aaIm3bI%ZG+q; z-r5GCY7gTd68=c|gzy>RUg2+quL?h{O^{}IKxBC>h1S+bU-8z~#}M&jg%gBSBVzh; zAr*$mUoKoDyjpmZ(AxH(UJ>Q*5q?X!Q~03p5g`?dC~s|fydeH1AytVOZ*6(JFW%bn zaPh3n_!J>Ej>zW;t?iBu;;C)K_`brkghPbGg`Is`rhi5Fw$R$<__KIxn}a$^l()7xsG~&Q+Tx&&68STQR81m3UP#p> z@^ghtgv*7ig=>U23O5R=#KiRX38}(!`tx%m0Q3Sp&ig>aQ{o$z{L z-Sv~r3g0UHhVTL54&iR$9^vCcyPna6Jo+$C;jnSgt9N}i4thnSJxsX&U)ZBZ-@bjL z(ZW8xd;0R9Y~$d;b|?g=U~dCK8wY!9BRkS+(zfoX&8mi-gFScD!pbmg9n3B7G|#!E zj8+b|XKsAG=n-S(z&)51YEcj#{_ayM=X*^j+UF z<<`u@Sn)gD;7aGt``Rqt8`>7y{A_LB_Kbs0&J?ug>eR@_j9b%dUW&0@4fmG8?!l_k z5L;FFj(4E zKHvI5-wW76-}*t{TiHfy{h;p)vVMRs)Wd?ntNWZgGHy@b8oqP(&VrbCXLeCJTR63S z`OcxRAke-DRu4Yhm$ofs^CDvbp(W~=Qp0wxZ|QAv4&PQC*|zK4JNCVb*0nUP$=hohDo-a2cix9yZz>!QkCjX!cT z8gJ&zCafR~DVpb5p5g;kl7T3=5_3C2gph zLB5uq5?XM8&dUN|L}i(N}8W9%S!;j|n^M^gUAut*vgDP;!%aXXkk3o+qS zPsM-eQN|iO2qC`3^6emmenf$xmokHJ+Ia*wf_-hsF5I4(hrcqcj34~k*apa$hl+(> zG{z4yzEAo$zEuHZ{NSZLlhQ1ozU<4JrS?~hje#r}KlrVo8mwk5UNaIf1HtxWv!l|V zW{#m2z8wU=240I0>XwNbgj=vzGOlK4q_kiQ{2HX1@JwR|AKf9zmY0Sp!2gn8+Gr8;J&Hx!tE>2cZQDbcf>)?_H2Roy!*^w1Y5$L^p&q z;u57hl2u+vb|cwQWI3E0{e^jqCi@iG>+t8E9|6mi|3<8lJBAf%j~>b8adnOP0k>$HvcQOm@ zi7S3ChnhR(9ZdClX)=XFzrKx`6dwNQ0_xS_$Ckx%japZylWn#U!{3oX=UR#z53+2E6-FHLB5?)o9Hsv}O%j zvvgDP^GMN}CAVh5tyyAgmX>eRo09%uOUl8_)`lgilnBTIc=uzzx;$Yiw6R!kDK@<+ zWfY`Ld-!;zQrfb!b1+Dv4}fsH8)E=G+|epF&gXA|ywkQn{`jKPm+WCAITCzHpXY;? z({>X6W+fyGjU)$&FX{6KjN}SP-k6XqFp?a5zNF9dg{G6Aiz7w_HNW&hMzRlLd`X`l zMoG+DoSRQzv><4yz>}o{JPdrY(So40g2=Jf3exLZE5K{+q!|L5E{L3wd8RQ?kOg)A z1VhsW32Oz}zEy;Okid8A zg%bh?AoQOIr$H3TaifS`4SmHZBC}vPL=w(VHkQEX;L#<#)8Z`>$d#x8Ct#>zRmMqhLlBr1aT0g=%&Itv-SFr{!sC8;MV!RzemLO` zKYW!@6(7pk$C*MXfj5Q=NR;`^iZ}^Qe8zAAiB<5>@gvmu;T3Tb518;0!naNM;#Ki8 z5}h>#ElD^YR_ZfJ>X3^2_9gC6IgxZZd(CuayO2WjN<{{4v%p_@DKDNH=aDu z(D3IG_Yd?U&m8DqAOL#5Ve_@{7r;PGiU<0LPZB$xT`~fgFIRH>XasZ%&|NUGUJ-t%`GCe9sTJ9U3@?cmz-Oe4}jOq-LfVO{K(CbHpwn@QT7< zB43=NFgu7Cj695EW+m`Y-X`RjzF8JFI{E&PTDHmzseIE>7Z9k;h&+loj5L;u0%N(z z4kOAW$I%70*-#FL)dM+}UjU!wRLUg5Dp&+y2y=wCrmb{9ag%9yUyIX_z<%R|Yl|Yy zvWiRw69^;V8EhR-M|OcVGeEk`@Qa-lb*vODb5ipe#+Jw6ag5pU9CIx3`BDG;K`6K5 zv0RY0cq*#e^vK>gb~CG;<}7tG{{Hut#sB~_Pe%o1rGRV{9*WFPYR~*Q=^pSfHbP*F zZIo?wAhj($QG)G)fQ(-k|6Y@|NpV(LV+32kqH75}c`=<59)~x&uq1fSBAoCBJQKqh z0m=7FOvwz?kY_El>L08k!E+Ot67DnMP?;vda}(i&z3><^gYCI!((-KNsfO`MSPXBB z3y|QchH%1Gc&6pl%M-z*CGj3S@+TZI;Y;0k;Pe>GvD(u=Xax4ANy|PokF?NbCbA1z zfbB};iIy72;pm?#u-QU_hbQD*UiAj>kfB#r5jo|CoRzEXoJ-msKFYI9j#N}&ca<_X zQ#>=ooJ?Q?Q4fP`AA$+of`g+Ij+5X%959hMi8p*ED^B7=pUH`n@F$D$gl6!_i4Zjv zSh*@r!aoPiMS>M&!9-RP;Tz!{nTY-9OT+A9TfJgV)GdIwaWr+Fo9l})psQKjkH_BGP;|j43 zu+5N(DGZ?;^D)!(M3TA6{-D_n)(cX2|fizKM+ik=O!9WP>M(}MIbyY7|zLP4?Ie6 z7*3iMz=0$vD-)$7VxD_D9y`2v)56Ip)mgcUx!8#b{EA>{`N#vg!iCL0|3)C4bsa%; zg69dC=vdIK<-_o--H+jI7a__x#ytZ6B0M{TJNVgR>lnw~kDTK6!taNttaXeF=551? z!TL>tT*#pb*pPcPy8$$lUC`(($E{aM)Iq5K!^frPFP$~pnR!NO#o~o?7f-)5I%nSe z*-N5bR`lt8S_f#`Pr3TI(=sOyak_kws_TB=R@TE3jP^&_U9aT(CO_vd&>*F1_h^g@Rmk9 zQAvG$A(h$RJs&#k)Fi*DFgkT;dvEC^sE8x{FXtB+RrYO#MwNYFM{mIz1Rp-X;H#4- zPxe+8KrOuzpRZqgUWe16kv?G1pw_K>_eDN$_BaAHb}Rp_F$Is#?LN8P;OD||=RL?V_^9FS2ewx=X+OBQ8(|We;>0K7>?8OR9E|Z|wZgV*_X5d%nc0apK z_jWzt*$_V`lS`91HkZ-e+qG`jwtLU6?YnmCaC)J4*`&_iWh0DGqc!D=y*R#je=~I4 zC)T6m?kn2*9}F}{bc9<$$ePgX6Ff~x+!9eVWZ z*(cg%@$C7tVLjl~=+q%4qr2NFq+9Q4{kzRrJbl5;^628(%jPYaw{StUXJN0x-u*6& zcDr2uBvlhMvz_@D2?6HXuV#_T8jdvRf_abhma`*YUkCB&S;8U8Y@ z4YB#nL4c(h_X5`AE6j@xU(&|S02?g#?bBgB6MJu1F3V#(h9bwFm=Z&qOznFpmxzv_e zd9nu|VK%>8K?n2eGSF`y^UH>}`Q4*5J%DsGa0`4};P^5>`kg{6_fgyWb=n_>9FkW6 zjJr5mzfSuv5Nqp7!Mh>HM``O=Kf0&kgYD>ncG!N#o0CL48i5W}+j%95*Q5xu&Xz?C zbeFT@l#|nG{|3fsH=7yI<`)PuWH9{m&}naaOaZo6{6No~F-ZXrYk)!LnGu}~@yy5! z@*G)7=b4can!gGZqgj^tEe5r7rkP9aazg)ORxL$ahaI5fM;V$7ntJB^Q1Bm6DJ%YfY z;>QZhgbRgy?@amYgxvl^-smC%e<1#s!q_tq$_$K077gP8Iq0ym3x=Y0y-8t}= zOa3Z_8{IjCTb;SB3`f5AEB;}j`Mxpao)P~l5!1|D;?4Jr5&r>sr2j}rn)S!~e1lDd zRtK&FdH9&Zr-`2_G&*ibzf|#S6~10*blMUBgm|m7W^~vQ{<6}&MMOUxBH}n7RX8UW z@c3bktCe(M>~st0lKyayJoC zr<;YF75_EG8{IUd|BiS}Ge#cWY>+cJ({qj{<_U2bH+(l?p^(>D%Hc9<@EqZJ!ZAX= zji=mH;WQz)gE4%GaHVjyutvB^c!!WL=$OvTm%#hQe^>aWuDRbow{U(&|Co6kxLy3+ z!fy$83i(=^@{b7lIUVv(3Ave!JYP~1&HNAiZ}A6&+?C3BZtWu;6^3|y0G}#sD6~4~ z?ZtNz76`fc%yef6xrR*sd|`=jve4?B^Q9c+Dum00mkYVmjPdJ)#-3WhT%ogSf z&GixawiVw=Xs(wC=hjj7*IB|M;V@x|@B$(CmQsG6utI2T!61B<_-f%b!s~?G%E|P% z3AYKYPC7TMGX8tQM}5t{2h_yOXF2}cPh z2}^}Dg>!{Vgv*6j3$GR4CcHz)9mr;U2!AAeLimhuukhExmxaF35$SvXQw~vH;HYJ}b%ogSfTMF9*}5_RrqDXHNvZfb#>9VDtx=}o5F7icMBgBJ|_H$(CVP? z75{7D%fkN_z9r;#W%k$q2)TKhywyGD7HRTPAvZ#k?7{EF}zq17qhBK~W_dxhT-eqZ<#;m?HJn$P@S6TT@tAhbH4anLtY@hk8psH>!M6wB;@9P@)L!1b;~bS_yXZF;YuNu0GR#;;U?i`;a$Regwz$F z{6oS$!pDU_7d|I^LHLr83I$C6uJC#Rl;iFRl>T@<306U*M#wS|6$h)pnKe>Pkp+_ zJ?qy!?%lVqRFywj_c)4k87`rF+yZYkYQGzaKU$mrdg?Z}x^*lZb2=<9T2q!feS2-z z>*rKI?6in=iT(XAfBXCFvf4*m^4ZE{5q7JA?v-f7U_ZnJ+dq6`+C2Zck*6Rj9NdR@VV7NSwH`g7UdfU(}ss>r*C1gSM zoh&IfiER*IaYkgXUxU^_xd?5)b`9Q%XKWaX;G6=Nxp&SQ-ne(xK+J-TQXJOEIP??x z>I(Lk*~kl;Cvd`b1cjY(gsz6%;ct}kw}d5j z!kAq`$8V0QXOGdp^**6XXJ5Kxw*8Wdzx8V2(i!t-2fwXyQoH5?BOuYo+;nw*nLom&3K7TWQNcds^D(C zFU|(1ESzh>{Y{+Xtm9lZBs=dbsaK_}4PWhD6S@%-+Nb$e2e!`@U>jUz!HEv=7yP3g z=$}^b=oRzMA7DODJ-?nfW(|rwl!L?hLne0BP>w+t|tn;?4&h%&!Ld)gU4B<8z74@1j5&kj`r4^)?AP zTUG^lOEYQ?8qR$-*4eoE2nd!N#kP&t5yo;EZp*C#ZPS2sdLtrALe9or4nCM4Z6@R( zjQQd5HId&&&^8T7V}G4;*4ell5fIETCy*cSC2jrg25r+Y55D^z9|*AIcEknqiy}XJ z+|cET{C0q5njY|UTzkH!&T(V>58#7xT$5YG1agd{e;gi%phCgUbC4Tg86aioUWB(a zdEUL-I*@03>Gs11+tDS^FMOV(9NUG%nHcjRo&HGl2NH6&EMlN}P9)oL1|yKSl*roT zmjh&(_8bD~3`3_4CLw3@v%JM%_~)?~it|I#*yAfb3$v+-Ml-8JRQs9h$W)S z4f2?ij|zGG$e%9kE<9T}R5)BXTF8egrkgCBE}Shi#|816rzy8ac(su8EyFhow+Och zcL>e#f*j{R%0DJF<1NiUHyBPwwC(NBegV%jq|TaCe=IL0Tw(9R!oEFw_v&||HK%?( zd-%eiyyi6QQ?EI#JZ8Lm(AiCF@&GIvW$dLabJzR_B`26Dv_yQ@Bd3R-&pUoR!{) zu~+8)4OxUbU?s||Os&ZcqnHerUrLa1s;&^Ab90b@D^VjzL=lq3+PEX{0m(BXi{-ha zSULx~zY;Z?EXQpFmgk;tinA+GT6+pN;0fv$KLRnk62;Xzex1l_>k+;Lo@cwbwbRm8eg#Fk&i{ z{77wb4J)9i=6~?kU#&{4p?tYcW%SujW}Pb0XPG;MTxC?hpD+{A6_Huv&i>anHU%FB1#gxb5j z=lnlfoBHB^P!@g1XHQ)E6Hl4FK?fb~8;om*f6CeC<+^f=qw5UMC)7`p>j9a%<=R^# zM45YRBE#@Vl5jil_{#j7!}C6zo_q48FImJZKwtKImY64&F%Q8QX2ReSU@4-69jq!Xo3(9fd*CHm6V;ueC@Hhk&3U>Yix!`&PW$0dnw={Wv z^TXDGJnKidA3oSGWr2Qaf;ig_9L~g;2kDd{(H}_2*|La%<~cpGvF3!pJcJ`_lV1*y zW!iHHq*H-T8%#pZ=4W|}!SFBFratT1)QLYx>#t2=>i?YAruyRma_#3_p?Q`DKT&+C zaGr31kn;f3tr4yl-X^TOHnmIPc5Uiu@xK(lB>bK5ZQ;AZYz#1#*IL+Bc&2cKaI$co z&}>9Ox+}=z9KTYymWaWAn{X=;a`%Y8U;KB)KP>)n@kSp6^1oL2AB2A||Rkr=gH7z<%pI)7p*cs(K#w8~F;KDAiP3{bERK}_6ICz|pwL8z(8Zh!+f-u;f z&jc4*%#mR2&M&60StmB@RIoe0fihQ7#@d}PW8z2(M;7ePe-)6lJ8u@WMpD4HJKvh+ z`F7{2vE;8)h1OEQtW&}6{2qj-gi)#AnGC}`17LanTvJMz`?^wZLQvSZJf9Z+BO(&( zRO|e8s-}<%CoIgTb0IsNurQx)t{c}U)~TjY_=aQGsS+0E)8AxSHzn7pXmBrFqjjnd z$XM%Coj}sL&5@m1ry>zWNET}oSf^rn{yNnqjAdTFaFF5bEtX%P3DTb( zdt}GDls}FCCujQW-)e)D?0@|et5Q?Etf;p*dP=8G-tuUt4ug)}A!U}8d~-;jv{j1x zwO~(*V!jO@f87bI6ilC3N;&!Er^Hs7|M>k<#@tq-2f6N(Ttqr17*U_^ViOMNzh=7yjQ<<$mh$f{PqZe*sqJ65U+N2Q5bFP@^{6ho91-lrs_uH!rW343jYS$!Tfkz zY4hXb9FGTQ%_qw;uItrLl7SMy<`8VRroSIX&2pj)8vpN9$3; zkm&a|b0F(RM+`L2X>yY5QRC5Rd`oSe&Cl`{gW;dYdQ?lBu|eA_e&GMcUa8h7Dko6~ z_IT2r%wDM|#Mvjj4sfqjKcICc-{am3nftDPyj7~7U5&yAeURB_*(-G#(s7-H^&#@u z68V@)93h-2{Bk`C{epAq)2>Ig#mUD0q~p31M=kNuwmtnY$jS2zId*SUuU>tkNp}+KP5pi8Pu?5Vk&n5b zlRn;$k&#Qyw4&hb$n4>;H_F&yaU(a83#FV2AIry9>(dblaJ|4HBeW{O!?qjEYsgHLu zmgfJRmYe4E>iJLUF<>Z&D z{^M7u5`FeBSe!EJi2kzHzh*5evC#N$w93T$#S^VD@wVe%x5mU%=u4eEbg^-`VKDAr zz3=IIJa60e3f^PWlP`g{bpYvh60wS)IIa zVErRAkl#ko!G0N!f^raMosHwW<=}cslR$oaOtba78?;TsJWf_8kLxq`xS`7v`SI?R z`SpOOqfXv^yzP=>9DUt=PqdF!-#XLdkPWUg{StEZtuwu-d;!K$t-#iS0c&KU!xRh(v!dIrx9J&xnEMIaw#U&NK?0Hn^Vr0zrnf<&gP2)|t2topiQW{E+{R zbtbOkB**KgUuSBE^z0K}3r<=m&%cqX*J`=h_r$6HbKduK2I|N4kU_#x!m+}OgfoQ| zLOu*K-D=_W!VN;RZh?5SUIE;#aJ%n`=L^&ST==~3*TN%07oAAC9AR5wf$%KhIANLa zOPxIQ8|Jh%>__0$Le973Hww21w+VL$&GCX9=Re9nCgh63KU#O{&;Exz&zL&vPJQdu z$t$ei4pd>!e*OBIg{Mzmck0h|hrqg19yC(By>qDH)jRgqMs|2LYuCrh!}FYVuh#b8 z!8J)gr#S<=~c=?tkd8o4#pZBeXKS9WAY%5xd?T$DFVMi2e1=oY?KLci)_f^U=Td zhutPPKV2G+J_lz^l&4L=VO^CRbWTS?9_y-Q0PhFR8bL+rXLuLK^ad(W<` zzQsHuDSZs2WdV}ws+?auUM#}CowIY0RoGuw&T~}p=QIG9}Nca|J6%I#zE*+4v zm-LP9PZ5(E-f#YE@SoNsbWv_G8W~wafyCNsge#Sy#M)}a*ax4H`#O@q%2^~0JrbHJ zHWIm*!ilxj2=_gPW}9q{ZmF@SmU1~m=j8qoS)_lRbY`CG{RTy6n3p+Od8|g}C|ths z?tn~256Wccy-E5*M1>lf@JxK&%n9Y>nUrf;pGLm?2b9mvy9Ys8^PErLqkoC z1RDMt^2uiI>BeApf7GA~$^04&NYvmAKgU;?`Vus^hL+<;?B9{X0I8z`KI7Up(Huosd2J%w-NxLuoyt0lk3+7b+% zyNO20n|=>LUq@Usetz0*x()x0)4*;t?A7=$1lx2KhW*A;qZ1dx&ku*DP++{$iVU1yPDen5I1C)`4i&gaR%31=rLg zGyvl?r5(dZD02kFOCVa=%=7r=s9J>N%>i*P9!c^RgIH=FXiPO|6_6En-+mv}$Y(Y3 zS%rMoAfKh1l4%_`pC#wB;Cz;t&(d1i^robTSpZA=1Bliv3D4kcEb|!;?{;=iSVT5n zTGd;GO>BzbR%%lO?cb^hoPHOekk7839kdXbYApn&HFh&I&&WJ8g@*qk4IE<-5Jm+1 zqu}%c*JnFtMKc)>>+3ciQw^91Q_`$oR__4Q08F-x$?jzA{x$UN0V1@nwLyF~&EzBV zg0K^45{u1MUSb=o9I;JW!|-5<{$?Ud2`mLEkw?P$br?rDA0FQ}Cp=@)j3e00#+l6g9L6P*gHVeN zQkb1aREra$Ig-V9>uoeh8_n4E@UAnJ&=QUF@F}1;37(n=C*&eye21Kn2k$v6R>ev1 z({@MwxDhS!F&?%{HQ*wjCf@Bwc&>f9`lD`=Nww^6OqqT?%UPpu&}L65D-dR-DA+K2shi zvEOIr$JyR2Q`51@c9pPsE8$H}Bv$*(tT>6ge5O23Vwca%kJ~|rftze|Vhp!OHH+cV ze*~V}$UGb;;SVBoGKn_u5F!-8;~Xs}`gNQ_;GpvG*=;kRI)cH;kQ_r(l4EGRt%oTI zr5eYYbcAn+vp=;%mapxw%4r{GpnqH^@YwmM&;*kPe@tc`ah(mLScFcSQ8s=Oh$--? z*m1VV$&ZufRWTLZQshp00elAH@!|1&hOv>n#o(NTENLplCMVq&9#O0e+XoWu*7;G) zw(*lN!TgZDam=?Pd@Aai+A}{+I?v=VnUD{UabFcDal{X2A#7IQ!}2xA>sI&_XO+|Q zlsL)l@aS#A1BRSL@XxOmt~tN{hybSO)iO@gMB$IIED8ey zV?Pup%_E=cTw!?9tiO#9raSSeVRNnjijk~QDQh$g9+!ivI0;_E(5v`2E-5;ZqBG!K zqlal?c?SLObtFsUl!kfR&TPC^*L!)Ttbbg`T?=w6JWkf+ff~nQ6ETOc7;(li&565| zvHqZ}?;^}tc23CY5hotsE3C$i@TR9pY==irvrhi_O>{alTL2%NNNm-EVGuEn1^QK+ zXopV*ZY5HCc0}*A58QoBR08K>3~+PHpB#w1NAPF962{Jl$0S`9C*g}G?!c0w#S~oy zkIv<(>d#k+9_@-Cf65$pK1fapxRBUNBx6e%TLSMntE%E8IP7s|9WPp(%qVdVZ3b-oxIVd~nU_Fs9R+1xE6 z6VvF|;}ovYwF!gNrpIN1y4rOIo$jSaz00DV+I!2QUPeJUs|o* zu%S0~k9z5o+IuSss=VAu2!5wHI=VfC?(bgEYq^&>qNBH94T298k63pYbWTH&&1EN(;Q% z1HGvQ-tvOhAzIfC+AuzWn$nEvWlC-!bs6k)XpYgWS-%ybea zn`K{l+O))853DIoo5AndAG39(&YmE?&@!K#ubf`N8ZVwbeb$&cb76|&U7qicgHFRVRTh~DnQJF&C_ zEUA!|u;Xs6Ak{f~^A-d)k|hqj$%~R4eoN<1Up$c&Fgw5e;bF`+CGBY?w;%E7`>KsI z7tWqD$Keo~KYPL4%JP62aR$y_Fw3z9zfWqLnm@}dS1(kIo4I&;<;?Qo3!GWA=TE-qUT218N3V*kO}jevnv`|n_1?9i>)avPTo(B>w!-VP z6V6lk3%(tx6}kaeAl&czuD8&Ff1P)nb_k%Hz0B8@V;o&)_z3(b$#sQH-ExEX1oqBi zxa0uF4MxWNuCaBt+;b6t70`s6)DAjokZpz#iZegfi%+vQ4M-=B!0JGNCFjZS zO#{-|jr@9$kh5`X!3XoJL4Jb~#{5vtM1EYlw`o8+zej$j*@GX5yA50^V z7~nkBtz-S@xc4I1ju!*{jCIyTI~suwRNE;>l*jke zEZ4kp26huaKzOcjtZ=T-ys?J-mEzYCF>zlntRdp$;espCe1jVDJH>yG2!4&_@eN4!UIC{EojJ_Z$Tqp7pDx{ zmqkQ=IYRTzXM`6hzMpWga4Zqi!Bp|wi^_cLx1BE~kNlP?yh^xESod4b4=enaM5MFd zW`14a?+8Cq{9lFU8_OuyepC4jq-FYZhzK{|RtC~B9LWrFW+KnIhnOccYZ~CYiti!p zCp=Slj_^Do7de>^Uu_U)3g-&BuEcO&*NImN*9mVD-YncA+$Q|G@SDON!rekMFCbsL zN9`$vKP%iXd{Ow8@SyOB(99di=da?;-b3(aT^DFJH~^dRya#ffm&hFm#BRbq!T~}v z&mjI>@!WSn`N_gE;VdEdEHHk#aJ6ua@H!#QR#EO&;TGXngABT}`TSKF=6nU7YsExv*CI9+<_n|3Q-$4xeT8OTM!IvvpC>$D zSR$M(yihntc(HJaaJkUT)5!NK@iz!J2saD23e7wX`Tr9CJ)xPm5&jeLKNId1?iao+ zd`g`Vcg3}Lpgsj!7GD(ooa<{tL<0O9$<65(Xwg+lKBp?rmKg>aRS z+kqHgBit(7E_^_^L%2uyxbWw~=Y%f{UlYD5JRm$Q{6P4zkhip~2lpcpv8}>j7hzXn zFJV97U}2GPq;QOo8=9Ek4B@51MZy)rRl=_buMyS=HwojyuLKdaf645Z)r>E;7b{Q@BI8TlfRvW5S;bpB6qZd_nkI;TysO z!uNz92tN|?(TU}Uh1|wQzPYfCu)UD`+8EzQI7E1^aIA2GklWuVf2puixI)NXag4uC zxKVhkko)8q|4rcz;cnrh!XF8_osRPRg)a+V6LLcxf#$o~EBf^Hl#==&@ zw!+TB(}lf+{e))=hYE)aM+>=;kL8sK=L#?`Dk zMCLPGI9Yh1koy!Ff0?jac$ILIaI=uR6e)kdkoytI|4{gZ@G0T*!WV?xwn+JRgolLh z3y%u_F65R)%I6AO2wMxeS&{KQg#CnP3X6pNmJ#K+r;#{SI72u`h|~BV>U`iZne=s^ zE3kZK!lS~D!d|*xH1Q3S&mZ>n0zXT;uzSE3Zejg8A_MyL=@~WdlXXNMXJJ?d?QNh7 zo_Ty7k!?HjYVx+`-Ffq{j_YzaU0R;Et;sFhk9w84cYd$D;jObGbDZr*Q;G*i`owZ- za^tOTJ*6mTTeD3Uwn{r(J-Fp9P3~;5A@yJ^?DlWAEqmjjRw)Oookq7cufgVvLtn3M z7*DCW+v!}Caya5N-qiHA@P@37UQL5r!?&kw$t-VNHnMzN*>&YNmw9*OY#Ub_DIHfE z9_6&(jBl3bK<8p(?2Z`od7;|fbY3iU%Z^yrSi^1ZoiEfndwyN()I4)Ee1B#66GyY$ z$B(Ame?|Et<)K^LO-su|Tc0|b)!~Vw>Fx`)kv)j(;ND4nfoG1U-=BIoD;4Qnr0S4% zI4kYNeXrJLRX5)DYVG)%Q)2Gc9Yu}eRXgvFxv$TT-5r};8@^;xZFrV`9#AP8WtTGnU=LB^|o^l3<*EiJa*umloy+iIdE{|6Gi6)) zZJ9M*yus$w+Z&aQFU#ta)ibMaRzJ6YWK;N-tc@wRdbc&Gsd|6;f3>=!+1BQFw%FEW zbN1~Witcb)7quzMD{4{H{FWBCHmS+p&~nSr@4Q-Dyyw;0(&|@hXVo-k-OkLtz2Vkj zz_J)#v3Dp&ZO7M!r@8~4KrR1*T0XyW#DQ}%vhO&jHhjN3DEnsUq-4FZugTVycZLtH z4L8}8yDcxiw9U68E6SVhZL-CS6~>yB=a-EyFD=_tzO`(B`734a0BC!Jyu&%(VWjKj z=A%|kHZ?uud8tTI0^Jhm{Iqh<{Agbr>0rECJFuqoE$6ZO@4N55IPd4pc#{p~$1(5+ z`XMIR{z32JR?51Oa}Wf*3qCP$ zCzA3JnMm5bfTRir9}~S^Ozo>+yiI;cF%z#~=+GG?;T>;uCI0cPuS3kojWj|uv@y8( z0@@g6Ss)U=7J(^eK`wlidk-MxhlmcZcOLmn8Zi2pd>N$aTxyJD@MH2Mx*;T!OJnW`mbjAa z6_grDmJ6ksX^b7U6I=<{ELOrjpRu=)WhLA(WU2jK;sHF1>IU-k<{722;p=3tSc#@Z70fb~sA*fdpHH z**J^KdVcI_JHLIqh8!Zdp$|cFTIi?rX>1^%H#Eo}1XYZ(Uo+xs9Eh)x~lndw}Iu_JFW9v!f*# zD)9B~0q1b>oGUi7y$Q$nG}u5y;4&Dt2oZRZfURT#cLZTC-Z0{LLtinB$lMqXk%U_T z3j6B_)$nP~hT7Gs9l~)kS0w`?aWY)ZkwjMfJ}{5KBgaw1J@D9kNq8UL>`NvA0fyTO zB+?@$;rv>ZFiW1Vp0i_<*!G>-YPWk$$05uLQ16Gy^L0fn7!1XZ$_$nBTd zkw@_JUhc+i&Cn3eB*x|8zYRQkl)(C>py$vtw%I8D!766yx34q&d2O8evLw?Q;P4u&Do#bh_0;1^O#80d#43mK1e z#{Cfg*(P=}fmxuC%4B^_R(>TDi5^BGwiERxuo9@ZtqVev$uH=L9R1`MK+HIH-4=KZ zaKa8lP9m^v7~iY~(_zCTfsMgN%5a!1pLB~rG)1VSxi9vAziU5abg5ExHA6? zBYHuyjL9s6y=2aL5`GzznehwoH~@rNcx;k{x`Ny~pvlqUbD8hRKLelYOu0Ec_2w}9 zhpXI{{}42@x4dmfMj#KC%T}a1B{zr1-5j=uEhqyC<4#nE@urO8o5N#2TY75EoJ{%c zQH#^yar_B7Np}QK(jCE*bVuSOL#^NW^ zCGZ9^1ee(bO0U*9)JgeDIZ9r%!fFt3&-oX@5=lD%bIJh zWo9ETdtz~`$;W5ypfz2YVtUbg#&HLF4Wsx5f!8|f zEdo){t}VzyZ+g_rFKE~PjP~A=sFxWn%x~u{1yR8N`BASuMZMgpH^rx;UUmU<$&J1> zvb)!?pp&;U+TB}PaAr3zx4>IA(94LL4Y>F(@EQ~p7JBIg-il~nvpsh?Hr_^Cweyxo z`}RED%PR27qF$SV(|dOJ%0_stM&NnE^%_n}ElBkm4)iKfxs?S-(4F~vEu-DrwHbNV z89ln5)y~^qRp9;BLBU_Gn&iEPO|n3f`W+`yfb`hKThIo@3^IWY3JB1_4!dpm*Q291 zx6*47?cmKS@J^l6rhSK2r;O^}z5A(N!v{tU^PYDKye+Fogi^837Mmpd_QsbLv@O!# zp?ZEVC%JRcu2&@XLE=z3{#O}59rsZN?aDo=jjd*rt<9g={#);GHC<{tTl;{I-%jiw zg>#lJ#xCK+w$*=N3~y22UN`{%cyp+KX4%cK$L_05Y-zuLdl&esinHx|t-W@VO|l^&2@uYkqlg%ia8^_fF(M*_gBXD-XTc&M zprRs)hzg1t4q^yM&{|8CDk81cLz}8qYM}+S7JbAAtyLk`a)Oj8DG8oZf^A&NyrLa_EWAx?XF2wX;?aX+hPkNFQF z1oa{qs(1wpXki`$FQ~Ck%~i5<4fKvTUUi4`t=@L%^|b=X_HlV0A-EnKXN)GA^+1vM zdNfAd?#qZeA0m@u1MR}LaUlb%=Pb>^{)a@4SGD$NpLGW9J&*mg9n$P#?OE9}nEtOA zugd3mi6v~t)J}-6fbAt;a_|+y*XCLt#a?JQu|A+b5fvY@q zW8pc^jM*cx^Kx60v_)dmI3XM)*fq=;MV_;m-a|Z1JWCuVjubBzr-i0O*Gt|cnYVqk^N8f1OXfp<>hs9~^Z96kd{;ao z@&IExJ+#SIVmlJ$PmyfKfI&V@vKjjY`CQ3#!K8kPWOEw`dzUGFfzq#$e52%Ll2=Ja zx0-(9(Zc@X`IO{-OyU$^Xl_d(^Q{8Yx$}`cFOmJl!QwgMaB-B#8)NF5{R*5e`7-fZ zk>`Bs-6Wd*3-VgYm7>|dkj`^3^`8)*7I}_jI?t)(@5NWdH^u$p`=Z(Jpw9!6<-%f` zm@ejsd>}%-PNE$HnJ2lYXy#{x-ayHt#IfS{#7W{z@p5s2xKO-7yh-Gn8@6MeX!cvk z_e(bWE#$`}KP^^^FN(hvUlsR?Z;O8xKN8LU4ZC%c|1L(jpCLUeW{J(jn8=4Z)HC}( z*j+N8@GzZ^c1XU8B1ed0#c`rJ4v^2^ed^5Tq)iw{!rW^ZWZ~4koDU!k1t97 zo%ovghG@pHL;uf``A(7L%@}s@pB?MSx01AH#<+uLN**MhE1oZM9%t&8h?j^{#QI|) zuU7hX;u7&@@pf^gSSfB4`JR;ZJt{sSJ}o{cz9{Y%UlmU@R+2AXY5(tHI^vYG#I|Aw zvAbx;NS-CxjJZdAwB!rLDdMGKsd%HfTD)8Qf%qfwm*R8cE8-u;KZ);)e;2=L>|!%q zKym$AigwIm7s-5`%=|ONLUD*VLL4nl5GRT=#mmJ7;zIET(T-VMA-P;!C*C9SeKy-; z$1MI_@-yP|;tuim;w$2t;(qacu}1tv{9JTX{Q8o_Mq;MeTx>1!1v}eUAodf_5R1g2 z;%MGaQTOMh#y3B>ltmK815HC&xm9$ndN)xO$p7)O*>{zR>l_hW=7 zYC~WM41?jkh80iLCg(M;{4xF)*G6_?Y|$3C2(Oq9t+-*tAt!>+z&RZ8b{%k*x30)p zz3V_|`K|-W2$AKji;$C+x@uz4n4+Sh5k-TF&MO*U8)>z#wiU)N<&;;~{c6Lm+KlpD zwb_tk<@;(oVwBdeHavgOiR`M4R%7Pf@(XGs(d|V$>h`?23!}Zd|lgo=shU&UkOn&I>UmZ*h-Sa_X=h?bf!tGGPag*0O>oCV| z^?#*}IJh^jMN!K7%<|u)c@^0!2OS(dXvD!c`@8EKtr~W4z_849+1OqK&>!rhZe;@x zo;#2_nJcqbjW~E9|BWnet*n(J4u06bI%`*L|LVr*x4zXG6-`z-N7LQt(ezNWihZ>u z)j8`Mu8tgzL>e59G}r}8yHIXl?U1r(54r;}f~1G&>cKG2=>snOqtDRN0uXb*En~L8$Eeb0N*J0#Wi&eXjx{Imh9oIEJeI`@5Jq`GvZhIye}{{}+tUn_G>MY^QPFVvJ@Rnu@k} zgN4Z9P~_!3Z7{OVsTt_BDQ~}iU+s#rOWOP*vbQ!|+;w-G3T$T&dt#_!P~TtPHK^w= zopx@!Q0^M?kn1`p_uM_;V3NB$C2tQ>@<-K1hG9Hg6l3M0j}96PDTJ~fY#iFtX8k8l zkHTJsZB{okBj4Io7Sx7Xc0%CDw=Np_W{-|OA zm6Vk)t0>#OY;PGy*ZFlE-m?>9<_6(G3oZ+>gxvz1mt0;{UI&pkeZd7o+PXu=z_bqt zH@SmBgcrqlIfQ?mikT8hn!}Wh{MUK1NlD?GL+__d>9c?-;iN}cfcHmU-l1!L>h5s~mtlNjb86-YTi5+5NXmAa1-H!xwT`y%5!WhX6n_W{Y# zq%*^GTTS8pZ_y&gCFHVW zy$_L+I%jS^Q(i^_;sx3NSHrhBlp12;=+(V@!bQ_4ISpsc znuljIAwEKI8qwYth@~Gz#C00{k`?EuV&2vG73TyhR@_va6RfyJhX6V}urlA;ROwQE6Ci z$q}N-2z0p3x`Za~HjTXmx>=ucWqf%a<*yR*O^}@?+zT@i+90@_T;5?c<#b#e-ruwZ zB3l{Z1FYSMG_$HX+~-0ZVcL=<+0&oI>%ZUB|0n4C_51QCluiA<+<=?d)X&m&SyLB&)u)=iu6aeS&?E! zxFU0D!m76Bil7%uP;3GM-K6}j_>Aer8=>s?qA#zdYi*H?orEzl$C|jsny91+t7=UA#F%LLFp6$NIEzP_*^&RtbiuEY?RSAM z@1<Yc<_Z1uA0kYF#KmG;Hvv|<_ zsnkMCuoCnz@>M@KEg6O^U)7htPuaA@mls2BQ;vdsofs_0j9|f)kewEXScTcl33F{t zdwm%y1JGH%N*D7>_(^N>SS$QMZJvWQit)n3 z$Y)Lb`eBAB$Mkp^M7o$_BZ=7vX4E1he8Yfo;~!#VdZ>!R&549?6@@zz3CUFycw$zO zNYz#dZz33jjPyi9QaL6vd7;xDHYpE4h+u3XQ`=Xui7y~v7-gi2k+%@y22nwL8H5VB0K}_|KcS-~eOFye>rLdlxg(ABPBp-HRD1M6kny8Nb8N+`E{+tq+*YF{{HD ztPV5I?Pkn;gviGT!FnhUK+CK(b_$yq)IsfL`KEUADlpj@yE=T~>M-NHp5ejH-_(~( zp5GY8)tDWN|B;Fs!2s4||6)dl`@)XJjEq9CtHAgje&+tguOhlRk6 zg0KbwgPy}xcC(t|cKwW??dEJmgg3@GsS>OLW334`A2Y#!yg2zfr#)&I{6%$!q zLz7`rkz2(ij*U*oqY0LX>obu}%VNd=r5g7pwxg z4MWa+L%-V5)0@j6Ko3K~h zZ}u>5VhA5BW@Hfpx|?9*Ou9Kwn9VRI705(@^MxBYsg31H?LmYj=W340XO!oDoH>an z5X_i-M%X;0CwgjB;xssxKLI?yqY1<(2xgvqM*P!!d{5xn`AoA)BMF|J(Gz3HCD<5f z`G!(PD$SNDCUnBtV9wwi)P>32i<8k_#(5$~wM0kLf{Tbe(}HVUvs<#E#xCkG%RBhb zb1)M3E>@a(2*8cY4IbFYbA$Pr$j2tMNj#|!_wDSD+hO9j*EG6dx1gA8 z%K4{Z9%M@cvbB?oG`0d8Yj?bpnJDAO9Ff67_1ekj3;dz2-%hG6LxBAqar;dCHv7!4 z*EK_tGzy`<{ozRC>6Jerc46ALnPIPe$3ePHczFGJP;S+>fgs%`nsGJwL zeB9I*;WPwx;zR^?ya!gkW8 zZ69s1eY9oUN1Mm9W!p=ecKK)5eFALRb?1wTSqR)E>|*VI5NLC-Pq{JKrZl`GdUK{WqNIHOZ~U7ca_Oet+YZ(j$m}hB;MT@AlH6h%YtiH^#U);c>0bLKy^wTT4D}ST)M>2o zoS_9h5wCWbJh-F)@qSD{zXU#t9a^7tO8zMwTAvTje0+6l?T{> zOT0VXn0FY754e$`k?~%G>2d$URO4TG9!_=cx%`JWpJBHj|DE5_n=#bO$@OL|fumvT z{Prz-M3#CDBe}zd^zweRc<8)S=^puvThgBHhoKb5btfI`$_259QXzx`l7z+jxp;x1SO%(f}j5| z7VG8m!xp~V-*LYG@xR(D@>qvNb*LSemGC*u?**6C_zvQ`pW;pXv`a6!k{i26!Pgv7 zzxJUI>&gfp3vEMF>XJ)FpFeEiutLXp8wUIwZ6mPF1MaX^y(I9pjuSXwnse7Bmkb@RW>R^A|DDB~mSlr$c#BCWwo$NOLH6Y_$Y#yHk1nn(=y*xCE_IS+L z_N@t&LDX3k!*g15F+wR}uN?89z5CDc*N^ttJ=WeP#My>C1TK9$;6BUl6p)$6@Q`Tr z&c-{FE0AUvtG68qC?3DV`x*4Uiyz}5==HV6K(>#|^9aH9*n;)QKpNKrZx7?^(HQYS zvz;#3!T*3XyRdy+$Ut{F)u&+Hk=P9BnFy?x_E~4p-XRSh2nJ4_#?s2Qpw9nlwTuxo#gu^ z|5);N$UbJCz0=-srR9HjDHaZW@KTX=lZk~JBeLMi&Mp!%C~c*U#0XLlzx+Vm(n+i#vcgv zZ&ChM@#o5aUh)ocuhQQZ&0Oaw|5xQ773=#8MRB5HzZpLv=(m!55(&AR!ZL_74$Dls-wkOtgMH^QE^)={HKY zbCZ`-M*ZuRze(~#lFgjt$bU-muSwMZ8}W6eza!R&hm`-ZXyzct`k6V%u{|2%0+IFR zkVtPWxr^jeCHIwl28nV-N*}58v63fAHgk+aZ@*1Ay=Zog|9CDfD z+r^dQM)5xJ5%DpxT6|vICGHX57XK_B6+abu(aH9h-+PcF;wiTlJBnRI^Lvl{9+LZu z1H^MhGoJzU>idP;Z{b`gy(Qw!;vM2Du~OV9J}hn%>4d=cJ|pfBcZz=yUl;lQf%<$0 zLH<=dD)Ko$)6KJfFonPWV4BEh-jw+)oop?(6T6DJVjt0d3#U->5OJh+j-i1bjP9Zo__n&;{u@5?CvTBH*M<(I|R#P>vVeT4j4$zO=| z{k}O4hITl@f}}?T*-5ni-R3$8>4TJBB#scxH^-2FiR3BbEOD;5NGuc0^%Tn4Z`s_V z^n1mhh>wc&&|v#^iTlL2#lMJ$#m~eq#Rg%&d_%FR*g~Yo2krM3i^QSgXz@aEqBvEY zD=rYP7jF>j`(4wcg!Nf}YkM8_E2Zxe&Gi)Y_DMF^Q;`26*<4RS{!H?hViMA5zkz73 zrx5QXIae$YPZ!S;i^QSgXwmvvPn2w~vkzEW@jpwZvjf+UgNeyBFoEJRnBPh758~^hxh}(cyepZ0M(n3g z#lMT5u2a%Pb6o~K`>mLkO79?^B+^fb_RRGeI8gH0;xMsTG}mj;n;?0rI76hL6YZJn zHSoCCYe-)sy?exa#m(Xt@u%X?#cJ_+ahJG9+$+8*zAu{VI@D{wE%S-e|1Q$!g6&Qf z8;MQC=3-3jD4rsA7tQq^?DUsRKQG!HA)4zw$m1kW7U_aPy*c81@mg`QXs-XDcbjDU zZJG6w&2=F1ACUYL@lo+f@fRXp%~{;MKg!6?5k z(zT58=OSIpC^r=8Oh!2-(x;4aUvYqFzYRmjGUk_vQ^gq~JB?uGN`NCp5B&NEbB9T}1kvQ63=D^^Ecuae_Ee zq(>U_7l?EcqkM}0?Hj_f#ZZ&B$gVJ0m~AhDZl9%GZf>DWiOcNY66L z_la~Tqx@5mK4g@4iLZ)#MY@VH|3i^ZVU+(a(shh-rbs6-%K0Ka!zlBM66A&Ac#)oB zOrImtA&l}8kq%*$?-J?fMfow2eqNMc5b<*f@9V_`U=Umc+ILUD*VOss$ZTB7s`;zV((I76Hz&J`Dk3q^aMyG-&5v0PjuR)`zK zP2&CHW^s$SRopH;+x`r@m=wd__0_k zej)OO9FNzq7!mEfa2b-b#T>Df7!x~+T||yUq+O0hBzuYj#QM((hAF*7oFJZ|c4l+` z!~5kN?T7K99evESKe7Ct`T4yIdiLm(cl>X#<>&XvLl%}3&-*immEe_lPlLoa*ebSW zmp8?{KiQZcrl`&M8QJ$Vt%$Dv$&7|~^(ZWhWUOtxvdOBf)%dC!zJ->#F0-;h`SM7c zqTBG5u$NnSJsRDWzPiahjn_vjQdg#}N?9GbD|u~FdCI!v%Cv=9bI)5idhTrtSI_+h%S{y~n)^bD2b& z6undQr=quuCKqifTK$<*yx}va?BazRK6B@W)^1$rt6E;d}-~6+jecs_{=>etJZBf;`3#-mu|~})lAeq;`5toM{Ij+P-b1^ zLC8Db-xH}!TAy-H^2P?3t>!>;e5Zr`#1;mAtkA=E@oNNV9cWm5uL-ZfsI<8|KOJ zzuT6zs_|XXwN1*KuFpDzk%PM%SM90|S6^Bf#dqdUFWp_bkEagk2v^FX7XV-Idn87)S%Wq<=s8e zd-lQRw8H3J85P+ZmqzBzXtz6hPvh37w7wnl-BfbEn+|RVx7!-fJLGz&KX&%Pkheai z!yczY^CCC@gOc6F_YPt|*Y1gK%&55E>0H>pFuFDav-+g$j;?Q9i2h6qA>2CXvpqSQ z<7O%LiG~&2EBd_;ouXJ#>xB*HesAIVbMIMr``mpCcg=PC(kAEdIlSj(%xQBIpZA#k zJ?!!~%jE-09+V4BV&WeUW+&8=#|GvVdH@<8MjJA%3IBCEpBbSfj*$)Z<-g8!9QQ&g zS1`LR|Mg+i3n#5)ws}z6_ePVFVpJnZ4QMrz@_RJF&R`QxF;7O%px((R(+Wo}d%XrR zI+*&s$1ut)Z{T!Bmoaq^+wX-_xN>MHA7grv@B)_gzYGVd5{XGaW@Xp94?sOBAOFId z$)=ETewT=_+W3o7VO&N3hO62S{4$34w#R~d`I|2>d z$D!h$jVMOUAj-wP9-Dw)i7R5{RHUSBqt-dBaVo{zs5OM5hmh8cx#zx&#C{N?Y=m3P z+_@Cl2zMk!&XN-4^I&%r#b+U!uf(A$oS#vb`AVFT_yukAl{h1D?#G4;dtka2YUYO_ znF&}Z&7{PsTrQwZK5aAKj2la74t9|!t8p*Pf%pfCFUG~exFn43jEmP$MAN0r_h(Ud zuUo=3<7+Q|Lhd38oVzZ{30HmbM-)p~(&X|@5c|O4queN;bGsj~)V)YgUrIG2I*oXC z=VM%7=OA^q$90V8G|EF_L0soU>hMjDZ^wvEqajEf8`t@WI&Z{vjOb)cL}FvpmMk+d z!(X7#*fhqM{qZ%C@QtvOISFn4hG`L+I`-po*!Uftw6rtRJgjV3QCLlqikYY&`TxT& z-Py?n(lxmNzK@5?e}7Vf#)%0B_y98VJ4`vi!vp@`W$c^y!W{;#J;WB|!>O>CeAvXV zFD6-z>G3j%6qsTo3GO$@E+i)+z}tUAX)-3HqcAm*5UQduBaz@$QTQ2}qaxudbM56< zS4dxkWCS?05_G}voJFNojGXDGvvp6J^ee(~M;h34cus})C!ywz378&3(}RqOi>PfE zbKLur2B{wM*P-}9g65xCLQ|ai137K3Nx}10W}c!nRI*@iV^;_Al>#B ze1O?$)h6`<;&}wPth!Zv-md@9fHr-i|ODzW{9 zeSp2hiV#h#^(a_1%eDBw7y-2rXZjmvS?M4|iV!ew0Wr%&$Jic3gO`<>^7yw1p$q}4 z#1RDKuP9|CV#83NpO*Wfq`F}?-?_K61&Y}QwZ=fWK7 zD=%e)l|YYR74WbwWz%OXZtH^zN}7e{TKL(9o&ETtpo!rD6Dnq!@jD11tUt-MMcgIX zEW|@(Q)6$DM|Sh$r3u?}OWDk!CVj4<-_*JB-k1d&+(mxLMc-tO;IDRpc)a@M%!u zH4_~}95m5lZh%F`?nON7@W6qtT|Js$bzMz$qwFd%8Rg7UzqT@CVSK{a`0r9`jVU!Q zQEJ?GDaAbr2P(n7#1sGoyAY{Fg^8MZ5BxQoa6GeZP@ZQRoGpgfGY%&Upf1l_OgHO_ ze~S@TAYl6t>|Y#Cn@bt-x97^GrHt@$69*2#mOyD~{FsBV#eCS$--S#MZ8u$9Oz^~G zjKZc_>Q%~BG5Lw}))=0*c;d#fK7d~PZ2R#{CQfQ&s-dzI0jom1jDQbPmR2$1pRVJ- z;XKO@Lx3v5vn)Dg0?AE=#@ugyv|fS$9YT$~zmyRUjzG&w*fPeyLcq>W@brxGOH1vR zF~(rnEQuW={?nUC8vk{zabHiGV3QI*jH7H4AD(dEPIBfseL7b$N-gX?R-+XnNWl^| z|M`!dV;3HiixA2XmLk|Cn6@mCUXJ)01n!v|0_nlDO@Z{zsEf_YMPSo{ORyc^M_$P6 zf#1=samr~E=FXdQ>AXpo$EMGmHEn*Z%fi0BPo8k;>?>mn=FFKjKZXZAv1yl2o;G#r zw5bz%=Jt&h}jV?n>2amgqgFa%(`;wv}k%w)-1oz z=Kr1R*W;Lv7*3x#?~*I}j~?Q4g$rX{I(hSB?YtH-ZyEqUMmRCzBZim9 zyet!+cEoG5;5>Y2uyJnN_MK6nUE6luJ9`VJd(r;h?A)I4glyXupCZK93cagy@!7); z_mB3&p0Vx)-Me~2 zbG?2gUTS}@@fK8iN`CjY@B?JoG?ZG9iw`umgwteyxJJhEy5*gk*WLVQ6}OZQg(GFm z@J=_98A09jNbEqjLpW>_fiE6<-;d#ghxw;?mk#y1O>fz$Wv9ptui=y9hIp^yYlnZi zzT_m--`3ma4n4*bQ6D<&3x_cIizOWROw725SqC%U`_FeiLmErTnQV5@W$}OV2}HSt z8Rx?P)qZ~8_|3x;IM4A2xuQ?dyAM4dKY$Vrf_>h*$)Auv3di*)iyPB+DP~PkZ7yH}V z4vEymb0M?T*JB=+lMwLq=Y)FQpi{rz{kAgX*~^N7(gVzrjRtVcpLDb>6`HvaVV)HJ6Y~##YiHCdb0~OdjUTg)Domnw|EC%ak zeYW1&h}$xVI*(;IPK*&PHt#aXL3_ha@!wU`UMhmMcLUu#8=XK(DVAK(>#|a|prp$i{kP zAdTyRrpDI;-4NfG5p~L7?^Q;$*t*ET>N(lCLe4`X)W6l2un_xcTWbuo_5w*J8chFJ z_!4qkB^KK&e#*bYmyrF+{`MF4cw+f3-$2ZUI{Sp@^<#Yr`SV`Sm9US0ehXno==Z9V6=ZO7}b49V9_9WVKlH?vF^38YJkZ;ECBj0?V4YKijME(TnU#jwE z{66xpmWiMPQ=fvNNzZYK<-w^*Kn&SuM&G7>sQ99pba{W@oMq;LD zp7J7}&$6gzp7erUCG*uM)9pBsLdiqKVsVT(L7XVg6&HxtiKXJL;vM4M;(GBu@d5D> z(HxIx*VB@##S?wU(R^wG<^Cl755+^`XX2M)nEN&KBVuE*iCBM}&Phr?MdZUAmgoB^ z@+^_B)G3?e94wZ6k@!7vx@eAf=$Ydjyk6-`MRU9(eYIqByhGk3*&O$f>-+PV;~nWQ zNN<!7ta!n zUo_H(Nw$7I=6r$li{_#Z1xq1+|gfUgW3&>h}`Q5C@9qisy?Lh!=?*XTb88 zi&u)*h}KW&Cds#pE5&um~V>qqpc*vkEAFTg%vA#djhe|&rek#_9)=w!J_l>mEP;4ybh{pdL z`5h(O??iT&+(YE(6WTdP93hSt$BD)-9D36v+wVnkxC+Z(FWw|B7wz{Ujh{I5)+@bA z#j`c57zV$1=P4X&nt;j(>?5~H!ZQ{?w zUy9F(FNwbs-w@vt|12I5kBFa$#_t^Uxwv;>y%8}g*7r{`{^!u^ru-gaAMq@4usBRC z7B3XXi&MoJ;sSA@SSsEqt`N&bj&@?Ze<*Tf6XhpFLx3juDW4HXxV@nX)DJ^vQ|aP zTdyv~w;RW7YPv3Sb-49~ZBh?MQX~1z)@0wktG45&)RmE{29;^+`CY^_XSBe#NIP!2 zxh~|6s|`!at^hR-Xji=2I9o%7IvW=Z(U zWz7}gyWEv!b;)O!)kWPA2mgF+^2(jf@O98l$@rpX#-@}t?pet-L&Nww=+@9((VFw3 zk(#q3Ud_PdSNBXV8eEjRp+QyVy6}Oh6X_G_>Go@Icj}tVm3QrFUD;$q)2dgTR)uW~ zo2+SiH@+^p311;fKXrE#*o{@ERqm;E$|lr?*Jsa&tY2OizH}+tm9^nHq)uuRsX51K zP;<7Iy*sUHNzqe9ZTT(IId9hDs;oAA9a_8G?RRrs>ZMN2IVq_%=cfL3PjOMxs=gE3 zX!Pu0jHP~*V`6!&Xtq(<dRNeleLmmQy{t{a(-RD8~nSIb@{cdgFnnv|5= z0q=Ci`|uGaKj%oDE!63Ixk*Xky_sij_|G@DXOSe1>h!aa8uqMte*@&Yk^1S4WyaJ7~!`xA9@e35WIo#0{`H(#NHrnHh zyu53OCXS)qG6?AU8&S3qyZsx+geHc8dconL-#8{T9m7UB7BeL{I5dKfUFkzqbg^s@ z|DIJ^z3*A2>U&l&!D}*H*V+-O6tOLWqWx-?lpB4Aah}{MFuslh5)w-$SKcWmm>+hI zy2VwAZ2u8B1|T&;+Gz+FwDEK)BZUYUYqg>@xo4{?3fu{iyTS~L>Ea7dmol;x0jf`9 zoL0DM1q8n(P(`u$l7Se;V-U2DVJ8FlNTLjZagv72xEI)omqUb)xG{!{Fi#UO0EJ{# z7~WH2tAv>nTdV~ltOn~&P#uk5R%*+kqn4H0f+ok7%toZ6DLIl*$u+@}Yl0=$#Mg2R z)Tf$~7ZNKFjO7i8Y&Pi^5r<6rHH)ek`NU7}iT3qHz*riB&st1TMlSQy2@XcVVAw@f zjIg($4+Cal?W{=yu*9{}R2v&?OMUskh*eveLIjeaM7LsiAF6tM62<~VlXcdClJgTKG#Rk4c~Az-lJ{qbr?+b+a#yXkSO z#mF~H8UBBWfHLeAfBnZMR(dqswh+N}E+p7645D0=XyAp34j2myW?@VGZoh!=D=0~H zdkMS5AE7wfj!;BjCoIJelx0x#yRw8<{I2}&#aa6n1Z;nTCPL0Ni%488FgZ~t8*P>x z{Pz#eQGtVVd+-q39z4VnUn^@7FFBeeqv$LgCtJ-qNoS9e)ht|vSqRvhHv!L^Xz^(%QD_W|A%-G^Fc6JL z&;pYj-)^l?06$7t!sb8!*&lP85R{ujIpmx~gKk};hK`E`dNg|6F(d!tVO#(H(O|PC zEm$yf%Ct)`rs$s<7WNW`g`L@{qjz)6>#Kf*y*kT9ElG`9nVj9hPSF8+7$ z8V%)Gv7DGUBgWa<7v^@saIlj(iVUN|x`OT6c@1;DtA;`oBf-*;p4-b07;Kh`oLv1+ z%WakKVRrncF<9x|zI$(Pdal>GzxU(PTyHN1b8W_;u6LXrm|Q-V&o*$#7>1cGj1{l~ zv=`OSg%HghpPyfVIr+WDF^nR^r2K7A;|--l+hU}p>tYy>nLYcsyFqvB+<9zw28VZ< zL0y;5p0;p7zGG0}O!p;!Y}Y?KsLPDznm*;qdGqoeg97J&_1Lb&Ec}7#)4x79{xQR{ zzG1YM|0RI=3npDUZ7{}pVN08h6(6cqf8!pv3ldUF7>xZeFNCmjz8x< z%fx5)H~T|@^N)NnzFGyvwddpU;^4uj#kz2p8DmDV zPM&zv(mR*>H#zh|HCIRpFRygG?PVR33jG->dh zc?+g3JoWsZPIAMP^BaUxlQYBFZWFhem*X~fTevN~R&JY6dp8Q@ZyLkJQ~7bna8)4V zA0ERMIH>>A2XmqCS|ac_4fjB1=_y+HKbMZv4hhsV_vK)HJ?3#a2_b@TBE4?VsbB9J zYXo`r2YRUV0JH3X&T`u*q}U=wh~tr7eEFcM;|zcvz*|*gkL}{MfGvZlnJ;$-BU)_U z49GUltmZIMO+#92-c-oJdb?m?$bNJt>t%gh5AtdRTLw|*b=<7R7|~+$aO@ppFA__P zGeVKLy;~8tWe{~fLuLjeT5R6Ukb~{Zi6!ju*s<;7?TRgfsM7#r16mxXpDUP01ub1- z{`zr!c^7N#ZAP5-@({RmXy`Z`+h7;wF+3((y%1L73ag|%>OGBseQK`Fnh(8xRsgBP zWjBJ2Q{DnSo?Gm~_Ho&X5L}PESfXF>j3K@rjS;u|GNR7Au(yv9Ew(N)uzJo?3>3;k zVl$-k_Mi2lsHrn(Z#z0JAL(|n_N;6fO#fGm=VH4Oi|rLZ<=-)$i?de=){BANG^)LSXpj4^?{N%DirH)Bjt{^yd-m=frjxnRLJr2nq+4@fq1 zz#_j^GOol;eP#|=*fV2CkZ*3=Ajg#7iG@N-%M~N4S-xH^cmx))4eC|#=OT}g4 zO7Sl7KJfwZaq%hfS@8w&cjC(;Z`)bVTjCM%6Y)!tH_6m%Aeu3Skef(uF7l~2^-dLg zihad_BIlW)-f(f0$j9VNzf?5)C**mOuM_Q9sAZDPehNK4SZDcr#m(Xt@u#BMPoY;W z`FU}dXvQWYf3M^>MLP!SeaVN!k43&;VEum=?HH&i_b;ULQ9s#M>?WGmAV}{g`3$j0 z94d|!FAy&lCyQo(h8;7;5j6WXxJdbYx4`=E5;usO#2<+diQB}ViO-0?5_gC@#aF~X zif@VUhzG>Kh-NG#+EXj}e>(Q53x0UHKHWq!MiO!#$!Cg##B;^-#W7-uSby$gzHOoX ztHkDe(-f0JzIOy>I_))y7C z#Aagsu~8>0{Zz51$nQ7N&RHVf$Qqe1n3z6R{GK>ToFUE<=Zja1i^V0P9V2y@H%`Jiv;^P7$|sQIv8=x93L45mBDN7IudN7EzTYIjZA(e$(iN7GZClbu7! zOE8C5d1mFV+U!lqD?_VZDhh3Q65|;jtaT=KTozsvUiV~eXuy-T$<@0swxHp*q&iGn zT=Px=?1mn!4aGv0Pu7MfVm-=J)+W`Ze1W!onp77#;?#WDKU5JtnjTH5iylr>iBQek z`B)S8!P;=f&C8N1QtCoSqBZaIhn|Zu5!DS=7NCZ-x=2k;-%y=f*Q(At?4V3b)_cgS z+213)+FQ>N6P!7W>yuRH9dg#wW=dV8E?Tock8A7H)SS+>Osn}5ZATwO`&l9dR+8$X ze`8(Ya*yrvn%9Ltb87zFtK+s%MbgpqB)8^3zmz)na0u-PqwbVC@8hi~@2*Lyz~~Ls zoUs+X*8p?BeG=Y=mgd27ncsq>Pm^js=oPAKP|Mb{CA8?(yx*q*whOmjs4nRp_&g)k5qDNrGLKSXsfzVE!HE78n*62o0Dp4dhNs7 zhp|FAK`IK987faWLzChj3iX8PY(_0K}%H9f#r@I@`j);pjNnVF`mL=7^*DG9e zpeNQZExeKaf;Oc!*uZsk`#Cl5_D$vy^B+^y6I*XRY5?TZ|TG zZ%SI7vBBx)9Qs9>cTZ@|$f7AlkKu^uP#gMw(nhzkcWr2W(pv0QABXEgpWw*&EL`V) zj=uRKT$hA>=iq5v!*E>$a@uF6Rdp$!gzKD-!)x3PTyy2^xL={QDdD19i$bd&-!rJ_*@NLhsT%=m#k7aGksB;fB z*v7rz#a@Iy^tgZI6g_>|Nzd8sR(`K&Qc=dT_UN%*wV@H6w3{1l2LO)^M%8Ci+(J->$J@t)1=)d%_B%`DyfTt*Kwb>MhLUuWu| z%V{8-@)^?6I&(u72^-&oaF}Ws-%|s{qze$ojCSjRB)WuPtk0uBe0SReqH7bGQqs#tF&OAEBBNos2sWUxmlx9>pw3PNUb*}B zR#NZsxSkQ64C?Gg;8#n0z2(%qEv{!oC*xHl^5A?uu6G^vILW!c4n}k`sPiU55;wP5 z*E!UC5qeS6Cr11;L?Lk_Ds~t;C?*_fnEx}&Ql2;6Lm89-kf*X zSHyLmP3V}YlfgUhu?W24_U*iv&@oYe>cO8Q-*5NZ%umIB=C{X)PR0h<;8UTu<9d%% zuWekusmrl6dQlc$aBCpIPyFJHHp_ujwDC`>VK3BRUyfpu^_?EqQF4*8P=wug3L^=wxuX z;s69QTcy$4N4@vsdPa0Is8fhACvNX`>U|D9zlV+35KqUPjA78@$k4mvx*t-v7c%|z zHlmYp6?Cpepih9`#yaW^iR&5BX*3aue}+z`X(dRsBZSA}ni)p(#ki&~JB|1ox-YKP-e|oM*YahjQ8~0coM-)Y?q{?P?LJ0(EOPzc@nt82K4SC_yCJUG z%V^GwYx=U2L9f!G2oJ?IyBf_!aZO*w*#%m|5nhjL<{HgAq3O5Pm+yn@WKeSyLJEE> z{I>Qm+P{r!`?C33bH*>A`7A=Oxb{$^osw>C`*I7&PR2{n{2c}2rEp7cU{B(6EkXs(EB`m&R85LzE0ydKvaWi+een!b!P z2eghLc=!?YYaeSgx5YJm*~$1ATD1tL#x+M6&0ohgec8#N))xpD#x+Zf=H9rbFFP5@ zJS!tCho*l9oNYAy-ckH#=p5INI~f_!&OvxFZu@dmq6W78t?SEQQ8p!gxiK%1GFGAF zS_FQJ#INs8Q`#@-$2%KMYE>e%#4n%UFKdkE0_6Iw^JSb1ptTd>?6~G5M)Q`qrZ3~S z8(O;&=EpT3GMbgp^jqM|KVb{9UW4Wv2!8EP8O>MYn!fx#HF0fvKP+bd?-&66O_Sm_ zb~9ZUZ|?#Vy`)0<)iy+d}lrlrD--8AkGKOSL7-~Jn*2r{Qj4x6LnPSBR)iEY> zOQ|h~&fHRJ3z{5TG8>UXQ*tDsl3Rl%w+2flhH~1jH0F+=Y^^afj^G84hoAo{MtHRV zAza1CL0?F&VuZgO$ca=jG8w^j#!UqlnCJvzk%^8bu*so4e{mHf$p{#a&dtInz8F}$ z8F<)4M-eY0VA%EIDn?%Q)7b+bndk(VGYi*ZD}w8cC%8M9(X3n{e=Sy)mD;tyMlLhE zkzErdgw5LUcV7v~RTMrk>w4YdDn`sNnJHh;s)_Y=j(Yq_G7SDs@K zpb|#K=HAU2PpGLYOjG@hGmdxw0V8%3+hZg*3mXXAws|QShC86+fX-EHB)=eygP7Q1 zqN5X=XEe7GPpeQM_WKH49UfsYiAI}+E3*Y53q!$a`bzV^%~_qVaoU?BTC10Vy^kl6 z9J(E>2~l;vRb`L1ui|~h=LlE}UabDitp39x)sMmShpo`s~s77ewTq&D= zaaf*@hMur*c`(%L+idjfC!3qu2_gVw(dyUvJ20HY5`@L3OD)K=L4@VePMW(8pJzkNLP~ z6$0j`+f&Km<63v4u=K|i?u+^NI8lB>wSTFbnyH}wc+RyF4+b0am z=XS_8#Yb{G{LVzjCoGLm9KU>)XBKYhYmKE6-ga&_mWqd>D6fujE>9FMVS7>$@HS5$z<#y^RQPllW(qZ;3SNi1IIsIjJ2)G zL8Ltb`igiDEx?6I3CVS!Zn7NP;I6OynN3hxuj4 zByx{)&ibZJ@0T5$C>!5~iM}dH&P9``v!1ZKoV_yx7FRA#9TZ zztuMB#6R#>llB(lu)&W=FiGb?oAj;cOPb(GQcK`+$tDGUo@`R!{1!~oFNRH`t>gZ( zuy~-(z`z6&mVZ2rvIWC9l#X}tX!GqM zh=T+_*IMfRIMO8Ym&P5(X!KitTdf&u8^2LsPl_K(JSqE)j_>6>Bl=14^QF}~_9PiN zb$`8v_#tJ@9a}bVg0*G&$jU!u$4?TsBIyo-pp7>FDrJEcTp}}8oM%UV$ACVFU!kvy_{U{!d&mvJo+#3cw0o0?WDHA7ExR3dVBTC?s6UmGpiCdyk`J`xv^_yTG)y zlivfeu3j_rCEDMgUm@@=hLFjx6tJ&4qig1v{#ww#z+2eAH?59~A>G5b0PukV_>^9q zTfhPxa=l5pUfY;=p3zSo+Qs;tVtp=;ol@X69qNsTWi-8EtQ&gAYdw@(CIg>GxU4_7 z1{#nJ$Jmb+=X!U$F>e;!Q|UwtU)UI9XbhZL|AO3G+*m;mbQ}Kt72;aAzc)4JwHgY) z*QNRS?c0p&#^%i6CeFj>7x+Det8-83SuntZe{OniH#pJedM&wM6kyL{BeG+?;G|nn z0AJeY=xQvb#k%(B>Rs92yEx{Z5%UHQMO$OuPZkgLe!sXs>J52tx1|d!Tp5ik z>+A(RzwJv2$2!#-sfX`k+cWNBOHbP#PVid_313k9VE(h-xB8@lL4jj@apV4^|I6KQ zHX#>hX2^ zCtPz)QS88j=S-VEeZDdI4|(YNM}+U(J$pgHe~`y6-Yw!<;G2AQd1-K5pIttC{O5gk zu@!USo}4>%+T<%Qy=3O>>2n;#CrzFVujF9vtT|JH;v~2((>FR${_82T`0*ZDoWEe6 zlRIV3<(E&xDJ2)K(7BjhVcyKiS1vf#%5;1@Xj<^{=tS|BP~epuhEABJr)XiX=Gq~F zdiLt8z8>?qoP>ba@+Z{m2A%r#1~298)$35{0cPQN_XqJV)GoH(A|&8dczlUrH_m}x zQ>37XxiDtCc*SnZAnLr9flJXqf{o6or}u7S*g>$1)tichV7-0Mz;q%%YyqggZ+UpB@ zdB~(a9y_*u8vQ`C%X{>c@>BU?adhBuOIDUKt#DnWG7wcjBIZJxnZrtR7 zW;?C06M^;8KI;tH`!N6i`t0%zTyXiH`0VnWaeSX$ z^YeY|#~9*1yEt`Y;W_W0@!92mMPJafMV_lD^N9sHL7XYh7OxYRh|9&hMIMVR|08jm z$PvO!e@WaU?iK&9&o2502Ut@ai0r2r3He{`vpZMz`OK8|OC@tI3Cer~!ul&D-y_-h zI3j?O#Jek8gM=^NAzv@u?$ux60A-$s7$wI~);5zOVGdBzThK`&mr2?hBDYy>A7Mb zr4JH^D}9tWUg^`tc}nNYY1%JU`mN$x68&8z+03hsc0DZlNfPDw+J}5m>Bd(OdVC$l zc3L07_oQch1d;w3W$1k+y$EbjZbTwviY-a#cNPnj-dj9N=|jb_N*^aqQM#Eg9d;H` z#(LePbmIevde=zaL?YZT8s9&Zdz>=#o+cr`AbF?sc8g{{bmad@`5%ywKURLN=;DOU z^fVH7GbG#j&SR9Jd$Q8aJm=8sE4fhlL&T9vA5TJWqU6gY&n01RfoSGANBy@be+3D- zLiroSA1d9L>&qaamo2tddKVIU zr%FCe`DcpfD18(OJu_c9>`hhv4Dkx-Et1|1lJ8LdDsjEiA0T1R%u5b?Pf*5s{z~~f zmA^-_nSUJl?@KoGj-&jilEb+0V)=$7?B$TiZ!Ou(GY&bIGWwxFJYD%kB=XObT%!C5 z;xwhtC82kvlGE7km!dPiO@-Mp5)#n^iLB9D}T81M@ybaqF-l9UZDJIB;QQJ&aL8VrEeq=ejs@( z3BB#&GfLk>N@4C*t3g zpNeh4{B)A*OTu1EJXz^IN$B;HT%`P=;%KE`OhRvpsJF$~!=OoFO z+)q41q(>j^jTB2nGgl7Mr%9eE&J#I`isk46NZux{64#1V;txbSC&^aHbQ)xNI$M&z z6JHiz7x#(pi5&e!eKVI1_^D*x2s1q_HWV9+IbtiZgLsmdD;9{Si)V=^nww;T^d^e* z&18En7Z->N#aqPNM2@PU{#vn0{DEk$-;uvna{akUey8-8#s3!nBz`C!62BB(UFVwX zci87EQnsU+*iz&xQl@tidx`W^WcnbnNVIc~nCp7vk5l@^qPd<&y8ZsrwMsYF^+>-- zvYm5emE^VJJ)*hJhyG^CTg0D=KNqXT=f&TOzZYKibf%%j;su z5s`i;l+Aqr_+957>92AF#EV2b$H-L4GsK%kb02_uPBfRuQ_}yX_?Bp|`wvL|i&+2q zzB}sRdi4-b6VDXS7S9#!93L|zo9lYSzv(+j<~kqw%cW1xVAi)mwAcBYCD;G%k-5%C z-b>2=qxfHq|p5zf?i8w*5|6QZ{ z*ZtQ?uT)$nn(KeGlfKbxul=sk1Ck#U?e~oym%KyVDZV29QLO*nqA!*1^7D2gOIl zpNdb5)gnFYY4;WJxc4K-uTg&e`w#nlqh`3aq@6Zmdyy{tOsCHz*oxZnb^YT3@RcGylOm@S?oo+q{x+luymrKjYJ#s1hVx_PuAdWGt{ zCOYMxiJXZ}`Av~?&nah$oO@2Wg?N#8vB=ry3@;Hm&z$mgB4?9Rt`IqAobufwXNFV$ zw#fP4lz%94mN(^BMb6Bo{5z2|vng}^Ws))9sh{RzqObzQb&U2 z)*TNSBLCsyXmPwaO`Ii`i1Wpj;%c#6TrXCLTgAHLCHKq!L2w{Yl=!UpocN0P zs(6~U`?}|wwfOvhcJ02N7e%AKzyH4=Kfh;B>=;;Nm+p&x`r3U(cqYRn*X}zH8V$X^ z6^^Z)=9V{)-Rv}uIT!r(k01Ya_OxD)neh)3J?!F=a@-pHBC83$-V2o%c$WrvjA-bM;lTktq(kFSFt(_PmiM++NEw1o&C*W z52ww6kP^mo6Vx)7uSL{M}BRsK6 zRr(T&t8&eeY86hujpB6@BTni{%BypqN9+uDECiQhQ2vM>>6Ssv#4dD~&=G}C77K7M zW&Ye?FN-<4{h0sfDY87bKgB(;*$wgUMtJ48W8C~4cXWtrgr$X9(_Ab`g}8UY!*%nB zylePxC;q{!p4%p;L8h0}G-pC;Jygwn+c|?>-MEn(dgxro?%am*?B;Hf;O1`WCvNVR zamvlzu=1uC>7Cg}`?Y1AxVc;QrnN3ATL6uPoSWCWPAH>t0Dk7=`q{P18rq;Jt8W(C zmEv%JIb+an42fOOVKIN~)VV&-5Apw-bJ7`2G=>dKA!RtDV#))-3`0(-A!Bm!f-!M8 zk_IIs@>qh|g`C9^QVAoZO*r<1gbcx?CL19zg`=6t2mkn)Rfc&4O;8?!gB@}@^Z$R= zMn`iO&Mp1BcRPCAaieXTw`hN5h+6}ls7m~At?qlmb~Rr+Ks=v*(HX*RP;>e~i(2TB$(vt;^G$NV$pQvv*M*>pz=&$XNA_o>Ywf*V(G)6MDbFI}qLd zbMn@O*LydHZpDr0v*`L#qZhjcm3IB)IiNEoptSq1sr385rSqGQ1V`1?Qa7|U^X;}I4C8^JOTE#+~r%+H$PaPS+KHP$%_9>M(XM}DIb$oyCro8MHp zZ5lY8-$D2V9Wpj-31sVL(6e~3KcP5;4O;+ru-qEF7af2f%cZ|9w;XPp22P_#6{SPQ zhVl1)Fu!N+%wCG*b?i*kY!)PBBZM@|e*Ja;ZW8?h* z9;nh{>;E?5olG~F$C7ERiK22m*R0|3pm_;4*beG*5_d{_Uhx zTNcX<&g}+|8k{`L)fyw-S5U70;tYp6Ti5+eJ=@87V~r#9Hn z_f)s`Q*QEOe`z>+lKS<_z^`R9c7QJ6FK+5^@SGse5ziyh1#L(~;`zq#?qYB8QgOIA zMzs6>%$7V~TqfQiZV)TQUE+P>*Tip$ytY`6$HiC0!{VRC40I&pH4AXwDDZk8J(nZR%y)XLUh% zR@d40phvI&m9djyryn~RiUamD*t!N|Cq{q6jd00r&zwhX%uxuXj0(ZW45`?4!5hK{ zi-A9ls2Dqm63MZXLP)h^Cs#1-A5fZB0Pjw@r#Y;Fu@j@h5(#@I+b|ae!bnPANU488 zQmpoUBaj?BneUICWFQf)EN(%e3ro&a|BNqO0lz(KUo*PPNN?GhlWwkZ1AMc zD9ozarPnT={jW4>n!l-nbEbpu;B^19#!mhnCQP3lJ2^Xcf=k5t5-eU{lIHB#iQg43 z0l|JbJ9d&hMKBh^x4~NDnbEPJ9PBx~=KSl7ot$Q}wf$-Lj~_efg|6e+!XR;&c)56X z>;(OTF$+8P5M{qW{tp;C=>>I?r1^BclYCzh?J&|i*$I!U zVe1-BHuv{%q`!b@;q|#@G8RTj3Mk%~ z`)ve;pkcyszwic$7$xCKsNtJ(IlP$Ra>7sDQIfexU^GnVh$31R3ve%G{$`YfIlBFr zKgZ^>Sf1OTB8S?HhRGs$)zL6vO>^BbEbkULF-k(@&F8-x@ef{SHB8QGm@J6SnLB^> zvS|C2y?S<-a`nRH(b7eW<}Zul?p|z@9k!cqIR{k6T(iRI&#usjep|k#b+3I@z06Rsx@-b z;f_j-nIR558O5l^Voy@&P1o=o5;@|H#9w& z-$TkTpP9iNMM2Ziht{wxTK+I4ZM-q~Hp{-Z#>V>rJW!>@*8d5_yT}S4}N_ycu9dMHT0$#>x%b{>q zr{r(dDe<4nCtrll{+P2*O#giNXX=#j-p28g$>MaeL^Qe&2)|D9M$zh&R7sAD_lggQ zPm4U)S z>3#bVXWmOkLaSar;!J+pmshn-w3*y4(R$d`iJRulOr&;fmAGkD>%@k6%M$nYE=sf; zwj!}--i3*Ft9m57$x9RWOfF5_HLPdCo9DE5j<&pETx?xzK4)w;XYs zY&jC@xCQ0TL|$_eH#NB?aqqk(iMxA0dBmOf{1JE6tVCLqR*Cy=UXs|*q-`Q?UhBk7 z8M9%pPPClYD{;ZiZ4zm#dM3idrYG)evhGOe=EbPv;>4a|*CbkY?3uW6@@BLF`8Ao9 zXxF<<;=Xz95;xr3GI1aBXg6QUiv0mCBU`{9|=4gWCyw-;Wi;qT#p8pr?AkY|LeQeyn? zM#gSsetU8J??*-qM{Z^428j_T>1TL%Shf7K?XprpQHJVpa4wMMM0am;rM+x9%gR&e+tm&wWEls;eNsy12p6(=zVPm!$2OuLn7*HYx> z<-W*$U$XF%O5(YEs!eC)+ZcH%#f}U$;yFJOX4V%^OhqKmD z#S;7K5e)z2&cDMs5^_($7kN5yFu+LpF$(ZPZVw)@dZ8AQi z83)_%*Y#s*ux2bVNdz@$3RyQ1{ zW0o&O;&j~a3t4eG4){V|oQ@2?NP=6EA^B>vyDt~kMOD~=j~M5~Cx9RMzQh}_CN>>! z`u?bcG1Kthuj1vbBCCTLk+rp28V=NIX~fj(MN_M#S#df(@P*ZJIzEO)aw5l+b0xtW z05-{89jAlG3mb*i)^-YO`%~jPo_H13b4pjo>F{gILv747{AX=LPDPAlJ>ee4wcqy0 z{R+r}=+Ay)fppsv;U39;V)k&4dILNpw>^f8kL-=vjsNT#`msE-&K%q4L47iK$M>sne?pSJVxv_iU z{Z@?ERA6q&HQwiG4Juddl2)k_T3|x_glVuIFG0L?lQKC#|HV0Am1?V zWvfZGbwr@=E>n@_Zg4*Yq#MfP74`ET$}+3ueghoh=RGuVyoLty8*1}oUOE;-1N}2} z5At9>EGKX*PMQbnQ3H#(!vlF-#yYY6@E=6J=etL+ABz3@4YwyS(+27{+}4kIoA)!P zVhHow?dLJ%U9g{@$B;l9hXnE%63jzw9K!ldQXXt0^Fi4|0&P5H9og+JuHbPT5vihK=NirY!uMV_pWS~yTYl7EeM_AlG2|X!> z2c8sx!(5p>%uLo87Mr9Nrxvz})7=Xe&r4z=O2^iv#0*%^S?$JoC9Q`wNwBXf-TuvO z0`V3s9-C!xI{b&w1Y2Qbg-ng%`Sma?3L>6EvvDsa*aNu7x^Z)BKqh#khJbwI982&3 zVRLpj&a3$e<9|8vigAu6-hlP6iJjRz{UhJs6pVk(VBrH3HvjpLQGzBYe+yy%k=x7p z!&o>TQ)kVdGky8|(y3H=UDmaP-M6fC7N!%!jo;1uGPGcNX$d6LrPM7z|KH@glUraP zxn^EQ)LRkd|MMd+V^^>)+$$`ztG9$Zs}*oZvIf|}4V!#ndot{Tme;jow?b?zmS5P7 z`>QR%CUM*w4x5c(pEdjq?%J`iBeLku&C0MH9kw95wrfvp1=h)HZFXV9erZk3eq`9I zZG|Zb5wYFe0wlS%YsY+)-GvFSMyV^Yy%;uv!|r4)%|2}z{NI5UytZrip50Na9t@N> z_J701Y*y~kfm@g%D2^@Pe(uasMka2L4u!`1E$j$~mNkjy7ZenAD(p~%e7kV-Gc+^@ z8@8R`@yj()?+0$zZr!?h53iZy9dy_J!fe2o-nCQb{LZXYDRxfFiWU?O=MH)q(R^Y? z)azlkgIn)Ly_c__gH6?N#kj6!wV(NRX8xznXSCkGJ8@3E`Fu!K){qI?92eM7(cQf2J z4V+FGA93^Okg;JKAP4j79LO&VVYYtNaN9J@q9OA8&Pn>Y3Sq(g`XWEJkM-mDoz3rl zxS3x*EX_~qVPBFu`7!((u)%nH8=m|-@}r1{L%$d><^qiWo$NdE0fYwIF$MAZDhxk*!n{LWcI8Ql%Y)!E4 z){hMO|0BL5vtG5v_KNT0nJcC?)N?ovT5CS3Z_hKc)_DH#a?-;yXGT&)`|})hPvCrI zkJp;dvTqsh87JMh%zs{={FAYH(E0bCzh~dF-l#Ia!`5AMV4VCXiL=G|;xh3Dk=H2m zsT6mK_lOUQ-w+=Wzc2n${H<6cMsU(F-*ZGW#)JD^lrq?w#0hD>3xno+3F4dY!jOk4 z-FU?_YR?FtDY-=9OC?_;*?en3`Y*}fEc^%gE`>iR|A!=hSMq+zKa%`2$<*~>Jztmn zuH++<|0ww*$sGG)eDi&W?U&qygxp$k2g#fY&-iA%0^tKB4^}wUp&8ECcBY>udA8(5 zl1n9gGMOQh#l80PZ>@rR;0PvQT%M|5E&K@f|TCzAyes z{EHaod5827k<$n$o9h8I*8$jG{``2!aC1F?y(M2Fn(G1nmq{KkP7;j}<41b{`SDPvAWHFBDgZc3+XTk~fI_;>!B( z5bqVaZWaCaiQg8#Cq5zmNHqHfBL2&ge<{8xzAYxi_r*VpAB+6t%W~_BO~e*rThZ<( zSSY!tc!_BC6+}M6B-{N3CrX|y&JfK$gNVOSvfXcx-<(+=yU)n2k~fPxM1Fl?ynDs3 zi2KBEi{BHU5T6&#{)0&Wy5u*-Lt;YwQ2evVGHJPv7s;>SWD~Ka*jDT++IUE;msx5Y=qC&Z^kzI(B}=fz)& zuZwSshr~aNAB(AYCu8~yvF?5+E#%))th?VyPx<#2sX4&>Mv4=~$>I!gj<`@+Ue;+x_jF(G~^{#gv+XFThZD%yQd>Px0F z1jA3Y-^oP^zgQe34i%|A!StUK?LH?9B$tXS#WHc7c#BveR*SpE`$V%pBFg!uWV25q z+`bsn)qw+UGY8f58|IhzSuIo*+&ty`<~>=-|VLd|7Ma~iS5Lb?yHFS zmns~G<+SUio9|$Vk5}S4Yg+Z_eqprMe5yWTLHAxzRfPF;eZ+V9BlINth}C<&qi$+u zMWf2h?fo`xDrsDqS>5=KStaLHILFHSyBDP#zQMgRlC!n`=5s5XY-_s3Ir^jWn08d(`pa0uI~weoP!s7J zgPl+l?wc8p;s2#8>)q~jbB?aQ!EL#+S^e$V72knwV`TG-u?Df6>hxW?@h1Uc`4R}W_0kymwf zEOOkLkg@&RhejRRlha9a(w zt=U=m4qI_yjO}>lo%+@Fc7_kH3wK&sf9spEwy_5BhE?g?&)JcBcwK7b!bpCk!0las zTZ7vhR%9HDWTaP~v$^bpNndYTeeNBNb~Ud0Z>M>2i{i$`=ib(6TjPo*+no;1(RlfJ zI~rFvsN5VGhvSpJxrys`&)ag|&aAC@h2BxmYq&XMOQSo^#qkLD!BOaw8EJL*?Qwz_RrHmg^hU6EV)-B`+PU1K@%^s1*1XNJ=buMbl%bXWPPqhYt{ zare(DI2yyUvZ|b|S%)*yM;*F3azTtO%*Bx@E_nvWWlT+{X*ZSN=)jfLZ%j@4G#(T8 z;%7>}y03pRk49d;)8*}h$kE9=p7|A8r#f#tnOo%^&nV8gV>XV;7cx7<+TdvW$7D(| zkGa#~4+me)jU5`8_DZ9a?U9|?)dOq7*SQ6E4oJN{tpaD$mhgehJ5qL`@Ap=}Q$JpB zSK8qXY4vZi+gJmmIi zT(xVTb2znOUXd5eh&3+Bn>MLr^t7syifONu9GI5Z{q6zO0e$~qVnBTPK(hR#BLHBGw6zmmRu2k-_g zpc8jC#~V?G|4_;NDWagF_{>IK$`zEt;a&`jguejKluO{o+Wn6LDI6#WZ*rf9J2mV; zfR<(VoEdOLhCAUNIrlOh=2-un@p|T%_tRFP^d-nAd|^&w_;SkiafbGi2$f5I<_=$! z(*oWZZW;ua10eV~kDs$N?swtGDc6_L(FHzPcQe*-X1J8%I>s77F&#GR82-5;SfEJ;9MS_f3^Z8RUK1? zHt2=%$bZy61t;oL=A5WcnR^O-N^~wh>0ciudHO(yl7j@bhF2$4H3&Z4p^`yxa+&8; zR+rJiw>_k*E~CTG1R;o(G#pRXjs|n!gvR1q;FQcOr79Bv8TYoy(P4K@Lc+@y25*(p0`Ov}FcL)__bkx8?N5@v#M6z{8?>%gK zj}iDcR4HjX!X;H7wum~d77qa4X4Df}#I2|KlQMHM{Rj|y8oMpVn5*#Oh`p)V& z9ULq`@7rUAmhMiTG@ViNzNYr$2{r`Byt*v4RhVw}8{*#|JpJwuo__ZybK)I-JS zf~irlA?%Y391*%n|G2GK9jAl+g5rkQQ;eO%h_;iE7aLgu3n$?>3|hZ*uto5<4YN6+ zWMl5d|NXGgs3i`-LSZ-@r{is3h{Wl5&lj@dbkz95>UbV%-Vzo{yhJ{%=UlToPDd}_ z-=3=|VKSOC1r~>xm<0>vC@93j!BH;=kvJXZY3eM_iqo;t56O$uQ31;n9pLyCoW!HB zNW40}ACBjIe^k+!+7?dOPY+Y8(P1FNcd`xrjB`S5T_^B4%=%(Gl-g>Ku{BM_tj*O< z%VcFKUkjP_<@g(VoK@sd8Zxk*AJ|%jN0#|!IJ@v*@C{{Nn5oX#E#Yxn!Zukjj*a^j zICzYZCBcId!f_)%@VyBhCwP~VO-vKV6U~fsBEbWNJcuISx3&+)UxmuB#W-}f;fTuv zw8r>ePO!<`=!ImPaVqd|JY}5xZfwj``0v+uqCK?`ktY`GmWIyj-g>dql0wAPV?u33 zNAuM3YnME4kl0o!&AHAgY`w&3$%?IlP4N#7oqmNTa>&!K&;%4(c$0UlUKd*udP5q@*dq8 zh4TJ|N{uIZ%Hf%1&RF&X{Sn0&dm$mS2g`WT@CZSuDx-s6#n5D;t?^&tn!A91+{Of2 z@nD&~wvc#h8PEFFuy{5Q<*<0Xy73Kg_=j%-vDf&cFghNFMPbAv#vg_4hr>U{W7z#I zVR8Q_y29e|;l}CU^CaC_?xerpI{kw-@re+xf=z)Jv`Fck28)!0e?y=s$p zfo3KF{+SQ^q~9mL%m2?lvgS@4(~x6Uiu%vk%n4d?vzIPjgcWzpW^EseHqKh^tuw1t-!ZQUxeUKW%*k!l4zGUs@?U6GzyLDO_96;7em+A-P#Id~JgdcEg(^(H~PwmH;hy=%I5 zDMV!GwleN7C&t=!NW&>*1kYdfu8Ka&FZqT)O+|rp`;43zFJ}NhNVeJy`-A++$+<8tG zGIya}!n=EcGkqq;Oz^MZUrPP;6Z)^M?b8P2!{;RWul;lQqwBNm<8^}WYu!`gtp2O* za`dV(?eL%PLH5~S=63>>9|y{EE?0dGKR9Fshf#k2*>=4V=!^$dB=?v0*pE zBbeX#Kz>;Wv-R5zw@m}5a}Dyl=Oq1Hjj&*TvydO#$@&HLUmt|b{PJOGnl;2ZVNVLk z45R&jqK$Wcqm%2u?ngW%Ukn&ifp{m=e|-_5!FD`{c)gT{u;ojzojjQ@;^fVwW-b6(DsV& z`9Gomipw)_zOu(_&6()GUV!NA6W%jU(0{FSi^k*cL><^V;VhN+pua^Awt(sIW#STX zkjQ%x{Vx}%h;zk-BJT-|S1x{0+$!EB-Y4!89}}MyUl89A-w_kyAH>lH~1@cS*iqG6ytSE{)Nn5P9FFoG0RzVr1Mh47-Tt{6ak5zZk!-I8Yocjuyv@ zpA)Bx{0PGIE5y2bubbrmMRB`$hj@?pW$_{LTjKY`C&ZtM&x>{SUd?C&>T^ipABuk# z`SFnTHRmVTP%^&;(*FXnjmUuy`WK29i5H78k%J?QXZ2qvNS-226S<-^<1G+Zh^xdK z#2ZBp;4uDX(dxg(C0qU12PN}sDC0jaJ}Yu0lK%WWO1>%nRy-npAl8U{@GyQ@%ogj3 z=6XPQGs&$*4mL7ff!IU5L>wSmeb-TvCy7(Unc~%=(FaGq%OrFBmgR7enY>BlcWug> z#cd+L2h;yldah3>{AuxL;tS%d;u|7AC^Nr5h#!f3u+u*xW{C~O#^MEH8?iv_Azm!@ z7l(+$#c|^0;xuuV_<3=W$S>Zk*G=NB;%0HD7#Hss9~8eOen)&ld|Ld8cu=(Zt*=Y| zjrdy;3QMLwABe}rzlst3d|-XE#B;>+#Fk=Pv76Xk>@8Y-*Flnpiep8q?@AQ_mN!>i zES8GbiDjbIcfDD1rFffIE$$ZY6CV)k>b+Wh*QXU;SMT*T`TtscSA0*T&I0TIS1}iE z$_>Qx#a1G<8W?`5_-T5rpHsZ);#_foSSqd*%fxkJT|L*^U3v5DA1Y$J9M3&ozI)qm|T+3LTJkj!^wmN!|PF3uJgic3Z6+c5qH@m6uO zxI^3}QXz-&_le&Xt^Vt?lAjY_5PvSdA-*LZ7Jnz!h+Ko$^c!9T$#gMKY$!GtFA%xb zF5`C=dx#f_{lsE%gg8c=Bu)`$idTz^#Zqydc$2tU+$P>3-YI@X{F?YJ@jD_loLK*# ziZ6-35PvQHMm!=O6R8qq`b|7XJWp&Rb`UQTFBYjo#q<-z+2UMrxp=L3qX>;ulkPTg zyGSi8=Jze}QE|WctoWSxg7|asb@5FRm(^+YmZ>kn@-XC4S8uszQMA^4s@`(h8Tc6-_F0jLve?%AD$^yP88|*@4C~^qHMmCH1zZ9_|m# z<%XNjt87tmKJ=E~EYFHH-`;#@eyqu^O_3i#fiSC*I26J{PTg`K z_6x-KV&`mZv9WtiLuX%2Xn*&b){CD$e&Yj=AK$QP)X`MvGlvU)aJ+oewvE{v4{qFl z{FVovJATuqXO3@p0I@c?yHcy%OFU@9-ta)^SR~|bd*z@P%i57w)!+{Ac*x1EE`2C% zN2}OGe0{%jUua{Gn$Tr#pZww{j;}`vYd3vxaMYn!x(_@wv^cUov^5HC-rx3wc5`7) zwe$O2&)b$+KH$)0vGl4|E5qBM*IZCU9qnE9w}*e98*=m8)-;H29FTe}l$u@<*_M4E zXGi^&X`AcC(s!(W$F{UbjIDg+orcxt?9AB}K0GkoePu(GDCszcno%zH?L~G zqiJ>Cw(`j1PUxr?3RTpvOxv8kwFy$8=leuqbGA3xmcH^l=rKDTu02qHXL@zRUEyuR znz_+d#aSrl=2&V)C|0jJwCjn(8EzQo3-jI!?dFivL1VO1N&Xt>>c6bnf20kO@xl~u#E1p$VQxTI7VZTvV7AYd3^FycZ7HK zJ2bREj!yTis?05JVO9)Bz-x;(t{sq3nYuZ=EqoxSI(5g^8fW*mcN$jZ?s5*toQ4(Y z+w*pWphccunFrnRCD0vjfnyL0H{II2DyMpIi^n3nOFA5Ay30WgQ;$WwZ3B9JziL3y z_wg!vL8!}C@~G=x`;FKkEGnAT=^*5SaW#?oaA`y(ZKN$D)&a>7Ncpr2(D3!}j9Zce=+KR@J=SbZ02mA=YeT!}2K` z$Cp=c+*sikE-*f6H!u#yPo2<(RFH!bHQ(U8 z9lQeiTUIPzkiDIYN>0 z8lpm*`dzqF!{9#|x`WiGo%D|wuVcOQUH)D;UcphvPN4MOO zufdb^U$a@BJDQ;pxUyLrcMQcpQsmH^JC-6}O0#pA)i{cL=ga1Bt1tc#uOQhwDURnT z$~-)^d~Is>!&fL7ZE8x3@Yplj)T}}=ei~($Fx^Co{|(V-Q&Zs2m+V`R!Vmi|iaiomzs`DGUN3_fFI9@S214R5d5oW^19q*q+8)z&t&GycQO`Ej4O~= zeV!Emb~@ad?u1kqr$indXuLGOp+^p_2&euTsCe_7hO#loeQS+5=Nz+F7za9`sihc&s=!Fnz>cEKX< z-ZDD2`PC{fqhk*&6sri1gdY|KlY3#I#YcP-7W#i{;&kv! zF#PueYSQ{L9-mi?|3u3G8z!f`s@@`cnm9SL8E#OYv*ku4fvOk4c#4GVQy zBG9lf-Rxa7W>4^R-V;2X_au8ZAJO}ooW>A*!XZ>=KTg%W)zPRGZ-5RTK4 zifSPwHBLtpUx>u%pkg3S`;NdR#yNrDFgp}K*Tm`YPx=Y=q(@;q<$0b%^>8EF#g8e- zgWxmFRDq7&z7USn@t`lH#_9N`FGS*W?1x2i>Sw>{JBhbpk<*&^AvoUm{m~L*YTG@U z?XGXCGLFxesPANR1{mjPwqUaFtZl()D!Q`jIB{!RFwRyw6|1gNqukb;@->iI^@mNW zajdO**gIqP>p&qd)z4h)%r~efN}1PpsxxUz_=+uIn=BZ|rne0Y;kIXwEVAcuwVMFk?UBZHHK?T_Z$iw7xuOt}cwa~Q+KYJtFJ=zxr=SSvGtK=-h|-K>z&s*a<9GIC-6SVn;dc{4#8qxNLic?|6Z3o@n)bteDL75(vSQl zEY=$@i_?*S#r=xleTs1cclJqvJNxdyoqeo5QE`*pU1n>@#3;)cew1WKQ2U+Sipdy0m`6(<; z1A^BKYEV%|$GIp8!dq+T;GF@zOYn?>e{~tJjef>|9Kq|usHodIBh%XZ#YA4mUx7uV z2)>u#4)4Z!M|jl;l^?C4<1JV`h6vunOqTo6D%KxWK+TNd8bY5s64v# zS5&7Ej()Hxn^3Yzfn<{c$tEF+F+3>jiQuhs z@WX&nSd9$l50MU+{;@;bKjz16lY@RXiw%go!(=hmM#HILLs@`w%Q#7HNk1Duf@8}Q zJWwItYv^^d!ud-L!7zB=li}%M4I48ab|UOmu(M$2!CFJV8L;zVsSU!uSOdEjmJPFp zbvO$90qjSxAH(9@HB;YM&dw8i3=f{DFi2* zI$(6fPdABRNkI=Num5AF5=@=if9&7_=j@CEDEk?``oDWdfjN9Ox8x$&!I=e9r;Z&o z?i4c$kkHI{IGG|oj{E=G%!1D_k-*%WJ~0#FWDTmFS%8-POU^9F!c*z5Fs>6?os*Sq z)}iE+iiS_Clg=yHjmO|WW?lih?d-e)zqk1V$2aYO2(10_P$Yi~8_yrR;x9?xFkX#K z1h@VDGZJo_hA}%MU}_+q4I73qj7cZWH!tvi;hYN}43C@qSTBAjv1#CRzJL+&59yGx zVe=tdH-m0K;>XMovmeohl|T%ZyQj6|?9Tr5c?Fj=beyQ4mHBV;yQWTl#dsUYgCE<0 z;qzoWZiU;Xfz!DP`E8^_#)jPtIat5($j`hl!JpR;`7O+GBmb|~1luXEfO{{LWu@g8q-X7dUPp%{NA^9tr8UN2Ta zhV`Ri9|YUc8SSwB+yG&=9rfT2RNL8u{C*8TYgl(0GSFSlkm#AsD_D8K$=ks^gT|Ia zzq9iS>O1H*)91X;pL$+_c^aN(UIA|5FuVu-E%OR+${4+K4meZ)oL|ex;UWiYC|@Pc z6c>xj#kJy1;#SeO+(>LCn)Qj{ zf4Ss2;&RdGQzLw{4-qGdGsO}T@s>(16W7cCR>@l=-y!)f$sAy0 z`436v@>`VmOa77MSH#yyJX6d_B+BI*IpZ7sXUKn*oPu+l@%UEG`ZXpIues!QlDm+I zS15m@?~Hf@B#%%$oDSxA@gB$H#^(UZ`yXi(3qUg(0d|ppfynzQt5I zAzwS+fuH#)Hy2xr?ZpDIhj@u-hO?1wsN@kMM{}6pWO2GUTU;nE6|WVq7df)S^f!w} zrvmcrl6Q%Bi4TZoz7OJ=>l1ub{yz|ZC~}OM`J3w$q+SDMGv5b%U-E}ygy${%v&05s zBe8|pQZy_5A$}Lh7l{{(gT$fYSkYX+NcTC()5W>s0&%%`tynIa>l*35D7jLs601ed zuVj0^EOIoMGQVq)kBN_q<~oP}PbL3c{4bG%#Z33ENKFvRP;fI0@j8W^Dsq&Z^10&q zBK0rm-&xET?fiy8l81|!+PsDW#p@wbsg3O#B90QriFQ82 zRg&#|2D{GpV)@&3zU!{-|&0Mc76k2)EO^LwCj8~klaW-U$pCd+xZRo^1o2*Bii{5LnPOo*Dy=|CE^ls zxwu*^7dMGt6t{|1;%;$|_*L;C@e%QR;xpopMQSRtAATjiEglkoFaA;Fi$3Fr#Y{0* zY%DetTZ!$&e6dLEBVH=T#9?CHc@bC1e}?#Zagn$}TqUj(ZxX4B$@=dQ?-K77zb5Vz zpAerGeH=yeQ(2%o$-%~t;P0YXE9$a z66?Ot4UzwFvF`iaB>7Jfr-`$~5^=t`Qd}*XFZgJ$sV@|T8_U02VULRnqO~SD@8-g2 zG~amp{|oZ-d-lYHn;zZseUCHPFW_19ElhIW&3PD6t@+mG z3l?LSfB|mr!s40J=9F)CdO?f-uYdgbulG%BAM3ZT=CO~X$Dy}RJrVrDgxx3b-(3cY zFa325);Q0^Z&lA6FuTV2wTK1ve7>Z3_wtRY?Revp#^D}s5Z!i-^A8!vyq(!K&TnFH zB&7%em=y3XlGiS5{$G$huC<_r&F^Pwe_?aJd1+zuBXpXD&7q4=CH#~ywDHHm0sZ@j zSf6lsfhi@-@rP75yugjZJ8cpqCyi@Cl%>^&b4}Vr{J%ae4gRas2BMwUr9B9rRZgTA zgz$3rJxGyd_y-OChk*2OXQa;H8t7C=$TVx9Q>i`F%E@YvY_JCUy+#aW{f6R&Ip$Pp z70wz?v6sY%6KTW}F3RDXb+*g%+Z|zQ376B8|6p8>_vBz5^pSK#;gd7maYwO0_PEhd zcSp0pTPU(bcMJ=Bm?BGb$5MQY;sA={9)**mXnCXHa3`=|`0`(`BgB4)QQsY#QyETO z;k0bU4^v)Y>-z4P&~o^X4w;etFdN>$<%$C?b(mbYA<>XS9SxtsKX}!1+vGIJ^m3Z! zOh~Qgj&<|+^QpCynRy93aq!M{yd10_o;kDuDkFcKVJW$Yf&&(IGc&ooI90{d+9PhW zY#at9g0eV{17p&W(I5~vGaDyr?YiXno@R>CGUeG_-Al9la@%DMZBWmx@AgZ*eLxmV z$w~23B2Q|f<2AunkYb+n)D>E9(^?lzEI_*YH={Q~8I=QY|83ys&%BGW`evawQXE#% z81yVIxa-YD$D<23?-@zM(-GQIM4@r=D~H*t6~4U7F%gvF@IPtV!UbJBq62IQ8i^zm zQjvO0oGw2d$8nQ}1w$c-uyMx*;*L#5go7DE^Cy_^xIo--!MMx}T3{yAleJOdVN&7E zZ2Hb{bT#So<0NnJXgU5H!+7jMw#*u45i~)03eL`uSrsYtpSK9;+=X*Xr(%uBze~mE z1;=e2EA$!|^`1UZd}-TiO3OChoUS2m&%SW^g7MQAFAJ<%*?;VasU!N2A2N0Lppk=t zL1V{`8heWM0R8F(7P`a&fu+lrImtZ64V^q_>WHD^km0}~r_oe7qtz~xxsD$+Zv50( z|DnStj2-mvy(#>H*$bA<=1QW;J#GsMmb;v%;GMLFcM)n^$bY$%B zUl22y;kXF{2M!uHE}*Y+<{Bh{^FP`C|Cu#2Pp_oH(?+C+GE(b@8@lJXjl9P0d2SQ8sn^VH z5o+mvVm-{{eH^*)KHNX2@w(LYDK~~UcsGS^#m)G$=&PV5T~E0draid-`id*~439^g z|Lqnq4|~!Y|9OXRf$(5F{9ZJMzXpPaVKnVv`7`~~;`xu(6U*g^V2ypk@{ycwJ;A>9 z{QRK?VV=T_$MP5#Eu<&cBW zkste&_2V0ZtsmD^V;Y_hG!Nn+Ot2>pWQNi17i~NjzjfKC*4TJIga?u@w*E^I?_~Nd zuOR}{So0v_*}Un;`qBIXHrS3mfqsEA*$$jW$#Wh~=T+o)hz=QB78y7#oxSLce(>b) z;QFvEHxHI&2D-sH3eREiv&QCUWy_%dKSIAHYBM&pz2bX%=8CC}@X3ARgFVOg_=5*F zh39X3WkrOWcgcWU&uImT{oxz-c&+iw$VX6S57rv4tI78g_6eT{)NdJB8|>$M@~36; zx9h2uUXsrM{m#MUE99Ml>l&vp1_7iGfQyIc2K5cj5ziyh6>UhoqVXQb@B;A?agfO4 z&hX2{DdJplp?ICRR@@}=9>Da~;(g*i@iFm7;tS$0#b1l>iXVy}i6L|_^N)x*Vnfl) zKtcEglDmi##987pah+Hp)?HulZu;ZY`j+^F_)pP?!TpV67Hl64#}|1OkT`UPJU=N% z#nxgcv75+qknxP36WCw!AaT4nNt`Oq6hAL660a4l-p4JHD@1eLQH~iJ0`HOkm&J$0 zN5v;aj-Rle2gR4fw?uOuApEH04@8dWFr7IMz&y$3Jb=t09)?@}j(o{QqPcF;{Og_Z zXh_@N7u)>kk6Q)rnGEk%*t4*E?Qm!Ge`mZCvnw^;Ira?3J0C&aF_?Aw@lM34-P3Ui z1TRXTHY4~yl)`zNo>59^YfhC=S|tO*DQ3KLFMG?5cXC!X#ydOnOpc_zfuP#)&KDqg zf8;-ZBgb53+hYJyc>d5Q&r9!w@lK9|n(@xdOorhvv#fB~oS>09Wp{Jh8I>Zxfe)|ceYE8cXr4zCpE@9qsShslstrZSf#`t z@9dNu?<{6$=Q`t^T{Pa=5oz4vZWI-v;pIt_9Pb-0@)L}yOF0miUsn5^T#_! zC&xQkqCfn}%O#gtxMO*R@#@GM42L_OCGui8)p%!G!70W&sfl!Uyz}gMC(a^k3gI|A z-Z_8ytl3i*OrKdYcj0VjX74GBmoB<`>GTEBIdkXFUKVY?vRBUzQ?6dPJX&goH1L}* zYR4v~U*>d|4|8J-~PBWnRcTQ=1-Z|ZPr$3U$ zonMk8R40scn(20C=GLiy)N=OKX~#K(^YW6Ta5GD$FZK6mNqS+9m&V0T@JiO~>^P@J zKFx%@WVifd$2rZxKI!zl6Q^mOeB+K#2MmT@$7gf`Uy9~v*VrU2aNw!@Vo&3gT_01^!O~}orOic z{OF&)uKFH)mw@?)=y!4`%)jG?-5(=U_i_9Jdg{b`uqh4toh@)HHh1HY)$d%3APjPH zvY2OP*jfF~yBH8oNoNW(Rj$_pLzDB;94<9QO-}6Ci2!PH^7D0gfCf54 zX0_z-z#Qm3AT*q{mZ8NGp~)FVs_>v3j;&|A96ZIyCTmHP9NBD*MAYOQK}QrJ)Z`q= z0?o+gH{k0lcAAmR8j5BQdwwa%Wr^+>mTyKjS5h3y@mVvn*&hyfJWEWDY<5J9PuJvR z!yCBw)Mm9eO zP0rcACg-P(Y@U2PQ#(4NYM(Nu>8~<&@=WlhpBW?vG0zTlE}K2G6bgFFqFv_9S=?pj zqJ^bPr_U_Cc+s3W_NV_RRXRW8P@;b}`Pux_#z+6=aZz)+oLH^@Q-htK9Kb)TyZIT% zGI`1W%P%_iuQrz1xSl^&+6cetII=>^vD3?8@$)Zf=EF4vza6cyVdLO|*WRRwBEM%5 z$ox1mWAmE{w@t&yTwmf$bT^;GkMuLq-Fz2nX46zI>toAZU#Hwuypu-ZXN|2>IXr^x z7}C(!d0{*F`epOG9d4TjPNyyM%cDcahSk;GoD|59YD+f1FT-uqFpHkZkL|F=I`4r; zuzn@TkH?AiqlTW%kMA~2lMhS7{r(1{53OMs?S9e5<9yjA@UzCo`yo7#e6jT(d4^+| z8xhau&9tl^OTdo$x|{y*i%-$r;;Gg!yGG$_ zM81GCU8Pu8ck`R_x4N58N#-~U(>*V~A-*lXC%!M%h#!l5muGsrwpk;|mx?3B&xvNw zXvAM7`9>1=l}+LoNn8+|sYyO4ni;Z4N4+rm? zk8+KM8}gxHJ$Nr5vqWB>l%ry6v6I+MJgcke_Y=pH*kAuZUCmyYhMqK^rmI;{*z3Zc zCibU~UAAwAgBKXPw0lCXi*4Q8Z)3fR|EdW)Ih843B(Gi-cKRzC#UVKaq=>-)1Y(oS2yJCc&(=M z{?M^JZ(y+-P2F-?Gi=;ek<~7Q-62zUhIULk;?0|MB($pW5qFh$xEu@IJ4YWX|J9N2 z_HG#4o0!@AXkunZuw#xp0Q*C3IpPd^{)jWV$#J*GOK{IgtZ&jTv3~ONN8EYs65)Am z66=SZhp={uJxxjzt$II?oZBS!3@b>i?YKPAvg6f>)=h3h`ko1|_Z;{)LR`r6N)vY@ zPN?IO#9bZRB~qHqPTbgJ^AT@V5#qH?+&HXV;>O9d6B{Noyhoz-W)-ws_pIczOl(kdE;o}>Ul>K zgIDcM%wAQ2^51{YWuEg;2Fltn+3mypcJ3=owCxxvUY6L?duigvj@=Wfy`4^P9K7X- z(-D1~?^cDkXB}SWJt;Zs@RQ!UBTjD`|R9TFXkNe zus=gyq1!!Fkz19uIkF|A(yQRPl!Khc)P(zBH^n}wJ98?VuFOVBPN!=QWNr6&7VVwX ztX^@rBCWDH_MUXpQ>xq@KRk>T_HZV%w0p|WIi69Ihn+izr2gtir&ZpL)WeaiQHM6B zWyW4WA8*ES$9Xb&GtLPd+j&inrxdkGw4MAS!m7`kow#@M@Im-*Z=`A9K?;4GJGf-Eq#!?eFj+&a6t`=^S2%p7*wA>wfnDTz#SU59U@aYu41|G0Lqt2fMvS4&?4|`;4s#XZDBP zxzFkJ$Ab;EFXhxDZP0&J?_|a@w;zAo`Tp8yAmDLWJ60X?)V|Ai^p87_ggn-(IE0C+!PFBqhqok+g>q zRQq{@OA&gUSK@WNkpH<9r`K~do#q3|fVoT@PRnFsH*%@TBfOp2N5cFTVz#-&SBVaY zml}Q%|FJ9Nr8ylDgS$fZ&$*o$v~toLA~L>8+-1a2I={u@tHc{d45#;EXt6}>3V8v8 z2j%eBM~2JlxLc7U_DrAcU&W7;2np%Lhfc2mP5#1&vZt7fMN3_q+=pO_5g<6c^Cd~q_~;& zG2%BVzQW4i#WJ|kQub>}v3okiHmvO>s8CXrvth1r@FtScuEhGEH)iQD*a#0Suw8kkmdE{FzJ~Ko~ zo}$=9@F<+M#+)!ZJVdMObWu zwK`4*_f#_5LKZcP({0vgL`0HxMh^_Jb+_?s^^+x_#H8s97uND1?uSKJJX%J_FcjuG zQziq8jdKj~F06?{$Gs>YT|#^X)^n~~9jAk9TEgE}&&0R&!%=y(%vKPQY~4&G6q_`K zaADmLf?a>&#*X~47&Q^b5Pt7p7h%uwn4;%~ldJ(Ut~Q%_y=-bVhIqsJzX!+1uuNcx zlCXVMI39u{)fXahIx>7AD^3R&*F?0uI33MkQPI{wXIN%M78>udL@!wE@V7cnM_=FH zc7drLnqUl@rM84gb{Zn=DGT)89@Bg55)e!@{9G!F*(1;SJyJ}*3~Q=F z2fN2?x~OxBy@Bc%+g?FlY*kNF<1vKa5}b;3unCA_TVivvHToVLubLW7BKR_blEZO2 zM*Bh}PR9yg$cocZ;R|_jI;voCZdL<)WWq`Cb<(tfj@D=g{HZWtrt3J9h)aCmhGEgWX0*2;|qClI#$3U#TwvN-$`&`S5qn-dwu_h0smwl`^i?1W~4p%F_fC7Xa1eb|6flVBX{ ze3zfr9u{O{>&9!AS*AK%UDbDA0y*SVjAH&1 z8HXh?d%BU-n6>!NI&o(~vLWK)-mtZdYr(UBk%#SO_ zFBV=U@F#c{A%1lk9Zwtoal~`Rf0-M%rxUs}(9Ehbdm)*&@t9A7MPCqC!J5qsd4BUC z!=Kn-{82eNxVAGgCAJxV6vnH6x9`u}B;ElTh4={8Y<)<_$FS+nawq-$*6AO#iMK{y zbcRiV7dFVGvnwo868>Eknb$ra#@S9cl~?bXqs(5j7a-kiGA@Q<+jJYogUln#u+ycV zhHgZhK}$j9HRv>X4LV(3N*_B-`q=5xXZdv*Y#$M**I+&&=KKCbNj@Z+Ie!?@VU^iE zb&2`UEmS`YcWCj4!5vzf#|Y0Mq#j1T?7Ii^JW&k?pQeU`Z4G&{=J{zyu@<_mjUxB@ z{v%1|i?T-9^APTlHh=mD^Bb;oY=!b08OZOlKz<_w`CS&sZ=}udEjXt5`CUd<823^` zJ~?r_TpY}sw?o}_FSB{@HgpLr?p%a^JWUGxczW3Uc;flYrzp-=-UDz}KAikjj0=B~ z&5uW}vnjh`D7gkU4?lqWVWZpHLuF%+M(89z_At_qeeEe?v(L;>HE!o5Zw}bn*JkE# z)nFvlP=+_4pb5%+N&Ao8z|sH8f*zbYYxbP!%jcI)ExmT}>}6d`&?V5wnT08WaO0>` z^Jc;H(h^9fFH;bX6QIg<$6`;$&MnX9HjGQ6*tF4G+}F#Cjx1>2D)QrtyLBtNy%x>Q-y5qF8VjMXj|eD7T>2MzQVx_dD}D zH$w!)YTx(YzCE8zzUMj1bCy}|%$f7d$;dS8JVNixXeJX@$!LVn%yGTL;XS;zJ-j;j zTM1=tv$NVUenAv@z2azgqjp>p(QBB|p|f{6)>Qn|i4LBDRUfZjp6h+-L>pv!S1r$& zSKFF{pK(D&;GXF zf~iI9jjw-DFFucr_PG^CpvMHC{A4Zv3=gg*`2$R&!_Lc_U*gofnO;8Kpkhz#y+WhQur?4 zz&oKmC{NaZ`{`58|JM8|KFZ-&6Sv^L;|&zoLb1+zd6&j?)?JB+Pt8xKA7bNjA!1B8 z?iMt4oD!rv1tA>sroITa@z`u0cwwF3IIq$pXX9o=wthy9LgpGNN)(8j34gHM&(a+y zn)>Z)Hs;qxx(apivN#7KsIN9o$uxwq9UO7B?YI{HVErzIKBlwI#;ry`P+#+aJ~qed z+XlbQ1Fy3V`rbcIKW{-?P+vCmv0qs~G&`>EF8HZ06C2&db+INzC4G$lCAMI?DfN#( zFY0lm!(9~5UgP#6-SKQZUqWoK9Vs}#yD1OB_R{Ua7Hmh4K)=*Nob8v&^P>7e-yf(z z&Xz?6n&*7j#2=kQv&|RUsE_-HWuhH%*RARC+YwJ7k1dDd4>2!_=Y53>JB=Yc5U*I+ zTo*Vj=R4bLzT}xR%EqxhIEe!8>o%c0ax0u?uG~SHM^1(F&{M1r`^$ISBNdL{vDcc)3rTYvf;>Mc*Ap9x?Zqt79DhjHLvmk{BQ(rELL4KS;}PN0B%d$N6V366 z_?42c5`QFKCvFsP6Ss@J=CfRLoPtkFeolN{+%Nt~JRp7|elCW%pP?sFOciU2^~J^_ z-{vxXhRB!dl+AGs4wF1eoFGmX3&r!q3&e#YhhL~~rFhIdK!jhfaC6*4zDe>=#Jk1& zL^D4S=^m5JQCsRaWAY$p0Z@Khd|x~$n)3kh{DES+B+*QSfLu#5zi7vJuH-?ci|xcr zv8#B7*iSU)3G$7QJVva%rs8=DpDSJ@E)mTjJ@i~D`N!fq(VRz!FOz(mxLv$o{H6G) z_=NbP_^SA}_($<$@v!)X_%|^Xzl-c2TEdd2ie?Q}$Sowd5wk>E!!mtOv5#op&mi2q zKLN)pe3Doo&Jv5n1>z;*3h_$u8gZL=t9Yk)kI3J7*6U&Mx8gJ63*sx{+u|R^gJMkl zi}-~Y!i9_a`Tm!zCe{$^iF^ah_;j(A$gzEfcNEVM&k_fU98qPuv&D17DdKeTd~u$* zNL(sjDqbOSY7F&m5^oZJBHktL5PvEDN_;|mO0;V$?v?zS_@-#rR{TJ6O#DRryU03m zt0Ho84`nQOVpvaXBBqO++rxCUeIWaYIpQ#JlsI0TBo>NxZN*~A7mA!MM7?%x#p@++ z5^ol76YW}y_etI7reX^*L+mJ?E}kjoh`HiO@oaIDI8B@-&JiyZ7mF*z%fxHMQgNerqj;CN zL;RKanD~^qOMFp$ReVc)SFF6oqKAiM_E(Z<*H)}0xru1kR^(Jcrtd2D6$gmJ#nIvf zak5x>4Mom1q`phVAB*e6&0?8&r+AO}nD`s<_u`A<8{*sI2jWNKr{Z75Q}OJ{`ZN+- zh;76y(XN?zrsUq@P;sQl>5|k}AkGml5HA)l5ib+364!{=i8qQjiT8>>7atLSE!wpe zcT2WwE50uI58|K1L*fz9uC17WXCt#0&$VJLcC1mEK};=C{|vhk@HR&|2y&b;)^0@qB8z3;@?CU4}uKGW!l*P*yllr zCLFg3hUPgQ=`f_{gfMtvpBFoH?3$Hr>`MH9aXStql!PNC{oOOeIo0~PC5>~oJN0s$rd$`Xa7xi5&STH=nZ;xcyElL? z2V4Air6x4~4-?8~@P6ElOh6cBk@IQCTf*!u2bqwhC4h%(G8REJX~GG7g7=I$mi=DN zEJjBXb~9fjiBDh^6UsMGBOji;EY1zA$|Lpg2oPX50MzbXL4Ra zI+%MPbZGcpAldDWB<>(+ahzuS2j_AYJSUUq(i25U3X5?EvlO->g?il~tibscvEf@d z6mNyE8lNTIVYk5>TH~ZP2Jb~kb$3*Fq0_N>b$6tjSsmYOzYq~s!c7pB<}P5C2N8g^ z_=p-S`R`u*L(up9Y)x?L^w(xgbLB!UDOj-#;XgZ9Ixuw_mzmUxl?AH@Ru)XFys}`8 z6Ra%A-GRwlJR{?dryZt85sb#PtaubW7|%w~NTLxot|3S=rN4$CJaNa-c1$B7s1B3y zBBU}#f*D7ZAtLS=gV|Cxf$NO5QD*SS2)u0gj)ezZP&R`l{&EKYR~Gh*FNlHz{-2!g z@x0?kTcmr7dbGy8gvPBWgt&&E|86<33g5TAoQ_wdViJMo8DO!&@4HH0{QWVPKkNGg ztZo)g&&K>DB+g z(`$b78^tAXvB2xnRIDY-OPzJRB=t^BTNS>{yZnb(-%cI)Z~tPy0r~}(sbk)++dd;h z5}JZchoL&-vPBEV(Y3;c$F*-wmx(l$%WaM@>+Fw9I|TT*h$E~gd`OR+jpKcx^)sqEI_L?d zA#7X${K0bj;U|9&!dNcDZMlo!w|U@o_CjBj9yuGg0CG@YZQTFzE`s`S+aK3=HT*UY zyv`BmV>;_>+!Y82>T4d*hgX(yeK*2y^H7J2iVqG1STEn{1odS@pWSbGl@-_bQ|iE$ ziH(kHe|m1qidwrh5bdXkw8K&qSf8TLEM`y1m$}pYm*^Y{7Q$8{_Oh_H%7)cE2Gwe$2z`Y=FME=#jH!k%8tpQ_#7+5Xfs)O>ERh{VWsh zh`Vh#PR&bZg;;&@1jh;gA>RM9jTO%JiXZYnv8EmSnf>9rV{3CVYufp@%l`c_-|x4z zsz9T+@^2!(+*kQUzpnN1@1IcT_gTBnyzj?;?+!hj4{(+^L>wtj67$6(@gi}Vc#XJ5 z%O8#{t-R;ftf2|RD|8%fNm@ND-B-hOe7lQCLTmE#$(u>9-lBnEzF(?C2&H7 zcRO2ezhAtG(cy%b8SxM!?0C$TjEE$3p{hvI0Yp`d$Gi#2OJkPKU0KEz^mgH1_h@nz zACGAd!HmZYg9qa=<~@2iyuhdqzlFex?-x&pn zG2&D;pFNJSf5Uyl&5%FE9Sy-9AOB==J1C-a%Mn`*V>%P)i6SJGMY$7M5>J9u>UPg% zC3sBZCk5gpiceDP$Jogn(>a8#`Uu8O<;h#RPZnuR!WA{6KrfV$mT-rWR{UFv7zDkZ`|>Qm#8A>g7O#~ zccK4#!%N?D?X;9) z&yFNwm6MYj)H?P~8``ll zya|2%q0yn)PGYsBp;bc3i8aHu-8ybvubz9VTitglsPS@sv*I7zkfdK2Bb!@P+6b+|QvUS#5 zfPi4R(V7)D5Dd5FRvrtx0})ZH47B=q!yeREg!@D^{c7 z^NiQ8@>m$>=jB-?NN2s3$HGdX&+fNx8Vk$BPN-!M9_gdb2jtHL={S$&0^e)?GYz-O zV_^><-N}rF9Y(t29e=x_GuSU10{v1OadyAefIm=ery(A3-a?plwqMA=Vd=bw2a;Y0 z{I;>M=GbW+tuoN+3j`T&F#Nw`VYT!K;P2a$7z;b@8fP2}!?iv>7RLMaA7U(wKXn{q z>M!Psy!J4Bl9(?Ri5H2>#B0Pg;ui6Ck>?KeecM>rJ4*My__6qjST6ou4C7#<-l}3< zk=H+lpCRUoQ^YyqA`)XrOT`irC)--_1`>L1l6;$Fe!zn1elGbj$sDO*`sXFTD0#o+ zcS)4T6OifXDDxa9Q$$`LDM!WT;`be6Gy4&GXGmY=F}4*7zf3gy73oVQZxGG?Mfh!! zw~P0RKNp`ApB8^Fz9{Y!d7WZ=4~a*_FT}rz91>x=8se#9Bay$Kp`?FmjIZ-|8RN^& z&Q$VmpKCSUzj#*~;|p(HIVGIq_H;`cZDs=SKQd3MG6@C1%9ejOlryqyk2S6NVsJ$e6&GF+DGwG@22S1irTO zB1!iE8q-6Z858D3!fVq8|3e&!^2hW-eOX?gX+~=jZC(<>DEx>6&A;2szvwgz$4Y zzH@JZ$T?O6=!qgQg~hl7?RZ=Y^}2(2>~PFEg{8W=6mNyE8qZaCusO0Z$EqHJeu|Lz z+^U5Luyd;lnDjwrKiRoe8a~5E9??O~ovKxPR`u}v8S8Nz$uUD81do&*y3m-z@J?; zc{0X0_<K{n=gwhZ; zZaVzIa@*l&c@M(a4u;!yTm-+(1F!RIbYzqsIU6@0a!}t_(1$;x4>v<`eXHTOdEj;a z0DVknosGL30YQB!7#y+s_}FFZw*`KihdMYMpjwCV1|Gs^`Cv(Bb_7y+nKkqvK%LXS6=v3FPJ$M(`a zhb`ES;CwUQf7yOP^Ww)myv{1<+fR?2EsG2^&l!Tw?S(+zHS@NN`qHqmOtd5JuEB9? z+s;6%FP=c2VE7L)mV~?RfU~{g2mMdXt2zZmu|Isr9>y|9peCmdxG9 zoI>HG3lVN+O_?FdNSIeySh4X!i#b$7ku-4&g0McyeF(w`%P0)T;796p2960|#&p(- z?Q9c8E4IeS7al8-R&0+WU1B$ejtf5rf3l0c`!y@J>!8$FvC$Jnf)p0x4rVEAdJ6Tr zLs$VGfjr7##YT|_RJ9*5v02mITCs6V=LA-4RS=ctW-!amRO8klYVgWYgCjZ!`koV= z{#{2}nxXBLM_PD1V5Eg$bfu9Ne>T#8t=Og&OrKsbePVV-w`j-Atn3RqO~mhJ`?>Sx z7PRMk|B18a=FeU@yYQldtl0(gqpcTp>(b_5vZy(J zw*Bv(;eh`aSg{>*f4~o@{nG;||Fu7xtFN_ktfa!O?3f{xlN%Q?`@nn@_9RBX{G;Q4 zY$&DTfYBfj4;s_j<9xFAKW2P|*Ule!e1-k?-?=*IS2|qWjBADec(jZ^8)o~#@&7g* zpB3rn{U#mL@gCW_uspoI3O?WNIKlYJV5GCUnKcjFLxBM69f0tlz6YU?b4}_ZoONNj ztUqtkY#w->8lmHlugt2Hj^8eOf*ItjjsnQRa?|jDum@o*m*KYDMey4^@H)T3Lw1xN zIUBbCa!}tp(1*XTjjvpdFq?-e-he))v(Cm{fqK}r zUgfdr1|l7gHS6s0w;KV$euihh@(Yb!x+wM2RU1uFRl>Hvp(Y2 zNZu;mF5WGgIUGpGF-YqBwfKtoC-F1Uj;+`^IE`^|@!6jfW672zPL6KknI!a@=VOEq zkvvxM6D0E`JM*0<+0NOyQ8J1*`gydmoD`AA0p+OJTx=_L5Y4kX()E!%NE|BiJu&s1 zBl3xs^8ePD$~V}lo&H_MRI;+V$x!Xv$5gK2L5u;2Y=hRg{?u{WA2?h+wxghQ=DLE- z&Xp5pPG2{*6zf&@E!bMPX8MMi8-FqL-0R&lutKhPRbbMU zBd6xnavS$c>6E{2>gEY+Z~17YH)Y-Q&C{-*wW)CHxa;%Qj9)u;-L{;c<}}F}w2N+&%fXMg#E zd#kLkpL1$XJ*+(JL^`e6UH)`Q=e1qe?LW{l{f%;`D7ATC{DcOIZM}Nc@v4qq$;nMvFy4l*~{O)M73$01J%gal49|+CZ zf1u|Kq>Y9*?=Fw5_|4JK4A#fnRC_J!Wb1Rvb*CJ0u(I;I^M@b&Q*rGZ`(8HyI!@Wz zdri$Xb=Eywx6e=O-SAc2{@3q4;LNDI7Uia4jpFF;^0XCC9Cc^(+kWc$7Y;c6Ypn}! zLU?99tO@O~tp2^W4=6>9o45(9L^H(AxpVh{ME6C6y;&aF#?&ae&#t4MixNH5IDP+t z#B^_K!|QFo**gBUuI;htnpoXNH~hYC!;MX@f35Cd?5)--a_??X`UStMc9(Zs@n(6-h(YUz-JN(H^7Ti*rT5H9 zEZbckUBNxO8({$+doeXVYbHEs{|>jkY!+pI}n+xoitIn8dUdL*rC^Nm&3ryNO3X`9n6XZdGO+`Yd% z@7MV^?k~Uc-n;ru+3IA>*%RJ^`aGU+JywT)JhUD?cUAZu?8j~I;+Rc)d__)V!|1g< zVn>vRmyAR|^jfjIeBg=^+eh6sp*(#4+3O;v_tA>!Z#L9<8>OlQ$-8X}5;CZCf+e zJ&o4BUe~mBe*4l6YqHk1U6*;oY1g&en6W8g{TVr}bGGfB^t0a{aIV5WzUrKu&X;-G(l01-v2Lw#6H%-mn&iimcULu!4lZ$Kb(k{L`fbzSZw(G72y2C3pM3Lj=A5;L*Eu(lUjgbgc9uQJPCQ{XwJfJhkyK9egT zrHn#0icmmW*?0)W*r<=>*R8QYH1Qxdv$`}rPx|2%)mxBO23>K-rvc1^Bv>spH=wy6 zH9uf9j3<1}iFE>m>Y$%@+*BM86c_J2>roc9#yba6gVTG};pvbt(@&7h#s46iY=PH}NlpbEmurG;$IHpZF zJ^Tp0>x?Hh`Qba3(sPFi9}`9iX{MC%EQ|+q;NyX-Q3{nn0l^R1W6g7d`4C!>ePTuS z_z_YXukQ%fHw70M)a&u3^w7W!P1^)KY`kX^pBe8sA_t|I)b#k32$XD!;|J8yW`Y$D zITuAxjB)(csgH~yXQ^RJ-(O^#Vfv?H5!-QG#FqVF!llDJz&14fI*#aqE#xdQ3N1g^z~4kw;B-m{7KjCTZ~Nfyl$dJ?1@^Q8B4rfVcI+ymF*eUxT2w|4`vKt@Kri1*uv%#O(@RIebD_!VI8X=>e`gcipQt^- zeTNR%v()ZH2zM>xUM#`}q4W|~)jteJjDmNpso@BM6@wnzAuP0_f@4_0?IuP1`ok2g z3SH%@rkF~NBv>&N{n;h-j5Xn7303wrQ(3-pM|%iX7wOBF(!;Ns;Oay8oxEm4pa~<{ z1g;N(B!u6|Yd&7~9%|~JODC@4gQzx6T|!m-%2YAWukSm-PAs{EmAM8RYPKyM-n_T@t&PH1tmerb4%&* zYlW4*c_!%8ykj}*#bID1dw3~5e$9}K2iqOk&_aR-n}A)$7gg z&K{#}G_lWw&tG0f504J~ZWBC6aPU~gneg<&h9H8!efZHILUu$-Xf6%>qK{%}Q?TKe ze_$e3{HDJc8=64uFy65Qe-k~dY8`KlQ3bWeHN=1HP&g!$W6gptC{IQw{-65%Na57^ zn9kQJ>wB4C{N8bUbZG4@igsy%C3+issZstFM!8CFY7cL^5fM@lsp&Py@Cx$0#<_#B z%y3%ND~fvcqR82-anlZcytzHHnP*P4NfWPeH0!K%Sajg4CfP09w(WzZjn!)T zjAotLD6?I9qqEv(HNq0Z8QJYJ+YRc_Ver5vLz^^dhEkEVF*VH3HF~gYGyMD}ONXXS z&TP`I8J95T2U;@NlxWNL9ol9MSTnQzpiD0}*XtZ@Jh%x~gdP(0@J-yNjnbPmZrO%X z_vmSjyrEI=^gJ)QhgahhtOwnwMdP*|&urfmeTRjcp{qGpiEi1pd53m0hO}$exP8{3 z4(;0wW>b=*%?hX%t*C-}KyRa_O(~_oT;`&v*RZf*^QH(XS)S*8fz^?(z%tI3SG$p# zk9bw`_-&cDmqops+-N!;>RmK~c%T0o^Ix;(-i)YsDi&Lwp5e7GWaGGH4rJ~2F3ZEZ z)Qv+S%(B9Avz=&U(T{>ZhVaJ*M6rX?c%@a#(`MA7PsO7YlZ~Z`W zz@+GVt&bdEQQOws)Pq&fI?^Yaa#A$9IG<}H|9h^I%qQ;Px09O(e)0H&*C#c)DsoxU z<%w4$Tp7N~TOGRE?VZZOj(>WMWV@^XI~T=vHSRKvYlZ)O@Z=2|UAB+-f19oyLg-Ia z4ATW~PV9Zl0Hsqhr#XfJ@AdC;Opw*r7ZQi=th=KLZWob`wgMcsr9Re+?|E$=c%7Fq zQus7IayG62vh_2H>jJ$SD8R-|MO+}*IouSFsW>26F3Yp!a!kwSf!A4%p`R!{ayG6A za!{X>0euLgzGQ4x-xcuNJn%YY(8qMv*|e~pv%|jjcKwrMyiGjH5 z;1BAHLLb}7`f;ex>iY@&)W>^ax|&G9K@IB|$8Cpb(>;%IunTM=#WCGO*ifA!8+F#H z$Dd=eTX}4{MM&4p3Lxu8_YAgRJ6Z?&r556BJ8Hlm=muv8^zB2Kb*vj58EBp}1OxS) zx6ip0=t`q64P==?eM@ni@?E-hR-ctEgW>=BIVL<~D%`(f?c-zTn6Sqy+{vtcTp!8V zC%k5Gj!E3k)?S*wX0&4?{A*4K2Q80(&Yj>sChLgU#SYi5Z9yVYJB4==yNhRuLqt9R zQqLqYU*ti{@P*<^@hb5Kaf^7nc%NwPbaqMJE50VaExs>)B>q+8_zBBzAf6`n5^1Z) z_%S4QJ;yG{i6jo#x#D~h>C6i@gs+r*jpElxrX2$FZIirRGQWz!{0~XyOE$_+OMXS< za0T;!BJ#wdY}PggIb2HFtZ59=K!kd@>JP(vN;Ye?LZ)2@x*lR*k-vEiA0dtr z&lRVN#o~qHCE^P4D)C3+CUL8Hr)cew9+v#LxLY*G8|w4A9Pg(*O`Ijp5f_RViz~#-M85H4{*9tJ zej(o~*?g}E@&l3|5q~Y3;~4SJNq$*;U3^D0$2Za)l6*uoZ>ACcmE;5-XOPX>-k^Ea z4AxdSU&%7QjhHEBi@ijC8=2|Mc>s=-JYJk6@|`ZzaSa1%dh z@-5;H@d5D>@z>%W@g?yM@on)#@ni8*@vkC(NLi1tSXJaY77VW^HWbsvRw9QKnXaSA z_tupAi$lZ_;y7`FI87`R=ZF`GCE_aaYVpV7262mci+H+ViGQ7l&gxh#JXZsY%aDHJBYo+e&S$pxHwLnAWjnt#knF! zJz0;%;xh4aakaQsv}+faNxnto;4k&uE&g15NPJv;Qsn#trhi?0Upy%ORXi#(Ew@Cm zx`=OQoACN#W3h$UM(ikZ{x$WSCH57$o(RK7i06t^#hK!4alUwwSR$?xIirI5ZVfv}+fCAo(Nl6Y+ELAEJkQX4Z>S zsmN2rMq*R3wb)MVES@g*68nim#gSs3I8m&;rtyUeUo5T^FBdDXalA?4TgC0--Qv&1 zhs4LlC&k_3UJ<9^H`?)M>AtQu)4?FeJ|A@G*e&Zj%{lMfxm&j=-M7y<-_R6=VF--l zYh2vG&N*MZqk3uDy6R@mdGfkc%sF@ZR^O6*W7>vWXI5G7o{{iTU#}#Rv?j7Pab1m4 z=kQNUuFgr_7%IIgvdh_&Q@da4=4$IBTf%F+!=6`lT_k&SPNeg`oRqchdgr>$IXlap z%sa8|EDwPpFbsyl#7t*Hc;lU5+5tQ-VYc~~CC-sZxXK1^eJWPTZIQFPy!N)Ma;oQC zlf&@)a>kTLW;Z*U_+0wY#Eri>7>b--9%C@^-!w()f{kell1FC#ly-Kh0 z$kJzOMKaw_tGn(Q&m44n_bN|mn0zFXT=ht#s#_XbxBRmu_te;ucw^Fr$i_c9$y*wk z`MC}IC0>_Q8d;OPKJCUjhrI;ny3_Ym*^s(9d5d!-Ty^-t(aCpkzI{p0V<)Mik%R@uz9!+%I)4d~MuMTcaLPx@(Lwh3| zA3Wklh97(<)A_Wz)3iLrNjVZqd1Y_%W@n4{Q9lp+{Ko1V<~4pa(tqY@dy-MQcO()* zUwK>lbbIW&KG}~sP2HxUjP>MU*S+BWeg_lWtCCLJ3ps04d1S~a^m|`y_x9-vDTLh6 z;2qwZyy0^vvtQ?a$)$C1Y$WbU-h?_fXn~D$f@^9{F!pUil`YTab;df>6IHw_FVZ|iF>-$dt~nmADHW)IgZ2blc4(rPN=zf7`V~|R{X=<;ivhG z;6^wUY;v&=H) z4(C#eB=I9s6?2DoG9jPg!v2yy1;`!tm+WaqZ|@1zy`A1Zb9{AXz|lAdaBom^+NCu9MI^K6m(L z#`dW^cbH?e34Q&!!}FQ(udbPq?C}Go$@7Y`7{WmS_&Wytovgp=Tde69CXG|2GgbUU zD)z=z{3D` zDD`fp8ceY!wp4$yXDZ};Xx@Z7{`}@G6xkK-a3&rOU-du1ZC2=%xFs8 zjl`MJl;%?6TxcU*1F1T9t9v%v!kg>rH?g*3DSk22o?Cf{{lR(P{WSjQv-WHjGF<|`*rDI?{|TxmQ88; zZV*DGVIMqiQNu5=%(kzAw>L(^JgebaYOpDdhMRm1>_X;#ml_@#O%3cqek|X#;&=40 z3*V;(o6@x63!|Y9bH0!5S{`3!|2@JkOi8v~Xv8KI&HgiDM~HqGGV4KX?r-+k!uuoA z6rM*93#YPLHl->2B7~>|Xz-Yd&3&b2BGR)9S2H6I;2Y^-7w(`2o6>Z^Zz?n}H!lS4 zt7EK&SFDBuRs+|Ft7TIf4b?Hik7I~APr>$ML z{A&7z8nHgay1ZfKLs=k~Nwy8)u1VIOzqR!;@h^~uc~7lK14RRoUG|VGC$x-hk!}5YZzCk?0d_^-Z_8H9uNA z5mn#R!IyWNq>=C?D73-#8vGkQE7zpA(vne7D8n zpfg}PQlpWZWtN)Dt9p*9K+Oavt5yidd9AAWTolio+Sv-J1e&FYbE5hdIUs>jsq% zE)VE`aQS-``X4;5euOqFL)N(Cfh}7Vbyi-Wv+@F+#k)`AYT`dH0J2qKO%l+TFjcX2 zLD%-;I|}pOftEh-7hz*Kxd0p5K`g@NImOG$=vnHAv+Xp2z%*cDD>ftvmCcRBv^ z_~J}?dz`^+fj?%PVF2$hfXA^h1sOBJBkTbcoML}`W#jlm)Y0S`ck;Q;;T3={Ff(yM?_#EuOPrX&F7AW5Z4+zVyQvl|`T|85{kCVyLdJ7U2oKkAXo%08-}c9D*TBHoMtr6YS^t|8N*my3d2nxBFk(AQen`B z@ObLSQID5QUFI(dxMcMIK+sRl-V3F-(_?NPcUtvQvZ5MN~ z0d_U(huvV5<6kpuJgjm4kFe($`qUhkJX0BN)3PpGu%Xff3x_EX;WuSG5yOV7CXahh$e>HGLAPyRD9`QLg&spTg4;PakWf*rK{{I3SE((5t|AfeW#{FoIPxy<1 z@lTj6@q>vPUNJ#&EezUeg3iHz;~4Zgwi794{61`GEB+ft4d!Xbds9D}~8MvSji7B#$!Eue)d{EJe&Moi@g#rudsl`6@M?_R*21!fs^b6*wR23@l^~U!gQ&j4E27QBGMptSz z75G8%!+=4RdXPciptnLvyo0I0*BjrN?8$@J0=-$0Dt<&&1jY9ZGy1y5!e<l6f z`KjU=S(>isRu@wpCu600QRJ_D;6P_krAjb`9~9pYRP6`F>t$2%x5zq%RjNfr&Um+0 z1jYN1vw3(O3{w;m-XI)T74#L?S)_)8(w$!@H>1;R| ztk)vcG30bc&XZib2Zj^=-yr{+us`s(VEU;1wel{Gc5dmxR4OIvRgZcF#*(ah z4=+FJrDh-`a{1uFgS|9Ze?>i59o5Rn_U5kiYDT>|JzzOjr$@_h$onXi0W+m7m*i$c zc;5&&U6KL++s6MhQ>qg$?Ob7LHF@&rp+kE2%R6SV?qiK~V0#r@y2q@6B#SHM z_N{u3F(2|jAbU*EH$Au>Ld6ugtvX6WL$!XXCi` zS2OXO@;&XZ{=05>#SgUo6>o(gj8@|j(RbORg-zEE0rV#-g6V=k@%DyffYK?M^D*}4 zr7S?s>gx;Hyirp411&MHAFm2dfs8jp<_3q^cn@jw!0XJzTL&)SV4d|AAi(+=_dG@{ z|7?ci{ggItD#T#9OEd6rU(GL<<*^;)0&F%9yv`%1I!=@xIUC0t+MvFV&+tc<*^Xpv zR^Juy+dS|(`=M_GJ#segQpiDlUqRm-{yhWSy*3dl~aJTao52g)c0JE zle51%f_u#m&25KKXY^6$4(ZPHgPqr#oSgktZuI2ruT~*lH|ZwqarF%R!FIfacBCPU z{ZdQmxZi4Ev&S;L&cjjvv73H6+b?9Gc}`vn{}#C}!fRq(a4 zwhV^<*Z!(zd_8VnGmc|_b)5CL<99#in)7|^uXsGsE~mekEAo+*;Sui zC&WD>XW=mZk0k1UNb)C=zmn|YL}t9P`#}2Il+iEN?!(x5AUu=d;OSydrRyUORye<3 z#QfvMSqd)}mxv{bw{{&rQuum>Tf2^%D5HLNDt?FLosu7u{EXxmNtFMp_`bsbES8IZ zQ@o3d8q+6}XkQJxbrlR_fAu4HRBVeBLjZtNt$9!l3+>H3Sq6wbHw z)OU_JjYNBAEB*q>OC*;_UM+b&iToSH+ZAr?AW;58k{?z46XLT9e?jsq;@c$3KcM)S zWMlULeSec|>>VK2!2Kr6uOl`m5#CDw#L7)NAY& z5MGNi>Q#?~+?+&zv=-Ydyeo-xJtXHy9!es;wNDtUcw?u4^o5cyPxsDaG;(_}OEkaZNQYZL6W>=HAPyJ#%s_n;#K|HjgED-+xL8~!UM5~8t`)Br zIU|DkZxQbjcZd&(=Jy}z%3U*i<}C%n+^J z>lut^^;u|(wfH^Z+Hw}{)s+r>M@Ux+)!C&Z`3=fxMq%J(On zYs>Nuh@Xg`i+>Yc{+=V9xnBWOB=d{U3_n$DCYt*egd4kWkTbZLu7}u5_oBI}U zyyQvZEOCx_p~x4(%y+4Hg=p?y5WYq7E#mFs-Qs=XL!z~NeM<5!ai3`Jcc7Qg)-3n1 zXzg5&N)G9FKT+hAWu`w>Y$~=8`3*_NoBJQItK>7pzTyCJn8>f|F(2nZlh(dapQ6${1lM9vIndCSGi#nocv z`={*+xAv>{e#zRa+WRDa(U*GvBpwjWeG|ezll(W)MHtg_ZaP_8Y#=rfTZwJO?jqM? zX1@O7AaR6f@1rJ2o-A^{JM$Hb7mJsOoB_}HQgMU0MZ8tKL$r3P_e=hj_?XBk^wekV zQ};=JOMG8ED4P2#`2Q~XyV|F==KTorwiC^L7i4Rn+Ed|u#KGclajZCAED&djMdAYS z5^;rirFf0FPP{?fD&8#qRQ#Fv3vs9TjJR8TNqkNGgZL-$WAU)~g=p^6&<|C3-vU+> zYm4cO@;=Q7^Gd1^V zNVi+zdqtW+Fu%1grO^ZBzlyYapqwny?18eiBc-JS(@?I0MRFIqd% z3nkN3f$>*~G<=}EMWp2e<$FXLJ5YW?q|F26m&N_!A4D2HF#azhO&uslL|QyhZXl+M ztwb6^FuuD;GYHDo&ePg;PEk1R9~eJhTp}(PX%@lwwIYooDE~yH83g4AMOs5pepY-@ zd{v~81mh2iG?AeEH<5M>l+#37MNm!`X%<1bi%3fd%7a82L{Oe6P8Vm2w2EN-5|MTg zl&=+O4ng@Qkya6u9}sC1LHTzgtsp4x6KM=V`H)DP2+9tgAxK(8khMgbEl_SL(g=d` z=_0KlC=U^7_&|BGNc#uM#UhO!C|@ShGJ*02k#-K0?-Xh1K>0C|whfeD5NYB-`A;G( z7$}#Ev`wH~RiqsP<;Eh76)0zkJ;YujO%fQ-Px_PN#YrNK4;X%-NJ9h4SBbPVpu9!A zUA$AIxdG!J6=`ljd9V1U_>PFn={MRJ#@13Lhel z5XXplq8V>R{wb2Di$x;ey-@!majAHvc#X&@E=*UOGOX=v{o^0_?9?%1UWaHjzRr2} z@z*)e>e4kcGfMaE_R){0qcFUpVjl$UquU=!yL$DGP-$q3bLC6r;S!gta^)r;`A7HH zBHp@}$|I%W(#S_RLl6I9g^Sgc>TP>1($}r>kr!^*DPbK9H`jZIld5uksfHzEu>MW$ zZILypIguj`QwHSJ$$1T{YE@a=X=eJA`7`sU+&}Y{DWA^#Z^yG+*c2|i*Gm-TKwuE@4Oohh0lBSP{Q~d4keDCmUB2ZaP^MZz)j#L za67mi+zIZ4vG?J(SLEj8=Ukez_K=hO;vuK|3y0j~wTD9WUpVB|UwbHg+6#vgPFs5@ zvHRLXNx98qB?nu@O1^yYkek~o=IknrmF#O7bM_U)N_G{*oP+7HlH?h&=$A`k*X}$c zR()ry*tUZ$W808Ew0Lpsn(f_V?YFm#MUi&fzKdf&+H`uX-KG|?=)OgxizNj&!YJE9w`dqFirpYa1O%E=P-Lw7T*fpC9 zVmE!sy7)TW)iYu@9h?zsTE8H+a#zb(2xZ>0echpi^IF70ySm4mWLxHv*fyhYdTiys z^w>(2yHagw3LPP|edTE_V$HS}#BTnwd+eHBsOP@?*v;Et#GW}L)^2BJEcGCC?Q0&p z8U1$irdF|LrVdMDKi*jwyZK^XXhocpKj_FYqokxY{ky}*sAUd9|Lira$>r=w`Y1W{;1Q>K*FAl6s=vdt=WuLB?%~*g#XDk! zix0T@7Z4-e!OQ+{~WAhb;jgFofl)Zt22h+3~HTo_+$6H2R?Qew~Sq} z*gfMS{Qt{dx97VENjMTtczGj&@`cAr zvGg1?H(!7I0O2><={Hb{37p8UD^RhJNb-4Rsv8f0?2hFIuw%I7d$ zHzW5#Sk-5#=kyTY0bU4i3Txt?Vd8gCW>wrCMxF?7${mb9)5shrGOJhhG~!+(!YJGq zH=+h9Ync125UbCxV5RU=X_EQ1s+7$Y@<)`B&c^dAP$}4~%%@!5fm*pLZU<8ED`{nZ z%_xOGozi~~WV1q7FH<}}8dQyj=)Twq&nRY%E?>OVh*+e{7daALZBe!r({X1}ZBb_{ z&NpHgEB?laU9DIPcgtplFJIL-h$-CLZg11cNoWGs;_720-YTbXd{gpR${Z(_Tpzb` z)rw#u-`6x^jSRa6Kt?7A~+t1iVz*K!Io!f89ljvctrz{6>8$nuk|RZ$S_Gq z5x$CIUqy}|9?t?#M{F>KA=F{3f*rOh*kP;U9mW%Sy2+VG__ZHLgiH~61P3T#Dbxq> z>z+pp!v+J&a2Y+Ld?8Xs&sbkbDWhkKFQl1uNBF82#$v>U#+yg*g)eN5u<#K)tUQc$ zZ0`gnrl4H!fC4S><5sWSet_gV8qXDgz8zd1Oa(s8yQY#en_LC7f` zZacunF)!Wm^yQ$&$TM~txJ>@-pvoEhU38gOP)_OD{FHD{U)R~xyW02X1@xZ%UG(0E zJ%Kuo*#%NJ{p2X$--~5j?)xXQjAV2%(o7`Pjxpb*ypXSJG|S*k9CVFl8F%~s38eIn z{w{hG{rsb-cf9=6yUF*D59l5BUG$n)Zcgb)>f${R>N_%^Yvgy)^{$_PL=03LN1P}> zF9$qjQQjc3m+v1=@|0z`J$2!aAD0X_2PFRS;?dFHzr%ShO5bp@pRZ#WDSg8O`i9wh zQMc8{>(6<K!qdm!XM@kH&^MU+ zcqxUxTvGZ52lV9z^bNN9cwxTT*O$vno9dSv&^I8UFE^lXKtNxv)wd6xoxZ*SWMfmO z`G&kihMf6Rg1UqHtd3XU;YAy5>18k8@b|XYZutAyOE>&|?Uft;e(YoR3;g}b+kAfx z$@Ybu;(FvKe)vH0OFz6J>DRG%X+<5EEX_l`mzuhl4kWi3{}SFO8E1d0aohIQvcPTI zSIcYhjv#nu;zxz}92YskUVz$s`E%AOeLfpY>qFov!6&xO)+SXW(Jdh>jpj?J$H`+}0{ z+B;a+M3jP5!~D8Z>WK|y=8@bxsOzv`T`%|JCy}f#;)k{=4x6@6e!-8QOtKA#AJV2c zV&W;YEzm!i?Be_LNVW@UbK4ZBnY5Hw`tfIz+}nsB(5ASyi4U|rFVOZrZ2L^V?PwL- zPDyR=6Ks1jYJ;{9_1jL#jNv$?6G*ikZL8Q%s}at=A=P%Yt)lI0AL1vGfA{^pNVe5) zTZ*YWq?JCRh|(YA`VU+c&BBGvXm$7y@7K->GW?X&&1qg8A>CAGb8u5L&LY2^XaU5bYf7x04dvhIX7os!ihqZ90c-s_)lnJgGLJ z&J}Iyu6R;yLY*txwAPOwMXF6WhrZUPK7ls%XPXxIZ9;9?CQ52k|6rR=K@HKST)$0} z)TVRE@qX-pHh<|29hB6{bIGlKEUsXE5KD>eMSq-2zU#;0%GDRKl-PR4k}a{JT%1+? z5KF00v84I|?X2jBt%@hr4>+H`)(<&>e#l`zEb{vSEo47XQa|Jb`=P#HTeOtdSxV}M zUgRV{7A<8zP*OkiCU5p*(NgvUCG|re@_j!REoDDYQa|)1Ps4_Oz!}DVpv1PLm->-& z{a75A{SixvEk|ts82E`FtCmsH^?P8T4+gRimim2w*0B#LsSgI)K4=IJ6u{vJSMJ&h zuL%jteo0Nxnv=9)&+k65sCeFt;;D0@g|lWC%#XHS)U8XKi8JOdj4qfrZ}$8sUQUodsrtckOH3;2JP$@YVe^gL!N0xBGP1mS8Q%F=`V`KqodKix z4p{j#6YGyPjSfFSR%gE!nI^CUmk3>)L92XtusCbY zj1F07v2-r-vvy{Zc^MtE5Y0qZqsTQ(+fl1okkz|yS%&w5n``4oUX@o-wABy1Jfg%;6kTy`}c}`Tne;e zHBx;=!R#}$AN|!%XU;2L5M|1_3+IfPS~MTuGKjBA8u#?=KC$o6(St_&|0jPZ}f=CLuO5zIC|c~;{1Y%1N!!LPP{y+ZNjX%^A}8=n_n=wuv16>a|`;6 z!2DS=<`ztknyUVLFII{lq7-aFd--1G$I1W4pQz*5%lAp0k}#rP!l+Xc#?($2TQeaq zEn$3W!o-w>Ny)ua%{!WZ-j*I+ol#scJ7apmw1qP!&zf5}&yj!Xv}wf!7Y1Wz&&v;r zQ;Vn0ol!7981(g!*|X*rSdH@+6gwID^XAMc!10yQd(_a3sS6eq&ziPy!LeEj@iSWx z=$3EwHb4sewi(+}CeG%+fb(w+9H%M5m=3>l##K(oIJ#EYBG|qy9Y+l+ms=XR?XccH zN(UInIozwPa)j7&`92MAOylme*07U9M-i&Oih{O^=+7n*!PT z8I=a*uh*o{cQ$S!#9+A(w8daw9luMJ)=AnvHp)cb&{mg;kpuXnN$M&&) zso1Q(ZSYfHCN{bOO>paJ4<^Wr<94TL(|yqN_;&OUARVex1Q?gs?D%%{+?UjA-Fl=O zV+D})qk9rtupRAsSM>8Y+0lOpeJ>jg{y$q58EBqUf)il`0_!5YHa3=d` z7Q#u!+HoEw=Q5DgMVdK6m@CnOG7ffL!x-L4>@M~e`JBo4(c*Yc~({*mMjl8xOQ!ha$8SBig1GN%}^zOP7rL-PBQIX#Q@iNh_yK2r`UmjwQ#9u}!VgG3Bz`V_DSA9_kuFJ06Kji&L~EaFhTf2#_hro2 zSv+0rCH51|_c@Smxa2&M1B1+;FU}CZ%}(`lrCTj>rY7~=DBdP+7p;BjFC{-NJ}K@N z?fR>g?NmQd{72$vV!3F)U#K*+niO-5Jim!^C`AU6%7LSVm5V^V) z^)iq>8=U9z=T?I78%r#e9LXmOlq?Njq5pD)f6?Ru(9Bws3CA^uogCvFzY zM9$o0{eLO`M*N-ld+|l_4e@R91MwsAQ}M4NX981yb*g!O5ttA%66$|DZH;( z*)Fy6I;r!O?jmuyc&T``_+!!9pKg|Xk9fcMnD`shL=EB*4ml&iTUS>>eO+Bq zS#MogL4CbeTwD(XBnzI|Mc4oHR6jKtA}X%#{&)AaKB;``S5;kCSNC*R|ElU!@qqY^ zXx0NkdnDs=p6ya!Y$(>8XG&dY#>zd$dx>`b>Hx`h{%XGD)5MzdSgB9W{JGy7Su9>AE*7s7SBiH3)0-vV zF53C6_e*|Kd{%r(d`0}D_$P6vxJUd{{8IczwELb?xX@ps}2;vdBS72g!!7e5mJB7Q2?oTr)2h!2au6Q35h zh}*&2eF&j zOFTs!DxM~e5ziAZ6z7N+i;KnU#FgS&@n-RM@i*cl;*;XD;_Koc#rMRW;$Os1MHgdS ztZ#zIi9wW)5?hOH#ZF>3ae#P=m@l3tP8QD-XNq&gV(~I@nYdD{5N{Um7k?u@EFTNtaE`A{H5;@h2_5E5*#y}F~I$}fd7%^RJEp`w)iM_;= z#GzuoI7S>NUMS8KFBXf%>%?W^TCqaBUA#+tSbS9E+%?u`oA@X3J#mlt7x8P+#lSF+ zt0kt2$B0eE)?!<+hj@b6UmPf&CXNv&h?B)R;>F@+;+5h`ajkf>c)NJ7c)$2N@oABh z_gJqt#hv0F@l)|jF#+GhOgo5m#UsRYv9;Ji>?HOP`-_9cVd6M(f_R>Ip?HaSsklhI zMqDdah_{P(iT8`Y5uX;H7x7wT*89V0H}wPz@p^5@?L=6Ae%}e8P3-t8_NDLCDN=2I zXx)WwJvw*xWB>5F3m>yExFvTssNR=8r!+KoYgKsjfP$+w1oxK=thN7}9`_&kqN>*N z(8{IJls$`Tan8B3Z$ZgT;redVoZvn$7+jjTEW9#dd8g>0Xi^mWl8?!OlP{N`-T z$;@#&oVYbq?k<@aJu&JuchWD5HY+%;U}wSa4mjxr1!o!FQE;Q-M+NSQ!To8$XAzdL zKP_R`w#0Sr>hKMtqLXqG$_H&+9K}xa7oS=cJjU()>;X6Z%WbDeU#}CGJ79Oepugw( zdvgNIy_J|deoD%o1u3Dep}8A(hHjW-a^AkPq@Y&$M9dPezxC|Hnj>DWIpSjvo+EDN zhmViGf%)O39EUUQ7&I#R?n5}C9PF=YFfsf^czbw%aRQBd@xL4HO9T=IG2l%63$!xh z;(^2|2=LH_oItlp{2xr<0HU{?y~XZ}ej4MGzj=J;KZys!AL zO-CLvg$emvq$knoZ;{UL51!c~9Rp)<4mJbt!9+6->xPYPOv2PHXfJm)H;>%E=}EN#6YdvC@x5C zgm{>MUW-c#1}~Esb`mZ{wBY5bO%R;qHiMu|%e%sZ#x21C$(VUQkdF57NqGYfHhvCbT{76R9WhNF#E{4DEacJnFEGf2MiTb)00gO>AO)H#xaya<2sLBO6Xd z&!sT1es{bX;c3=Rf2Nr9om=2y*f4%qTg<69#~}kwo8~-e?xQQQHpI9saO-@>v}toI z#k6UXeE>6_pM$g7oDU~vk`Ol;=NRH6-g-~( zq^BX`Y*>U6RC@_Hvx4LmzB^2=@ZBlodRRo?0Q}ZCW9N4&L_e`%)rl3xC01w>^E>Ei zcgGTlRem(Q{GL3Pk(dSM&Jz#9Vov>h{J`3M5Kpz0#|~`ORX-Ks#xNb0!tBRN2kQhO zTwyB*A*F(~yVeg$tDwU#-3Wpu#5{L`*?P__KYwNn|LROf!owI_fh1>L*!r;`kHLnV z;md;g%YwGp@o{Y22ppUZhFwhw^_j78eP(R+N#yUQF@5nr3X98v$b&T#(C9eV_h+W> z`_7MnN?6Wb%W7%%HvPhcoJ#N_z$HuYyRO-Aln(z|7)CUP)zmjS`6Gp#iQ`~R&UE;l zE_OZIropAb7P-pLl2{6hbL&>H&F_H4Wip7o4;C#!`0ZclR@m07u@1m9Ch92SHCVG_ zX?4_5)r~d^p~gh;KN}Xa0uK?|7$E^z-W#pqwH|Nc<>wFG@+M!Xiiy|KAolipsP-X~>J5gyyuL07&(#-ajnu_)IlpFZv$zjf6umV zhp(S*)stiC$Mlqu{D1duZe|ZX)B4}JuUov%`9b>X->={vYfQhxRx7C=lm->fdB&%A z?S%iavp!|s#KMcFP4sod&7lbT4%PMxXBGB^-tu|*ILPs*ATaX3PP^Td@4FP)9cae) zj2y=)5F^YqqDdFdh(Iwq(qB`FB6%||oG@|b%nN7CJU)VHMH!vV#G;Pfvbsc$gWmSU zvt~{_J~9S}bg;9J+IJq;z5UtH#GX(PfdcoGnNu#D8p+D+l-ar48BQPmke$W3NRFEU zXF@;d`%j$PesE_el$toWRv;-+>c)j%&aW`My zd;8XoEDT?sctz;Sgwo(5@2bFJH(L8-MEZwy)8qR{yps8Urjq)nqUuZsU@iEdK1E+b-e4P#%8^(bK>t@hP zDA1)$NXCXugdCr5$3}Sg4f**pKh}es3u}*o)5%Lh`RI_bVTF+6)7#plT6Y?U#L`;~ zw>^eQ@H=7}9WplTO33l)?TAZ{*N!dU4RG6Im_!NEdoj+#I;l?>pWZ&C$NI6IYs1>~ z?u47ibcCfDgv_?rIByJp05(3}@fZ)E&I4o^M*Ao%Mg*qG+gXEnJ*)sS4$U@L>!$oF z;_>EU4a-Nf1vb7ORdMZt_xe~p>cWkDV=| z^NdgLZ74u@f}b_6VSDVApLC5JbZNhu} zK|1L1w`V+a9;}QWA1Ix4bY5Nu+?$5ynlw7;;8B$Ey|yKZNbMA!DV`|y7js44W0=lZ zaf&!qyjUy|uMwAvH;K24e79kGyaveU#8<=};!cq-ZjAT2_?76Qt>~XBb`gzEE&TH( z8{JvR(}8Den9eLlAn~kMe@s%-CFA%v>F6FsmiMUYYa~Q*|?)MMvMZ}K*jQ?BlcjD8cnbU!A ztNZsy>caS3DvInOo*;5TQTpeK!^DvySHoiXc(JBV zH<$5bI9Ko_FBLBrIlqklOU2dV4dNZ*-QxYC+0zlnZI*2JCgNu!re}4$-;w-h(e6>S zSMnF)-$Wiu8xm8+y5iAd6OrGg7(Y|&F7_6GXs;rx`#o9lYwlHq*NpGod%^s^<5)b3 znmJSU_X^+8yL9tEiktsG^bI{Tt4Fsi6Z40^p-1>*h*z%82G!rt*K9~BODWGT4K8Um z_qKwDW%nQ0|EaUz$(~%0uwrc3?H<~b?cBU4$E&xp(ek=Wy|Sa0;c;uFI{SWI65Sp2$`iBq-BE&h$?3t09Ovk$oAvdm&+``a_4Wt7s#k98 z8^UVqX=UE39#suGMqpErHht3PCafBWz5Z(FEXt|BI&E2_9B;)I_}4CTj(7IWxYRY@ z(d(5btg3&*(&*Y~tI`csPFbB&cjfa3uDEMMRj_P8=@$54E%&m($_J_fn{O}OSQRLF z=D?!#?bx^B+ERDL^9QcJ3v1YyeOUVZfh*w(mc4kOG<`!=sAOYRX!Em(>7EeW9}Yf; z6di1P^UQ&()7|}H_qlBetBzP*`-UUS!#N3MsW}bSP2HFoO<32tDv;c@D)9R*Re_7$ z9xom!xoh)*E7L#SHgxw}-G=UdxyOLrr(_S@-LKC(^+RRhC3Pxlt*E^!bzR!(&|2@) zI)S0P_jGPm6>OKdJe(6Q4}Mz53wCW)73%GtggjQ%Sy>w`)v;`Km6LYDPH$CkO>#7= zDsV~!mO2h+@2tDJ(JFUOiCcHcQEQww&c16(8e*OMlQ*QS8@hXWc_ zj#Ys%Xz}yh9t{0*Tgtjule6X~@9CRdcTLXjegod9-y`ax6`NNDdOf_~t(CMgxvcKe zYqxDdeH)gitef2Ae+nK8x7nJoDq(*(fYiM*^yeG;qQ=eKW`PX!wkiH>#=Z4cjWvDy>Ydb4Nr(ZA8&!)5M2s)pl)7Jsv5JyZ0q&57ZtTKQI2XEq2Trg-}0>i=A z;F*wv*ui3VBam^;KyXh$AA#X-KaI7eY*J!=epz`JugDBIHk*b*_G(1g zTqYou`e&m^{|*W+HTMOu3NBje-zvCBOg(sC0IT4l&^mFUXy&wJcVvjlHg&80(H-cE z2KWwT81rldWf+pz!nd{!;LAKT6o}@=If5uRQJ36NOb4ICaoionbohxN1hHa<=Nuox zi8ZihZPvTt_$_P-HVMdVfyG)w&C>%FTXCK~gf&s<*bNK45#lrBKclFE4r-K{NObTG z4B9VO0ZU<%Op@~)CdikW2rPnGJbyLV(FCW8B4uI|EHqV$Do~!7$%6~w1V{nQ?qWK27y-%^bg-bYs1*1LYg8}jV9`vf)nyzWfu9<8Q+(rY zGL8F;J%Wx`VPlC?P}6TZsOkAI3ylJT;nYsbk5w}QUyjZ}F@#|4LJrPdC_PL!2MAEW ztBYA>)(0Jd@J|H%>8SGk37wOxi|P2gIVWR|M5e41)($2{!k&;d&TEm!6@V^Nvg{XlFI(qv;u!0W!&@m)bK?g^-AcQOED1e1l%T$0X z7Qjhd4Qn!`gQHRKXYn2~g_$0xpo25$p^+1;pyLH!2vyLr)fd7Qbg(|SbrBp-L1Pep zwa^%Jg#1QQRh%l-1r+QP#fuw{ok$fCdD#|e?|`0gT-#YY$78Trh37Z%y#eidtaEGKT8KHy9b*y5re zepSSlKhqRudWby7cNdX+M+Pl76F`Nn>O4*ds5*J4M7?_r*IdM ze$uD%r20u07Tt~V`%N)Dt|_L+HN|w(6g+vTM#!E-xQlq|{Q6Ie718$Hcoi~smcPMT zH8a~|P(ecwY_f zaE>>3OSb21SR>F;1dEPA_*c#Bq6#|L+VHmtoA|awZ^Q91EUpEDmBkgpq}c^{KLPyI zX8Eb@@cnJI5yd8qG;p{vUGblHRosdR{)XTtI+ko;uCUVy-oZTQBDaEfDy9PEPMa8` zo22lMcX8dHN5tKqN5tKq`O;#{H2mjH8MUytpK=J&;cSmU}91xmPFz%ihy@6)ch?mcyEC=wONAUwvmb zYuVpzqtLO*kMb(u{}!G~d}w@!5g)@E^+P)R-@9Rc-F+QfzuiX={H@37ejx5g|Fj*d zt?{oui>Ez<)R?L9x9PnN$NR8oO@iG6Cnkr?H7z!h7;Und-M=msRh7o=r zn(kKc8odJ+y@lZAi7dY=qT@y5KZ1DG_(QRA2OJy)N2HQsI?St_GmP+W-AI%d^<%I| zlwe&e>(gc4&TeXzX!<9X4XJiFq}~kthiaUi4&mQmo;{w-j~- z>>Akhus6Zp1IwSYO|Xx_T63tlw;=pB*gIf1!#)RV%@@eLiUmNPDXPFT*ksn;OVxDQu1u5Z*Y>qc5O58p@y z&G6jNf{>S7=q0aX{NzdAv|KMO*SjzR1CnDIuV&u$#Sw20 zdg;7K%VSzz(hBka8NVJuzTq-A)imlDnxgmsHAE6&X_ zTB;Wn8tu}u;@-Wu1oJa)ZgVP`1`-|DtyVdtJ|OI&v`jO*Lho?qp|wmiyExM`yCD3h zu7W&nT%X|sGQX|ITCHb_tp59#O8$|`riZIvYOcS7v`VYb{6XH|Qa1HZzEw6IH*R?U z{Qtj7re~jjUcae@LppuWTFT$6ZHhI!p)NgPLMFbn{#WRo@+amHdZ+%P$UlSLDXzQ! z_{EX`o%BxQ9|`P(%PDwNhYV+B8DV0ha+2w`CP zTY9J0V|3cHi6GoMr^LD8bXMWu%Q5(Cjg7|-9P#-ETi|gDI#A4)`LQ14Tv&SyoX)Wg z94A7Dj14P<9G~7TxEj;o$Mi4;8%u97-1ZnaofD8=867e<>`KV-={qOT_KV&r zz8=`-H2g7or@Uu;hu*3AY5y+0Q{21p7L9X;i<8#@^%i-q$senC+E2&ji5#|MI%kVh z#Hr$cn%?PLbZ+X;%oj^YTs+IfRV3FT6|u7S$s|0F1{=77e5!j68Qte`Xq|UVmEbMLzE~nI60Z?gh#b9Rx;Kiqisrh7|9z4l79SO< zPr~D#6U}uD`F|yw>lyM6$-Bh8B8Rzn{NF@#eMA1PwT`Kz!T7C3bDcxZl5E#FK0)$8 zaj)Ngg0l>xJo$7S9qV zirgBO;oK9Jyhyx6Tqtr6T!vF^hFmM&B3k{|jgtRId`x^ov}+u54ja>XO?*pySNuS% z6h9IFDt;|m{nsR<#q{cn4aJDqLi`~;*nWyPK+F?Ih&Ach$rX}s7Vi@86(1CTD?TAUBmO~rS$s=;NBmIS zEq)??A^u&&fT`bp;*nx2v5nYO>?u-njP*ZNoFtwr&KBp1SBO`ME5tP-HP4vdgW@yd z3*u|yTOu{n82=0L88RJ>ZWYaXwae3N*a zXxBWxU-ECo$Hb?_=f#)B*Tn7OyW&UU$70R3k2%1@_6myBb)?)-Y$7%n+ln2;nrk8V zlm7s5h&WuN?j+NnEKU_?i1WlE@p5sIxKvyr+BJ}Gl6kwl-$lMtv0lky9q~xfu8Ev3xwUB5K<+8ou7TWNGSx$w?kI7b zI6>)k^Xq#%^Q& z@yvUC?a@Msed+WUO8gU@MoB&pOw5IVRS(_p3^<@0Z{7rh!FeW^;C^_9+~5Un1jS68 z1IbCOgtM57uscPG6Y&3%#4PyFPvpDG#fcBYXPy)0i%f8q`!S?&3I1VyMZUw=3bw=1 zNnBHr8al~lO~thc2&6kHOOZ_QQmNMmQeLOHAhkQn|Lz}n zgxi2$a?2KiR8&Ozn}Oy6$i{4R?h=3*4JdgeOkbk&azr5LwF~H--c* zbBNOuj9cU|@i@e7oQg)*LD17iDeQuXN%0FJCLg>YV#>h_BBsVKh&Zr*UALZ_9a`Bp zh1%V<4_*?n&cRC}rb+i(OCr`?w7^9bGjUwKtI!&Oq$PdPdFuP=w@w*YzjI3O6tqTy z!?GF^#DA(NlG(nScespzCG+(^-J5BZVY z`A^@>Jhr&Rl&Mn+fAW%N+t5te(JZevv{!P|)5l~sZ;2htF(mD})oYGnfu(VS`;0hw z+@StL1_1qs4<9-lYmz~4#O#}V$cFB4h^50~1;$>-g|lWlv4rynj_yBh@W6cJ((mN& zS-;GD;Xg=m;Sd{Z$5I{9KYzryXrFME|ih%VLS-kL=g4e}4WU)-C%dZN>dv z>LcITkxifac2^!UVC0}axVQf2sF|2=EAi`_#qQR)mGW-ew|1k2q01Al2wv%x2B=^8 zWAsb7!#0*#E6n)rhWt-gG{I+c{^Xc%uE4)+4{kmw*UUGY1(317q3s~!wLE50>f$jA z64VyV?=0g{=2HjLv!)P^LH^IN@v>ojw~9}%0n&Q|flLoifF@0*Hy+j=1E-1ZnaoqBk0jnE-u!}v`vKD|K= z{O^lQkFQ=fz2$J*W8ieMkX{-cGB&IXa(sGY79@C?0Kt$Fq__eaPt`U2byx6glx2-H4LMDRJ8HlM&i?LB!w~FGq5;(nhhF^r`|*9 zqr9bKY&`BGWz(h~%SXd+n(_50jB6J-WA#8cV!ko+5YpQjld9W{WsK{VPAM8A8=ia$ zMVBz?rGd;dKE3DQnFBv-n9iY0y#LR!4%)E?Wnx>!_w-_S4J-2uR~zr3mScVVK>-`X zbJ(-0jc0cLj+g5?5r}LL->}82jb~Qwh?m)d)rR^i=@8i_*|5|{IRUiBr2Cz>cIbb9 zhmwkYes%PC!nd0wyhZW;@pI^{^k+I~nq2WTajZB+{#3jQoigYefV!+(eTKal(v$(*dg@V`s;a6wW|C2@Q`68UzNKdNhF z_I~=~z1fichjK)0A+{Aeh~}jc@p?+`BlZ_Zh@-@D;so(L@j~$;@e+~4C@e>rXwExi zGsFYlD*rphhr~_dlOjh(n9erwf5rDj(+?27Px5CXM`n1O=?7q%WYZ5IbEt;l$B7-q z&Z4<)68-C(@n}ff-aQqMS3mbQ=e?5Q9kP04`XiM7sO0~@@k=K*emVS~I)3RzSarMJ zN8C`R=`w-D+ZY^7_-W&pX3)}K_)nTPyL0=Q z)7qbt*_A%$UwBqwdn~7aLcv)x&WW_2e9oM+W=v|I6=^@TQ>6W*sTa1NSvX_L1VlN1 z%2_j~Oq~qRNwcO-D8!=t?PpFjoC&{k&MG`BUY<0q{e%mr7S1?pLg5J)PMTz25d6`~ zf9?3?!PDTX$3Ho3^6c2w3jRJ2&IB|=_4)aCAHPIjVo&>aSN>)Eve3z3pL8 z1owU8m;VJ5<&MD*BA?&*4nfn|N9;dd;f!g9|BPqHRBFa!7)@(fj$-^!ypD)dGv93Z zS;Kc1ns%^wrHq+h#xMP*;Ja&lyZkbK>G!8+&@SkE(`<+NW&F~%1lz@4rM{nsN8xzm z#jaW#9(0b4k6=a=sy+Uj$1lHclAS+(iJSjFY5cMunwaBhdE(*DyIY|6i^N~XFVT*; zN&Yf^iFUwv-<|9i;D6EhWv3qg(53nR!{e77HQf2b`j_+lPc1*I{$&u?SaT5>X9uuLK}Ed$6dxHOex z=BaK3NkG$*rKHI=|KY_i6-LvNjtG3~FcWt$2Pf@FuU|ARf6=r= zA9sGywCp){+KdY)&p7LX$fPOfPn;P!Zf^Ik$B&&nbylR%Y$J(LjfmY3axAuuG@C|F z?=%+v?WbNibz*z&06BJw1||=8q;gWHte>=&*-y~4Jj8$?G$~Oa=i7rf@#Bz(TAS;z zMj(F~W5mj4{~8_1nRbb-!x>vNC-h)-O*_i?W5%%kuKex&VE;epRjLCYqK9k9o4q{N z9rFkNGB)|6#wOW%zvxz)2dLPn$3J^)@}o3=?6V=V<@hBn$3poei3hxxDTJ#lo&~M3 zVSL|@AJf~1^qxZ?)8qK8O>aEh_82(LvaW}tTlp{^i4RA&@*${!jaR-bkInbe8u@;O zfC&7ov1O_`Hrc3wubaYp@U_aOw;XPJ4AW?gcT-e3W^7m)eB#^XxVZE%OcG0v&))VJ zCejY+9gc2gccjPj#PUHsCYB!cyqI1`Seh$v61b*?H4LMDRJ8FPLSd)dND5=TXJB#o zG#hk0bQ}*yxAGjsvuX2KwjWJR-OB8^c7ZcikGgQj728>k^mZ}<8J3NPjO&)pIcSV* zcs7DRH3OM%8Z6I6e0sOQGY5Xw*z~My8Snp#Zsk9$Tj~FZf1hq8Z~p(JvB~~8nH-zU z6;Bh*=mh*HNM3&H4Cg10E%J@S7<+$?|2 zrDS}whbPj1Q}R0s|48y)$zMvgYZx7k3zOxiVL5m$k|`puOUe9-Td zh1gy{qb_CF?muEIGBdMVH%tkK`Qfq19Y^8hVHmEnLG_-8f7sBjtlbUSrS0Z+Typ<` z&#>QNNuPTQqGfK6QQ@ftT~;LSxzxRRPqsIptkcrAOFAs$ZggpvMpsAIW|l1q9}!J* zkIeC~b6fuvU6-AF&zNYq%OlZeb~%eWFX^_l{q?6tn?}!Z+OF=nCOta5Dwx~{mixMG zuiCJ_?W#3ZPNd`NrB2q;(K)v`8B05_iR3iPXa?o6EN#X1U1@i{iHj39t(;=sgFR;gYtBzk2 zT(-I4D-AWo3RTCcjPl z-IUr(>nt0(d-uilqp4*H`_mGF`_qCcYl=TBy0_cv?NtwL?tcUF#tw{W8?Vk;oYS@3 zY1eKmYCCyL)g2q!tV>@ubf1&7EV`wtbp5GS!M1JCX3Zy$tP1uTTNPZK7d<_SvQB>T zK)`)C8jiZXPmB)T{qFRkyLZkxB^rpnvu(?+o|Cui>W;c0#a$=f)t-577>?Z~-CZe8 z=Gv?^;Y_#JvYhryGM5Fmw!5L-+~l2|Ru8~#iksbW(N0S`nEe#*E{S44#aB1qioFyQ zj>b-kp+R@Pnv;7+@cPh-6QbL8IVf#+oR{p)TX#9A%jV7PRt4v_U7a31`=H*^c6D&g zEe?9dl3Q}vGj1>0vMXtFm(^RUI&MBL8oqvc6txWp3bs_0m8^~?gR4q%qJyKTU;nnz zmN?%nCig8kr2z8e)+@K~YIWCwg2e^(Rzkk(_XSTNe%^*HD9saSg*|hQSUHYI-sP@? zANROi|3yQdk#^DgD~9g=U{(~dc3PK>^V^mfjv+?M+J!i#^u z%Rx_c?&=h6x2n_Xz}zuT!kz^Q9oFEw>E-rByDlyMZ0fxoqS5kp>n1kYP;gJU{??vR z54#*TC}=!>M8Vkc%L~fKzgqD2c(+Gje_FuXpXTk~*2!&@(=_J@T%`$HPeX6WhUHZ_ zM7t~2k9JwrE_%n#`cd|*E;qdXq4T&|-_6`Bg6=ZV<&Vha@lSRp5I4YJ;={ZTx*?;T z%;&^F4bXJg;jWoqOop=WIHEN8i4Mbiz8`;4APSWj5<) zy5Yel$>62TCKznVuyF7dcqZ^i4{JAU0uuP~ujampMX`MmOJe&XPQig#$6+Ir!M=!G zQ!lt6wl89o;$_wQBFNxgbq!FIGjfs@k)w(mvYDO*o_d)4vb@&O9KR??ql3DD4t01^O*QBM1Oz9 zGg-n6JS;)P_KHTl4Nf;+K~=XmJU< z9if(wu-g$zOg(sU3A-JkLQx}hCRn?81X`Hx2+0nGJp$iAGgTWt^kL-$BF8vK5+M_H z$s0vZi68{AVuo*ZST%y+L?~?G@=*~T?44LTf>>z$XUwnQl!oQ7CK4Ux zu&y(fSZ|!eiMwI39pLk zmL7@{GklkZ9y!4{2X6&Np;(eWLaN?MQmcLi83QtL5IJ6(2TIzR_+ZyB&C9mKl?(O*}bn40-BuQlF~?t z_zKo@=FG34gWU!GwmncD+Zre^>S0U^{685Mds`8#Dt0_XUrP@fH_|{|zl!gBU&Z&m zuVQ^K3x`q-AAOHd-+R^cz1hA$aRsb7Pi#H*GbI0N5goh*;$Y%e#vdn>jrN486e7{# zH(MU-&5FgXGs072-qx^B75NY>k|WGZno~HR6WsW*77a(VfkkDv7GdK`UWmNuvQ2@m zNS}MlkvxO&o((K8&M^e{(897U^O37D%>EptA8;-*^ow%QH0F7vNjRTio&jgpeCGF| z?@jpmO*f31O!5h4jeXkYGw)L4J(}?Io)*jd0i?jbhEvQVW|){G2p))?|K?X*4Tpc_ zj)?0JD!b|3EIjrOBUpCqDK@Qw4mKYA3DyO9*k<%lj|w(quAlc1z`q_$&u5*?hJtit z`$Ad;9V{eH4Z#B9BoZtlHdOS>%H6%)?`Nqm#u|AFaCPI6Gb#;4gTK)i{4H6MITM@VTHc~z5xv4|u}} z*hGwuB-8~>K(H5}pSczGL?KC5GsBc=EWxv4(&0Hd-v~=KUqZ)1SX7l@??zQ!a~Ef` zBOMgSm@NF~Jqg`{;Qa&lj*p9~Z^NdJJj(c+gYd5fY&%%A0l{NaIhW|m;|rZHk3Z&1 zC)Nk}B7UMDliAqpI7*6m4!|lLq8rudH!Zw%iHHIgLr-Gf7EvW%A1>m+tCQy84;UZk*Y{Yd210J`;34shv{Ik zaNf*K-rTHIh^?__gScNqTX7_{qll%r8%N`gNBE_f<(J|y-=C%M>phlL^>2P-ZS71d zNW_@N_>U+s=qxhqs_`aXejAbhZ!Uv1>8zPQeHpB+4mO&r6=~Ycn-c-MdebsmgDt!Z zBG`egQ+w~ch-dbgyBsf>?hyVP)YVJ6+nZgM?#<2h>R=B!#%MMXd$@Upkz+X_ZFZzR z1Eyz8Zr_0$%@vw$=ddYVN~Bk_i4{#d^zu?8+(2$%ho;S%c4*pxd)&>$v2`+fqN#G9Jo)f(m1 zD)i>yKN=%8|bl-dV5oQd-V`6*PF^oJl4K z+vhDvKQ{eX?@pBEEtKiD7$e?JCzrd}jphb*UhT3Iv5(!d;!&-=%Zqzw2DliR-J(vr zfMsFzF}r11^*Us}zRUDZnb6*dty^U#W%-9Who$^tcDyq?&V9F50`hSFtEb!@#(s3) zY8`teI{tLHezRs^l3eUOaK>D|#b_DoLi+6iaQt|}MPj5$oz7Mne^w5s#@?s<9_ z&MNF1o51&NU6{DZhW}!hesyo)x9i8OCwAz$ zc=q)FqVJ*x$HRs(t??g&YIxxB4If+Mjg99&^zt3oH;mUf?vcYfIX-KTVaz-P?C_se zD8|AD!Oh`1Ytouxb8^Hx5*`>#G!Hf`*I3y2^g3d+a4Y<*v0?rzl=TI1aB5PuY~!5^ zulRiDHbWUx{Ct@o>p@aK#U2BvlUmPlB6P^uFs>65pWbsA$4!GD>%r`8dS!6iW8ie! zBR$5m#)e%DkNEW7h)WN}jHP!I-1ZozaRSmiR6DOjSbTaPAwAZQ<*N;A%jdtkRqK!( zdxXEY3!)gqylA<&2iXypreUK)>#;n6F!ZTuCKCRYBHp3&SYAU|d_A5*yzcfOkmaL! z88*Hi`{LTAKEiB0_^vrmfJ*(Pyrf0;&-*Xk(@715T}WANOX^b z_TNIMUP6D+%+*0U>m}c+|L5f>ZfBgAx( z%m1)mX5JIRyGib&aE=4=xP1AaA^B{{=Sw!9ACb<*l1mhRmE=|84f4NTGCxN!{|6;= z{tokdRYdcf_T&A9?Z_*It+(#M{Js#rwtIijRp;i_eR^@3Q>7Pm>>ryTpCsXW{|z8!^oDkK058f{M zE|H&B8U8!*Iq^mD74da(hxoo|t^*uz*2M$AkpJIAm;DU>31V%Llg;RVl*ox>lv{}A zx`CW2xr=zB$bn48KSdlWjuOX;6U52lRB?uAt|z2ZEcpu2Tvzbt)I{cUy~r;vl`TT<8)=R!yu#4X}B@eT29(e6jLOY%PP zGx318(dx$59HTR_(CjXJ*SaG~~o@n={n=N^sc$sMTr@L12Qjw}JtjDe5-QouE zH{v5=&3)-!lK(5>+u{y!r?^M_Oso>W5xqpe97$qrv7va3*g`x`>>zd$dyCm3b$M97 zd~vjRrZ`zVPn;pn7ODKh;}?rd#T6p8ff)Wj;wEvk_`JA9wENk;Bl!bym-s{b+)>|% z`85)ois@oo(e7_Yg(SxBE9Qzr#F66Z;&|~K@jUTDagKPgxKOnF+g&GlnYcz=C*CUF zDN;j<<+JMxLtf#+$~m$HTSvWvoX^TiK${;@o2G$NEI!{&k}oxCx|(s z-S2Lg{v;##p`w#mB`b#TUdsh_8!(6#p!K zDDD;ai&f%RA}-JG-50H=o(mf=9_H5A_Y17U+oM~g+Qine$U5{sVwqW;yLUIye^_^X z-_ghnkD#3ms&&VgZU~iy%Ck%Blm(WoFK9ORoPy-#b;`Z6`w#5@G`Qc%9veYC z>UIzA$#&ebv{lq3uWNM3A1|r1Cb_)Ms-@vqoTR0-)}$_Loa5~CoM2Yk+SP1tdP9%A?w;r3p>B@1r1t6~a#Ge#*yydxtO~U4S{3+xm#Vssg7(V5#rBaA&R6Y0%LwaceE9Yc#YMl+=N~a=Z1=axS?YTH4Rn zdLajT+9_MA8bIs5G5o`2+pAL6hsvRYzj=8yjJB+`Kj^IP-~I8D{>|p%d^C5PoAc2; zu+I%7N2#B^qGaIiaG(rlWQjQ={@FOa%F8<$w#=N7FW$JiueY@a&ct!B1D(>GMLA9f z2j?((?eJ*#sMD-*DcXC(8KtM9MT2$Gwi}k09(f?4?)K8xN*f$VZs2xj8^Wg#+jQr) zgjI=a@^XS}du?Q$J5~k8xV?_Rkza1BwJKEpeEsyf?x%HJw8b&h=1$tvFR519ifvm^ zyE>~wJ#Cv>NKq5CWVjTz*Vm=c^3)7>tN>26J6U!!sPB1q-!KE}mipOh*b6go^kpbr z`!b)jQXl2;Jo`kSDZGIiw0XHb3OX-ByKMqE#W6XjRB1)=9=HLG@g2b7&U=M+g>3Pj*L! z=v$8tRKC@rw<|;t?mE84Ij;ifrG3OEj~Nb)LVb+j*ClB45ht6dOEwhKk?S9~p_mRo z5riOC%<#Df`g_DpuuywiU;F?Zn_*L+jhop59--#xfr?e=5I4b^D0EPZ4EYmxSbsXG za0O*I;z8p-qo{%o4#k;+>FCH_<(wV`hQKD7tS)kx5id&)Qz4ke9s&y|G2A$Z6O&+} z)?QSBa>h&!T*#R?2Ns!aDyE|h8A6Zjj$$YaSFq?TPRwI71mm1N-VIt%aEH?C;Hx!4`!*u7NkjU-+Om zu&PkZwKX<}vbG$2Lr)+Uz(RX9P(jBPz7VXS<0@YWRnW2A7s3^EurbgssHHJ%iMZ+q z>E?NW7H^L2)VMHmSRx)ufB#5-sobs*P#WSUSd_B7W|uCn?$YYI<;8StfW@JN->}mT z>bm8{Y)!xGjykyO&NW^4DYUTP*rQ%kV?zUxP0fPC$ubWy&QZjv#+gU>9UA#nH|R)P zs}V?xA7Ie-{I0?=UtV~?uVA5fT~tBGJ-+{Vq{dT(*fs%vHAq9zp`IJ4prg4j1S{z1 z=nJ6=Iy(D8xPp$8VR3gD0i5YOiD|G%si=Yu{#GCgi#N>_2IroRdA<;=pkskAgevGL z^@VT+9jp(|J+a<6&7>8-TIhgu_zgPT)}=~y3E)RR4VkkBa0hHn;104Py?y@>nd`fY z&IV@~_w1qqB+Y^{9a~_gW6R5QSllu{PKaFLyNgJ_c9+%#9lO9hQrW}Mwo;tXTNTvFGu1pvZphXU5fjW?b!On%eUmp;#e%u2{tNu`17q714H4sv@&5u;tJ#h^vir z1aY75YkO$C-tyb1qxran1jr_)%p(YXtAe60(cL&tCuSSx2=;VdGT)aLy9O>8+e4rn z&kmApd`}~a{0QHdmbuxnAxFa+fev;kv@F4k!EB_@fMu|;Nd9BB;i$gN=U+d}AOJRB8a#T*35aJgVjWXG(zDz!Xk>j)!L)0@2#h1pwwBg30Tzvb1CTL zj~R|9vSCfSbg+otEHVPfQ2_p)d)BjC7mAK0I4kOB7&2$br{NF8VFc{Mr z|M^>mmK#O#ml`MK0rQi+-c)KB!TK40Iv(=|cHXcfljY1j|!T+AHNP%F>XbQ*l8dEsf9bYtg#oClT4?ZwK z^Pm6N?AGutg%|Gv*ehVI*?@z1vv~maAwK~dbkOnUv+MuK4Xb_So}akk%Tobp>Ze4S zdb2W`LED|G?sYP}Y1Dl0l-0(&Faj<7p@YIVQn@{RMQB0DOP=H#UxT%l;cAkh2>Q-E_r>q1_=LT~0IFD;VZIh`u>DH)kQ zj5IOBYth>qo9i{nKt(bUD{rYj^hWF3^j@@j&Rq!cOwJ;<1BKjBU&}-61Cudr}3nxyRG}B>&m}M|c zgHgxdIMnVlr%awY@tla6`0*dCOrL_EkMGi@=MT~$b?FOm(9fky|I5BMu^({zJKq{U z7~aHFi*NV<7H@34cJQQ|BWg5^7yl4pA1(6WZ;xTTtw?yXO*}4a5Zo9>jhRTqf2!v2 z8wci@9?Qk&=lJxxVdVB3_*rAarozLz8P*jCAAzA#Yi!uL@QBZMM{_*bL6?&GGC!Ly zbr$V0a5|@8urWf1j18-)OP|*fqXdY<^e_w@ORo%Wdkmb;c}Opt4jCJEHRSm6jYoQU z@MC(ser)+}g4-Sgr*jw5n;oFbH#Te?#Q5|!AU)QT>G9i&P46DKc?^P$X@&@iHO?Eu zYwFS;ca(F;H6fosTpT{lPt9>wBVG?HfVO$D&lpgLx$y};m~({Jsv_q)8NN? zpz5)Da6~<>*iOpPho?)wp@~0+^FzAyJDUEYOYgTh8d~PZ=+g6^@qN1V-?u-F{mEyx zybt}Hy7akB5BGu7MBaBOPZ4>4p?tAeB3>gd7ysRK>F44?qpk>F^2ibr7t%73FW9Wt z&5}8iK>2>je5s~vbm(#1bCQh?G2}NSzo+;gN&ZxF0QV&3S67UP9Ymx1i|~GwkqN`9=6t$wlI|;xZE9>m=VSnd7-kZA_sgJ|9tTx@e+{(B@Dkx zG;>oRUoUx`$YDpuv%2|ajtXRRU4fev{=B$Fd`JAVxJ%qC^5Z+x_0%tu#Myj7MF`0C}TPmqPcD%bC8Vw z=K2MHBl!{W3Go^6CGi!}T+cXehvZ%2Uhxa@Zz7c!m|v=Rlz6PzQaoPF6uXF2cHr^m zItTM4j}Xrg`Kg}qW{Pvf5|N9*FnqCiow!Qm?q*l3x;kNay|&#rs11T69q-*6W9K?x_#M zcwFn9>?~Sc`)tWM;vg|k93_qw&k+m6X=0&hb?r+emx@=5%f(gVdhr(VZgGS78}Sj5 z3O%gHOXBO|AI0~?o#J1_PsIb`H)2hlduj+VeXDEVT5?;llh{o>N$e+{A`TT#6UT^W zi<88u;tbL1+80UYn))oyRif3kUms zeDN~T>fTd>i|MZwZxQbhf2a{5u1u_#SUUuv8UKy94O|ABg8Yrv%~`N zd~v2YM=TK+ii^eTM5~LxM)Hl~t>QhR)y=1lAnW_IxJBG1z9qgRejx4=KM}tWzZP8# zDly$8v9?GZMEa+TZNv<*i`YZ#D@Mg3;&AbF@eFa2c&<2IoF&c|OTUa6ZV(n+z@tq-@NB?uh#XUJqweQm*Mqt-{&PuqTw~c^6(8? zpyR$YT;EMt+Bhc=P1xrp)LNCeJam1aY;DwCvJ_wC>qm!G1y8}6-A0GsD|c>Kj=2c# zs-e3}!%Lkba?)}_d%}qcYng2vXnjHBx>Q0xb#nZ?;Ra1KO(xJa^mQHl@oKp z+>X#EKO3u&FW>8&TejEv?Y6znua?5T0{5$XUHG|cw(WJVS_=CL+{^a{=55^@XtQK* zpy$i5%k~D6Uft`#&r4de*E{-U*kyaYHmxd?e>&D+d{U+YS*XLtBdu1xPayYkj^TUR>s zW>hY0)2XsW&(@Xe5%1F6nU$CK>{i)oUhB#m5pTgf_XMtp-?_4RE>~eMth_9jE3$W~ zOdrj4&*xNLIht#qFW#28=FFUNIdA7A?MZe+YyY_MlaJkb4}R>P`z7oqxc7hTB9AN1 zom_bv^1X82d9)4rYvq;>LgY&<+adb8QkBUx+CPi63x7QB*|LeA)yRS}pFXybBKkYqXp3}Zy zYjAB=^tkBDd!3#*Te&aqbhi&Mmy%5wy{@qAKK$SaM-oMGc;q?Xew`O70`5xc9>U=M(I^RUA&T|g}yXt((hDSdRFMjl+eRZY{ z2(IZEeSGJi_9l!Du8HrZ!=lISbROpghdDkDUK?S8?gNxLNOQXHL*JOeynx5~p6-UI zL*d~zQ9YNz3^WE3Ix(O>{srth^yQ2dOyCQ#_W+OXUTA#mwzpktt~mU2+@5Qi!R{&t1mQJ1Md> z?sAHq5s=Ek68CzF#SqP0gcX$PBX=_u!AN{XPvyA3yOQV`};8_%3h>3g-N#)>(AIjyW%;=*p@>kx> zy10>t^0&73Tx4UURQz(*o{LQ)K()*qIgBWPg$CR5 zVmi+E{Rxh?LWORAMG)tMy~;$QV+1VJ+lW!dIh-hjH4E5R{y+BK1U`x?U;D4_>g)|9 z0hFC)6%Zm}$3bNYEvtk@c4Z9&Weq_AkszXiq7xQ{gg~P*E{KYVj-$*gD(=gGI&L#K zt|-A#a2e6e==(gUp3^BJT)p?s%>Q%m`>#(`X7dF9J`uyMt?dH3u$x$vd&0HZg5rr|KaT0UnO9e{$Iav1_1-Zn#FeWH1UbPw( zUbV){hrbDQLsemc>`;uB(VmbTqovRj!ZBJn1`)y1W3=pq!EjmP5n~-jl*5>|OiQLo z%&=O(X`Ypty$uFKRzopb_$3)avKa@z%M-#eTK0NEdW;rk4ULU>-B^baUJh}AROT=~ zh~Ab5vG`VvY=Bugybn;A55}v=*|LW>DV}?fbnlHOgH3*YwnYyJ$r~`xxhV{ zWLZE@uSY=h(*as1`I&LQY@y9P2jtt#a}d5SJp-5?W)pe_@@FvCB=j#K-}CGX{po7p zopTV$w4s?B_VC;XlU{lYO?tE8!4lHTUqL*7ymVW^U|I>$)3kle7@~!B zg*)|5|CL%f@oOrA^YX-9gD8M8qoiqJgGXB$h7*o}ft45wV}j69;JH^`hNFTw9q&uH zH50YW+2<9-Xz^}OLy1-}TJ)aQHZagnbb>MZY4L7R!;uhkl;Z!RFi0)ojn%)9;15;U z$RH47)7otW3|Xe-9T=!4ylW0amTj9yd9hk{n_T1){DBqsfK`>B24De2jNo=r`!{Ee(_n5;j0F@c^C#Z5J z+bvMyHIk7m_C2PgM-pC1xP^M$*v%@eGMXO2n*qo`o7Q80?|6krP!TD(W|s7eKV z>!_k&JQeIS3dR$jf+cSZ_Khpfz>J;}SnI*bgH8#$Fq-(0Dt3P>@XOEK7)&D=EYpxf60C|gN zKcAGY0sk3YZN2ydyMd!+C%wC7@nDkIC-Qp%sdEfG)j9T}5U2}tmV8fTy*z$*tkhTF(^ufrSK!yzhx*urg3gj9q^EDmN%YP4=_?-Y%X3fW znGFhg&Y?cGC~g5mdiv(Y^)*0#(HwA?2e7g6;`bkZ`EJv8T2W)5qIxxqA~zG{AqP&n zB)2o=?D2C8=1eb`G%GS~#>~9=kyZ=4b!k0*`s@Xf!Z~wh&W~U;aU^fndy`2U}ImRmjREVy{=mF4#6 zF>v5Ox7Pr-W5lgJP3ocIEbLK$ITf;O#5{xLfr$IV(k%Dt09-jG;i{qmOs{)G;G^Vb zw2kM#_Wak#*v27$X2Sq1`)~g8@E4v||0m9NFaf;X0kSY{Bin2V@FoTaaf^UY zoQRp~FbK)=_5^U>!rR7^OQ)UT9zoKe92+dO1MxvQ5Ws@z9etYu*dg;~;=xH<>shC$ zb#D`a_(=2F{?X*8+(zIhy5hs+xe2qky8H=4`py0V|EuRh{G>=&5~rLXaYEsoVj6_0 z88htPKM^9nO+aNVP6(JBU)$dc?3n2Q|K14;o&M_+70{eJIL`Tf`kWnU#bz?X+&`zy zDTwqMHaOB(_s~dg!JH|1^XJbgnBO{r`)O7ub4P98wL|AftAf0ld6VYnwT_HKl(Xz@ zw_T?R-P%nqm^6DzexxApvKjMd%$XhOkliu6Q`d`}Ufu94n8cefZt<`t^qEtD)%M#B z?&Ks^OB$RKOij!T)e6)OobJ{M)D6@N)OQ;M8evj!7=itB75HLq4?a>(GFPE@^_~g2 z=?TNCCyWRuj7;rSov-TujJXSFW?9I4*3`Vo3#Lz)F?-q^NA^jRCnL*#Uo;ZGI0@x4 zJ#W6>>8CC;`Am|=`Go~e)|5H3X62#DWuct2CKVPI%$U5O@I)=s@J!^_&0l)dM?gG& z@Z#$o{_>=YdCY)KU>FWXY>uko=*Qy>m}Hor3)dE5s-D;1C9oZbfeHthgX66dta7;6 z^PUeoKB>l!w;DUnG9>;qxZrEBd1x|S>}cCKusWNO@i%GFVf|)6wsv|I;=}O0{MM?& z`mwD2=N;V?ee3Gpd3iqOgJj>x#(~vog2C|-T69>yLdbr7`R%>mMwt(O=d}86fZfJ{ z)#(L&>9pvue%C?v>%+=ECLHzgTC(~!!*1ii>I{Xxdu`?W{7PW=>stwZ%pdh3+i`t& z!%lthHpdUOy%&Co#*hBHVf^7Nl?$>S&qoIAzUJoagT8mAi?C%z`ije$ig^n?;mF@FtiE*Ec}~B+ZD^+* z;bsr3&&rm5_kYG704QeP5psARm>5r(EhR6AYp$Tm;Qxv}0eF6vk9V-dDvw_>j{(JP z>Vo%>Q_N%N*x^6e4gmLZa}VTLa9$TdG-lR4iKc6as&|6$Y(e7J8s5X`&-x?zOe6b> zgT$fY#Uk$+40nlmxwurkMqDG7iFb;;W*Gl5@k#M{aliOS@gHIsjfnB;i)V`6#HwSl z&!;T&1bJOh<~2*2*K4qa zurju0;rCyAGcvqgTVM=8R;&wh!=h(X@BSO(nM!&k{R|XN%{Gru`!xmcBFk zhKVD^3E~v-5^=V;K(uodR!Uwit`j$i=6b;S%qReGx7_);h50dK7Qm+@za;J#-xd#w zheUqwV|+9B2mDs@4`Pt*5ANnV0;@?j*AwJ=lFc9m$mY5N&GiI!lYdV!N6ZyRh!=_G z`a--*B+nMjbq4pVC0{R^>kjU>NG=s`6@Me%C-O%J=I2rI|Ag(L#!h<5IF*b;m;C(C7vgqFAfxki=)H|;uMi%NKCnjRp%=FTJGz_s&f_Yl>0qm z)wv3f%l#?wMbXYxcvJG9#1F+!#4p6J#0v38k)vLi{+eQav9WlDX!ix^D7mY6p4dnH zx%~mADBN^$jyPYuLM#&Pz5q8!UMFr4W8&@NJ>vah)wv2!$^BXJ58`X0owM*4$zOR-LPGjoep>Rp%=3 z-IeLPRs6aA0rn}}b0UXAG5(*#55z;_U&UkM_u>y?65fd!-_BXclx*iLG?v^qR?fAtu?*S=b@j?i=ts$$Q0p zA_t36-`nDQ;z#1QVui@jWDH+VY$CQ0v&0T!ckvuCD%yPl?3@IkpBzfE8-u;w?z(+qrT6?uf%V~A4I-`FyR_FA}d2SBY!Ho5juIt>WF{ zy&}i_QJ}cuf3G{D;Vq zlBRsbx?)4Ih1gom7CVdQh`q%A;$V?uFR6c$I76HzE)W-qSBck%H;QY-5^=ML+bo6w zSHAy2H0Q(P->|d#@3ko7CDFbgp4G8^=l1`Zxec8=b?aop|NQxWvnN0tW@Zmw1q-duBS=-9HJf$TuHl={;e)m@WtWSP_8 zmJ9YDJU(byX4%$bp>W^~r>WBntKSEb_K!Fox-|EAXk4KC(-n!$zQySFR~HW`?~__> zQ$ope$Fad$*I4g~(Um!^_fII_km4Mjusm~PaKohNpeS`Dr6m z|3JG{YA4zd`ARWK|q~_)ZWr2#&g*9)kw#ChI zzFfJiZfsA~IjiITY9$VKd)RSRuyun{=jflVaxiz|p{p`C)y0_oT3f>ojzZ zgp+EPHHF7M)ODmU8a?a7l1OH(wqvFnQ{me_j4F z(0HTr{L?%JV@z2}-6Z62RZas_!Yth}oF~$KAL4o?oKVU#=8gv}4m8!? z0|$?{FUDRADBpvh+&8f9=G!Y0h7C(@xYjuuxvJWhgc8Emv6`a2)iOUS8HeA=4yb=f)Lt~EDiZmNHCy*1T01dGS#V^4%}?z$U4ZI9P;r&-&m z8#{PBcUgFgvpGFlH@Y^uDf$NHJG_Z9e5oRIPa$#~4j{$%T$#ToKX9|NenEbq?D>jt zv!^Rk0&g5o-pkxLn;$tANPejz<(|Z2;Y7p>AXc-aW8tK?4sc#Yoh|9H7SRWCoU&g( zaPaudW!s{G_wu6KqNCC3OqraA^1SDzibR|#vDq=SzIO_9$_FMrUE_@!i5r5Yeam}= z{%|_#F5#`y6H78Crrw-ZoUr+{jrB@WHl)U?ZyGT)Bj@zoP-*h|A>~IdOS&a+wu^LB zza_XPwDy_zOBl071}z&>zCLwGd20O$4Ql3eXgE42c;spq^Fvaq6(=6KE-7){ z%f}--U&hRla7k)eaKps-74b`3OY+8GY(>uRjyW|__E+23KRO;Q1+C?TmXcVSP_ic) z>dN-Ap*LI0%A98o)GVvMsqW@Lg_~0oIlm^n=}^lkuKJu{5A2r`b&sqFg-bHm%)$N^ zHL+_;b~IsKwY9aP3DIL8*Nh%K-f!=fpVTd_xhY{|;Ox2+-JFU8HB0JlN!aLABxclH zGo<|5@ccuWo9k|=iBhPA`7!N_TQ{U@;7B->mH+l}C->Tlgy~<_s1^-n_bxv_cx&(A z#GX0Fs3k@%NzgLv&^_C?Z$JCN%o3c5*DU7Pv|pACJK&OlDCaZewQgy`CKo%d)LehYA>IL)uJ+67Le~nD zriRfh>WHT*VM}GY+UFcSP;+D5SR%THHH(uDWtOq^KmM`v_*Q;XFt^xH;0iFnk45Kt zF2>pZ!v+~#W7Q2M@JDD&Wiekz0?C~aAQ((A-)4eI;~<4H>D1MHeGVmD0bL;u<_UJ2 zOZQMxe}>^upWxu-bV*M5JB3hE5fI}16SvoJhT+&qw|5?`U(O+AWV4h- za%eK8P^cJzF^6RZkdVbFD+0wp!prautqR-$yXLb5Y9kCbfPjlL0FP510X+8bf5>O} z-wr0ZEyLvUOXGBkd^85kVzCcVoKJBWeN&(&nIA9%!x{G+h$(k5?pTU5DDrc1U>rq` zT}o-qz~d=4K)BSo3!T74l$POZMe5u|PT*onpCe%@{LmYiK=A;&^r;x~;RGhW2Qd@L zP2taFp4bWMDpO+=T}|;d7KstdD6*J5 z@k5BI7$)Term*$~r{mwxPcdokq@|sk=AuwSr#Wu*v(tW+#@!(jB$%xt5^Eq3U6Zl` z=Y_pMz8xx1iwW_lK~#52rxV0fh{>K}`kKS^i!kDzq#NglkZe>KFnkwsRe7|56(j2j z?jy}f47oAdxZ5O$+yjj0c~r*3Xg?EkDACrl676Bk>dDj*F*-&N-C!^nc6AXgp6+1? z8b8=+!ysFN8WD755iK@R!%U*MYzIOST|9*=i)gVa92P^A_`wSvLt+Upu_LIhEer-R z6DLW>M<^XEZS0Wd!!Zhyh>U~8b^(+1ASNhejETZ}>7;`RLYo-{j&dPEa&Lj_lf&aE5THb*PIHNxR>Umk& zRzwTG^<(rf!5f+hPm8&EIHQ@tFJTaszeb&n%gF?x1vU!rEu|$BCK;p9*L=1#v1yDF zr?n))WvrTry_|931u+o@lSh`sXju#cciv4(VK6j36r<%fPe_i@vfUHHFf3m=AEaF`l*IDFEf$^prjA4_R2!plm*)w3K^7a?IE4wwh+w2yM+MK&_jj8~%@lLF$N!Fs3$WSqKC7#lW?m zm0){AQS1lUb`XH@S`F^Fw6ur8MmHDL?drMD#!FkcW$V(t3I>Xk5hOZ0J&Q_4>aKBUUpv*gp4P%>!m3fO{)9}Zk%%+mz zEONeW|7~kFm_%9{#rK%WbQTz|%gz5r-vnDXjc++)RZoTrX3DRc@(VCFjJ=Kc!`SQE z@5T%KYZx1kmm;r1e;9iq`rUY8aue+8*v^7E@KW6|S$1ulXY!>*m;breXCFQ0tRg+6M zuFGYUYg>~)t}5Kzig^M0{U{g0Bsyc)g~qKj?<{-CNbWB zhC#-61hE8$Q&ahlMjf=1-qU4-eY!v`b$tYb^IBcgAnr6yV+cN+Fi)khGA$;)mwf;N8|#I{lb&m3^pU*ddC}QTno12NtymccMshZZqfd85F6khsrSM-UIgpkot=@nW6^li)023|hS#))-H}NHm&cWuvSAN_*3GXSgFc5nL z0t*v2OSXwuJuAVwbe+osG2Slr!XQn=b1)`Ne9-erf|C*a`5x&Zyax)3h6T?j2}{%7 zWoYM}gm(Li#WP;BNvn7zdufm-r%4?NT`AA)CGCiDF4TJJ3 ziZR2?EW_B&4eiV@GfO)&$qdq7nW0fgm^nVcfAv@Q6n&3#{v9R(ZvojYVze>|c)ugq zl|u$UT}n%P7`PL>BN=xllS4vyF%)3GA=;O~ARM7iL2(h2Jpcyo1ap8!K@9U;iIFgv zwH=6O3_)zZV71wTRXH&uefb)dgwtm?&u$QZ^R(|)=tHe8O7wZy+C*dG6{vT*J^pvP zJ^pvPJzmmLn#gbEnz?Z)-nUf6%4s#l_b;_*!Z;Vf|nn??J=$mYiu@4aGW$4EwU zos=Kr*=~SXs5Tt%(ZQD^|KXRnAqhdJ1u_!+-#^)H%A5kskeF1MHv#**VE8R^{a>8v z_L_t3cp69CNfGt*$fHgAIsd)(0j z+%}O$oXRyM;kIxB=K<$GvfBk3sItUsvvBy&Jh%!G8)l1IBWrn%El-dUc! z+^zAPJ1r|NqX|vp%*mNH$nvFyNOsW0JU?#e(#zrh-p-Uc3-FP>a^s>CW_QgUvY^oU z?`~gYrs>Vcxd!FUcK%mS*E6NqrPGA??nUtlbaq;$nR$1@JiSxTtE_s1shpd4f`WNn zI^u-!Gj(w0_MhFs!7nG~T=AKGa4;#W)N;ZMzicxN_k>e=v;9zUy;yPH{7c5^bN2W? zgNOGY?){%IJg;!U+zBH)Wi4DN_nhIm69&zgJbw6`1qD;`#$y8B&&=WTri=O~iLz~G zGbc#b6#Ptpf5z6~fAD<1=Dx=!pPDC`&)2IuzvTay_8vO1>i(xs-m8zYLP?+_=pF1J z`46vG^6#0u$91mlVf#V-;K20RV;RD1vx$PE^~-@BLz?2pKJ+B#A{^iPsFwQp$z}wM zjRULG9FFU0(P90jLAG{!J%VtH(-p|)HyL*Sc{|~!z;yf~#q;uf_Ph&xabR^iU?Nb2 z79I9n^C0{6<@E5z?oeMUjMcXib{hv)XBhPPk{9<|0YAUK5k7rk_*s3Wu>18*hQ7Pd z%e05}y9Ew@eN&;2`DFU=8)01E9k4S_dl(+64e^1qO1;tl0T_R{XBwY;?%tyahvdu! z%+WP+^0|Ajz}Kdg0p}tdKLgr>`Q^b^Kz}}F`pN~>7tcoq?7m`f?uuZnE8Og1&qeyO z=j61&+Y%g4hkGp;o|pB*bNcnIM?2+@)Aq3XtZeCb|7XnIt8EnU& zr1-qJU;Lx^zWB9RL86R)6kRkluCL575KKo+$#o<*m3)TeY{^|D_mtdM@({@*Bws9f ziexkY59ce8yhQ%jiyOtw^1o9u$E`4(kIDUM$^7)qbiXdy%x8l9q2y!YkD{5U1U+WH zAJ_^PG4*y9&37Hd&yn1pggjg_S74;fkCTiyUGhB1mq}hG`5MW;mb^to@t-g*)3iI( z3$Fq50Yz*e@}5EWY?1dk%D9agM#TZ*Q1L>MBVZW*Qn5h1OuSOOO1xgYNxWGs5pNUk z5FZkMC+-#Zi7$%>MBY=Gp1+8P#B%W~@mtZfPlT_=dIW2Urkz4=EV-H3M$8g9sE6@- ziT%aF;)SA_w~BBa&cg7fy@LEEOL?Jqm3WPKlekvgB*sK`KN+7t4U-RwzZE&Gi0*cN z9!J+uep7r;n#gfVlp~@Ucm>(+A!NpWLALYq&Qmxu z-xcos34rl)#j1M`kZkAYy(!tw&-+L+zw9&q7vfjq z-$izO=$|516HgQQX_Wp=#1>+f*g>p1Pp_Zc2Z_>}mpX!ja=RkGb{=%8dff3IA!oxk^uWIKN^ zh(W9@=M=G;Xy@;pYR@4%f3JhW|4KYhwDb1{NFFZQy@xKAJXyR{oFiT)E*7iqIdqfU z*NRo=@!cW!?c#&tZ^i#3J}GiAFU!Hs=liqd_ry=cBjV5PLB!F()Mw}WRo!!_i~P?P ztIq2iDfh9WozFL0@-?EJzjv$T--r*04~b8U&x=*(@0Q{2a7|+s(b#-llua3qgW>H759nz#n;7;#81V)i~PvK^oGTBk;Ad+-d5}(_7n$+ zxgy7FGkm_dP_%pLZ~!;`*NfZ4yF?D@rvF~?S@A{jRq+k+FQVNmr(E*q;y0q5-{#<5 zh5AEcnpi{RAaeRQ747`Cc9QMOATl~3sZmSipSmZ!< z#=l+MF5V|TB>qm^EAA6t6#pP{EIjpnAbu`>DSjvZLrlaA8pEfG96nFEq1ZxfEp`&S ziRX!Z#6e=NI8K}(P7^N?=ZOo%rQ&k&Msba}Q7jX07w;5zio3O#XpH3 zh=;^u;y2>oMXbVX$|*&xCe{+`h>gW&Vq3Aj*j4?U&75A_Wd$A}k+dEyKa-AuEmHbfH-@X{l8(02`fTMuTOFmJhQ zwwZ_Q{fqC(21jo`v-dx{efut5x_R24BJot>egeyv|slQ9_f?vSkA%Y-M037^~L(BNBX2X%@WpO#!HK~W+vsnBZ=YZ zeUsk4wRghX?T;rc>wY|8?{gKan*}=U?wxQfnDF`A31!=U_j+1Rd7m6-eW1&qYX;Uo z*cXGUzpCMG+Ld}N7~GDXvhF?>OsVzS+URSacp-x(q>GS2h1~87S^jFG=HOO;J8;bD zpB7Cy_G9-zbLU9^l@qm82p>+ku5X}#-{#{3Rq@)-*78()CylYfaq?`a$> z|6$gkS$ipvJQj{_EBp(#=*|DZgil#X!KB6XFbj%x9Y>E)!WbxXucL3bS;i$PpJ6Ve z%itoqVCI%V5AN^cIiE7WiUqDP@*2qAY{4bLAnYGd#>%%>2C1wO0&-rTCoQ5hWAvDX zLMKq)l#0$nc zobUn;g)M%t@nD!GVb3P3}fvX=xmQnSazFOxdekifeq;^pE~gI zvOQ)OtdE$0V~9s#lJTQhcJl&EXrr_bChT0!b(@nsSGsta8v~m;sH_u=e`G#o=FZLv zu-UURyv$(}!_l|YGZhBYXb5uyb1o|~4*h8u)MvGSwBbgDVifRCJMDV{U z3`g5uj?uQXw}L?p5p8^4HV2H(l#e#SMpTyga5$KQ>19lYBzb<+!g!L2Kx-aPGAhGZ z6&#TID%`3jlKSc?Ea~NEoK=^K$*n`b3Jh=Bp@FYe@_ud(^ShL>h2-L$!3twxnGD0? z%!j!IW-g39R=~0vhQ+!TW<5+PjQ?PY?Qu75TK_MOfX(iV->s4N|KbSP*RjFn9iaj4 z={?%J(qOjP16pP`?!H3EXJnrz0aPtLKEW^TslsU#S zb1Y*S#K^8S4an%kQn$a`V$>X8-6*Cbt=cwNHE&?@)( z;0=M^)w{vtzdNoGm*W3FuF)%O+-l8n2L7|3h@P`K_-ytcHXNVdwA=nB!}*_E_UYJ9 z;Q(`l5vdt^|y<;!NJ<; z_a4HHx0&+!@mcLZ@3varTyCD1=d_gZ%usU3q@m`;UwcY|hzrL@bkNKoN zyvxM(-2pq}w1?p_29Z`*sWP8KMf6u;Tw{;F*XrfkZ7D{p91)s^$sDQ zt?*ouf&OOv7yO4y9xZ=P|D^wP$@3(ePgMwimE>#X&(Aarf2(-E_R;lO@j+O?|_CiR5MCb>a;o@4wWuMf{C;xA>s=Tk#puvikKnR78{5W(Trj=za^d|)Em z72H!ren_O;RBR(=iDq0Z{LTIsU~joc#lhlGajbZ;m?zE<`KglUyHZ>w-YBjYH;UWD zyTqNMSwaAM%zhc*<8tSxPwMC7b@CnYUGb1uE`BN6@qj-_w&MX)@sOjQ>Y^S0*Hkhm zT+=^G>@0Q{`-_7`bH7HP#9qH>wkAHG=hVYK2wC+yM|aG)N5tl0E3xWz-%0L0#T?PL zZ=(;t{n+~l)_?7;A4bg2BR}^$N{23;yL2)kfBturjlB7w`^q%&Lzw*?<(8d^>k`Yt zSpPL;Z6mDz8pZmrffl88LN_OtC2mez8^}&64fN<=KYe}1nx;8U+l%&xHyu3Qwm5j~ z$8JN82EtC0O;M~&nvlG|VNT8O0s}L@3#8rCyHA4)#xT|= zUEQ~L^s1aLSpBsu)j3+Sd~CE&G&kxrS^J&SbKQ4N?%MAHbJu+rn7D1%y}NSClXCi& zC-!Y#k&v$3 z6~T^a$f?`b`EtXujLlBFPWy4AKKkKRLHti&p1u)PE0jA=QoBH?evNKf607}c4oHj$SHf&qCG~Zc_^>>gEeDosw8Lkfz$M>)zIja=sVGO zKgrm*EV*{EbF}|esK-sA%_(Jx8&@S??~HS5tO=J?Ut24u+Pdw|nK`xA*Iefub)8Ul z=Gxku(#pc6sl`calGi1y|6_w8N1Zg3WP6mN!xB7ryvNp*QupT8(YK;+M_)dkymdkp zeiIQUciFCocl9iHdq&F>qLGTkl1;n%l!y8>t4N%`<~wKZHq$biS0t`n^IgDseAoHq z&iQ9lBt8tSY#&?K91rfjcURx?RJNRwGb$3g4*7odS1S<9&4J6xHOJkpjlaLTV#xQ` ze?71~H1N!dgiC{)1Lp*eg#v6v!J8jF;FeS`P2D^#nvt_F`bczC^sf(8%W-eU3b$JW z>k{8Py6cBs^LKr*tLLu3x+S|$n=a!c3r{^URc z+CjCANu@Qhn(yJdL&`s`lk!zkO7d4p$t$ov?vV1&8ieqRWcaJ3aOUO^R?SV`i1lY{ z2D-UlCAm{ZAWd%DoFtTDa&ghuWA6`bs#a3FENwGaEe#y$6AV=ZFTCAJyLn?y#>RA% zep2yyUq5?axGWJZxoz>}2Em*mxc=s{%~!n!as9zR2!9v;|M4{#EG^D?6f4oD?oZf+>o8OYZ4d45%&mRB zw&#|GHoX^RyW7^6EwHln{TA0v(q^|J0awkGLoK4-8ng}Srj&%&3_1E^$F%jWqbbFq zb%|Jkws!RXk6o-l+kV+qpJbG#Z3=Bn+?;?r4%VTa%XMheHf5BAN`n;vT>0l53YUdT z(n>>HQesmYWRx|?L0ih*fYw+S*KX|!=jiRYe&0)XzDjb^=XS{X;y_wS#^w;#pH0X} zThr)JdTG-K!zCGIX{Gl5Kn;OqxHHU!Cfp&M+&UFW$8cw;O^wv{ac!g~q4wO#SS32G zETc4J)}2jT|Lw=&vW$&srBfQz$!QX0I#NpTzh~`=(ARaNA7unO@-9+qZm8_)-c55p z=bdD8$dt%C9}mU7Vjb3-?T3dH9+NmifnDfd1h&Ik4s#dXd`Iwo2yT7e_uW8ZZv=I* z*erV_?;*b1VlX{|35^YsHqhe@dUTyemr%lMK#)CEx7$MFlEi5=ZgN5~rR1aw5JSHe zyP>4njL+v;sC8@n4{oP#=iapbn$}+Y@gkT?IKYl&7vgp- zn&8<}5XlLCXTmtC0d`^ngAf_d+>ic#cdRa(04Dz zD_{xa(w7rtxXA{7o2Kt@nD9f?KZarv#YZWQrN~}lcq{{tqc{K_)wrnbcuJq3>r#!2 z+FnG71GB>u81!O_+!v#oS=4qy5F*!a4YO|*Fyc03Fw7|zp7;vIuj8Vd3h}$R*pA|I zYMw|{vnZ~LiorE-|r|kLjJtKVSI23w~mWLAR=4%$!F>Vh;lc?>Jwq%1;MEuHAcV^2$}}- z20Ux5WK>T+4B1I%z25=Lb_RTxYcge=3#YWxVPWU55iKoYxdfI>8?xpAxI7FOX?O;f z7pUR02zsVQ1AUE#=dFg?xY#mnNTXpAFF!N?)vO}qrM7>N1;`J8UTQu0K?beO)b4=U z2@_ZyywRR)Q(c|xK3bUE?_tTbLCwjc^>{L);w1#wPZg!X{Z<9NO?t=BLKVM(CDR5q zDvlWywc10^_lW1E_db)}P<@+TPd**8cQU?`@O30GCeR%hgDITu@HHnJ1j}hWS*8tU zPV_iqd(nB9*~RFS150f5S8eovBZ=<3gEmZLsRoI|LMPj443f{v%qKcaW zy{wA5@HQ&i(n1wi!;)!(p3Y{b6fo+ijJ_eT%tpV(M!(xeckpn?v_bvR`QpZxw!qfF z<2L$01U6^Cm=>P>Ax5`B{n0tki|=-U9RW^lF!_JYMn7bupA$iJ8&uJ2^+OI?;kM_s zmi^{hT!esL>-OZ;keyl+@$Z6o$k$EC`{0veu3AraYAr-4Za?Jdd((t^A|A?Uexrh4y&i&Sv^ zuM4Q6dN6{!x=}%IqhgO$k=zt2Y*3X@=Cz1+6O5OmrsjGYfq-6GJ$X80948-CH?YyAK9QB~Fqg^A!vun#c$YiUR`TJ(qJZ=VFGb5yFllsWd<4G>3pONrbYp+n1Fw-@~0ZQN-I_M9U>GC`4kp zb*H5ca)y-{nZZ_`mAC}PM5X0g+-o6}7144NOrleW9}$|yXkQPL3@IBwbTo}o;&j$j zXU#^e3259X?})o~Y{YPsIjuEp!gXu}WHb=Df5ddL^>Eh!$1_5>4zj z*5Sm%FsyNMuW=qhaQddn3oRcQ_u-!dKUjBK+L~G$M)dTGdv_5nb3OOPz_r$$7S=SH zcx8o;v6aIP$q9|ibo-p)#KkaJ3%n>s%R(5`;Pn7Id{~t+Xx2a9?+Kw8Eg!((JZzb& z&PPmjMok?eMjgoa*v^9crqs={smIBY6)mh!t!)PMQ)WiH> zjF!=!5Q@=qF$~f}%r@51#6lP>C|wkzWtr#B%j7NNj;ru6w$%~%4T_0U-dp> zs&|Cv6O8#P_>m%3@M;?e#bS;Q_&*v3Wk`5cS>RRWWu7~0bcJUnShHBJ^;6(8&z11* zHKTnsx+7krSebGMmLm_wSiR$6IF^!P3NfvPH2f7YJ`d zzF78_?Q=5c(y1n!(+yn=uz_&6C;5Tr+!Ckct6nWE^}0ULuX(?gY!RNVQH(xaU^1~5 zdC%rOPw=BVn@x53Ei@q-#n@1IXW)s*WaI)DX9Qropfhi&)nRBSFM#2*0`MwtD6cJE zRt#aUs7wr!@Dg^p*eJ#;tsYD|o(N2Qr4MhWyxN+_W6ia(<^?=8b44s8&XD;q5ex^W zo_N@Wo>&>uUaPg@di@2)t9UC6S7@(Vn6^1EPbhqI@D|4lgl;6?Uhtsd<={2@_-(#w zNb_3gj3PcYk%m`B;{D>J>i=d!j;;(j{!}5&`<^q7Ft0w&NJbiKF2!+`S7p50!6vmG zrcS&arT+M1y#ke6&*n|yj~ax)bQBhj3E_HnhOo~cgjnheQB)a%?THVXQ=f&tZ+Ib2 zaTfaWp>*oA+=WbUhY4elIn!8(mfa-wFkBunu7$?+a^t!WF3%X(%Z=+?<4PC)npoLn zsmJqU6@PXLKe~Sp6ULw)#+Yxk(WMhgK3(ZqY?>C+L|4{}^|?Im!^AWv$1WwZraEEQ=E;y?|LClakk3ZKh;@S z`|p^#J=Iz0%XM*3E~h#RN}F|e>NZASKD!XYmzM%x$=N5{soPj({n-1ixf-g}&j?fc zr#cIL$9o}sc`5i0>L(@M8qDR$B8QVQ5wkS_C+Raca2BdBqAg=zL|dr-h$tgoM=A09 zL2NHX7F|mG&KaY~>j9x`A}I2P<_ksfd(TPb6QkG?Rgi>1CcKrzDDX;1(hWS;6GGHD zcz0s+pkbT$rHCR6(RX@Vrf{-lfI>2dZRE(MO@?jNa8m923sDsjW2^oECZ0CikbRnb zrD`?#O4Vv&%jLbRQWMHS#cb2WCjyJwSAf2fx1oF`Z_no|c^k@>e7u-h?!4(FVcv@= zcY6m)!sHd>@E?`CRqHEvdvag7+sv|Qv#S%&tXB=*%OYO~f@oW$_W)gRC9}yLu!7iR zfo$N}uO!(v(0j9~!;1qO2OngZ$8!?J0iWWfd9xxEtYvW_ zl52|%ePdf-Sn-}|Vk!`#$UahOw;Gr)<;PI@S>lh!cOLc>s>WlISw1B1Mz9C%T?zK3 zl{yv|F%9f>2T`e{r*H8I>5#sFPoL}47Y}Q{df1&bwxI&=fcXXAdoq!4c8b{-A_u`} z`wCifVNh+vL>T$7Tf0;ucE+HU*C`5`c)?h6iI-r|moJLZ@`2~huIjZg33xX~WLkM? zA~LbxSaXS2VN7INcmbj*5#=z9j2$*;{oMGBAh@=gd?KiVmM~CDv@+JAtX%f2@TO2) zL`!uTyhjw9tqmwdV31*gFS#ZlEm@vB!CHj-<ceE-=NMOXR|s^wPrDS)`X>4;#tg zRmHakmUPvgHeZ71-V@}z4(;soviC~6?ZrY33eg=<83`KrmSFMyUP2F9|V zf$+JcA4@%C3Sl(Cmm9oZ2VxOeyuukxu*1u!_C1dF&yi@p4$yAj)@ZjcWwci&Fy6Vf zAE$8kK~&uqCK2{TR66ZFU{FGYch)uI$(>&5-c>{kUq2Cscmu{nN43-bx#vaj%?1^+ zt%#|92?kM!*Nyc;f(6cmknb4hVZ^&IW}^(7M^wGdBCIxtu%cMaVK23xY?P4&Z`KE{ zIWMF)#4~D~h7$Z3$TZlGg7}6xC;~S&47xM*kD3Z!!%NQ`ww9rl%2|sD`b%q5n)~@Q zQ;Rux;Wvlj>_dk0zN=-&NQOUQJB(=vI1>i%i}-JjiTFPmCIKCbt}SDckGusXNHFJA@ERd|l`(D_=(t-5gZEALi6uM*4o>h4ASrIEgMM^92}R>glAU`udx; z$HDgiUs8QN!ISmWsY^-q>GJnoeM$A{I$5uh$z-N{N#)Si$uMXnY~LTjz?U1>G>5^( zFb!Z^MmydD+-9sJpu`+iZ$^B*uYA#tzucpe?Tf#C(f0fC)-?jAWxS&qf1Us7t3Pxx zEMNYc{@lwy!rIsW)8e{)umAA39{_6o^aB8VZ9e&U*=dR?-iYa>SC><~u-X3L&$mbF z(o3*Um;Ytl_Y(Xw?UBjce_~SUq@?=VkiR|plIm+iCu@(?_1}G8x24KtdJpG#sip^U zRl@k1D4)#9aMIm^R)+G0*aq<~;}rk;LML{8(A6Veg<;F<+1&s3)+9!E_KI*LP+zxd z2-{~ui1@`{;H!cr@ixK~d<28fK{kVQ;%5loZb@|d{~%#M{XAmR$kz{k#=w_Z>tx3j z;M=s{>EE1ers8vxu=wp}FGP0JeF=L3;t$3t{%MO&|K_yvl%JYZj3W3Fkcm%1J)7Gv zp!`_S#BBG=mjd~nv>7qwO%cZTn)4o`V+qZ+VbRkWR=RK)4w1c z_KnqkS^Op69BnF>BK=->IezEjE9GS{3HY%9&p}!l%6D(O7UGk}DSne!3(?aP@5yh2 z({>Xoes|fZPzlZzRBaPc9bJzsulwP5;&+Bqchl@w2!!xmOqF-)%DXewk2bna^(~UV z`g-cqH9vmWuhhk4UI62J1kp)J^<8@YZkjKtzDI231$m-+CDo_P|G4%g)u-!ZkL#O| zE_TsxNzR<}rp_Sv20bsP`(cC+Wq&TE%9Y4VKm7z9dn<7Z8p zl0ReiKU*y}q&RUkj;`J^BUqm!Z^D#W!)MHznw8HA{>i!{D7*QEQ?UjE{83g^Giy>| zz84xT#?+mAfIIIsjkp&_?0;|Py=J4i?cODkCXJiG(#q_)m*r+s6@R{{ZDtF;aj&Pk5cbai_GflvAjT5$h>xjMhu+yG7V=A_En|8uUzgo(Z-V*Sg z^kd_6bpX4}?HJ50=fV*;C*q!sAcJVx5{S4TFCB1(yX(px*q3jITdN0FOR0Z-ckCb7 z*iG}&QpZc}VzV=#w|U-TV#B$)3ktJ6bnsNhmqGC_oAZm7Q{iPEk3Fv|a$r{5VOIVt zyU)e*+M#lvypB$MRhcRIlL}5)p2eKn{ELU-YA*5hT~2VdYq=OLTEz#Uz1{cn=M)r1 zP6!S!vvAG->WvV8T6QOFE2$N6Dp$X$dYAvnu9T+wO}SOs4iI9;|0R0@^7(#}wR3t^ z=ZEe8?%FwB|Hm(#$lw6NW=CU9Ul+kL7Uj($AOfJuh=xo~X}rs{e3 z`1^$L=W#xa)lK;*!VKaGbXdPWkTJt3e(dgvQDhkX&X4L;i|&d^7hf}M99SK$fqa(F z!CLdGgu4`zj8-*e4DYbvCPDO{w=KSc&u!$Lm&vr}Eri|1p@y%s9VbGI4(m4;vR_{r zzI>;{jrmB0vHGrq-Nu2{snx+-Q;~Ka*6(WA{rYxzU($cFc20>e4&%QBed#=z4y*5G z$S3HV?v*RkhoX$9?>DeBPJ0+0f9~Rahw&uOkN!Jh{Ndi|e)6?*eur>qQ!E~H3_Sbf zYv;TSUz=72T!C=iObqXz&C>G_{rT99eAsfX2|ruT8L->7ObvUW?;Ton*mIHgTA|nI z^M2XdIV*c&{Ru|UVf9(r((nGySUabdRcvTW#dG|3tewN@W-M>-V2M{Azhuw9dI-)k z;r;z&Yv-`DbJC@Ax_bAzATG`@;&Yu9)-j3Md4_dKtjE%VM4&cuM^xi~uE={1E@ zM1I|%`wVfmc!juJTqSN0%fvgyUE=S>7sLbNTjF2DL!wz91?T@(vRyaFtb+pgfhahp z&+K;wPNa--oGRv%xHx7j+(OA$N;Zo*!+*8pTjX!{J%hgANZv00-IC4vCGdYr@^kX% zkMKO-o08v`{Dt@r5uI|AZhj|Vc(acm7?FD$xt}GuyX12v_mgbaEkQcWK4yqNUjEbM zf2rgJl2?f9M9%Nz`R^BhFTN!{W&6l;X6t; z`-(yCEqRdqhe{qN`4VvsiF%zcE+L`!I{B}byg~A=%afJ|p=>h5Li} zmfSy-%t^!4^EbKwC??}J!~EEN!7?Z#Ts^rrA#vTcA(76`az9&gU&%vA#2YS7k^4+> zfygge47XIgPVQ?Z-y(863)6MK_=xy>`9C4PAol|#()kXFbbc)Na>?IF{*lD_T^O<^ ziSuxXI@wb0ZN!dpKUZ>ZahTlAzFdemRq_n^&k`?_`&E*!5pR||zq#?ecZxgYzf=63 z-1kX-PJB!5?~CQ)7xMo~{JY$f(3xa@)5Q8D&f8pUCsy58E2{7V#IXuDMVu+llm7zo z8gZ3aLgIX8zbw$~mj&*W|88-g_?-9_iE!_WW`R7YsApfP3SIOV(X9ayFl5Zzb-gk;--zubMul%1E zUy=W-;-BPxNOHOOz1%sWpZN-l86?hATWlh>5ZjPQS7#FO%zjmn`%1>+$i&BGVQ8Me z(8qoN_0|#1_hrcKB%`Zr{MnCVxE^9u93T!AIiiN)ri+(~1>$AmmEu+6_2Nw;`?}P_ zzA?E~+$P>DJ|OND_lYlxe-O>{8hZXL`H)yH9uvP2e-MLw{vlp1v5xq2`<`}Ixb9+4 zF-PRO5Y)>RE654r6!B7Vj>v^07>-M3kk^YhiDnTGxZC|tZj0q+$%mWzAU~jn*Iy)*nZ0qxqmGl7fn9~;aok} z&F@8!`JT*loG#WEn~SZ)Y|-><5Wa`xo??G-usBj2D^3#g#MvTe%<=qJh(+SHB7ef8 z{~GaTaf@ii^1=UZ$@hx8MbjUGzwHM-E%#T%SH(Yxe-RIfreB2k$0VEn5o9y+6J*+G zQp9Q^e>bE%e>)_bh%Lk{v4hAJIT-F7F-Pnt4izsH$BPrillG_Jw^;sHi`R+8;(Bqj zc&oTwyicsUujvbNe?@##{FC^Bcu4%KcuYJlntm7TuKFjo|5aUbrfB+M2-jG0Td}=( zj@V1I{jdupj}pg;lf`M`9C5z5SX?SzC*B~g7dMKxioX$eh_>JMTgi`!Rr_y$ko#-m zpT+mYPsAhQ*Wz)}^y^rT>Ia3zbg{13P;4o-5wpe4;<=*f??LZC$)?{2d8FjAqUry^ zeY#{W48r!z@0jFO;x!`IU!wa)F(%sn;4aAzi@z725MK~&ztHYy`nKFZ6+aVAe-P(O zQh%?yX!kFzC%KVm`-QC~_Yuz*Cx}zT%f&0itHtZYo5ZzZsklYFL);j_i=;yGfD*iRfH4j0FY7mHlQi~8n?zZTbt z4~P$muZeGpRrfJH9q&@qS6{UIk)9)Yh&Wu#6K9B5h(+QCag+F<_*?OL@n!Kt@e|SR z4~o@DO}ZM3&BR_}Uy;k0G5vGIs{3}{FZTz<1L7aWuf%V~+IY93zPe)7eKN<${UY%S z(e8J-S@Nx--LLW~$?uDHe@d>q#`Dz>8;MOtyT4>-$yN8293}U0;w9p2@k;S3(e4+y zUb5XU@=nPQi;s%Wi!Y0R7T**9DjpMm5QF$_$K*@2`$5|MA6v@3v)Em<`#X-1JVl%? zUM4OUSBW=@rQ#OxUhx5OueeWqO?*@QNc>d%R;&Xf!l9(sX6z7UuZjkz~7H<%LE#4xQinoft5$_cr z5T6jA7GD+*h;NGr#gE0qB9}O1dj26MWUAc646(M@P;4T$7TbxP#qJ^(O{D(8;)UWE zagvxPE)W-q*NCgcVv+kxQ152(R*_3F(tWqMN8BsEDE>iwLwra4SUfC#Eglzt6kYs0 z#q*?!)y31r`eIYDrN~vg7_YO~L+mM@FAfw(h@-^`;uLYVSRgJEuM}5`tHpKV262mc zn|P0Szqm)-D?Tf}D84SfCH_VHQ2b0hDt;?gh#~yw$nr=QYlt<)dSWB7rPxO7Aa)VY z6?=;V#0$ic;#iSub@KeP#0BCaahbS6TrC!h8^tp5cJWSer?^{uOnh8?R(w%>O?*@Q zi};~BN0&%IhTwEpIDBdiVh+Gkt=et*YNc^4ng!r_` zMPeEL9g&N~QvR!WT>QJpbz}`-xK-RHa#>pH`>pu6_>_21 zd|&)d{D;^Y0|ywtop_-*MqD5+61mVV!^cFfcT0JfxL&>~lI zoGXqJ$BFaB%f*|;5|In(GX7H{SI(vUhR6kUDIXS(ieHOi{IEp-bTLcpAadPZ`i~d6 z>MrHQBA3~ve51(Kb}4Ta?-cJ5pAw%HKNb&*T%?!rYl>W=mvT#yYw}X=E^=vJ%7et= z;wW*BIA2^N-YjxOU&eo2d`5gh{6IV;a=l-MPZhbqFXe_J*ZHN~UhFFVN*p6zByu@m zhQChaiocXgMK1hH`Cf6i_=xz1_>Rc+ff+s|rinGgGsH7RE)mS|Lqx6=OnI_6L!2ev zApTn9g2D{{JCSP!Q+`wA(!rF=#be?(V$F!>f4X>%*h?HGjuRJ&SBk5}VsVog6Ympu ziBE`6i?54siJyo^#2>_96EB?^Vr{Xb*j2npoFo>BSBqRRnB{S=$c2L`?-kz_KM=W| zF#W?~8!<~9A&wTOi` zjEK#}_F^Zoo7h9_Ck_&G#S!8}ajKXv&J-7lOT=a33b9yRFK!ge#Jj{DV();L50gK9 zBe3~9t7CR{2eY4#_blAV+3nkR>Cz<<$?o2*JAmWo_y0NC7AMC~vMeL~ z;)-+DcG?|2TI1et+FrS6-J&fEiXZ4*xOO*o01BpkYp`F&vU!^pY?-w#*x2j?)a-Qb0~Bbo|B~%b9(L|2jn2O3 zsl!g+;n9)DL*sIfhXy)L*G4x*_f;g^6X^a{6g!+OdMEnDfok7;bj9rZF1hQ)!%nj| z5Pm=6_KD6anOi!}Nt?K66ZZ(o$SLdFEjnw>RPGy;c*!l;iDpH2>>2aO6AL%&jvhRm zIQ=r7bJfd-o#_iUI?bHs!TjX)4WnuKsq42!?~XoI5nMGenzHWT;pFMP^9Sa?j9pjY zHXXaMEK1w(^6^md!NaMmmgnD)AKbvOPvyUWFzLm&MPH1*4DC-=xc4M&f$g4y#~W<@ z+v$jR`5vUpy(MA8R^+7o3J0G=0>{z=!=rl-96amcu;}8o|MBF#S5+hh z{&0F))M>hM&Aj|o8(88`R3zW?TjZzJt})T{=(82!0CrqicFLY+}3SM=@s^6|F2!a1)Um{(f5F;L+&eJMI`?SjplHs$4Dfb7u~%XUN?NB1Nr zuXm1Ky{u)lund~_=3)Ps-O2$Sl1c~=24xVjfG{eNNkBja3?(2#2=kyI$RG|(ks$;Kh&HIL36l(w0!LcC zifG$7HrlkUG%7eXc8g+*N`s_eO19$5K#(=gvYSd)l!i`brp#Wu=13%qCEXT#7b7-%bLKr>Gk8tf)iBy1 zT0i<2&W5bw!BKcw%J>6jcbC#zpgFMR;#J)->pSIt~*S}G5Xba|Kv$LV^ z+H6;4dY=$9^%a!lpg#`w?O^1X=N8pYqdD?+;(VgB4ua_*|jR$sEF*V@Y=Rcv{q;>4DNf4Q_z;k3{OoMT&GsSNb#`N-So z!-dm2V06P<(a(W{f9cVTXGL)Rf@zVp82e^v>zkJJ-u9PzIQRQBDV;wpZ9~(IjaToj z^xzxl(*>{BdwN>4(j)aED6^=f`qw23vez~*xuUe+sy?fOYpz`TMn(OtZ&XCKet^-A zZetm*p{4D325)6cb02vPC9xKvjp);@ub~e8A9>?1p#XKkjcrz^Y#O}wmCA6S)!HNV z+T7b>b?cHp)f<9xdv49!wlc~RFDPxfIt|C~x^>W_IQwV6Q8A!2xW4VGcQCsur=7yF z`fh!_-fwW6^Gox$wb&3^^_$Afl>O0eE898%Ye8x=tOd>5Ps_x)v#SI% z9X-$qexUv`D`z!)5G{b`p!o;t1$wkEy|APM>an-@jf!_m(oSZjwcF5XQ_lL#HEp7) zC$mzQe3kaZ!HU;P=Wo6#2CqcLlcP`O;(XraT{v*x`m)fP;6077euW=BKN>tVDY`ql zFY2|JwCbAD36D%zhxA(}u1kxu4<Xa8|S;J+flM zx{bH5$9bJH)@z@;w)gb4w+y+lbjepmkI%Zd3}@BmSo*QPeyGyN%6Xr6Y3@ej^Qtkt zlf6~EVAIX91@L;c@5#YOSHrVexWVv7-Oml?22S{yX~%9&`F-xJSjIiLwq;<>?COFu zWK;>xHO$*-Sk>OBn7O^-=7O@|x=XN{;rzl{HpQ%E(^i#4H*hUm*)KY^bPDI#)N7_q z!>G4g1?^PKrKu?!uDgfVlWE&tulGhpr&UO^@~Tps8$?$Tc_6b^N-jt6H$+#r>JFv+qsad>4Cd_u2XIm8;@&iiCM+gFgI4QjC*II-zOCJ^QOY{Rw%Regx!5E%FS52eE-3U-B_jO zmuy_0TABXH8;}McEzS&m7Q`$o?iuVF&aDykan&!_P_Syo2|svq>8z3k8)mLru&!hD z`@jG7`G(P(H+TDDuJK3%qq89IE5&s!lr!yv3NP=r%9N?qqoMYTy{)}dC-lty8|zrQ5wm>P z(r_iu#NDM&AKtY7=1pCn+6Yf*`<4zqdTVB*b3?~6Q)k^9Ue_R6dL$4$P~k-mRD{}b zRV>C?pNDlmJ2k{71w_qUkL8ya)u(=%#rd&=bm^KdyeS8q(1-qCXp_JRP!!O}IW7mn)htei9 zO#w9n3#bXFm{;<`Y1^QaGcF|K`+xo({_E9;IhL}Z-Xj_P6SV`cW9CqrdG9|EPGbea zp~cu0425D=;=A@K{gE!TJizoyiaRm4Brx5ACV%|{{*$e5v z#lOI4iu_?hI-3?4LyO&w^v5$ zi0?Tw=ELokk?x^Hw^v5uccmF{bTxsUFb)p|8E|xEgnJKYF1=Ma&yR-k!}I@SCd=hPUUS}Twr z$l_Z$3I8vCvR{~x^ytkL>5W^L)S6zkYW+}N+K>2m!SparVvvY_TAWW9i5c+XLVqz5 zSuOKJFz0avhx6!hh2)HbYma@LZ}BaH7>uG3Ef8QiaQR|Jn8SKmVXOrLQW1Pb+N5HH zzV#p!FJ^@0|IjfD3xg#NqLqyjZ4iu;1eSgQ0*nI@mm;9RHH#Txp-D!Akj2C2dQjyP zs&4UV)yKY596_XF$>@!%^pTht2BE86(Q^hVuX^5PwEmCU%WV}c#KV= z_~OMZK0btQ)JzAtGT9GJO_hfd=A#3&h_v04PjJOWwyzd3vfT=Y7cue@0_sZ?;RHgW z!;2WXjc1cLgs)z|YV}_&VuZheg0Vh=uj`sZ8R0v-&=YFcSBsL`_0=M_>mdY_gONK^ zbvQ;!5K>`IZ$5mlFwR%^C@-MT7Q`Px2z#Xm7N^dIh7w=SLj{T2_zcDr%SbA^48nmz zM%aI_97yyq(V>K$A$g`hA)2hi5V_hWxd~X~^o;B>`aI%8r)T7BOdpg^@YO9-4kJ;c z&l?1A4xpCkU9)w-e~rcR#f(fxz)3?aL-4)1MKMOqmBJfw0MQK7{WC)`M)(m647G-1 zjPN~s2$?ZP23a91#>f~1OkxhAMsN9IM$ARiLs^XQ^>g{P2*-`wV^3y`*6#VvIE1ViBPS40=qUh7Mv3}n7TjDEW8?y>PfVe4oG5ul zJC4wtS-zN&?FhbC5Hg;4-ZnyM#UlQGsJEF8qltV3-&;@=V`Q1tyJ>>H<|Jv10Hb)s zI0Vx!MkZPz9Akt(gE8%5gzrF_b}{l00vfX&c-2OUj}VZgD8|SMt52F^%NKKE%|$>Z z2+gtOiy7g&hNc=xvuycd&ay*h&n&n3P#>UfSuvu#i`9gF$#wgig1iVBaE+7WX33P zb->wByto}AoKi;MGzekL(0sy91I%|uIR4Nl4S4Zlj&E*=ndgOKjJ#llaEuYYoQ*x1 zF-CS+AuGnnUIYy8m%ycFDwOUjWQ23W_X>+*ZjzwRy9!e~H8K-rzDw$+imCH13?pA- zMcoKH#HceP4$|}G5eb|V~Jr1Xw-NeO_X~=O1IGu=@COVXuZ?%M7I7`1PWQ6M_j=FpyBd;M~q7WaN=omu1 zy=5^YJW)_O(aJM=}a_NWt;?6DSMrJ8wk~Um7-0o4(}}lDG@sy4V^H0_g^Z|+cE-C1=~*rQ4i||k z7Bcb=1l+3=tS9s@EMkN|lEt(jv_$SLWaM_E&;PNmvo_9$5_SzQEh|c_;iX#^Cf4xM zU8Z8|O$A01tQ;zEXdxr~H847x;F6A;OyZP@4k5BkO@r za{Xr%g4XRUWW*k0T%t*%*d!K?QWD1)<&NU4QWuf7>Ur+Su%d6S*u0$cS3{VX1Z(1Uxkl7Sqy+*U zOU(5enJ3ME^U;;hRJ=}dK_Z7C$bAH(g$S5R#4-fqxQ~~jXAqbSP68O+gTUJcpr^T_ zj3exorYI2OrK1Nz3i=2+7>y!eju5<dNW%o`)>6W5mxFfL0ty zdK4b#9;R5ddHgkl0mq>3CV&?h=r}gW`&wb5_eZ+>TIS_Se*^(%DschE>G?n!}a_5^!@ad%tDxVx&N_Ncts?m`Rn=(m0e4?he6BM7gjm~9kz*~JL5I(rc8 zK1?PGyqCbGlT{jofMf&*28|>}m}ovR2EjO@NK`t{RT`;Xoe_0aM$}c)ouxnUNzno+ zI5?;l?o%=8Tn>&}X9S#qL=>$+Z?88_Y1rfVjAs23Mk1zO*yCfI<;Mc&PS7xG_s{u|AIZTas?{__h=V!w_tzS_#D z3L^&dWRKM%(<;-gbiFl38*#>HN3qJ)ro^k<_|oe}{Gh%!=X5spofGlvhx-p~(r7<2w?G%??w5$&t+@MrTSkmTwcszzA@^No0zEwOA@l zei&$F923GI-C~Zdt<7jkO3r8$rZ`hXqUI)%slKU}5y!AxBbo|!plD)duPMstjA)8V zw8q3t5?4Q4TbcGXl{A^{Y?zSG&Q*Cw6a-|Vg-$tJc_-t>&G zJq0~Xx-65xbhSU*=20&c+61Q(@D|rnJOR`_{CwnrU(-kA-Q+b%O>2#qDAe|V=9|r68gC9}x;@HP*@o&ox2eyezSq_M^b-H<9N541&xhUQ zNOog?9!)|wYT6EGDJ&FM&uJVTcR`0n9sD^t?K`x<2xVhUGV4HQq-i_53N~)jv}sdD z8%@b>?`P!rGa}i|`~?vR%a-);mj)vK_prLW6n3e!0su^l#Fnag%0^ z#!SBO$|mQwKd*87woTeLX@A~%7y9$CAVx0m=jXI)f(370#IM`mp9>xSM^LB4QsTpN zS?iouu$AnOL>nUh@ErfsMeq9s1wB}<7QY5Hl}Nh zHQ>{1;GS;s)?I`=V{X}6aE_Y|HkO5DX8DJfb**jZcw!nVHfErmUE=?%4Go*l?c51= zp=DDzZtA%sI{wTCn}5W*^Q_JtQ4DMncYqOVnQy+XaB{(dnUkq72T5dQH^-0FJ`wHU zS!>d>C-oXI`6ln*v3Bjo9ycHfJKg^$X0GGSHPvJdO+-C2<%Sv8z!La%Q*WAlZNya4 zTJ<(on5$S-_O7`6@@|n=~0L&zUo0_MFxcI0wk- zWZVO^>(b$(NUPbCZtW0B=T=R=@vr}16ePMm$sO_QcYW>21b-JI)Y+!X21 zzGM4NU9R$ab;VuOHS{RpnRg{pE{Eal$@AL|?Bu0ZPaBvX%t);rsv9^fP|vR)Xb@-^ zILB`kXdG;cJ2qn*lOI0ALl*xczUptb7jo ziT#L&HM4aR9n2jrgeC|~hr3|2RZYiz+*%^wS>z|vU4S%IkDL5F;+|RtDji_96&O># zdEz#A+cyf6qN#&tQ@$&dw?D8P$MNnQ(JQKRj?b`%Ja(P=&9^1$I;T4^D zd52t8C#2BBgy;(min$@ACaHHQg3W8qdnJ1o3WEL#D1cg zkJ!&oOquR#aiVy=I76H-7KwL>tHcfBz2XDnHt|XEm*NZJF7b8o4e>+qkobjoOf>Tt z^{$W{a6&J*azNPo3BS-ei1EzT9q`GS16NWNV( z=MD7tNZurx^9K5dBpaLNke`zLocNOXJJHxWN4mEqzb}3)eky(`o)Etk|0$;8qRsxI z$8_>+v7y*PY$J9Rdx)2d&K4=ZN?|$t28FC@gLInoH;B$Q`aH>t#bx3h;@#ppaie&@ z_^|l6xI=ti{I&S1xJP_P{Db(B_-B!Cld~OPi~kaXSkS0X7oAP@vn4kan~2RtzN*1| zd`*JvE?y?~6$gmJ#nIvf@mldlah7;So9j5v9ooN2bhg*;mAqBlCO#(qQhZi?MSN9! zOMFNCP&_1lAs!P?iQkA-ZM0{guI!f@;#pz?F(PJ*ZN>ItH__Q}ze4hrV!k*+94}51 zr;9gmSuh#On);G@z%E%Li&w)4MhleDT0c)p*)a{nbdTcp+S zAWVH-vA)*H+3|6DR(W~P3< zxK(sENq0zoM*NNVJMmrdfcS~{nOH8K62BGyDW>AtkjKvuYl&xxjm4(o`Qn9QSJ8a$ zh;sT!?kDDp&i3e4lCKe`i#Lh$#D(Gt@lJ8AXl&8rc=t)>E4XaOe~3?t&xw4|fct+d z8XNVH--I46dQ|GZItpC3e4A8yhQ9J z_80kmJJSspM~l7xWbsCEmRKk*7H<_-imSwR z;=STl@fYHMh|h@6i7$)472go|iwDFH#ZSdA#B%YJSSfxlhVkJM`!iE?wpHs%cD7ZU zN&S#J%D^@eksk#KYnd@vq|F#P38t z=(1jEVl|OJBBVYdwh}K8JBnSzo?@ z2gFB3XDfH7$sRsiU^(exb+N8kUu+^a7cUUo ziB)a#_Le>>4itxoW5lb)sp9qGY;ms0-+i*4E5#CVjkrmSi4Td7h);^Y6kiZ`iToug z%YR4wqxg~dg?LOnC4M7*FZ%cpo8@GPHN>;T24Y0a7Wvy%=IbI}D)tty6bFkV#4+L| zajNKS4bPUmKyHj8vC-MV6)}xwOQ#@O2C^iwBix-H_ zHuA-iFA@8S1H_@?NO6LAt$4jSL!2)biMNQ(cJf`4SBV?Md&P&uN5o%=&x@~!uZnMp z?}#6Yhr}<$W8x|C8?ma5<&0XkUu%eGiw(u5Vhb@xbheheNp`lDqmrGi<$TG`*7DVo zCyLjJH;VjOI>&jLc)NI)xK`XC-X}gJR<*JGtn@F6uZnv_XKVRA$sdV-7M-o-uv%Q=xxs}*X>?HOOdy0L<0V02=&*P03r-?U+&i3*m$;-tR z;#zToxJ7(Gd{lfwd`5gud|CXh_@?-__Gz8?hQQ+; z6;FxZi2o9Ub=432+#b)qI9*LXzz`pA8Fta<)JX2p&b|A-12*3}c7+8uxBZmOw~p;P z%0}Ez+kD%18EfJFz~#egxP) z(Czhx;~Lj2t%g0d*9_X10h=iiSRx8-zwcx)Gtkm&vMdUFT7KHTb``;~9V&uX2D+bB z8LIX7{jb;AR)ODHYzS@+bh*3t#OU_iR7r&#p|V_5O;3E9zEOs~hMVJQ)r`)5|{@_P^La_~`5D8OPGS%wy@n$8h|Y zzX)%tz40J&rB((zhS3`Tf<*^vZtfEGa@y_ljSaPTmj+=&tzv0yV?*uZr5R;4H-|UO z^X_jH-0UAq%WN7QzT)|cU{BPgellp{< z+rvssxUA;J;3mH^m>XV`vAOp8F1cQ-?)%s)%cHPNmwxfSZm_eZ)@`w^Yv@|HCDFQ! zGqx@bE&CuBHuTV=?9GcSg4F`u>%zK>>(Sr_TAfQf8BAM|`|AF>+pYDne$j5x52Anm zqUQSIa2?n|8om@gzbRPeZ_a>auddryhWB`5z06hBR*%VTmRr3vebrX4*6P#~ermW~ zosHqLj7_QQQcAK)L#qO7Hbtv%?*46P@KgAD;HhuDyc(NeC2qUdWK48r^v>vt=u^>M zM?<;4J?izrUZe<4*mX2D+PpIL*6hmEy*s`QZrSmzSG?of(9GA4X7t^2G_8ND%G3>Q zDpPBftvIkEdxy6p+;R6&uV<@DZ&aH~4>?kMcK9~@#P5!V`s_ZMk=wk|+mMYGKYub% z?T!7Zm~oA^XKoI(dI}cO{#YDr<(>F-vEM3tfBMGfQ9~T7-JYXfe;haRo1?+YpZ_)# z*>yD7vw5YzBD>Px+osar5UKR*q;G!y+tj=#SG;mGrFV8^trd~Vz}`q@tqn~pYqd|= z6j&eJSZyj=C2N|pNKhR&W{p1gBrLQRFarM=|7l3 zfz40nK6lcqnZ7S&YIB zxZcC8375|E`h8w=!(cD^dB*yh8^Rld_YU@MY4l-(Ks1bV*UQSP44i0S&eHpPXBD@B zrKs~iue~|-shS(vJ|UmdPfw;1`#f*o(^-8A>q{_y&mn?seUUby6| z&-z94qECD_j?Y?V=?w+uV%-l+hx9NMe5oLLgAFM2{ca$95^DbgB=ej1Ml={qF&Btn z+E`@q-{OugW4R-gvYAPl$nSci(WGs_ZrFgjol-chHgY6vKy_gLo2a^oui^MZ8SRzF zXlq7$Pqbw;B?93qpo0x4{?IxY3YnKU!lBOCmxAlQm$Jm#fWou6m$E#-cco+lY6hag zzXt*jfj<3RhG)!dPYo4_<8AwRyrYZbqdVmK)}-;$%s2Mms|fzE%og!|QW5buim-88 zL?Fn+;K%GkQSZP&7M; ztcEMPtXT02^vqwg{CPp9o=tf-<@rWFMR_QbFEDa%?5b`oOce$XLH#FuVVKEpV*^$$ z#LY$Kk%asl<>LwYFy&JTxkf6=qj9T+rg;9GvpTI?6&bM{A1mX>FerVIk@+!WbsD8w zY!3dd5n+|eicRt1RQ35VOJ&6?jR?C`R^&%))hEUC(i>BCSf*NHI=MB*zB)`(S?O9x znXj{wR_=AkwDbvKxPiW&?wH^>`cBRB$>C%UX2L;eU9<5 zxpI?o+4v{%Tvnzd5wB)nv}+hbHtz8<&G9CfoO7|)9@EMzDVt+jxstiFPT?POk7Dm! z=TAi;wHl$KH{uSlRu&>Grd9|My2GgLlGbSj&1&97+9H^J9E-TYf5a8>kSpR@Mp(pN z7U7bbBIx4+E$@qehvW4xF!eu$UAF#KPC3if-^%kKdo?EDUt`Wu)AG3{=le`)dfUo> ziRZL(U%o|YTF%#t3Rvx>{xvAXw481lOv@KA!fM}%NNtzYR6E8JY!S>ppG7S9A8)$?xTL0tW2T52^HI)6@%rCo>i;k7vh}xet$MEIR?dfP4}KdC%vU-B_xSwg z)YN}9_L};$7*qd;psDSWnu9;f5^NF7&bL7V8~tlt5r1|?e9Z{EAdKrkZI{#(aSk-- z{}TM$jC{8L?=$t!#V%WaD^H|sW}cOcnYG3?{NvZ6Hs=E-=iYcuD<6&Lv~uSL$Ye%t zGpfv&RRT}?=U{a-Egz4)rscC4VYP2Xq_#_Hs(n98uthLC-*X8(?O*MR*z1b;*cEY# zMYyDFGq+jlJBJ3N5YuNpu-Ek2 zU`E(y6A`KHl9~qJ%o1!7%+7as0$oC@ToEf=5u02QkFyAu)D-b@q6lW^>py|6q4!)7 z@46zsa7FxsMYyDH-UOcyzk1)4cGp@_{PiV^nYgNW32NlgWILZc#>eL0Kx z#Q)G0@q6qxMSR2vi#Ul$ZI{#(5o&@G?3u{yD_F#z{qw3L1JA^I*lo^%HjMBbxCD{f zE~z;O@}Tj&vv@KydkKs9)Hm5DVVB81ml0-PiAZgi%w#WvhTH$RiBe;VG^J%`zdDg> z0o-=cIw|ds8e68$HmMOZe#D+>wbSjHX2O7J4O>7ESK8{bXNn>y)~FU3p339YtcIr4 z4ltT^ZlHY~3ZtrxPNAY!ir3zxu5A!kBGk<7OWc8ArsyN+YuILPU&2Ta1axp;V3gA{!rwK}CKJF{ zyb&cDe=BOuqg=4PTq!qDi9?mI*iz9 zwQfk6m>s$efpPLR1Y{&=U`ckCDy-IZArrIP_8~A%zKc*p6`Q3BvkOzvRZK(j72!sn zt+s7KW81cyZHA^Xrl^n5Sg96zYl3WQ)pQ($OA%Ny*&CsT^0=eB(P0{Nve`Im`Dp-k zB%ib~dW3mM^oA1=)7(*RE+q|b)%@8e<+w!3aX)sXRwm`>M9R@WmeSm|dqW6w@97OC zXonaBlgK~B_)((KLBU}*=ZIKPFLgz#^*j}HOTb!P>#-A8+F5hGB_A}jdm`_>-En8x(=ccvK=0&-wvAg}M>7kJXPcqmi zUK~5~+2)ROrjl>~vn7_?;TzGJ|1cdooL$5Yff3K-goS4BFrIsjOkWO5Bpl`v-hjP! zW;&Btr z;|ET5xgJVQ%x%XwObZ!_WONDwto{-!Of-++-G|As1(633WPOs+?Fgs}VNXI-g{$}h zqaRK1M8w69)5m-q>5U~GLBJ`oB*w@N1kCoGz+My0BY3Xju5H^AuE~4MnCB6^w=wnM zV#~7_Lrt78(V>JrnNb&ZI%ghxl8hptBM1(sDV`BKc6rG+N&BGYI?AkW2@QH3%*_xN zPU_v7N&TfdZK-$X6FL*!ZMF{hZ^yKKj7z3n5l0d=&_m4C7vutmr-4xlJ7$E@tD6}J7vW(1t>OX8Ofrb%2mhCYXO@q$6MyH+snE(nY#+Az{I0RP_HIzi*toN8qe^yV1$ zH1UN+Bv1GtZp_GWCO*fIt3LD|$;$-dA#$0C&k2#{_q*PlB9aR~(~ui&yy#Vs>vzbk z!Hi|0aY5Whv5H)*?Vd4+@$}{%+dMlnRp%ht69M}dldALLq&f##_ac*Kc92v(QCCHlcVuRxaN!2>l)!Lk4rOUxF%|S@Vm?}L*9v&C@(`(V`%(aNCU72m-1>~Jxz`xs! zVJP5fQ-cw%Ocpc%A*r4eIYd|=+(;$u<$&$88RjQ-#2|DYQaKf;%iPmd$w$ny1q4+9 zMb-@q3&BI6EVno5h=o5qqEjUu(W%@KS?0B-_)*C!`{WzH;iAYhBk3NDs&Pie+jg^2 zRiz85;;DyE3S25?;%vrs$EkRt>Nd@(n2PmE$9b%VQDjOya1%TWlJ-)3&8l2SbI$iS z9X;Er*b}o)SGgljK<1eUxYiRY-gR_R@vaM#ig&7{;+@JB@5)TNYh)|_Upyj<=XDPk zA6Av8FrvxzDKO2A-$1Y~RmP91DkH;8_nn@Rs`*A0|JZ@5DrHf{ZcOR{X5zgXu3N5N zw?TZ|sN$b3Cr$FAA5L!QvR8{F2ibqV<&4)u1 zO^1(SvBfs(iethmrvOz|noU)e{$i#t5peEsNT--$$MFcuZPXosmHmfFc&6tk7W3mX zV-@ypHhIm{l};+xB|NT9DyQP{by7K%s|U;Z@y9dP@_*_`EbCoU>oKe%ugg4>fkGQi zu2Plx%Q{r)e5!uD1DXGXIhgs#Zn`?{d7mWvM_k=p3gOmnX7bV z;xO@bKA{@sGBT5`U;JK#sw!QXNEI(Dp^CSanQU3{F`%kSS0+-$%Sx!?WigX2D}Jd= zsN!9jP{qqisPbJKdEd=b7w4W+ak=6x;%Vm~6-?(_%MuXC)Jn~Ztoe+QTOD7T~*IQw=3zqXCtUiQn6w`eHf4B~)$CPXye?4_DmQ7&{{fO%Ylk^hC%-a2s_w2<;F$AzX^!()2~#ZQ~HX7GWB~ z4N3ZB-OMC?5#q%N%Mfl$((~qzw|Km@lFWbXHfp!h(C!o=HVQq#IF_c>*e%}X1DRHMf|Zn{FafHetyJn1Fs;X zBQSsOFDStOOWL;U-mY!y-f$Y=@AksA@%3cDU+VWrwb4|+T7gm3JY_J&`VNq*h8rS& z2NrUg+m6%A%$jo96>!9n5xLYK6M-rH^NEWh{-FLX{g;Y*_&0%+K-bMqne~xaeqV-6b^22?b3hHZ7Whx8_*UZ-d7B!T<^;Q9C8Mby1Fz-07Pn zO_;Kf8RPS=+U7)+_Ut&ti8W)QN-UKjDR`*Z-U|e z;Ri0RG9Fny{JA}#Yi4`UAJ@Zg5ozHM%K_MpFBFyd1^xZZ9Dm+2dLwu?Xg$Z|_%)^s z!14dN5RLQS#Ba&qq@aLR+))(Chbk7F0%Z?WyQz;ctQPJ;hXqr5_;quP4F3g>C5eaq zngw*qaDy2XWO%x$pk|HJ2|rPfcv99NZczU;t#ho9D6DZtsF%y~oM|>J^_^EUkAWhZdCf{MX zn=kVl8KiaFdW`7=yeIB9cietZ;8z&&ts)oSX<~BldraO4vpm*|x8E)gqFx2Q39Of- zaMA0lq^nui^PXtJ9CmZ*rb0|UZadtQ_iSd5%j3D@79#HQu!NT`^1KKm+T1>VX`Wo( z%mO_3L&tVxAh_~=j=0N%sP_@d%S%$Y=t}HMF0UBn@he%D$8*P($M+9i9z?yIE}r*= z8^ol2n-EVfFAo)FJ6T>01Xtdph_k$Q2;9!<4!e$SGC}4(hG#^VF7wiV&!@p6q`Me- z-RA244iqlVeLIn^t4jp3e%#(dNN&d{w8Qmt9qe=MsD*e^H+Uyd-XZAR=8i=sHP0)# z{NM9wuq*ff_i2EiBe?D~{IB>l;F|HHJ`K#Z^2dD|VD&cZ-haoZ0p}KN-1iX&hoBVS(gvYm#VJUCHN3ZcQS8 zTk#U<`H2hD4;F`M|0wYq>2HwC&kb2lvGgm&RpLF`ze#*R`bSB$m#>4dp1+oUw`5~u z9QAlt^2gf$8Hs%5(!)TBsqeoer=u>cKYs?ma*Yjf$jvAtv=qCL(DxMkiG#G?*$f{m z{S@h^i-pqPBHk%Fo8W7eZnN|clBoCNBiSUK^cj>t>vi|8J zO-3+XZSfrGTS#src9Z^caez2P`-hA4XU*~_lc@JiB?hfTMwzr`-Hn*XF zi+a@m9q~h@`+~&&FC`mW+mOGLoQ9h@?yp56|5>83sSSOO_IDADV`Zf4sdW9Mr^9OI zA0-+a+Q>gk`wPV-+JB39r}Xzo-XuOMy|I~%a*WMv@D=TUReVe7{wVn)kw#6}uD^@C z`J5;`P!Oh>OH!+JBpPxAYq& zZx$by{#W8I(b>L!UFqJI{-ESf#FNthL-g?w!FpGNWk4t`5@=KCmm;4rqdcGrmsQq7P z|Cf^gF8MpjX*d?^QHwHKau>I z__g%^64THYmIpVNrk+`11L?CRw-P%^e~D;pIV1m-+CNwvrTw_AHs#{Bzz~PE#}Vs` z=9@Y6Q(MXHMf2PMeGkb|vA<}ZAFzM8(Ck#HHfx;$7leaf5iD_>lNZ z@mX<~xLf?a$meE``v>Ad@vwMA{Hti5Kal=A$$U6x{@UW%;<;iIv6Xm%*iq~vM#cVO zzBod>TAV1(7UznKMEBftyX3pXwW4|ML4EI&{E+yB_>^d#dysCI{4GWt`vVRt`XOZ=D7;#AC&x{jl^7wtkeqx?DOdKnY7tQk;^4%c$ zW^sX7ESl#xr2Dz#QgOXlCO#<5$lQOxew`@N$w&#UsU{-o#pU_8y4b%)a3Ev^^K#0SM+h*f<+ zy(s<5;vVr$@eksk#KYnd@vq|F#P3A>Hp%o;x>#L2TWlyc6I+ToVh8bJ(L8se-_3I; z*kAe~;&5@CI6<5$UN07i<~bDQERk%UMCCYOZ=Vq zd+}ZIfLPT>lzCo7Jx*x^+-QlGOh74 z|1`0x&nM^W=@#vG&-ZspcD|lANq$ItM0`^GrRaP;?UG#ex&MIlG&9F~eJXw-mW!vv zO7VL!L(lIu#Ir>6c>v05D!GN&R%|bJ6?=%6i&uzw;xKWnI9{A0P8a8h^TfsCGVu=a zZgHKsQQRs%C_XOk5T6rY5`QbcF1{_kFCG*>5&t3{7rz$26$ALPpW~1sRu^lD&iB)~ zlADXIMOt@e{vKkk*jIGEpN2{vD~=bP@2Be}JKs-pB`*%@D-t>Po%!D(;7JUcM&fYdyDcUb&VJRw$y--)zm&h)j!2I9G5bFsD9Uc5-WMC>K@69C4HxQeM&BeB2d+`#nm)K7nC=M4#i<8CcL>iZ8J)94x63J^s z=bPy%$-BkZM4Fjr{?Ej(M85Av{r94eS8phvEjAQsmY({H#hzlWI8q!d(!xB`7m74g zPxO<*}^oK@Sq`7{U_eYWD`Y9h5zY;6N zG`uj#{nf;VVq>wb*j}W$f2JQG4i!g=H2BZ`(?#0-r@Tm{`G3kKB8~r3zF(xZf6C8@ zH2P2Zb&>E9ITK!Nfn;t}ynkq#HQKTV{A z11FQZWbuVM0#7GyhD6h{H;jm z3fzA{q>ly4$3(hXp!_e9jut4_66slia<)hZ3zWNv^s_*@zeq0&l&=!$T7mLRk**ae z-y+^F-X+r20{8zyq;mzzyG8m~p!^4st`;aC73pY!@;^m-R-l|E(!m1dW+MG8Q0^?! z%L3(oBHb!b9w*Yf0_7PZoh(pZCepgO?V=JeNSz=w0jux1{y_hTZ6$gt$MY>;L`q?7gFHpW!yi+U@>5hT>9~EB_Ulr+q zf%`uY>41Uqm*U^Vzl(Ii!2PvFdSam5T%wnK;x2Kw z_?oy^+$X*(9ug0WN5n713h_J9y@!LJ5!?P1>x%WoMq<_XaoS1WN$e@+ihaepJRUxy zsjuV0M{Va$k;L{>K5E-v)TwJbll-TB)LNGyKlD+1`}PgJYnSah(P7zJ4MWF%mKJK^ zpDfOWSK1!0H@vE`Um85NJT!9O$H$*9eBfj#{kiD!=-?B9aQzd0AbsC=Uk0W>{biuA zMfuMP0~gQ3|F8FlPX@y4`|LUH6%L5*$n6S$wCk&VeEiWu@5IDqp=iJ8htYSBd)@XQ z_xitkJTSfVc%c89lU28>UgklGLAL5{GsXd${#>W(+cO6KUCNt%GQQDPU^E8IXdMY+V5{jtqjcTnd`Of zgEp_t{P_4yg}M6z(K^v0_`%Wg0KzBO=flGdeI-#9jm)vLfXUKbP-Dn_s_zS=6fpBPzccTB& z4dLuSN@?1f^gsbT9Sy4=T$5IIu)^CFzQ;S6l|CRhb&Y?*ulBSTShF*lzBV;>u%hmk z)YVr-pUw?M?}(<9#Ey6FhLOam1qv~Og_)gBlwaOvI|A6S3EG_(U2WRzjd=%cMtj-T z=`G5aH=J6&95Wy=eQJ3qqj~xA{Q>8ggGjdDAwN%Wv)0qWo6$r(f8z{MIp(%WoUQeHWEykC{?_Teqp@ zw<%xKHZ3ue0$tgMHT%OX6{rijk<8rG%b$&FsA$-XDHBLwGMETU|C(5rV z++H3nL@#&4JfA+L{Ql`J%kLjEwY(Y1Z`Li)eOCEH4Lg*lw3%K0V4IH6e7fJ;@Y->& zVfa|8-z)c)<6fHq(UG!5?3LT3E zLS@CdAGn%xCL^$Ou>cVLc z0tuh9>mm6$NZ|Jx!2gq&yZ6;L<1yyIO3ed@Lq#Tkh;JyS+`>Zc3baPL)X+=#pBCtj z|A7MNt+8V=0Ow5jfAb#vZ;KE<7kLA7??H4CMSRx^7p>gOBCu>goX`J0iV3fxxPW{4 zl4?3V=LVKiq{ZTNz7QH%M)7`%otgL+ihqEZLFcQ>De=9<4EkQZl~R4wCw(;wx{V@# zypm!3zW$6AIEZ&$(rFeaV8lsy#UTCuxcD=Q+u|Z$Y`~vO{3paS=)`peOS&S15`4HC ziQn~S%!dnCBk|4pjQQ~3Y9xODo-xVg8%YWNTUW9Z_|TGhVk2a`<+n!3nDVs3N)`#rOvMslV zCTzC664zeHfak!&0+gvV=z;q>yMN00C==^mUY zULIjyj)g689xJJe+s$F~_=+dXLSk1Ii(+C}mHY92wt4bh9-Iyy?_yzGk?3ZkBZ)tn z=$J!54O737!~hc=#u~F_Fn7yFU0`ZGlHgA|Vd9av8X?u2Z#+;jey!Oxl$dU!Lx=(d zrYeFPCB}=)uA#*3COV28VVxn3By1B$6L!Fd5oM;~BMI9>Ly0|BOVCgP4LSmKO>`vD z$!ZDPGh>j_Y}xp4yCaXtMSxLQf}ICL{zWlHCR+Vm;69@-2*ntA#0udUBRi~+8Dr!* zD`dqO;gb&f{*Qp|F^yn}|rdT}(m9J@It`M~`LZ-!xG_*oE?r#HoGGk4lZDsdl#Te;?fJzgW zn&>EE0D|w$FN!geXZ0n3ogjIf70*~LPa!)&@`%q7Osg0Mr$ zwZi|t2xv87=LVY!VS?391ZLYP!KngcqwfP8_R~f`KQa2VL$So@&$grA-;B-d%oro~ zRLmcSD6h#l>p7BpOmrAwM-p{OjO4IW(A$yB=U6>}0N*2_7$du^5RNhOr4=$`jL^~? zl4Zph;oxGGZ3J9kqC*Hf#+WvY@OJ|k8IJLXCYs+3{n;AJx*M&q1;y zlb;wFbO=Z08wB`<2*()Vkf7m2J2Ns!#0bx4=m~pT4?|CzjpNk~0o_jUlY>le4vp;i z9kS`ljhcM)Ql@uvF}9G^vX>7b;B+H+Lco7XQH&AxDfF&uPcP1`_$8pU) zJ-J)IPCq(lDktLUTB9-AUy#UOi0NAZMG)?A#s&`ZYUp_Mapp8M7mYNzM-u6C|FiTev(JB)ro@&Rb?XAkkM4r*u+{e?xiZx7z8=_mj_s8w zdWE`FTj&0yjumys%EkU-1e7bLTk{RZBvkdFn z_{`+;cq!z{i1hI?u0_5Twv4_c`-GlY$j7X{AGyowLnLj4qKy6|>yGqc@`Tk7Ah}RO zpGnp>$DC7?sLQM(F4;Y8U9KQ)y=E1;w((x_Yy^6~ngh>QiMy>c-Ck!PCD#!893n48 zNWncF`~We^UdO^u_T7;RE1Gmhr-2+u$MMvita!_8h2wwHS5g!GM=dGDAdJl zhw$H4sx+5JEi%W(Aj5KJ-*E93mZAd(RuBJg30bz5iZ zGmKbot47#6!BNC!t0nG3Ff)@4VGB?m@tlbcAzm@jQ3QtumC1F@L#s`D*c^nj5q{uY zipr)4m@Z3VjBt>W>}hAmRYSPvD4Nehkes4uR4!>RU8T8fAa8C=HISYgi{RLzRNk@t z*bsL@S0V|)-u!>qdlUF7inQ&!`}9e2Acq7HA*>z*R6rsD1k|Vj!Vv*wN0cZ#hLKGY z1d&}-bX)>q-;N9J8{qD^;J%@PI_@~=qo9e-fE&R$`d(M{RVPiv(V1tS`F_v)ehrm> z-FK~BUEN)$yX!9GP{7={=TLL6{ZZ2plPUi21ZVZRij=(+(7zZ_new0&rTDuXIb%bJ zHs%-Hg7Rmk3az+{zt7(A{|@uQzp#p2-QIA=4!)`35o5=V9|cpaBZ@DcIeQ=M)Vjn;0meuJQZ3 zHN&)|$*$_p8J)a8;1HI0le2R=v~S;@R*P%K)G#oYM!ajr>-(+GWYgzVc{@19gtE00U1fgyU$Ok0wAF0NWs$}c z-1~z}KC>U@IL4MRdS`nFe{%Sz170Ka=y77~7}{$dJY~wnqS*K;(_%188|yh~^tiEO z$Bm8kpEhO8xT2yd(~4ThI%Rjw?iB0LKBrUrE**}K9Rs_$<3<&YYaJVoB*%?Yl6IX& zbZs{pmT<=u#$Z5qLJ`^z=WfTGPF>D*x^=}3a@4p{qbE3SHoPf4U_^S{%ywsVa#Cxh zolzrHGqrBGo_o04z{_$Qx{ch%UK6)j=t$f*qlo@%c7l1QJ*1srKCb%j+6nI1A!y?F zf1`+c@}Qei1l63A1V7b<&|+MvpcdHXgF|Gbn+0ZEGu1AZ#@J!E&9}j>GvBESKfk za;FE}JDOKoQJuB=X~aa(_AWxB1-yKhv~_o{cQE5chDYF z4%UQnutdsX2U9fyTiATVm6eRvL2jilSEftRQ`dL$cACo0_7)&1=Yo#MSBpJOuK)8b3wtKvH%udR&tiMU(*N;Lfx;rvR6@zO-| z6b*7+$qhwod+u1t?ZvL5>8D7SFS(aEOyqM`mNP~?Uz{vX6K9EYMbm$g&e+-pOQbjb z8M5ie;H}c%BbxpU{Ueee7oQbh6#1nQ>-B-iXPA_Ci(iTR#0v38(PO_u{4_B`tSegE zbNp(G@mh+o{FBi>u z1N{=o%SH1>1p4bG-zwfIZV?|89~YkzUlg~AZ;J1TABmrc)os%KC_Qhrrd`E!(Yz5s z{dkXM_z_|Yk#8iZ=UWo;1o31sF7_4&iD!xY!i4EYixb32qOmQG@L7^C6|WFW#ATwf zHIDcR$+wAji4Ta6h);{pi?54sitmdbiRP&%^5+rudHdk@$&NF8)od5PuXsl*RJW#4NFiSl#A1KPzB-^Wp_ON%E;;T=y+j(6jTibcY);jX-Exom+ca~&pOK-Gf zYfEpE^4TWY*kp%nZRvd>{a518 zqOr-2cs218g6)?fHV_+&M~X*@UBz6nx=p<5Ht^;s-U89sUPpN=CEqR@+w0IjDft}Dt&XYy3M*1q(51-w(3roJVG2JP7$qbx=SQm z8|+s|wzla?C0kqUH%Y!#yia^ctZtL;73qylcI@Xnl0Ojlh~?sbu~MvVgYG!|FlKvo z6#Iz%M1By>@bg7$J8p(#ej&~9KZ+~Gwc<_Uts+06X8b>iFNm**{HB`We-X>Yzlr>~23ZKmrZ4ie82M~Gv@3&bhn4Dk|?-+ePbYvXOD zQ|N--hcB;G0BD?TLtNqk0pL3~|& zQ~W^ui}*M38}Vn+!w*63S4}ZPw6@)wORjDcj_ac_U9Q+eJWcE`4i>Gg_c4KmbWdOT}Y=4wirrEbnkjS8AIT+#^hCVyOzwSH&CZ6z7&QZO&^n7Dg1 zKA&pQ05g}Qs9dgxVe}?>oDIN zFtc>`j*JbVL~41Y-d*L9+MFTz_?|ZF+n+u3`=f)M^bzo5}t&SAcF!DCLw`Zkz}d)wBd^V>9S8_!z*Nc_h5u)-k~ z;U;fZIPKsov#{gEMF8_>(nhxEngVQ%#XIuSleVtczOM$^;UW%1%-nuBEv(a z*L>cdAFs7IHXcI#^X6x5aMpAF=hFDv_}iFu{7!{avaK?F=g^99-{&f$?z5FCcg`t% ztk7NVEQ7AVUH4LDw8e9kHQb>Uk!=WV;jDicGtIYE*0}SQebH2;b&;+`+P-Mo+dFnv zL`v#z2q#*_H|IO+uG_q`V%YqRad+3a_{R9KitvQ9E5d!;Q=dl}+bUC0R%(lVm{UtZNkE}Ct@W^O~=<+Sy zy?xP?n#MdW4a*O9T#{PBP+GJImr4Q#X${*3M;p&EKZmo11%!{OzpO*Gc zV`uNy`I&3mtj}7Nv5xb4F`KtW3g+GSiF4*WX8G2?zC6A5BbXPvI1*VAEqS%#m`z8- zvsTx{%-@m89*Dj-k$tdd;T4705B9)<=hZ8tv;7{(p6U0%$f{6cQGUP8(N!nJ3o63H z(eqDtPhczV$9}&ti@mE||yqw|;VX_Hvy zEZx&^L&jR3O(VD7?=)=MW<#y`(fJMIk-`rvoZ38tp3dxE)-4pT2)BKrd+Ru^At`%z z%-GXtUG%<&iHx;O*Jk}=4s&eO^x^moI1kabO`0%$d#0~C`+B10J$3e#?>H^qH$G@j z#)gLGTpqbKr|Dfzt$0qn&4#1%|8ePE_hhW&S@gkY&Xce6d8xTPhTTg*cQh{0T;Qbo zhFQa#5#)ta_&G}`oVJlyayNA@GjJoF5Fay=52qAL8xASlh^j8*_&1y~1_5F7@~G-^SmF%cs}wnb0E`H#KhV1JLm)f#df3 zEB>~F^C!&qUkmTq6ftIS+yM-|jw0U?x&s;dBE`uR2Ql<>xSFjg4yWiXDVdl48cK5u zDDu@^dP|0$OR)#UDCa7lN2xz*5#?Ov5tN#va_K8s*^v~FLiN(uC&hChM$OdaQJ*06 zGlt&8(9smRnpgU5N%04YeDm*z(#Cg`bCt)iMFtuPbCr$6^|7Lyt865`0*i8XvXPF5 zR133{$8xu$n3-%m#n7hnmhOuw84$ZC#g{35&HXo#!x$T+bL|~p%%*s4Ql#YGp8lVUX8iXd^=mU@!Js0 z3m}>q??8f4e>u;Y?>X@`IpN2p5iBR>Yl$P_@S*y=1eo0F!iNcO1YeMP&XR{|#7tTA z4;FXugl5xsoIwO5A>p!lU~)6B&oN(_a~j&i;ahR%CyC&5u7R6MmB?V#HWYtfXVK*Ij~pQH?tjuzj<(Ip^|y@^oGOq z17a|onLA4lTLk*~z*TUVUlLBxv&58)h$K#dr#l?F6%jYyK?JYgn1VSwL66`3gNb{L9+}c}zY&lrJrDZA>;yee zz~QJ6Zy5cOU32L7%|cIo zUx*~=iTOe_K~EcBsGXpvGaQ=bL?GXI3y3q}%q(wu_)-zwZ7fh|yu%2;dlg&+?+T+G zOk59VszA>jzJO`q@Z9eU(F8qD_(JUjJ=@?=1$N1gd@u1i9CDhSpoi}V5v8hk4rV9K zH$4nZPET*s!wQIzR!>8W=wUxLQ-L3YXDb|zJK=ZdLBvOJ zCO$pv-zL-V;qm+S0CX&~1v>P@rbC|zH7ZZ|9U2{%o{M}vG2eI#h=s;GfbhFHCJI+| z^9yGNy7`60rkig@69N=syCx#_GZ5IHV1$nc4H(b zJ~7^5gx{O7&-Abxqb=Bln;7pPf;Sjb33|AwHd>k(Y4!AsHu?gB{n?zORUNxvK6Hys z6f;v%ef;5h^xSCl1%%(-VZ?zRc6sD8GeM8v;R|esM-|xJcfsKbK(ND`QmcA?0Z#zl z649FIU}g(k9NEBZS6sUZzkP-iYyfC&nra=D9qv#)kEx8FomWBtFhUuRVSJT-L0n9cZe|fgqIM2e*Q_jlv<`PU}&$&97 z__@FR{?P_(%A8gSGN+rR6U`TkqeBJKn_gJC%*gVF686VBAEoIyftcy>RHFAI@c!I5dEs z-~|=2i9F*iAb2^2w(6?Nul&r$61Ku2Iq@|dXNmHMEc2kB^amb;?Z5+PJo74m3!J6z zBk?gtbvD6qOURi~TvZp7-oLCTPwlsni2HyniHJ!*ggDW73#yV2r1a3)LMdGd_@ETXsZ4j}xy59-NNb0J&` z?Eavh^!gXbVZ@_wIE=*8a2Q&<30^JVg<}dd0KK2Wp#cd0=7NlQKG%d(#`I>uVefbb z^GxMTWP6r!W;M@Fo_EySbB=nRYdnvrx91bGLA#mFj&V2*_7Bj^heHDqydSh^cj2(_#P@K`5j4%&-(`R6Z(B$B43A|si^TS~ZneKlPOFa1nwZ^dgnA(r z!F!mg13lbb6v{o#Gv2cZ?yQMIPu$lN-1Fa2Afxs7QxR+{lN%fBa$ird-He_M_nNOK z*oH>WUE$UYE)NbPMLZzMX_7ohNd*GUW;+UcY918aJChSV+(+mM|G@zcgP#g#7Can7 zBr~MITOiI1_MnT$67wtr@@SK$Igu)Jh)TP7bF-~eJn3~h`U z+=B8_7U0BCoBt=KZtE@C7__1DFV5P26SKAt$2{#A|EA}j>eb8knr3@rVqVjj_rSc~ z-Yd9{&dl{@#k@K(uTl1?r(u#VLXVCe?_C`8&d!D}$4=fJb~NW}*UWC;tiAu=n}O-u zxtzY;HB#5B74wQ>oEOZ$G4ur2yT^^CM$BC5RL!aOrbqnQ+gW~$!d$OC=JJ|}z4*HW zlgeM3liSz3Ao8i#Z2S@4_*}0+c3ul_bhcMNyPe6@pM-5DF#9u|{YlYYu|EgepZDCx zM9uIEndU>%Oe6X8sTJa<>Bux~{e&j3qm2I|;}1@^Hfc=-a{7BShk1>LVFq#z=5BkO zC(Q})4P(bOZ`S9yWAXPGZ)VK9VP4Gp*oif3ew>$pcbAh(PcEiBZ)o4_oXFOuUd`Ue zwL7l)5yu^O1m>V;cgGZYuXb-tu|}3Hcu+96y`b1@6XT&O$o2N%KF3xwZCA6mckx2x zaEJqQSg|>zNPTv1@969^yrDdT-h52go*&{|Zm)Z9?`cTe-4gGic^kYgm~6e!o4&!z zig`FVoQwZyz;E@}VBYt|G2D_}7w-u=cjC-xOm6LF{&sh&Pqj9)s?EGty!S=ieGl7k2K*qj>t{4h{-7v$p>o^QtF} zn^ZKe*!fRPuMU1(U^*h^TBB2T;1uisrIW3rxEBWJS|1a*H}cllJ)`BK8ka>bPrD*@ zamtn9tGqvku64U*_%8(hnfcb3LY|HJ-^JMnHDWf^W5fp<+>VCh1Bu^?*B)`ImuoB} zL(k0)c#ef1pR^{o`6z(-H-KXtI?AWP**d`Mg-%D1uKGI8GRebF)=V1q1mhstht2WPJ&#T%z({qAy9aEpGIv@}t9>HV;pFHh z_7eMveEP)j;bNgUNt`9}H!I^^E%LQ6<#pn%;{D>|;fN(Rn6#1{99_{>);-UGC%+rs0j)h3} zTawol(mX~0+eyw5yNbN-F*-X!;@I z-zj;E_@MZrxJ`UhH2o3jK9~HZ_^ntW^2FwTg~fVeme^cuC1#5qM1GOP^rwma#6hCz zmk2*kvYm^4f#hl8MdCd1Qt>MBT5-8(J`Y2_H%q=<+$7#F{z-gNd|u=;d)9l0_-FAW z@e|SXZ^W~6v%i!6fEZGLGyNU$xNHLRts^!Pn~AN&)*@dFFn(w8WU-sbZ@d^jSUgu8 zC30NGaDK@~P8Tm0=ZlNPYeYL2dyV7`V)Z%L_e=k<_@wxZxJ}$Hz9;S!cZ+4>Z_UB3 zfg3vaqn21t%o3Z6twcV-XMDasCQlMi72_fwX~6ouBHFpwZ%ck({8+SevHvRhYw>{icQK3$AM=ffnc`t0A7wMVnRv9= zR_r8p6}yRcF7}y{2a0El=Za&+Lh(Y;&c&WBdA@js_(yS>xJpcjH;H$No5V-N$Hiww zJ{;$M?hyYhnl}y5eO zd#%b#h_{G$h?~U+#OiafUy}Y+@qO_lv0VI{SRwu>dKmbzJ<>$8P7LIFk{gRhh{uS> ziXFu+;wfTxv5(kK94ek8juFonCyUd>OT>BNV)1Hmxwu-qQM^UGTih%@EIuYaC%zBIgsZ{D;LSMLRe970GsP_B)d8-0V*z z?-suj_lf)g$o#`%x|k_85F3j}ibsi@)4=p6hJY0BR(KLB5oC*6<-y1i0_IYil2#Jh!^cS`t=L?Z_L_0UTiR75rT5KnF67AgVJjwZDU$MVfeUA26 z=?lfFVzD?|oG&gGuNF(im107?NxW0MSA0nPlgRl#-0#=Kcf=3G-J+eFy-%{8oBemm zE}j7~pITxaF-vSBR-c1?rt|~F;o=B!y!Z$4LUFoi=VC9Ee5H7ec)$3t_@wxZxJ}$H zz9W7h+PT)BOSW^Zzmd!dQrz!|c(~Y5 zC|)j>iYvtp;*H|%;@#qd;-lhI;&UQ~x&LsExOq;B`thmuq34L_9RGXfh~kV1?{%n%%x_H}5eEww054(JygLQgwlZS>6G=m%FVwz`P;WYDT z*G)A~R^14VN_u>##^2GzKZVS_V}*BS8Dbax2PR&ID$f`;~|8sdim z{V|e9AO2&2Xv67%Yh$9Ji&d+_QI_UkJ1omEcfYG1G!t@#M5 z>J4em@y>-g$0MRy*TOl}r);K(O-vEq%l*cpFGB2>S0nR$i;=zCyfTjLqC4%MV;CeO>H+er!zGZr;I9YhXo=|E*v#& zY^>e+V`q$-HojelSi625W9`OIp3)8$C!9qo$7`O9@cH+EF< zsGvN4YP&I0CKpc|HKzFFDdWfEGc|i8^alVn%Soe(BqR3@wm#1ElvN(LDcU9<* zZubn{AO4x|&Z>QLhEweS|K?2X><=b>|2JnG2r&)sh1@#91#dU@X2n67&71Ky!hIZ2 zSnsLO<5602n~L8p{IHNCPYm15NFf4pU}w|7>s*Er7RR-Avtgs4uzrS}g7;iU2Nc%J z_wm7Uv+CfTKLS}U%j15K+&7yBUS}KvV)SUUVG|(-^E(Eg$<&69`SIs~&F@n9Z5nu; z%MifsY&RRm?@xmHbwz&dp<{kLXKa4U;kRkvb?!#M)PTZzmmn;dUm^12{xQD{IGf)M z@G}j|;?@)gn%`2`jbU_mi8dbBQn}DZQW)bs0Ea^`)dtl@B~Gvc$T-|yg0p_geG#uK zJ=$15ZqLC5_hV|Ho%vmr-47g2mYdx8T=?yzR8RoWSPPI z`l6qOBO8aKe2`f+nDX)ZI;bKD)&u?3ih;*#<9mNyHZX$=yOg~8EsGRZ$aiYlnOuhLQ z2fS2riMUR@Roo()Z^01%Wyw3lcg4SmyTx*Gzv!WXSZ;mMu6NL!GA@edTN`x9whHem z_7u%GHVEg;D&{jvG~d)f&+CKPFY!tedh^W;Xnx9r4@mzgiS{+m3AkUlCQ;`5?8ZqUCcd8hc9_=Q*@{wVU7IrGaDQ>n*$Lc9MEO}K3zUVjc>JCKDzo%`-UAlpU|Nbo?QK&XIER<_=k9QRRa5l;nGM+X*}hP^!Te4 zu}$IC;nGXvv~GBAv-BmkmY=shLJMTqzgiLAln%Rb=fwN%b)!!6wQ<-|ONnf6nt#{< zw@=*zZjC#;*Q<2u?BDTH9rv3ww`PUgIJ}zAu&(aeJ>Cfx4)LyT@4$uU#Cybh#hvC$ z4>)ZdcZ@t_lt11D=iG( zv@h(vwiNRoSW~pPFwDLea-xZ_hHqq zz4t8$;qO}uYORf|p}oV07Nl>Wl{KeD>v)4WYE)9^fQypxec=ITK57!Hb0E~WVP(p9 zwJRh2>sE$CZ`28WlNO3rcrmx*ecjW_z0iN{$Xc7ezHNS1X=Hu+s#>d4@}1Uwx9_ZI zvNbD_0c&EIq$hSNy->Cw|aBJL^u%08}>vd>N7kx9dmd2mNZ~>1(zTJB%P&n?<N!g5}?W9ItEnrKOlB`Kw; z%eOZPmEc)tI`*PH+lohQXT>qshgPSpL2tSK-S~U)5ok?kWL>o8{4Eb|$t&~n;$+*erP%D_+9UmrtaFi<)o4 zy_suhH#9cC)M=WZwR}~6`l{M{aknoy_1m5IgwcxY;#v7wYu%E5WlL(_SbkM#Te;`q zIMnD@c2&B!G*p_lrboO#&Lx~jd1&YUr8t++*1tGcN^xY^lBGD8(3-ypce}EUJaaC+ zoBzl@m_*+W8F7)7b6(c!Hu-Lad(x8bl{>!LlfEi#UDk%f**9u0JK)6X zREECx lyB#m>o`Umf?~W{-M=5BRp}T9Xj;z_YIemTF>a2v*qCU^itvExYNS}w^ z6KhiG?5$TB(pmWf^0>2mD)K1Xff}skb)eJkG}ysRHzh7tiRr8TGM`5L$eKTPZBpp4-(RC8 zQynmIoSN<;By;=XkK@E}pXBDIzsSF5@IiY!_|mVVc;;jH%cr5~uTkvB&_xtyGl%{R zy_sTLh7MrpcKD(+3+SFraWBP3DV{^|6u2mdeeQ6I95~gYS;YcMuOM12npHfPQa*3s z92vUjQRMeX(JPZ8KP#$5(}*L=pyNk1wPwOJqLDH%WU58eh(;P=q>hpvr-b>0e%Nf zp67C{Ad~!UoBRuUn7p7VvanH27PFvH7E6(wb2!}7U4D{kvbYAprUuv3!z>PKhAeDU zlf_ZcD2wZnd?T|M;(lebI03;Xi@x+Qizk_djcT%}c|1s{|A9haKM5~k(fBeTYlNDIv_gxUBvM$Tv*;dtiyIIFR%ZE* zHzR0tHZvW&Q`cp&wVT5BEQMj|XPbJ!&}@!*D_qx)gnraXntFUO%tVJ*RgZbs59E=; z@CM8SKZBXjv>uuSv@ep8g#H-G;R0;d?t-^!%Yzrz>Oqfh##OSh8szJ$@N{x{=&Ig^%yD8=-#8jDEW@dLA5f zdE_oQ*BMTPL%y0cGmV@%c_g!8bekQbBevOWZcybxu^SE*+c?igHG+wWKj?f;9vrJf zj)rrcbBIDX&zUtZK@W3*{#zgmCm5rXUEyGu$4M=6j!aPK1y@6g7H)##z+jwV5d0U{ zOALR447*C)C0g`?m&k)-5j5Fj=EuN)4tm5?IO@q+a5#9xLaE7Ba1q$*M1@d3r90qK zeNBS?N8y+W`5{~crlI`Uls<<`^)-pV!f&R5AT}9AqX%}5B3I%|Hh^tmG!)v&Y%TFO z4-N(9k$vINV+f9xV8nD@f*!Up^mBm?Mn5fNjDPAn6uP4|IVYaF2a199@ zuDm>i=EIqi=;0hToR`FSqhE5{JbHMa$Jyp4=-KECp#(j=`ys?j(8J*@1X$sO=W93| z?;n7c=oau2UE$1mOHaP9p9U;4-hl)=k+Dom&&x(XjNokq`xr{lQxAvNSd^tF3l0Z^ zIL3H~5gp(>2jvx&=OD53Az$+!tZyeO;x`e z$nM9!hh3`bf<<#p7km+VG|lV;J+GNagWd(+H{OASe{~qP7hZNq^bn#e9FEOgb745s z7v=;y>41^Y@nT?1j8%10l*?}Vq6uNS@Vo|xL&9$QiSZ63{BDX}sp_T!ZHF|Ova|X9 zYua4XzrKV5O*T70&$n=BvJ4#m7#vPp!tYYE+yp&*%Lu)_5SdJ?Iu9~s=c(-=w=obfv-U zN?ZIW1bdT7O3x=oz%ihQ*E5_q#9reaLa-;9`1G(R;d=I%F%xIIl?ko7xF!48NF0K1 z&CwV_@B#tzhw~EjgiYH9uN3GUW~sBAzJzgkPOp^Uy-i?Jz;-tH1Fd{2^6;U$jOuMnU2}Aq4v!%rhS%bNArPJ2YY6-sEQn&^wX=K=oZV*oD^?8uD4&U_VI zRrQLK)uVm|Ty4C@XT_^R9)`5$a6A|q z^J4^#M^WH-{PO4@R9YbB21Ml;3#A3~np1W3?Fg(|eF8PEI{Lp>iXB@0gHmwhIo|s9 zQg|Bj*j4Lefqh{pue8;AP+(u|b+}qD4D3tQ@v+xjb2bD@;qj?$TK}N4Ay5iKdCmOw zQmP-H8p+;}9Q{J21CksAL!};(JmCTfZ5sy@s!;<8*@`@mY9y}*=Jybru14~tNKoYY zfLOK?6nQ}l#G<&}SE&UP6n}(EbNmZ*f&#BlY4|bB3%FU6fw$2#XS%PjEgqMtj+u0M=xm-i{$V2LM;w?DBJ4nL#k zCFtRy!oZc|7=Ckuu>GQ8Jf^u2K&J)gqi_sT}|dxgUHaM(-Y2RIXvo-hsq^aPIuo}J{s4Aw;B zp)N!e&eV|}|5sdpf^CdFnhFGmTX#U_kc5LM{yw0e10N1y=(j@|Bt>JHttI~E!O;wR zA?W{XF0em{n2O`ffuF4$5F%sAhdQ^rN3-o$!N`V6~_w`3wPS z){-@(+SU~6s){B@I(*ERYHBf%V5QJteaT*MXz;#x;@8AH-s2B@JQOnuJaMDQ9Z1Hp zyMfERD;40DN9a3&Et2mQC0p#B7#1L^Od$Ho{9 zXEUdNEF6B-6Mj1_>08xKOZu{%R>7rW{J?#npTDXjzKmUB}R+CyL2ZDDW3}pmFUF@?;zwC$rgS zz6jW4P6Zp#5}s4w(56J#^rt0#NuE}Cs@|83nNGWek0s5FLkVX2i|U+*e8<8e8&eMc@LI&*UMaZcbvY_QFJlE_%!Rn&mnsg1 zFhmIs-E{Hf(2b$IsUSu;Ft`g0-4JLtX8$Z)wZV)ovCNC1yy79o?5ez`>AK7q2s9h3 z`2<{`_Ef2=|MIBLs-J+#pPe|!4B<~w`x7u2#UxTBJz zBK!NGnfcNG^(M*ZE$sQP0ni>{9VyJLA`#nB+r+FV+4M)B+t2Nfx}sKAz%$2g$vYzs;iCa zEZcrm{eMug`6%|_AMUn792oNlHcor1vL9REnMhFeAFeiQ@vN!XU|S20*tZ!~vSQam ze9Nek4_&DG57(7NK4EHc7V$Y;UGo6YUdZ?}wt4cUmcjyema1;Vnpc>tl8=KQgjlU- zQT2(5HH1(fPM*>BccWiypbsZ+arSqdAHy~lRpfr9ZahJ2kK#eg4$kr%Tz{xyJ}J&6Ok}Ic zA8-7P9JumRRU3ErYB$d0wY<4`KiATa5x8mx?^nU>>zSAb4KR~uO!EXo_2e&b>IUzl zHZNAQCSnJwN|mY_ye%eA*@LPYytM`@5X@dx4aEG{9#VEkH3uGC)lLvkfzutAUd9US z41au}A7g`FTMR=(yPbj?G>4YI(jeV~# z9Q&W$g1W&0z3pyep<_R@8~dHrO$_K69<28>2*X$wHTj(jMqxI-|Nr#KV(x@?oT=nALn=Pi1O`9|Vlj<>3uZwSA0aN_P zjTkd&(1b~2vkQ4_f3biRnx?3DET+pN9EXrOOd3^O=*LE9G5rAxGPz#;T<;ICp@7AJ zuzpZIEFEPRkh&i$7(MHZH>*cwd+oB%&_YG=Vct`Cqxa;zZ13cl*Mn;qc^4OZ(OAdU z9b30*+!50hwuZ8?KGaKdva3{EjOxKT+1|TOB)63}nafCdRf|bo9?DK#=wOK^tR=O9 zj2zFuXYh}Q6|UMZLnBKVQs4Pm?=8T$1JnXmA_=v zETifa4w(oqxG38Ao}Qa6-4kxEbgv|J54gjmdnc*8J*oTaTz`G5VpEP6wK*+K<}`m^ zZ{X9Usw|n8z0vDc;=Sq=d((Tj>CnDqSF>_e(_F7c%zJxo%)7yj zVM(fX#~o+>dLLqus0ZA)BP*KXuv8tj7HrmWfx}pzihkX=ov z2w_CoffoKt{36rNzFV4XVNH7gU$+m!yYM0GgLKOniA4Vm`ygHZ_nQZC8lwp?B*9Z=f9oV#_#-jLX$}SB*#S=V zcnsrqG+YGkx8fa(IMvGyj+QVAFk5%Uljsb_u{?0vWTPlG|H(cwUcB`s+i( z!6WlyvNPdq8h9Pr@yrb{u&9Eo8QZEwjSY^%kpfwQ{cC0 zn8U0NjuWFtn+>}FaxlMeA-_WK^TPzLWPS_bw`t&Y)*!!!>CtAx=0XnUR}c9yA=`!L zjIG}?UyZ;1HV`NO3-%yFW%Db6|DgOP`0dL4&_v1nu7{s#+QV^c*ad4}*vyV-Kd!0tKoPsP4N$q8q5;g}!uXPLqLHs$%}7Sv|5`B~XAsQ-7^ z2Z5P@z-C*;SN$jKgRo859{$D_uiAc(eGuC8V4LuoQO!OGM_|>>gP`~M*SHW)O7?r& zqu{Y6f6YEf8-+75gk!7V&ZMWpRi2 zuJ{*`FMgSCxwv1n_CXFuLovLMc(yo_MEi{u3rTd)$qJt-d5+{OBwsCgh2*u8%^EsL ze~0Az75<3iXC(8D0PDji`7G}p$sbGpoA`GT<8Bi_N+P~l69?%VOEzoZK;K1jPjQfF z*0@3V6v=!}&U`KB0@|0T( zC{BD+f0Ff=9FyEe@^O++kZit1MSMP)VEQu@ewJiDnc#68DNay$k-}$6UMQK5#2CLs zOh|v5Xx5fNIS(qFi_tT_d4d7`Ym(m(KPI8)V<_?)u|nZLiYd6vFq~gR&`!+ZB=##N zeJjcBC7(#5Ts|Zs&y@Zwailm-;S{qMJjEZYcxLSr z#G5Jo9K~BKx%yfsw@81l_^|jmiFSWVd|CQGOMXu@YnY%uUn|_KT>_Z{W~L8|wZ(d3 zLlX6DNg{r0$(!g7J*O4{(O$OT>lZ<>GZ>sklbm zAl@RH`#th|Nb;Y=mqot)XSpAUe-ZbH<>J@k_oBJ~Bc03pCs;$YYvUa*xuMuxY$YBm zwimmKxngheOz|A?JdvLVvfMw2GsW2=UvD$~YH^vkO02#H-ow&ACelC%)6=L6`HuL3 z$X9vP?-u_iek1-M{v@X9KASF9U-Rw=>05|xMKj(&Ib9{^iao^B#52W#;&5?<$hRV_ zFW-WYX8ZxpkUUp3;}GcoDET^Zg}6q%LA+VKOWY(rEIuYaC(@z^%ik`(CGHf>cm?5R zyaN7J`u$?17}otfBGwVjxCQB&NH*ga$iKDb-KmP-L+mY@aShU&aSb?J`q3iaba8*C zh(+RTalTl6&AX-2^V=w}POlAQfaHW6t$gz_4{8Ic*JRs8e z0r$s@yFfGU0uPhEk=RUZCAJnjh@Hig#cpD6(TvNGuNjwt!=)c97K&5EB5{^DSG+>} zqqtNw<2K}L$7?r9f0wvPd_;U)d{%r>d|iA~{7~E_?h(tyZ^a7nXVHxBP@kyAN43QU zVq>wTXvTYpf1Kowq8ax=e~RSO#6IF+ahNzlq@@!c*FT7p#Tnuyq8Se&-qn(qi>t-k zM7!qQeUcv%w~BVnyH_N?F50#3K9OwKy8BA9UF)twvdeKF>XRbcweIY=(To=n-c;d7 ziNANvyVDi_3~{hHOdKVS6DNvO#fwF|_T3`Mi^V0PUHfjGTBNZmHu0?Qv6w@;V-slU9pkaOl%`&i=D+2MY|SWPsy~E%>4R`G$lrPjCg@K zMZ83uCte}`QCupn5Z8-0h_{P(i!@fo@}3f35?>YnEWRgxEPf`^ycyFU5M4YFr<@|z z66=T!#in8_v9*{Z9xu{h8uL3{93T!6&lN|Bw5Z1T)5Y21d~vaOwOA^y6z>)96JHWv z6+ad~6TcGoi523HVi>D{qTryH?)glI>b~FG{A_Jm&X-ctHHS*ciX18GeL#ve-== zA&wCjh?j{siMNW6h>we}i*JgbiC>5=Uf{5NyOvy2$<4)%Vi)lYae#Qfc!7AOc#T+n z4L8~iWO?t2`^8GJAzo52ys3DSc&d1=I7*x+UMk)o-YnX+(q54KnfQg6h6fWYFI{Xc zwiEk^{X`l%Wc-W8#p2cCS}`HsBW@9&673pgZ%KYv+#{BYKZrkxweSLi<<}8oVoR~3 z*hP$sy~VS{;bNgUQM_23BVH|*hzao~k(M4=pC`mu#U0`<@l){|alaVGOChF@hz-QX zVjD4AJX!1}o+%C#M~UOaVsWN;h4@EtjkrO)Tih%@AwDg>F1{)55BN<>FQ15^=e>LA+7CUA$X-SbR);Mtnhh zO?*TAK>UliTPzd56Ay@7e2?uD7Bj`e#71H>@o2HF*j3CGdx)or{l&rJaB+lqzIcH+ zO}t2)CtfOEC0;8o7gvinh&PLOi<`wq#K*&1=Yo#MUXL*k#r7sOY@_r#sz7vfjqcj5stwSoGR*idXL z(o8Sgud_%yy_EZjL&bB%(c*YdQX z{vV074orEU_@l@d71Yx}FnO3rJHeEX67$7gBFzUge41DyE)!`knBh-|v>Hr#hxj+~ z8#>5NS`C@@(-^@e1);ajCdkTrX}EZxd;cnECxld`5gh{8;=< z{JZEj^3$~wbHua7bH$6rIU+3_v%H%`8ak%@p!k;fu1NdG3=iR>HZmr*6lw05`ZGmZ zJ*GTLoF`r?(ik$s?-pMXUl(Z_nc)XS+C!!s6=@Hd@)2SiF1snN0b8k(QGwe7MbDo#13L-kp`C;K2oH)Wy*6! z+E=E$M5LKz${WQy#e2mU#8<>G#IHnJXJ+~aB5gBMZX?ndGv$*-+GM8OUpz}3E*6P1 z#O2~@k*1uP{u%LQ@ilR`SSHfYGvjB7wCqf|xkv-glskzhiKmL^ilao@foA+aiZu01 zd4ouc&y+Wd4~vh9?~5Oa;g}ykB4&z*iEYK>#D3x+akMyIoFrZ-UMH4{kBE`W5N{G`SDN7uiqDBJiL@Zi@DIg3 zV!8N(_>)-cNI!lZk(Q&G{ur@~c#?Rwc&>P#cRYR;yUqq5s$%`l{yTp^-!2aQxf!)93I_7je9;+tV zEvHjXPUjAtIv(FO7He;m{@8=+@84e^C4 z)(G!+)21fz?DZL??bg;`;+_!AZ<~Kp_h<=L-1+*Pg&FJWZ@9mE-q&9*=n#*t%G?lL zadf=?vdofZc&a?LM&JAf%i1L} z*8R|;4Oxlr8(dnMR&X6eTA zMIo=ehxb*Z)bfR)wN5mr*7Dk=^_JFM8D5fK*uNq&d}l@O{FDt|$u*y&$D=iljXUep zkbCX;()il=+ZE2%cd*LOw#x9GLo334pR0_z*uy*L6h2nyE_aqeSKzLDsWRH)xyl;u z(2B@5?!UACVXRHHt+K|Qx9p3iBCU&bEz`(a6eLOJ1!wX49(`S=XnmuDL!`5;lD)R+z!QH2e8V zr^Wcf>kHXu(3d9eL9cSym!j^;;eEBkThX)pz7$#&S)IBrlHYf8^LVXw=tma}t_Yv) zp70z}?#G_LF^heO{byItUhx|H!Zn`XQGY|m+6L>R>t;0hxslT@Tz*Ab&z%i7Jcn~+ z6IM0LDj89>sz%T4DXT*(yZ+04Jd{XTmxeyR5q&)CkbOMW^zq2PpS!Y#xAp9cI;QOl zr#-pDiREo+!4i8GCe~zu#lM~O{aKCe8JTLz9 z{-1u1l!v1y?a5jlU7NB#QobPCuxT{z6t*s$U+KC}XLc{^7DAoc+B)sq(P~fDx+r2U ziXPiEWqtR;A=o3v=l(o($o=?oNBSP~O^dmPnnF z7Ye79LkhX6|A)Lcfsdj}*Z;e^I-MqIAnXVM!zu`bRX~gwLelK}zNmnJfb0YX1QHS1 zbex2+gtZYFMR8@&anw-;xeh8QI4-y_Iu0U>IxH?h9Q{4dsi(S&s2`oVGxz_w_g|l! zeBbx%b?Q{rsp?bj!Pp-NnK?lIg!M@6_a`PHr+}HR({3EY0|^fUfe$ISzs2|@me6M~ zb0invKu8$`9TObH0|^~9ipoAFP6gHq>oL~I5rc@MI(vNu3{ zp6a^{&0%PHxa7$UjWBc`)n^&ng`sa!9YwV(L%*cT313z>s+7WQsP<#zE2v&cwLjId zR8y!9pt=Q;S(a%awdYWGvnYrk2WBk(SETJ@{E<#J7hB+#- zj5;2_V};?QZl#(MQ(uK@mUJ4*Hsfz!W=SWbjSN%63Q0!WPK}E=8SMx(u9q~7`^oi^ zjF5`oXb^z1jQUtPs87b!Utu&7?h{j6q84F(yKW8V5j;zkle8SQGhVlcC&ko6yqyj= zqdI~;h6@OnKZcn)JjN+je}69i_X`v*%L}Ghef@KgUj?fnqd&#+tcpa%7X0@({=ut) z)u3FZWV>9=a)W{uto~LCr&YvPC$ZzJlLWjAm?V_LMNI;u(dL@z_vC z@ua;gwkzz1Yv5RYGKhR&eu=1IvYZo$QsC!m@aG+II2;zI2t+B+xCQ))?~FK-@S8H{ z&yP~zp1|%3ca;0Wl1Nq*-b5QC4&_wFIdCR(3hdp;oY)G-lqCB$youfNCfU!+&^l;+ zED}>U)^&r@SIVm2ci^Sbd*q( z!a+v~M=9_=2K$~VQ3{{J;lw=+eB+1&tQ#=O{3wOmrgi&v03LKif)@rv2}CJ8#;BVX@;+Y%yYAVmlm`P{@t)cFtMC$dE|F@x!tY z0b|X&qN9YO6jB`}9HqdkJffvUDYS*Nd;>X0ILnBAiJov~7b!R$rSHuUIh7YxCbq(v zU8L}!qlBUqb~#EoN`bd!L`#WM;LKgr^$p-Jjz}DbGlfy`<9H(q;q<;C@g6sXz0EN^ z)0Y?yXR1KqI!6gbIepgYetqwQ$i8Mef!ooH!t;!$7mDJ^^^qff3Vh>;#J6xJ{}l8s z&RRumqA8s5=S)?n-}ObmFdO?FyBp3AVwVy75l#o3G2hbxXUy?*z!|xw1Ac_4SPx}- zlmdGmF5tv>MjS>s9dK^I(*cLEA3A6H$es}Un{GCMV1L9uA6@t=go>uO3?^#B!6aum zN}-|S-yX;`;!wiri#YKpa2$#gjD7AboXL{C4if7~I2{nXNWtlV*u{7U#4fS}ro)+C zq`>hAl6M3mMjS{u9S~ia0xwA(cRMNK zv#;`6Y2s60pM^3f8t=S=a1hPL7G}fh6lcpIzrzcE{A_envCIE>*9*Ek;GV;#cBNX= zIiUv-JZ(*sf3~GQMna4h2%f_x4+@;B4u66TWc=Nhfxo01mr6GdyDA&gn-BE>D&xjsyRb)jz2vR#Jj3DfAeW08iGrZFq0YP zf9)t=E3=aYv1W9jUr~S!#!lo-OT86b>cweink;5H8P$!pMGQ8zTMM_fd3EB2$(tkf zW2Uu-7X?NX1!%jI_q?Fb(SI&2KkRX9{Bv=~n7GbSb>s3ry%!Fr55el-@x$(M~^v=~gmWbbIb03f;5isco5p9h)GM;=e?*vZr!ETv6 zN4CNxU=2K2>!#@3^o9{{!J&f0U*Is-u%f($eF4W5Fx5>Faq!oVaPDYW>Wz(@WNI*! z;H?Q`N-NqF0;_~86I(Xohy+{2#y4+Ko_}?5exb#Q%i(aH^DfXekT;pGCQ3iTxyhhZ zo~p~>5`1&GI~1ME;4p&UNn>}2J#c1scxgNg#}wEdibvtFJH&A~+-9sO&+i&=FoH<% z%BM0Y)^|b(UIf&b?)gdk?>sMgy`r&X_uTXQT19!z@ob_$TasIRO zh}zv{6YPJu#|DD4v7#gu z-f2SgC=B6F$~y6q7x$sI3J&QB4hm!GsqA#Z2tJI&!l=9f7te_`Wz)xfP`uejqGhjx z3*pODT8vJOQX2(V%NSheg*D6I*G`SH*?Hr@QG3k15I743X9B?vW&GK&{0IyF1Ur=RcXwbCgnT%3 zc7pG>5PsD3Am;`@$UVfypN-1KGYSQ^miMUfP!*UA2M~NpP0~@DiT$L`gNK9S9z#Z@JX>IKc#uuPMqs zv_?U_%+?qGhr@BdNM6Hn?6GRwT=YF^*TH$N$EGWq+?mvDsrZkBhzz^$@?UNK ztJ@6!E$WtCKFuJ-F^PD+(ds%Oj@Jwa4V-w_I%wi}j&ZbE4(d6W=b&7=F;+SB3VSZh zR;IUT+M;gl7Ac&g!*k$|;tV>(jW76#!Y4-RuyIOkhnr3HgX9rrc=B-Ti%Q;odbr3eV+zD|i zI8*g>Fvp;UiJ%ZCO>25J@nm_Kk!L&kmT@rGz@&Dn(ASq!#)l(n=;y&VbgRc3eC0Wb~nvmCOwu< z<4!qtd8grTOtb5yAw1o_HXTw+dw9CtDy_cVJk7p$L9V^XpUy+~;(`oDS%g>V>@Uej zo!t*PJ6_#sy$KoitFY@?KEs{?dzHq@>8y0SY&s8Jy)>FN9qojsp~Kln@NB#WCQVQJ zGWy!Pt#o_)g6{T7Kgv04&n~d5r`gCad67N)El2j#bfshauaup?8Esp`)T7rVBkcQK z->cKWuGbG3)VXucfB_!Ekr!EGl#xkeL9lHbWHNr@%vrhJrj8vq$CHG=mi;S+Bx5!y zZ4oSFV;Xkb9#3{@5t%jzfXVJ8;ykx z=+?W-pq`!j`&?6$fNsNcuJ6@t0D5odu8tj3V?^|4Y_?u}Pnj}q%B*oXBXURQ&Ytz7Hy-1u z@R+^RmT`Nh7nwfA4x5wXe~&3m^E>1B*znWW{Bq&4m~|B2IQqycSATJtJ3>nmmj;(5 zEDx-(@AThobt=bK*m&5THFrwx=rLgKOotO(DR0@Tia;#_4Gd*U| z)pIER_Z!!&iRNIN@CO)fZ5+h@J0m^J7ljYwVYFhl((z2YB80!?^G(yw#cP2$rOWk> z8r`uaf1blH+Oe&D6DNO6dpF}x#$$Qrhvir-pD!PMpubxQ_`CJ%0oj{hCh|Lton(G& z12?}Bo-`1BucMGN6tubdO@Z#p40-{X_o%2yp0J6Kz2&w@$9qQ1T41^KcgvmcNdwVW z4#Vv<3fkPV=0Nx6H>xvUZo!ZF;TP&ye!qt7rh(|=yl%#GH#h7~czE-h?#U0oZO8Jv z2eO-nd2~d6>F&Yugl&TC%`YGM@i?)5mHujmP>gtf){Fpz>^yc^N<<1Yr@HU&9pR2p{`u{s@aI#+UEnsZ% zHgy{Zt;BFXuRB{zFsdE9syLyx=>dug*cY`db@tr&X8YLl;+t)Hj#sZ>>cjSOHnw1V zvrUV7b|3(70-$#;&&onh_ZZRLkz4Y-PjC+-d1`i62~D&G`7OfB?c(`S`zvg z>64|;kZx>*Av|CD3WXaRVJK&v^vw$2F8yKYzmxu~^cSVSBAwH{SpK`xk4iT-!Qjsm zo8f$X=l+(LURgR{05iOq*h>C<2~7V^(tAknE1fgo7(PL~SzIix6#26P<2_8G{NG9E zD>>>fN;fvWpuZ{oU4Fl;8a6x)lu9y4A<>@M~b2Z`5A^u+6E$$V~ zd4>4zNdK$&vB-Iq-0$T2lWh8+)92$#71-B(p^R;zGTTXl(I9A1mFQ zZ_sB*pDivF7m0U@zZSQM+r)>&$3$~pBHw4E?-lonuZd>rEaJT{{X@~%?1ld+>3pZo z{V+Cs!SAKpJRhNR0s~o2bkEls((8x~#HL~k(b)J!`m3d9i(SRO;y|&q&Al7tf0H;* zTqrIPSBOR8T5+?uRoo#yDn2Lf5nmBs6ZwM{_y2wIWATJ|R{To*UbJxmGwmmG>KJv` zw%#Su>xvD!Si`R;y#R=kM(Y392i}ZYvKVdMRJH=m%YsB@U zu_=sr_e+07^{4?=C zZDTJZ(K#NOVmGmuI9MDmy0-Ohlze-aOhZ-__4zlz7jPsMZM*CHSL*dJXR&B@Zsi&e!MVm>6pxDhpo8u6 zwfLP#d)4$$7R!rOMc39IzW`ypW?~z$y?Bk-SuAa1Z6Q2~H7WtJB^Lt(VNIWK%wwafJ2R_CxBc_Oz#adz=v60wR zY%R7EJBnFiH?fzaY$7%n+ln1T*EU~{^xk5B@mg`T zI6<5&&KBp2`Ql>nS7M=9EN&D_+x&Y>{=39y#OK9*;(pP!1^Bk~zla}+r^LUD--zFd zuC2f_c(=xOOA#xJrELf{m46G-wIz6!^lY)K*hl0CKFt3*af~=ooFdK<=ZlNQWnzK2 zO57-J5g!wGiO-17i~Gd=;-AI0#Sg^4i6_O+#nLto19+#y{R)ZY#Y$qTm?mB(HW6Ei zZN;m_PGUE)mpD)yD!R54$4Q?e&JgE{3q*ct$odwF#o|Ws0r6q+8S#1XfOtqeEWR(g zwirK?{)Jc~Cg4RE%P%8V6Kjh6^pW9Lh@HhQ;v{jZI8R(C-XSg*9~K`MpBA4JUE7T> zNq=2@OFSa}RphsrtlwASKSZm7}_;zDt$c&E5hTq8av?h>C7pBG;gUl!jL{~~@Yo)FK9Uy1xWmHU${RuWy?kPW0a z7Ww%q<7bF?3^8kypqY(7V2H^9jOv#vR8W!#q)SarqWa+_xP zYGl{SPFQKL?sM8#24DN=^)9_(qc{h9`pUt>|M6(o^6|Ba$Jyz&N zM6#RWpT9w0{`V)`$7udUu7G0SLa%lc`9F}r_u#g9so(xqsRy%;ppOd z$N3K59*qF|iX6t7NU_s(6!{Uqoi&{zuDkehei8noTIOw|70O32zMD7ehy((^VOS`T zjFJ=h-8^3f2UjDCFUT+L^Josxw=lR2{}%-BfY1Ek6^MIl@B{eF^Cf-`FMKzD5?W#u z{{nf|2FklBFE-!JCyrp8<<_(C3I#4l0cETmkgYDJG)QJvHfbf@!2ex)BNCe|c^cJj zkMn=OB({>(onccUC2=JWs|Ul@Q>_Dkt0zMbQGEmdtX>TL2UWfzwR%%+j2Pi2O#88) zu?JD-8%gV!(bqzEK70Sfp9Pr_;=$8-fzT%?l2~hTfkpjVp|JH_&AW@q-K1$+LtUg@`Ao3k0hcHP7Z}UXJT7JNcbR{U~K0T zYD$cZ0Q`?_DUdMBnP4gWS_^QK4T#2*4S|1bQ_V~oM&VZ`Zd871>)jML;AV`t0Z&}E zO>9%#kSA`)6BkeB&c^P;7W&s4iaGq!hGI!saNZA#sOQ3!{s^f${O*Rce1q}dY;JN+ z`)0Dc;81ZV(1~4evDbX4i;UL*H`Y`LEHBB2FR`xqx^cs=<6ktS!ryNq#v7Bz+TECT zCLGfW31+SPQNhhY`@MPN?MD*Ea~f|jJ=n{h zw+M5_?P&#erpclV6zgh%l4xAvcG7mtyXKFo;@q~ z|Mmpi_|$04ruEEFjrr*X&b?0_FGoe{ld?N6_GF_WfdDP)zlXGL8-w0{~?@V)dl5l)^`gr}^iNybl z=grplT#9)m&MKF-ICMwilHk&WWr5}P3jdv$HQOEm|ID1(pO`O;6E=P3xXI~b$BmhN zW$+x9oI?oL!ZeLr;c-T#C%>~`VG^j zOc{r6la51{J~}sd=EO0xb1%+i{LIl)#(CP{=fs+bfH9(()5W-L_|LOBcfo)Ed|3{& zOPA}tbGrB49*XBy=^%t*Zlye7T_EFid2DNgXVDgjR~0^dcwv4V>~PS3j)B=9YFAV3_kMmpIG!T9K4RgB3!xh&d z%$r~RYR-N#KaK$1{2qYJG%Sl-5RJh#4c(1lbh|`1UN5|ZpW#MQ7~^pcACgaZgPudY zD_sR-9Bzl;T$y?a;_-BMH`b5a0XXk|G{t_Tz>oV;3C`V*3Xnb3_O(Ex{RMvR=9Wcz zx`*!|GUI2N$QJW3o&1#INZ#|K;Hn)lDFP0woR{B%Y z_elSf^h46$lKxleG)uw#IwRe}3Ca4Hd8=S8>2*oOGxJvAZ|1GyI$>U*!9Pp!_{N0s z`b$SMUi2Q5*H7+0`!QKvOchOkfqx6>?Zm6Z&LZz!Oy5T|{Rg_~KOkSPF`Q4G&4CDZ^Q@0$3$L(neI7pk7)WA{NI#*MEt9GLi|kphiI|=k*?c12>KmXpneHIG)k@xPa9t#(S zH`QJjDwbVMTa#=DDGZ zDi+@kd)irxDy$C_CS})!?cCIL0oc~AoKNexb+UbzrxYa>2F_UFE!o!|N!oCvBxTF~ zQ+6_}P(OC0B=xcDPi};L?ayu-9_bwE8u8UxdES>O6DsyPd^$~=Os(9WSnZNVNotY=?%*e@vNZN(qx(z!!pA2-acOf{d z@VsyOHq%1&F9eqrp0|9@@9c8Y*X6Pc!6z%CohqKUA1W;I?|yh^&dDUU;JV8$B(&@E z&0XgfBbA*EpJjz5_LfV(x&1<)Z&rNK<7A*mlM4wq`8QctTW12+R-G4 zZyFz|ki9qZRAflxv&YM3+pA#ykI|5@q%wz#S4M`_WHuCPYwk(mVw3PJ||CH(&yyy>SfL)mI<9p3@wJ;@Wmxo zexH+{rov8lrSQ4LuzfDkUX1$xZF-ejfi_nAGOGit5(@IZ81-nSbxG^*#IHz6D-+k( z$WGZ<8Amx`)$oI%O~K-%b+E;qwB^(aUuyPCHHssBPOeA}6!=%!g|Nw8Cb+IrWMIUX z#(swO8&!1P+FjwiHUD9>a?Z(cPUK`_q``%tujstLZ-w*z$wlXFgxfy|w=(WQ3)!Zx z4bT2P`ccxszy|-RG6^_lJPos^d&)wB<-i*Zc>v(Jzd( z?mh>{L`MAE&zLaIm>oD{V88oE&zP4g@C->Rv1vR#*DKlgEk^{JccW;e*L6WLHBv@vNl zW26-EyngjV}tCZ)fGOeSbX~Nlug*v&G<#F9`=&G zEsWHe*vquk3%=8pFZi`*XOY9EtVHB+@=((Hlyyny-=~k+5tf)z{Np8}FJ;xpK7A+w zrM-LXcX%GeZ4O(&;xB&IHi%7eI zPslJx{DJ|rQE0atPoF?S75dylx&0jDllU!)vqK3NsD%;>5bpl48AvpraPYnuXxte8 z{fUShxFU<i8Vz)e7cm7w1@IiB+c z`E@~F@NWEH7~~fW3xfR4Xnycg1l}5)2^qg{wq!#6zR6$s66QI-Z}L$xA9HLuY8OlLd*+fR}#?Vt#7g6ob z&}wMkvQ_ZU>Or+Lq;mXR!y3TI)2OzjI*{sSszppYi0T2T<)_bq6>(~hfO=C*{f6p0RIg`0y&TW= z6$V213sQc>JPy^ufvLzxz^f5faVCVm6vji?2%(Z2vob$#JPse_@Ers{ysQtdcXME< z$>D;VLzh(K;KnpL6v4;&6xFvB>B{{Instt?aUVj;@f$2h{XHXAWnGW5VEXs9UUZ9k z522>0&mmM}Wh=SSOfjQtA+?kIa|E7c@?jRg05SWTi(r#{DFr6~20|q_s>z~y?N}Dy zA_6am))>otxXb2hf?$(HM+(g1aR`;%s3wcO@hoVOj}I8uRO{DnE#7vs;Obc>3od_E z$&G5V*v{*YvmY&TZmTS=8m1lE zBeF@}g94Lpg;2?j>P^n4aAV(at;G*CO!Cj%x)|KYr`Z((kqSJ%&j> zo2l62mbuA4U~)IAl2_sN{t2YH#PpRvnJZz%-(oBT#0X7gCgmrcy#SWHLX!I-9>cE=gpn`iA87C)UZ zySN9TW*6V2zy_{U54-3_HHUZ#e3Zo`B%jJGEdS$f77R970%3}?;v*TwDL)VCKxO<|)bu&{?9RC1%5`j)^) zS+oc^pW|CA{Nvm#7;LggZlElNK&a$KHCfyXA6R!Bh2-PmijdYh8c|c{ClTx%T}OY3 z(QD4ZKPOfP6YEqgmZM+ZkeU9(3>xpW89To6!oNO)#>|sR;QX1iWG=42sWX}lgANy; zDTDWTKRMl|?8Vb<$|;p*-;~$<8mTF96_?;zSd4)acZMbpGsR=&g_dSkPNif_A*zT2 zSGkRRs&HZst60^O$gCw%jfv1j7!z$9uQaFk)NnFl!kWKeY7a*uSk~dRIR@@O9uds^ zAlkygIN(EO5rs_0pWs)7&gu)4?t(M1D0EG5gD7=}LtX?g!X_347W~8I8*rmX?0y6X zWiZ=Fbb!NjolG(l4wHk3MJSBkr1`4Rw;kL6Lwgo8i9 zoihIJ-f{7by!h@7a(B-}LW0<)W-&Q1J|{hy9dgB$opspFgChCFdY zp18OeI9nz#&#C=Gv34>|>$Z(i6x;0cL+JSM+?GevmuyU8|DI6?tIzIKRD0P0?YD}fVw{Dc$cW^=22WBeD zHL&k2i>&K(D5AZ*$xP!tC>u~qJ(cJ7KPF|X4Tm#zqc9#0EksOp{V6Pl3&FZJ%0~UD z-3=FXe4>p`)2y16hh|6&J08;RE5J?N7Oaq0D_Oawr^HmltLTFpYN~P zDG;0BGpWgv!iz?kkr$mC2c0QP-k`6}QTI37uGC}G-xLI+0)L@9KILwsVO5eE?0!I`F|Fw^lT zc*eteFHe?Lj_95w$m2QqybfmyItzh)9sae^1=zpQM;^*^JGW7?;mcl)NbJ!49ntN> z@MRCa84g)m(G?KbBjHc%a{T?#{SXd1{)E##owLpDo=C#Zc^uAU^(_S6HQG3I{vWu;>jT+wmtR7;z|nM_FaW ze#Ap?Xo2l{?0-&|o4L?*xxwfbsN(!6h3nu@#W}zVBMv8=UN+A%y^MxlaINxO|F*-< zrrV!pEHwQo7ar)B^P?1;{?w1pumy0~6~gIHvnk-i zHR^UL6Fm(_(7ARFb-Pp<-dlpOm0j1Y0pWD4ex57k_B^+1nJn13*r#ClJkNBl0w^$e zOt6EQNEFz?(0mI`PkS8-PHRFJzU_Gw*rlARwoHw>{mW#5o@6#Q=MPUHH;&{ML;fnjsZ|JqUaj>+8JYfQyh?zt+Zc9hqiMQ|yY zSi^GTA?_8Zek|1tH`PqbsoIP@Rk3cA*Q&j6X_)rRd}49uJ8C>8yAm%`KfbRF`2wz@ z>f>z(G`iV%ZQ*5w`$n4A624))h&UIEVLuhqyovD*A@H@t7lj zDkiUUmTv@M-ZuCKGtqj-mlrjsdL!KQdmwxSS3TCmN#B28!)@Kn`gNiV<@f+G{7ze& z7`7ubhC6ydjD?;UYH!9kj`Szt!WhpmbuPL{o#2MHJGJ-$g~XQU;;5bEj7#2QViv?2#Dcnsac+ua_;~?eLQ$u;Gp8Cj|W3}x%%nj z@x!Bk(LQK9nWKW47br9v)A|JYU%2@N$cH4*eyh&B@cy zZh4-Dc4N5>9cxuKGcQPq_{q(*s(W=x#I^Bfo7t_RrX<9W=pSO-3<_|ZK` zCqG&fbT-yQ`Q>@?Tj0qr7MDZIC*cxsMq?EtihJO&zz<=5=fc8@h#r8$`h|IB{Xm`_ zI64HsIc|`r^DG2J}=$!QmhiW8q9h3R4|_ zf=vMbXU!wnRCHOCLrjM=j~Nu42e5$zdp7oiW8jl;T0@Bj;%f$c1aPT6Qz@g^^f-~@jjLJMzGrq18ca0T~`%o+ARDj@fZ9I@# zx)VrnXX1g}B_4yg4~jEeKAL(l92%l;5T_00&2Z?EgmWYcN0NL+gHj>+kDVIaumEn*VQJpHgf1&ciYF18O3}IyukzKj1BNFZ5l1&>(ZLBPoKv{4uiM{QENWx6f%tzN9Cwc#1&3zMGz(c#84HKz#DBAK7v{s^u)AJ+ zAbbRecOqV|FxnO)Ved1Q#v2^7GnC^n#0bPk;6C~sAWF+ZNy zObuli!_AA;bnbbvs?tkU^*lVx@+9_D)${P+eL(bPuc~@t&h$JedaCLvZKkJT+`L## z=QbRxYBs!_-Wv1bJvaj{0fYZ`4Wkqp%X27>LOpK0Vy`afRnE^?gNcfC_)R0TzWauV z57c#{^yiQQ%^IuU#WCCg2V%tbai-^R#v7hB;K&$vWp@YZ^_8jE5Uy4Z7;4^64Z{yEB0Q9UjM^&Ws!UY z!U&t-2-bMc;U>pRGYKlQvHKo|AE4p?Z2rJS>aM0gMwpt=k`}Vgq1p& z^!g9fgW2*q&wcs#OI{1QwR{@szJc>xx%fP`6E49wmls`%jOB^32da}Oc9D2J<`sL# z`y#wvhU4QE@}bCB7>K)tzYF!O@rqr4=*6rPe77=@8#5ilNWKv8+?VN<3x}6po|~}u z#Ti5OTFi6Ro)Np2$NN6>(koC;Ufz44=M|{u)b-v+-Kw&hQ{g;SrI)Jexh?*4Z}7a? z|99Wkx_NQlne(U>8|@Usi-yz_@ZuTmPm!@aJM#t9%4UcZyG_%pBfNfkJj77FJMHQT^>#tZaPRXvBodmKGg^^9`7eZg%$=B287 zV#db`bz;AwV+7$TEk53e_dr(Dd1#NdDreYDhV#^(Pwe~=OyePnjOB@O94a53@YAsS zXoS0aK8DGB#DVV~fKMn8&jKZm=u|G6pl6Bl|0Ll(igKR0>9_>{z- zwHn4=UE{@} z?tZ31z*Pnt+DaRrmEEm91|S@5X2NmA>28l85if{O!aeO|V1m4U&w2daYv8N!~^T(Fey%DnAk^f3Bt4rO|GP)U*?b>Mua~xdjte#rd zfx-qkVPzep7_?!kMt1LXJ7bYOH`flQwQk(Haf6zz1AhAve>yULZ$Wz8Ym4#Phox8> zZtmqSuA6R0((DfDEt~YSpU11n*L?-U`)h61vT3$iT(@=Ty4JT`Y0pi&)J}GaukKWP zp0OL%(A0gNQ=@?2XpdMZ-AL~(OqbtptPJ@bjrnb~hRW}B%&#Ekw=~abf?QLM9d>g% z?{jlnm)Bjne}c&*PKi+`RT~AohfAUp@L*p0HoI$qeE>J#+1)R1)uMiTv+izchFvDj zetTh>y~RqyTDZ-cH#h(7BMUR^C#-#;d9|>nZoD0nuy0LcY7;c`O<319*PfYSSIE%P zyIs=kE7L~U*%|gfP@2}>9cs_U+Pi6X($n_b@fRJf+w*v|mRO#n^(7j_vd>{kM8nO! zBlRz5!knRY$MjbAb2v~h`<%sim*g$F%)Wm?ntgv>`epXVSSR<)0%sN8^?uWOp(}VC zt}zD#t3e-~U%)kZN0=3Nd3en-yg1Y;X>E*enmxm;!;7_gzsIt{1z39+(f+~Jc;8&u z-G0L!YEK=HLb}`Q{oQZ9#zvlJ7CZ!H=xb66+>mt4=CiDs<7UmCoa-!e>#TL^80dm! zruJA`_lI_oJO-EIHk@X;CZIgalE#yIm-GFhK`M`JFUNqCSsvEAk$92nd5!-q7{9AdQD=PH;Ws;i{((tyqbw&nm88YA_I2LYSXc>i>&mO zS~(kPYZyl8+_^(qBOafD)22#-{b1IqimVvt~`3IjeD6 zoAmbSZPHq`XxXMkyH;1EHG;*iaieFAYn(O$Nt%ySl4fnLZ{KVTY;fH$Aq}RxCeE5T zZE9MpmaSX1X?Lx!Q+wQKM~@pl2KHFfAtrQ2CmJ`WS+6#}VA;f8W&BCOih;^j6|0(E z-MYl8Vb!!#t=j&&7~Syu0PniK^`W~P$3s7ApKLl}{2T0(wewmW``>Av%&dpWVXZsl zZR0kc=nhHiKxaIRnaox?9>cg@2FLmTKNqhl;*>7eJATD@%xv8iPpYpyD$4a!+|4aF z0uOw38rw#8!HjBrNmUg-940eACL0Xrrh(`?hc8G+csyKjLaBJYQ}Betozv#V8w=fA zZclvJ$?v>aF3WSvA8?R>s83fkPTSUAr!C#gKsP^+ zml3`G{|@_P)h;T)Z57A!f5JW)K5I7Z?UcwCk8i)kJ{i9DHEqRf#!uKMrEpvWKmsPp$pvby+l_Q{N$D8zT|jjdC}q|?9x^|z&SW(DFRSUFA$AvsihTLZ@L44C3W$^Tn10hb$=n?xd>yG~{``PY?yL-7jv^Mx$abrE|ioKu*X z&oKFqB4Ku8B8hsM^)Hc*vxcZIQanyiV7dZvi~JuDe=GmriM!?hiuBjS59H7Hb*!IR z#}fQX;opch%3?UDLa^M5VqN(+5!;CFdX-lzUPS)=qz@9!`jp6*?`fI;Eh66;vK+oQ zB$ty2UnRX*+%Ese#izyR75;+wXYpd|B~dlm4#sqa^C-uG3f|e+vU5wqug$uE$u3 zI^w6w-(82XiTtmUf4105EWHln_3|H2BEL!EEE4rK>oB7H+oj)4LSIFq{nyEVoBSV; zzDqi8gC<{`j)olnvK)^4$m(LM*i7X3jNup(8)k?(VmHy;{}FGXbTi)w`WWdqiPOZn z;sSB8xJ)b*-F3$Am%c+Z;{xRWq;xYrfc{76FNp`lH$*dDK)es79~D0pPm5oR7sO=V zcae^^h)7P`Avs@`tRprMIcbOftwjEgLOoOLBK8mmibKUQ;&^e2I72LLZ}M*WuN2L= z1m(Hwjo&B#2gS$5C&cH(J)#+(ApL97-xAF@1^%a`yLKtRmJVZYW#mpjOdQb_DScj_}q^-#dpLH#iQaW@$Vvk@@G0uGbU}0YrsUY zoam0(ie$KM0b7g zBI)k>;G3np>x1u*zDs;cG~+;&`+{^c9)$j?^f$$K#E-;dqPsr$8R_4M--)zY#r7>D zRuL}|)5Q8>GqI(ZDQ1g3#6IFsailm-oG4Bgb47O?nJ0ajc$Zitt`+~?>w>?hd_NG6 zi6_O<>wF#>rcSv6@7KmoNigGtezen6IJ|zBDG`2huf4B6#;vw-(@gwn=_;>M~_>JhU z7hV=)XSQPnvAUQlHW1zQ!dppiE0$g-yu18+i$lZ_;y=4i_^*_%P~0lsCq67bF76ip z)pfx?SNgN!1@U_^h!^l|uOzXOSWT=g))gCz%|v(o@b=O>i8*3Vv9EZ&c!M}eoGQ|; zChK#%c&GSlagDfM+$!EDJ}f>iJ|#XY?iJnj$X}EGXYoDp1M$5053vfK$ymQj#Aaek z@k;S(agaDnoF>i^H;MO%e-d92KNe4j?t0>7@u0_gR1q%`)5Q8BEs-*wyN>uZ(mRXY z#opo|ahOQcrA$9r%oXQ|rPmRsZBxcyBW@PAiVuhni@U_9#M0}C(>N;gdrSO6ED@{X z8JgiW#P(u_SbClBvGRA<_ns$xp}0m|FYXkd6ictm{gM2SiQkI+;fVFBE!Gt?MR)yd zcYW;f@-Mv(_I>hyP^5KO=KF?tR{Tn=3>*CnuP(alO?Qw!R2(VJ6Bml^`p{dXKPT=H zKNOFOe!OU4c|ozh*hq|s-9?(SW&B+6c5$h=MqDpGAiC>2KP!E=_?q}<@gwn=_@#JW z3{`N-4~y=4&9$UoE~blDiPwmw*J&Ot|8ZijI7ckKF7tZ%Zx(6Km+kR;ai6$fd{6v9 z{9JU`U;bXYUD3&>qF7aIApX?4%RLm{N4!oPBTf@%iTUDUu~1wsZWZqnpAdg9?i2Tm z?};CXpNgl&??oFwr?H(XidDr1Vq=jOkr^*b>@M~e2aChSG2(b}syI`eD=rWhi_1jX zTxNM2#Cyg2#Ye^8iqDA8i!X{Vi-*KF#iQbJ@wE7bctQML3|4mPlO$FYtBSM(&H7$0 zwi4Tl9mOoMyVzT#hiZ_e%#6{u~@osUYxL({WJ|gZEpBA4JUld;!X{DO= z`HOf${7n2pED^sK?J7>Xu$UrN6KjeM#mmK(;uT`1m@W1a`-#_yW5kK#6!B(po_L#h zhj_QRQd}o)67Lfq6dxC#5T6xyi?4{UiEoMTihmV97C#ryis!|Dh#^caVEc!~N@6v! zuGmm)CbksYiy2~Pv5VMS>@N-%uM@|Mlf;?g%_7Z~vwkbYHR5{l9`QHg!{X!OQ{uDY zUU8rJn)qk&UGXpC$Kna`jQFMat;j{+SkFW;S*#}36zhqXiOt2<;#J}`VnpmN_7?|> z*NUUXiQ*KIcHUX9d~vCGr&ug*6dx2H5uX)zi+>Vd5#JGyh)2ca;#cA~A`Q*6K9$8Z zvA)Ut)VSb5XIkBQxQ@m8F7yfHL<41#TXbrUE~4`)H{h>hk^P)ai(~)$mJOrzD0aa+#_;128Mqsa#aTE z-;1^ILnZY(A{T3*-b0)yP7%3u1H;#fT(E)qgCbXKp#BGOpSWM-nhgy9K;+U5)X$3N z#eaxZFiDHymx%4et3S*7j>XMN95WL)bA8mifhD2#GT?n@ePqnLNNVzA{T_9 zo+@$$2#`X@xL9zlJd$mJrazbA6l2d%W@f`a<%;ydCI@q+lh*dWb` z-&kxfW{5q+KH^|;xHw0gFK!j@6CV~I7he(&h@XjPL@r{%`Uk{hvAoz!Y$*;AM~Jh< zxguA!V19RrMdDiV3Gw&h2jbtv^Ws0mnsuH0E)~wbU#23Xk#dpN7#S3DcdQN!_#Li+Dkqce0J~KqlgQmV%+$!ED?iUY= zpNnV3>h+!UsbUkcx!6JMDE1QjiChAM<&PB?iAzMTjKT27#8<`FMJ|NF@NdQB2991{ zY$mo8hlnG@x#9xxUh#gBt7I_$r^T1V1L9%veesm|ckwIn8_{a$0++9McgLt7Y~Y`il@b(59Q%E9K2pKP8R2g^Tm8|vA9gUODqsqiN)eZal81C zm}5EnfyeC9>xEv?HZ8uz)(dTyme#^}JO5j@XwkMUBDQLIWt;ZK|L4~WozN16;gblq z87yu1F2RiVW+zVfdHBmF3zilY751q8WOV7eCpOP0xFow{_T5=)uwH2Q#Y>Be)-B7* zJbUo=HN|U-k|HzK%_vw}yr!_IVChOLa(C9g=l^&rXcw)2V%_2Aef3sktttwH1eX*T5Q}Q&wi4OJ2No!)B}%`sMAbHcVN271kvEsz$?;$8KJ|W=ip{ z&1<4}`f6wU8ckkvRW{e^%RIL(|I)~w$SV=75Nb^-^qpRNd%4K;wO3+g%<6k~MUI>Z z-gw}I@5Y&r{^^8o$BbfMJ=jQ@5L#6$k~|@4)t1Nukryubm-mR2DLQf@bYs?pekFm7 z16W@YzBgjs$+^jE50nH7j+{tZz6fEV4F6ije*tp1>4B1zf~_d|0Ls{N!QPR$8PX1{ zQn=--YDjy_v#6iFCSh%#lP7QWok{WCb0)&hCDrdYM|Z?ir-H1*+0kNnpOU%j`GqEci^@#M`Td{+BNN#H79qbUWG*Cd_^ByuIj zYrdZJ=o8VU8?Q2Jl#aiBZt9FpWojmzy3JaO)(xJ??`&O_cc$}@p}XEH3G7ZSJWw*Zpw`N3imqPO zX?164C0h=ZoZfQeM8}*VC4r`abvXL>?73j&WIp&hjuZScT1`Oh@4<1mj-1G-$0O%2 zhJR|>>OWra)k`d{TadN=M74ux_d12}4=1jxyS{eO{tLbw*5RdUyC&2tJYFpgInOUB z`(?r0`l}lhbSdn%GN;JDs>f>d(|Zn-q}}rlj$LFsbJ>SIZhHt>VBQ!0M~{^3Dx7J~gOvPn zk;k)-pr`nn_d2*}V_=nkZ7R;L(2gb%|A#k3_C^jyd<}0{Il6GvgQM1Ph2Sx35+iJd zF%OPg1?CJd3H*NSntd0Nb5O^eHj%3%uUxQmnnV&e4PCweLb5gX;r-PH7ru!UXx%Nt zN&-6u7QGDrBh|RZ@bJRw5&woEtFWf*t^2E4SB+S8pk(ahgH{h-H+22*jsBuP9I6+& z`=PzKnoQo5AMNJL#Ig?~e0Ll#@0+?VYw z3wFz1U7T{-4*O0&cH7boGd51%gfrvuJ|~MpR@;PAcZIR;Z(`uol3<^cp-Xn03e`Yc z?+&fqg>zwO!GV%d`Q;%^*iwD-B(!(+-B)A%<0ORo>Nc7%er0l`&V&go3nJ?xI6BL_ zMQ$t{&t7!nK=jZFIId|c;g4&e|3-V=L|ltb%$>0PrD_LC>aRqs<<}N&pD?f_lsa-P zQ=fnw4j(9)Q@9e>H5}I+NQWz0cni|q%T+*hhXu0s2?=#qXyK<6N^O~Rc#q39YX_-6A;{N@I z8$rC4ou>_LAM-|0p9R+C8w zCvTjwDR63Ocv7@ctu2wV6EY?o!u=3e)5*&x_zUm25Xd=M4cEM$x3Bco-4R)d`%;-5 zi&j^TTpM{2*U*W+uBZvlwVk*k;Hq%y)(>+m^ySJs^Kn%OtmKCfZyc)d3GVd8PpsRu z-j3bv@AR!+vu1OR?8z%zoBMqD=&B98YaJ;$xQHWyt7>vg5IS{R$k$}`ngb<|-S+%f z>mQo2ZsXA-C6E2___1Il2dnem{>kcflZ)^2)r~A&_x;!3eb2CM+3y^iykT|mjE$3` z_Nn}E?MPa!@PsQTEH?GU{j%nG)R8qicWCc1q_}PMX7swk(5WR@@)_stZDq~`0?Q-s zl=wy+F7Zu&2kkKwSAAdIB^MHJtctUy%#91#e{UL>b5A6IxF-&6Ip%wQij6Ux8B+zU zNf_5zO`$wyJTCs{w}NT#@mrx65Z~`lFtcg>iJg$hrjb;CJ2OrVBpgLFyBf!c?Z+@h zAh9{){EBj~T>cLwY&A%n256C8M61ha&mecZQw{=b3%S}^LnzXCzujvhQw0(SBT7O5 zHA!Nzp#ZF9z&mg!yrFScanK4(v6A4OcpZ}X65oSgUgB*0Uzo^Qy9*LIXLx>MA^zW* z$obpzd?9{*6qs$jg#@8<2nZ~;I5H05t(q^e+`11a6R3)~Nme^VwK|&;;Ooo6L>q3_ z0Qe_!y1A9jN#xDomwX;sSveaZ-cPjxLn93Rn(Dm_?ZQyb8c#k4!RpFTeted^mTEVK zzE0JcUh7WvEY$E#Oxu%@D?$oSr`n5ZC#sx%ZS|(gfU;Z=w-2?AsAJjbSP-`_we5Jg z374>#epL5iPr~2D)H0Y6Q`RhqYu2awE7UNbhAgALf`L;Qb5^7d!nBBRN=*GLRs4da z&;m?eD9c4{&Ei7cF}0v97qvCoDx+ahTced24U5_uZ6tCmdxM*9CA4x_#&#eZp)8iM zH9{TyK#sbgD5LUs=kRASbu)f84KInQE%DeA=2U8H5D)JksPc<5N9AvU;khxj0)Dy) z_oF(P-6;!d`F$auj|VyhM$>cgzh9tm|H5F3)i+T1;R3Wy1&b5Dt*2O`RgtK;i2okP zKX_HJ8kDP)Y?rH9Zcwm-)!#}%5`TPQNZY$$q<59b^5|LU*#Rp#xkK_*W*NoAMn1b- zD%u&p&^gOOcEi4wVN421Ke7HJS5{2Ecm>F?mSEJ9k7eUaKEfi3kLyEniAj@d`Q?i& z>;xBXOj)rAhH8=uv(PUpIE8Ut$~NH)91VOW#!8qifd5>?k3{QHu21sB!K#1<@h~6X z>O+LNHli&Yto(klfI=o5422Q<@igu%y-4W|I1`J)lgQTzqVyCT@*+df*?NH}mG|Kgk+ZjNhKq$!Squj&%LK2O zFab$C@q4!Z&c(moywX&U(e7e1Rwh9x9Ku==Ern zZE&W&_d`G+l<9#e1%CGgC1lJNcXX6+ltRQ&Qlb?4!=a1K1eQ1=u@w%9=SL~*a{P}0 z{FoW%4ACCWEILS`w^0g@E*J%20vxJO(CD1mEeiZH21+POVXvcvqZIfp2trb#6vn_I z`E=l2BMu`@!ePO-`B4gWamj%}P@=sN`w^LN$YpwzLKYl4!SMyb%+x5AC2*)ZvBro) zh_~QO`%-w{Q9@A)yj3D39HmgzQBtB5>cZhLv;eXlkr)YQmQSR>k3|uM--tS$Z%8r3 z2OVExuMvk3C2*z+6xx_>H9Hig(AH7HQ3{!kk`kpb84me#Zv8?>B-X&0Dp1(&_{aP6 z5VsG*R4{vQ$n>&)L>SH-OA1vTB@`VBVI&;72f>bx23!QNbDLi0_H3hY208mRBJtdQ z))5Z^A37qz&Tfi23*jr{-2v z1zbh9LEQ_7-6Regu^$01mObBde$1HTIX`CPn)9Q(6K#5w0zV7H4)Oe0VZ_0NbAI4- zr9jIA=&<_$8WljfCI64THvx~b$lCs&?x(Ymgb-HQ39E<@Agn@Eh|o$z2w@A0vIvNX z8X*XV01;6mE&~V*vNbC1%OLtH_Yj(J`~w z936R>@xC_`{edt62`zAyln;!3@#Yc=JVvnUekkG&7EJ!lB|JOwfXOg38wPhIm_G0T zSc!xoCG4?KTpEcT3&peIj)mf4b1c+1^R>7rLZJl`_Xu!-5r+}>Sita5;3*ly;|>7R zGUxpkV;@4;LjWzu4gs_rI|R@&4*~uJ1+hwsA{03H(K0dLh{Fhb2%u#O4_muCU2ER+ zhs3566f%%7QXkDp?A$OyrCHR_yq zff;9+L&Y8+g`D+#xzWc-qtfYz0|?h!N=|*Iu+{(B0mds2ju3)J349%z^KTssx-Ix< zjyo}#Ev&S+4w!v7nE0OQP$)C@!Gt}X3~{Fu#2@6zWTPoi;4V|_77x>P<}e*Z z@aSX@0eit(yloBz{@@PnubaaQ7Joelk3>Tx*dLrjffp^rWg>WNV!y=>(Ly&f*eH)s z{savr2p*VdG%st5$PrYN2Xd~w% z;nGI%x5n5yVzUuP5nR~>+fY86g1ui^{NQW~T>Aq#ua;0)hXg+aPqjFbiMnPl}{nK_|s){i%?${Mf-xWitEXNQuf3)KZr=SZI;iWPzMR+ z3H7D?H~Ugz+AJWpBcU%#ODV7e7-V9y5etY?Box_JLP0~cDLOcA!v6dm3U<}#QG_m5+e#?ZH+?Vot)VM5-5pHWtLfs^rLn8&;&roQ_nM10n~rrr z3%GYA*g14y*K7)0p9OHi8tIMttVon-3OaWD45SeY-Fzz)Wp_p zDxqN87#-WBLT(bBqd&1WqSuRFaLgX#I3#QgW}Mr&KDuXW6%ezK(8lHx3bu{HSQ{f_ zZ4}1Z80ofy4+y;B4`@J021~x!P$t?A<}j|-?fa$ROa4^H&(lma3&?#6PM*SVm*WhkrV=s;!{YN1H_9) z97gmoC-%{Vy;770BD^A8i=+^66jvglGO-p3x2pkjwsLdToO0~C>_Z6Kb8|myUn<6h69C9GroWe&F_DTRxJj)j&X=5qgfrJB%;ECTj=4qez0PqyM6&Msdxp$24 zB+r|olTY;7(Z_|L*U{V$@me2$0pK&jvu1~kCUjliGItxs*?xR5nm6vePOutJm7|ex z?@CNY!qerv$O3F1w;scG+dK+(yGIkcr0t5knHue`V>r;@LCzOP`e5V^@#;Y z(fU-D*gS$=idAICIJ_|nS~IVoF@oqj{VYJR^p+-qDu)!8NRH?QNH!1A+Ng|0!q5=B z>51mKvBEGfnCAusPT2HENVv`tyO2x~H$JedE8Y|cB}lm55d07cMZcOuVZE{E6EBp$uLY7>C1%n~+kp9~fVb`a+vc=)QM>`8bTeP5-$A zrXgWp5XDIGKB!-dWW$%0A^sU+mtjAn+X#imoLNYyOsKO9=5f!huy$e{Qih3TMh6V0 z1}70(xkacF=Ebdj)f~_H z&eRYBW&~a#^UgQUrubL9{s^iEy>{45|7KW${~b{Teii)S*I@-FjhkLP2CJB3QAuq5 zuVM*c5TmgKaG{HfC13_tu>`hyfjqxjmLFYcy;`P!O^%Ou6HDN7KQ-^dcI}%q#h>B$ zXF`M!NF2fUbNI&S0e-V~cn|dF8})#RCcx}~f2LiVe?032{5lp>EE?PO^iR$!v3coP zeo7(NrBC^wY4e6nPxohKj=r?xnO*$rGP?|Ip53%fM}JmUSO2=K)7wL6;TLChZP8*P zx1oM=*372;u4&PvX&b-xeE(W3aG%BZL0MP>A42nNKQGJwvzIk_tY5X5tI1GgHCpD6~7Xll;4j#0_Coj#L>i{h-NLM{y^E53rsGHy(k zq87wjKnwuZi?!y@G?}KLafB87S;9tcxZI9fO$%GspKfYki=v+5E1EskBI=?crM7(Q zz_*bntB6&h+%}Z5`DP@umyIi9Gj)wC+i+9o5{v~7pV1hUXRHF6JT zTK_d{SBedc55I=(kKHKa(X`^%vPGxm8Q1C3Y+*ZL%*go4Db6wFGE4zGT+?hFje?DD zp)K^UvW_&OMOIVqtasC4Gswo9Y0Pxbx1O|_re^%U@T=IKTxVK0bxl#TwMLCOwIiVU zW-FMDH;tKL4|A*RhU(C^r5n)R`x1Z3BEL?SKPA&Y6JaniTQv4(=HR^3uvv#@jr|!} z2nf+QJi2Xm!)(mvj@hj+nOk(guHgZlmf5U>UzCYS)woTwX3Z!zoaEnx2ocA<%qGp6 z=KB9Ygorx=TY}B%p6RDdYTC3hP9-C!x4*DyqmE4)cWl?RXVVT%+qS=~El(v)n@;p+ zX8N^q{A=g?RVOv=H?&31Mth9OiS3Wj26r&Jv*VMTND@j_appDwH);19EIL! zp2>ZIJ%UXgm*anjm>a7Q-vi+{zQb1Efx$(Hj<21VNwKrPE0E=v%_;Qn^t1fylC#G6 zS7!P3GX2YP{Istop53k>st1GktGNxiaH=)_uj$$eQ77V~L;RbOFygL*(TD>4 z7GdMciC0daSp3^Jf4IjRS3G07DIhT#gr%bw6;F!Cg3g*r|Gy`yMjGz^<6~;Hj(Zy5 z!$59&iv?9~Oui}U=EU-ZTS5!{TZ4B5a?`itneo3DR|BC!vJmH^IO|uDXWUule|?0F z1{e}PhvO3o^Xe=**oQCth7$&s!?S~VRW8RozD`FK&WBCc2Z-J*RO0%X?&b3MWEt;oC;g!u{c#MOzp;>A9f;mHm~@9J z=;iXJL3c8Ol1PTe3_FdbzgdK#%vg zU?`v0tv`NM&-q&l+0}vQ4TL|Ib1#>-2!?onOXK`ulcN6ahwSRm#~Aqg10K5F%jMkz zL%hHB@aOg$zV{dPw-GYybU@-O9Xp)szPlImm|hTFxs~m)e_bKvvE1uOs9xl+XI_>xwc4mOffIN zi)Ypwt_!&a68&W$vCVjYi!e|7z~)}gpVJ-V?f(;TI2t*}hHg}>(T|=roX$NQd-*4g z9JhxvGxqX5&aBwW_c$|RFW;-~WkTh6*cV4U_VV!&SNzL2BN($VPDgX791~s_7>DER zShn^1o2Pbskn$VRIie?jU5;PHW~bD&=Z_#{UZ1!gIOhaeTdYT72wIXTgsE=wJBdBS z-eOoBEEb9rMSf^W|1-t8;%(w$akcn>_>{9eJmN$20iS^sy^&AQsq z`BxG4<3Z&=CjA-d&r5$@x>-*f<=>b7iSoaaenjK}%=Y-98U0t2UQ2po>Fva9*>j}x zYul`Mq4a#|{1YAhn)R}gf4TIT;*H{+;@zTI4;%Gflg_^#(*JwX%{ti7zm&dL`A4Mx zD4pNKXZwjH%4bNgExn2K7Sgk%cOtPrhsuuWV04}>Xvb7H z@_fv4eZ_uazBoj@L>w<(Azm$BC(aQUh~=U=PSDOW>E<|r{)lv5qu7t9#h1ia#I54n z;)mj=;uoShj^O7<>Bq$&=N0UUVpWkpA)vj!*jQ{WwiP>x-NeerSAW^_MRQ!i?)om|5@dD!@%;qpC!{obNoWDC%u_ye$4~B zIgY_>+0PQs7W<0*L=(RUjE^ZZf zi0_L##a-ez;z5yL6rlf~L?1HsB$3}7pk7OCAT|+OiEYGAVmI*|F<0y-UL?Bp?+c}m z5ib>|ibbMZ|9*~i{xO;TTPWTs{$5-w-XlIFJ|;dbJ}dr7d`)!g-}3_qw)3I*srZGs zTXgH+e=GfGk+<8d@7BLhmG0KR=Qqxo-$ZOKwiWpW4d%P`?|Vwm6~p31;vjLPc!}uN zzrS31kytG9$5CwOdU2t6hqz3IowndsKLzg_xrai!?iyT4C5 zzn;zd8^k|~FNl2pWBwNL9q}*XPH~rbP&_QU_3nA^O+VGdnj(MPKzpWmx_GA8Q*`Uy zUm(4|I9MDmjuqW{_g6^2TI6SEY_C+jLA+U9BrX+Ki4pNZ@lo-=#6ODs@hSap6aON9 zD1I(}A?_FdF8(0?B=Xm*^jB4^CDs+2h|R?|VwTuV>?!hRj`SB6FA@idh2m&&qIkJD zO}ti|BVI3-i?@l(#Jj|G;(GBZag+Eb@ilRqxLxGWciI21#e?Eu@u>K-=;Jd9mQNC^ zi8aNBVy1Yyc&6A{>@J=wo+tJf^TpxfC~>?vNxV|LMw}&{Owd`Wyo+$L@pKNLR|zYuqe2gSqUG4UTFew}Z|H(9JE))X6xnc^8@JF&CaUF z9}piApAt8Te-d94-xl8$KNdd|cZ>VP!{Ybi&muprX1|ieRI!FwM{FWC7u$**#BO3w zk&7nK?*MVAI6@pNP7tpUuNJQrT|9{ErQaxW83y`aAx6Y|#Ye>r;xpoN;;Z5o@g4Cm z;wR$g;@9FgA{TyO`#+05J{UCPC}xPY#0Fv$(Z!=^E4`E0O*}`;75j-7iCk)e?Tr;D zi&I4x&tjJJd7_JN!Nn<9-^I6BBmHi%a-56*lKqe3X7N>Vo48&4Q2bQ>yAf|~KVm+~u*jj8Wb`raZ z=ZLvt<+vOpWq0v8CQ83toF-l?&JnK{%f;KorQ!;4ow#0nRNNqL5}y~hiQB~wMHkQG zE9ra1zl-0B$3++4BN2ZK<9PCKVq{J6G%-_bA)YC=7rTo&;(6lvqKp4gAl=3PxJ3Fy z@p93{|F~BATyeg*P`pFrLNe_4J>o;+W8$;oi{dtMyZE{Ih4_tlQ2a^!MNGh-G1*=f z@iei4$dzoE-$l$7!{SBaAhB{>kIQAhQgrb==1RX=yj67ZJeEseBi=1OEV}p}Tv~_y z`;)ju+$O#+ek|@1zY-6Mhea3P<7ep!_yejLAF+m5N90;Q%>S*p9(|SHPs|sGh!>0F z#3|xc;tcUR@fPuR@d5D>aijRO_>%aFxK(^x{7T#_{$2c5{8_|OsAfC4SP{3kw%AB) zDz+CpiCoQy<-;OA{`#lu-1gAlTQK~U*M05YB{TN=SL?oZ>eB7sUiY8?uaA$+q zy03R`xP5Pem$EozP2;-~@0{AWQMl2nmRP6l5v_(nuF@Q9oIZQluePO6 z#+{4%ct;X$NIo14R5={wmpJvb`LFfnWgM zeR$`Jsovoe9h!Z1SJ-Rw_Kwm3N(xhd9<%x~_<=Nr1wN+PPHN*{G(_6x~h0DWFhBq7w_S$gF%inM; zUgyRZ$Lnm{cr3VX<1w#nVyNTbtuG@5(%0v*y#s67#F9eR*F(Zr7tJ4O<+q zUY>b8ur2d=^}CuKuii0fMPTI{H6J;em@#nQ-tGhU9mv6oj%Rs?lLLVsj~w;N9yuD^ z{0LUzMUA%dSsc9bB2P)>|`h z-_q1Tr-A$44BWH-%^>zqa^n8}X@SKdj(^G%Sk*9XLvW?P+Q;ggPagF))Gi-Wo_#bp zwZZX(>T4i{p2vKv{#QteQ)?ejtsThmvHxHjbkE`B;MY3>tLpZ7_Aowr+#XsvINafA za1?6y3-qjgJXHP19dFb;<7lwK-}?3nW8Nok-I203aaFZ7-s+hRPt+f?Z&`9^|M^MY zp#^2BYrU*q-$u%|>`zQd+8_3?n(ey8!za!PEP6P+3Eq2e53cGF?u9;XL?0WL4>Lzh z1GKReQs{XcC)GdT(J{K#@zh#@?m_eow%+%muV3#7Vui{r!F%^_Nv?m$_mj4xhZlA~ z8mtoNS?jomUV5wFsCjqaw&-cn;b2nA;S)W&ZV#+}Ah!y7Fl76{eJhjMhZlDA4)?%H zipgc4?y0g8``E*r$;rn4=YGfj&)m8%nD_ENFE@U_H#=Uldi6cX?NDXy)_s0n*Q1F! zEsy({7ydTP4b04%)dPFpI@%U1rsk|mUE{TD@LAISzKI*y(xPf>-+rP~_yVj&>NV?# zvBmh>v2FI_j+eiECp*~feD?cHj8)ffc6eAXv*re_mYE$syeDI|*LL>yM0lLHJ=hL& z;n2-xfp*@ZHD!tW`=oi8ANMxw7!Gr9j}DceR$f+)5&Hpq9AlU?A>(*Lugx`a)<_-K zw{Do{ly7!4K|j;hdF>uL91QjP_P(;@{e2U#a%oD!vJfoiZueF;59eziH7Xy@ePrg* zGP933k3Qr+vh&F7BhDkckGxgu_iqjP`?scG6;bS?9%#Aq(cl?@o*Bo3W+t`9{z+K9 zt}oARJcFM5-KNL-bLG^OyRcqmF!a)nK^QY{-RFC}760`$&NiF>yt`9)#_kiD)AyVa z&RCPMVk%bDwCics+PuEcrrjBsi9xJg-8b#thS?YijBx*i@??xd=)2m-J#2q7^kTfW zzhXyZx3@ZD&AknSt63*I?3Fhy&o~}9{07T4aOJ+;aqDi5(|h5|_p}VBu5P%tL4#2Z zcqKrs#K{da?o3$jFBlhhUOrAc`xJ3DC_WURG0nr^k$CY}YoQwfaB0J#(9Ci2J1je#}_#> z#yjm3Xy`eD6=3Ak-en{2_}r7#zNP~!KUN?5;+S3m-K*XjZ~XE{HB;*?Q>#-0SJUcY z>ZYdEAA|1I;0k;En$)^z?Y*XUMYOin@l!?Bw)%AFUd_&`%`aF54*OriNv%sDe~sK) z1rX?_Rv5xjSZcE&7OgV{Z>f#o!MdRBC#1l4KEJ|YTr@_uanX?iUG#xa+Z8n~h8q{v zd%+KX%Wt>-xat2CWZ7}E`W)(J>#hC8Si0PUI^WGfVKHGw?L!N-L3<7A=hjJ z-I#4)Af?)_sObPhDai$^^BZ!3%+OcP#a`!vp_Gh^^h~&LMU9K5uwWk);jJ;x9cJ#f zHvP{-mfd?+pG@8K-|9C(_o|oUtuR`%jj8!4OPb@w>RYLsnpQsq-EMg=bh!_^-7T~V zPR!8PYpN}8OM!duTnM#YQPb^WR%<|E+#Lbg%j*ycI-iK4NN?v!vN_tFMaIwEE+$S%Y6a zEJs=tt^Js({dbl&wXGg(?%K6FLm=64W9{3J0-HkoUV<67YmjR;nh}u9M*ki{ZCBK6 z^uzREU9kEhy7*(LP8GR$!MWJ(Tzp9vuBdVGL(B!M^XrmWsyS=kkA@#+;~$0U;jiar6zjHB|IehrsdEm5+ODW+d=M;f!TTCkf1EBp z4)F^FwfL>s39Pvc!b}SMp6x=qa7F7p2Fn`jg6D2l-$)mqgd(mN8(5PQ_!SE5#RqiZ zike=06LZ1pPt(Pxq0gO*pPh?pt>mH^gxap?X*~U77VpJdUET+nBY(OX!7eChN6_jQ zP&XrJ^;@9hDhUS#(V91ynp>kat^QfGrq%t^QL{#I2)C9{gkZZg7m*MWH&lZ8R>P zb}rs3s!%YE+&V*a4tS}E)F;sC+NZz zH7;tj;fB=ZRiBRp^~~Dv^|&_tgYy#Wac%hZ^N?3Ra0Ysywc#7^yx(9x-=1LY|HEs; z+ZE%vV0&h&TN0kDyeDwk_B1UBZxFzW8S6+f1Unu6b zm>2db9=`1o^ymrY79^kKumt@fQ^>uohJb~lh{o7ocBObqe8@%yk&cQsgHi?(G6?gv zTeL*-E3UQ>rL{;XMBE?EptR9u5bV#dSEkP}9U4U7kp)i7Z%MmC#L`Ne=26Ho_5y-E zHFgTEOqYiec3V*%WumXPkg(Vi(H#l(md>MK{S9^g*r$R>%wYi?x-lq-P~rx|6XCYv zVxwr*j9(RR*jvFW}2-SMrbP@JZUTVcMPtCPO<>y_?PlS zarvAP(U8p*Upp(_%WHX{ZYv4AK*^1W$j76QKukGW4wHsUbi zT5BarkW6U`^R1oWc>$dv?m=SvB+m+HlHhbk3G~~%xTl{-;__+a>quC!j(8g>9ZO;M zYSF9J4D;SNLfZ$X$WY=Fq?#%+eeTjAi#FzBf6VwCDYJ6sEaPZ;smeBsu+$ew&AejV zv(rJ;(XYy~+*e5GAg5m~B=(y#s5=s6lD`VawSXbBR8v9gfpot5@oUvQaZMaTQyT7NE??KtnL*Vi$=B> zgEkrFG9*?f*CU}5#N$RBN_=3gM*vPe(-zoEGT8^Ip=UkYRvO#gXuHz5S%f7nKx%xd zQrEaW*(|~`oSm5}ca8Ru{Kb{z1f7b+{*XmT>DtC?wC%KU_GZZL_ITq6w#B@7irB5) zN}A7(yh4H>58xb6ylTWk?in8UanreS{Vk^C=vc|oztz$ z@dgvmoBD%d^#{57?!3wqxI5givS^|?-grPk37RA83#)`8Zg!hu?kvjsMHmQfBd+_z zi%1BI5i}7;_`^pWnFsDyR!-^x@#3i*qvX@F6RlRI}#L(Focmv zC^P}!nS|4YXOTrnW|S!K^GqnA2nC*4%qUTK*eb~p3NIpIl!z@x97(*3gpdw%BNTR9 zySwb6VP5F!B0+2o@cIUk;5o_knb$U+C}1b1ID70WmhY}&?EZS>+uN_$tWt2HJR})!;2I(g7(Nk_sGuyKRS-9c+-q*Dz$?VS8rc{Z+=*`i1jG85ecWoSrH0P zBVkAIu-j(DAq0;$bBUm^)7p9T9Wdeu;)oFk6F(Sn2yxU}3EnB7kM4osHpAa=RY}?ID1bu zn3ZO=J*kf%el>YU{PyJGE;*I=Q|v0-R77`GB=$TKz1jK#=Tv*sH#7%l)79pTIy81y zHPr1Lo_y<@+#$Vy3Mx^6tk+TN{T=gU9P-|0X7%{|%`K7=LBMv6`aXn`1Q}YsgG+Y`?IdP(X zgeKdmLHzvLHZYi2hhz(Pb%klN?GASBaz1lS0^9`?909}x=+C9jS@PL9-BodSq1Yxq z^VxgQY4hUlL2>WmtS40oWHm-gz_&oK zd^^Q9NH~WQ_6i111yIHsdm+Ig!gCcd!H5L}M;y=S>*i75$YI0XGaqiNd6C;?tb+-A zk%RBpo!YR;IBbfL6oP;vFACU1;(jCM6MT#_{pXqfWh8|lp!hZt`cK#sKic4V{TE{& zN!XM5Aa`dK^s>!~cqEQOK7GZW#5$TMF&>4qyS?w8N6;@$1fIgMsYD|7Gd~>xxcBh^ z$~-d-cq4@(vHPjfd?vB?QzLml#XBT6!QEcN?6ScGAIx!foEPE!J0~YTkLd3vDVpaf zbACc3INB^h+SBr|xY13-mbXP>J3MWDfrQQyJYSj4Qm~_Af=2LT7#8ORj-zF&f*c{r zvGdc&*fnEh?3xjMSj>Ujxn`UO6TGR6MH*-YEgK1Yjo`4Dpas|9K8DIq*qm5tZV~$x zv#@vUNzCH<6?L-^*-Mbn1i{Wm^V~@^RvkSwuba^LLL{6H@_9O-%sqwKOz@Eo6MpGD z3fyzp#RQDD3XUks&5$tA1b3+MhAbXF+=0eLZ09V_ch?Ct!%eGi`aOhbjf5R+9uL}D zGhuhl;(ShE#`D093Ssxs;(Tq5HvxjZ^B;N$Vv5<4e1ek|9}P4F?EQW|_X)=yhk5K0 zmwySyo(Cz)x*uo85 z-QbqSj+4P|D$wjE0cE%QDaU#>cqw|c0tw9$>yXTC4rW!cX*ojEMq7fg4@$A&;<)i+ zK5iDt3l-+brg@3eFfplJf`kpt#ZK&xgxe*e5D5Ve5%>dwJvyUTXHMmxk#HVHUGp+C z$!u+r_c_Q5c+i_xO76C@;ZH`MZobOHOESuMWPK}#NIpXaz3HW72P=n2UX@WkMDnhH z{-=PvxMDiuYTCVF8DxH#fq*?Bl9yEbD9#Txnuj=Dd3|-|-Nl^c-L|}lK5`p^xRjCV z|6Ef250Z^dJJW)s`aCzT&xvt;PGq0+ZTYz;_ql6BcXNO~1XrMp`k#1;{wJQ?|E>+W zEh~^rU66areu!f}dT^WMb_0$nZpCJ_f@y>gD6(-&!Otb5$8jZdWd~KTzf{9HvL6st za&wZgvXi*Oievo=QWbm_C>K=OUzBp)MyvX$IO1Bh{p@_|?nlk8}TXwt2@Gg0LM8Mj|);xU3NMtrGC zL&#D*;;~y?DOTcv6IYSv2i>~Imtw!-rXy9B#C;;c11>Jt9e*&*(nvU8zo13l^yBu! z-TR}I8^XAXC6y|=(x~WsvE~2B7c26rtB)CZ7(;Y!>9U5&jh=&Psx+E3RT?K&>T_~M zn(7!+^rLB-D*2*`n;y4qtYmNhqZQ+xa9mg8rd;UPQ_h*W5*4--H+G|Ge~9Zl+yB=- zSgOqU7)c+zaAIO^KkM`HTMvW$TpuDE+h9f4SSbpvFa@KJ-BX|zBjIvn?mskRX<}*Iwh_Dw zsZ_%Gq=TYpHlOg#<(Q@gNVpj%Vh*AuoCEF?X2oGARMDO|7#Q!g!+%kT!f{i5TKCTCqPYi5IM{InjD(w)KT8$KUEn=mI zjVXE&qiK;bMK4b@Rq{oX-R9`A!b*>yT#+WtRo5??D*2+R(r#j8q!?Z2i>3bk0cUAV6nBn2#YAygt_^m-(rCwhw&hC2Iu{*URdvc97Gm!?Xi9V->}6*EPBv6A%_-Ayr5bhKlpsIQnQx&z`q z+H)hp^BZpgE1e%`VriT~T%}4S;vE!49YoI$G|e&&3J9Lgtb=F?=b%j4aTA4ScbZ{x zxpAipSJ6E@A*=Gi>ayZaLEH?Q<4o+>zix&lbbWR$yG~(rer<|Av$GPn8`pSOiY8r& z<4v|y)K{!xbat|mEft+nH0jFZe8oydeZ@@CyF^y9zM?aVCS7=(uUM(5ub3%1qgcuM ziq5;$Fl|JN8)%lGxsr)bj&b{yDl6g-aqe%|xmH#@hh*;w6JuUtTA8igz!b z{&Gn4S;x;S_Fwi2&uV^V^Le8Xq%G60iO6+1{-w+f8jpcQ zzsi=xtVBc^M2@Mnah{DGSIzpUW38jC*2F^L2NiI#y^T3{iN)2Xh>ZZ)+!jyEWD~8j z{B!aqkM+}w{b`x#e;yiUsf`|LvH-e+@711CB7c(!x!$50+3BKoZs z`E7E#`ss!Kv@Ab83k~@nl;mMhwE9H}%nr9` zcqYi6@!8QsrB2xl zF=-<9om2~19lIjSMyHI$75u+ChN2nQlZGKS-A;-|_}lRm6&W!Wt}yDMQVc{>!VGb= z#7V&_ZKTX--bry9PZccme^2N_e9i9U*o7_PZlib?b;{U@kA)`8a|g>&=TndK4beLQ$4%2I*_X@XM<4P2R>R+R zOeXqcU!1?OkX;>!Ue((8yK$VsiPI{Tn^*_ygPPwqvR2H;RgmM`or*tAk3G}2OS^0L z`nWm}y@kCzFOz~^u3dgzINsm3Tlj2i{o!Z1QGZJzyE+iPhkJP@P99~xT;3wc@&0zg z-v(rIT=2WjsK5K;>Ol1N_4d5y+|G*2y9aW-zuRt&?KiA#67{!HbvPgRx-X1*;3f}r z_K)cW(UrS6@864C_%_O&g}UxVUwnOn#Cu#57q5NC;xi!P4fpQ+!`4n>_yLovUF^epL}q@OK4SNcWL z3#4BxeZ2H5rOy%P%YM7`CDPYOzeoCG()nRJ`}KnKZK8==hJNl+{(jjHNk1+<1t$t_ zkBLhLwwB&a42wg=@#1A9+T|K!tUpuweCan!Un2eY((jS}fb@;hpOOBubQ4z${@<0p zORNx0{IFDf--HOT8{a7XaJ`(jG68|Xs%i^2jcICe(ekS`~=?BE0Wlw-lZYO^VLe?aaP7^a_ zKb^#OcOcQPp0f9nexdYy>7%5NBT;XP>@#F9k$$7}h0>QvkB~_BiciY^y!e{9Rr&lT zFUy;FT-c5;r1QI~wDXr5+`bcHGR~LOtCFx)7x@KB+M7ymDQ1z_?z5E7Uu;nCC!Igv zq&`CWr6l}bCeD<-OuR+BL-|X@RkE9}N}~S5vOg>PE8;eBhw|SSKbQS$660P$qF={k z|3!M0B-pW?T+5F6^`ti;QLnY^on-GW{XFRxNFOZS#lIRy9sRyW_7d?1v0VALiOXbP zCw;y6lNS(So$Mx# z70R70Jy-b`NgqsNJ6-&$vC6+f`9;!aOD~gttMp|g>fa?kB>P73IdQY{U0kZSWdBHZ z7mw3@>`y7V2=KPBPsucC<~1^KA*11ZRdoJgWvida+j#?qUK z*|M8>QK;8PdOzj6cu~V-A1C`nafa-3#hXPJ4{DLhnRrm}@8Uo`D7%RR1^b^=Z>#u@ z^8X_KmE`;;IloENGx49G`^cl7OhT_Iy&j3wO!juNXG=d@dam?~qz@)BelEV#Smj@# z{37YIrI$&+Rr)d#_3siNl6|B2oVZ!}uZnNU{*m;Z;sM#e7k?3bJU6qQBr$`;I5d#n zL~Jj+iMxb+6L$#=D?d*hta6t~A1_XmeYUtjyhZu9i_2wSL!yuOlbqkOKP~-F(qEUp zL%NHj^jGTGuD{D};wGWL0r)cWn?!z!SX1`K(wm9dviB5CTqOAEr~He=Val%@A8Cf{ zbH$s*+eoy(NW4q-_0k^{P23~2XW|}#TUG8I<^M(8Df^ewOuTG@oVvbct|`Z{zEj+L+E!hpG!b4XG=B`TZpa2j-q)^ zLb)92y~I3mfH+hfAzmt8CSD~@6Bmf(qKWg4cJ7qEQd}!OAU+~)6rUDf5?>Lwif@Zt zpqJZgp4Y(r(*G`U#a`z7e2xKAMH2@ex_M3mT|DYDmET_ElD@2Wo_L`+P#i9f5-$}m z6R#Ghi#Lcji~L?2{Vx^G^BeTLrSr>K%;y)Y$Y;doMDrX6`*!Ici95wF#XX{Vu0#3n zq?_kE=qIEn@;M2*dENtSNHHj!_UFZa6|eeJmHVr>SLBKT z^kbek!5^jnA_nzb_TPC{MTZ;q40?|B&LY^z#JdZ-YMfzgVJeNXVBmHjiLGe-1Jf}i_M*555%VOo{ z)%RupSllIkCGHnp9O)mW9~XT-&p}QS(?$N?jdt@q3pSSCN^B#V=UC+DN;l81&@Yz$ zui`_`Ryi(|$o6g$`Ex(&?zwik^tIwW;;Z5ok$*E`y+dLhKEFY)FE$ffi7rm_InudA zI?In0CyP_X%JG=z%06GbMRakQxx_mCx#!adr9Ub@DLx~b=Twy6D*avY1F>>EW-ifA z|KEu}i~NHU?MY&)SVOEMHWHhPT;rYfI*U1CFR`C!o?}sNnDmk2rQ&6xd5%T7V(FFR zFW)S?d9FpdrP5c35%FH}VexVC8PPoNqW;U$Ul+~uF6=v`?-IWf&GRnuk4fhrEx7$5 zv8q^ItSh=W%q^v#A!dtRMHh$pJn1eDbG~#Jhk2Cr@!}-$YH_+)BF+_W6y0<366xkS z8QbCFFyAY?i^IG@x{Jg7g7jBK7nk`R=`JqwPU*YEJ)(=td_?*W;y*<5T#f#?=jn7l ze?mV^Y#^Q~wimmKJ;dH(UvYp~AdV0(7AJ_4#jC~XVu@&;ztJD_{0-hJ`%-a*$TgPP z?|a2Z#6O7Uc^vuAOMgv#Lwr~KKs3+gDF3DOePV_9y?9LIGa=hg6swBWMJ~q7d>5y= zxpWt&IZL{Een+{U(p{Y9u=G5!@^kzpvX2+1h*yaW3c>d0i?@iki)+PuMDtva@{dXX zSMiwNSGkYHgQAPKT!qiO@K;sj;>^_Ri%rFrVq39;c$Rp!c*^H{_#3YLvEl^r3h`?3 zTCqgDL3DAI?~uMkyh}9C|7gcN|AP<9{-o&QDsPtls`!>@J`X^>kEHJuzZCa~hs5v1 zF8(0? zBnI&P3GROv=QvHei*tOMbQkBinej0kba9WLlm3#pLwsL6D7v`DE^cu(e8GX^c81ta>?`&Y zFBLBn=ZQCn3&lIcyT$v&%JGF6M279YB5oDm7T*^?78zuQGDPQgMa2PFycODsB)r zi?51ritmUYh@Xgm6TcQK#3SM{@gHIc-&y2%CX3a?nqmX7iC8)QZztKiiRX&viFx7x zai};#ba8+uN}nngi8IC7;tk@>;vM1=ag`Vm?-w5yE5{3dQTCU`%JG8Vm;GaLm+0aM zySTwW%KnQO#CJS7t{Gx2v4Pk`Y%6vU&ks#PQ-Jak@BDoGZ>3e<$84GCCXk z^_cia@dfc!af`S^d|%ut?h+4(hr}Pn<6;uN9Ln}m#ad!rF;i?Io+-8$yNW%;Trn(O zBn}csh!=|!#K|I~(Xl_J;tk@>;vM1=@h)+VxL$lv{Db(U_^kM%_?q~JxLtft+$ru7 z86A)P`&Rr({6(ydKd3Rko|q}N5Zj6!#BO3w@jUT-aiGWm67)Mt93xH=r-;{xGsJT7 zHt|mJ_adYF(eESTlj1YtYvLQ?cJV#&Q}M6jUh#m)Xo2*9LS(!^>NUjrVq>wD*hb72 zyNc(CxniC;KpZBH6vvB`#H++r}ix{kL$05y_(1vm(-hy40TDpi^zzV z)GrVj?~?i`kwGr0UnMfgCH3pYMdDI%l^78p7dMIwiplzKiSLOYiF?HTB12`ee4@xu znbhlvnPLmElh{pUC{30x5J!j?iwvg8{34MtHL2eqGPEZ3UWcf8B z!){XFATsDC^;g8L;@jf;;>RMRaI*XXk-<2rpAgeCtzJWHDz+5ciXFsmVoxzo93T!A zM~IWfsp52Trg)RMP+Tl76CV{fh|h@6iCe|D#rMUJ#Y5tE;&JhWnAp^Ae~MU7Y$P%Y zD95XVc&>P!m?sVpFBZp%lf|jxbaAG5lekd4OI#x|awyy1AU-2LCvFwr7T*^?7I%qX ziQkGpiiyp%{bD1rsn}XC)#2>_;#40Up`Kn?=F;i?Wb`o>NusBp4Au@<5+n*}V7UzkKWXk*{;@#qXBEy$5 zf0Ou<_=@<2xLf>QJSH-rDeE^B&lKB>3~$Q(Tyc;%RGc7A7H5jHMaDK|{X0ZPHl=>I z$WW%#pAugY|15qWej?~rPR+78N8Hwe{qa>sW?Tv zO1wq9U0f%w7atM-ATs1B{l6`KCjL#_D;^O2({1@AkwH&cznRFOr_{TM40=la0&$=? zSY+5!=3gZ;`YHA6MFv5ozEr$dd_ZK(Q|3P_z9GIPG6E{|cZrODO8r|g*xKreVr{XW z$nd8u-&SPsQ|jl6jCM-BKpZDd6dC)J`LjeuKBa!E$Z)6B*NO~xO8p6u;ZCW)D*i?M zQ2bszCNl0R%cqG9e@eZHm?dV5y~VyFgPyW{p?H~ig;*la6&dQ3Z+agojP^woEdv{?A)|o6Hy<>+CUAw~8v0JxJ0A6EL z=Jo9#whKMM8D0UeHM<>seb>^637rjEd-V|CwB0v{2Hvt^RXDIXu%>3D)?HH@e_eNW z-A8iE!rl=CgIe=Q-(E+&`K`l!!*3l8ZCDh(A>1YmYwos}Ufb^{crE>9fi*AWhIaaE z_BIHtN$BG*yLw+z$|rrEJ?vHU*Yx_f&HQ_Fy(9JJUy)m5?ZACEr#0XA<@6^GdnuFp z1n*qhC+Tn?q5o%N_ARUO*MrkbyhA&#?;XB0d_j1}L9fSO4tjYz4hE*wJQ&DZd@wk& z=E2~U9S42TFS)d0ecq&s1yhPE9w=#9kvQeriU+2&thl-4+KN^sf$o9B8G)G(0-jw&ym!$`TC25@xRh-vm0}@!jS-59-T=-6m!n+5(k%KV`7y)km zlvWiB>R(o|pvSuyoy#ghDJ?4&+83~=)4Pmohs(HDXO@q&1DrW zdQ5_iWr{0q$UD6vp+579E1I>LSaD;IRuwnqEy1XsUUB2di4`}EWL}qw79%HB+|=W; ziknogS)0=_(t)!$sxvC?mWO-Vbgf9}5j>m`d}v3XK2@L03!fQI-sQc-DR!vhvMGlu z&M(Dw@N8^B#eo*HqkJKf5BK&9sX9+H`{D%N?&D z^y=SqFwo}pgTXd89rSx-bRE_=6!tKN^S+z-htDvIp_K`15?9~p_3aZ}k#PvWB{_7W z3?rWs==8w;lp4wVZ}2$wq3nVCQfdY z*%C9p!71`HTsb81rG1Z+Xbduc~-^=If$V9gbn zQ@)SBCi|j^f2&0+Qa1iUX2I#d(~^Uab_ z?O3U&ft*Kk51_ZnheOGK+~H;R+E``73wsa!F7@z<&i?MR!nxtU?)h7|cerqO@GkF+ zKHHze5pzD?1J$PDJy`9+?PCtk%S+sUeHuLY%P?<0Jm{6Ye=sm|IL3Gxj^NWUFDK&I zoLF)Hl$jOlaSSGv%&fS-q*0j1VW^WGtH15IYR{+!N&8a*qw2@b8}^(rr{V6eM>Y7g zL5&qWmjv(h_TQY?X7^L!p?m!BkGoG~uHO?}aiiBJ+#x(7eB#GnP9*M6NIQQ|aOIeT z_l->4Ki~Ci%I|H@rl4o07n5)<=~mIw^yKttPrli4#-8A+F$bTTlDPi{SGR;)bs4sT zy}mzM_VA9Hd(QW9J~!vrP=LS92>cn^RmO1gTQC&rhpb>A5uZQ;$=6d0Cj8DI=>&{^ zDxGy3&iqiqJ+!<}x%=hDl5~(rP8e&D)C~xQ61WgkFqE_lntvU9`Mr6G_WwvR_Y#Q6 ztOX?@gf?G>5KIoeOmlLm5wyfW=*j>udP%tP#rs{b%}e61+vg_nw*_;OF2{Rm5`QN# zJE;b?u*6H|j{!n60-I4Gxi;lH0=Rwgs)Ts?NeQ%rDKN%(h1KIvjrlV6)Hf)NeN?&dV_*{1*Py1I zLG>yY{+cR(xF5Kh>S#!5T<9-QM3t-ZRxO(41+JmS-wjkPy3PwsqsEYGX-~76=~SCl zfyz4$tMa>|Rj1Fm(hC%G!#6UQ_i0x3@Qt}NB&jW^W<=E?RPi@L<<5dybyf#2FoT}H zGFnGzt<#v7Ep4jNI!W6=?NV2dUoK0Z;svhdAXL3V0)GOA3^Zlz{H9UbfT)^)KBYYp zRqv#F5qIFs+hDw|I@H3b%5R6HT^d!V;Y$u_t*Fl86uK8`wJ$>0voK`@3W786J}5XF z@A<)NQJ{LD2@5~O)&ez%8guz}58hy^9%z|fGu2OTkUliAdY~YXfx!&6@KRIHff3WW zj_0TMNbQ-*?>vNLPsYryh9a2Bp+IUXvQ3=(q}C|Q@608uQUWVgVMz)pHkv)1ou1aO zX7xagK(EB#=ce)78u&$mYbMCu-}xl9D%51#3FfB9RBZb#^8?rjeq|$L;e0HSn6fw* zUni|@8)HMA({ivUY9x5KM?&CRkAh#fS(D>e*EvArrYYhQ0HHZ#IEF^e) zhh@HrR&Zwn+*4|cgyIC38?YIa-nAJ7*B`(twgj8BW#B3L!hAr1K}0Ph4kfaX5bEgp zc@%61@?8gvJ=XqEwr@8Fb!TDL+IiA5!e4{N%WN%uD;?+5TVdw^AJR z*bBsFoQ}}`5c<*%%!arH2_?1x90-V&cBI{`!uV!K8?Oa1PX#egCYakN#!~@*qqEP7 z{27k*R1oi}6bc80tPl)2ZbJW3Xl(5haD-1rGIk2Hc*uLhh&rZ`(L{YD1Su!VJ5m8aacL96v;TJu+rLz4M?m>K5fm!>oSuZ#AI)#m)!zUfua+N zm2gOUjggFF3LFUZIvdDyb_#ZIhPlC+4`Bfk_Q!JIWhBHg4n-(zwMue?!n;;Ui%{Uh zD2io7DC|bU0k#h~YDFT^4DB_g5ej_RM3Jt*wMHCD*hw>l;IB0iNH7$kaEDcrBNWyl zA*>9s-iQUnS4bxCF$IhomE;J8wpK}tP{^}NMufruB&>r@6d7>{!S!m;a%qIZ!`4nb zZp3`zd21y$BO%mZQG~+J#y*tbDm11)6l|P4^oK%so0Dcj*`H&Tj0lB1B=m>iVl_Ae z662A4Z$_z!r9IW!i6SHB6LvxlWpu^0##%^hMKWEWz*T6>kWl!e0qJlqf?&-$M}!oa#`LBNP@|B`xw4 z1UtD4-Gqiq&TD&C7|K)QM@Sfsy}%DvBsj&5cM7$vk{sbY=OjmYqL;OYq9@h)m>-Rww9F~n70I+r!A{x1qajW`*9LV>^7 zHM@&*@(2@OP;u1U-dxtCU7!r_Rx_xi&mD*JhT+ z&9#}c%v`hQ*O|qU*!gvMY}$=>)6Skp89XmG`-XG&*(o(ETGH`i}42bj5KhDR1I3N9;j|btSmi2KV$-4pu zt|SYrTomt*_XpaRsE_sVvBhr71tiA=K`spsSbIMbM%qis3?nbfBiVP@XOSJOy+6s* zJ?zEg5G#jbeVJxX`DMnw=zP-lYnt0Ma}!q%EdjF`!C@)d%iaj$JtRCy5j&Agv|?V* zDv($M0bnTx(Q%xb348yBXvLh=*=P{=Zv^KE&eMSiuTAVAF1#Fft^;?AhJY6KnMb16;Z)83H#chjxvG{Dl+ayL`4M$7)KdL9A-q>90do*Fmd_r zyUtzRO{;(X-uL}~*ER3;9jN^3d8+EEI(4ef(tY|V6y*t|1R=>O;O;QWa|rf<-~!Sx zN*qBjM!!PjUkEIL-C;C{xr{auyp=I+ik&t4@!Z?aWEo2E+@s#Jryjr4HhO*Gy39Q7 z@I1>!SnY|1dY)u>BSJk-D?IBmjxIGDpP?2aP)B-~gu(U>f$CE9)jkBYm-ssZ+B-kO zGinB^#62*<`!KWOcI<{M`lLlOvE3UKyR;0p*G}eO`+2EhJa)+$yaOulQKNOlULsv* zhA*-Q3EWraw>Mjin;pZSFvbU+wO}RIPF$9l@d*exR0PkFctGjS{d)t!WW(`c{0ju! zm&ICF+=;b$cY^)iL-b<=9BASg0t|H`*&e8Ea}c$yX@|%J1au>@2q75{OkBK~aek{+ z0djFLxqgHKucfi2mTm9FG`16?h1ghjVJr)!bqJ`E*oa`OWSkuvEluHB1mq=lBiOu* zbI)Uj*#R6$F%9;>Yh(#vapWvr_&=Oe)u2blXFyf84VRm1(rwGFDTLQ03Jz@OeZ_5s;bKiI9xL z!d#5AdL-FSpn1FdjH3l+>w>>L6|<#eKLm8oi}REDKul=>0!~TzYc{q!WNb6hY+3k= zfrkxxZS3awEncpMY<{N+I`LPoP4l0z6wQxT(D{i)B-*ygz5%`Ij2ts|-1S)HVr0Rr zDPyN)o0VyztI*&C6}JkF=~Jyj^O=K1LaJrEH-*gKo^G{}TZwDYA2{19)4a3>9tu6AV@;ZnJ1hI5;k|qJ#^NA3 z&D-H0msr6XAO$_$>UqO&z#=DALvF8Zw^=q;IO&^>Wo<&255T%Bof^7W-2zVX zizT{+Cf?5E@d{xD8A{%&HtDgrXUEI$o|Dy7<9coKicO5Gp^Axn?Ve%!+2o1+>D|t) zw$+`4zG~gNHJ5xz2`Q3=^=MkTx6jXYZ})}V@8;#Y_xp;1cl2(2_0?Bj)v9G{{L|7j z*;laFab!lI*R?23&zs$paqg_pML1GFeW?13#u71ALT;as+dP!x4#;*d4K;MLL+%}O z$GNNhSR7|=Hi%_go@bXNk28PWv|yg;FK>WcY2uTz-EDJo>$Sv)a;N2TH5YGfBP@_~ zeYSg^5z}(rS7GdKEVZ-P&30#Pg{55NyAnH(LExr6FTu~1U%aJ0erj!rX*Z6aGEja!>rljt)x1hzjmP_b1{gT z9(d0BF0tiX%)Xe`$zlAog6j*WPy5M>i%}{)y0TA>6OEp;$j|?h^;&pm@iXhSbpM}P zucd99|M;a^9Q;g(cOJM&^funu$8X*p9Q{gmYuMv)Vn5@>f~dX65oZ~W2X3!~9A{F(abxf5_`8qJ7&F<2E$npEpA+BGlB8~aDUzHK!n(bsX!iNjc z+0E8P+BwCvkD5BpC@5@j^ep$6BR96Wc+QRATr+ZF8W+9J^H*#ZJyH2K47i6FD+{3k8+Qzbbc7ME*pt(T*+%hh>Cg_6feX5dzcXxPR@u%QJ0}_Lu zV};~vJtTf&YkW#$$Tc5F3*?^f^lJD7lkle$>TuzT3s} z#y2tK>m=tZ{btECB%9B~kpE7}_b7e2WaFC{>HMsj_J6DNrzJltd8cIa*+24qEZO)V zM)`k8{!013m27+uBYy_w2isknglv2eL*|=jl(UuILGopiuaZ1iG`@zB{}##f#rwpE z#LXn^KPB1t5QhA!WPT>dbbbKJ`u`;Puab{Q=I4e?|EJ{dB;%>flusp*UYW%4Y$ZJo zyODV|px%sokn@x>&nYA>9fmE%9I=C#D_$vHCH4^qh$F;N;&|~Uak@B5Tp%tI?-3sm zH;KOyw~E`u--|DZyTsk%AH+Y3W}aYw4@*8Oo)o_oc_L!JR1hnP)kN#-J0!WGm@T#u zFA*;j&Afr#fs%)bX8u4wR`QMFRFN-_uswH(OT=Q)%p;`#MzWbdke`(NjQG0vmbhR1 zllZB4Ts$S75z9sE+dG-#5cQ;pl|{1_6ZCvvmFe}wCZhRH2ztJ?%JhrH%f&9DdH)va zy(RPd#{8qi@#0P5RPk1Eu4vxeMY+Y2?-iGdE5%1dz7NBC%)AA6NPbB)^B4NJCBG}0 z`3wD@CG$%S+WAcUhj>~n6ZyRn^CfBiRunVDs$!NH5*v%n#WrGl@e1)uk>5kHo<8C= z;xO@gajbZ=c#Ak+yj{FUd_Y_!t`i>;9~HNW+r`(!H^q0w1L80F{Qg?`&We1Mg8P>& zriqosnqrpNNaT0mEZ16WCw3IC5W`|maiBOv93_qsZxSbqw~B@0?c!Zxk+@7;FK!Ya z6Q2;D5uX!F#a&{e&+miMeb3zY@#EAH-zz5&J1c{K++~kY>Ib1Y0U!j(Dkf zx!6tYA@bgj_6LdAie{}V#PcOj6sL(Z#ChUE(fS&{Px1U`56Gw`6O|1!%Cy8clEwsb>B3~r^V(|fSsmQnQ+5XMq@5HCY7sXQXEpe~-zWAZ| ziFj1}Li|cJYj2^x?<6Nz@aj(yGsPNWU9rB{RBS1>7p?DevnChpUnPA%agdm}Hdmrg z^y$hsOI#@4DLx=B71xLx#7D&~qFK8O?Ri%6tK#e8yQ1}t{%6V7H~MFiPl*2%zY)I| z{XwrEt#9=6B-a$P#71IM(X8!-_O+L6*7$pQkYWLb0Wo zBbqhCke(~q`bxh_avyPkI8?k=SerSo};pAzEMP|CY>WbJJg<^@UzVa&6JBHP%dWwwUM>oj>NFy|9?*6a6~r zM~johsbZoJ^hBTMiEEC%ta3ZWkHo_wKUQIT0%C?(Rpd{OnBGKeCw34!iCsnhCW-m; z#4%#N$R8;&eU7+TyjNT%t`awj4~tvHZQ?F*x42JyPdp+X6Hkd}#BW7Dh_YQlF;%Q8 z))e_eD(17k$lFOaYmGtQNpe@Qm)K9t6Gw>rDHiQb5od~XM6>o7(iclE5|@eV#El|< z%td?K#TUg=akscfd`~ zdx?X@JaLq0eUVR;JVl%-&Jp>;HMX}%Tq{PzN5sd(C&g#Pm&KjpUU9#8Q2a>zR6H)8 z63>X=iPqP75TEI>eb(1`rey2uJS4fH*j%)}&O1o9zRs_de3jTo93T!CM~V}~N#b=SNyYhNc>bhE}j;@7QYjH_{@s^ zh@a;fris@oSMke98M)78Gx;RT*AX=a8{H-b5yHeaBJ}5pRJ|(^)z9#M$|0I4Q9u?1s)^~d{ zKA>lPDPm=@npjV4B(@RTi0&*xk=R0PEnX~k6t5Dm76*ve zh}VguMgE+a_1-GZ6Bmj_;xduHH)j4vMLf2dH8*kCjUF(>#|?%T>GMW@o8-s7+Rv-u zgQaZ;x>V5?^}%w{&-h@uq(e>{llPZ>u;jO3E1VzsV0rxO=5tqfDOp-jw6rAofInO* zymVE`YDy(beK~K{zOL@F;^ixxQ=i^#K zTh@dpZh7sv(`{h*nzF#~er16kPW_Vb+VHOOq%FQn4#F47$ypzUzucep_2JnQpO~=u zo#Re}_mO`e%3c|syn49Pxh&AJWbNeQ)YHDyb=^9I^Y@KBu`YQ6YED~p34Fk8dv*HC z?cqbmlgCeGjZ5|(cg7d2avI==5&6Mob;6bMQnM6K{7!f;>eyNCZmF;V zu`TfWvGHFuPs<=pPiUcS~jHRyJyxpV50+Y8{iW8cn~oqBb)cMXO8D<-Vlz9B7KA-`V! zKJ3lDvfzTd%6-1RC;nDgDeTl=R6M9GkhQn0>Vs>;CE-D3!8xy%SKKl*oDqJrJm~vF zjfKTMoN!s-{Jmv0pBmQn_T#z4Z0+ioPQ_a-Yn4yGG5mwb$2JR(;)&vf#b%mjz0* ziuaaHEUHs-#nQ``bzXiYq_T~B%T8@Pbo}yeL&^dz0;@43M0HhPJSwmYiUtwxevY2t_YTI z$zIy`#NkPe@XnL`QkO}~C$E@)=C&uc zFF#aPb78^yLuI{6`kq*v+`H>C`3>rM8_u$8w_|2+ezNb0;-Ig60Dgjer`!te$vcz# zo(R_3axz#OyPjN`MUM|gbkIF6(7JR9WW$c9RwAHVmwf4sZ;#+5u9=5Kzh#@@1qCCIhp+TzXm zI9FtiSjp1I5l>CsTQ;+}1ZPAX*)1rCb7AU6l)IH@!jUVA%y}^BbVky{r!xZm!!PVl ziBw-7#2(cwy?b*hY+ly&$dfFGQQDyPh9Tig!h>;^#}#6h6IvL)2j?Sqi!ax^I*i2C z;a+oQFJj;NhK9GVPu4r1aGhN1qw=bu6tlRc4i);_S?ASBZ6=#0;_yyq?gP0Me zL7YdNQ;QZ{81{N+EP7{qICUj^r;6#FswLIK7qEB6UlPtNzIEjfHD;_lbiB&=eC%x? zi~4Git1j_+BK@46=v2g>VDGUvTwEKx{)k;0&RbD=Wn!O{?w|R)H*t+i`?{GVBXuyz?*x^L%%$oBQM>fGt1hPQXE6%OWKlD_~~ z8n4c=-Rgw{rvrh1?!WkG=F`ho6|7|mjOW|7ufNmT-ZiTZN~|b8=JOvcb3%DIgYx{o z0OzfKxJp+{uySI5a6{(Ng7wSHwQfSBX`M$UDu>`-fb-N5DdUK!tCR#kfLh zXsiStf(+M8=I4OH0Kd^qo{XGpc!dDpj|uv4!|C|=)jNK5gAZo8 z`3|65#S0kg_XYm8M5t)|5A|P*=unD{@W(fRsSi-xPH`YpcT@Zw#X(FxhLAFW;x!cA z;sx_6oj`5AAr$$lO{K9+&7;^4Vk&(X4W-2QNK)y$Xc(p8XlNyV1??M7@iw%z($=WR z^*U3H@1hahttR-$v=YCc_IV;cS*yg?OFZ!@iZ4dR%kg;0vMa5~fAyU0k-QKIi6BYg=e4Ze%6W1pnLcae$A!=r7b=B&zy9dOrP z>Gr7j9mRCE%cOEGrb@Mq74-*iwE?~15`bww16cSUrLBch7uIwDGmb3}v>fGfp` zXgS>!#rY+Qb5n%9j`<}zFU~JfMxtM$%0J_m2z`b*H@6|lArHSq`#1}t8y}?bdqpB- zq5}wK{joox+9pGPf|>B6HKM+W_9q%5;1{X$qrZ@ZEZ0K=_~gbn`{2yy+j)$H5KuE= ztNU4pK+J@KW%I!3HV@+izmPNQ`kFO;5$D>rv_`$%LWuB`VQS_JC*7^UZ^5dVUO}5` ztEkCl%kp{jas=3$xfooAfDE6{WyG8V9XNVnQ|g zXD&B;2A?F1^hDtAm4QW8&j`OLgMKTp!|EAfM?!D=Gwye$O|XaT64be19wT`O@V7%u zG5TBQL>QUr>30ETMn5GGVWgeuo+-fyBXo>|-(;so80q8*84*T$Az*y4|6VqFRL2Nk z{X+>j>OtgPPY6c%LSJ3ezx@cWs|WLFk3lePWhCDSQv=4A$UHCQ)Z8LORv}<72);~b zya_R~&=Z0YM$ULbYJ`!+_;3Q*GR$wIOCX^5Mu6``_?)3cZ3N>Sg^>ZCo+vQU0mQQ= zI+)-~1@JCH1ab6@#}`J@Js}ujgx~BVB{jlGcTdQOFv9QjamYpkw|Y_HegrdY7}@CQ zp8$54=n#UV4n4HHkl)68!*4Kg1Oelf_{>BH69F^cFsvBi_u#M|j4(356H+6LjPQhv z2qTLT(6oC2ezT1z@f3n-8Y8=+Ceva>yiwnu*lhI3#0aN>$@DxT-W2GM5o@+4_^WaMtr_@noXf}?2o)$Kx66u9_$aFAkQJf8`Qqis%`%gRGscvUn==Q^%4e!n-gOe_I%v9>t4h z4?xOjlW8b1$wY?{g$RDQP#`rXismuG8G@RKohF+1KEOlGw%F4@<919lZcpZn+fm9m zj+fbZFTkrlb)EKW@ooc(H_v8d0nTyg++Br?>_fo0 zpWq1%r$C~+iS{FSW<%~{vwyB7drY1E3D%3e_s(G?8&#oMgxXRRZ43G*t|gz(VN1N~ z`x70!Iv3Anq$dLM6Kc!ipKS}@euf7;0u5nXmd#;=4ZyG`_@Xbe5L*$DWltd^>Y`_( zU4;B>*1ZVGR5qIty1zhSg6)L<#kq{sH*FkF=#sFfkdd&_5BRyR+iIFSknpZq#p~w8 zu35z!XUDEt#igcUqf7&a5^NkAaCkN&PZ|9{f|oFyzzI6?K-Up`e->IoE#GBYuC88X zx|&T!exjF&4zw*VLKFXOT04Rb+-R(gAiU}Z6VG~D;*^OFWL2I~-gKCaH?((qmWaE( zWAJPtBc9u!K?L6y#@;*bD3w7n=jl$b|^F(R#KpIVUSZ;Zg+bIl=uf8F?+qHK+9v zgm-N~-Mk>&Y4n2#UKETQCSDRg^z;O;3b3=UkdZ#-Og)0&c^=+keG#6_ix84%<}Ah5P{jyIgEO@1%r5-&zl&Yvt#G_Hj#Yjc;`ZW?7ZJ5!kc-X`>7}2 zKtLZ8yAjaXgLBc}W^01KJbHd7$2`qHg*XlZ!Rs{g9-bS!_a4DJ6JEG!x&@96FDH!i zjCwx;sv*`O;0bYl#NL@OkG-E`RlH59g0@gk^0iu&wNE%y+uJtAxtH8S#_d%NtwbZu zcCT86)-IUOX0=AZabGZ>-l-^r5pW_V*kokfJ&$cJMDQ}=$WSOjfMtUB8__iG$QKB> zun}LG=wL$ktGmrDD)$9hi0URfg5Yi?VH%(gMjM)xA%yN@7tFVNi^AO5bzT;N`)zj2 z?rjJW9x}8Ip95lG+m4MYY|bXiiFwEZYUzUcwgB`z5E>K<=Es-g{cO}=?B;eLyO%e( z(KHIX5iqR?&I0TNq1&0mh4#jUdes*#ZtKiK1g5cJ5^H0_;={?=4AvYZ!baJn7t7f}(vfUd( zZk>?3V}4KfZHElGx!G>zY`0!$Q@tL88+NP%Z#!=Po^Gp9W4C9v+s3%(q0gmpZp!X@ z4YKMrc4vl0+>q1!A{V}W1~+I^uUQU!E47DHrpB!hY3LSYw{O^>-dOjRkXz~m;bjLd zc|vl@lNQ4F89w(9zEE<|I3r4SQ;j#D_0-cply68hW*kM0r|3EPnPprV!9G=Ps%I+A zlcsr6L7tlfXFef!I-F63+)Lo{2kw4u3g)>NjJrDLlBSK|ap{5!kYr4xdya%;*K?{= zhbayC$M{S#F}KjWR#aF zlcT;Vd860hOb=dJc(O{g8egz36C3i6F_Fbs3;r>#pN5?)!s(Y%n=xiwN|~7P(`8H< zohfTf8OtV%i5bgohS$D{2J!oB3OAu?j2^<s7%HJ17pMWJZQPzP8o})7C0F* zS*P|iNSCBzVkFZuu2KqeO}-41!RxN6UK#a5p=Ze3L-?ffvU^#kc#>M@HQjWA>11Qg zRA!pzdX_w|V%{#t9}Bml*OFPrv?*({n!Pn*%&6A`8gE_!v-74h)9qn4)7w$6SsK~r zQ{VYIcS4a{J=>iSa+?=mQZ}sX&cN9yJF9-{`gPsubj4OTJfcOLtTq_UIc+Y)6lvHR z)6Km#gb7|B{>VZYRCSxxuV0_hta0w0IAeY5gzDC--vutodcq~y`~Lbh;e2ddy?S+V zei}Bd)z$Ut_x+Y1F81yMiw}9`PJF{?c#Xe%wmq5e)7WED(ZE@+QJ3MxWIyYs~iUxBv?Jy zEtUM5{VM-q#zC3&diB5BZJ6n2a}4AoEb8>Ct@D3$!S>^Ryrq3x9!k0wvyQ>e^+INf z&7p-n~3(*^L7^RA}`)0U4lEk{~)hl_zoNQ zoIha0$~kk=@#B;xardjdUHwVFUtQ9@@1nD(&APeZ`qA(KRxs6LzKs=(omt>ykGa0! zdMA7Iv}vAmFDkQtG#&rr9emGHj(_ zj`MusM;ue$`0e5t@ME&D&&XONCSxNKnOaESR=iZ~EQZB_BF{mzGgjoehVl$?p2#^) zeX+Psd{o>nz9jAv-w`<%SpEa?6Y*c-cO*WLTlAj_WzbN?~ai8=b zO8%>4<8KIdzK~p|^zS5Bz=UNz#;*|AK(cu&74j95jh`UM#y=OxuSwXBsY;(A+4uuO z`kj*bK|Ad)mmHD&u;eEsKTV?l-;*AP#mJnM)SGb#a=uXJ+#$`!dtgh+IF%TE2a)GJ z=DSk7N*pR)D~=KK#mV9{u~0PQ680XDyj0{hf%WhjLYnajZjtI6@pHnsJN#H%qpD zvkE2OCf*_5FP4brt!0#7FZp3{v$$P+R(wT#O?+GA`)Sx4e~RCV zyg*SO6jMbr{-Nh9vrG?(4aJtCnHNa!AURj;CR)E*{Un?9SCHS#8_@dInxgaqakj{p zzFGfb@m?{}pVmg{%{)T>$0a{0J}jO5aknezY!?+*#}tOX4nZx42*YllZatck!h7rC26@E4nz*v7Hq}E?Y*qig>5jU3BY;>h(kr|H*1{a3F0(yhPXgnB;F?$ zi>t(S;zOeKo3%~ycJT%A74Z%6ZSjxd2jXGzh&x#j}VRe`1DMRXkt3 zKx`tm5Zj6ui+qKj_PU5yi+#mw#9`tM;&^eAI923NifGUJ&AL}|k+@P^D?TVbB0erY zDLya0Eb=!>w7*|GD1Ibyd4axiw6!WzZ+lm*9my2D* z9%65CkeDZq632))iIc@!#X@nRc&GS)xKvytZV(?8w}^@Uv|g5er}&Qe2l0LJL-7;w zsQ9J$Px0U4_hM3t*IyMy>sPC~2=UvEq#A6PaGkR5%a~#;xsYQ z-_{+{FA+<`6=FnuNPJ9uLVQMiPJC5-U3^zOApTiABpwluiKoOf;v`>i`B%sVtui>*h*|KUMgNGUM2Ps2Z%$(YenlPEMM|uahhoTge{P~ zM7&R2Cax0s(^T%y7V#-@hxn5Cs<>O+BmPnRK>S$zyT~8A(*D=tx1y8o=_`t9VpXxG zSWj#uwh&v37mFRmE@D{Z&udx#P;rzvM!Z?PMVu+l5$_O}h(+Quajh5;9}yoD`Ga28 z|C0E+_?Ea|{FC^Rcv$35fLZ>Z;=jf3#pLt6^c1m*SY50m))N!`g|(BugP7}u)z ziq=oqNXg^G2_k=-%=Ru6?-Pr~RpL7FH=^|mwq5eG;w$27;@jf8;s@ei#3LeHV3>A% zDgIOZxA?u7=pU>KK3HV?tBVc9#$vYEM(ikFA%?}C;xG9JyGi*bi?@n};_c#H;{9TY zxK@makBQb#*fWx!6L*Slh>8BfK9c^hcuf3UO!Ob-;0povS3pb^GsK!=me@dSEb`au zET1cO6}yXl#ew1oag;b-yh)rU&JgE|w~Kd+_lqmVwc1Emh7~*3qL;hNU?c=wCT*t(I-vR$@7hMvHZNKE7t! zbr$>T`I-h#`~7`S`72Z}Px>}v-*aXD1#Qdxd;CpnmZyFT-RsV&J`3BzJIixr@QYRM zj_7;h^V~qI`p8ohcEcI_d^!F${?@*W$JWIcji4k%2a3Vfbb~z;(5Bv*;aM&b&K1S`A3{z9;mzyvA~P4QTb!U zl1Ef6uT<67!95*xq3itM>7f79{m$CQPVPx@Pwq*De;l{MzT7f@rAy2FO?@3R%KeqU z+5c8%lQRGLNgK9xdplg=w68+N)BcJ(_b0FRt?`|9;Azcm>OXm9r4|QM*V2>P;oF?1 z&Z(of`SG{H!n6(awf2wOMmR|kXKm7&#$8uuJ&oS!SmvKtbMXshPU+gk9m@hEYL+Me zE2BJhRAzaS`~rtChE(*5ld6?!%)ufDojdG*RTroC{aQyV_zJQeJ?>x9#(NqI(Iv+@j- zO77I=Z18t)o(Oc?bt0u}qw7D(7RqlpL@a2=W&DW%ESLalf+x$(O zQ{OCbn>5-VT-Ew)a*NhygSk76Uyt;mQ<(#)Nx0EGk_}BSX_dRi}14kWv zOI;E;9dvw`Y$*p=e!yFo`+8_XWIovx_qCrc67KCTJ#ijS&Oe( zj3a1f%QD2g+44SOcDDF2OE_B|!Z^ch*^qj2xBrooyMx|rL7T4ba8A3PJMF8;wxyo- zr&c)q!^Lg)IjyeVhglkATT1tL4v&VnC}+XPN8^ulz#M5D@zC2R{5^M`aJs}F>H6iF zm1`aiu0eY1w@cC#$4L!FtCy3`K4r~U3%``a8%Tl<$MQ&*WY!RoF~Y_*|FFuphJgAN#8xO)7cw(_dfD_n#S`(dJYi@cjnY8Q);I+Rb~8y z`hp>(xLl*hZPW!h{Qe|!LGoAN54T)?dGB64oC$#>euM2YliT5Dqp85(QNmZ%ijCL9A*{BZ~UsdLd=U`wRZ3Y6rWoj_c9!SO= zf|E4g^HqhXb|-0(Z!I8SRbvqK|KRgI0=j%_qvGT#_yNNYMu9kfGZ2lpwQ+n1g;G90 z3pv4stn(Y0;1}PXiErXeMB^~w#XS>eO&+I`kKe=kdZR2}b-?AFo9_-h8>jNc0AHUk z@V6yGD!b0tm-X^Zh19nx8h=_3P@DtXu zJgFvb($e?^yW~`iw6x#FY*)lRUHbKo?>YbbP*%e&Tl#1#{S6X~VG&XEY)Wqyy3c(C zNSn>dz4#`)Rh7m!G$j9>Z&{t!1b+_mc$iZ6m{N_a+mfDqDP>dAlQ%(jGUx`ZHbPz8 zO?sstF{S?=E$zu)M@xHh=Nc$o`3(M;(%j?Ux!1!;6~6v-A5yDSL4;Wuj- zH==Cz-ji4Iq;wt!SWS*w({C@BlK+a9^yG?of6XiD$@!4IX17O^FJ-geaQU6C+4DP* zYW93JBW(6oL^5qw)9hDh!85_)m(#>s?gne(fHm={HBm+rHmfmFsWwey@W-TledMF) zJ{&OnP#4MG-g|NmWwZC5+>6D{(PL@8c;fqudjV#k*@y8+HTys_W*-U>$+THb1MZ^* z&jgF-(Zt6tf3Ivz?64-@vL-&F37gfJ_|lj-Zwl=2D_HLsd}i8T6Ync}?f2yNlui3R zc@Sjhyv6wQezfEv*=><(_B_l8kKRy3 zGHq7V>>0G+nPBlLG*RY`uqHNI6Hi+cZ_tFzYD^q4CeGUkJ1bDm+w3Z=!Q!PfF)L6TU(J~v znQTogv?i9*gw1M9Y&Is&+lRLBt4r_b-D7(31tfXn)|20*YHxoB zG$yJe*_dd`2uVPIdh zWM@&aJBHuZY)bu4X;+!~bT zD@(rKf&MUJc6bp|%?__*ggg8gBAGU;>9dz;!85_)eA~&_C$P+#*k?_AVom&uCTvz? zqGE%n2^N2ZCi(_GuqLvQY+BKZ5w@ZWBAGU;F)=u1g2lJeM8807+yt8)$+sqETNC%w zgw1M9Y%(S?o zjZ`y$gAEbk06rg)OqAhIY)pL42u=Ke zNT$tdOjKz^6V=<{>dhPb8t|@KfWPprx@~@P4IG!^t@CkxtLfvpM($N>@!Vf)A^$vy zKhXbQa~+ zuXH(Ig%OJ9Rq_o^W=$EDuuoNdj8?AW%gLmWS7~Sx6;+a)9FsfK%Y=_T+euT65p-wF zZEKAe;L>1e3+X6pR1ZF6r0|;jQvD;Q&=;7jm z@bV5MFc7FEE<}K1nseQ@;-;BqiI7PzUN@f+&qTlY>dtlBid$C{97r$|e0FS`4@Nio z(V=@*k`0b`)ye|5BG8c<`7#1rX%e5io_bCIZwVqW3r*l)Fbnapu{PImv!^D!O6J0b zx3QAHV=ka&>*n*tSI<|~?0LqGA?+vAcAKmS>v=y;W__0;n3A1j+6dM*AL<7oz}wJ5 z;BFHgKy3E31ZNMrmS}=@ATPm>&|PQdya*#bJv}ki=rIc!S!MJCh;>FkbzX!KzMl@0 z1Ya#jo3_qxf?XSpU<5{9Mu3MmVyDp;&WkX@MRuVlzA(`t#4zkQw8Urxcx{{)VT2t7 zz3m%B*+u_0+9AaE2=Ej*FT#j}UV^`qbig}O1BeiUX%-_FBA^e5epb)OD5LLBj4}FK z=0zCcJE|DD1ebX=b{JXZ>4|klkNk{qSRg;)jfw#T-P)L4f1}3bo`>OQ^QUd&M|-MMyM-6sO(HLn(3Z?ic>$rgFXR)#mV~-P#59( zZ5u>9?`e6=&FkIBOonjukeT3H+wjvw4DhrQ0S*LO{t*1T;^Y|wj73hCpy|KCJet=a zFgH02!S2RX?FMx`)EU~n+0HUQce8GU$M$XnmL}<0DGMI}GS%DVy0;p^>zBIqBg|2P zQ1_>D&7LR2^&`x~;Sy55Xq}$DxSSj$FC(xGWD3;>@5G&Weu_TxXg; z!U!*Y5CRcKI8h)ZM;IydgrM=H8$j>k!jlSAH_;J92m$`b=0zB3BuBnaZ)r|<41jNH8I*?%RvMl)(0vwn5BaDnP-86vU^SbLyooPHxFZT4r8zy=U z@isz5r}*Ld$;Dlh>qjWEuPa4W=)z>oM4reo{RqxtoN)+xUo?$ogufdxjb?=N8$xn~ zk!79`j4<*b0=kHxlSWt~b|9E8VuTk2=m|Rd!{{TtOT-9XEqQK01|k(R9sB5yFjCzU z0ue@d)<8;fgpmt9AsAt#Jp#@SmjYeADA5N2`R7F#xz5uQ9B`JH4lPmJM28U}1XSiX6VN<^Im6mO*WP3qN^m}+3EhD? zCOVv0fZ#f~En|dNIS6yi<&HBGLZP|!;Ut8AU7k;SAz;_%L>QTafU$1xf{=x?W|A4b z0|;*dVHaZ)2)h`YK-fi2pmhjl7a7@zfL+`SZ1bXoH-Rt@7)NklPUg4Y@YPXz;NXR!6+g^COVuqYXiI}!5Lw8l#x3iDqNp>de5|uW4*kIgB(Y2o3-|V+>*; z-sxkv36|$HBx!_MNcIl(2|LU40!nrQ*k(l8Uhn=e+O8A~IbO_hA*XxAU0&4I0Ih8z z2WuCTI*8Ya&%9_XBd5CA+91WdHOS)!ncfw-AJ2hX5ik;M#`Z`ZWy}oQ4DeclKDCz= zWLyy~Gi(Q<+*M?-#cLyfKU3x!Vy21q`jfEW3})l$vJC=G?S!5zyPGupVe(-d_Gm>Eyx}m=4hKA^*h3J_#`bbZAdTR> z!AR*v{>!MZA$T#t1<4oTP-NB7^0xk1b;b?tHKy!PVzenc%NLo526MWtC`(qE?q+e7NB)0SBhN9q>DC z%wr2r8`RtDKJ|Q*@J8yn1Gy^>5dFiFix6;ViTh1-2*HDnhwS<0o|=aoSqSffKZJN0 z!SA$-klqz`2v3c?;bl7>26=vDoQEsdboD@@D*_Jue6w@B0Kj=@>f-zjjCL0(<_&eS<1 zFCd5;@>^>^9{x#QFQ_MZfk8Y#@`ea`=8$<_JV1^z@u>llmn_;Z0eR*}$Kh1pA&b`& zKCZwWcYx&iJ|*^y5@7G~cIzFU*Yg!U(&+y3@h+!xM&mbLA-eU7om zCLck-#SKqxZE$hp2N4lFh7#0?1}fszssIy>_E=h(w&w3q4cq%)-hbX;6dD89Sevw01)(Cwt{O*?haT0~5fGQk zfxx?ZsDdgGZ>zeOAp&w)6{qSG=c;VGE<|D8SmH*Jka^pMapntuY~HHk%v+T;Z*9iihjK6eFV;x& zye`Du=^+~5o=eT{MsL8_mW1O+Rl<>Bp^4`fr0Q~`ihfc?Re~+5*o|>Lz(U@=Ru&W~oZp8;aWzFsL|OHXtC%UZCN&Um&rKTo?qkU8_oRu(HwzPK3w6GGh!72M!i1# zHK%J$1gnZ0sa9p%K?9$8wqorVWK-G7|EZd2YqP0o7;ECS6oZ3J+u=oRrK~Vv%uzMd zl#O;iRX^W>EdQb@U_Kds#MCg9mA&CbZDq`uFes@?sEn$g?5WEM<4)&r&6?5ZOjrjP-Ijl_@;0W*x@QKvS8LGA-;Q5${ z8Hnbv26#-E95+*0CDjS4ZAR6Pcmts#?jlqhMcSwwyLqxnwi=f5s)-&#R`K7m$vt}; z0Xs<~v>@^H!KyU-;~SN5K$vTnu^GJ}vd{seie9m(de*3-7euNOY*FRyb96?r(EH~W zq)KDewu`C+TU2?rq91Lr(1!?dkJVIZC|X-oCD@`W;aD(-r-}|u+of@z#W2^e?{MbU zK(XiRpBN}M$+nlxPv~u`yv9YZ9I?hlyOxE#T+zcsRYGsaaz$;$RMDZyLY}SY@ue!E zw_~}YwqmNNEf(@@MK8WFRkXKbs;I4)iXV}fjd$=ovEaO5RXpX~iI8vxp^CYY(-um| z5pRGOjD#}?Ra~nGho4}r2|28RHA;>fC_KAU4V6ueJ6+g<%tgCMN}Q}VDee@+-Jm*7 z#fJTIHO!%Fy{*|cDy|=6s_4XLA+NWiBZ{gA5#nxWW4WToB&LdvP8RZPMMo4>x-!{z z#d1Y$#Z=LW&qAK9=!l|97anUXmMdy2rizXz7V>OG$K4L7_8`P{G;>g$pkl6{IIhn_ z{j$j&?Ki4Co6*L^RM8G+Aum_7AXPh!t!Tf+az$;$RM8G+AqKNL9k+J(eqKE2fGbJQnh7MLRqThYTkPY)I3_56|p&49}>aBa|Wh8^Mpv z$p|S3>0UvTH8IVWx6fDE$lE3^e>23bu6>+75AhKQqY%c#>Em_0|FT;N;_DDLBJke9 zZt*%^?Cr)21Fx~X8t_DJH+w3(8{NR!ZnrxTr;f9q(=>jI@24N|0OU7czx~Q3gRmZg z_rJ%a8zxR4Gxk4Z4WY!_U#?mfuf;VRDxa+4+EEriZ zYs%PZ(4m8-6^y~U0f?g`>6iHC>kIO|-1vmg91QmW)(|=w$aR;`4uN@g8KHXF?#Pf^ zFXR>!xHYrgf?TZm!F4@Svzs@#s=-w`H@jHKA~SS_J0XOhg!z-lVU?ermo#YZo}b;? zO(|;D$DI|z@*bCUY>j_SyI{Q%H)GrtS0Muy8XA`CHpMDJ1ADr!Vu7OcJhOt4xBSUh ze%kZ7mAtis-04A2U(-|P=ekShVv(cZ5qE6J%?P=-W;bk#)qc`Kb$hiitHrprvIBl& z;?SIN0eJFCO?kZnKbkO|Dz!jB_W4xYW~REcg_v zj|E5E8RM|fiC4N==WcF#^dO7~xec)%i#wPd>`xBy0P+aqI6pZj}k z?uyyDz1{sT4`Z&o8cU>nhWPL2Z*VWh&>QDYU+C5hxj4#|wz|`IE53D3w)-BsH!dA# zMW1i#*l8H=j#+fXTe;+xoQtrOMr;j?=sFs4D`&(nWf8Yh$HQ- z25Wf??A@z#*E|QSnsn|pc9Qd7Sx>`TF+&Tfcx$$pRz#QApstJc1|HS^suf(!`5?M` zZDMPLv`tvYW#q`t1FmZ0#IM^CYeaO(7cMgrUH;=7tzFi|EH`3|<;2!2$)7y6AaqW4 z7|LmngYmz76&N!*9Mh5K?7r4YF{|pBrCk!2=P?V&m>x=S7@u>Ildy)0Sp?`mX(5$V zT(slYQE3==5$84hC)ZKwoSu)hQ~vvFsG$F{r;eSNJ!b6a>ElP^~@FHZIilW)FxET&C%=K;O5uP-Q= zdgJKn1?O5BH}(3P$HsNSFGTT6JKTNqyC`pKCtBFssCrN^AFlLfOU%bKZjBLw2)~rC zHS#3Z8-LGbZ^v37AATnl-ST^Q_W2`H=3!ucy%2005H%}%KZKuW*v+Q#%ffhjQ(%uj zhM_(7fwjj61zQGDXG^AI*1BMvn@yV#7pMMYRjirNh%s-o`S=1te7(Eza54p*#d@i? z_0B@vmO<3XxYTh%jA*lI(;>&(>wwqwGoYhA{In=)?_R`h8AP4du-7C`VWW$Y7H_XR z>=hxA_SlWKeSE*fmO<3X>xg5`L~S;04di%x2j|6(8-Fit?LCG#%Wyn!8-9i3{KF19 z$V_8+Mzs05clmW|s62;!m!PcOZ2JyCVdG3YgM1xqCeZE@Uj&KYkHgpx+s`=E(fz25 zxE=F|IxVjJb!(`cxylbcy9SMYp9re zoS$4n1t)v0bJiNR{wLN@;dtX38{I^n!zl9sp1e-HL7XDa5HS=@KF)FGFBaE{kBZyH zm&9G-J0j--%YPt#B7QA4$3$T|--#h7iG1gj^6e!0VaX?zeoAt=WImd*J(Wo0KVJ+<-&}HQ$sHwkl6Q= z=P7-OaD4t#x=cJCC6mA*pqCdqUb!u;E$e?j_E$?r(sC;2au|3+dwd@6pS z^s`F;UUEg8?6{xlB-&F;asv|O8;ci9-$^uU9iUtvrSm5?%s*V|<0MZI3#GqZyjLt% z`f_oD^uHmo-%pTe*K^YI(?H5^Nq$%IpC$j5L^-o&0rLG*`ZDEn(MIlXkVJZ>Wr($;=dU)YZz6V(zO&d-DB~f41*BttlS$-D5i_N) zE4jYdM*5CoSFwlEdyCgdZ`J@nyUiK^*xy^Ezmak9?&{e@E&2N$kg;#E+GJT_>W{ul@{VU;5P~>R&HDF8vPi6>*o+x!xM{8(;jW-}>M`EWPo)5B*t{ z<32D{AW^Q8SXKJ-N%VU|68+Rl`gW49kla;rU&%vB*t=G|S$gA3AMyE;7b$(QSSBc8M;wdR!JJZD)B=q$qUnsVh{tB_X znCScdTIxBzN%Yq(%6F^e+a%v9xmfZ_lH*(YEz)n3{DS0C$?r(sPokgyBz~;)<4XTR z@>$8>ORk8zxSyFM%GVGZOW#_&M7&(-UBs)Uzee&faf0;57d`A7U-aN@O20$AU-?!` zwm#?|m)`iEN4Zxd?^3?q;(qBrl6+V^CB5-6kMe#zADi(_a(s(br9WTt1!5Bt$E~f> zJ4n7#a(BrCC0|Rz?)9SaA&+_sm43UpSn2nQ%cb8a`C)Op^e>6VM?CDkqx3(B2bKPb zMbdn~2ey=)Bbw(5=yN4sDPAS=%SM*JRvaVdi<8A^VxefBH&E^Y$xB5( z>(kx_@lkP$_>{Oq+%4`A|0tU057;>-`E&7%SSAK}zmI(U;VM~GtSMd~HW1D83-Yy+ zOg}s<*HP>uhQ&VO0CA{ztw?`7EPsnwD9#hlc@9FpmC~;j9~HNViEHE0X&>$H72gvN zihmV95l@I;h+m6mMe|$)d-$%&*i92Fi#5e8v60wRG|x*Y-%j#nVrQ|t*h?HN4i!g> z_qNz?bXQ55=P&SO$vefj#JwV4 zu3>(@7(@O|{8ap0JSCdvH01lawel+S`3C9L#4Ir+Ca#s&PWldF;#zsVq&LrXusc-p zwc;2tUz{vX6X%Ev#JfbhX5KQ%{H+n&ZJztUEs~!We=oi)?iAk=_loa{2gSqU5ixPC zyllXPzg~uD#N~C(=6+`@uX{f}cn}DSj!M=SrkkKw$pF z=gFqhw-oz|1H~EQY%y^yy2qt|QhZ%}OQaJ~)_YR?r}&L%o&y=zb5lhzO-x*Cj!sBv zuesP(yjZ+k>>|=hDf15&6W5x{m)<-dA|IWYGC$okk>>djyhn10xI#3~iAdihd9%1x zq!(1$c}09vv}?_MAlW`Q9+iAjJR_RtN7ymXk6;p?qrfz=vRGTR&ykHKHy7K99mLL} zU0be~g~ zyTw0Gw z#W7;OI9W8$tFT)rd7gNec#l{jt`O~W>n6#Y#jWDg;_t;$(LT@am2B6R`%v=7;!*LW z_?7rCF>!6V6x`FYKhwo(Vl6Qwn&(~QYcAP5_d@OM|*FPe!4hMTqxQ#aTFU2zPTQP~x!zfo#tRhwy z?Q?$v$<4%U@gngOv5OcMdyDB?4`2gB?m&zB3%S8IAWcwrHBcfen?n%jZ zjky;kmx^zRc8$6BB%993Gt-15`{GTaii6OC-*jBV_%v~;-Zq>Pe z_Va~2$s@#HT3c?m^34~`=Mb=WkL0D|N^yhup!i$yadEr&tVloaY~MTL0r7qDkoY%| zj^LU9j94!IASS1K=_w*T#WQ~$v7y*RY$di86W5aKEq#A6PaGlMAdVL&iBm=TqG$bg zi1&(iO}Ukl?V55AN`6F4TuW}3^t;7Bh<_A66Hkcreb4&86YZLD>3GqC`f6e=vA%er z*h*|G(sw?~T_yGr2Z;2g&vd&++%(BE#Kg7YmPl{cj9VjlgP6Eh+>_EjBfcn>if@T~ zMSAmRdp;BYA)Xe?#BasKwc+UhpXIZ}2BKXXuC?TL;$>oIvAfty94rnMM~P#^#I@mO zNG?jgyEYs39s`WM8+wc++kZ`X+XQ1Zv(r{Zz(EAe0AccKq3 zy|CYcqFp1dn&etyNNgxJ7h8#mYsFn9{ng?C@fvZYc!M}WoFq;c{~z|w1F)(hZU5)o zbCcW@Aaq2)OOqlcflx#iL%S-{i-w}qKtP1h1d%3UU3C+JNRyyqTT!vQyB1Ja(G?fe zwd{(b>nDnm1#1M?{Xfr~XYM_TD6Z>%-{0@sfs^07Q{I^~XHL0u-ZOKdxJ+CjULzKZ zYs3xW&7xf^?rzEViIvxi+oA9m#8<@E#l7Nt;>Y4av0VIGvAft?JWV`H93@T_&leYo%S0~QL;dT;o5Wki z2gTorJH!{nzld*(Ti1B&iSaG5_Tf9KLRJ>B; zazxC(S-excN96KEjDJ#mPTVQJDee{jCVnb%IV0w;D%KW{6Qg1?kqaC#eHW4I98vBk za=9bQ=ZKTU0+EX!G5#WPxp>{2b_7Y$s(3pFwRS0dMIqI{Fc zWt%8JD00yz$~#1^(nR?$A{T3-TqbhOCd%#!KDlBOYs znqmjBv)ETWL(CJ$i06qj#Up!g5bYwm~F5bKC|{rnE^ZMY5g!$|iBF5W#8<@E#W%$d#E->;;%B1c`t5`-`b~RPw&$~Ue4J95 z$Fa9qi}^8zTTgltUo&^?&~9e?Xm(C^cIOT`9XsVjqghcp|8I6yR_D&0qliDb1ES!@ zr7i8-KjyknEay5cS*^JH0QV5Mq#T2m&T&p1r|pLa2VK5(ZLejq%#BGeg=3LeQS7)_ zlb9ECv!AO!rjc9h9E>b~`#|x+(4lbZeOP0A&_Oq&cC5ic&rRDE?sV{DcUq?d?!ptx zE??-LJRg5Q-<@&D&DhX)|Htma0kNE2WA|@JfBV423v**9?K&fNPHfi!r`zrWPQP6T z+-cPhxc!O_gho|A5Sq5@fCqXDCzfsQH@R%Zw7F%sEo@$vJne$A+om;#-V4f3Tgle)d`u63|x z{mmD175h6bcG@@xU%fa4|9uw^+JABC+XqJXOa3S|C2}b2_KuYta7O*u{FG^dP5H@s}I_rRwHsKGo=q!F|W03 zL+t)OXQJh=jFlef-0hVE&a_w1rmIkTM$W;q-mSM{1M4@AwT=yrtwigg1xF1<>(xN( z)i~fyJF#p<{V8QD(6a8dDP`fb=4C7T%_?hLKc~#=)}m~4{pM)Z-O$&uYr~ck)a0_u zx=ks&O!=C$Zh<4@cD?CPW@uj7jnZ&a>&|6K-CP`@J9hW!lYajhvHG#dUgrsRyMtv@ zrX4IhZQ<6k*uq%{+-?t`|4c5sd0LCIn@3G4YYP2MySd$FmEBsuLs?Sm*=4u1?ud}T z?tbQgQ~$C9ZtG_bgj!#A!0VRT`P{zUV<~9CrJv>Bvj=S$TI;O|ZD#@yR4)-=ZRqXUkmIX_PE&kw)X zjEiL)3THgA+g%shFlhhsRQ91$KYQ!$O_8w&&Rp1cS1;7b{YmQ-`N*kp%STT2S_eH3 z=Wg~Vs9ScWy1Cu=p-=rgi(e#2C7IpSy1CfyJY^Z#v6D<}90boqv{1!&zp|sL43fyOcFwSQBSe zi-qA1e*1j5d)_{G{n!K7P8+oU605=M#ooV==jjxrt&beHE(~|{a~#?|X5YObTu;sQ zE$m(dy8J-1h96>r?H??}K8b1FWb-Mc8)=0YtPvk!U?^oUrEt<9NM0eY)m_guAt^nG zNYZNzi=Ch2$C0LmR`gB)Gs2$ECGMSqz{kv!C9k{C&M4U)@8XV;a}r##KoYN z8;Pbw>0DdgNL=$ZolC15iJ!})b7gfSy$2}+3#Aud3?=DUBi(owq1n># zdP?H{42WIg;xfFLPx~)6j!E3RDnx#q>x+C{o;ER_cr(N*{B)BCt14E{ybynfgyyZ9 zfADq-k1T@;45Yz3oM6&#FKJoFB;WwM(wdbp8~C9Fh5%4Pr6n!-poOUx3BQEAUCv`2^^BuqTf0upMeb%B@?racQA1}55AMfOxOBef^$(|4+&$gkHu%& zK;>|3NIV8$3GhOLaV%h<$uyLz&hov?)4?Ph+8K!XUS>bn_ihC4^Sx4JPO+{K%&vgE zxM9LVVjMOs)wHOTo>#FUoa;03ixRWm7Cro|1aqnrtO@4Np6g*MU~DD{Jy&5v5~7YN z{A{8=HY{1OsFWVo99dcG9>#mt)xa8TMhiWxJG8L+&)aZ%{FXTj)ibUM{&IiNSVSM= z9ZU?xhGjw)nRV#K`Qbby8~yNbDLuFPLZpAyP`u1K7|z2!3pW8Iy?> z#ygz26&n_vTU1KVE2G~D>kfQ6)vSG*B2tC^qlSss3$yJ7X!&M zOX(Sf4QC6%FEX(6#B6M)P3iHE^WdxD-GmLhNW6f}6h;p}o`4W3rRPmw$S9@fU0=v7 zrRN|v6!saws|CD7Rcy$-sFWV|8iW%%O$hdNRE;P!-aLYR$s8AYuJwgTY2swaW2f3? z!qF%w)3_%1>-VIgL@qYWHcp(54a*QMD5Yn(FZgGPf2NN}bgNm50^MrXf{j zM@{xwg{Aa7gAIrG1%N+8Q5@l)dL!S2*Y9j25}j?{qCjUujS}bQyt$=3KL?u5GlJ)) z-`Pg6AC+S>O-WBJ(@n5y8$G$cFt?PRe!fsxN{`?7h8DuhJ3OwZi%RKP<_il->EYK( zCdORH%wZgn=yF)rEYan#l36Yi_+4(!T+`*wLI93bVJSU+mm4+?-U1WO46 z6pBk+sD|=-<@dD_iN1!zlDL53uq0czwKi-zrCh0 z&R)_oaeezD+-lwe{Au+0pjJ&vL#T2FHk*t7Tx`rm@@T_9faLXp;XH&qel`#NJZg-y zM~``U@ET!<8BVfkY#!V6R%Yw-Oh*mFtl=V4!-1%wJ=bfYbr{1xjXrCIw0P%O%Buhm zN)6}pftBN!f{y1APa<0u{R7eOQLoHBmChsqzw+vof8p5>?S z8%W>x`_jLM`k`(yd#=;ZQ@yLN=L|9zTUF=t0j*~HEfqscF^pv(eZN3iFtuG`Z@-&PSP>RUS*JWATKh^%X|SH1Fa6; zBcp!&z}$q6fdL);13Cr|QS>PsX%_+NAe$^GQYN@O!XydRnChc6)e_~HFYUVM>$E?MCF!-=}gG8f=gCcNl0 z(y!MnyKCkq)*Vukv&g~9SM;*&aHAoHV#5{NEu8?*WNb`^^|k2rZ)c;4t=MqkBObwK zR^emEkD)-^aS67WS%-~x3RVyoR<`?U;~h${>2c|HOL<-BhYgh=hGH|7;5C1o2_H_( zFy3LrY;3q}yQREbtiqOrHI7hEdN*N1C5X3-cL?!5Hly@2c*?Oc2O5ChG@Rq89^pS$ zKryc=QEXC7uYdI&Y_Bd{q>WdWjo7$;8LuV01k;a3F|G;z@;b}~+s1+Z-Fpl#+`ObR z>2Q!25&C(tD8q(l8G_eOG|#52@B@i3URW6kJCsm8s9 zzkcz>eOP=RHmuOqhbyVkKOGyYK=?H)KAkmt6PrnfW~2XWYxUA4tx-JuXPMx$3D!KxnZ*NRcLHkcKESIzFhA0w5YP#hmeRvk#&fZ49e5F7 zToe5DV}}q-f!{ZM5-EqU8T}(y+{e#@t3N#crM+jBm-MI$T zpj^WLJ%i;a8$sYcBAnn(nJUx6A_MhofD)k^4&ic45_CcNwHVv3$+SR+*b-h~Mz3EY}Ry$0|olP`s=S_@y4KbDS{Y(3K&tvB7*-@`u z_W=_z3v~6UH>jQ08gauoGqiVMyWXb`7%;$_-!J>59Q@msO`xA3!%r|j5aj#4R6i!opaWHQHZ_dhc^EH#QDycg(5Y2}kv4hqX@LzzLXcdtB5z37udlN^Zy0-aD9ByfhT` zeut88UeeC{n>!iPZEx|OgicJh4YgHXMStjxN_*-3Y|vx{;bQ5!X8K`&)@pyAYJV!@ z;EO(g-t71U$YzRYO?Un6sgeEZx#NjB<8*xf>W=>R_*-C**}*-=cs9PO(+LUi!# znG^Hp%$YfRPOB*H4()Qx{UNJMhfdL!m>W8O{G9w&(b34#-rhvo=8Wyyb^>O5o>&mY zB+*mnOr1F++9A7Rc21XboSwWJkLNALaofS0)Em>C=PzhGAje6rk}@DQl$Km0T+6NP z*7fSS$GP?0mdkKk?p*k79(bMGkswNsoQ*4l9Mo5<8%H#JeSFnt z^<56X%>%Eq1NxZGIvaNh0)qOQ1@z%9S6ts(_-!8QcpdsUFOGFK?m7en_2odHJ#K6s zTfbZ2XCC$ky4C2A#g&d5!JBR*Z!$~}81VzZfnlL_CBIR&}zQVob8@uW8Y<@g{(EHA| znlE|rtBRG`0}{@w(6TI#JvZSzPDB@Qo)b8+5binEO?}v2zGDj}+z**2yAG1GRe0^; zJlQxLacA@fpTY2Zqw*BlxCiJV1EUtukyhKkj)eF+8JcLf#lArz%J4W6yM{yRgsNgF zLE#-mbTN~zr+B(JNE|MX7YoFh;$m^R_$zUZ$e;eK&#mH};^X4)$t1t;lRQ^KI5e** z{vFBhOFk(1bII&O+qqg*q;9GHTB&wA7r%{<$X zvnWGTdTlFw266v;flnEwLF7m+v)YZZ>>H8RgOhMRr{vcFR1wS+Wd z2w+>u*&?rVjPEY?7I_b4_(<^_agu2I8RBP3o+B<4mx#X-OT=~JM)4N$4v`ipEcXfV zMe!w(*HOm5C6q?fi+GC7aQ3gd2M>kk5-u_qh0^_y_Tiq8aN$ zy6>7d(Tvt2{u8A?BK|{+;5N&0IMPkl6zhtO#3tfNVtbJ_*jqeJ#6O_$$HeX84)F!?W$`s} zulQZ_CVrv#!=i@^A@?&y%oJ;h4aLS{Yq6c!NjzE175j(-#35py$YEQS`_Im+c$xBD zC6C5ABcxUGygyQUrXlWFWay3ypMGhUSDh~+W8-| zBJP+h5g|87y#hb-ni+76;i*`Q9rzP(Y z|0upJ{#krW{4eoC@e}b2@gJgx-{5RdyRJZ0$#uo!MVgv2T|2Rpc(O>_Q^wo*Acsk| z^Ff;R1rR??;j=}v&H%!fOE&8aK)zP;N^zaIQM^_BwRoTSkoctdjQFDXlK6r6u~;sC zEr#*4iu)50GsRkB12HPL5$$}BT_txH`-rEDgT>+EIB}9#D9#nH63sdUs8{8A8)@Ck z`tA}duQTw0!ao*i{>$|IxkzS+nPNS$foSJnY$>_&yo;wRyuWDYTg;P8gJPCr=UH4J zd68Io-GL&7uM#(io5TmiN5pO7(;`ilS>Eg7UhzHA&YyTta=G}m7{+f+=8uSW{=^27 zn~5#OEHOvyF6N4r=TW5DH1&@Y3&iQ-T+z;-xJ>d2@oKS1+$3%m?R<%5y#kc;h{7Kg zpB8tByTn(-_rwpxgW_l6*CK}(Ogo7gVlA)SfS$)BZx<`ii})vnzaj1w?YxKwBp(th z&x`2c2Pf;BB4&!U#G|f@fb?w?Z`MbE+(mK^(aw)}rsP55DDhk|Uz{oyigU%q;>Ds} zH^I)2c)h~y{D^k_gxeK_y!fK{s`zJ-UkR{%?0kq{NIopO82e#-l2}Eo zE*>W~6q|`H#cZ*Y_zSV8c!p@_M;sw}q&QBr^CM1|TqyFh2G(zdc(qt0ZV)$#w~2R( z_lpmUPl*5bb=3<&y1uh#tnySkH8^npj7yFE$rjiCJQf$nQ3& z=QMG!I9wbpjuk7$hfeu{|4E3@8*9Y2C-;_-99u&u@cIJz3bV5S{kYTvPASN}^> zd|C>3tnW~BaNwon;3|BF+V#P3Z2361uwm?Zr(Voy{Esic`A7b^u8;9+ zCH%C83%l4w2jA8>&UOS=cKDDhiYPCK85*2|=#U#RqcNeRuKaNxN~uDGlO90|to03l z*9rU^PDy7T{xTv`IE0z_rt2dFdLFa1&Z74odV8JCq~R2fZkW%zt~46LpA+G54_~6S zXYwrg@s-zo$dD4=hQE=F@cUI$5t_=em+%KwFQu-gPAZ3F!XH+B!HD5hjxdGyON==vK?zIryA^77TG1BFbQ~EHp5Is?ZWUv5t81?s{NR94r>OYSn%X3Fi+>EUX zd%&d#!iP(47Qb7Xhk%qYYg*0aaE^Nu0`T<`kvX4#*5eO?{w-fG)pXO-@r_cF`CzGv zV?Ja`I-_P+-0#!;&yDy6Q>8DP(vuu7lK8R-KXUyKp!^S=e$3ZP*l+Z|#ikFMbHiE8 zQz`CDpLBRtF{e(z%8N;u6t-*xU#^5;iAYirzh@f4(fYW<9R!Jo5>yv*3L~U4MuHhD zex}42ST))Nu-8O@aYwT>W8py;ln3Krha7VXxks=x5WXfy2$VbSQB5R%Vw14{UQ4qH zQ)kT^KWXg5@pC4QpOim#(&P@qvEKF6xnn2)i`Hj--w;Oqk9(8+Sbd zg8FI&^xbVacHz^o zJ#GkQxpBua(XzOdXfxI`uzSwwXxv-`vhUZxMtwX!EHkL@3iQ*V2(ylQj^={lKZX5I zvkHaSR`CP>JM4Q}peVM7@7UrA_e1P^S|d5z#BblQb7msDulEPs5)(E*-+M2J+X1n@ zX?W5$zpK#?c%P!Z5BmsNTRe`$$=aMmBKAMVXN&wnM!B!pUmPapiTUDmagKPgc$ru% z8aoW=y-o7n;)CL&;&$;(@gwoDXucYPp1NpY*3;Tk7`q;v$0srz9l5Lc3#B_va(~HZ zNggfP*iRteG|JF(xx!Iwg>eZqnUUGvOcxc|XDOc~wiiu%BD|O6GsFQRe-bg@Nbx*z zrg(v9?Om2jHtmai*GgU~ZWeDB?-B18P5;1k%+?>lrhJ}dtVd7nzZrMIMU#D);q5!- zWMf*dxI5OkOLlhG&RtFFV~@KuJD#;jjJwoBZ^isy)f&V$ZuKteTaa9^te{5GZIQ0- zQ-@B-sJk-Mr)II+@r6TCH+;|wH(Z&78IF!Gs(xMV)pf3KP?A|(e^srO@5VA?HP#O< z&+LCr!N!8O3tldFmW8iNTK#f)=GN*rR9|0bWAgQXD$ghyTd=;sY3CgL%d)K4=2*>* zb#F*5>L1%3dos4Cyl`1|L3mwC@x@2d+$WD@xJm1tJd)xjmp*&MbN_H8>_!i#9&`^! zJ`4A5Gp?{8TpB5Ins_Ty)`g0fA;+^vLdcO^%AC(4^&gNctyp;uMS2&Ed$_k*DCL)HG8`!e>5)nP-Ze(D=D?Ocz4Zp z$KTL!W9vSA^|cy!9faOtH-lFeSFZcIXZB)iEQGfSU25^*CNpE;81x`$J~iXKk;g5z*U(;~pGKwh@BauHLRXCEw zr?(K6m%>R8IW376ZK>|>k=CVAq`x#R>Ar`sGz{#WNl#mZq(8(|{i&Z#pT3K!22fl? zk=HDDAS=VWKn6bgaNNOP!22?`Dz77%JA|=YaWSgG3z<8V;$I+U;3F3d8B$dg6{~VF zV~11ZLYY;#W9|rw>A1jE;f}dyQCtTxBX0(#W;&ZK6Ty`aBIaf?A{S507#WX^^1eAT z9(z5-37D%Xk6HPGH)8@687bdL&|{=0D2=yq$E8uSadRkP-W_)&wQPh`g|=btDDK+Z z6iWdBcLje?y(0rn>p#}J<>hwN4QRW#1TD40){Q2 zuo@E4lM)=+j8q)iO#RN0&9sUmn;hs2OyQJ~n52mdl2(Bjh^>0!(Pv{qeQ_Qy=HW2w zAY(SBHQe90%Y+XfSQ9yDjc-rEbfQTxgy@6KbBZ5WN{>xlae%XtNj;S40CoH}mtV?Nivf+x*%-0(2r~aS4ws7VLS7Osw`fy)F}BrrBwJnw*Eg_ zY4H_)DZ#2zV;Q!AN7Guo%+JuM!v24&vPaWPou6SF`~&nBf32qcL7J&G6MZn*8Cnt^ zRuZPa7PcW6IS(AadH!LE??PO6yfC#!yv_Y%9c&z`ZH;ZHGtV){M}6a`&`rI30=BzB zKP`v{InrLCA0~Fg*4pldU+efz_(v+Z6I5D=Z6JOX2inJPtbai-bCWd)E9_X8FI$}$Ke@Z1Gw`Z_3jv{PMqc2W!Cy(nC6bO|(&gANZ5c5e z+FfTP!HfvC`BR)oba7sCg9_zchAieXM$c9wTo5j$=L27el+sfV>M%!HMkzhC5r>dj zN>2ecOjyRoD>C7@B+|3NgpVfnoA8SkmD2NxAKnOcfv+4r-oW;PN_PH~DKS(=>Npp?SlctH0Cr4;y-=cnk3 zR)T;R8Vbm1P)Z?!4ezXoOl+veBTMOFk(kh;u+;8Xyddr*uj3{*Se@YzkZSAF77>b?7L>C0x z8=;A2H}mxQ%|3!)*M$b+8{-{8m{!7$bH8aTj}(O8{38f9K;SjuH00S}YH;>Lz>~&1 zn0OCc$hja)vPNj!E0)s3yQHX7Qq-L@H2{7EA0LjkcElZQT zH-LWQIL6>N#xUYzZ0KSHOAX=Ll_-5!qV%CGo!t!+Rwa7fP?p`yRAU(7x4@7@3k-u^ z<5=u6Y&c7aEyg?iZlIP?I-ID34K*gx@B^5^XZl z_C;J^P?~YM2PYCuybQ2<= zIU}HX+0sgN&Io8;wltu5*-~gRj+%|Ff-{;>!(9<*I1cU`cQyX*#fJCgL<8H#^!P`7 zOrpHnb1Hnxp#?Lw#LWo3m#)1Y9GoUYeZUz|6_xD<5LJ6K8y3 zkA4>$E&zmoQC);dUg8~jFx!G3!JssPO@W-bD9t!~=|*%P1n^pkBm3x5dNPbKe`zT_ zey=>+_9Tgx$xR&-Ntw-yU4*a?tBN&cC(#Ev)JE~ z`7FE8X;k4EwrS<0e2}V~_&un9A6v8UOw4CQtC}hKe0ZWw&8HB*9&zQt^h}$9Hf~ud zJ)avJ9W@72XPSdEl&FQR6&??<%XqjlrI~CdKPqN+XTD?W$K<)#TJy2*2j*dVKEmNn zXP@L+@JY_JvR@(#Vu|zpwq6u3?_A{L<>N#=q5Y8bOv|o#tn>?XDA9bzCHlmWM4uRv zXscm~orquTc;!bIgbSO${KI>5&;{i>hzptdPX7-~MD(rq0oh|`bb=yuv8bWo0#Kgh_Hz+cg{A)LV#oXrkWCc3!o1Sy}!2n+%v$$E)7GNdss= z%1+)jn8M}@%zAXy(mZdu8}+_fLiY30=6a1@_42#-q`v;mkIy>QtGdO*+(=d1d1Kpo zHQT|{(3=qT+V^XGLdVvP8~4Y2N8Z`}yw9LuWvE>!3?r9{Z(1h7m?j&xG;`*%$s7#+ zbguxjiH9Id*B!$%sHmyb7rX6)ai5cXHT6mB{pxy#JQMFWX{nI9PB|U z95gR54~~OkQD8;;kLkk-rcOSZ5z0}FG79_5nd=nJoHN(Y^S|0^#~cQ8fMm52wA}Ic zKi-f$M&DtxL&F&!+gY7E;;%ijaif()F6!`S#wox&Fj0yaq8vNj{4H<_eVdsdV|8OK zfZ{ehbH<-vI6c3@R5?L&8%~lFFwUvii6{C-VWxxqoGfQ>JH_=oXgkv^a6RYcyjRue zipZrYmnC1GbVc||@2b!*-CkAs$n($G(O?3fx$VBE#eU}2GkjHs7QwT-?{Y*7dzWmC z0H(9=^DC!g99;`+5p2gw*9K`Smm9nV+Z*)|r2~vBK!pz4N+HCS%lDrcHIKXDQOC@Q zQwJe@^FV#9*E!g19(bKRMDCzR&c^Y5sr54|iUz7)Rfz&|e7_nj_kkvO48k}&%Vl}C zT>b_L>dUSLod~ne#w|oZP+zll{<~G`OT%XM6~k}y!0QZwK8{~oXXCCxKu}*!Kp)Q^ ztM6v`Z64|v4}JBI(#{-Q2m0lIM3LE2W1|Gg!9m%%^5%~+A z=`Izo5^2lE@D1W^;(a1t9W(xUaku!o__p}I_>uUfSObm6{EbESRm!J|W_}RJVh_YK*sI|RM&E8NWQfpGKX z3BoyS%Y0!Rf0mz0Lar&fiD>5SKzy!bE_B57X1*HmJjoY|my6elH;cEE(0`xghb3>9 z{EXyXlK&+6ZOLf%3U)E3pP@Z@4zOM8iRPy&32wP`Wtws!cD(}{E%eR{~&Ld{Id9(_*ZeC_^D|6AM(X`{J?&q z=_im&B_9&a@kV&%`BltuLHKQKU+{j>92dw{anWXY4bjdM!nw8?zEHIDgjAlt<0M>C zn6ABeiFmnKdAk^@dfc^(avMBSMqz}0nyH5Q7+leV?jF(mRC(|Ao976;cdliv4_}893&1C zM~UZ(Q^fPcx#9xxQt?WWh9oR^qj;xykNBv#P24H&7VW$f?@Iog_^C+C6zb0qYl?QB ziAIu}h^@r7Vvg8VJXP#1_7ew+BgB#7IB}9VT`Uymix-KN=cAx04eL)EX>yaeS-exc zM|@cPo%po4L;R!oviN85Epeatk@$)Dh4^>T#WMoyW9O;JkQ^18i6@Ee#m-_kv6mPV z2Z%$&JaLRTQJf;q5NC@Qii^b+;uRu|k67>Z;!WbM;$7ms;v?dt;?v>|@sHxm;-AI0 z#QzdM6c37@iAThLh{?DYvwmq}b+NWcb1BB#`7qi`?kIK>dx(9-GsL0dSt1RtsBfxR zD9#m^i7Uiw#A5LV@ka62;@u)mxTyar@ps@k{ZD7{-r3>Whdp3ZvXm zY$mo8b3}ee%5*)&zTyyZgm|tvL8O@(^UW8Rh|9%aioX(Rh{p6ciFb&1i4Tdt6}OAO z7he$Vyco1(qrSh2`^7TxbMY&YHt0;BEY=k3ijBl3Vr#LT*hxHD>?Ov;0pbubPqg!5 z*m*Gc+uyXCc#*h5yh1D%uM;70<{l=VZ~&>(ECszZGHpJn=&D7V!>|#)(Y# zj`)H2vG}R@rTC2)!XO0m;Wp@maLu;Q*APuO9-|CT(eovSIm|qj_W2uj={ZNWOYdk` zq|P!{=<#)_JDl9X4>`77`d&WVV>l|upe3I9eY^BkTgOC-zH-J@S(UN6%EqFvGIIMC zWUhS3Syqr%)S-`e(DiDrjC6YXP_q0=-XZ{4;O`3 zjVO;a7*QV1p#AwTm+dLfU6#IXXL-G4Nh_^#O z?#S;?>=+Ags1tko$hL`2lM`Z2iMujoePrERxhaQ3pEl~feSgwv$)8qBerCUu+vZ4h zlk*&t^V#Mn#cIXEu+QGs+iB7;7AlEsOj+-(OkVe9Zqni8PaE_Oe_AcPZGX6Tuk!FI zPb2>$hup}Z{f&DjuiU;rrSC(#)7RJ7P_wjYpH{K-lIk~nesB7^`_Kw)jwF9QX#dA^ zCZTrQdvA(`VI{xq5~o?URVg<_HdHNXc{r*3=G@-7RM zSl<_I&=+lx(K*t|Jtb{*>U9|<$-6Q)q_0X_pL)aOeVL`t?W-mGZgbBz$0F=rh5q1j zF!Tm&r<=gUAJ}*E_m=Ft!}IAsz8C(&#v9)>(6pMr3&TlJ;x*@+e%N?F%U>j+6#jq? ze+j?WWiBJaNpAq*!}#NMz08E9@JCQMpCJR*FeH-nDk+{4^3rN+!&>2?-;i)KGJ<%6xoT9ZCx^ zbCvm>u}(<3N#sC?YQBpkeX# z)?uq*ZJ8&yrBs=g5GtVFKa5H4V* zD>##8-K`8lTwNMwUJ6e=o8Y)d5wZp$$jA=25S|sx_{*Wp_$h+!WX65)JWbDE;Nh>( zdN$>8>_7XBhWgaN+;r|WMOFi2jRsn+8x6JL;pN6Lxm)uLbsB8KpUv1fNKpGTc-&jL z%lr*myE*sKh@2|1cAL0Zz`PBZ?RIQm##*-L>sD;;z2|Ya#v$lcMAjV+52rt@XA>MZ9U)&cpWn0(!1FjW-hUS} zvT3WOz{93(Ne`R$6nN^{l%{d`6B92Z*tE>eJGJ}ZM^*!4jfTlq!-eo1&r~M&wI+9i zHzDuERu|Rr_jx<_nbR8jO>4y8FmVH>dk@>tc-m)~_Al|YMm$W>w2u*~$!YKb{(Ov$ zKlA-!{>-dZa7O#Z7?C%gh9;{Kokm$m!(aS)5(`IpMNCkBU6+azv+f*nmC=eYp!|)1BfLLQdXX(@hx-O-?_T?>{G= z%a{2pkaxF6sAf~%+5UUKi7_9uB(=ymqh>Un^8wk9Va$g$T(6uTyBHy(uIp7zOdN#S z*UWrCCa$VJk}*Ox*FB>qb!9fj$1&~kYoPjfetT1+;USu zU6ZS?=cSJ{b+4P`WY^^7u3kDOPGUzqE=M8tnRcix*HP}nqx#&nXN*}kxO zDLpHUfaQVd;nO8-KQ}K;hW$E)2+Bpi%}Z%0$1?)4kHT0yRBG+;j8>#H&X&q*v!pMu zA;IlS>7hPYwJ(Y*hPfb5W~#+{+#x<^8pmpx6VEaBdF%t}rr1@X+-A8amNI~uU^}WD z=9YaK1lV*J0qd}3!oHJs#mz2oiebjxym9I62;FKDokeUj-r>&!uVTxD!J|n(*QVc# zP-vu5UM<@g@0eV`FMSx}>0;Q-_0$<-n+2A!CJKN0VdF7`#kCFU4-eZ1nh9n?Gi_R$ z$Zf2*nahORE`ScVX{lAh&fqHsoB~n;)Ax**U8ue0E9r zam4Ki#9I}~j=g&z60R#Yzh@66)J9vD2HI##yp3$)B+Mo@xM`Rf*!Jkf4=hc_M;jEl zqkaH7Jq5NwJOzc}@c^WtFa{f1m6(7H$LN8j^!Nu7D_h$G8COG-Rlll;wN*`V7W>se zp~h9LZiLlk-+~r=g@VsMDD+DNL`o@)gKDM72o}sN8S#^fhkF_}97W=w@#Yac`ku4E zjpq%VSF8|sn5Nq#t#!?^o%Bq{h6@nE-D4Wk?>_O9qZ?HC$7^`tcx??HudVUp6*%>g z%{T_}G88zYE^$fS+;Lx*yA(rQe?aVeY&&H6c{Mo^v&maU&MW(7$M+QAUTk_Tq1)I`K5|_h_(5fKLYiN-a? z_rV64`;1?%f2-?^w8>6hNq8im+^76yI8M7$XYtC5Lg4 zX!EKihs}XYGJm~4Iv9@bH^M9I?qwEr@TLRNW?sYY-i#>B^Ru&?W_ua!wuVFA`=Ndq zuiUh_9sHMi?ciUrxCs8QLs8?$`m@!rfGo}K5&A-iDYlu^dyIdJN&SjRy=8F}i``-s z+6B@6IVj${ZD~92b*CMdqpcD3Zin;?mXc}S58nwu*%xkiC@Wb)KP>m*|8nu%?30>~ z%Espd?P2QQ2_G4>AMDM^^In5-|8+9%_bs|w*}1a+pimQ@`@(W!7m}QJNX4x*zKcydr(nB!VDex|5ty9;D7s(m@CtK(oymI zf%w6RcSe7HP>eKe{?$ReiOqKg`l28)p{BkL!I9I7!KORp;cyQd(7$K@KK|zk z=7^gFNND;YC-WT3G2-}w%lu#kVHiaoJGST0)3SYZaP+OoJpc0v(Z65MTxb6_MG*arQ!a9mp7dj@yXS=F;Y2Qm%#a z`#^y8ns*vZAh#ByahC)Nu<6c2d?464*b=|Z^*)>bnPi=E=fFx2-Pht8J%%%s6hp6>Yluc+oNoVb_;ZTxF0pK+5M;vf1ujV*UqOs{lx*d|)pPBD1 z@k8+o@$X_7?ZtFvc?pm|fhpG&n~Lp4{uXBZNU=cVt7(SYxiU*6KPEme@}yw8-lADk z6Y@opmy@_aUnX8f;>0vY4&aSScc;R)O8%|nCnP^7`E`-+xLNK#$)Ag1oXpg3Y|X)_ z8a;3Aj_({l1{nbds*OJ^wa#P9179a6lC}TTC>_;Mem}qV9$0**|-Xq@H z+|O0`B}#v_Xl(3}Zk^&cinl4g!dj7N-`^|TtPP2L#-<*8li`T}FU5aMVml~)MPh$F zJOi=b5fX9@$@NI2X&^RNe0#;4wIGq+*w!O|Z^aK#ytS=An=VR z{6~4O_?~z`JS2W2a*&wm&HWIh9TepTVpODI7Q;J&5lruf@B?2SxL39`yWC^2_3%#ka)&5!f;6n?9Czi8L6uKfJ)n&R!ZeeX)P-}e1Y@~0x}!Yx_kx)GFNhhuoWc!Frxs%|Zr z_Ipg4lJY$w%^@koZYTB|lMEYft5vbo=bG%=)X*I=f#BIUINSW(~kTf_XFA-^CNO`qLOGC={h%`8){G>=bLdt&C)MJmE!-2ucgrO=-;g5bn2Ytr#$vI zD_qYRF8vxrbqJw$k+lnWST+N{fDMud~PF=Po#>$<>% zq)Z|rN#7vMi=?~=XoX8JoN^@-_GW@st(cLIFJ9|Y=siGh&(ZXr%ffn{&t%~getn)4 z_S{HKhDO4C!t%o5evFNTFGpbVVE8d}{=Gm-_+$KyaJGCdVwqZsc+8gnC<3|eWd_CM zq;eyMQ_rH9A~BMBC4wY|vz+2K9S8ebLrmzY34iPOZR`GQl&V=Y&I>i9@->UexnX6;`8 zrA09V)~sn5SH5yN_6ByS*ypS8pd3mo?uFn?-#C^gxH%c!aUxewO3W#b21LL1*U02y zfS*5g;*R6IFxep(9k94z5}vg%t{@ou?R7D!3#OC=Rd8KQ@;Kw48zF7RitA#c-pFVs zk@w3TfdJ#oFE8W6BZnN51YJ;O7YjKZ`S*ueOHAxGrf~MmDYM6)ADujPdj6bf%LQFK zw;D5L#=Pj_e>c2Jr zU%kL(jaRjQ)7qJd%f!$9MLpW+cx<@b`_CI7pT&ZX_dL4B*q9DK-Hof9j&XD?u<<$g zSn0BmrgFJagjr|rS8WjBKZ5!(gYn!;{do0@Td2QL9)-=;0bXNJ{Ba<_de1^!P+uPO zEkh*rC1ayb>f;lp%>%EQKk5T|c&>`;;~1#T1F!Q9^zjM9Ivckd0YQDY2lQ1z zoUPv$_-!8QsEUYDfdK2h9dSW@k3b*WmGwiD$Mrn|Kl89Z&=uf!4#(lFV;r}qM4OJk zS!dZqietJLuwfSqZPaq4JK8(_y-2|H)^VN__BHFczjSY63+~6ZK)di!&bAAJ<9!}p z^Ba}p!`9id$iVJ7+t9eV2;{Y^1~%&B@nM`4NgcE>K+KL5dKrl6WBDU+|(`+ z@ZYg^=7}hd?cqDNc*6aVwKH2GIoq7~1HRKgBaz+LdyG3~yNS;CzUYtNS@podC-xt+ zZf0xb`L zB;O+WeiHh2Nk;XI%=3xi86x`<<*3+9JV|UX_7HoCXNUtt{-ma!iQ+WT90!D7AbFu^ zjt9aole|VW#{=OvOE$*^ax&!uJ)H_M8&b7PTAT1;Ewrw%(0-(b{WoN zj|CmX@qqj8v7o}|o$nh9Iv<%`P9*s?w#v?26ysw-7eHjUNQ?z#QNXWtC)7L-e=#id z3AA8Xh-U`Ig2ppP9$UqZ1@RDKEa-J6i=^BRB*ucwD=>~eX)NdoCi2IEo~5^wInH^| z86OMc+b}a0WCn{O;UP>H4)estSkN>iO=f2bFReHh^hMZ=1<@uYTpl*#Ef@=WADP2n zh0BovGi0O=X6#{!kyLi7@DU}(SkTps{(JZv1gE)K5Zq&q1+l!qSP%>F$AacVNd}Ae z$AY#(titks;8+mfN&aUn2uBS~_LGbS@rHq+9y8>lp&m2j!yDFr#)$sE9V4=z)qLwK z8gz{KS2SLQuV{GbcJvj^QOAhBYZ%CUjiJ#W|KkmR3@ASKU`7(m@IpN3KcheSfp1*m z<0C&}z{ecv3hjFA(I0cf{_Ueb-}~qa1JrMg4#h{Hj7MW*!Oxr$!$1{v2gfUE*?L;< z-rb@t`IXLaGs-)8=Im(Cp#!3QHPRa$JbUKE{5f-G&YsgMic#NoIcD59t4oJY(U!CG zr{|BKliw;j8d=)g!Qr+!W4pGUFnj!ri3QQw`4>!`gSAki9kM%S=X5#8>Dd*h&Ug+L zJ8nCkMZK}2M*f1f19F_?Dk%d}Lutu1!nNGmZe6dQdz@R}J>F~JHVQRy|EI@@e*PbG zptXN)V?+h`t&E@ZKiL>jA@nW7b5C99EPePcv*P!Nia zJFBnq7}4HLZ3ZuX!5weN8o22var!D!|$LUGDg%2%4Ydl z%wOu@R(XtQ9n$@fF``$H?uU#Kl?U48`^JcPa1KgSJU_AtU-xyIn zG}>UB38bE*xnTHz#)xWSRXxA0_{jawj}aaFV-SCg2)BZN^BB=U)SqJ`qs0m0RMCu0 zApSpNM1DJ=St^XF{M2Jad=1Yrn~~ypF<<0QamJhD0WOzp$B3?#yi(*?KGSa$w~7yl zzZ0!J^S>~Lbo4oJJA8*dQOC|*{UN7gk0G7z-;gSeA%$bKBx)E-bL+*N#@3R^tObF6 z!kxgaiobZWgE4mS>SZF)C~h*>_3$_!PpH8u2*m`aue?sr!0WRq%aEFW;BFPG9|zi zh>F6aAtkScKYXprG1ipuHvElbgsUZ`A~corjE1Wx6;T()gRWxA8cDn}aXg5lo#C1i zBTn+ol!Isz}|JJ z`NLx}v$3NfCeWDWeCOB(3iPMMh>sVUqFCmSvCgSjPDNuJ7Nr50#GuPj%(a4}Go~_j z)F!^Bs2(cgqfI}b!5Lopf^%&IuT1p+d+m341b*fdZJ>>g$A(Ln8J7V5N9}il$Isq> z+MrJUBOhxAn-|>T>~DOg;YN8BHtvUY{o&zLk9F3276O9$c0k`?L~@Me`^IMehBR+j zWuVo!AmC^84%|K;qDRiAt2{PS5BK$LNW*ejAG;rw$7cA=b`4WT z>3~%R+IArWyXRz~adQ#KzW;q=GllG@N6{AuGG1E_h5wArB*td^_WdXAcl-y4W83fW zR-oG``^Jy4-(lb5*h{v^A6=CDioBjt9wz3A`QmhOj(D+X#sZM9ShD%;5BWC9cZ&~- zkBZwx_J5YkpR(j(F%2D!vbEc3L>cEUUYQsgJ06@kT`7a++hn9aO|tnG39|WO0P*IV zWXSo7pC&!leh0-Gy*w{jPKL<#rW_TUi6@EeMbn;0*Guvl;sEjgV|$#gN43ZKjf$IVGP zl<7>kZu08s*H0>*T5|r%lvVjfPsaWbo49`B+6@JJ3Qm}MZo%O4%&RA?pRy*kAiOH+ zy5#G<;xPrKh;v#x2mf;Mp7Kq_d&-Nprx!(5N7lZHX))4@1|7tqX}bMLr0H9A;ZO6{ zp0xVSa%WuYlA*EnvF%5ao7Onw^y+=c@!FT{EPrIv>vh|d?D?==)3!z7H9O07EZeyO9k~A4zsIp`|CZ*z#Ve`+D83#Z^mAURAB=l;WM`A8hJ~{N0*{H|#9m zv1!kT9o(l;>tsj=H$8nMDV~pdQr7&Ugu3?BeZFpHan0-8!_Mb>KJ4yRUzxP7M#+;% zja0pm!h5dV8H{>2eX~50>#cFu)++H^g!}be-CApE7oS@6M%|s|<(qmI@A2(ivyoN2ZCan}}H{G}m`{u5xQ?$J<_or@g3ii0`jci9Of&1m_ zb^8{bRua3tPsuLi39ossJY2X9ZT)6>#xif?&hqGu%*8gu=00;I;xgy!b$oc`RPrv)ABVqSdXiD11y?+K}2V3$*wB+F8`XxhFA73=Ac<9|{ z;z*u;Bh!c1q@lEysBLo7es?3pO@=)9#%C(EC$+s;H)UPJ)qCm=zk5VUqmmQQrlHUM zGIy5eF-N?ooOSovC9l_wmM}JXV}oMW#~#)6bt!9~D~}9*yKd9#-EJP*;<@sS!p22S zN-_>*W~3gv@K76=-jynbNz^nHdw-TrzI*`fcUmWzUYQ)j6|M zW|n)(#MSxNO(>dNlD?~8!=zRDYihlJN-Q_lKDH_L*L^r^w=dZ@Lu+4|xeUy8BkcYL zbUA!EG5BO-B5`qclYfU`&s>o0*y?;lVr;cBA~3dkJtWVJx^@}Oh;UM0hHT?4pzHZ2 zB;`_u7~{Hh67Y!UIiU7&Z!&?m=J@A2Ts5dn=IiB}==~tZkJX-j9$JeyuqWp^+Dm7GG=L z%bZxlihF{uHA9Hv8dldc7G)VR61j)5k)-t|G1jmG`L!mkVN=~r`0Eb9AH3?-bEx|; z@~2^db|5`%5tIHbJnkSWWS!H0jXxN8g*cPq6pBMw8IJmAn6;CJvBJNjm^UNaafegn za5%&c5(h$Q#>jXqf6YL&v6tXsKVt$Gdm6#4M~nnTM#@D^GbSLVk}#cxhizjMhH zyFyF4zu-uE;3HG+X~iW|sw5UQ;Zz7!f57S_>_1p6;&mLVgyZiPd}m59{@bgQbTbKt z5H>-@)k&fz!BB!P=P~2|=_C_lko$B5$6X`%FxX63U5V96n2M!@oUGFK!LPBQX2dtf zJDlLNC8j0cvWT93*r1On@Wb~mqKA|2;qzExogcno2|cvig-T+tA6~wQo`ZfkfpJ$~ ze-1nazVN~lde&h>VFddXDp9nUo;Q7A&EjMR_$KIR3S5=(<|L5FuliVzX0Fljr7s9@T z01+cb2@t{}2m-Pwl|`1I2na!uvZRQLmfElgsKBL4m0H_Ui;9Sf7A>`E(W=!JDk@bL zr64Yp*!ur`=6vSfLqt*A-}m)zzu$Rf@}6hrnP=wAS?@W|nKOc5OL#&+(75Z2NVGAC zP0<8$iT6!%5OEkW2}Rc zbYf_t6C>D(TMWMZ;14mz_;?Ay_Cn6} z;Y7Q`6YUO3Ec|e`d&G2M2=SSzH$6gfvY2G^VVB$p(|qv=k4$Eh?4w^+n8P$3SkN@# z57dyvKn>?o_#684+3LA-ITC!LhDRwJwEIohFCiXAMAr@3XJ`;zOmaA})6Y!|+3>`W zU6L5G;ejEWYun{EG93{cKEYmM1#O<2=AxI_z(fh83D`Ns$0$oSl$-2yzL~* zqm1R@M8I-Z!1DI$ma_tuw+Ah6k6X@zIUc<*`UI_El(#G}X3bh1#lhtIHu+2xnf#H& zYbO8txiKdEoqwcV^+q4|Ot9_nFiYDsijO%Eezj4o=5MK7L=)H}mg0*r_)t@EPK?6A zct%l9jKW9p415HK!U;sI10v*aP1_bQ!4^CmM`E^zal46eLaAN1_@a&9s(NF_iCYh< zadQdBC^#^xjO?IcYGlW3)k-AHUJLhsrHCXN3n&124FU%y{R7EFc--)x>Sm&f9I(MGx6jEVSE20n1nh52ZD z+K61_qRTU)EHM9bO&L0u=hd3%>kVjYq$2#!^;$>02~g!nH?TO~tRgQx58vy6ReZmr zt#?MAch$shjlB9uUzG=(%g=h85v6cOk@*h|r2BbS`T6#LeP0LvCmJiL+|Mh6CiMGV z)(AE*cKBMy8F}5>PHx-Ln^5GP8THmKnCKnC{B{$gUhOAJnuGSedtW| z()xMzFz`j)uWO5i{!#DTZf$RDi+?b6Ztj3a-V~Ih&$Xi7WqDrbi5E7>&B^cY&6?;9 z>E|t4Fv5GtEy7XoG}Cb4Ij{fWkFv=V%P}d3ozB63oP3HIIqb98^0AX9IQDV#z>~h4 z@a^a6D47}jg2I2bBY_!OGxT5b$lUJ!S}9+g$m2^~0_+;}zwCnb`&H9&RGW|E8~H2P z4#JV-+jt6CABDKzfj$Lu(i8v5lcr7>A2q!+Utmf24gBXk^8dp77|jA_Jf84Q`F)Mo zarXOneP6?_ssDTSA0K&KRhZBc|M`p;qiq5&!h*r-@mUwsxQAf^^@0~G_Bw_?J8T^) zjzR(FPPM_74MqkYA;m)h?(gv}*Sg5T-6V5~#D0xKv~`elIN$P4CKPNLf05cWi{69Y zN4$HaV9R*17;Ja^S@;ov47SVmxE$mSh_()r&Y$rBJj#TEE#r;NpuJaG;c^gpw3mix z?X5)G)bF2ab3m ze4X!Xw1zszgvX4p`p$+uRG)4R4y(sr@R-E;%FXj-Jdfr!z~|g&hz&?M*zm4%2ukgg z-%-3k>?QUWFBbV*llHC@;#Dy_m_4al#F5gO235qDmOpaF>dW8o9zWMk53%WB9YH>DD#{~jugKm z^5G8iXNq&g`QlCDt>T^HI`PNiPeeWrqCFmq$=`^-6JHiz6ZeR3i3i2Q;>Y6OMLx8l zUGvTaSVJ=3ieP?2(fW@xm)u(HBz6&v9|`Jpm(1q?w8JMlhnzKM^;Ho5jb(C&g#Q=fvuB@b6asUhzHgkjRI??BC~NGS11A&9{BP zI+E*&jm4&7Td{*!ES89;o0Fdpn%Uko@mg_?c#~+p`2)S>l2?iMi1&$`#LXffUDN(= z#a-en;$Cr|_W5ovYu@&2PT-gEBief1dQZiWi8z#S6vZ;$`A^k@MiO zJw9D0=ZTBN#o|)Yd;pK^@d6wA&wO%h*QNGqMiHy2FXjrN|6o- z?9WfchsCX;{T9IQB<~gXiHAhm7t6%yV!8NTae=s4Tp}(P&9{WmZuM^rm~ROo{~_twZw)*p`8n}L z@m28+@h$PMB8KT(&TAH*sO;o<&A!Z!vSa5?`9|~few0gik%v|0-|tBHQ7+yzD&noE z{Ch@aNm=FJok6>fM>ct@!^@2)=|cc%aO zczDd8;hWZwACPD}XxEl_p>0%EIWUH zXXZSMD@D00}r6(jtBD+|cn7u9OSr-2z9D#PKxx9SOH4bRrQsksfo8Hk0y=O9z z?qt*H=7-Y(lkcQf!er=EReL2~?bATDc)Bw+x1oY>;_ouih9>?d6Y1!Z-}2uACj7Kt z?WkWZ!{rZL_d+!3`;L?D1Z*HR;LO&a3H~C=d;|vF0UQwi0LtXA5BDO9{JoP&KS6gO z`^29!HI47s#VqBom#pFV=MJXG_q%K28`JKPPmtG(62C(24yAYl#c_0Aqx7_q;Gi~) z(q2k*S2NNvNLeLpb2tn6lQXMpTw@gR78GZ$=6*)-TULZ zMtmG%y&cGRjp)>!f%LVAyomFwt!A~|@oGjiEt+aZN zR9Tz9y_z6V$0}t16FCLQ(Xg`8d{*4R%QiEtEH%T*3oKfUBPvx8L& z;#G~<8=~JcBl;Wn!_eD`=)O4^#b)EalnHL!S0ho!DwvJC0y!E(R(gUJ_phKnH*S`i zG32Kk%^2Q`L>;SX#_&<($O3CWO$!HKqdqOL)L3|)39f}Vk*H%ejfD@9gJovT=Mc@b zs%8WKfXkeOW0*f&M&yN>Q}=oN<8izrqE%m2S%Xt2c!?<$g0m=m8&6jMV=DZ@Ni^NX&0Fijn$#CU zx?EI^knyE%uQlN38tIyTp4?usR~f4kYo6@(nsu_PjuQwmTwyr0D=Ych<2E zH`+Ssm`;K>G_wnob4I#*NisWG*DqqSUcwy4?`!zbp1=shVQxE+2n~^hzYxLlFZ$4S zF$xzGR^enH+Ga*!FmW6ajy{7(D#M3%5D*Vdk%IFNVQnRRXnA4|G&T$(Y?Y9gBEs2{ zSdZvAv**T`cmNUkn*eTg@X{+u&JD$Q5AQ=nRtHS5*4aIp^sA2Ie!!}pGcy!3iulKN z79*mo#CpUKnq)H%Bc`#L6`|s0#Vul#Ssz1)|0Z0H|KkwhTgc=5d_TDY*x)C(0^Bd* znQ5DcE;39g!hdR@)Gh~-ewpJGBf-&i9WI0kT*TK9;q8{FKzDHyc&W-W6r8-+n@T^q z9`HxtV)p)opNsz{u+ADpOvI1TN;4i0D2SbBUkivOR5*!-;48T>Lko z6aM>4z+1v5biscvh3Cwf9b;mjFU*ZG!G%Ied3?1(m>c^Lxin)+Koe+)LK1mL~$S6Fw@8~;Y+r=V6ne0;+w0wz$qS_ju7%kSV|qk@0T z+JG3a`!GZv0s==mW^FZD@ePvV6JN~oE5?_MT7K3rq)cEXKPzsFS-TK%7&0pOm(YrD zkWVA~S)(=7YMtV!YPIaZu?E!w3-~-lzXyY?p+r`^>p3V3newpJGKWtq*e##CAh%8% zc*x*pxdf40mJPwY6*f~m5s=@;%D6thFl7;b^u?#2#+stltH+j?`P#VHHS5s(Jw0JZbo0tbco`$S za^nb_3xCaM$BqSX2b~=bd51!IURGY%^?o?7pI0N#n@OKhm-vmGG|A8@rsx?xy8GbX{D>RS$(jDY%5T%G3_FogaMGu#nz)E-=u4b4 zXH1wmYl>NAW=)SCJ-F8pCq9i)q7qGvn=TLw93ZxigX&$O3;Xzgu8+SWnR z*#>*O-)VzQZa_xRUKA^m%Sn5gh}Pa_q**5)k>PIKQ909Y6p&fQNPnWB-s3QI4f1TT zdOMMU>g>7+dG)@YZ)X|w3T-8j{bP6?F}NJ9upD-r(bf2JU>M@tGLp`E*gL?40{h26 z`q!;Sbo%2$_Urg|&c$}x*RNv!TYG`5FXaE9Z)ffJT-rR|pWe6g^mAwXzMcH$gnvx> zCcd3*P=~&L=ZF`GJ;g!daB-A4S>$gS*8i@!P`pK4C9VR%~NQ~vdm`TUIKE5!}sgW`7a84~^az2sLU8=o-L|3LX4D*rRd zE)GDfXMDe)mnGTwd_g`-a%&QDo@BlVO1V3UvqM)8-*-zIsx_7`zilo z664Azf*cp)lLfnzC6|j8(z``6pZ~G_)spX)ypcqFKzxXV-6u)t?~weWBl#T? z@jdYfiTWo<)c;&^Dz2+2XObvyOror**iq$O#cs;)DfUOIt40(M56nULPy&~}4yTJJ>Bd1e607@!n|BmYUZ8S1 zdQiWwI7l2Sns*maK1T9%v0S8Q2(vaqz2k;EZ<~$2ID!HXdHzn$K61#}>SYdu&agaDv zH0NKGkCsfA7V6Is&3PEI_3d7yeCyjymnrI7-){QAP`+2B6Aa}?#ivC&HZk9vuR-g} zy<7Qv#RH-_e?yO6G^`iW`K-Fnc75gNh|NWF{zg4Bkpozu{PRV79;aIl?VIyBc$wtU zqCJmaDcSmJUnkj~&lgIzzS`!z4tv&D`$sCbzS=*NOkW?i|CGoXVkmRA39`CRHeGy} zZ_eu=ZiyN>S){`c%NvMv=%L(Bq+bu^ZX(@#C=V9t+(UVSNCz9rvqk#!Q2xGXeXH-1 zOt&7E|6H`^>!&2|6zP>iJ^J&IdqsNiP(CIy&6q60o50AmMEdfuytznU9m?js4OaJ| zHs@*NUoJg*=1~6{(VVA|w!YKmJPmo3%IT#;{rg4w=1_iItnL#{?;Doe^YY&$9~0@z z!183VhFD9aM-I!Ii}bpoY<;2Wc0>6>k?u8=FBj=$L-`t!UNn>!iFBr+yh@}`4dweq z`pi&%T%_v^Wpn-o=|MyJ9g+Ssl&!BbJ!UAUiq^L|M{+CC`Zk;MEcCl6pAImrKUjqM zuk;D#eGKZ`^KSL?ZB*sW#C(zWu2`@7`L~bq`->Orc%4ld@8Vkf9XfY8yQA?T_W#Ad zrHsscljZ;Kn4jOJOP6T$oKEN9Kf~#Lj`yJ*gfI9U4?MU$qogdQ?8dTz2QwOkk7gxf z-quLyP-4J2#!#B^l0hTI1aJx=8d_%+Whm)`Dcz9u(D-Pc`r_bmLhq$`gc?tSI@_uZ~X>1cM+q7R%oi?EbCJ_yZ8#t37S!x_73m0t87YIH@7Hb)MZqOFN@_Pv)?`uKZ~ z?>|y=dT-}R^Sjrqwy=8_=(fR$j6TZM1Ln*$?^n5zD^P@qGU>gDi861X6i(^{cng?S zXl^}(Q+Q_$Q(_wL;7H0U6eXs_ycLqy5G{E<%my1y`8lh)k!OfVnBJwKaF{p5Abkgl zNzWk*-yOOWS;^sz_@Bb>4jn}zG6&`O?$8`+W0uP_5Z@i*T|s&>*Jf!Qi4iC1JQmkY z+6tt)_3+<)5T^0gm-!E|1Qj@~<*%5Cq9lD567FUi?2eeR693$XD7u63lL~m4ZI45& zVf=u%u#5wfc{%>Mk5cqtK9gN@w^D3JkzI2iqsUkLY8VIJZCo}F1;#JXW`Em{Cw&{Yzit`6i(bnN`q&jGuj-Kz z^#1#j2`mGSeOMoyz%uCem+-{nDKF^u2j#3Uan0kl0|&V%N5FFO}(nNP&c75#1@Dlr?PYq z$i-pWmh%L?5D|G7Z3Q#^@&P34GCyFW7j1FGnNPBPqkeQ$>i0#YYz%;^3B~w-CnDMy_;c`2N*fv*GtCp?KvuXob=;jY2D)G?LtkNp^o=sKf_w@vagf};#SL^noL z916}a3iLP0Ap|=GS5-I0QQ#6oh2R3iAdHw$8~?|ctl>mCqUT)a*YZ_)zBM5S|3fAf z_A~H*9rS}CDDyRokdw#%ZdGOt_^i0pMs!d4WdA?J?dS{MQeWza^e=uS?P1p)(85c5 zpaVijM6YJvbsfE|554JhGon9GS{~$el26W^cv3FPF3s~=n;IW`z4N?tIUnEUZ3lRB zK5Q}ByDrab8}+VoV2jS+sKsFCybN^j|&8n`X=VhF(Hn z;t*s8Ht|WfghSA`@&5TTzn@d?*&R;a2!b05CaN*(+Rh93Uom5w|GPW*owjJ;AjxCo zDg1i=jXpitv;METy|2?e4BPdE%M5hIAF)8n-p>m(yG z(B67$1ZjKb<8^8v+j#{7?=jn8%XqD$$04RD`wYj~gu=RzaGS;0W52$GXzL*9G($tY zptix5@!e3HW*Oc@a#q?-12R85R+rTo$t)kUC3r4Q7N-Cq?uMx3LO}9mr&^y-( zAaxl2h-lN4pNC#>TeYk34=4*R$Ed)#e3dT`?qHc$VQ8DdwnYXO&)EPY`N-sr310fK zU9KOtY4;5zomaAP?~w@wYtPD-!Tf)RFHd7@*wBuOpXr%BCZX{EVxG1pFwgPu14ld& zzRo;t&7jUP;W7RzeR<5a;a7fUjn_x!IP^{YcX<5b^V!Z~SFyX;N91vddY6i0#WL|) z(faW$mi$9;rMOnyApS($A^t&pTl`S`TujC|@qV-Ui3jqB4WA!JMe`gK{p=vQfP~y# zIB~1HP+rJNH@`I}Pn|Rt1u;>B7P+DHYM9l5zYFBTw8MW=iu#> z&tn$rogM|@8_B7P)#+`dphMXV{B?GpLCbINl2JiLSC&SLes&U!2VLUD*V zT(r-_uaJC|I8D4x{H}O|c(eFJak+Spc%S$S@mJzw;*;WU#NUa35dSE?Cms@yiJyv} ziyls99GB|P$?GYf{<|#C6 zLvfXOmw1nOpZE*$SK?#hlj85iKZt)8-xRCQWp+&YpNhQyZpKYCesSn;UCE8aCSn^g zPdr;ResZW+EV)E9esajaSTbkBV0)v))6H#mgY@k4cV4HP$q96P0gOGU8QS9nE@!Gg zr#$sHCOe+`Ic3Mff`URkrTjY2DUCz#DV|g2l>TXx_ubO6q}df^11s-~6uRC~H)Ghc zP|1L$;Uix7`J+*H&hPDQdcL&L?fq9~ zugX}lu=M+-m8Ex-?m3V-Y2cC1^PMKi#WjmxIFLN4=ADh!Ca+1ot9@C`J6bG%xn8|x z9d6%Hm4@$0MtapPN6!@*{k+v7$kflJ196 z+}iciVi~J@9&$bJM9Qb36B$R(?b-B%^I7+U85u7eFWH`UN8Z}T%R?vJqghLxW@oK9 zSiI*zRZf~-7i{mk^5c39*STxXyPaD=&e|sHB2^jJ?SV$i5_eTv zRYrEvsvGgO(WF?@wH?+ygKv1|#(o32VeG!Dv`H@<2u*5P;;q_qAcQ6EI%z|LUWZbW zIJ$1Ea5+kQHCUU0HT-$K^H*VXdOv_I=ll|APpW9ZHH~kK#_LpWPm48Q=O91Hb+O)^ z6B!>B^-Nunx^~a;R@*OF8az}+p5A?>T>8D`>;3#TS#R2k>W6< zT0QIc#5SGlv^=jkJC?ep(c0_BY#GB*>QtP1#|LGtmhP*EZTo2J717(1*QLZ-tx2o$ zYTb?PqCv^M`1U2XoZKdN7B9WADui@$ZgN%Xks5b4#8!~vU}QgSy(UzWjx9Uc#ddNX zM)8vzY$G+64LtbH+*bI`Y4|B@`|g=*8m{fJjN1zLj7U{@%DGtT#TIgWx zk|!1a;*STMNj26~G#GerUpYsl=L+ie_}QxmoL>GIT~Xq16*vxHgevNHKjhi*Id)!8 zr$x!qUMp)ZZ+>TVUEUgwRP;pXXxGx3v2%NVS}%Gcd<8JI0Ge+f~DkhkrL<<=^nl-OoFvu5G`n&ARkhWOdWxP*u`Lkwb1$>(b<^l;fqh zr>$$d7GHcUxf@5DHaMy!EpD>*_x0|^7TbGO({=4)-Ak5KCEb#`Hm4-Fw9krXtI}^t zfra+#BC(vcDOJfOrDly(G{{|tz4exMYa{EpR^F`Fch!&a&DTCZ%PrxW$vPBqx*tk) z{Wat7yZx3oTiyJQyfyvSIxV~tX*g~<$IilW%RSN*Ya!`G+R+PFhEAk?l5uD9n)IGM zFt?ps)cYV@7MATfknN5u9eD8lnaL{_d{p*}K|gy2Tg64|2CjYfK*$}m@mYLX72mzZ z-jbP{d^8$<_CVNu7Tf0Fbr-G3KHI%u;O&D~Hrh2THel7BvyVrAu8A5Sub=xo zEMeSx{qempS~zsg2%JT*F5L9eOG~4rtxNYDAMsTE_b!dkiT7ikt9e3p!tQqbccYM| zAQtlM90;LE3jIaBa1w9y!xQ8!D23}o!^`Q5|8U&6jtC`V6S>W*(ZQ5)n zRAt1p>z&YNE*~~J>FyR7b{|7IrX1k~6N0-I>mUPODBGB5kDMBGHFY0n>lab{CAFTQ zIF}+KJT{nlA7ZBQLwSm&{Doh03QM1+cne}pE|~l4i;!%DR820JyMv{RkjgZED9^Cd z9FI)nM)EAX`aN_7A{<4G_z#N4jpR2}eh`<55K(HxF<6pJ&TY4oRq3~$NhcN~%{3A< zjr1BN&U9y_^CFaN*;-0;M)|E7t5o#1Hq5!t-HZRDDE^Y2{~Z^6DaDB_HDa4Ih$C70 zJnP;}kw2e&@y8S&#Ui^eu&yz6BkR6MaU^a#W{p8ZjFSK9&;WmGG3`7Vu7yVI&Y8duv3 zwf$7P${l9aUbJd&#ntGxItHrlI(ME``^2i%<;Gfv<2Dg$^d!dTg-wHnD9Pr~(y55k zAfGXm!fBm~G?N&%m2hx|v7~R~RP@zziGAtxVHqb+AI90lG6S=To$O^qx1vC47N-vz zjA_B_^kMKC_NNc49VkhnZ&RIM1_q0Y7^W}rOTvIS^h+XnWWkhSi!t1ZkcA{%fC!d< z(MhS5QMi~WLBux*A6USI)jru{iFb$L5JVh-IZn_;Qn~v4Vc7kkI)rFul0yk=HsR;g z1-ZQ0Z(3$z7q$p|pz-~A{9+@8hp|M;fX5RA&Ks_bj2MN#gyR`mF$(V@VkRyk2b&;l zzdw(OWxnvh0w&fO0WL^POu-_+<^v0o3vyx<<|CRuZ9(Fo70^Eu*y|ERjsQE&*S(;< za~>1>jWB(BjETdDFuZdfzlTWytJGIzhx#DG8H6bF+t@gd3HHEqX3RBR;e62;bwa(` zIFG&BVe)xOHlYOnRlaEf6H5@$^d^2PHAZ1gBBOqc0Nb|67<;FO6PDHda)3c2{bb0uabv@+AY zSA&hIavl?XOyQvA;ft4tnI2~gnJ6=b!O%-WM7}@5k~fh-L8&uBpyb@v}*+SM)dUfJSMntL)br$3GH^r&2Bfv zY~_Oq8b)P;n<%z@f|F}v3+GnwqMszVB?jhqyA}-{&Z+ozNo93~5Jl`fe{)%SWKR%!u6C6QX$c{db zXl$~hdrhIg7MWIWvjV-{6z}bP^r+JG*56v0R&VQ*y!#HztLHJHmA}QT{2u6(DPe*= zPIi0~Ob_)7H_c<$HwFsr2%Fvp#(4ESc72!Wx^ISQb-jL|>#O5kABOI&LBu(S*oqi7 zM<}Lf4Q+g8%>D%ev=5l0ykLfZdzmaRH8ygxcw2 z+d;iR6MX_r^g%@v_ToQ(d0_+yUL9cdVfSWguYWMwJfDdS9D|@muq~|C;`zzB(U|QEJ~8cQK*0nK?@fsCUM9GN7@q#5cIJ%>nD`J8 z);2Ck?wAv!;E%&Ff_n%m4JG>{VgnkHRHiE2am!z6+c!O@i91r&M*o!ki1`w`*$J)7i6`elVVOn-)mJ(=KDm0whl z!-4b92DhM@(SWP5w5UIE?ZA*srk7Vw!>NEpgkt#;9hSSzqV_57=K} zo5ixdJ#O1(VxP7Bwpl0jfmb76VVlLWomf_0q*Uv-&4TSjAME<%AoHaSuE5}cvpjx^ zu?i=Re!xN>Uh2p~{J4^XWy6Repi2t;sbWJu5}gpaU%!aB3-M*d*AQPv{1f6|5ceYP zL)?#e1o0C@Y*V;_hOHBkPusH)vk~hfwnEHDEJW;zSd7>Y(FV5h3ZiY}o7ip)J53SU z#s!G9%}tZPxOo*#|8#DG^vtk zMZ6qw3?eu88HhHlNBTj;&4}9&w~F4`J_$XQx=L&*jn3%4Uajkp7mKW<+}dwQ()-`Gu?sMDFIdA=<#BHSZObAfi?|b!Uw?W9@ioMc5I;lY+stW!{n)lq-8L@= zPG$RLKZnHEdn4lu?>hWv z&kWnS(`m0j1z0wmiy`FAfSloQaZiRE-ldkKf_3JR)yB71iF2t0rn?gmH z-t~of(aBy~QIjT38u_v5SuOB7MV>b`+N@1(hbBxzxiS>lxfJRj&Wl3&K`7cJF5DK1 znsh(E;KKGJ&+5>=N&EB9I{z%>AD_qk#i6_=?OEm1c|{!|-x%VAvsK2JpZ@2(iO63V z>WBRA&1WN@yQYzf`E37lH?PBlCN#KceqL_dj$Z24M&6ug4;nk-vICVy4{3IDnXz!# z6#USneWm3_3HfJTcplVN&S&QiK{NteJ>=%~g>aWC`Ky~Z62hJHN1)_gmwjGqti9vr zweMgg8hG23{Ahk9(tAyMz0rEp&EqoPV;bFU3O1O6-EL6_HhJItqHd`3nj7J&c-R>D zo!^^>=NF;mIXCb8_OsegI*W}xVeH`LmJaPZw1@oUe9Yq8h$FDgEt)xtS(}XcU2e3) zd93jp)A23t2&7+}KcaUxZ$i1(1QYW{y>WTDUbCn-GU_#sw(v$ry)&cUgd*=u%;y{R zMirq9c7I|9aH|=M-P1<4uNyrdhLHtfgBvv?;!F3S2VB6n%p%21)whgZ z% z{DWrTR=GvAbYy|4rk3mlPeZ*INo=n z?I#7KqO;CFZx;573z2un0ueFY~cjPlk#@oUl3Z4i%nq;xNQlnkG*y$0W$JkinUl zPku|ryh`OCu_jNQ$)lE2eP-wQOIC?@c>-@#ooW{6DML(~U;p*0>C+@>N)ofOvgB5J%*#4?Fv%b-rQ^7MCo~MqU z;_!c&qu2BPoo{q~=~l@t(hR|W`MX=qc-B|o)zm58-RhCK7?-R6;+)KZ9iBt`AN~dx zp2=g(aFvDoB7P_kEzH#vgeHj8!w8yCU5{l9EfFJ#r_*Z(o$Bp=WIKT}d*M%?5o;Ss zhjZ}!#1;n11|p3||M5_mhhM1ZL|x?IBHY+xzeXbl?Y)FY@2vwFHhE1oy%TtFJ;FFx zpde6oHPXR$_jh!hXr|vT+hbSB3PfugNoR0F=rN&S%jQB3+KUw9*A?=(9BGKw-g2aE z9VDF@u*Y9mHrO)03lg+fzZiEQFov|pC-v6ekCC=@kaV^-_P@=`G=nYs5z;|>$9wzB zM|)W8xIH>huueWA!#U0HYs+p-kXgpKO|*KQu>o=HZLoUJAOov&y3OAJy;Hrz^#&AJ z$A-PoE3^V=hv-$LgUi8hfZB1!!}R!a)I!>B%Sbx)Tj3WT6AHF1GO&2gc5L9hYje7H zxQ?{PykFKBXzc~EOfs1N?|6p`t0NHXsQ6j`6Yp?gwfsx(aJ4~wjtP(TU-b@G@Em-q zH@T`E&&_f0+q}!w6@B45N8QB!B9C9ecer@`p*%(8woaKhj>#LuN^zCQ=T$7fPkc~( zTzpP^N#xx?>c1&+o27h6{8X%sL1catk=rcgZlZZd2l80SbRA=PC5Z#;3UM`w9g24c z$zPDrqjwc$^Ue)q-YKMP=AMN7N6Gfxu0yJ4-|^xdL)r;r=VHB75^^2MO~sC4u{coV z-9Of&OCvc)Tr7Us+|7@$9PKC_h%sYd$LytnrZ%XD}Ldu6Fn|EFy|3flnXfWj& zBA;VXhwN097@=}dG`eQybH+XEg(@&w^Ek# zT*Z9zjtO{~%15hwn#yO33sug$f~>zx`Pht&U5JJ}r?DL#%gOqpxqA<}z2uG}&kfWo z5-$=5izCJFh!e#t#kpdIc(eF@k>_dJH~TSY_FwR)$~XHl5$lP~MBeeIUI($WSR@vUeZ>JHp9-+vrQ#&fzOz>@nNJL;XO0)( z4dlh z{h~Q8LC?OEw^RAgi*JZ~L_V=#yL{R}n&S}2Cl{2vi*}Cqg_8Nuk>%Crh`n3+_lggS zeBej@r^RPQKAB+tYvSADyW-zO`;Ob^lFe}i^)k4hgM7k3=7>?Twb)*?@3fsSxvyy7 zX&Wi|JK|*VYLV{EZ0AOCiC8J#A+8ng74H{+B|aiPAwDhsR(wHxMSNX+Q+!7}DDqJ@ z`}GgeMVfL%>6@}EUJckO=3?~5Oce;1Q*y~uiIPI<7l zh#SSt;ui5K@fnft8PNWp#J9x1ibutd#ea(Y zO~87oVhyo@*hp+4wh{Rz1M77YOT~WTF!54xtT;iuTD(S_Cw@=7Mf`!tcO}@~kHn4Q z1LCj5N5m(@r^VljFNm*-Z-{%ved7D#5s^Qt*?w3|7i)?Q#71HZv5nYKJX^d#>>>6Q z2Z(%UgYAtGCy7^yv&Fe0-w&bw?cy47y|__)KzvAiRD4!^PJBsxRoo-KCGHpB7e5yN zF7l?1880zitSQzL&lLGW3-$BFv&D18?qVAB5o2li;sy4)~dBaRo##B0P^B3}fe{;lFt@ph5#2eJGoBHsw2{DjCCgDCSpB>A@ZuK0m? zROA~%)JqciP7vjWB3})n++O6%K$LrkeZ>JH-w|T@Sdni9QNC8>%R!WH5&1e0<#pnZ z#h-|LONixEt zwDy&A58$w6>Z5r>`@1n)a`oSjQRO!iTZ!$&e3AFZ*{|xqFN>95BK8sci-W|W;s|k+ zI7S>VmWflu*<$tIrHhomSX?4jiYvs`;u>+ixIx?~J|J!qH;Y@uZQ^!uhqzOGUfd2}zL+CM#p=J4+bQ4NA49zY$%SI| z-_0e;A0!SHM~I`uG2(c!Oq?Q47pwoSo~!%{agn%KTq0JAE5y~}8gae2LEI#67PpAo z#O>k^ai{paxJ!IRd|liv?iKfm`^ERgBjQKmaq%;eH`&el6|=-_vA&oiM#W}gE3uuJ zFVb_+?5|>xXznLseV0h?BUb<2Pj5rkA0dts%fu<-bg^8VEzT7y#On72mMFhcTp_L& z*NE%I4dO=e0dbSKS==IS6Ss>y#GT^v;x6$O@pW;xxLqCH11>N%v2Y-%k1YqWz{$q2wab++T%$iR3`hA^j<ArbV(BtIpD?EIapy_%T*FigyT1e7&iL0BJ4N+?nHFwDwiiJ`DCa!>cO$nE zp(JyYGL-UjNS=9+bk1cg2q#Tv4fE)w@M@Ej!t=Sek%Kc}0dpcrDcl1iDZG)I_$UVt z>mHBEUYmT@;B8Z{`yeJK(PocvOd>kofO7oDybJW_PQn!MksM<%{2*k^ys(g^k?{4% zOkRw1*q?bJnFsi=Kl4ILm}m7!R``+3LC8)06?DV#nHN&ept#i(VdjNYzP2BJEHg~= zxslYTXfrYMLQ0rd0?D55fHt#B@xlFpP;Pax&PeJDk%! zTtLyx4ge2A$GMIoJK>IG_clSS@f7~Kmr^;j)XBs%ck|J-n(oDJeoc2!XcjV3%=@QV z?suvBBLBIyh+043zu({=vcByXGHN>f!IK<(r#*#ved}N#>$vIZc-`E*Bc58rf4e-X zZ=FJHo@rnD&U*UE@2ulKV(_i>;4ADflX=TREDc^%#}BSs7rIU;ZD|i=XZhA!X7sI7 zkWrL@#Y}S8BNH%y4qgmG^j8DYS$>KCpPmDFuZQ4T!W&F}zW<;5F}^rKPy=uI7&b8J za))FszO;VwYv^nPZ|V@L7$H?L60A5lhJtwD&a9Wx{r+5Hi*k_QQm{E2s1gi8c@(yq zkaI5oe?3p`{|v|NFZi2R^NGB|PBCx&A}5z8+_}Htz>NW&Sw0@VcX?$zums$_%^=I2 z`%jJ=9c=tNqxj!q0A3(*UF)Lx4V*K-h5z2~~jblS8jGoury&4_j%JRsWZ>TwgskDo9;I%vkUD<;gGIc>(w z*3p8z!n}fLr~Hlu`R8;xJKAc-geeoo&YaLXdKs#8n4l`{3q}{VA2(y{)GNxOGbUU+ zdFJG4Q=^?acJ5ek&Uc*dg*Z-)oiKLXWXH`zGO6dZ8RZjZw;xb|n=L5=QbTFUwZqx& z8E!qVzT3cU=$`52xQ#DUH8na8^Vk5mcwm0)O{2GN-RYlx=@~X z`hojTceFec#>ZXB_b~gPp6j;o$BpIk!OQF zleI$zZb`?(8eBWmemz9$Fj5|cX#0SqIa%`x&<2|vfsCNN4Y0Qug|x?ea@JlM(zXtg z&R`70ekK%b*&N6=&7!VYa9&l}V9TyWMzGy>wQz}sJhsbx+wLt$+d4>^w~M1pDA=+a zAqVYc;0lx16tsscvA8{6U)wrJI{ckNJsWJ2bT!L1r1_GosbI1jhK&!Un6yvBxTyZu6go z-nmu)smJg(qD`9&be7wi4O|}#e?bf`M?qj*c=2b~8&+q0n@7@Vhf05ALcz901{Ti= zXFBHXRvx=x+SudzVViazLeeS0pmE!^!P>L3WibEW;g8wc8aA|};%9pCqlT5ah7-X% zY2>&(+%glv^Jj*OXL$S&K_GZeEwfHI9)946CxYixmpOuoz&ZCjK;)S4d_aH9ixb8E zesJ<3{>!fsPvfK+Ka=VTjMwyO_^Dy;^J7@>@RXTsCT(|g~$z``TWI4E);JOSBX3>u>3ypL9x2u<{y;*C-E(DzxaXpcQG4- zO}n{bC(+#hK>l#a<3;PAHH|X%{h1^-{u{+xrME(|@y~*tdnB7%2awILd(?YG`p=NC z_qJqo&%fUzn)QKlZd=rgip|8fBDWuwoAm(pkla@sAo9l;^+t+g#R=kdB7c2T&#V{l zCds#n%fvgyb>b#*v-p_!q8excwA8-TkM+Z*c#qkH0&{??2VY zR^R@>k(zgIx~24vNUi0yE9)%FUOIo*3kT}{^!d^kjt{L&D$U0Ht(bp0+N$iTvfanS zV}4OqQ5A9*R(ZLhrIM!l+f;X9KtcWg#Q3g#z{ zRD_N-b|c3cJE_aJlomUEo#bPULy*0}&SlP`{WTrTavg0o`6|qIoiQe|%G&?M!ir?qetD;=-9Di?;iWk*o>oD z8A(T@Nny;Ay6UBD%$?n*qRt(Au!J++)g=u|YGH=nJ{75lk{i@nTIYzD+-#Sx5jh%3 za*syBn@cY_9+@)ocsTu%vNFxz)UmFuE4$3^P{4;DKE4|aD;jz=;|pp%4} zVbpy4rH1i2R7c|k;-726F1Ht#PK0zoo(&-wa4+vi$i}@gUe4eKUL8uIlpjIz&S%y+ zgZMw3#M}LN9~J4saV96_htyfk9RJ1}9lsz%Qg$IPaRZMx{k%{4uX``n;N1USkKs(> z42ZjSlUXaA@;NQJ5##n43ExdA9KMQWkuZG_lO`aIdv=vT5`ieXOIa=TSt=Vb8)KjPySUhrVwB2*sN9?4n7FutVtv_8n>-BaJrbn4J)&$nYlCv6Ne*T!{zNS&T>9V0p! zJCOMt;xlo*O6t+E&$nenC*yf!?n2}gvwoXPsW&;UXGACCWn{jFcm_w$jKebO&5i3B z(a9*rN-04+Kd$!(^?n%FGon+2I(-m*TU)4ecU;Ga$obYcOoMkylkJ_-lvCaf#Ws2J z&Ck@6XXs2z$LyS(e=|Lij|+};^sTnb{2G1|-DSXbfuq7aLvz-^9GoO~7tX;6BtkPJ zaTAnigJ?cp%LF$R2odv%+D^WZ5o2PJFJ#4-xYZZ3V@zAb6(Xl}BHJON!rT}Wyn_iHVw|5p`xN&|>0_h`JV$Z~+96`nEMf_whk5T} zOdRxutQZr1^P`A-)5=Jqz_fDx+}Kbg%KUsN#{BprfAuY0ynu<vvh zB085%vOSE!#syq=eGqZGp3nktt(d@#)?ev78<}9YW0=a|_PG}k=^Rstf9zRTM67Yb z@7Y|_D_*xDo7juUxfR)dv1xx0;kSQ%ynXIUgAg%a86jg~?j#TT*~DH%7|Q@mn1cT^ z5U~z-0MGkLd(1*E7qvfP5`GJJY!+jZy9!F6Y64A^BVt^h177x%tjEVnN%(n;nCjG?;iDQ5Bf<$9^zUCeUOBVv;kH zCYfAA3R$#Pk zR$%mO78jWd7cg(T9I(aJ#T64+DR%e+Uo+2v9i00R!sb8!*=rl7harwY9FJIrXan;u zMdUi>;@U6<39HLxwqYs~(-El~A3CJBB0hn*9g#~P48eXpWJbL`|DWQqQqO5uPoFYj z_JFbFWu>#GUQv!)z%&1&KiYf+mS^^8PSY@Y#)Pp`{^dtWzj53mFDvRzk9t`}_qJ`4 zo8PQM`}6Y~H^DqJ&6?o5%9Pu-$Zc|Fht5q}6hOh7l;@ol?a;cJuhlreS(|1Zy61Gx z>DW+3T^4?=hB;FV4EI!DdqB8kTve28G5 zUQHh|f^NNffJ-F8pr`i)LJefSzu4}%^e2VP>lVg3GXIh;5#B}Dg z&$9TWYAg>WGyjtwRej-ERkOfRln2pM%nQ;zb1@3O$#bjtGpkdqnE(7KLH>U=C&(16 z8XLk&Tm%NP&9|TVEk7G}^6G?PVZZd+U+5b&zywqLBBOY_Q2S z$Ozhd9`?9=w3mr!?LB}r>*OOc?8NSs{fp@-Eu9Wdc2^iK5* ziuZbG*9JZlEVKg1{xR%A3@*njO%mgbpZD?QKy|ho595*XR$NN7#Wn+r=kWd*f8=5_ z{K{ugg-|%vas-+%N!qvJ-|-CUOl!>0j*6f8KQSjrV>E?TsK60Vgs<~m=O$3+nD96s zpA+O1hiIHT6Hl2=QO;J)9UE-K+#mRyh3lL=-Sec*((5XA7fZzcQ`J^E-#J(c$GO&D@I9j|yoFYya zuNUWuH;Ft)(#~>mmAGEqApTV3^#b)D5zYPxd57ek;_t;ji2KC-;@`w$;tBDeViLDc z*fsknXl}uPb(MdXm@Bps^Te~obHyH_eQwD|GqgWa93zewXNlK~OGLAOqTW4{?-RF* zX8s?Pzae>#xKG?K9u+?p`7nt6NfT>{^vh;GAGMKYe*{}eZYLIqg{%-Ld@ja1`Gue+Sk&iAZXNr7GN!iXTV&@Sl zP(B|&vb?ugef|(WPGtGjA|D%4t`PZnkn(czZt-5xT$iOJ&KEc=8hv!vkiR=v-=0^h zpHHGHZzkr81!DE{OCRO;7YB($#WCV|u}rk*nc0%(id}VF%cfj2alXU*Nrh*h%0DFk zOTKlUUyxsD^v9$v=+(c}bzxY+by}VDduIuMh~XzMmk~!uoMV0ekcFE@A6%a1E?-=_ zv~>I~_(LRRmwKhcN*B>9qTR@{v&t$TtesJ>%BiYX75%hURp>~qs-_>}tFq^PUMKxn z&GeLGHB)My_}R8+dSUzO{JYn1Ki1?u1V@z$U#fYCq^5&GKkFd^9Tz zpNw|*y)^J(TAeYakwec#>X+P6;@(;Ni03uhm3lOs8qO~~9%`Ep&kgkd=x^(|$7;H* zA>|(r<+$h7u5z(Fuzob`&^~LlKAzle-%BBRcZ|Y@g+nVs*u4k;-G-2OF&9mYw<(5i z$3`B5-N|x|HikY9a0fqXZgMzywZuh&nm{ZgBKo=N70Jg`(Bh>3o&&v zzTIkEJAMQyZ8ED~#KP?qe~N$Zz`YRbpjKK-mKw1yMee`uAeN4z$hLiN4PF?h@v6`l z`Ce;Um$>*M#q;7K&z5P+*wEm;$mGRs8sC8R#h+7T*L-mVR(TrdBlE=_5OHCSJA^b+ zleMm8=L>O^NxK~hU%U{alg{pP>+toiquzaSJtJ;4dOYm#wLV{OF7@`JAj8-*qIn?d znxvE72j#qy@YQEiJw4erZ^XtBo%AvI$14S2Zyxn}pujh4#5DeZbWQSVR;e)x|HdI^ za1hMWUC(Maq0nDCBi=#XbRNtK;(E)e_hekph%XzxN)(KW>#d+(9*)_*JtK0OASZnz z{(V2Lx0-sK56JJX5&cmxNhf_f%6}DCzn$uH;%1Hb17r4e6#O}^w~~6ljO!V3htWHN zf=sS#v)Fe~?;r~N=8fo&mP!7DRcai@zt0f)Q4_z~{j63uVwcW{tsy$*^UuD{1Js!m z*D>N8>R?rT+cyFKRmYY{;={CQ34fMQGFFTAbIC~L$DLc~=aNYU(|a5`z*Bj-@W6rm zR#G$I{T)1lC0ZbQ&dhL(3EumF5Q#Ct10aNq7!%ulAuGnj%ZPZWyBj!Yl7k4Y5zm=E z*Z8!coWlGV6Z~m}=7^}DKR534fJ%DX@Zv;wX3aL;@p}Ld7$&wN!UKk2!|;rm9b9WB+l9*=!fVGI9mncKF z3AT^6Hmo+M^sV$qCW?M7e z#6Pa^u85g%jbRUGXf&C}G0Rf^tU0#kwa8t3iW6Myf^91cE-7paEvl!s zH7teNNtD_4zF5n)h+1kZQOmYjf`qnGo5gN$0}2c#S53DT@l7bPp=jemnO!~EU)+dL zYHjyHLYuwKVh=cy**Ki}BNAV)fr{Mb%Mr1^5IYg!?PIvxPjh!PA+YnZwq*`FZCfFS?MJp=4c(x#LU}JBzc-2>3pz#&ZT7y{a^T8F!3hX0V z4b1hoX@B_b*2`67w`r_~>U&?HxlEMdVQs1a5`ZbC>PARuZ$2#DMSR8*8Z0wP2Rh=_oScq!Fz5pUF>rD(0Swxz9Y zt))t>TD73o($@N+)z1rp&{~aR+yC>t=b7D;2!hpL|DUb%+d0qszBBXAoH^H>cji4f z4A@%O&kc&|gIhpw(YVu(4OA(6);t6z)K%1^Ce%M)Lj|`WSI~r!^>uyhczlE$F?&Ru z?(+Tx#CwSDGSmf)3MfT$aFSH22eN5QV&Fq2Z3;7$Q$HVOq3ch_DJTN}As`~g#GJ?; zkB;HheG+0hVt+&z!ZM!0E|BI$Gy-w76V{XQv~z){-&jPRozt8UcrD@z#A-wyeiy|$&$D=CWRrCYV=(uH4}>(a7Ix1Mb}c0H!3d}!xZ zZCbU6jxLUNP9v=WzkJrUSLt!3ElQ6b8ZEDmKIvV#pmbIA68n7DB|nL_+26dfdh^K+ zVcu9UW$fb8?)V(i=RI-E=8tv#&z?W_@vl)~wqj{8W3RMF@QtZ%{LmDq=+&Q2#&wY& zvq6`3KhWf|I@8Kbxtr0I`D|5adfBI%RA#66XLFfw=+n#48(qyC!hhHtGu|`zJIAa& zZla&h95b98UvzH>|F^z76@JdSw}s$^Ir}u^5}5HW5n`|w24f5Jb|yS{6y}&A-{FvO zq>n`sh)V4r;3>$cFCWqAy8*N-1JWylKF(=!!I9TP5Z33l3%(gceMv;8 zZ#`&N2BbF`m97g39Jvl@VSUx@gZ-qw0z{{e?>{V4f@q-$Ml&Lg3DTJUBgAmNEro|R z$EHK@^7Dn0gq1>G>r7uPTp?U3#CKNUVA zd_u@`n)!b#$^MSOSVv$EQP7?Z;%OIT z`!*@x&m{kq#j< zh~T@6KYX9}_+)d`|c~ z;SS-e!kxl*gtfwtgm!;|{#;(Cz?861NE0{Z?SyV_U03mag*FEk`OXx7j&Oo-ig3Pg zq3{af)xxg|R|;vWX8qp~+WiUqcg1fOZV}r33F*HP|ANr&Q;`2z{OdxyPeD#M60C>w z42X8W0@6-TzL~Ivu$8c*kOp(+>n`jiq+y@(p+Z{r$=m%3c!Br}g>!|M2p0>l6s{7k z71ARD_1!6aKuC)}f-6HfI+3-CVmplD{vsIkQN&xw60lUgyA8!nVRb z!g3+kpfDdzIk$qm`!*D(RFJO_4i%m*JX?64 zkP|JK|6(EMR*=75$jKGtzb53I3i6K%IjMsD3&OXBdxQy0O<;Ob$hj8ey9)aX2MFtb zbBU8En18X5vna@~6ms$e`5y>5dxHGqLQa|>zgx(u66Afn+Y&iDf_S8m(<8`t7M>y; zDCA5Dre7%JR0;Bnh1hK`f;!yu46LQ&^fE*?L-*XP|GY~py^YX4_sYcEdo}9oBYu!@ zh;W2(v~av|vT&Mkrf`99k#MPSnXp>8MtF;Go$wyveZmKXn}nN%TZE4bpAv2tz9`%w zd{wwd_^z;4_>nN7`+rhc|9O~}yp6E8u#n|3KG0lxFwkAvHJuF^A6N&N@@KrTD>7s4uIR#>cKL&U zyDKvIrd`pFzugr-=cZjT#N6J$-IddE`!26{yWPtMPu<;SaNFHipEG6mHRrV59hot8 z_gynu@6KH~Y4_a={ganL!xm^*wktYg8A@;2l`~@tG%eeeyKoC?qkpRS-c&pWA5{-y zrs9x7e`m6Bx__(w@JJOsZ0p{){e{)Y*KT*ah5iXwf~wx-FT4Ppw>RNE0y?rc5!t!z zXK(EBD+k&;zwK(w=lS5@j?Ny22U7ijDSxLyhG~iG`MB~EbI3(<`jd;~-byZ(^A&K> zY96ni_7)e*y@m;i9D9~0a(5#sI|1=oa8W*Wqy0u%`P?G{-6ezsTtpeH0hhyve(VOn z1M~%)<@29?ka;lK)?_EM>{^y^&`S_@6;DdL9Ic$zib?61-P}Nz{;d1`(OC&4fVP z=~-=Ou18v+?Q}w*?cznIjqM3dUIK@~A&N#4ZZUH7dcZ~_M`D`^8$e-N8-Z%*$$nJE zV$Yg3BSyUH;ebqtfuc_q_yHmrR5q3{6%jK92&)jI-X(s`dJxpl5}3qAauXtIB?NmC zn#4slGZ5j5$8f#T)dK+*Lg}pBLUU|Yh6l((NS0*UdPM94B~o3$SMF9SY|RJ zcbFLHF7ZSsZqjQR*ebQxJx|Ef5iB2hwjwz0wT--f+-;(0!YhG1(Np#`h zwq2r^-VsfvBT>)y>)GhdaSJx|E7H%5#QS&f0xvJ!>FT8iH^+0+QwIC}S&`8n-sj)} z=0Do?%g0UkpT=Y!oN*tw=|dtHF`y1;%17GqoDk5{%Nq4FM*Oka9PgPvE|WgBG=-!`8nC5{-{T>DNu)V_>qBKgdTpTZUZ*6KwhnYy z-*)KZesX^c5S_mJK(lxWBEvJtM4OTeOk@0!(B-=tHjj&4CZ#doW<+#rCBVXa$k)p; zK;~iKIpk>aCD=))n>^dcuoW@9A3H+*av0Lwel!M+dNW}>^u3(nvURb}(C&FL6y#h9 zsI@nC>PsQA&aggy`(S_jfoyd`c%Q!X|I)-e2ED^R;qgA8Z9aHrAJ{g}TQ~ymL7&Ao z-<#zzCe>FsNXS1Bl#dop5Ka@$7Mec_nDV2DXy38oJBlw8-%I={;s=QzDgG?+6U0vy z?`-wv2L}4hMh{%0d}gBu|8?>AsNDC&n~fgnzYuRWdhlDtb44xN&G8@ZhuP@CbD)d7 z*}lO4U3>%=F!LvgNN+6uDDi3W9M)mF+31nKx8&$PI}W_oc|3T3CGxr_riE>U#|gU# zdkF1(LjJzu2MGBrq@Iz&bA{uCvxIYmmkOP~lV#$s720_QeXGUu-cJ4Nh2If=U-%Q@ z!@^$*pAc>rz9{^&@O7b`XVCw5@f^BieT{`h!nDxYT#pm)Y_2`TpDeWV4tj=(xAPAC z+2U=k2zZVSvc5S&XM?rg0b93*e& z8}L2x9}4q%-auX;JX~mVLLj&E3|K6A522lJkPjBmAz|t{Q+SSWhH#efV762aIa1HP z!k-8q7Cs|%wo{HeGXMVy?LMma5Xu>d?t190{pKrDJzGJyURhH?_Inuzuod*|RfZIX zgWC!g@L`Tuz%qlZKZN@q=&reeT-pD_&~0Fm+)nx^r^$k)1Ol z*S(QM*+hDKZL%ES#K3nklBvke@tbni9#*jo-_~%tAWtV&UbQdM`sp{l*1MZETI=88 z-Z8{ld2`VnEpB=O z8r$B=UYZ*9dp%KGRFd4APA2xI6M1{nd2LrNd3V5fj=Qb>x(@iN$35#u`9=L(^uMit zyW88Z>9F=`NMJq5KYlCIJKp+q?Jeu^RgS#)-b4a^ERxON%=7S7k0EEnkA*v0yPLV= z)oS&zYhP-{W7c|Yt95PhMU!Rg7pAVSV6VFWm=VCM5$@Dp}Rj^x;t9LZgdj8S_UxNm+;K(^=# zUJpGdA`y-ps+h-Stqmoa{b=ul$dxtA(1Svh4>o=CV+{U-a(4_@zqUx=T9O594; z{6g>nkf7}-_~r-it9cXT7UIWbCW_%~w>+%1F^3Tw$V?W~5--X57g6Kj+p+x}*_+v> z)1C)wOY+xc*w=7}37k4uYBlaTfl~)#PenWPPo=6MEW3d$AEg1?9XBk{|M!d}Y*ujV z+|P$4cueqNiS6iuY)FHIX@k%S5$n`rH6-Q-OrnOw=70&7+4D(@Y|U#(@N@)|t|9R~ zM67KmJcEc;=YxoRwAl)E5_})R%5_3}YtN+z{9*+E8bZeqKqjO?!D>Qa!|;8F5%HCS z;zbLvTAqT9i1@z4h&Tk44nSftV0fy(sZ4=vMadSF1XVAxy?!GQ6N0K2)Y`;ENRxE++A~ z$xkP+DUd(Dm_#S5<#d87FCs1o#Duko$bRh-61SOrG=bNL$=OeF92cA(1T}UMk=I7( zOV_*<(ulAj5`qd>mJ^p!3BJt|FD{ppy27h+o|Hlk8!vl_xn2F;kulyB&gBD^G^! zMkYtLkL?(sJ`1klIk0o0VQlvEh$yxr(~hozo~5?OR6HjTtk3jG^Po>2+;5-c+v&xl zR%H5lqzZIe1;?w%ZpSOwY-NpSM<(qmS!tcwDs$ZyS!=Pe=RPrbxCB(Nb#G(jT0>LBD`toN zmwg>1SVfD)%%8~$Y@Y{dl#X5u>u;ZHJ9jQCIj-b{lJ?R0>5`+dJiB%0vhE$bbd63g zZq+i{EZq{Rom!pNxp%9UEnBre2Dy%H)v8NrNohCaKzc_m`EHtSS=zb9e)4te6wNE9 zHkgu|rn?+NU4vS;Jm%oKr{DPNm9laaGOIRpz z*ODuvZ+M9&FS4P%N=|IqvJ2LhM`xx{rW-8S?OSz;&Mb}|f&D3N6|Jg@UgZ~KT5w>2 z?rY}ZexXl`9HQ|v+|w{Z>q8{L((zz1dFF!{pZbF%mHcGJf3(fnR^<06!@BT~Tc2&= zxUG%GMr+11eMwty)-GH}9DH-cEd{SP8z6JIU~R6lia*KB{O?);{>A*jND{Z$e1(SmieLq z`>}jXV`zt%Ks;DJ{xPXvZ}`y}LpsB7M5mklWHg9tWL$9MX%Jw@KNB`I59|zwL&Bj> z>SMb&Chy9C^adhf4G9I8Wc`R{l$hN0-?({9c;MXsv|wG92K!%*5~TwKQdPa zr1vyV-ZTjXm&TW(u)a;L_HSRNZNQbGie1o0JBAA`?JE$3^=%3143hR3w`naFm-vUIZ@7tiMuLO~yO{2h%e!vB3On(qDobS7^%U5^JC*}q+u>t31P1UD8c!97=cqtM6aFzIL#jg_2abu?6DSo5)2gLtC z{LjU25&w+%=frbNob6x;+qHO~BhT}Vh)d4U{?38#EWT98`vvp$5e^WZDjX?1Q)tEn zN%L5w_5r59AbXnV~KYP?-AZ7}NP;SS;J!kxm8guH;L z=P+S2q0JwF-2S)%`$|4Q$nhDL8!MbGoGZLRXvY`%Y@Pt{Ym$FM_)Q^A4%GKEp&eiF zkBhhY0^pw)|3{(OeIWl|@y?$67xC{2>#v#3$327f6$qOOZ2=ABw#FaWS@JSrPhq*R zzwk8SaN$|PbA=OyQ-!mHbA*=)FBe`dyiQmxTqE2dyhr#Q;rE3<6}mOGkBNU$=0P@SlUm?6!Xg&szZaxNpw@SWVXubv@|F-z=3Lg|cB-|o& zYkz6{VteW5npl4g@NUWfBCNkA*nAM6ocsR85qKO^&(XqTg&l;nt}*>2;Q-;O!qGyv zmUx2rDZ)8I_q~fH;;$0c|IWqNB)?O5ztDZ}qW*U-o>BUgw?_|!i~avg%1fg3!fKm7oxeJxTg68Jy!~u5C3c2`vlh1_Bfu?UKHG# z+Ol5z|87W+9=&=5Sr0x>riy>AaEX)|War6T`M|n_zsB2h#nN^a@rs66Tl>RWZ|M(e zBkO-y8>#+5t+%=PzWjYh?92af_**ju7wyaYVE9`Xp4NO{@}mYjr=RxZ&Y43t)J7iI zfP6o!jiFo|<>Dw8JA`s^l#8KU0_E~iE+6F*hfppbM6}&lnQ#t(R$Ti#iuXXa%{g2Ta-eb4MN@At4uK3Ex*wWg_B79q9 zW+`T$G~Ji`(c$}Y-yiRIO7BRe2R zJKiTGVpkAiG0rOiHv}1T_y@&(dxS5sm~V1Bz|Aq?`?lW~8$4=l3pSAt&hPg&ww(|Y ze5dwLA^Q$lno5E%lW_1L!O-f3)&KYc2TNd)Ct$b;C&~Os4T)g^6RRP?e;G)L*N|8qFo_xx z*9S~~4T*;XCRsz`k$@?vA;H&tC`i?iNby*DXA+tlIf6h7zkRTQL^@y=+XRd;V9-Ru z#6Vv6s|Ud@oK9$kn1?}|O0Q@>riPGhi`XC|Y8|m}Ih<2h7^|V+{JO$;4F#*}3KKOH ztgS1|uc6?{y24})1<%wK7MQ7*oe*kL&@1`awNTT^CK-dKR|PvnNkLfJin~b(doxs= z?2(9=IY0!N zOwNRL(Zh9f=G%!9bWtW}(z>X&Zq9-l?hy9^mR}@g0u92j-x7Fs*Igye^LQ{~1U6eD zOJbrD;mSZ9BVHef2|o$M3F0GxnDA~OP7>J=C`kiGAV%P!oX9g19|S=L3$3tK)e)Xs ztOw1A^XyS2`A>qD=7RQFb&Dakz@rf8m}eay=$IE{*9JP~CD?g^j(N#W866idG6mR# zbVPWpq$3{Ekss1g5Ymxp2X%2=RSV1A5G&@X@YLCZh=t_@9yD86&OYKH(ZX_)LlAMG z2%{14DVOXVlp>UiAoBRRz@r%sVc!14|2NyRKcm<2Ut&db!#>MPJ9X)C+|Yp~$CVye z_K9@qz#+#)M;1p*(|{|ZeWuQ^?4<)wIxafDINA{6`Bz4Z(`G?7Gp2c<<|1QfOa62g zWZS>2hw`us@-OYklP6S7=sb7Iq^jw&XU$D_o;tO%^Q76cs^(0XRCVI)sZ;l3J+5OC zK7gedCSW^g`?nFpF{v{me`zDeZE3=k2@|J#elf_LQ)bVpnzEqt&@wOHFn4HPBtPCH zR_Hf9_}b$(q5B(eZ~L_ow@0SW$wvI2;2``cbO)adarIr9&_VDR@w{UoU_SfP1FWBq zX$OhHZ%9er_J>7o0ko{b&r@oy#D-YUq1~go3M=7}`CL zYl}-DJlGoK$*AlErwr)yg+xY%vzcc=aK2w|G%x15_X~d@{IT#6 z;bX$z2%i)FLHLsJ9pPVv9}52=tiN`*6|Mocr>*dKp&QHQe?+G9Z#8j(aEfrgaG~%k zLi5*-{OiSU5Sq;%a%bChw%n(b{*sW3R#@M=!dhW2Zj_Wa5H=BV=0D{eUL+nT>?-Ub z93VVZ=+@kxFP_gCmUsS)mx;etc&qSh!uy5a6Fw^Zm2kW8MIpyKssA0}d%_Qe90Fx} zO4wXjBy_gZcH+(NI`VfD?`)^$e;x7)$p;Hh7oH(>w$lmXrwL~YoxkG+;yEhI_VJUz z#MQ!^h320f@~?~kmhd~m9|?ad;S0^uUz)xzt9YlOE5YlL4H+VceV zCU-x>Woz{#+0b2=h2$I6u`%`Pp3a7Y+L%gumIb*FZewbX=M6#~8x#Gu?%7lcudRo} zx)iHev&$R2W|t42tRA8dI=XNT{I|ky>%!l{>*^YKUHvWMq}^>gw%Ogf<7D`2owU1k z@2dr)eC@CyT3ko`7W>HCA*g|oU{9XQ8s7rW99>v7@6^y>5juM zY<$M^yK+%S?!q>^kL`WI?s)Gu<_C89j48mWyYB`bdk*zh?Y?U8yxm*QnG1c?>!17> zTJxA`jzeSa!WewN=9nMYbo^%X0h_fRwcJYYuPb+XGq%Dn?KboM8i$|RuH5zoNJqNJxkX03)>8Ge-z~S`(|6Pfz4<1Cdkr=fz9U(va`sZiA~@&_GYq!sNt+D zKyF6Nn@|cbvG;&_ncPIj@%fZD$#Db7O?DjryXAL8cK@6!u;nzNya`=Be;n0t@=o4F z$MJTbH_35>$xU|L3~>3Qu<^&U;9X>CnhV$;l7(38lVoxIi!H(J2K4_?Ta(>9uLLsCh5b4d6NFAUDv#D$y=wTo&@Or64gsg(N zE}#c}1WX2bhZ0*DO<(#!U^#me^r{CEMaR0`Uyk&k;nhQklM(Sv z-~@L-otEjS5s)pj^layG$HxS+;l!Z)yaY%KOdpGg&NcU~N>5V%1A%-v@iC+4u}>|O zW6QEA*WU!<*#^i4IvIJje*lqnCB455=v7HX~xWJ8!w=|ezTV6$=UBgAaWjl1(XL70Ec4tX)R|CMX{0-s&j z{eSW6tG|OCB;`jdi=(OZ*wRity2F~$6>l-odBxF7Vb>@Q`0gE}3yZs#cBG@%E+zE# z3b(Fs@wyP-TeWS2Vy^0IUL36|J`PS`yF@FBqdn4PrCqR0udG}2VJymf&YN0Z(z&D* zpKk5kh5GZ;fGbgPB!Xpk6DCdS=3!H2OYfY~Bv?6@8NL5<&D`f?>-Z!SM%J5ZcEQ`H zGF}BI<>%vjb-%_KdZIHUj+P0|oqoZrDU;K7c7zts;cP19Db*DVi%vPEce*_nPmZ2F zd*aeS53=FV>U6V$ zX<(iR2^?A9E;1V9()S>d|4sNxOnrPSsBaf3#Y^%U$X#&yE`q?(O#3DBjj$K$Ag4>4 z4mLc#{t?ExtC5fOvOZVuBG9f3NUtgWH>XJ`xU>b}!}?ZWU_AvH_2nZveK&%3Wk7nI zf69C=xU~9qk#!+`No02V?gZ`1PzS&5^JGZi$oh7X`=F2e$@Uc>I(^>;%`zp342`f; z=LPR5#xsraL7~exv%#U+MgD|*hhi6Lj-BjeH3l2Dk6{~PxSuzL`UQtDvmcE?hYq{f zANpQ_%mvpk#L(_}Z{T3?O&@A8ZXf95@nM}|ea(^hrCo$Qo(-R7?HunJ2eyj@&(tO{blsuh9NDfakr7a{Ge-oFIOhaJKMr;gv#O+bp+M$ZL-L2H`h_ z4+$S7;wJYi;jf7}(Rhxt+#kj75O061kp7PN50q}>?#OTd7?FNB`j&d=F@;DMB*bzd zM?9#1xcKvg7YZ*G@{!AOD~QOyR{ZVazajo!@tefkxI6McDjv-Xy$L_)X!rg%1iJ654qHJ--tFjPP0EABApB z-CN>!3;!nkK*(V@_J>`mbcQ79VF(y3l_S2wwTh46e=xqDN&KiSscmWH<` zZ}WEcO+|M4O&U}uSLNRhzohZPtqpET)?k!A?}#^Zyer|+l^R*c*i`<`82pRUr|7`i z*a^G0HIYYA@8^qoo?Ab}{PTeReGtS0iHY3?1Ms|Nqp=)J*28dp?zt?PSp?Do`LZiN z27rt4l`nGq6mDZVT=@|@jYWE1Vv^i$%+s5aq1RCoECPwquo~@qjwPZ@wBJmUi0~=8 z7+ci5!)kWxJ^GW2#rOi{)_d@eo%1QW49WF;iqah5_rnIRkhwwdgC!icz@szx#25-az)Z1BB}*Py{k4Wj5ySW%({y&Ig+;8eT}<%r246K{k}Byx-WlaoQFcFD$m6Tduu zb3Z%;6FHfp5nPjb*)N}wwP2UzetdkgkKp6;4P^^}|1&UtPDmrd1z>+-8$_(dh}Dqj z6EKMy5+?;rvWCR?fJxPmm>4jHH6(b5p`dvUi7Nx9sD{LbfJvM0K)%*snFrx1L{?8^ z8_g{!iMIo$s?NHEG=%ba$R=WPIiVa8L({Pu5|aZaVc*~ins7lI$*sQ*7_`ftau!5n^5t7Fb7nL>xMT>WGzt9ubHM;}KCRIT=`mh};C#QOG)$ z2V%l{MC2~o3Va?ByGnS&#Fs82@=(D29hF#MGq{gUq5l1n_d5jJ7Kvlt@6h)B6KzSx{XHh;Cln)?N-u3bU%DbLN z`Q}0S05av-RokupO56Wnn@MI8yR8|Vt6F(MCWGr!WT*@>1dz#q!WP)k?Gc;8Ho%Uo zR}quc(XpVR0c7-)BLmNf1C)0s3wAUaln)?No*m7jet_~!Qb!jCYNb^TKYr_($P6-m|xbkY~8ubNiABoE;;6y z3x>34)uNRVCrex!os^CqT^yY>Cfe?f7QJsHg79l39#$2$q?;CE7!_86X4&3)` z>=N*?bt=JQC0YP4A^51(!Ahe7N4~ru$#d!m&M9hARGq#-vFoxHOIh zhV@k*xqrJ&HS)PKRPlG{OOa4;X)C~o^(_tQ9>g3I>^1ULkhPJTV|^>Pf5 z`50b6bTs)b$k&sEf;+FC1s~pzTSEPUzsQ;WXbc+lX2M6%_vZ|kt&4SrcF$Xnv4%sj z+iXQ;C++^6~;5dKJL#|`ayRJ^mb*>QvXdC6ZBzA4-zwBv|;^^c?3+92l)PxeDo;SoYR zj*z=GFZO2-d^e@rAS?Kj#8(Ih3pu1oz0OuMSv*HMDX$b(2|4CT`L#l~HfFVWv)LiN zM*K$My~6Jae<=K!@E5`-gii~f7j74Fkd^hnE&Qv{8~{Q7Pw`RQw3+WY#!-brKP2TxK94Eg18l3tzobM=~^K0mAHP1@^j_|L-0z9-> zPZMGNH8b`73eHx(xxyQStAyVXeqYF8YU+Pc_`cAsO=*rt3e$^(Zmr1);>QTb3NH~} zCUk2>)`|a-@TbDlsq~^oA7V=i{S)Cets36b*3%2x z>r111Q&D{PF7`j${GE^c-p)j-$)0E=v2_G2ORe`s|9Wnr-}{)_$O-Rl``H_Naw`XV zKhNj+W6g>Ae5dyBM~9>WiHY3?=A?-{$NdD&@==lxIM^GUz>sY^uEF8;y3v#r> zXRV2t&0dJbTAJb*ZMZo{fX-PGe7Ejc(sg`_4P^1xeSafTq8-2_W>=O{LILQmj?TN9 zIo~w7m+!9t=kvK6d^m~dH<*R`{Jw94P9rv$LZNvk;~$v@bD4Sy_455V$ro{dzz&e_ zlf5d#@~M&JYqdX^ncIVHIDHn@qMWt^?3#eZni69-2W&U7yaOY1nONR{lUzaQ4`JC{ zP)VTJBf%E@1uR~Z?Z1P6ZYPKuaq$3et&L(LQZ7SdI$!FGBo*Wf0bd6Eu~S^Z(XJqg zl*?cRxnnBW0z@koJns%yaGEPfBIPnzLAF~3+kj}#g6IFv6R*-v$-Qzw^ zM4XD~&$0cx-4!B{a*0-m7I}t)+WW#rzF5}ycR+ieS^IL@B~Lvp-N47&HcfpASP9KA z=nQ?v0z`ij%jeV)z>J;E47qV1MFK99F4|h zk~9hD4R+uDeZlNyI3F_5Jl2_z0)514ojiD3bgF!y9Z{i6v%J$&uVgt4Gt_#!Zs zOMOPxxYWZzbV9^O3fatQMvlVP0{6ZI5no9Q1i>}|;1{{N9$P~)*pV@Wo`_hTL@n^6B9ImiaNHu6n5ozLRwWGB*Dib?S4Je57F@Yl(5L#U{<3GX?3R zre8FPGDh-|j^3rdizZY}3v%Nuw|q63pn z)GeRMIv&efZoc#!7WNc&aQn@up=b2%|1WwFn=@tZyqQ%8KCfuBF&AT>(r9C6B+7Q{ zice$x-!|TS;g;KcY`sm|-3fubG4?AcT9$ite0k0_v1_B(MQEx1{OmXX0S?KILU*uF z;_Md$J~G20c=-H#>^GTL05rfo?nZ#NW2Q#k2jtj<3odO41Q-^~gtzfze;keH!<_%| zsE?0nz6`iBAibYJ*GD82TpFLvj%Lyiq2OuP8KE@3?1byx1pCb%)yw)^z4h%kSK+^W z8tE>$x-NwvtdHN`;+qclBOlS}s|M}Lfb_nuu>sNyE^P(qu)a+peMzJ_eRqY*fb_l( zeLr$aLTUBwH(Q{O`^okdAUb{bt4s-yVFnuU)q4F$^*=@=x_s|9I5hjsG&G)nG+l5_ zeE|YTGi?L%h0kfWkKtLwaKAhi>K9rQ+ z^Ylym&A)EHnU8+|B>T<&9g@|3VdSyo{qJ9~-*jU+jDz(Q4iF9zn%w~D=Zl{ttQ6Wr zWuz|_ze2cDxK4PtaFfvN04Vo}_$P#0h4t+>f0f+UT%g=>IAPiDu0-4*%^m}^aeQ1D z1xCoC&*vX;nebYno#&9>B%aR~=DSPyE#Y^B4+HLxpaQ(mCSodO`W=;_Z3?@9bR*B)>vv zL$*lgm?`VMMYvvQ*AL|PiGM)2S-3^WQB{^dkX`FtrMv5i8VWM?}fb6mp=G{8Hhy!WBY}X)?V=xKVhokRzN-e^_YuZM>_v^BafP z(%t#*jz=Nob?qWOOFxZWq*qs1Oc)OC`)ey-gz(xKymtg^e=0YvP4wB?y@FPe)$sfE z9DH-F-W56Lxn0q7R_}_+5d#AAY|sfuAn_#4XUcWtV@>7I^yF0#9Gjy=mA_Qn4qtc{?jo z{?2$~+D{spM=p5dTIe+Sy;+`Kw_bkRU--_pN_gDzem;bKYr7Ehc|H2P*xLsZ6T1zT z#2gPACY4)R#82=|26hxXSt7a1$;EP(AT4TZFP+b=Z}Fr{~wnTTCxg-yXp3%NfUa!j}42EkA8 z1WluXldYS<=Cxp|dD-Hh{!vfxZdc>7*Tl_fy{&$DA@u?1`R%wa6Tez0R+BoM?KgAmV#J@ zC|dwYR*04pZb39#0Eu8HM}o4zJ9P;n+BJwc(dfC@27y;ePeh~-CMrDBEUir&RzZNy*mLj4A8*G8iW$TdZ)DHNys3A83k?kf@ zZ_=9^gBvf~w8)r(SQUE?We0b_uSE^HrHCjy7+@idE%y((PV0bQ3o}%Wh6K4zBdP{E z3Y%-*!ZJ0qL25Z7$`0v(UyB-YOA%3)J8glv`XeIOQ1e1&2Cp%YAlFc$YA9q4++_EG zy~xf$S$HrTh7@v35m9y+zyfozI^-JO0lyYCIFQ3gAVk< zXYs_A9$Qj|(4#DRUNMOh7>-KdE3GWr0I|F{dVCtvx`sVbhhHZrqf4pWtWh)7dJ5ZU`2U)LH9N z*?(@8M+aP|d=CD#(w#4wR5|ZNSm^lOk&DW}S52FD(L~@>$fs7$FY7$Fvh(E99+b?S zJ)x>I42maCn=of`y7L8-FPSiBYUi%$&cnOm<1w>lcb;1{XZj>$nK^yJ-08C};1^}) z&9bk{d>Y%4oRM8LZ|3pdxN-BGy~dXPK-ks8rW-e9+;k5X{?zHCIt=pkJka8xkc+nI z3#U|FS~(?@6BT>r3XL^)^||2mr7QH&M9Jhnd%~r&I{-Qf+I||*wKH;Ap20jVHA$a2adu&Db zg(`N>I6imnm?>=saD;1AD2?w38Y%;YP>69%4kGm>5c&QP)<-`ieCu|>rOkrC z(M)>;`F6NQh0t%heUXGQ8_1%TUG-NKgG>)x>^=&^g7zd%gd_SksLb+>#K!6?kC$gApTLg~L2 zzg7Gn#G5}aXbP6U6H_+!O)6kjI3mw2;Dp&SE` z6YnoXJKuo3H;_*Y+X#;nb`kav+WCh3eZ>zD@^3Wtj1-@`gwK9FZj!3R?}NP;SS*&!ncJV z3HfkgeF>qRhu}G`OnF+!A${_lgdAulUoIRZGE?cp=}J$j=mVD4P6IVf{5o z9Ghmkv*~OS|DbTQ(Ah*ec+LE;2sy8Y{JX;Xe&i0v!;p z;Y1KA_dm_z_y$g4|H}T2 zZl=cg-lU&4-G4&;^wpQxn@+^{rsCIZJM3Gx{5ra`|6zx%&fOVn*5o$W`C`qs9(Mar zDx!N6IZffEk9*2JABOf!N}OI1-Md_x;y6EyKx1$ zdjg4x-3EU8FkBV#)3=9bh99@Zf_~x(FdcnEm=w6r|)%={bn*>2}$RtuN@c|2j>tHF4 zZ8rNX&iCsj@s8Loj?_$pTFEAD8DXP zUxiQP;tkz@9$UXJHZXbH7HkB%^7+v*zh5WFIwLKg?^gaPWS5Zb%+&sTP<|h=0pA?_ z3TpI6Bxw%~nCFm|?8&SHnf4d5CuUf_J|+3?=MSPH8t#(3g#Dq+{AaR!V+h!WXgWEu z$CJGVn;`WJvV)mAjAd!DZ8$u`CP!z;JDKt949h!lvISc-JdJWkfl9W|uv5s=MjNF5 zmh8?9I}mrB0()hJd^Hp`@=uS<$96>C%G$;8mDNk)t-J#Mhh%?#+hvF$Lu4U}+S>q9 zxRTY1CamZ!OX4dZu%aKT=o>CWl0~cVo=|~CP$`QoWQ{rVy#-v<)!5I0IQC96J7xSP z?2INnXxN8?88Ne~sOq{a`_aeQ=^Q z$?@pw(E<(>?hC`t(Lt;e0)ODxG(lC-{m7M96U?C4xj6|%ru*pt*ZzLgT<;n+n-C5x4AE&#) zR!JCui0>6G3MX?`+yUIdF^NT*dGi9ld4i95Yjf2cz%87s8hQe^aDtENVNY^DWSb=! z^vFm8=S{&0Ts~S9^zc|h8ZpdjCpCO=woU|5*8yya5=03 z1}e`0WuZN`gAj3i3CfvZ&L5iiENm^b!FCxUjvG@SFp{?s3!ShXkBH+(ke+0=M&4m8 zOvRRBoG!JC`TybJfVm}eG?{uAB2ECpcEo&dM(VP2$KU>T-0^)5Ase!=!*2ZnpW4lBT9w~*gIGoy}xJnoHL9UHYeMw+{rLZ_O4 zKS9*E0|sOz!OOssPtk9#9l$4*}zBdwMP&Mgr!U0;z_je(cP1#Kv3B%AO5rAkBkUQ1{?v4sH?B zBZ#=o+m;*mb6;|(E9$-&3+O(!?yug;r_busaEk|@hE0m2v(nKf=}Wi_ z?y%x6CDDtDyL9W=wM*xcmd6}bc3c;jNTV00xxFOatt&oE)ul~Qn`mB|pQtJ*E*sdr ztVM_JEqaw6Q_`ZOWy`YY!gQDRy^7i$*P1Kn%A%)?iS`~`M%(H(@5<#}x^zCKB)VXX zc|(Lrl}qbBZc@c(fW{5&J9^N#z9R>oF?7JN(c=b;965ZXmyr({Fl-=_18H_G-u^7F znKGkJJ!inUp{I_5;!_66Ad4Qvim!}WF#P$eOu5kmMvWd<(f8CLXN(-MADiNTr78BH zZW!yDGSST;<7}q8X~#Uci$-VX&8*9Vphp=Fo0&i}2GK(^qX(Ca9p}se9@cl*slzJF zg4;EFij6wslv4(b8udAtbmvx0sG2wTAU0ff*xZZfRMAoC0c^Rj>UIqqbg>jr9vw5g zGV0V}1J4-JcjOn@$76eUkJoL#UqPE?c~>Wv=Ux-PHs`w7_0g|HZt(jSRO1Qq>1@CF z%vdp|GgK9S{N()7?i+Nv^(n}9hzUge)v{0~bl~!pKtP)RH5iyL{AhL$aK2n%cs&z# z93D8@pgoOw7+K#CM5i01jmsYG8WBq4t5H~A0*cn-oq_t;7N>7as0>K&n@D({go3MU z26#s^X+6g1wo!?KOPdNlT<<+FB&Cs$^-}KYy%e-71Jb(~e-Y9o6kHmILBjeTKbkM0 zfj*e0GWu44c4a_%E1{41TySaELJ-!sJ*1E33fI0nK)W*3aVPX`4hbB28`8r1-he(H zC+=?}M5pgw&@99Afnh=tbK>e9H>UppF`VxQP;xN~C@_ujVMG+Kl-O&Fo$ciqAoDQr zRnpPq$0HwK_+4Q87@k24@5i1{zZ4?P?FWZ4L(TTqLEryC=7Ot>7`&neDU+Mx?*W9( z!8SppJ`}Y&!}>Phyr-?l1*gyP4#V=#!#<4Wg@WsqKorefy^iM*&W326o@4*;%*=+U zCqtM-Q9Coj>5Z*l*dIY)k7q-alRH8oYCV`0&{yP9VA&_Ux6nS!0Xr8=@5gTG2k;5W zr)!-@ZSdzc9|I{o*NJZn-xJd2L^x6d;Hwk|#d_?$!aI5eo;j6;8gnNYCf7bJnFoJ#{pC`0+Sm2KlUnX?x zu1+S8`{*e|Tzt092l>wuKUVptioa0&Jn;*~+qx8#TPgWk$=8ejhWPJ@-z5HF@sEms zTKu!(Uljkcc#eCroqNQ8DBk=Ca=&rGGrfQaoL{;r$;aL-x}fl!rutr6q=0G3GKXu+|Ebf*^-YJ+Ib1NvmsYXP7?&{ze>15SS_R>g6UicMZ8b=fN-aG;R34yI2RUM{>s_*LOb;Wvce6#h*3 z3n7gq)c1SgF5zC`--SLdNakxMJWAL_*iA@l3-g^O94DM4oGqLyyiWL4;hn;72)`@* zfzX~`pI|$-`#0+6)40w$%(9YhrLr3nGPdL6_isDy(W_V2Ap5~>$5niZ+>h<}ss~ml zyj4qKG4@w?+L}|*600)XPfPFf_FOm(-X-^ai`x%(a{IwC73GDrmfl$e8*VwNV~&R3 zN~7)sHQgxx19uYp``p;I(p3sdV{$;(H_Uzix|~ z)z$m?t2~z0)R_N!pwAbQ>jH_1-3BIBJ3sxzGKiuBxjD8Uwy?I^1ry2r1!bpm<9t{0 zjF0{jmvzQ><#$*jk#ianWXa7gzvP^fC?7KNUD=yt;Jfm1lKm#Ka4grZZ$Dv|b0TI> z!&q#ADUQ93j5&Ue?5=#`c=4^!yCjYi0Crcti(DQ*AM!=7#C4eUWG-;6IJ-Z^-9d zV6N>1S;Oa}UmD9hGg9II(%5}q3(T}Slw}*C;k2j0U`w_Y*i=^#M?%zs;`4du zY&-%Yx;ALcIdvqOxD1E!jp$TJR4@&q4Wd8po37wkSCB*#m%$2h$5gN_h>nQ<_*Yy( ztC}^EXyP(hLAF~3*|8-oIDt1;Yw9v;U_la1Tm~!1Jyb!SR*P709{=@O!CPEG5=~qN zEBGxdSlAN@u%!Td#14($>4Q7}FM78egKR>mipG zXWFGqJDgV{(^$uR(9Qh6VSjQylnJ?cA-Lv;XhJ^FI@nKVLay(tleXiGuTEzkU9Er zmw+zJG%I6{hCAkinxlE$!8FZNEEAf8g0+$`77#gk9Y}&9=bk1&fGR1vE(up}evE z$TGtPp?qwy1>T2(y*Wn`J1~LhY$xI^(6z?NLcQcf>1?)4LwGM!(M&@+Wo4O$xE;eP zaim(H!8@+!xs)={$AWWB3@5!57qYgF{|De!x&lL_V{^w@q{rln(7m+ zOmmwz2Cg{2YMwgZHLsm3jQ*R^UvVBhk>`4&KUh?J+SzAEXN`##-8T%<_sogsSLwua zusQK;6IdEyG3l1I@YFFP9-{fk_IiJAKtm>&u$l1?y@O^-e`##Q+R)0*lV;DVnloWi z)rqsGPQ_Z!1NjWibXz?;aUBa|cDN7DAhR~ZI(g(+G@~zLM}w`=9EyI-2$@xcq+mH{ zrnC%-8UEj3N~|~j>Go7hX2WYk5By!YFPLjl-q{cIZ8+Yd4`4Se`BdMAJCM!rOTVI- zCnBDG7Cwv3a7{*AFn&pv4{;2WX2SNuL$et^juLO+b>9WozCjR#^>Hy6XYMwG9B<6_ zz~>vp7(`bFr1t<`HBJc$966(2zQ5wH^TWZr1B+#JOa&dTw+yAvUe? zXS|nVfXu`2ETW^yk43(oBoy46GZ zg}kr)D>lP!EQj-)=OuA~aEOq@hm@Z$oFwGQPx&Rn#ljWBmBMwx|KB#lZa8V#UbDFX zoegjf<+z{D7n&^)7vnPJzkvvTwfL`zzf1gm;=e2Yr{Xt@e^NXbakVpSAuzuc)tsO!>zsU2RNwmM~K)x%G=QDzMyzm5Je<80^ zrkm{@I7&RnCMdV-33!3{3xx}Xc0D2eYVp?ztA%`zp`Nb^?-br6yidqy8uR^F_=xZ^ z;nTux!aoRK622yUQ&=nfNEqe$3;nsmM#95{9294IJ7KYqe`y@VWvCqGok;db)lg&ajEUnS(=IC;BnfgJNDzfQ;zZ}Q&} z+H)Z{cpsyjf#}Y6*YAAKsAr4Y|F_}}V2kV3t9y^Mg@fDTHnTE}iY%J%7{g^8CHKQy-S^xqE5uu2}w>U6F;) z!^5fbU`qd`f7`uzq2>AOs-<Oy+%aTMliFR}H9* zt*Cx|Ky6}0)$0%Jz92tZ?XQfiqE$0;n}2KcmZ2u~SK9i}TOZ$Vp5^8Y}lC@&K&5XP}V*Tu;CYIZd+5E&wmOJ(XUcoV}(_`5fpL02WV(+vIVPM* z_9A3!_-m$~#m5JySrimA^=zuYfb0jz60qa&;42u%)bpA7EZhhheFy^oB`o+ee}%lM zX4vH6K9Nd-7zd*93J`2ZkbMw{_K1GvdoKG|T=tilos*uj*%u)zi}+P^cwyQbqDM{p zBoK`stCRhHWSz$B3r4%_H@fW4GW!EAdlR-j4UP{+|2otB50|waZhVdJa9Qy^;;G1# zGu*c$;}_lr4uuZ3nDgIZiIa)#vsvP3dK>AV5qBTTOF7e9W7yL$E2$L!AM6WxE)yP8 zA2+WR9>BbYKh3zXE-xbT#H?>#OS3P%5ri^CSi2JDr(rg;sCI|8PthQ#v$ldd802Siw!2z*6BiC7JZe*{dTh6K-9q@-&|G(kj(BLQuV z96{h*EM!U4kSI6#XhQ!$9;+e2mkrBAVkRQ=@DIa+K;FED#NvQS)sW!d0xLn{!GKBE zka#9wn%9tE{~=qd293>xG$>dC3A|KbpIl(8@ObTjSyV%UR|fp=5_k)RJZ9?}cLz*W z4T+#LP@F`{>OwXW>p531w-tO@cjs3F1sKFFWlH7IqvhQiq$ zLt#{$329JRU`ybR*L7n|sl80YILK3_9FcBaiIa`4O7KLfGP-&gacv+^-2vPvIq|VT z-uxxt|4L5$D3Dvf#L$8W&NH3_WdUsmeTdQ3!-!KQXV2IlLmVo0&7we_V9zWIXzQWd zM6+k^3FzkRn1=&8#h&3q1obA+6bor=wcoKmpzV(X9MuxF-^ohQ3lQnRmZ<$MybJWb zk`uMxMX!KOyjzI3)Dck~#+)k6^0mYd} z=z)kceMt?8iGiHJeT3Yv;ZAZVpq9XWKvBZ0ft1xUq!G6x+I2&MHy<#Q?ON02RTaLx zCTEme8K=`2l(mq?HaPy(!`(H@)78V>U5G8F3+zjGiLo=$N%ojvM=-AoY0zbeyo63d z|1Unn?N|EEgY|cX9J`np&YiagFq91c8jd$_zXGfLOPL3Qq zQKG-YWQB(RkG(5_ud2A-_rCj*ypRB4Q4u0OAZ$WH62dBK2!u`cpdz9q>`<0K!eT&0 z1q8JU1(#MdXsJuJEmGQArIjkR+G>j}*0yT3cCmn@;8LU5_Wylzzj^QG$r6#af2;F* z^S(J}X3or=J9qBA=giE_@hWn>hEdEnsLA0+L%%ep65)4Ec;lG6x^)Bf$DHYN5p}!B zS97LM0=Y@#OFnsnGVdb_QiO?j5*sAMz`q+er_%7M8TqkF$!?Cx!KIUu&E~EC>TgU74 z>01=d=d$43hG<|c=TM&T&D5LR0gX<|yax8C&(}ixjcxCs9YIFmaaS;oj{reu)A6y9 z;bcWJUGTPRA1=Cr50gmDWwxx}yoMII_0SGvoh_G-9YJ{mA&>SZ&Ie#!ST5^79^U3b z(BU3~EdmT1oSl&FDd>$#pt7;frkf5%u-r{}MtThev0UhXg3Z$#g zyoQI6F4$LDKf0g82ajV9jssOR?a~}*kE02~w$CHzyasu%G9bsg(GdfO=iJ}IZ)dli(osIg z9wMKAh#Z%Q97~AiRUOECDCt~bFX7Sb{l;L0^i(=9-(|wd!Y>Ht3zrJ{%FgtwglmPI zQ$)V$cfdq@KkosI=PNz&d&0+rrvHKewCG<5eg@*UBah@&kJ7={$BXHaIetz_jg3s3SIR_zTWdVO#cTq6>XL% zf<8lZ2cf+l@?Hca$MUN8FT*`8$2)`hlFI*yACcIX7o$zMi2H_pTYTvu)5q?29U${iL zOh_X<)88z-UARg3HQ@uoZNl#g9~V9;d{($yNZUT;|5K+$Q|4@Nwaj zLe55@++PcSFMM6NPgo=5+ytf%;XRj_Dr_ihE^Hy>6b7d2BJ3{gB|J|!KnU?hwtb!f zY4W4H8jJ`NpL_T|#&Qy$e>#bu_#DLdJ*Mw1>?a%|94;I!948zvoG6?roFgn3RtgiJ zk5-7kQn*gIQFyy>lW?+qktF4FN!o!58SFmTX_L1(RV4vxF} zxxG&DE47=q-ZqG0-r)^D(tS{VmU14}#$tD%4bAA;V(@-9<$-1|*G5LCtVhW+Rvu28@ygzCaf|)o$k6>ssawxvuPlKv$~D}H5fa=R@pr|tKWO#SypViJDP>?M4&A?=pc zhf|7CPARb6eQCGyCX&LWqBk`gyzknQ9 zoUz|ap~P4AX3Rjo=u60JWqqqzGfF@UcnGI;{C2U(wAym6uw;BV)XZ$`7PJHcxzhAb!<{4>z0}9hewpR1 zHsIJ@lw{iP*0k%=qPGs-clF@bw?(VJY1;0LTcc>VmaONDEvFanPtlpkEWWv!J)39V zc4xCTI0Cjn>*AiRX6#Q=dqiVx`sg9ILHeO+dfK6A+EwrT@SA5o)_q9GZpbb_ZPMZPV+1t|2-?!@gBDBSGwd=Ny+IQdC?3t(Tk0cM? zpNiUrX0+Y#t!B^F-ng|rj;}3y+6=UzyXEvz`_|?2IE!$uZ)o<)-Ygtd$X(H@Y=4T2 zd~U|+1NJ8&l&s$%bS0 zKk?R(Gs29KktFkq9Z7iAtZNeQ+G8O4kw}9u4d<`Vm zL8SgYM&6Fn8kFVYs}igZHz;Z_*;4-^g^g?dxaGK6HJEBCKBlBDK^Au$t5C_?=84Y) z41T~N*?zzwB{sD#xS`zOJI~Hy5I;Fq<0RTzCzw5qC`y z#56oY4t&U2Ur5Y{_nc+nY6jl&iAXgA)WjhsqnZKk_5-3tH3Q%D2@DhnJOb}JmvFtu zK6uI{z6I|&Rm-axxCRx%-ur}`Ox>#DvrSNvsSqYqus-L)r#b5fCa*6{&RpiSttNxj zX&7L(i`TFYJ6_j1?0BsW8&WB}UA+Ej&N5UxITOXUtqvT?Kpx58;Z43OKVR?6YO;7R zv5F$9+8$j)%=)Du3Pf5|J?40TnD9o}Y}x_ey+7M>=FYt^b?lW=zw*eUD zybs0^d&Ap&46jxkkqSc_$FNZVA|G*&iSuPLY?K*@Bc26sclu}8EObB|k&7MdcM2G$ zF^Y8|a$%A!k71rh#u4|KI2{AR1*W~%-+v_ogWzpOhUeHw2IiSa|4Ro9``s5g8DO*9 z>Y!zeJ6dx;gxF+f{D$zw8^V0HtO?NU-os3j`0>=$QZHrG^8(x#pg%-7#~hNMp4Vhm zfW8vpy8`q*2>VUor)QYEB;k7(k6g*X;=qA0%!9LEXNVuDpE=$KD^P9U|99T z@q}6tmf8yo;c`ecj-$dO@YqX* zpc2D@64On|kccFlZ^S}TNb^A9nSsKW^O|003LisI;mZSs^R{Xn3m*rMOPSyozC3Wa z%gy25k3+}AV1i%xa&zQgHx*glg7{NEyp)9xGlh>PTnQg?mMz5m+{auxNgh3u8DzMK2E&9XoFJ?dI_KYRrzSlJnbF za~xsk;&)X5_rhb$zp9!6U;G5ZZg@Wrwgn=w4<6+a*xh)U606|N?m>B()eQ5{Q9~4B zTqgdJ0}eNExqFZ#=z?@_Bn~-UaoF{qW%lXV2)$zLeXoYyQlx?YegB+OBom*5{tt zshhVXC%bL-nQhNl+{s&-)7oo*4|L>ssnfm7qn)zNU)$`n&%sAK*3WI*wQaYdZO-g= zW}8ml;+(c!y0tySYf$Me9o8wBWoficr|foJ{XAYO#0?vh+wJT&XP(pgBUwyYDlyv4 zTa=UAqs>L}!Y(qIy0$%IeYZ2uZ=8$aF4kMw)5OSk-$+4uwqeD<}h(D1HpyXKy~ z-djB0>-Z=b-9ll^P2+5{vC}FR&8akBvF~sGi=5-n1xslE_?JQad2O8fB)K?2NBi=J zndww#Qq&Q?@qtND<|7n?M_v#e5G}~*ol_9a&&`AWA-_ko6SfVRR#q{sbMz9-Lh3ec z?&N7xr%s!iT`;M4_T+_S^QO#iFO^P>5A-SY~1T^h}vJEeTlIaB5@#3u@} z=N5pjoVjT3WZ-o0r={#+lr5Z|ogd8} z)jgU$ect@+ipqtvrXb0jS!ETo=FI?e`l5MLDp6o|#WaHz;7u*7EDO>f-Fe3zrZ$oZ z%r)aVnpCl9Zv5*hoEH|KC03^a7xe6o)<%Nv`M{&hDdX8O63yp1{5Ge|0evS97*R5` z#Q&dEGOcn^`J@XAa+WR?e_+YzNyBGNo>($}(ZVUyCJr7j;5Z-K2+kmj&vguTp5S*j z90=?i?Zh)ZZvOl^718PQ7e;Yjqs2O}(a{U%PnlLxF@Ir2=abMCoc_HrsFqE``E^_l z@<{{yUNNG;Np6@jA~nO$Jsj^l_#Q@sk-&4!eqzGr6L|N&JRJ zoo4%#PabQ9_CjmmKIppwp#}d2h&|82U^;vMOH9W&x{mOC?mu3-u1J$u?iQN~arTxw zLg@g;{RU}v+QPuG!J!DJ`bo@x7;|klBl1*Gc*i#KSg(uWZ5{+2+9ftJAZO!fAGcvf zbwvZcZ5t^NHv{2dxm#MIT(2?Gyaw=A z-WL(Jc@T8YgS-p|_S=co1k;c1(T{bWHIu1epqIpn>)|8 z@b_*2+c+!F(iVgKlQAa@-8A5AtN1L>Tru%z4^PuU=b1Ae=Xj=P25I)JxbtF*dVQXU zo_Yp?Y!Bc0h6YRV`ximyIXnw-$M0oCL9$Ia#&b^C(H}_@CxX=(z0J6HGUs;%;iZzV$B zqoPrLQ*ZWA)}K9#$i73ww0H&kbo!C%# ziqOtaq8^^{*+Mfv4|IRgLxtQyf$8eZ(*r$C{8_?9!pntM3s(u(3vUtLDZE?w4dKJW z?+bq*d`9@3@CD&-g?|?A6&@14D|9j5@i>x%4TVjFX9(K}I}5XgeT3%-sezVtqV#A~sq#*hrW-FQ~2f9faA!JYgT9ogY*zdZ=)W z@B-mPVX1JYaE_4XFV<^?@H(NLFSJ4QZNh5dSA|~}ep6`Y3q30O2_e^Tu$-R@e<}Q} z@D-t*KeShL;=G|Sp7|*!BFqpr7q$|fDeNe;^N8|A_Y|HhED{bCju4I$ju(~+rwVBy zWPO$jR|(e&*9kWY?-brGykGc`@cY6a2zLpe7VZ}A5xyq;lMrysc|LtKjyGqzy7N~0 z^ohn@Y~D)GBY$J1S6)GZpZfUwI*mp-a37hsvU+Q1-MWbTC2xJwhA`%;+_WM*2y<8( zz^8?7A3NxhL0fB`br07%I|r|MxHhz6)tZ~uJahQQcF!DM^Wej^$?IAiPO06tKN6a< z|F0F#9=`6ut+mN38n6BF;k6H*emL^sj}NbIx3xC1u6XTJNI!Dz*4p$H+xDj;^_vyX z9A5q4Gl#Ehck1D!zdu}?zVqSQM(e)RYRdka zx5Dk`9LjK>MNaHMAhc~tT&9ru=5nka}R~xzdXM&b>O~hr;gh9m5ii2 z8r_*$TDb3q(oUtxnnz$;hVAn78|J=knlvY8QM$+F*rp*6{SfL*2cT=K&yH!;oa|nFpMn>kUho4@ z9`{1?dh}wBWD4p(n!yDO7ENaG+x+vVDTGrRQH~qQAwUhQ{2BH!sP?8W0qSH-N+#R4{ii*SA-(NNe&^& zC%OoyF}p(_Mv%K4@dX-_5Sk;HiipTelIN2=A7tuw1l$oJ{4XKdo_P)VJ%r4xgORLG zFWef! zluP^zJknfQ%|HX5C6o=|nFD`$HJ`fudd9znfuyE#ur#r5x$v;-k4s)ZIyti(c6~C& z!($FWjM*++O%^LzhaInX9d`T(3>#7@yj}cQ(x6Bo3njFz4jk1u9#xGkMfnOc%?2Yp zusRjBN7|6WAcz8y)*f@fk_LhPcYU0(SqM@u!s!J>^In4K1w_7E!p2EZqw%VVIkpyz ztESPA1QI3&Buu1)bB%-&f+X-_jyV-|4%{+Fl0K?1|Ok)Kc zE&pXmknBv@5WZwXcsj!60h;IbngG2T;d=t~y$G}ZHvh58x7|F15^OI=ILtEcf=4() zWYi+8a5M|d(d_j3>BOh~@N%MmG!t1&Q*$&6mJ@lALQL#v z3J}ku055Pf3j#;8z#Pp^KTRW|in;PFgeCjRfb7^IL=aESMKXFl4cQ$K-VP6QJ%P6r zY{TW6OYt`#Ogb2^O&Ik=x?})vA0{1=7?+9vkO`R~+=SREgDyy$TkL1oL~Xy|a)Ku6 zpE+(nuW{5{5cL}O^A-;CGAeVk+xBSdT^{Y$!>h`fk>{o5cvaDEUAuQXqkBhgmXbOw zJGXl`#1)>=GdtJ2c)HiApErJ(m%nahZgy^NH`uhtdky+|i-&ogqvv*Q+q&&J-o~qj zVOD+}oAAf611Eg2g|AwuYqvR27#l10>o)la0r~d;gtfva3~n5mI++i9FIbXqzx0Q6^HV8$4;~rQ#ZO1eCw>dL|gGbq>ECJoJ}_a zbg%KIY1HV=Z%S;)k6 z*4enVUEAEX-@p8A0^`lF)75^sCF3k{ckE02~IQ21C4tcM|sQ5YH zu>=m!$$$_(+8@tWT!?;3Er)fKb0in!e{L&o>O|2Zu3dg-q zVk>6fqHVKS$hTY4#s&$zO!O3Cxp0y28X>P!=DSU}NoZ}w+eH6B_*3EYLcUcn|Et2k z2=@!$6PmphkS-JL#`Nuo7_T}CyAW}K=PCYd(QId?A12!Dp#b_~(U&QHrs%n%mxx|2 zdbQ{qMBgI%t3qRYMEQ@4Ha14kzf}5{#mC{8dh9aF=k8 z(42SVH|HJrNAceg)(X?uZiqK?1Av%jXXp+>tJ6P6^l0HY;WXha;R4|z;TqwMLNf;d z<=icLyO8%})`Kci;?IQU{DS_qXrr43ZEec?#IF$^&!*fQgE8f|5JrXOn>XNh6`d>W zB|KY5B`x!h5?&;{L^wq_L%2k^On8IP=*=OA%3;c@7Jg6onDA%9UkG0k+C41xi~gJN zu<&2PG~A>pzp=2D@Jt~U$&5c+I6yd9I7(O|yhJ!jXl=!IkBUT_v6=G^`PV4@^+L1s z0DP*hSw83X5Wg<`rtrJMM}*8GO(gTi-&d}wBU!@@LSW1+ckro_iv3^RUup&d`~c#~iw%)`|3 zxI3PWuxIaH`F`r-+X$EP0Thq>1qM3d9&n0taQmwVMptDY2;YD&z@$g2@imgFIlGev zr4O1u=!FB$^?UG5m5m47>uC*R> z14+YfIgmVI&w=FG_+rb1TMnem?o_k+D>G}>T;HcAr7BtzxqfNQeO0A3(FVP0hE$a! z+@_}O^=)d}wCs)eyqbEOBNhVccMUNzIImej1ON;(ux z`ttLm_6^T09auIH>z_ks>|S@knehApXZG_4+zIOrxU;9#bbz$>6AEgst6GFF*+|lC zx37CB;!@IL)Ymx_asKf9wfLsYPvC#>X84AKJGl0k&1vr6rd`7>?|CjKb8%&FqJyn) z496rl!qWf)p&6+|DVLB6CvpC%cPR&P`+b$6jEE%NMP4N3NeeH~ha4`}l?WX|$`zXm_-c?gvJ{!2>!FQY?<{u>AS@6}8?fB=T z0jB~u?gWyLk-QY5+)MbNN2*OBsPQHfKNQ`B$l+3xT`+=`sz9SjaS1pb}Rk!v7UZUSK&f-ru->xKZD< zv(tt)3!%NzjnQpPJAVEUDQ6WIgBkgS1Ej}^1r@y&ER ztRS~-b^Jj2q7ifNAOve0fh}J5YZy#b2ri6l26axzjyWEEvU8W|atz-Nk6q?R64{Fp z9zc9VeB#r7crekIxo#waF_$RwM#OOEdLmm8;UeNgez=&p!w(N4KI?~v5?}Yj!-y(t z6oSS@@jn$F^2QLCoA4roD}8WN@N(9xrC+b}iKD2)Ry4s0TH{`E+&0-=PlhBc#JD%dc~b&O((Ce3j{L)sB+HQZbFBWo^W zO9IUTzsYmHFu<-DjKy%h-w{?@{!g#646Jtjgv%`JwXpJISWo><8Q!C-`ojV zuS8qghqzIGHI^%0R-!Gf8VB@(trXJRa%UhMEH`=z>W2bZF3V#UVimm2gP{5FS(E`e z8@CvAP~PU2^|PgIL?Ibg7|_aFn;>s%Kpw9fTR%QL*gOb2TOjY70fr4y2OO;5PRQf& z@p$~%n zFwvIwbf8_(bz;ZS#4pzt>)Z}`uf?c%o3WmO!*hB!b<7LPY2aIVJU?tZdu<@-EJY;s z`qoj-kzA1f@35tD9pu1RA-0wLntYnpVR8&Pnr+R$sUCG5CP#DMwuY0$Ya@gX&GS#h zWo__uA|l%p(HFXk-(A>O*k3qAI6^oDgjSU9;TSea~+#-BHxI_3P z5#!HKgg+zV+IwE{FNuCl^ghvl6aBvEe~LCX7#=^`m2%8W4rud&1G+Q$pt~!+ztGs) z5O36Gz%Pi;F`4PBM5CBGI#|>0s6Ve29!CqId8Yww+8fC6g7Lg|h-V823QfC%KSuNg zLSx$mf3j$f^UObAxKy}Yc&+d{;Z4FX2{|4zKgUnv{lbTYj|n+`G5#sxPldk~z9Os< zz9qE#%BQfskiUg6Qwn7B@pdv8$w{lcxn?ZO?xox-Pu&kA1_z9#&u@J-=6!dfA3^eitd zOc!PdTL?3SS;9`jTw#H*pRiCkL^xbHPB>mzDx4~$=A89eD!f*Bo$w~%mxNyy-YL9S z_;ulTgx?qL6z&r8`I~b|?05^(Zx3M|n-~(=@wi(-UXQ%ENi2F?n^-|!y=`KD!hIF4 zj!le~Fz)%hVNmDY(_sno2087|oY}GTD>Em}yr=Y6wdw1w``~LIoH?sw*`!%(Kls}F zUzv4J8924C&e~NQ-i*+D?zy{=YFBOZ6>pSzhoW8>_NZ54HmFvxL7logk{ihzT^s4w zAAWRgxZk%AIisFDgdIp9pMTI9;P&kg9xYC^K<#_p?sIGG;-<=Bm-iVgit<1B!o~_Z z*qQQpow^Y|F2m0B0!O`2$~mCWAMt1Rxy?i}k8SVup3J1-lrDrw(zlr-lESGCag!76 zMBY7Q`J3A|L+-HI+!h&)cF&Fc$Ycx~Wn?&vJ2J$Cxr8f;r#@+=y9$sT{vrNT%*|j~ z$Xy4*aJ~(v8WYOVW8qbI&IcMJRn}jHIC}ePoPWOtK_K z-c9l;lEayIC&{11$lsIXJF<p&;zuzJ_RUl>LBVwGUeC((4-V8U_q_=){fAaPyjtbuUOBpLVe+54Qe1W9iFC z0~aTyKy*{4Y~nU`ZOUe8IQXVG*Uf`5XgxZNhz@OnM0VvwJ79D0V2dM^nqUcGrU{NF z%!Y^MZfP|i?D^1$)P#+e4~#iq+L*Ysaixf(h=j#!e!{VY+fD2x1Xi%F*$gdXcC3U= zfoTWAV{=i$h499vP>R4*_$0h?V1*BZet~0I}0OiBhfPdpScJXoCbuJ=M zBFrZSOZ_mxIL7D0BR4@wBg9g8WMf+y*9rf;ARv{Xq#1#vxRZ3%QM%Ta}l8w9;?pqZ(Lvem%^iBhQ=Rdu)Ybb zQm{f!E?)(VJ3{I9l20hT6zPLGd4%KzlJP)Ul|Y&H*n>HbZ~*qg59B1P6h4@63v5q{<_>I6YED6t z`S+g0_pckf-h!MQtN;s#yobWW@X6`lEsM78)T(_uFuok-7qJg4%V|sMrZ7KV{lT&v zgjbuG70YuN@ehy5_AJZsdPEDlW%ls;=XlRM<1an`eDCt{9r3AZFFhLaaHisGwS246 zC*8jDGxMqFz>b}>=8et60xFDw`0LKUf_iPn_D5EZE!{)%;eRmPy>5Vfw(CM2g}_E zMRgSEST4)saS#{7TiFOY52PR+19CQQA?TpI?JfMb8_MHTrIoi9VVeg*=NZWB#DJWQ z<6C7=-Y&@F(+%bEnz8bzN40qnbPhq@jsU|3`IZ=z_YUOo_$aRtyp?w!!py_6=)QqW z+}*`G#?fyR+H@UJsRcHX;+T$lTr_LBjk+D_`d9+UG<38p*)ZunNEhsbtREfq^1*GbnElBD;ZSot0;4 zi$VU$us`v9#hq;xpYxxvH=T~6*dD%Pi^pAk_Wk6eG24V=dxE{m4$atxKGD`>qhx17 z$K^FZI}*<`5tpw)){o!$ZBIm^uHttW_7(OQ4ic6K#|x(k=Ljo=R|{7Q*9-3weogq0 z@Y}*ig~pzN`aUoEurL*k!sEywCi!CS^2?Qfk!WMb zfc%xBjr{`j2GM414`^!1SU+RO0R6CN^L<;;J4OGL2>KVIe=FLq?fDC7oS%2a|EJKy zMM!=+5&2Ie;`mz$&l2BkL529<;`bABJ~;D@7H#bnQ^cPmguD+hKkpmFdxZB2zae~B_@wYB!k-I&Dg3R_+Ts2pdY|xJ z;rl{f{46&tY$$9Zj0&@aU4-3)roSV>HX2e0z~y;1vm;~Rs0hK}0Tci5+y!J)-kAEhxl)Tpbv-|i_;qFa=M9=QyH5;jlT;`Zi!E zq)WQWm`##+qlQ(5pXg>8{9eK2E(ksJULR+T(hQeFeO#V7Mc z{@EwHi{!P6#04T}fNYdQQNx+nY5W%ccs;NQ+{-uuWbn3sC(>nbTznXTCN@FSOmKb- zjxsV6&zU>P7*LpzHgA)WM(!pyfywAUvzii_iFYBlbRN?)V>3L_nv5M0XkrtXj9fda z5}D~NW-PnUW*liVPG&}%z+~iynIM^e>F=Wq_gc2!T5!|(4CRxXOrlS>6$K+(qqvPF z6VEP5WMG9WK=US z&hSeJmzm&b!gP38P_C?Ipwj0PuJQTHV`_HL<`oCF5{l+2)(WKxEQBIi2(Oh)U||zO zGFWne=~smpeIPT*vG7{Rgv`q!k{nhx$jvm{I8Fo?)gbT?JZC}OYK}MYV+m}ax<(r? z%;T5Vh49Y8#Pf*m=^G`n;0|~gEOAM z%eouX1i$CY3A!2*mUFEJ|{f`^KRFlq2dRv|nO z6JQ*9iCJwE1Z*}-k?b0H>`-a4;g1(kIeY_LO&ddnS%n?WtR~H*NJdxzkLW5J4br$w z{D({^>@)Dso@*UN&xU7zTW*=cV7lcPK|iAwAiLS$$+7_Lf(59Ni`7P0a|A=qH6a>+ zZoBentSa)R=6F$j6mHUZugmy}=XY-ZW$#SiiWC1j7?u9UreijH^KCkD8;`#qU)8jQ z^PNv>=$SOB|JcEK&S%lylW5MsraiFX^e-7-FRM>|jU=XH$wY*+YR>0JY(bMIjV&&5 zj1A~NwT39s=<`2g$KilBuullXPqsV z7&ts93(u*!U>?toGY*A)ZpUGZ$KA)V$o^0I3E?xs-NF}ye-OScJOh1@`HUVLXyy@PK+-y)=jigL}oXP}u%26<1Dk8+f2-A(+yN`J1<=&6zKLd9Pq{v_c{@vXjkiTJCU2r37G5v>vhYsfH-#L(nf^)PPlUe~{!aL&@SrfH^P4PeC~P96 z{*!V$2(yKGLMlWVKUg?cXzed%{TkxS#5esG^c>N~{s{VV(JO^(gf|O~9TMqGe+J$! z{#N03p|L|E{&CU26#iOB6)o#)`}ZNyN3+9N`^#zUFUUuoF45Q_f%&3)3eOSt7h3z{ zc+pe>GyfNaiT(R}@oy4R8O-#iUjwNVCjA{DHNvEgJpf1@FzJ_tR0WehDCA9)bXZ8$ zFX_{S)Buz2BD8x4o+p|bU&fCWQt?ZAx{zvL(p5q}*OC6BkQ!god^RH{u1|VQ{KtiS zF8w#zjrzbu6mzllH%GA>^~lff?I%9|o^&ts0TDx_|GZ=Oq`NKBW%oH|fxF}vk%owpZ##n;HpE|yUsmlB~t7{ zij_#Q3n}dSo8LZvmD_t@A7epkxZ9hVR=WFuTjlm;t{)*}*V-IRBr`W4lEUKR zMj~G5UKXkaZgi0_ucIVhyx7mJGt$}p++G38<=}!T3jBj}BO{U6 zE#a*>3LlwEruh)ZJd!1hz2IsD&BJnY#$H775%|On0kCAVX{Bn#u6*Wk`D@GQBM8=c7WaPYbf4xV?bgsuJOunrM zH!-do3GCZuSB_{KH`c>+1+LLxt=Ogr^R5?jycNRSK;Zd>rjsz$=MrYZo2}LusPc(O zH3KW)krn?j=Sv$Cmo_dgZA>f`0+ZpPfhVw5$JO!sf-fSRYqDNIxDXyY#ktiig|ejM zXOPuJ2?TZ&vrdBn78h6t(Fi2o9>BVgK#6vp28AMA3NViGe3L^`f|8nb8cNE-jAMLD zcqAn#sadC?q~#`^l97j`mK8-H3m$ud4JYQpCpqs9?|i2D-jpvPzJ(Z*bn=srAaX=P z@)1bRppuV3&^RXP3J>WciF~+0@{vf+ppuV7&^RVB&pp`KjaUQ^jeDkv#2*78Lxe3W zcJW%qN*e&0XIXz{Q+<~?d^%P&d}J|3;#_opX9WxtA6eCa_N%Cz3biCwJ>ZrYSk++K zl#k))!7os!9lf+|8{^t_D=6@mlA$I3|D=*>m5a(JU09H_bgB3QOGZx`K5O#ClKG1kPMJ0lpM-H1S(Ugkfq-yK zK>K}F%$hN8+SI72&i|C&xPD=y!D29=hKRWj8)IoGB6*v}>q$)in5eI& z9%EH3SG=ql;91#>eiG@XnL*l5Y~!YY43@hQ3eL?)$8y;YJPzVwc$)`7rxPj_WkAlx z@p(Qdub_GT^wmQkFZk4FZ#?e0pk3JQ9rn(*J>Z7mTgLLd` z*4ciQsITVwV74ERgW6Mj95|h^zKozT8oX=*{vYc`M+_XEvk8q+AAR++=%=6St4~~C zy%OzyBz?92ta8M42OPD{xbsQA9n+WR8~Vro!Xd&@!g0bf;Y{Itp_$K({MU%SS$M0^ z=minKMf3y09l|GxxJIphko}qZ+vgSklIYh&?-Ttu(eI1?r|1YeF!LL|A<8{XG-oUF zIE~&A@mBBML-9u6jrf70hbn!E=<%W_i=H8xV++e$EP91#RL2|_uRk6i$0#DNO=47- zB}~-g_7vZoAEfUux>(4U9?BUjyhLdAxbsAF9A>)9h30&LW`84pjgaFZX^x-7dxZB2 zsiPp@oHt;d^9A~sivP9n72zL*=DZtH@nC%AIoIhX_(WeNh6k&WPVK-rS zp`CYso@k@KL3(rkfD^A=N6RuN1Blt`)8q-Xf&lh3Ov<8aoE)9in#$ zpBDZ~_@a=S8Rp+Fd|UXQ5br}KK3PcB4b!(2wiR0aZ=Ps751+anrnmF($B4c_Xf$Xk z@&1U@VA9+EYOV|9$L*xf{B}OYS1edqX;#9|?-t)D=qP&1o_VVfW6V>9k(34Y%h_}0XzeWj6q)Vxu3TFttztUa7M_YDrOJRB*0y>ZdL z;?NU^3dgQJ91^wBS$R18;HZ7STRdpr`N?YzC(n2bsRo-=D`Tlf?Yky5E^E!hE#9!8zh)Azr;eAK=<=|vx;zlBRK+Oo88TWG7l|IpBk2L0c8 z!)cdR`mgBQZ@hYOFI>_qMjCsQX`ZnAI?x@2zaQXaCORldGx31ou`RvKv+)m|=9dYf zqz8HOLn+^9R6qXN`Sl+l!uuV%UTl6npL;y&J-rde^b<*%%*>G#E(D2dQQ1vB_QCL3 zd_wZ)*ZWiL50P6mnOt}$Jfaf+n00?K_^8riLL^MpCDgm+KII{4lAAQwZ4GwvSHN_V zX(72P`7{KtOrDMZE0ULizdZRIq+OQ$EI3t8NT~2u;pLFD*5#;` zvKxYuZgO8nI1)Y!MC#QDhF%DnN&Vhc;50D9?hB!Z5s{X|I=yJZPP)sF8oB3~iXqaB zQ$*M7X>=~d@$szDFl2Ji=_hk?4&^j zj8l;Vg%Q)ncN%ISjj>6{?|hheCQc9TG&Iy~0wgVSL*(J^L{cj^s;hKv9G@1?Z--=@ z=GV{cGt{J^Ux2AioxO$d9Brq|H@DN}PqEYGO#_)R6N+mhO+K9}&6 z&m}w!pNaYKw9kXeDk?{mRn8o=Xx@~{S@Y*re5!ZYi9JzFLHBSpvwG;fipqtbXmg$O zTra(!R~g0LH<(%d#U$>X^KR9!yn;bq!>G4l7`EK$-oA5p6UrIAsQ1X;UTXAO139ER zo_EH19agq&4gIuNKHh8CuN%e<*M-utXThXOXJ*-)>6i#ijbv|-{l|`&G@}2wA(Ms| zj~omr9y@l_SpVA%i_7LX@QbGTQ?ukB_fdO?-%+)q^oFPbeDmZvu#zTQ$FY3>1 z9t555p`x5~X`Kz0fnmdp+XDfd%VnL7yA+IIxrL`VW-UF-Wjok%%MrGD5On^T>^M;d zP?ci@qo z&1l>jr0Zh|Ak)x218>8mcOhMG2IP3WbU%g<9>>#xcEPJm>^Pbr9H_SQA>{oUJnL*( z#6b6OXs0Oz6Jlffex65`8I;F;f!cv*ot0;4i$VU$*cXU(iMz1B06SKQZ6!a&e`22? zwt2ixq~fkV^UK-)SbdHmF@3!qrt9nwWSM#=#0kMEHQ!3$xvtMQDDsr_65UC3cj0+LqmxDYv7}M|3x#Dw z@TZHOEi`j-!KY(-UNuD1pMdPor1=I+G;f-~uA*~=y@W<7i1=dBLxrP-en*Ig;7e#ZdXMK$J5qP)guL-vc9}zw-d{X$F(DXm#H~kOzviN@#z9FPe zjpZH9ra(m*<68--B_o|9>>=zU$x0_sJ0*LK-lb_eqFrvqwySxL}6I>me zfYYgb`y5&W-hOFYle6#GwrN|lgKl!xwo@MuANp61&4u?DuG)6iHt7D(dbH-RRXMN* zvr#M`4nvIz9OV_UPs-oc%3{~|ZzaOhwmu+_Gm?-q`Bz$LZ9S+OnS zu=DnlZ~vlu)5G4|1Axx9C*LhB@xUc@hZC34^sw_*(c8bsf8yQ3v8}d+l>QFql*8V; z#c%(j$6V(d+b;Wlc>kWtsTtYZia!Xyvt?WQ3MX2)tsHZr-F}Ct`(N>|=-;jGf6yYH zFVhTRqv3XkfY{}84BP%ek$$R&v@!wUl)?m1gn#JU?WQy0B|?VxbFXM#5u{oMbuTvjS;*uc@F-sNbU)~)&1`Q zCqegrEm+vG=No_&nlfPr;OLTa8?r(7-x*=){>@+o-Tysc`MUq!2*DcgBp}T!6ME5v zq5Joc+dVg?`#*>jbiVHYJPspKkc}>7vci!d-7$^LT<{{s^+%kqfH&l7l82bckQ^L+ zRlgxGf(#z7VtET_Ov{TqpeM3$by4G+89R`A{YODU^IzN#*n}&I+`&xMq#IKV@iqU~ zl0Ebc{J#!wH2=KLc{_1O8_j<@8os&Z8O?utaOnOwH2*l%|AgkBy#fk%-jrhwE$%=o zPGEFh9Whe{5@f{^FvQM?oP9~Hu(KnV~sZY=(%!efFw!CZ5g5lv*@gH*z; z@MohNf2V# zv5H7cd$ht>os%UeaD=wFlPj8y!`65LJ_QDh1|R;bWi^Rs;qig^Ujlw@g5&rk^O^}> zfPdqf;y)KYu-^;M@jZq$mcY~95D)ik6u+6P!7+|0N5dmC;X?RSC!IEAd`A9QsnTMp z-tYX8bjA>3<;7E0$E_nAJ)-a_cyVU6Vj?)q@QMf=jd?l+izYq&fTXvtI(|dftBAtv0Yk_Q#t`yeRnCaqtlnAq?MJo8cd5I}402g^w=Q{S7)wZ< z(1(X%QH~IeHg0 zN?+-%3a!TA{fTTJpZ=Y6{(sp%f_GMX{~dr+WX==M6cMRc@T8o zf^8wnfSi>#2Xyc_GSGQ5z@t1quvmH5B5d;@=rl!POlO^qy9$h;yl6lkuM;be`Y@Y^ zGTK7krU1hR*CQ?{FBkH7oU9+!Ay(eq2s2MEJlzkGsXn%kh7Idy`?wP6>SOzO1nIi^ zRWSdoAKj1PgU8W3&@RWaeeipczcv#5Kie+EK(}<3<5{^7%;VWUcA&6!N01j_nV>C) z#J|h-@z+?Pwv~Lwr^)tl5LHgFeI)Fv;ps#~QZvQ*`Rqqb z*In3KSS%bSyh!+QZ6E8D?=In2h2Io@U${$XbkC^IZ$!T;{EP4%;s00LhtVOU{+!B7 z+k(*@gQj|qw9z4hens@_M9@ZujCd-lNFP=_FF?`_h=}KOVA7|H?jSl(c#d$e;;9Rv z?%D1`V)oa8oT=iQeRdGPK6#-0Ou@-;uskxJ7usaI0{;@G;@zLJr`}9~Pzw8w;tpV|*K-nUoCL z?(@<|eACY04;0Ng3Cu@*BJmQTwJFULy-3LWJ<}!bUsNsrSA|qLGTje_KNi~kUZ`Yb z{9lBB6TU5^vXSu_LaG``cNS8UaKbi-S@Z0&g!sCIqu3w{^83`=1`+jdVlf-U>9`Xg z+@3ykb;F%+pW=+E?NC@4+Ia|D4)wh6aJb!{PfIzR)C=5t}-UB4pWb3$sgjvl!cZGWp?@ z3z^2OSn?;`N0J_6bR^}AfVk#<1t{<9{PRCE+@6ApII`ko;BSPv2*N4Ge(FZdRQ*VJ zGDU^MJ&*!g`(DVCRD^JNrN2-978bGA%)U={D?zyZ+&vTr$HAP=y%_wIrI=68m?(UN zHc9t9lBs)`sc;>F{oxywVb(kO3*gfxi*U#IyPOm;=3aOwouS#t+VEkLA*WFbR&CW1 zN^={t#1q$N2j{FOA7%DAXSt`;oqryQPdLYM#R<+nZvZkdRh<*uEs5bU-F1gHqr`@7 zoT1IS;Q|Tl>3&{%KMaG7J0OOK3Wpuo&1eFn>*}F-$??%rn}y^e zh~3DqG8=d>bu#Cu4{BeHpm7=aXZkRvbLVF<#4Mn$%Fkkmc~bm5`5cywW2PK<)Ple? z=}ePala*T2zE4(6`jOOwOdWJV`VySjkkf5r<2jxaU(vo#4hF!k7|)cnS**Gyx7YB98EM&)(P9XhD;!|da!)0PIN z2A{~3V06WC>__a6A7f9BPxV~i7Q9mAI0T*W9vlm&&B>{pwzM)Qc&0z)8*rdKTEX)+ z%Nq(^fe*2NGtz)+1J88kDFc|8j&XDy;rXOL% zM)4W@7fM60ais_c%iZ1Badv{oa>=*lRv>KiAZYeHj4~i+(A3)xu0K*11A}%OzE9BYphC`3Z z+k!Cj zea$+yAKlaN!Q*%Y$AO<|=jK4$&P@=ueI7w)Amsg)0XbV1F>rY1TcV@EYym!>3@MND zS!Ph)c=S^~gjr|hS=wTde=_u8JXdiSh7Kus?b}xJQ+Tma#L_(Dap%=(Ngf}2YTS7+ zkq4dU&#H;BJZPd=KHJB4JOgp(ndN&ynyKTCbA_qHVjFR+p+2llJldBV7~bnn4c5)Q z&P~*Bix8^8v4eX`;341WR@fh?W2vvstgq7d7Y-7Z2*(Sj31|R`^AsX-A~HSM=9~4-3B| zH0K}P-PRXuBi|kmCw8$s_Slci!(`X;r(xDZ2hy{5)VSl%!_4#tt~xr9t5eg5IS0>k zGPW0n^51V#xbt0nk1j8a8IP^f^J|+#FRcxq-ztnbmARZn8HLFPS`fGutUm+Lfv}BS z9tahUi7u`K8I342goWA{AsAPOlrsY79_o-w_#aL(>JT$!+MQ=YK2ESBIG5e09iVBQ-$>Qi=@Fftg1-e{HkBtNNfJeu{ zg3hH3>OjtAOcXvcfb2q&{Ye@mK#XQ8PZQo)q8n#bz8jacx1Qx!t(2bCdK-2pPF48h4vv)YeztNmygSDyIV zk46FQhdKRdBqEy^nvgm-6W%$XcOWpjuJ$7e&RNF$QM*Uk22QTxKc2JOVU9RWSdoA05wmuw6C<+J)naJ&q;_qbXvp5C>Zy{YMy$ zTOa+$IP}w;nDlr%2UsR(+n>be`j1bd|45u3bYJpr#PB40I# zxahV z=$@NfUp>b}e}Jl^=cqo=vg$iEI~zo6Qth0WoVLgxPw z{=A;Nl)|)yc>OOk8B_3>TQVI3?IQ2;<(e8bUVD0&JbsbG`xo-CXS2%k+hOeJeWAb8XjL;l7)Q?&rRdJ zoUrDKn2iLJjyG|n!EHt9$DTNH6m5z9mJSZ)lT97TH^;oLkjS%w*&g1zh4DpTe0ZA- zA9dd8j4rd{ymv=+&SVq+J>0o9!WC#=2HVDFaM&F9YRf2OG%g+gQFwmIg~)T8&M&!O zS>b!R?{&^JpQrEXr-y+t|QW{v35;~v;Bq&zVb6Q=v~4(cdGVlVe*_0C6M z>_29M)pG7ir{=&*A%Zyd%M6@Eu zoGj#bOLG`3$OMk?9hXnFzJvpxb!G_qM0ygQ)6eIL*!IMLW?V=7oz%(#YlS$^6k3dEHn94t4C2mf{8v0U=)aU|+VUVywP;;pk~ z%?BeWk9r9FjJ#v%N#2D#rnAn_REI2+f)p$eARXZBMxzCx}(TtA%TXUliUh{F?9~;kSj4 z3Lh6fE96*5{lQDZgG9XGysP+si4LP9vL20yh|d(Z5r3@ci$s@+UMd=5OgZdHEH7Qi zYm9W3u#=E)p5&W$0nQdZPq)e)s&SamSzUp#i9l9wg(CQ!?an=TLOO!R?zGrj7jS{*@&c)@C`E zhJMV|F9r8ut;>(F`o--9u2#P!wbSYs9Mk1&e;yq487uJb_Qv0zz)W=Uc^_vXDn8j` zE~q1{eVIqOcI^vifq0jaW7ocHClN`ZHYGmqgLUz^QQ&dbzC6gxZsZ9-!5!f_p4}h-F{DXBd5>e%07P~~jjc^T~zs4o?IR=Z^arhF< zwJ&B`2k*R8X&3@)Uw*=511Wj~{AYXZi@AC+`-4~rkJ%r*km@*1uHXfQEoxT4g{nzl z5XIfA#HPiV;zSK=9HB3~=Tye$bF>755n*hql%K^AlYqj?7X*xB8gjAGkIy*re2zjJ zDGbt=;p~1^)Dw36G8_M&T=m3xZp&P6aX+kU>6jT<)xsGac-=G`z{lrv@U2;O@wX2- z;<}ZizRt!E<8vK`Y1H8U`hle_b+j2rQDB_dau%Ect~QE)Z}vpg6|o1c|JhY793_vo zZwtquL5(t2hF5v3L)T#tI$>Rfy^=oHRiH_YLu(rMNpuy3l0o3zi>@nt@Lh2x?qPV8 zH1CQ`Lr*$US5XOGeb%&;LtY^&e>`2qA*6W$GOe@6I~5EYX53SF0KC^G3dEHn96XM# zcwyfR-tlx5bLy$97>#EFJ{C~kv2+!jBNBXkuywx%`GWN;4amc*Rji%)?ql;H=xl<# z$pMB9ZbV#AUOD91^M*r@$=iZ3^W?(Q{Szm&K5JS=)KgdSL!_&ZuA&y{*w?IMzoL5@ zK6o5U1MR}6E2iUdCF&}uBdL$B;;$I6>NBUKH~MJ~%CXM2v!yKt`Ts6mML%1ZIrpBVvnk;h(GPbbrp8VuX77^9Ja;DnA5>WYQFRL z7jir!&1ZMwc;Pgmc}E9-iRdeZHwxDaKPzim%y~%C8xoMOm()F&_5)53eVLGNoQ$s! zCeHoXApUJa_Usd#%VD}s;+mDC=`gzY?pY`*cGzi)oxSZ! z7OJoO@5M3zoyN`hcR85yW|-*WI*o~l!d(IFm9Um&IU}IYN?6NM0cjz-mc{hzle(6L znsiJc;oxp{8XXX}Ygx=7Zr8H#tv`;V+2;lK(b9zcb!Zo;_>WgQW?M>1qEG@{>&*+{ymFg&T~&czwO9&`I+AQ9Ir+6 zf_7bcbQ$h%{(GclG5%&BF=Yy-bsk|A%(1m7<~U+{g3srL9A$^zSPR9bPJC4JgeWtW z1bBj5gT$ZaK3^8&w(>IF)}gj;I>wx!4u!*;bsU05f8sSUdLsIKu7_>b*gN$n(Vqlw z5BB|)H=E#F*PrmtVBf=;hMqLvH~6$+-AV+m2{3H12>hVDHzBVOk<>fz8QIDki?Gdu zpp%Sy+lvgy*|@2oZJ1H7AYDd)VS}ZJ3zpk8!*Olt+m!x+S(SYZNXY=TWz(qYN=Wfts&a>|NWl*&dnygqS*d_ zRp)bOzjMxkaM$fn_LEio?}IvY zfyc-A4Pl`&e$hbt$r;#bL+mHZAlFH{3A`Q*+YzJn(j4dE>Y4qDyKeRECtIPfA@-B$ zsN9CwPaZ@&E#Ltuxa;OA;?JQkOA>)6^eliM&d}#Ygy*V+i%dhjq^*q+a zM`1tdM?JX41BIp+^k~uczaR88(G|j_!vAableTDx4Ve>DK{=ck1ML~SpNP3a-fN_j z!uG^1A5V!W!YfgnV`! ziG77bi|WjkIjDW55G$rK9Da;QdDwB)v9J8`jaHb=(lO^-Z+e*Bk_FtB6V930c91zU zoCAY7Gd2h2{WrJOnKM(ZIWrZQSHn3oeId(vGn_BOc{7KeGsEE`)?dA3TTqbzlSdKA zAU$V>b5=0Y!!B?vgJy{MP;An3X3l|hyd5^_IWtGIL_BLSd5Mg>DV)fvBE+*eZ6y92 zHkvc@c_!VQnJtv@6Auv*@$n(FhPDhY<&d5;!||W~dFeSbRoqWx&dmAW2ZJGD!$HbP zviT;s*sE_OM=sf%8KY=B%J~5^r?7d3b7rQpSbENkD9xFf_Ic!OMND+Z#-C2n2N4f2 zXNE?qPt2SdJbPh_SYJ%6LaaY$hD~K2V#DXmxDwG>E$o^)A#zW|ZitvOQ(QY|hMm&s zk^oqsorIE6O_Z4$@`?c#4rEWMQl5h-JslVLlQbwL9E*vQ{%8lK{K4kTtQ~aF`7(zz zj)VtQJ8GrQl$x|f;8UB4*-XM=C(*eywbNVDbw%q*`jv}gZ4WXi<%60~@H$s_ILZ-C zqp^eHp<3bqb7Y*wjc4$&nJ;7A&k>D5VRd{u2E}#f=*%n}i4CPnItYB1X5ix{`X6>X z-naQ^r0sz+jHK(^Q1~j*koht@psykGWlqQY65p#`aOXQ643}o!(Xe@JcS4c8a-^f@ zk-!spJ$O71^4)pVx1qeyKpV;?=;K43`VKV)<)6?;ITzfquLdJ}e0N9m9m*?cqr0%*M%7(HS|63X|U*_8lw4rpuP8(uFnGU(6I|(4K2LrEVv|hGF>ZLjI z+;yvOLs!N~PObx|Tx5|B?-*3Wt118%p>( zRCf#tyZky2bbK!wdXB_~Vt)y7ZA+*JI9NDb$d`BWKb;T$Y-iN~DfT{k%G{E!c2FYU->V)$wh2&3b9pRkMCP zYg~2ywWF%@zjjT{-PJ#;_Nvy^-2T=%q~WC7wSWKZWO zxthF*B)_@Uy1hBS9&mKVuA-R`Bag{0Y1tAd%+;tl%@?s9+fq z>=ON%*HWH)e3gkmAyI=wo)fTwoUE*ZLy;JP=wI--E0{#C73_^fo)fTwDJ$5N=g5a! z6$>u5z0Giiu3#aTX@%~zLXd3gpVZ{2MnRL~n~cwF>W}gBaeZSN4AcazvO$A{^03Ma zzqylDfUl*T(&*HTj=4jQN;cvGE(v}4CxiL!Q$I%JM86l*)Nke&b6^qL5K6dJTyQYC zwJY4lKsG+X?|BrZCpJ3UcF-il>vKh zkuC(JLk?1yAw@`9auT5fB4$4&wlL8tByzVffxno{$=|}nTtwd+M_6XbNrWpA18?QZ zElhBqzFEeR2tyKp(LgN4r!$g-u+)NRDf%bUA&HdljbW)!C%vfY&=M&Ofg)Uk$g?M2 zXXy>2h&uaGNLt9n_83H*J;55IcQ%2V1MlKhTbSSueeZ0-Lc~mH&g^~M7N)BZu~Wio z#K2p$Y6}zL@r^~wLK53vh%wF_1M*%%x&mOKEw-hIIJ=M$R=M3)_B=Ii7i`00OjipF z_Cbtc`Z+OFTv0&`5BnUXEbuy(BStPoH;|zeJ7Eh2*oLg};#il`zcBS z)6OF;M~oa6S@mjzC|k~1!vI%E3u8Pg{f74%E?D(qRbp!X#3yU&|HZ$|eSQ>M7psqX3d`WQLFXBx$t^%vx$P!<}aKvdD=x|XJ0fO-?54vz(|XJe^KRhn9RcO zT+u#u5$Yn8#(Msl{urJg#hin2wO-pBg$S^Iyno>y2e z_o&Yje3WXQzQ9hqDLB2kDLR;acj1ghi|1D2>Wm&czLYo0{S7oe?UmaW%yVfsh zQizNXViT_Y&Q{ogd}w=S;1V(hf z6S2b=A;@N3d_-3UNw2>B(dAu;yr{l@$A$J=>dQfN`c@D6E4%{%d!E$HqX6oSxUd8O|L{+UJopeY`&0XQUZ<`@cUZP5THhn27`679+7t4dhd0$c3k%yhaCGFj(cLe z=Nd-TN~A90u|(KzXeWt5sGIn`g{KHhgel=z;Y8sK;auS&;blU5eaHSbh`vpDr|=%( zH-(P~IZ2Gixl{O_FdG#?em)VMU2|beA{tz4<#!U@U36d3{Y9rlpDEe~6QR5<-3$FT zYy&h+UfdtY=}^C|g#>!FXd0!MPlFxvZxX##^qr#3!^F$Li z5?2W?7p@cX z9%ep`qr@)>zbgE?@LR&~2!AO2iIDv=%hL}>d{OwaaIf%P;lG42wWA!Ntp$ei$A~^o zNP8^x76?xkenwaO z$fc)9(;`g#wvZ-a(mxZ@CQSMTA&tVMcMI)40{y<|xZ0Ol?7^qinDWO9X*MR!ucQ%a zHzt+{X)7i@PB=+eE}SKtD_kL5CA>;VQ!w@1D%>KZNtyfygg+4eSV+4v^X>it(vnR2 zZ$cWBN&ibob290s!lbahkalF|_Z8BLOnRtrv~awTwq)kd7A_Dj7ShDb{HuiF)0L^ncCz^P+nl*jIIOzkWqY3x^-K%l9>e z{d`rc@0+~qhJ=4Z`yJk%M5ezdkrCUIi2o=xp*sH5`0DuP3Dt@IrmQ+~ z&+|3MzW?1lexowvXQD&~O2kp(m7ODZZBG=Jm6Vm1`J0=YU#f6l?986~V&^_nbM)K( zscoxcXTGyDCco5$yq0!IasNi3e=jPfWymqM+rTen{kWf?y)Hnv>jiEObrULyWpSQ* za3VMEdw}DS5nK$7fty3k_jS0a_OR*`S$xvfx~Q(E;B#b!-vfM+$&yi2$VW@ObSewS zvt9!q-l}ZwH4$G(Djw$_8c^qhnb8mF41Eu5ve&s7^^ zgr2J~oxPK)+Zi98tI3d;=ZZ#02EWl!+zxmhTRt5c@s-FgBe|R;duo3m$@@tD8~Xed z_xlUP+=uM##EX2s z?O32nw#XPNg&3;gOO}Nsw%k?3r$JU&VsWHI+U?RF*`boNk+MM6VM-k05O^1c3eO4E zh05yfg9_>$D9KQ2k}Ft_1TS2+x8Tx^G0ywn;;tiDE5(XRvvFj56;9f<6|m|{^WLpQ zgb&dvVC9DQYTU8x@}>zSRz?VW*ZM^HLEK#bkI)YiY(||5#WB?r?2D3mlnX+(K_^XgvRrpeL^3H4ZM!JKMv~oh%ONj zE+CM$-J9)Pu8+toQE0_aOVPrAfGosjY2{T-ivSJPE6(B3wIN8;~@ zK6l*HsWhUSyW@NIe7$UvcKhYu1O8`m;ZYbf2Sbi_c>HBd+pk9;?aEO0MEsY0g9!zf zR}R{xnU#wJdhh`IorJvTe&fwOZ=3d;KpxM7Sl{2V4S!yf;Je`VRo~z7I8GoRLWlEr zya;`ibHVAm6pZNcJrmK#*En~48?ONG1_Nv{)b5N;NJS;)3dx$g>pD11V=LumG0$h{_tQ; z*hhE@5sklC`9npI6n(a6TjmRT%q|Q0iFBIBeb?~iy0k07M zYTle+eb%VhbkJs;L?-q)79sQotV!R+R}8g4i5 zkLM~veY<%8t9kb3RI?pfsV1qTQ^QhcRmV?-&HUOQ)wJB}_a6xA9azM#4vs5piMblB zb_cnQc5E!m-{+s%bf16fpN|XnW(Bco|J11i-`wKJNveHtmd% zV{ErER&aa~=)ljU+cWSJG%E$MjQ5}102$N-t(k5M&EUr(H#CE9y99)O81bKR$8z><>+DhN% zSFmsf%$+bwGs!jvm4s1wu#VY|8*t)q}WQUCKfOuh=;i7Ex2e%*GVS%vK7V=rQ$h)+Do~!dno@833 z&n7$*?uqRv46Mj#h|<$>d&RsS+5h=vl{?w{_ z7^`mh-zqweo!yoT?4C-Sv|N*UMaGr!tAe#LzSw_wdv4$V_2KKsqdrgrX6IlX6>$>@ zF{Rr8Dd+53_2rnya3r?eiJ=PHx(7@ND5skl>kwavFkJF9@cGW^!Z7?%*@nzxz`)-a zdtkwg;|)i2Wsvk{;{^Y}go4YP4BDlcH3%m@)Kx|#?_8v#`^|0UdF7Dfez`xM2a#Uu zsJ;z2s3dqUxV$-FMD@+Z8wCGzQ6Jw>oW9GDc4d(C?uS0gx#03H0VAq!Wkg>t@|?aK zkalIL;|I`38;%Pu`8hD6`qn`o&yU9!wdL}ifn^F289L*?@T)5pfAB#P%P;mPqMo!OrAC=J%TQ1iHKG7)yI(-qAC8PY0!j{WxRU2Hbgq;7z*mc$`PF;aD zUK<)Rb{&_?>S_Y8t}U0ZGxdh9!+4enxesE;?Lv9jG0pA<-eBm@9 z8!Gurg_jE1f04gIxLNpR;e$f6r$O$AqMs1%5IQ^VtDV0xuD#T^r_!Xu{B1&OC!n1@m4+SW|4~TG4(Ydq zIp~~8+ptt%2hm-G)<0y`wkK4Z$-DN}UwYW@9B5oHmp-bqo^Q{Cj0?tMHa0A{0qgnR zjb{x)9s4G1o4HuW#_zS`f>d+ZH#1Uqr=EMmJLkqX{Gm6!;m`T?8?m9!z7d;q;~T*_ zH@y)ozmK`gi{4DlseJR5IVZn4X!+tdUtR8>u?Dh_Lv9UZ9*0E6p8Sl=J^7jOJ^Arp z!#bMVJXzMJtZms*Hd^?;*Zt*t5SL=zU;orUA@vR|qkhF8vqjor#{KJnes64OajYLO zR+zqZjL|&_Sy;n{Mn4P?wvIBM(HnWeLbCdu#r$}d^{9!AACs5Jx*1SADtI-hfR`>P zwT?KRW$nXHykOGt3kmT!AFLSv+aH1%f1-lx{9C}vjNgrImVX~uJ{xj41&Zh=F6Z`4 zcEd?TEF%JP7|AIluO>O1j=7Nq zQ@F%RWWkh(S(D46SV&+?vmy4CLME3W!jMPc)5Ml8VIn-3u}E2< zMr-umVnb@e;=*T!xuLmHJnqp#du+uUB9@sI#T)8)wYqr}VMqc_LBu|W5yO2ii6d#D z6Sk)#B7Znh`3cL!rVz0d5&0vC%Fjj8!hwv6>s_WWO52-=cOu$-1C5IR8;fd$3xQzk z)&fb-#tc{0!})%&m59S8cGxF?wlnjI^!Gtb~WQHHN41ftJn)*X#HM zE}*gh$Wd?(y=aEBG=^&~HpF~by8`o(eW?3mxgZ9+sDs%N*&~%TX}%`oiujemRWZKK z9)TT^7wpq@ky(WdR+qqzhQdjV6%qwrqy|Hv_*`94T}JTCrcbY+nA&PIQG1rrJ`uN<^XGwTnK>tua1soK0r zNJsZO9Yzw)|KxtTKeylckupennK-B<6AEr$7lMxJdk|)peDJ7`e=VH8)kwQCNO~Qh zk8&=!Jibpw^*tWZ$9u);+laI)Lmhpfk8k8IxFoMpRNphu$MfXz(LUw$ZAF@83K1E; zhzrg6ur4r<@oPdS_YRaTa6-zX+=GZ{Qxz_2CJy32w#4l!GQzlOt)nuy&Wh-JB|xHHU?tk^gMn;z9F{6O=zcWOhdSF`XVe#M)@CwEfKqo z1Xn8|>%U=39nmAb}6cGU=GFF^ZZyQkfX*Oo|K z#AAv0n|2ZrLhPf+?=7@9YS1O32MdP_&k;@$&Jr#Wt`M#jeolCk@C(8_gkKRpDs* zE)#8bNYG>Ui4O>vnSWLBX3v!Q^IG2&k0`>n)M0$d0TX~kOma)-;K9yE}GNd$+!Fd z5O%_D($k#vn^$lBfLXI=R%*5Do<%)-_UTpByXYWx!altlzSeayAC`DE;d>9)DRpaI zUvppVhS=sdyH^EwB#zqs?;zM1zoGYz*Y6K*8&-N0EQf1SYf~FioleNwKE67CMY5z# zN!yZ+CI0CX%Wp3KUHOT&w)Nk42Aj)M?fjvsl2l8qYmIfTt6IV)*l0(5v)ApM9m7gT zRmYF_Pc5m5@4@QU$G^KXN2>^U-Covns?V#s~G+PiQ5uH0Pa{j0?}$eo%Rle%)Zm&!u! zYb`RspIS~Gka+7K13q7xcx*yy+ki7c-H7zW)WduH#9iet+8NNI`54Y3V-wGU=dk(J zAM8nHeQ{4R_mB}cvoFdp1N_zg(@1Ax;Z4|EPk=~lr|**pPQ@m%%!@tk z=OX20`xj#Ck7L@av@OUSu2SNUZwb0P_&gZcIoTC{ndIXn&tmRNB#)x-L_W~?kZClX zx#y6)nB;2ap381C6RF(U^Lk=Y1Rly9kd0^0>m?G&-bzBKNXcs;)P&Cjzno>7@K#fj zZ;oNI5&t-Z$*;sP{*--X3X#EoET6A%OdZfTd!&O+54!aAK~}rYscXD#RCl%OT#yMY zsEr}2w)k}|Y3J_DzBorNbv?!(pUGvh@l@ra*mjm^K|nX;)Ot-XT;+gQH}EdmF0l~0 z0ASiB@bwCYU_vQk;4QA$!URW$fKQlb$x#Gr|1=OYu|DL}$8`)MjH$c?T`W0j7=Zh( zXF(44Jesf?k#^nDTbN=|7?BAq7G{8-4q?eL1U7u^jmH)q!bEGV? ztTffJ|3+~_z9q*Ist~c7LNSpCgvu-?nwJE8B9DxGuq_;eZ4wc7Y(jraP9X3F6H7+; zwq!&(2rR8o%%v5Wo`Z-3AXFfl>6r=c4t&CTL>x_7?b(cFjq<%L@RqOI!UT`Vx6e#K zI6N&r2cdz$ips3XIcf`;>{(iXIkH18%s{I; z))8PP>*Bb20xNKa9i#+0EVRNlW+~njVc^NQz)oT?A}jQKMAqd@#At}hKZ(4U*M{3q zz_{A>uP;`m=5U1u5(BCGh|IS(sK=Olw=$v*A6wu5uf4|)`2CNozQ z_Gr`QgkWhBnMib`LA=B2ja}NOFyz+6zO-s+Wp_^x~#BH#ExI_}y^a z?%~#Ka249HRT~ar(RYe4;^yN&)YmS6U7h_GyH5K+I70Uz3p~(7&I`GqPj75N^zH>b z{3zeKvnwWBnfd(d@Sj<|nk#dM$9;fr8PWmtKlKqq{>P8n?b}ECQFfyTT-Slm#}79S z*xd#H^A>#m2jNqPZ)*&E$&H5a5f<7QDTlt+LVY>rF?2*sARbPx8)WM5H~P4956v>k z0W92&LLA5Ag4=H~7&84>)Tu%i}+=sJ>+_!}mk#%RzMd z)*$W5AnCmXeT7UYxV$RRQGIKnuNXY)<2~c_-GsC&gQV9K2hIPHF1Y0NU_|w8hd!Pk z_3>TS>AM|imT|}QA`0D6@47Mn-g>z3;d2XPa%QsyJw-Hq zdd#m7%^Aj|ZA>uqacT|e>y*Dq^cO^bS@c6f8^a0t7nT1vA%_#PK78C%#70EO)v?XO z`oO^BW(zhOu8?huG;V7{`#T1@yXc<6enPvh$R8kjkkGC#_~S&Iu?+NN(KCf}go}hr zg_jCf3$GS_R%q8B`ZkHS>ks;CqOBc(X8*_Y*(Q8k_@vO;{$CRP7vbx|-NJW;?+Ih9 zXXwooS~~&VR5btcGQX9OW;W72gnfkO(*eIkwDSQB7d={7f6VX<@n;KZx1)ZJqa>~o zt`(Y(2mBjEZx(J9-Xo-?lI3YJC4N`wh^8rw6)VAf3oNj;XvUS;RGQqmDE2^$hDD3FBj5CN%}hBjl!FSG)gl6Uf~ag zKN0>}=+=0){xK`;n^}&5=q%Sx33T@v`*ZS>!uG-f)sy8P*f(OUD<94`(yv#q zen|_5Ut75>e7M!|jd-0gf;t$9k<|Tu_vjukufvWJrC3=xBc8e-_252l{e$~rRYPhr z_YJPetbSrwV(`G~#JUIf#lg?4^3QNNTv?g9TxEG+b?&;CFlzd#+^J>dHfB1pV@N62 zSoTjXg9m}@E5EC?B)G?JJHq|VF#zlubSU;Vk_#NNC_*516V?YpuDVXrH(SL9|^ z_@^@;-j8>k1ouuU?S19%Z13e|Q*G~0>`1kI!XZBEA633>Jy6G9QKf5`Gm}TEL z84)Dh4n}hPdoCYLg^0hQlHJ(&Td3r6bmv*akkKM+k16FkOx z&Kov;_-F{s-QPzOp2L`OWQK<^hIsV}aCkpce+n}QZWnde3<-BJ ziEz5fo<$geXaoJrk)T!$^kU zO5ddseX)qX%!odos0DU({Skd{B7s)}j+V?*ImL==eEY9yx|F|un4rVt^R zSu02mwL&9-^#lPe!_AWb!@^zIK7fdMB7_}?tPLWsd(@?M8|beiMvn4!kko+E*jnJF z*o27Psm>O7?YEG_@+eE-HL5EBh6UzQD>M=$s7j?KlfvdH#6KWLcD*glN>}6KU{Nw6 zMU@XDV*jdHswHO|A`XzihErF-H6?Jhbb0h>Scdz;eh4bA3qrw2ab1OI@t0BNHN@QX zQt8Ykhqo8F2iPUsTnv$&h70T|Twuds13w*+joSrYp!J9w5qVi|L1eAFaG*S13Kv*^ zY$^{TvYEI*KAQ*mtj$Lew;{T~JeG^*u~uAgb+8MJw;WR#Jue$+_d%SH|I_nuLc5V$ z=Y2o7BN{;3?HIs9QtPC&MjKt3k|y%kOZ#We%*2$OAn)a1*3h73GMM#N&}CwAm-bU*F|7Vm>pnb~+t5}E zuXP|E)}v>qDR-4~R7DqsPrJKp%8$)DarJ}sX&U}rTrCr1(CZW6LOe3ZA+Cfj_;a^4*b$RE5itcyav7T29 zIqo-s$nzl5Y~sow>8;N3yd)C}F7G1HQGHLfZkT`YcIbP~DFZrvRrT~e4}Gjd9v|-& zcYHS??aCnOEr;!$wtg2}@_I0$$CsN7&yV_=AUb_~t6`Z!M1}y?4B9YVU>@VWLMOKY zHbmBy3r_AKFmO3596y%dF#lkG$T{6C%j0AC31aj-nkQ@PnKm(Z9!-&sG&gT9^!)}r z7kGRO#K`G+@uS0fZUKHXMCwCP+hi2Z(%d?2m4lzUKe-x2*I(dNfN{?nqLBcgA5Npj{-gnnB2sHaA9G((fl#!bon z=Mk|#4k#zmu+4m$$(i3(wE1m7pCY=Y*IN9p!jqMcW@z=r{)_d-X9kgd88InrFYGGpA?zo#`v&p@MGp~<5{?tr z_rJ~(f39$maH+6LxJLL{;RfL*;b!5Ngm$0dctP-IDhK~$#Kp! zkE6c7)%^M3e@*#zpMri^wB4tme=7PHLc3qVr%Qx-Ulsmc==`kjiMIO{a#?JzKpPJL zboVQrKjhb6BcDDN^7{(U5DpNYDI6(0OL(r({8%V|foOhHi24=@>8Bxmm5}c+q^}p= zBD_s#_b>7v5dFAtyO5q8mjAu*4dEVPweWo*9X^ylPDqar>F&Zagad?h0Wp7qaF%ec zaFKASu>QAoH;cbjc(?E#A^kzrzfDNr59wbC=^!Hgim+PvzA!*X!u%{DokgTi5_S_7 z3h6Rp{s_*>G&aCDWrFZ^i{%}gR zNy2jBbYX?i-dk{7%S5jfRteV#*9+}E2J)LkyZ&~o=sSe<``d@be^j_#_>`~#;|uI7 z6zTB=g$G`vt?vgIUoaT|K@jSUFTm)6tfwA0DU%}%20cT6fA1Z~q-Lbzsg3)*tsD3G z>o@KTDmG%2K@R3KV$R{doV{5&*?Y6HC)Zq4GjdmU=g$?NSabEhti4%T^!pFpm32X4 zZ&qR?MjH&;m7SG%dsSl4u0)o9TB!dX4z;2H%D?1cf?6FF*iqYG)p8ho@I$d z*4=>GK?k=|up(T9KyElO@^t77Y+@uv8vL9he&S6+B0iZAkN2^C#K%K0 z<0i21)s0)h%8b*Rp5^}&ET50*a1a&IPh13HfABw$P9pLq$7lhT`W(qiNDgH#Uo#Rf zQ^T3O1NtD9J(Rh_Nmh^?MO7p20@)0y92;$5-oej?Bt{#IvJa^CBX5jmZ^5jxW-=wQ>=e zZ<2`Gi%XaYyAKnH>U z^h}xw?ysJIoi`;)-3GWlOcIVW!EpqZ$>5a96Vnbs2w+ki%Z(w-v*ZNALPU77S4O^0 zJ%NWG9_ARrTZs5Z2!T!Bq?rJdd_s7bW5{%&3JJKu2|U!$d2cBzHa4zeVFn~D@G%-5 z=p@1%M9eQGga^9V-@>D-LX^v$$u)@B7lF0oKKQ}Ch37Ge@FpUZ5yJC;GB7acDy@vk z1R|6Xcv?;wN?CA6mt4Kw>MRE5J0bSb7>I2_B!DM#(hy zoYnx^g1dAa89*Ukkr=FPJXE%v7}}U?K}cU3mI^C$p2=4Fk#Z;zhKSx+BtLe5{2-Fg z+ulMSY)?mwOf#j*0z`9UhhIE_)0P|xLy$0UKLIc-oPupBV#Jrv0%U_lP+4D}Oo4JR zElk8#xxs;RCqW|OsHeJ7h&a|*Z2@wq3W5=h5dq{`xE@af^+9F2tcxEmzuLB~hwG44E zB3~+9U><{mA|6ob1qYp21Z+>z7SbCqQ2EX@`!TqcH_Y87o21^ppBDWWpkZd_| zWZ#oI!#8aUL>}JtY?B=8xspHqy3FkP^A;t$&zwG`a!U6_Gp1FFo>|d-+WdKy3#Ux0 zJZ=8Wncn{X;={V`**y0D1kGWlq<**$&P4qFeZ2vvOd2qJ?2xhHcJkO6m5VDTPbex_ zwoLr8v7;srn>}^X*!hbWPMa}l(0~En{)WK9~TL=UH|3yRi*!u6xL5)6Y+=Fre4kq%X^hSZ; zybKpy-Wg!Pgq{wQn&UADxnsbA>BC;|6Tp#(t_+giBY4xfp9uw*HwCmyGwVVe&>VMA zk-YPej_&sk?63-Q+%NaXBE$;BsJ>r=nFP-Tmp2!TsJ`~NK>6TNUk;+vcRA9o43Zw# zUc8$L1(&x9bW~pv^z81r)k0!f;92?xXtJjwoqfg;K*}&Yf#}kt`$I0; zrg?k}KSqq6M>m{@tLH=cm@A;~SX&W*gySs zX9@Y=gY<0SJmCuAYT?zw&kHvTzbt$}=={q+6TMUTobZprSA>5P{!5sFx}p6#TWJ0+ zH2R}R<2X+sf^I9in`rZMA^%j-#mXNldZg&HMRN%q>YF8csqjjn`LD2_J4Anli2mRK zBFa4~{trYyDS9Una=#P*W%2(i+Wb_|yH9c$ooV_wJBWJCFNJ(t2n~A7pA3E>^T9WN zGHCNlfgVUco2&C8VvH<&F`y6p!U3u!bb{hF{w_%C4w zIu7P%3u#X$-BCz`I_Xn{!-S)Rd{>WUHQaCM`X#(-nBJtYy|9z8o3K#G_a+`kv9L@y zSU5~LN;pnfE}SlO{nT916~ankm2i!4t#F-?7C0V1%62rlC2z~mt6OdzS+jcI6MMYuO{r&6i5s4;j(g8nd&SRJCz4g~W%_I0 z%N+Pri;RuWSLYVTH>`dyvmH2o&JEAEXtXhBbMA(pwTR!^`1-P%?6-0^Z%3H{HQ9Rx z)@1JnXRm+8_Gg0W=`nQzbTGslOX1fDF zcSn=Wo>Lt^lY1RlgGG5ib0(;Fb{^x_lI=7P#~ojfV}AeU)Q;58t2=GYy&11oDy-|eZNL))vOix|llyM|hHsQMf6Py{NyWBgZhE5H%g?IGeJ8Oc|7PI3{^w&` zJd_()le_z2tTEd;wR*Q#O1XGGO26aZoY?a8fGd#GHWddqk^KFD639OaPNS6H?+Mfd zYax42es+BQ7kB2}`~uG5h3dll8ijSSr3LEZN}T1W2V713twopA<-5JID~ewpfLeK% z>)durg?00KZQVR}68j}<2XUYOhy3B7{E%a8x8ciXtxt6oB;deIfd@zGyJ*C4q+Udc zR^0SGml^R4I^<&Z2yn3i@R+(A~jLG{wdr$ajJ}N%E!3Pu+?nUkegd*!Y7ed<M!?kDJX`xiI-2a8E-Z0*@iybs)P-{;ouZS37pAD+e8wP$hei{OUGzbEy#r4Z2uhq-zt}!UFsH{ zC6i}-G(HL!E;(B#+f_#EboN3RpxQ5l3P8nv%g&ZzZ=(<+-a@j58EX`QhZOTx#);=3 z2Hu8Ew9r`?jP3b|XqSXph>%SXD~vssu*{O<2=^gE!+mu$ECdt9a*10*frnQyLFvem zF~16tp6QD*F`DU6BwdvhSz;oUCc<J*zUqt58RPnQRZoMg%sjTa_8nfqhtLg)KUJ1nYh+ z#pV$WQ96L|2U^$nf7+j!elxapeLti_bGzrC);-8e1`CsIg2n}HgZY>zThP{K&Yn^L z_vY>03ww9(QP{0bkM0BD_UzTFLyr!@(t_^2f{O}*W0F03_UsW%EeL+xU(6P1{87H5HS-U}HvUShyZMyPPdX>rG=p?qC`!HhxysC?n9eV{A zPlSqgL1jUZQ!t}zkTdbDp521-p+Sda*As*DCk7pp*yH$u;IH0ob9#*I+U~?)=|rpq z%mVF`wjMCtrFB;UUc{Gf#Ad;f7ga8tJq;pr zXHQu)d)@_L&RjgtoT*W#>fxNM`>pGH;aFN|QPXMvWS!bMh%fbnF6)bv3cv8^ZUbEj zUXu^wOf^^h0bHtw@EE&2!)0tI^>JVOmtE}v*Z$?h>%;k7T@`-1_OG64?&;PMbOI6o zN-Pu!9XPpeU@*-$eFn;LIH?Qn!O0hw2;1w1M`h>m*=nLLuNag};>IsOI@EUzD41&O zLCoVCh3Lv4>5a#ZzQ}}v%bN~W?gtRMz zr1uUAWgVcNuSZ@~-z@0k`SJMpZ_Met9ck(-L}Yj${*3kY^fCWl#HidlC}CZ>z&yr> z5YeV89RHt?JCNV?XOeev{a}~t=LjH=kAbh|(etQ?)C;|U?mU_z?bR&xZf4GnbkS_ z_FBKI>z3=T{p+|qJN7q6;(I-v_@DB2z~DfGjP*Uj#EjJn`-Be)zbkx9_=NE1!e@lf3I8bkv+y0^!F;91u>Nrz#|hgAPZD+$a_kA^ z`U+1KmI_nC;lk0viNZ-jnqjGDzHq51N}|W-xWS4 z{HgFs;qQfi6uu$cBmB3}{>npdQ?@(c(L!2=N%s&spQz0t2fsx8fx;2OF~akOQ-!mI z7YUaLmkTcwULmaSJKZGyX5rn!dxYN`iU<>v`6 z7rHsD_2;bGb1tj4f5Yu;jN9h(GNO^j#L>-3eho z-(_O+5BKE7ChywVXmZW!>f#+EYu3KwVV&b(Pa<}HYICajU)OpgcO5lk^J`kX=fCTpKBOjN-+-Eoz1e&7vV*;OK^|r-9{<45nv9ws?aCf7 zs3zmx(&|KiuCSbg+%q0H{sFF|{L@{*Agsq6E3M95`4na`KG|qmDzSND*|}xScL%Y? zJdWx@tl;dQ()>OD?XsGLt*P7&oV}dYm{&2#du%kXznxaxXW#386&*n_IEBWn-I!2% zUL$WmIJ_=Ee#|bxNyCwZJC6MV+;P`2qct~fUgPD+h;3mnk=>8rfN-=QVQF5)O$EOnBWkus}Rcw*jbiU}lU*8Y?K@ z1<07f^cw$ufb+q1f{b5=Vz{ZeLGTlIkU5ZUwIt|lJec8h+r{nZ1c!I{gKh=Em!!lu z$Q?}44J7#h_lG=+Br|e0fgifueo2y#O@A13-#`qPR~}8h#gGe^S2l8NNW!aTjx`n@f{`uI+`Yz>TZ7mGRCsDj zDSHY@I}9U-le9xIawd!B^F1ppas`X5N*6KmddlF~|G)SvBVWeM!9mtKD7nUR{Uw(p zxe&&(%T4`eetO|$CL&8O4dE7V+?mV_9h9yV}evV@G{XUNYvq`^O_-* zM1*?6R!dIA)&g@w-RBb69bqmfp$gH~Hs(IJB02{f)9hfNkPx2QLd>C5;Eh6uRbw!IIzg(I9aL2@ghEy4 z5XuoV@x@H4V)`aTc(1XwK#^I9necQ`glTpLk>z+PawO*#sepqYbtQJP1~KL>Tt?(! zBF#gwz*8?rJjAI~Av-*~^aZ5WC5Tx#JJxx+zL~-6pM^@UlkotU4T( z0x7G@w+yvK_CttAMOFp2Ys*aVEwsWGT_!@@w%qVGae=2c39%e;I-(0(k>I}B%z0SR z5G}tL9q=d3H+Y20?LJ|X9fOKwkYB*>dgd2w>|NNs?Fl`4^q{vbFWIAakKVx&d>6EU zF2C%8uHAbF({BqpR8H#B{?g!taE@boQQi7pxO%JV&YoA&6Q6Y~vCncI>;s+f?%0gT z=xVx$_*`d$+;yMORdn}v(;e2;W$mdU&OBVE54_ZFWVC0`lmA1`ypN5W?vQgM+3g*` zPj_TKI$V=a*WV2vE_jky=!k6sF?`vsJ1>m_POh8MnPegqA#P(r!9DQGK)W)`dK+=P zQy$4HMw@WeO1)eu0Dk zO872gH1inm6*{@4jl;S!A>~o-Aw*Pbh2y^lxrX@Y+T)-Bwf_1E8ZCP!8z`l|a&;~~d`Nx4YU&o2Fh4X|fgsX*D3qLR1Ec~*NukFk`?@pnu z(+NEflZL!oXZH!^|6KSi5ppj|?k}SMF8UoJ^zIX42^EviB|@*wBSZP)MJJWtMKsr_ z=kcE`zOCnpa%G~;mjarB`(gh{(d?z6N2jLsSJ;G|? z`@(?j5b{~Vd|`88QrKSDRoFvVEToZ}dT5>{o+YHMl=K`SpUtE%5z?eg+U_&p=SANt zq>Y*R-w-||d_?#Y;m?FSg})ZkD9!RULSOAIL)cX4e3D$2kMc<&t=Oao3Wo`~x*++J zgylk-xyfH7dApy0G;5Q7Pw0G!S#0;<(-=*( z`v%xiw5?AKn)YbspDv_9nzZ?BfV4=Ho+G3&n)KyDTBAwdB)nI6ztEmjhw!oSor~q& zeb`cTD`8UT?#DvWd>3N52KeaetZUl)GY9t3_32&Iuc1D=P3VUZ4(OxHO8e+eqi^i( zSgLjEywvqrNA!BEBYHj75xst2Y#Y6D^w4oVQF`aN#;IFZlxv-~de48KtBZCl$$op) z5UzDPtS0_G*E-GJo0U6qSMD&bb(;J3s@y@la<$fJY)?G)GkEB(ZA9-}g7XLCP0T+R z=ZdFYo4x11wY9XgCh=BmZ&oa*_PaU{o%QW@N^$=dpwGdBf5#0%Ghj4;jaql>j`Gm~ zXBc}rIOYBVc{t^)KWk1gH%IO)w#+MdySX`XvsogMv7IFnS+@gfopLu)@C*usPPr75 zCDyCb-5*Yj!)&<6SlCazXgcD2O2ZR3!W74O?`5z9!3v}6!ODz3gKd`I8e7ePdlX3q zKd}tLe%XsiClN#M+d#_0`$j*XpP~xB{v_BZ`-5J@_H&4dXR!x=@Lfo3%xo4hT}G~?3=Z;t$;V|L zt~wtUwR5l+4SBNI>gs#4tWkQS2v;Ho-op46CfJbR;UU~^$x(y{5p7XYCaCV?I~OR^1<~o?rI?5~39%f}1pbieJ7hJ9H3<^Oe_2QhpxLP8-6|MQcM0J?qgp&Zp$ z*`n4*k%K&^@A60)B)yK%x19+Er;oO>sJ=DOSBOm33-1@F&;GBeEaC6ax7aBG?UJ;) zMfE+{^1!~JFRDx-kYPFsT~e?9sPi5~qLX_GcF6^xU0@#Lw-9luSdA9O;NTDB3wi>% zly_krNfBv=;5Ool^#M z`XVe#M)@CwFNo(_8(gh~od3prE!J`EF_5YaA7q_O_8IkkLG{+j)LYy~=LZ^yebPQZ zOgLJ2zHpk5jg@jsg_jD~33)Fuf3xt*LjKzz-|W@EABtw%CVz+U*TUC?e0q4|nvG``EM)|d(&0fvp;-TTX@Ggtm zZ`uAyCxz{WU4=b_{e=C61B8Qw{BuV={DVh4S2$TXPqJnhlRZNnE$wt&mYpy37;4KS@^2(AHo`;&+CYC8A5BHpz}prI|Y4$Xq#IIy1VEi zVLu_QhSX>66j&~Lx{!85<}VY{a7fzPE0Bgi($-#q)=q(LZWoPo%y<41S_Vn~R_OdC z{}N4WAMZ#xUip4JzjuMU&P83cOmJ6o~X9?#DmkC!2tAuNWYlYTt z;&|4J-YDEEyhC`m@E+mA!bgR!-B^9()y~zd{U<%Mcdvr^J>2)*4(10b>eKLb7M~0I zfjWMWiU)5>wA*oVDmN9RZg|6+^Q$-fIXAo!TmGvzg5@3F^ybWbvuaMqH@)Q-yjiu} zKWz;p9*4vlNIVXSU{8J!-;*DIX=fk5u&iepd>FB;9lKxmL-|u)Lh9X}6^~X78pn2s zb4L&4^WDm417c@eKg8m3YXg2}KAW7M=mm*bEaO2ch-J~z7mH`S2P&|>zn?wv;#t-a zB{Dusu|(EI068gQ@hska!CTyvj% zDSpNfy!T}0L7s`M0{@KMP`+a>XMYrDe!espXAqf3f(w@&A@PUc(9=qIly>Q1NjIEj z^d(SR8%V%3PT-RSGY1H~iNPgIMT8-J`Gwn z{ucK*xEZh&_d00{lcC}XgaSl-2#b(HG|M>mLR~C@W!abM@ZK5L`JLj)v zuoqyn%}t)yqo@eu`HPBr1at7gq9lgn#f;FDnKo=rojZTpg=3NDP2)0IR{Lf%4;L%@ zuuEipKnrS}*9v@Hd%%EGlAU-F$IYKVcTsZY{Dny@e3l%jh0l_s7S5kGW6`4d3m0|% z2-ZsTO8TK^m@)$kpm}})k{JWSWz&Wid6|u~hG)leGMmMl`$zjNf|mZV{&D{CK`Xy? ztgUa|Z`7X39?b>zFeOcL*92GCn!f0u7hQZ&<&>$w%7r1$aw#m*hGh}CewtS>b`mkp0#RAEWhzZ0XWY@7_k>%w0gkYMlbPPp^(ca%ZBg(*cWhl29abkqw zlEvVMuc}BO>~7-O6l2=O@ak>P93B_n`CS<#ZMo4eF`?k{_{!kY%=$cD-F_8exFjFa z(ft8QSBvs(LJ)Q-9)Qif`-fj+(+xZw0v zff3bL7}1xDJa>FIA??Z_>D_{i@(9BvuSZ@~UorIY{CK{o^0dC&k!G1fM1~q%1g`nv z0`nN}6*{@jP{z7)!O1-Y2HI4GIE;g z>GNocv}?;qTA|-qBHXxr5hJJPar{^zm@r$z&KK(A_2E9F`nIFeP6E#br_a$2qx_G; zj>_|@4X#!~&VR#>%J)*%M;KV+wV@$)RMso&WENsQJ8JmK(!SDbKRvR-B)HrI`?6L_BhI5l^g!VV;TYi*;SAwiAv*%@f2q*MB!cFjW%92R(mzD{W+DGQlm3SA5#jfR zKNdbA+#!5M_=4~y;p@WP!gq!53FE9c>@OkY-*wW*3(bZNx})fmg`W}f|2*Y~3(bB3 znx+NvFA!cRhl5C&#BHu<>Il$ljc4y(1&lJT)Tq>*{#b*Jk~F z*7)lDuU%GiP0i!g-qy>olFj4bUsiMZ-Y=D3R&y2B%z3q()~Hu8sy6%B!DU0sTI~*k ztR189{f*0N*1YYXT8h-WT<0c>>)d=4YNpSwCT2NG!v= z0I{sG5DfCT={pKr*rjOJ4@N>o&~K`7vPuYvjPHR5yVP}nTD#Oa6ugJ5l7ZAhBW=9& ztgxUNy!?b2b`$ZzEFX_2OV&i)`5X8xs8q8!G!EZDK`|tha*(iZ8A%roNZ7ZG&tC8fCjNxPCM23Vfo3(}JPeKsvVyuG`jeagKlZ)^&Whq%zx(!`nL7)^ zuqddAR|G|YVOS-IW`JQ>WCsxug#m_5mH`GuL_x(R#zZ!iC_3(%gcxH?%s(*+aZ5~M z0*NuaL=#PXQE_>qCXQlW{@-`{tG+##K|n}ejMVQ|e|1isI#pe_ySn>S^=a&j6=X}T z;2&7f30T3MnS!M##4C(Hb%ZNO+n^O}g+wzaUX;&?!$srSGs~caI7F_&T>w%|UFMx4lk3$2;wyF#C1A(v@|zHEgcd9V$CX7toL!zjTiMAn8QpdzF zL|FR><1IOwa4w?RA(>!BS$4>`-H-W&j z34Uc()-e$_Y64*-Vh+6N!0O24L`0ZP36l^5Z^_C!Cc=6+QdyvK?p*@DQ;5fh=^B6q z_Q^?zvGu{NL3TG*q~%DEY+KCd3Rz+6#vo;ZtdFXz9rD8>Y^Vh`Crb-iSuG+NN^y5B z@QlnV=uT4fiiB)8LaB(wGcv27J4s`E$DIwOI67P4SveIk_I(Vpc#tGusCEYn(#ycI zz}8MhjJayzK^mUXJc7f(zbqc&bR9;igx7=Hefvy2jDq2B=z{67n|(9hhKdi+AIg4OZa=}c+H`CX z;}~}Ez7e1Khd=3#P>w>s@WwM&eZ^}}JcQSVf6X`IY2R?cU5)r$VmHRh*aZB(Yg8<+ zKhiKUM4<#X8jY=e<;_7{AHNq`7-P8P^enj80@;oMuA7exZGQ0yJzL4nx^BC_JI=TLZ zjoWM=h8+H?8i0idA=jAA_GieAHQRd~a`9uD?PK^cVthYpV*Szrd2T;w+eE!lNTbuX zM^vUR)*0J9?>p$^eX-fTf(lM(L|=?$$@o4U44W(Z6)fbt(EulMBZW(tA+D~ON5sSuN1Bo-YUFX zxLNp3;dg~U6mAomZ4mY4qcd1<2{8vNJA|!?IMCZFzoY0bqWcQX{{rO9MhHFThXFL_ z$EbIj%Gt|r;I9&Wo$yxSy+qXiRpEEVHya?z{Y3nq3(dR){tKdC623zO|3jgVlZ$$J z2Td#{BL4`{M+-ZP-%Hq6{L_T?ootjFD|&*knh3sI*XsN)T%i0_%KyCR>x4Inf2Z(1 z@iz;>z0Eo?9BBz;p4)e2!AR3weWYsKL}qIz9xKI_&4GHu7{;*kL~1` zOY9@;C#0>9{Lw-h`$$h0(%MJ*d?77-q(3LzD0J&$?-G5V@H@gsgf#TA{4a&H_mTdS zkk&rZe-+ZcM>-{>nUC~QLK^ukNM7@NG|^u+!MIt6{O|6f!m)3zVBhX@6l^NZ1=r-@4H`(a-KvO62j|y zWV;W3w8I|^`+e$5l}B!cFZvw%y|1hs4{!DBKWO#gp!(F$$JZwM;U_*`ip)IwWe{x7h6)UGMm4Hiu0-Gr=+ z3I7WeF(MtCJ0c4#JSNABbRjcZnnBE1ls1=tKhZ0-bF907`R zG&l`d@OZ>hME{(AuHZW4T0u^5Gm^}_D3)C30CW~Y5l#z&8wugh{Uy>iW4X-1~{RL~q z2J;dhbt%uSPytgG+F+Zo6c3az@V|(MIDHvT#ZR4`+xZATn0D?arQL&tr9rbajMcaJ zGil|%#H`#tt=xaUWLSr)py|YNhf@;WdV6722WZ;fyGcIu zTJD->f=4K-AMyoD1?ENYxZ1l z$?0IYH1m#yf=-Rpn{5N%h`TsfFY9ylF3!?7JlFHm;JM)HS^!3TKeoeISOOmR19yy( zzAKP+WsvmdK_BH@aCw)45!d%hOdlU1UHfS3aAl}t1@v7RW4PpccP(~ukrPrL{tmf)v4Qu24czHwS+^#~@HfI2h3^QDMCY*H6NGMkX?M~X5PK7G0+@{ua^~9s^y!kHD4Zra zKKfJNBGG0m1iebM*$hEDoA?IuQIE47-mday8%I44h_Z-@tw`E2qz!QnavR8+LH#JD1H}VZ}FY&aFFUrX$d#xUhBdm{O zD3N0aF)eH_>?GWiEqkEy2Mb3F`S3=4XA60qAw63-Pe^MK`74E23a=5;e8l`)gm($= z6MkLzP2m&5r-XK#q5LzVe=q!_@D<_fLOcE-|DNcC{;ynN6Jax9JK^y{TA$cnw{Dw8 zDALY`JzlgOpWxeZ2|Q2yY+Lpv;$J4Dk&60m5Ykpf`pZJI;(`8_Xj-nAZ#G0A?Ny|? z9F|D474c1>9habe9arXi1TPO_bThtGc-L7feJp>dS@tH>u^m&$hIZ>Q$D!#!zPL0JN$WHd$1@ud`C`E^4*n5T9=3KNEQ`u z&80hEQd`j&;5t6)6kZ5%2blg!wka3`} zFFq5T$As*q)Bh}EZfqrW0qpB>t1K4NbN!Ekhf2E=;WiS_fhEB=D{S z*3cDoObiJ5gprmUO_+#i-j11=7V@!;La2BwAyjY%Arx$2yR8Hp22cWX8yakzgVPo< z2VX*jlLjV3#S;lV5n)#*ge|W1>sSkQu>_2^Ob$at4TQ;vxikqQ3rP#q#8NRo!ep@@ z66gchA4o3)%L0$ru*jL>*wIMsFsQqhhg-TVX%}A;tJp5i6d)*qf7Cz6Wz`v@MvCV7c7}GYeDsl zG);~lZ9v^0uek@sbo!sWDmZ*TiTiNic;*7ftpUX?SLa-jyfU~dakX8c56B++$#;m$ zTR`?ht~!a=vUmuu1^=2g!82kNyQ@zHc;TH?n7I+aXJQvzvK$ON&PJgP9#HuVL;DsU zLn8YY?}=R*3SWyI{E!I+m&aqprI~d#jA9SP7%oZsN4(yba8JGknXH$0@!SvMB1BgP zNv|Iom1aW0<;@2j*LN51vB0Cg0z{{8HPWsOlHO$KqnryaZxtAEeGkR-@mb#Ky8&re z21#!o^v#ShTyh=q;`$zkKJFjeSB&WN-GMaAlp!+w3J2K5?qCAVJjSmHo!lrWXJ5JC z6E-vYVD?4dt}0L!@WA>^EH^4LCxClTZO@$*=}AQ|n4Jz}wdLTCI5zjXxA z)kTc$p7%I9V_)o{?>0T;$04*pXF7FX)&#dw-}5}(%^up&A+9rrp3E9J&h3vMhm$A| zdmRfCPZJIj4i}CQay+2ibRiE|(iaFX5nd}?E8Hafq}xNCo#`f=5VZf8oe3wJ*&Bcl zi~l{L*_*)snP_JheTFpp&DK&PpLPh+ZxBH(+^#iN{9kCM>2v?*XH|~If&|9M*2>2k(_TG7L!WK;W*7Wt`Yi1YpQY!+ zXX(lCS$e^K`Ybj1J@_mgkA1aok?~~64p_>G?!Y?J++%UQ!E)2XNF{QfV2360`jJZJ zaC#uq zI%K@a6_=ml1cX2QA@I_O`9DCmKjJzHmY9;;QMjr{Y%G+kI)^ zUM*hXAKGAX;2um~`}Xd8#&PK(d)G&LEZyDS#SzT~jynhLvs8~yJb6ChPD}rtY+dnd zg1b@-!vAGAE&2mD0XgsQf=l)XLytg~wI`pYd?s~eC`h~6omL{;xV-5gU79&J;@0iy z7{eu}ATM6;o_v-r&eF&C>C@o3;Pfp3Bd#yqym4FC6_9gfsADzs@j1^0mv<=`aeaI8 zS$ZSnTp8-v0DV<4hD-8UEv~N|?Ms1|ZR=v6vW&Ac{T0tY-O-0GFpu$mp_4lS$`&~x zY=U0Y$L$_qK63i^u~NXrxL4# zY#-@`LbHW{zD)FW!W)FQ2=5YpS@?+XF(S?-X9MB!PTS8m<^Nvv3!>i?){Fml(Rnza zSgweO_8cy{gRrM?pm3}Z#T(cpc$3fed|Vq-f0Z93c5^fbfBh0ojy)OP+!uN!`gxNMGKCZL=qlCu^ zovkT*?HixxDL+DZhVU%mEa7=VKJZhXuZI$^5`JFzCE+bXS_CNP*1Y{c(cc&D%_h}V zaxJ;PO&i#xPVTlJHmP2Hdh`y(_r6wbGY>kLU3wZs?>)n3>AL(4mB(yNRu;l%sn_9| z`sAuRX1_dpJiL}(^TFL8JO;0&SATGK{bS%?_QBn6-!%2A5AKH7(mzh+cXXWB(xLQP znkb^z(o?><(;M~JPOR(t;lj7zzPE3G@ZOI6mtKScKOFOu{tUFmABWC(39+>`EVF@O z%GR9vsSaSmF!ek3S|V>aC|uOAasEqbzY2yRH}YR<15V_>lz(T&Mzx%Ro5>3OmvW)u z9{iW~hZM|YN3i}>l5f-J9D{U2|E0DN@}k}RmtGX}UmB+KZ>746o&VATX!2P@=;w#% z7Y;xj{(zq%oklF=jZ)~&l&5Owvb16ik{s!Z<}ASSG@gV0xF#HG{lUz76cHXt;l6Y@ z^G-qyAmP5$NSa+i!qjCXtp*@r>N2thq`5D}4T=SSGFQ}@d(X?6_!GEyBGHVw=GyaN zP?&e&Dc=#XGopV^Q|yKn`l&1QJQ6LPfEC=CDOiR=JTConhq!`VCup^`LZYP;u!7;+ zB!{s^8sGU}`%|no`s=VlV_3*#S|PgXU^wVzyo2w7H0EOz$H+c-ARX(Uk=vLD(lam) zHST|u3+`IFH>D4YFU1RcDVz<_YP-eYWqT&&$c5E*1fI8eK{{p5NRJGOqBMA)PWgwcrdOUh)}!m$&OoQY^(Lt-MVhq)H0JdKFAlnr@&BV7Zqz^>_x81qZY ze(7nfNJ|@#VH3|p$^uzw#62lyKAWBJ%Ay5#?Zxx$1!oYk6VetrMy%|TY$AEFW|o1> zY9?9PB`Fe?jP}Nzb+MPZ$;vLt9S%!2*y->rO(HW4>~I&FBf%c$&U0tuAue~j&yMNA z?SKAC!Uff{s%onbzPHiGW8Oxwns9TH%L)JMqO>_4z1y6MK5vdk?=)wla4-s~J1qT2 zOW$rX&qR(#(-X^2AJ^f;pdhVUK8J7YJv>Bxk?ePJ~%U3)& zxz1oR&F44<%GFvb+_>x0Ads#MbM8Z2sT)nwF0Vh*FdIbSaoj$aLGEyH@EB=#TWl9^ zZ(JE9y%W$-KI^*RlGDL(Y32<>gZN&H3ob9)&iXEH`&Ox5*2n!I^7wOQkn|qKj;EPW zaCr+r$M>TaJ5T~1_k;IbPTv(syD~_6e}cY_Oena#OF_r=t%f4rW>6o`7pLz=q+J;# zy@EV^TRFyX$@R#K>w5@_xPR1FjOg^;i8RZwE{3l|h(7*YU>@WBLMQh(?BpURq&&(! zjEKLg#%0Ya+&4SxZIFu}gKQrI?Nssocmz980v`7Re_^yAIEb-;U=k9xmC#5rR2I`AJ=xgU$aRrK$PkpH95 z-cg18d&>V%e4bR4<4c6BpI>Yt?cQBIL41z&%s2m{$p4JwXzd|?glL*ASbnnj&cEnf z@y*XD@-I+6y4mD8Zm=B3Od`h$Vp`Z<*h$z`*hkn;I7m2DI9518c#g12I9q7P5$bdH zJd@I+y*4Yq2}tK$;$RJo4I0z3#YdEt*g8_RElD@DgZKGNIuoL`nJ4ez zo$YRY%0lVA+rj(c{71;PgZr?9r#4g`v6X&5{hg^`P^EV~ynn8E_JdY$!}BNcJ^$3; z)zuz7e+H2FAM^ZKUeVud-^E)8|Lq^=m(?duY4hMY16uyo8}-!(Q$Orc>GwSrJhOk> zyW7p!ch-cYe=*RnLMQw$Vs?Q2+k7kdsnd`ZV3_bCKcMfj;}Ut*$fbC%DWAaF@^KE3%H1oaM1Q&! z;w+LCszaig%d|q@v_gb6DOZq z6}Q0BxCbwajk&~(8)f0E?_he!{M38{YR{`(-7}vZ08^$!uTk%ZX%^P=#+_wm*30sR z@r=_<^HzDtHk)keALh3TTKh-%NBTzvZTz;0c0TV<3>G2ZQ(3E{w;6 z3~d0svBTp@WM|`DfGb1UZ$VdKjNy{mcG)f1A>LEF;F8&P+4jxDZ<(-O_5=5WxERru zLDIVtjY>12;PMuLj_*ejcT0RGqrL(}r|$}+T^S_3d!UbUF1Wl)!HDZ?8Pmse#p&Zc zwkty&--f;=F@{U7M_ycCd+6i-v3Er*yzKiSY4CW!bEPFf?_T^n~-uJT4Ii~Msm(B8h85^w+c>QZ1 z)JOa0AmMN!#})E<(@&f(|dZqiMI8XpwAUOn+STo=nF)z6W%WT3K8|(FZ{mv96MS5 zXX5`-xLy1|i+)-7w)ne*Jh`aX*}6#W;Y!uxxvEG!tuhh zg&g;(pW`)=<2&&}A?-n=R|~Hea-1dqX5k$|8aBwMafA5(gjXYaF_=Cg$=ATl56g@&-TU1pswW7JLt^Gpl68M3f z^x)(HtGfRgw#Ajl`Jlf%;GJ!6JyJ7x8~ea?Cw-0^elaL6navJ~fyjt_LJlY4r#M2v zCnRrv;1kl0Q+7^hR}7LlJt3Ajo4NLVA^39~!R%BHyB3 zvnwVhLQ&)slIJ}t=jjbEkUSdT6OuOspl$_~Gm{(ngzOG}L%ZS)$W3g?_6fO#XGLgL zv}C>=HII@DngkUN58Xi(&y*(GSQIftZ-IfopCL^GFZ&LKIFGBj=% z{I_!Y7<22G+o)YoR>L-hSxz6Z^X{WP&D>JdXtk>CJ@ny_zSu6m{Iihe2pt6yu;meW zu)^X-;BgmtOIMhW#f~ALP-e-|6#y#BG6IIW#t_0X<1=N(WXkZ09fi(F!CXe5Mml^P zTNmXT2Zt<1c{qGbf(+}JOyDw5I9Mcv?ZxMJSRr+>1iU&jS%!!jSpN`2I(!@(bNEP2 z++}=BXNB8!q?dtZf%()LH`eh0Bo7WUv9-{cv5q?w4{>@fj?Pbwt44Ppc#vH+a(!iq zAKB{u2WxozVC~9@Cj=Lk21iaDdFsNTpfr(y%f<#5B`uFMlUd<(Dx!>p$tHI`1g-2k$0$F=gl(LbSy#i-lvcrJS=fWXmy+ zfp&)!;@;$V`O2<0ei7jXk%8AXrmfuY$a^h zXhc^ANsnt6K43z@({}^Xt_+gi zYsgp-W4PoxeExC4>2tKhIR9X*p~PVt3$9l}*1zIg?Ytk&9IyLtt80bw>=TX|yV>d* z`en=v){wP_1{`BN_G!yvKM)TS9zn#j2>+7=giaFwWZ`MTK|jxI<{RSk&{L=!E(&SJ*_@Oh_vN`;F_Wh}pI`8W+ePDl{7{=yOEd`I49E ze^hJo?*I9$}`!+&)z+IhQfPaqqiBy4?+W5SkI#3zo8= za{U|L++V-p&t3mUV)?J%2$p~2&C0nu-<&!38*dI?zVppl%l%VVL*j8rtcJwnkl?%O z$(<$17q|8H%PP8=MJ;dZTd(`e{k|;mB2w>dtAQP@lKX4bCw*S;{HMU+!Ji%QVz~9K zpIZQV_&BsPDUs8j3KDtm5t2Ep0Kwl;Hu9fn#?$D-+&pbF3-VrrU_dK*+*nL{ILmj6WBPyJ!ocrpKppCj}1hrmlCrs}Z?-6>X)Ofh%FrAS_bnEw{Z zQ6za>7uaj$XWWNmD`bGgYve|zc zWJMhl)R1LM3KfjWC>T!#p&&0KQQ#N_^A3Tzdo>`1iYE|Ct>_tqN<QG_ zK%7a5k3iBwYiuPRIY)%}NQietmc$7bDB2kjBBLO}q(nwpJ~p8?QXHnjz+H-mI8Dp- zr^Y#=ZihmLKG^XoGpc7+EuB|8g|>+$rL%e9FR7gY^8nJg<)(pYepT&kP}Z9{JTbiB zX}$rRKD%qzuH6uW+R~tD+K6CoX>j7O@{`(E2Ki|-Q8iq1^dJ3Ej|L_pTgnz&zm-{S zWj)eBHna39(_0M$LWh!On#s5=j3kU7GX>HwQ)I!3%spnx8Q6F7z!BqyjtjR_##PrY zt(h{RXX&zK;#Z6tJ!SZuX_Ln-T)KFA^<-FnoUg{cT9?9uYTCT>2Ew=$?o!l5+MD7A zCTmr;Y3x77&cxy6zN;oyd_2{F7?GBV2R4>G*{ z4Eg;2LLU^Q{R6knk^O@g^0>agfY=Zgv8~JFbD~Q#V>w3GAIBIj$vM|}y&uAEz`HTl zn?mG%5Emo5GDv#;k&$LX!R0Lg9oP4Iv+y3D`U()8zAKP+Wsvl$kipvl7hK+@V8r!( z7}Lia5~uG*q+J>6ScHrzF@{U7M_ycCQS)&B*gkZ5r0-6oS*8q;VJrTG?C(i4|9-@{ z+%7!REMfr#<}p5uh>Kp0*xo#JYGZb$pGn@y-3K||inzf2W%w~-d_P)ZKiGfVkB_o5 z(Z}L;$hg3^F%aznY!qygcsAb`JJTj~+6gK{aQb2_OUC&J!_I`=jRn^$A?sgZXQEvv zbG+`qoryQ6?33Au*>ITb_&ohh&KBK=>HM@J`wc) zispkPX+9_tj~Dh5RtO>9z`nq-gZ1-2B&LP!g`I?5g}sH&{?lLdAmK>iSYeg0S~yS0 z0f6;o+kf~NO#T;z*9*TSy6`Qbv-|84o%F-{ ztbb9j^)K)!@sAUl9T5Bm_CL^O&j9jT$99huP7qcJtA%`&r`(0YONCbm*9bQV`K(X* z`-Jo{)^8rYY*y!uwt zFFvrY@}^YY`qY}wSLUyquys}CwUyf{bJrEDeY(E$ZQJX;^mFxI+4lNm&2#n1soU#Q zqqo-=dC%3S%Acz*D!FV|aNJe9a%Ww!D>-P@F5kbYa#yPzt^D;rYZa`^S>LHLc&BY* ztoKxXDxG^%a&5oLf_K__$#>fN<=#*)xe2Mj?>lP8z~HHR4^qjJr|OH!;6nNO)XtJr z(aw^h{GBEFx$C~SEq~MV^&KC09xXb~Pi?xnqD{q36?r$OHsHI#e$%a~TZ$^Nj;!$P z`s7i5Keoe19iw*i_lJSAb6fEP_=<4Tn!(@4MJBw?B>e}_8UDBNM|>6>4v6u9_fXeT z)=$j^8-5sjkxJyP1r_j$lW=|*S0E$!D*w+u)5uTet)$Es$Qe;fPGt6a8@!C!>-V4n z`V0(0myAo89B?KJes81;2u4CC}^>PxtV3QrUHQwHJA@>MxBPA-N3bp~P0Qy{6_P(E`3g26`A3p(L?k;SpZ9&SAc3H5ntr1#{;kga2D7H=A-rxX%i88R->rZe%s$&5_)Blw(^$ zIU~I$zXS6Rh@q}aDRWGu%SdqkUCfJG--hlCSFzEzVo@PnGBVM`t!zVsaX2E<@<^mL z66rLNhgRTSyd97UyfDfP$&(=AtsT-1csyd@ElbuhQ5q5{d;67#8*+;3n7B10O6r(+ z6cNt-2tP-pD&kgSpF#KwqAi+Z;+2q(Z4_8DzVAW}Jj{IWY(iM-q7`*ayczPbjY0uZ zus#w(1(T>C6r2=EMY-cB#9TD6g2;YBA5{P>uuDQkV+rdJAzDtPVpK)ouH`~QE>_Ah z{j6n;C-9)cTfu%E(8BT9RwAM(VIE?_TV_4OgAn~s;O=pa9l$~i$Dv5VPabUYz!#YIso`hsUCv^Rku1w6JaoQCa4 zM7$79P8YC7YQXA`y2Oc>ttite`@Y3Awn?J}; z@|SVuyIZE|_zym=>Gw&`?+0sduqYig?YE(Or|z9#11^K{x6`r59@FlaW83!+X7vk7 z(#IXswfnJ02j}$*j!bvzS_T{OvB9F+p#8IxyPkMFY{tum1?|#_Bo;AdY@Xq&wA$W1 zu^f%&%Ko;clfeN!8hnkqe>d>@clQ=9t?kB*rFt;clfvD(>8bUQNOn8mWsmXCRR2fY zux<6I{Q>ctY-als@E*+5`X?;hc*Ra?Cpd6W!4U7fL? zo4GqD8$#@~+IiD(C9t=YnezpZEJ0 zPejJYS_kR==TEwI8qdq<0*r`u-v#(TT?ZMzI=O4xK(&u;V`z`Y{wTcs8O^pcd=?Sr zl}x~0<`&2u4h|l}BfF_RKxCx6|Hch8Z5A##eN|w%H1qfko9>Wx!R4I;M!eoFFubjS z9P8yx1^0u}us`v}^b!0-pE|HVhY1C?kKqZ#_`3J*3UDBWe z*DE3OUtynSA7|P?DiikQon;`6_Xtq@F`2@iHYlS?QNN*C}E97$y`QH;hD&(5)E|ec7+TK$IZSOThe!Ar6D}S+QdtVj#W;2ES z=ap|ZQ_weww)a;-e_8bXD*qkP_Wm>SIZw#_q4|jW^Q>sv%SivX=pCZ}D*T7|?!9N{ z|Id8SpZt=fPgxo`-@pqaYo~_h}q0Nxz5$V=KdqM==MRYeI$3e>V6IKX^2*(J| z5S}ZXCOl8LP`FIELda_p^a)c>sExXj@JNn)AAp zn<<nO|F`2f6K^xeX*3BMt<^8#{@h_>?q^j6Wdr&8aag*2#={+sac zLZ8PM_;wxu=@W*uoe#jYXge=JcNX14c(O3tPbN*Y)H6YNj<8Bdn=SK~3RehM3GMtq z{sz&sk5ax)c%N{y@SDPig+CGgT=;9@Z-svm?hw-8O8tKq(ojpfL`Y*R>EndCJl=5M z<<38lmha9_-WO5cou|80DtaK5n*b37;a?AASPVee~*>roHFZgV`B z*&NTt%GH&htMu2E)8A(<{C(yWz^i8~%$%g!OsG#4O{h<-gT@ zSC5^|cLnc^+VR>cqjtPdR`^cSLhqfXUegagzsq}Y)Q%UsZP`&+K5ECGdsLvj|4vgs zc&BNQ|KL#%=AwqjcK8ExPz&Dc???ZkKi%fv^lNWZ#g{O5)B3F-RlK!deWKH6;3@Pw zJN;Bx&!2lx!%5)1wJo7p8}Emm_@CIWCH?OM{mtmy{@|=JW@dwVoAvyE{nT_YZ6YPn zVE~et!m$H6kw>#!(4H*kKlBom2<&vU_xv&EVq@PP=52WW2{_LZ^g5ZUcwPnlM>EMo zJs2>Jx|4ZFfIvIC6H-Y#>yt^^L_u8zX3lV=lPkk{8$M`Y4(Dcoo40uYY5R_SXpaPi zc^e*N;Y3Ymq*8534tgD1j>_S@O(jWoQi^AE=oge$)ci%*gnmJrV;AyYz{Vf>0+>rk z(!3jz>qt(FNRChWgCp{Bl08V;+zUsa{5}!M!6*OJh-5eA4~R$(Ir%)l{n0OgNe{gF z+fX7TdEv}|HX>gn$%}rNdn^tCJ|cysxI)~Ya}P*sz%59GAiXBbSj_fnEsG4Mj1@6*5@pcde}_fr zZZ@be<1E4Eh`5Yhvqbz>mjyPvu{okgLw?6lD%`dMzz$D12@xN*T2aRYt>JjTpKwFS zUslJ&ZHT@%neZLNz*})i9TU_IKDJQ^RgYn*yAbguEkao8!m!kqkdJK?cvLo=@S%b& z#+`(16hiej;d2w1n4BW89b5!IE}Ea=m4!-kye0Iaz+_l-ETIn~T%8gwK@7YLeA`dz z%E2@aCV-f{4-qvG!W~$anE+yU@ir0NNSKS5@XlWbu)v|F|Ep3 zDr~5gz0w>LH(`sHL@jo`mC0LrNm#?~<%?M!wW74u?aG#jzjQ@oCD|t}ckipu9v}5q z%cw`9o9Iz)L4E>} zXQvB~x&)BjKLl|&VzgUXyz!u2V46q#xroyoGsa^#@)U4^GBXj$<6gV42?_2Q&us2= zJjB~)&n2I(89?V-_+!5O0awDA8Nlm1!_xy_0BM33K)QA9(zRExykE}~dj!i%yY>vK zzZ>+PSzg)w621+x`&?hfyKsEAFYdsk|3}R6#T^eH%t=0*>+9~>3moyM5br;F;!iJQ z?8gkB9Y!!LcK5L9!3`&0F*Vy@QZF;R+klO!-o||t|DVqGVIN>8`oy?9DZ-!@_f6bB zHpp>|YjnP^BQg$Pz7HP1OX1R`bVl{GrL(5YSuk^e#;TEqN3K z@Wk|QG2i!itg%U@2daH8s~(B2cKkypJbV*yp^Ei`igLqvK2h)<2mE>U5~UYgQV9Pl`V)d zTyib);`*M0KJFj&6(c%*w<)IiCGOUirSZ!lm0tYLPd(N})za?U*FvOH^ z1D_|I#qS~HaYXq+!r{U(Lf)q{f4YzdE9pb?edq_AY?tCBVSoIq=lkAey{P|v)gRzQ zC7mK-Txv!{yN(h+E&3$UWkkq*M*M-|4-q|9G@Z6mu1fs##IF&3k&w1r%B>N76A|sP zc?`7UtIButd_PeBW0LI^Y-8rt~+ewk<*yD4{yutGRQ$ZIk4`S?woESxHwB|J}9 zD_ka|1)JqQFI*?QK}ahn^KTb^MR>pP`@$aye1katMEf1FKn!r zMswof!efOUgq?+MUh!nnrwFs>7u~$#naa0$cIclbnpSz%cY*K{;blUa>6w3nkal{~ zHop#hK=eaG8t$3@6X7p~zZSZA#Fs_WU{3iDgtT;%HhB3RM zSwcIHAoqFE*9q?w-Yc|sbs+a6(VP#U{{I%bc|4!TH~5?&Aa)RbMtG`_GXu<@BD_#| zvG7LW%|gx)Q2s~4KMP+L{!RFS(8o;%<#U8I-;+KxEcUKk-*-;eur{(NS<_xY+o|4>|O#X12f6HcXTxGiA*ot-)c;_uB z-WpVtyzigg?0x_AjROwbm3(*9j+a^{-^oiR>iyGq#^z3^@O-h|O!~J1{io5jghLBdV>L{PlSc!>@pn32e#i*>k5=c7pC7;a9cl@jjK?LujzQy>2K zaF;%xkjmMK3gIrD3xG22(rx%Ul>#T8h;8EA6zVmA$qI7&bE?2Rrw0Q}Pcn}q7@A~r zuc_okq{10hcut>-R^@zwH7vJTR5!bN547YaImYMt{6ekXg!=^;41NlC_Lyc(pd>GN zDc&{u6(nyb`6ZHrNb<6g;u<5r@)0C?RmkU#`$I@_u+Qgy_#;@?%_K`Bl1rV!IaAC1 z5y*l*Q7*3CSlLLCA7JB8q&`!?D_}@IgAA{*BR1^IQ0^?snP!tSl6&YC@=WC_j{?(o zHs$h7#*&jwW)+yHA{FYIL>V?Klr!=+$`##*O(=6dWnN+t(`Dp)ltCjKoo_q7(N6xHp$3i0etpu6!_qX*$To)#K_YW4fr4ubxfQe5y0 zj){$k@XUS(;C@SvCOnP^7g{Upm|(53`4CX{w2H|umU_@~#}L9&i{hpDh!TacsbdK& ziK#(CsD5lDg+wSgE+aUJf;>SmXF_0^hBJ|1m_0xA~uG6sv33f349misy-;c-%z_8$=SQjyeM;LO|w0JIac0e#X=6pL?1sMKTc`ffv-Wy%m49!8`gi~cS+wb>W*-0qFxdgNM13AW!9w;0wJX6TAfcbNT3xpR5dCoHbbHW>i zn}qiYc?V88v*iPSDteo6yYP>~zX)Fwz9+PIfKa{}I*K;c!-V!u5DtF3e@Fg_wRMCS)4;MW_^x2|0PO!YKwL|$@(HAQJa?w|dHlr8hZxnq85%wSRABFPYlKgj- zZ#H|#|5S2jtB2h4lKYe7UKjngd#wL$0AcC4%lOx=d)t7x;UcQyL?=GlYD~quy!4 z^Mt&{kbk~#x$siq6~ZqH*9mVI-YwiLd_efH@OwgzoveprE%CR)-wXdFwBr)_Z;0M0 zrneXO~dW-HWwBri-Q$;Tq@(mr9 zyG_WoC!}pI75J!VnkUJBMM(Q3>0QFZa6uz&bELo?qE8m)@_)kpggbsgn!G!{dA(=( z?Bl$p_}RyMNAa_d`<~+S`b>TOgyq5t;b`G_;Y6X0w^C+g%1cH5^fPbE_8FEElD>vr$c9>@ps_%FsIY2XZNzSg}u+| z%*MEd&|pqy%8vC#@O9{S+d8ZAFwE%WRz6Vq%p2bF?QeL)Zg?Xx=>~i?@3N77T>Kc zYMGgz$=~__zOJzoan_qBEcZ|O6Hw6n)yFV10@FfwVpW=by5948wMzlBQ!q0D1k-Qa~ z@bepYkbIRIMqG;I&k*x@u!f)Cc%9@r=8of$HW8_OyWKI8gH`@rQSL^PUyjJlBvHuo z$FuAflBE&JfhnH{Mwt69$&!d{iCxV9$hQxJ_#{YD{1iG?{G6e<0nBX*c_#8o{R5r(K-qR^$QcQMbvDDV~( za}NaGso||D!m^M{xDwGm_QAv#Lq4`q2o;PW%tnO8nF>}|att9nD763y>eBQCleLJb zfp8gO;4N8M#{{bbA6pC5*bfmeN*PiUJ`Xa~GO>x}Cn=}=;VwU&;SF=VAsOBX$IIwp zi^34&nQoRt-6LIoXC(TBywizcJ8Sv(TcA7}f-<8*PT1a_Ad0X*e@mWN%T3!la>@}Y zNo2>t37}!PM@xB4u@Gy0)RH#HNmwrbj4*uBB^sf5PA5K9FR6s?wXxeD)1Gc$DDi{E zr9m-%6VL9^4R54$3zn4zElVv`SQ^YL4Vsq*6H9{*>0ZIK(%`t#uEEIC;0bSL`Ly;Y z@s*Xp^L=}@gzu-w51qM|`)KcTd$Hw)`xbuFBQl@wx2;{T%v3C?{j|N9vinOW;C!@e zxyU4rzQ>11_T^i=nGdZT@-^2gXzd^2AL$1zhjeF`?k{szAFmv*=%h&#^AJ zymP>a*UP09w?U5evLCn~L|%7Y86>@1(5N&M3NCLR=(xUjTZYfG)EBp-Uk=)pp^EQA zA9gtkE^j3`aeYbLkyDQPiV$7rBpfLmE36V$3+D+rII-Rfgck|z{|28=)6BR39k^cf z9m0ErUlV>q_#L4g2PkL%JMfp{b3CHn-w9tAz9rlx{D&~x*IM>GOI!9U^tBUq5q1;y z5%v=f654Tqa`yiNCyPHrI9s?($m(_wJoe_wMl-Y#H`$XWfYN2cdzTmEV(D z_dwIiqBUz$h3ksfH(BGobsyw`Z5UmhwjJ z*w7c>pD7=-VZr53?0Icrz%N*uSQFn7(c9aju{{?(-a{Hv)!?OP9e z&Ch|snS8-E?$i;2&90wCod)_7Hu3|pX_ud*6MQ~M(tSFci4{0 zhlLvNG>!ge-q==r^JD0P=FX=X`s5EU|BlC#bz{=L+2Zr&w^hh7w%fq3nazdxshMEG znVG$XlgRr5sGv1j?t3)jQ5wrn!Ra%N{A3;nk-%nl-1lhSVsxs{^ zykbIbQ-lNz$Ar#^{H6-A3=w{{l66e*S_mR#Ut}2`5=C`P{3;|$>X>*F5r$d<1_Dz> z{Lt8=39YRK_~JAZZTO#fqfY{`Wvm$@QD7^ube`IP_?<}zHCzyC=os>yhM1Qr777)N zB~XwbVUVZt}KwY(;6mw;w6ao`4Qg6 z-Gi9xjbEQUV||k8CtW5Jyl%Tpre898?E2)m^+~4LAN+HPCD;`w%Z_0~9i3_P65C~V zalC~nZlM_4aGysLeu0RtCa`w1u(PUn5#7gVm}Yh8Zvtnw0}pRAFu`60KhwFRA#8yM zQa?oe6R?)Ih45iHHUgB$|qeMzu2knoyJ=(W01W)POd~$6$q! zv@JLM+u|WkuR>nJ9PEDz7Ou}&SUaU=@xmGQ9lZnjD9lgk5~`#$s7Z6Xs9(@xbN8dW zx9@sNr#8KhDeFAE%hB!1x_0hzde>vx4ehe-m}AfE+GSQygChNcnqfivTPMF66qcSE z^dBaRd-w^MY|DF=W2ik_*|YWwdK!EY244-tqWJ^0y#GgggR-u+&%o@y(*0wY-xpUe zfkO&!4Sn$F`DR8caB`i&U^-VBl#5@8+~sPpAlKF|*b2am{+opl`2vEtqUH1zhUR3@)FOOEgLKjL;OmRE&zyx!FN=$6IIY=r9RK`mRFSm7$IwLSG3J3NG(*&~bgw z#PspJaqasO(yk0u{1W8gjg<)uXV|Mwck?Yz@!PSuKV5*xY_( z+vOjDKHg}#;OZjAcF&uLf;^sEfsaGc^pyZvXY4TYu0|&9gf2LJj&>O5AB^?wI80-~ z^-9S4SFCSmzpy{Tz#h+peOcdrB*fV#?BmETA0L_W$myD@Ai` zA%CKfV+iTFLbKO`=93%w*9zAPHwo_*J|z5}@KGU;U6$V}{EhHM;Riw=eM9?Tjxe8y z1JKqHqr6+^ZgyDEe7^Nw5=mXzO5SuP70-+W!x^uZn(9_-)~n z!k-Ga3GFyQx#vW`AbeH$hVWfsy^w}7w#%(EZ!Y?9VYZ##%pH)o_aT7x9t5zz9!yisV!3-a$0{eaMp7w~Pq2KXcKpB8QtJ}-Px z_^R*?;rqhB3$uM1(Q5|#%f8(Jr0tM&FJV7nxp1(Mwo=N`_)6sacf=XO*}{dwCBhZL zRYLP6hH}m~5{;GAbF1)f;g^Nq5PnNYYbNEN67qdK($5H=6TTp%xs&S&gQaDUFRyaXOvnl203Kt2N3Y~AJOGVSJO8M)B zn}oLs?-Ono@*eb~=1sckIN&uizCIoECOvzlGhwguCMWmq8A|Vc-efCprZ9B(H0X#i z>@bh>CR28-E97@tR#jeG*|xI(*8i$}x<2{93zhg*OAfx(lJwen$6a3e5Wm(kZ+v}f zMM>q8yM7!TQQ5RI0ba7r`1<6$AMJYbg#WkG&p)M--(BH1S6<#$Rrz@3_R8m>Yt)XP z6&6=+uXwKF$hU%mf~|etPn_QG{lwWNm5=XwBKYo3zaUZh?zSf};}Ly%1$DmiGS;i} zc(C>+{riA^M{JG;lKn@sn)6U9Iba%-h+fiW zK>`l_$&puLiz$*nK^koiAcqv4W3|$xfn&cBChw^f87-ES{rku{bT87xHmSu;t+U+2lx5uUoL_e}8 z)4yAbkzjFF^Vsty!9PTB}+5JS)io#7bVq1WR&=Xz8SmVBHJ{eM% zx$!3wt}*_yOX`@oA>?lauo|euHVR=aW2k_CJ?57Pp#psNg$b4fKcj#HK@^Th3U+#e z9rWHL0)_eJ!Pq*ccvA-%LfC{!NJW7oBj$SuVQVH3rW$uLfsMng0U_L(2?STgIICil z$&4d}Rj_}eK!x$y8Pe?3TrZsYVS235qt_?LtWPq{U3d9z-{U%vZJ`9)lMwN#7Q$#t zo<*RRz`M}5zlXh&gFgv=oS3{C(f1}1SW)0D_iaDI#-9zAg)(f*5nV%!i4FPeM0^2c z8L=iz6D%-)2qIooA+R&>Qo=G~D4KaGfql^%G1m+Coqe$?Mqi6G_uu6sX@O4$)YTYY zOEo1jsV9Ux8-OgwKE18ys|DqMb<`TsCzZd7T4E&7k z&KmDnZIHlVijcG|H~d#zVE>dOvhl+aM? z&ZzdL_nnNXnOX2`pPo5qUiFf6$7OwbpE!Bef~D!&g$w5`NyCtxuAV=wdd7_E8IyaK z_DSPI96cBHm<)cG1q&Bccd4$LHfQpjP~GJDRnuqFv;M(V3%9=w%<1mSBGVTxuAVY| z{4F)y%J|ogGT!q_ICEcnV&T@czc)(sWQfELc(+ zG~1j^1P=wJNk4dc#bro;)6zd#F%0SNC_OP~y15+m-N7)({dPsa?rnl&(q+NGhSN)X z^P03T^GmkF{F=PYl^h%=O1O!so;79ZfA(7)A2q=g&CGE+C^I?KfSo;~)cD6lGKCwN zS(-9s+=$`*hgW!+_dCL`pV)u-ab}ycPX>=iMvv~8Y>b>XS>lsD+qC<;AMInqAVl}?Ki8BhX<94?X zCBeM51eZQ`n;yfp&p;jM?)|t01>8^G%OHu8&g& z1=GZ4N_cq_O1(h9|Z(@&U z!v4%RaeQxNzA5YbBboW8|I2TXEJa&6Z*!UOD&Yp<9m0Es4+_68{E6__!WV=u3vCG- z^#4`#he996A?s}->>xZ_Xntale-CL4mR}Ll0R`uc+`P{ZL_bD^{L`Xoz$5*f=odxP z`p5Dg2>&5|K28+!n-fu=`8NV~5a0Y7A^&92+4lRP;y19{!}>By{2JkfLcYI8|4C-2 zhu(FhQQr;1+a>oE;WvffQT`)Bbf=Z$*ue4}KZzy6)Zv0UnjglXzv+;f4k`Wgqwxm5^}6%`7Of7g?8M5 z|69?25dKN{s_+frd%|791pj}OckiLlXi3`UJ%MS_v=oxxN!V3L10nf+h5d!Jp_1?B zw?>Pm-Ie@vh1Eiv7X_bIQs%D^UMpN9_Q|JVm$*o{Oz7sb zR*Sw`NV6~HHwo_(ZWd;rA2bA0-pyOl9!&_{L&7wzV&0$gAzN3$`pmC(M01G=4P z8j_jcTgbISq}_Z~_B@rFpIRU}TA3+-rO?eseMvOzrXM-)#QPkU&pz*4ik}v?7t*Ru zdCPB_nfJy#RqsaUsW2N=mSzaI?){#Vd-v#W?0tB@XEg^S-17D`XfRJz&}Hjt%sZV? z>9wC+pFD5Wj@~DB{or%&cm3eXdb|Zgx>Hwt^8)nWPTW;k(Q#L9g@5X+@Q`#(!RU%H z6?khVk=pvj*7$x!Cw#x+>~_0yD!wt`y=`r#!aq{en!)2M-@u$x2Mmt*dl8cU53uz) z__Pf<BZX-% zkMrHZZ~ah|b1)_f4n^~yW$u4j+RK{*PVk;Y*G8i6S+;3Ku4?E($&8BkLlp%+PjAgL z&4oG!zmWH(e&y@frV$H|COMeog(PY3@`q5@uMmsaB!B4JNc!WNOe37my#GZkwn?WE zFCfX`vwjJeX{n5#P zkMfRh@@%16aXbkqBEsiBgm5MJcwT2@=g5-?VZ^B~MxFf%B@J zJSW=kzqiW)pk`dzhswY&c6-6eA1p=QW(AD{eT4*EBxi#yP-(FFcI z_W2Sfs5xu$EmUky!FXKb#UMhc81Gp~ZHof0tT}M;)xAR6lVdhJ9Ir5~AhKShdFO3``NtzBybD$k!~6@P zd=4e##lDTwE@DkY$^uXIP%4^y>mIS#=N2;c_lep^9_z&<7lBIHRDcC$ABormFFW;V z+47j<((PMyIJS-~whXNzuw<5mQ&tRRxv`RvwBU;EpxiAG7(XyTBl zFAGF8MvV^U%q&7vi0;~$nrsg{0A48 zB-@m#I~PsO}ofoCD|vya{MrJAkGVhf76 zN#Z`_gEi;GDsv8|S{^dz)v6_`k4KXY{U7~lTYWxg%lHjzwV#}hX!G%7`giStv+BHi z^_x&G<7WIgzQy{x5^H-Qdt!Bl?HC(BFn#X4biYwU(*rezAU$H< z+^LoG=g*xt|EM&^6O@$Nh=MLXF*Qbqd6ly(C(o}uDt!iuboRpzI+af9)oIGS$#bU8 zNYATWICK8YxpUIpx_0kc+VjkyUoZ4plQ{?>2>B?;8Gz-2Dlh0Xv^2;)C~s(kM8n)B zsb*pGaPP_G_b?uzN-J>&Q9rdSz}0q0VqufYdTu7Mz~?;+^p z@p1o(5WT+JL9gQXm#&vp>R|fR@ zVj?5s@&oZL8;>y)e5*Lgr|~Ttub0gAT6=Hm<6FdSW^FYKSch-1_IfQD*COpz*5`bb zZ`qDU8T!sxn0TUapm2zgKdqV0*LC7lAun3;=L;7LuNJNn-YWFI#SP+rBz#Qxl(0tl zyznLAZlU>TP_Nmzfx~eTaX*#|?HeKRUnP(J?KYwPUck+9m-3m77X1Gc|5GCPpNp>% z|GfB@h1(=I9}4pG24Vf?Ljg}?E_w5vfTszXd2Bd*4ZW$vaElTl|T_p^|6&P;A|G=+E}0*f&0qn=b`;t;(;FK3X8TKVO&Jf7`QO z@<$|pQb>CvkK+ZU|6cef$+wIDtMDI^<690Z*GSlmhAf7HfQ#f77K85KQ3NH~Z6Rr?mD_kwK`xoWb ziMRV0{5|3y5Po0yi12aYuZ1rNw+LSn{;%*Y;RnJ5?=#e6V+VkZ#kUl;7Sis{d`Akq z2up>>3r`Xb7Sf8$a$|+33-{-%r74@`RtW9uAMpO$#BWOeE#Y^C4+1Bgx3LUB8t%y-B&1=Ud|F7i1o`eldMC&a5)Kp65kl}AsrUX_lWT4!e0pKpkVqRh4fR9|EqAf@E=0DDwy6_*iP6%X#EJ%{aQTbk`ETr zb;0t!-#AbF0wG-$Outg-`wRbVARQM>|E`dZ3G$B#t-k>Oym-1PnEtwuP73nx3+b95 zUnHc5g1q$)z%JrTg>+mneYo%};S?d=7)-xJ$ln?t_RZpGT|anr%l>AuSE+OE+BW)T z5yHBB!KKIc?B=rX|C_~?=uZ)9`GR+BxH135HxFBMOid0})H$*I`8R{!SW{>4^H@s< zYv>HV-qzAd%zFOKB-YePE}FXi_QBJ)FPl}3HFS>Ho;z#d_HWHPV*3?~7H)69C_IsC z=$wz0a=4z(?>3zj_9{Eh{KO4vc5Dl0-H+9C+9Pk+`+RKQ-Sjxt<=OEtR?oq&z+r%Br8|IHABy#MDo-ijW7SXv5!eq#lUZyE^hkUi&ZMm?$a=TniWb}FOW)=JMQm*oFPL=X2y6Sk8rF7p#pWYS_#fFknRH+g?I9Lil6eP*j0{{)gg%IH{Z6++<4e z^*RcCR%_Zf>U5r~C=~?N<_5Rn)^{{_oolc7LjXOLhvM2Hvw92jvyfa}B;6jKM&K(1 zoD+m`h{<4KxR!g)-I0Hb11^}Sy(dc)KgC#)VWg^{9zrJ0m%yoCl4KL>$NmY zcTV6#<1k~qjaBikGF9CofN2fqU+geRIQh`(lnawXeM%fIbp29}zv4g;JphpRXeXr2QkC z`QlFl>*FBf3z{zjGI$vA=$OEh10Z*=n9PNIc#-2fOAF9^|Drzb*Jwmv24wImm~WC$ z@M)FcJNMyaN&(~WG+Lr+tG(kd|go01wt3h1f?J&&p zflPfcRY&@+0PV|w47x!d^ZDS@z6?QJAJ^9Q`gpJS{ks{oFGC&uk-!&GA3Vu7$hf|Z z(8uHC{_)+}>$?Lq%XC3xxDzL#7uwJVrZKJ;`h0)PtJ^OA1LVUsRRypx9F-pD8KB?4 zU&d%AuRuOtYd&!Q7@k6mAICGXcA=Hl9|y$IwG1-Y0DZqFq2TK!#tttS0ef9v2oHwb z>njG$I&mCPScyhECgL*35fd5d>mhR>?BdO8Rgkj%To%cED>=cZVJBxhv3*=%i)BK6 z?BuPGoo%!Nac?`hd)8*wV~Gsq?8BX%94ChNLjvc6=bQ+ah2bGYBpyM;dFA!Q^zOpm z!hXV&g+qlCgp-9cgbRfi3AyjoYxXwa4dTBhyj^&=kbNQZKTgE`^@NZ=>k{ZJHYxoN z;~v$KJ3j)r9URz&b-UuWmTe5i+42hrLK$n!=%Eo>*`bxnC^VJ{(n zb5TA}c#4oevM3)XoFtqooF$wiTp+wqxKwz#kbM>P-7H)uw04C29`WB5()Y&v)~-Nn zN8q!PzaZrO&wSg2JA{81@KzK}n-$u|>vdnKPwly?;N6ngul`7@AiCIH}2rH>S5 ze^cVWB{^5=)j|%YWj%b>(jVl{7g&?~^VwDT*f%7QiSJG<$G64F)7(_pSZX=FKf6$m zo;`Zi*Df>-*B3%9yAbEHTDE>!`AzvSp|0#yb6NSc^8E6qn9VBx(d4St`Fa) z=Zu$TTruNkGsf&H{_hdHito8<&x&1-?+TV&y=UoPCsbU4F9&X`Sia}7ot(|;cNNK< z#mSd9g*R=Xj+>L=gz{U<4k>F@7Ti?4BbjVagRc+@M(#?Tx@^yq9pUl)!M(dFrIj|! zzhS$X3hxJoJ+NsK@9ixSjTPo{j6Uo`^B{qJh}Ib_vdjxG`6X`r8XLorkh~u4o$NJ* zSyOp@plg;Yn2Pv0PsUVq2Q&VjBDb&x9Yd-9vN4$#Dw=uf8sx%i8vJpNnWx4hW6o^Q zIm^Q3fZWtiu+6g@YktB$B1q<;g!?{Veqtq3-S+{GZeS+p1tt$Tq#Or7z<@a!!UFaJ zVc9RR?TA>=gzP}Fv;-8~OSYWs^JHz(s6j0JHe%rtY{FB>@|~`59X8=G?&4~)M>5se z2g%Ys=h&Zc)7lCNxGZgQEgeGqlJP|~H#ITa~b1QfsiI*Y!DTqcsgB9fWNGezc;$*~d zIw$M1g0GQy8L~Yf8u<)XkVbG791LO@VtDpOUoeeSD@Yr7BcH(v(i)Cu8jq1Lp-T|M z1y&o!_FEwuz#I8QD|CkyLe2wi@H_A$<7*FvKPWz)onzmN{Mh$Ke(XDDymC`mHIC;+ zvoKg+2-6|a`b&&`C-NGFNwEtc3JpQQ$VW&UIg!vFF&R|nuO-pJF@Vc9y+@ez zXl&g+M$N*4?8X!LNkMdqtEz}@x7kNn;CZY-jGc;(U|lYD!WK%fb)vD7SeH`II#~L{ zj*~r;(>~s7=bly|#&(OMtkxhq-Eu_@R0cL{=PAl+GqNt%I8YV_W1Dq|6lJw6*(r#) zObOEv6Ty65rWV-EkVypR**5{ac0u#vx4?8V{A7UW(lcK-EP-qVV$8bU8f*g5-MvQG z73-+I`E__e;DZWo|MSO*`xiG`!{k7X2!Dc$niQpz^U~OUvu&3)ZQ5WQ`1PqY#(Tec z(R9$OQyd?@{h|`k*O~k+qgNUI;zgLRsw6qLPx8>)km2$a2a4~xXgZb_KP+vQ>exGH zt)bx<2HqXRcKz_;tnuOdHoIn;0UAo7VPwCuvS7bs$oDo4*I{L?`eLDR7_j%d(7251 z{?tXr<&2e`cJPc@-VEs(!}P~7kVkg^$jlzMg2%1npB)P~USH9r#ckZ}VjUfypLL7@ z?^o0X2_MVetvlzlZ|V*XMH8UYxA!_gt?{zt-7^H^FhDb(-hubZ$2121KFLSiU%rmW zlU*;*lMg8o{efOLMH>;{_d69!<71w7L?14|YwlL$YXJd%uG_mS_scz)eJ+g0!H&L} zVWYY#AdA;~FLvl5e^9ZsiJ;^4jz@)Ck&pGVJ{|{gE@E8YGzim>`QX#efgrB0SF4O| zx*^iMzNMgj8R}RDeZ?dceA;60aeXJp^zokY`qqHcAk?6_`ozq+MD9}?!r!;=QAmd=^GHytW`eg5ZD}#^9+!A7@kD* zH2E>e*NcP#_m5#CV*EHNV(o%UCpwPCpkt>!xElKStKA1*7cq8tLAxgP8v{NDm9_E8 zfL>orWMo`^AZ*=@YE|G{#R)$R+cugfcD=I2Goe1V?dHhNHsSRc*|sw;G#RtD@2Zh6 z7xANv{bnCU+je(hZ(%=Sxp1^_ys%O@TR2~Mnb2O}p?8(|+k|%r?-f2M{Gsp>;U?kx z!Ukvv?q@L(on0-PDlT$PKyG8JiQqelH`^-sKH|-$3Z6r!n18JDn@ttG4Z=dY*;K*L zSGw6!!7mk0H!{nw5`TmEb>eBdW4ev`guV^p>pOqdpP3)W`4{0XBJ_l~0g1Upr2F}L zno4eC%pq^9^sbWk7M>)z9}7A}^3xl?^En)!PQj~DhA z+I5cf;o|Lj2hV38%T)+x3eOetXDieBla+X>@XNxhg}jHEPU9%?o5F7k?-PDc_ygf% z!k-J-FSGpbgjtB1d_F+hW0_teJXUy|u&=O8nC+Vw zFZo2_4B>2{-A~YezW61=WkMQ&S^tf~wL(9ZnigTE(+W(aNtpNxA#K9s{dz7m3X`|- zn?SpdfE-szc}mxpS?s~nYE1c|LYj@qmk4P$Cf`p;TQT`D!imBP;SAwy;YGqrg*G1? z%KLR&Zjs!NsisMp`X3O|vP}MGLfVzd+x-KiC7JyH3TaR#|A8=jOm!L$ey01e)qX5> zPsy{#RF9N=tdO>3mY*ry-x%vv%6Gkx24|MPTbRr1HP1aaDQ6)1`~3u+w`P>%0q^hk z$ZmjH7i;;dy4O91`Pg2)+|cHF%x85wJDECsRZG`TdSi8dxVl{pR$9r$N-H@Dtef(9 z`M6!FXRxlyt>bp(_raPg7q8xP@Sd_=`S;$s=a9euXlGbZhV)#N@GGsniutXc%K|;#L>~L6Bp>?Gnkr=|kz9e)Xib$xERmnHnI-b`_+-nt zsBU6Le#oHJQ=TT-Zv+({4@GYE6u7y513C6%D0e46bs4!->U2|_qW>g^9WK^MVLzEO ziJSQRR(bERz)qV@DtQEG=eXK=Co(#}m5~h|X12E}h1ZIYu#mn~XLuxr1tr`L*oJLK zL<}MZTSk@#S-{>o97uLO**8!)ET_6(Ar{WZ#?45zn=HGkaOhT$r-3RgW2&(W$(|Ci zSCSnTv3G$z=&xXTI=WDNCO;r6VvqbI5=m_6^lRiZ6dwX^H=+u1r+cyBS*18cD_BT^ z1rGz!$Y-#E-5`MOqpSjqTw za02T&LsF&;$ASN={6H6@+29H30EhzLF<_1+*vSvZ5ym58-1G%&NlZgT7Q#G}S1mR- z2-U?b+28`FZ6r(aRKSc*aHYvBbH zSpgAG9OlYdye84NUElU={dt7wVu_H!LIt+GI2r_)7{}%I*9t`0xq0taBkpIeoQshq z9^$;cXML`GAP0H@j-PYneIKs8aZvh-F7RS}HKfbq^~H35++_5Ni%XIXOOgwhCYxbG zoJ8`HL{dg>Fr_J4At2o35XYbPq5?^ZLL#D_1!nJY2-09PUPd?`j zycQpAi4Es`!X!Bd+PPsKlYMzOVsFM6R{dF-@rIA2efc`rpVjH>=zxTe@9X$aSW4sH z%GVKp?xgfU>JPLxS@C?&K1VN`6#29hLBs46g@<6IJ{kG;=j-4)qi;r~GWseY^SYUg zRWXANb<{f%Y4LhFaq^?8Hy>#{4q~>i<6*perXlyi*Ol$-coYXvj7&TZxC4L~mjZ6!(+K=hkzK%C=kmp$mw_zT}4Tv~ZRZbcNXB5=W*Rclq_}1kE_m5#CV*EH> zkF^VaSwzQy%ZT+x;ThwOzGzXi&-QTh==v&}+&oOo}e<@18|jTDYk z`UK%r$aJl4H z3Reo*$5W4eCj$Js`1L}&?jX184)}=VzY_jh=zR%W#Q$0N7a^@(tmhxXl+Iheu#vE- zu(dEPwCfh-j}hNfxUcUWXij5&X9%YX&lb|Y#`Hx(8raBxMac2>)raF@FaPf^?`ipV*k>TPcVP{`GTExECBD;Wy(3vzP_w2C>ph%`^&XBt zye#>4UNW&OJbuc+cQ#?oha_h5c;t6HA68u|{0cDqEd)7EVq(9cV;pONmvS5C(&dRI z7Y30_-x0Ci11}@2_izm$v)+SQw)-MO%B}a% zjilMb6YQR}ns_RYA2pzIn#Hlg!z@B7)!P)OPDRF?iy_K!>pi$N9^e$gj$G?(;D;d9 z*}$*86JlorH?jfk^NCfI!UldMwz7ebqXZ!=;5$$_U@Nw1M7In>8QBZTuD~W7NS6IW z!BbG@Y~b&MEgXxDvw`!jKIm1j%@ETRkAD!NB6=FR^F{ALb}NWRK11&fwVwP_DByFUhEH?HfkkXg=}fg4DVYU zbd;V(T1P~D&OqQHVr}V*0Ty_5vsxrOf!iUTm?nXr8QssP-gYhJY+Iyhiu6pHZ}V81 z^0bYP#vKW3;&tQ#8!{f^{1n_?iGWiReO?B`*Pbu^6EDPUcHk0c2ZoLJr13EE_TxzQ zqUpn~PNqu|$$*odbG&&kH*%empVw{4jcjy1qY1R#5OvrXS*rF-BbxW4UWVLBllqMs z)HV1#4pq0=;-i-17;|f}y_+qX!+g}h(Lw!&r|-vn&r9t<8+rF--~H^`blGM3z^ zANh{+43K#koiBcb5yBE}9c z*oDTZj~%x|F~-t(Wk9blCNeTEKM;0Yo~umot>Pq~#+Y@sD-K{)oezthCje)9}}@3W+OxS zXT-mt{5VXjhgT}=W8X#OHAGAc+X;^mb{6&!@<$r;4-gI#4ioZcBhyb8o++FzoF$|Q zgZbFM5|;^A2-#0k&VH3>=NY(8yq$0G_lSQ$_mTwm*Atq} z^84$pkMywLscSqiXMn2Lcwj7ao3^n3IgRhavj(A-Z4-9QLd;(icB?tNycukpIpuei z|Mtyb!u6QX_y){t{QR4V!7sd-m~}noG`<0I8n0*SqEgIeT)q9yS;ubATeJYP8;2(? zL*9+Zw+wkUA_r$T&fQs@%h`>ehh?;|S-PxES=+LvHcEIsW;fo6$oY@M<6j2#F0G6|~G3R9}s6DqapSvMDKKJPp zG0Z=Q+rjLH(}*^=a(F7)$z;#N#?5^E4YK^|CLFp5w2hOV(v%}&V}oj=iIVfNGc-98S2~(EP!#a89Kcves4{Xa zfei>LVFjX1dQ5^EvP_FkfvxE26pSPAVT*CC1g8K~mt++1ksSr6U=)E}JFI=cR2q$t^7FU#oWUbv73 z^hQJ-Lx`^Kg(;90I$(PuA}4|-Dm~v4vFU=?9}(%ph)OR6X@UD|S8eoe?haYW1}kF> z@2W&_7`OGCU1MtRiB+LmL3RV?k-Rhx+A z*KF~%^SV!jywjYyb1FM=CAEn&=S-cwU|QwGb0<%oF>_93aA4I2u=Ke9Q(Qgha5OEN zn_Ljb`!T0*{v`&I7KO=qCCMVpiZMQUexJ?^-A?G-`IzL~l4O%Kh&jo#OOlb%Wf5sd>B*O;Op!sup@Gs(9ir-&;M3qLgP;i|ES{A z$IcVa6~abDj^XgZlYENV3z!lfZsgYRY5^WUA?!KD#~Xh$`Z6Gc)A1NvPC~(_Re<+2 zlm3W&9o!?2Y?L+;biCeajolo9te5riIEZr*OyDAb@3?KnR8x`?sE3ud4(>SIg13D;>GuMFt*#Y9HN z*&)F%5x-pduN9Bot7XTr^QHcc z$DLMsJK-_H&cYr-J737(Py9e(w%u^Dm5nTGxg(iKZECtT?A>oys!t=%etkS{{hg`s-OUf~42Cy*4gl%kxk_yKH!?kG4Un90OVP*qcVmsyy^IJd&TcVxyMBWMD>;W6igUzK; zlgB|tG!M4j;Q2XM@I2+`jRa)OitL1v>`^oib}mXs^I$J#i7@|hLVn8ZKej5@MbgB5%Q66_&soQBB9W>{f`-t&dH zd~8#nXodbuZ)FGEZu&2ujk@+)bw!+TdQ>UfnF7g4Sb5A^MS{ydXixe+vh#AcJ9+P>Kl4W${`Py-hxv(8tN$I(R2KCf^1l z_H|6*S`t-`DK`7)LNFNBxEOGqkrN4g6515jB)B)R5BkArXUzEPQb$tigWJ_nga;7A zU_5~tYcGAr8{6fbK;Y{emgFOpAY!S$OV^UH>nj*bnC0apxX;K>Sc;f~d7EJ6C3(4} zj3TT+Oa}8VHQO|g2D3~P?(%XH?ifaavcPiJAfjE^7~gOt;a)^eY7DTz-A*GyDI0&V zBMHM0F=aBgE-+_%M4UpNnK6#U)_h9W(EY1fsibjIfjFDA#+o0^{4p%ZWVMJ`8~pRD~Y4o_6lNEXW7eLjA8Y zd^W5aW&_VV1c5T|U zX`4zw7$(2LiKvajq|-#I2{B!@$-d6%sEyiMN9wvL^`$ye*G8$&yVRuZK$xr^pFC_l zlqPcr+x7@gGv{aKbNFIb>bY~~r#nrbHo1Cor}>prt7kfX zdR3>XbLUjgn>@98A5%9(9*+8q@*O#PEIlXHwi@JqjrJch(l@#{KGhkk>63}yo1dXc z9nggqBF5)+Nc(OT$X>R8QR`)S%X2T!xgxb9d1c}%bh97Ve(z4t7xsI$papA7P)8!> zBkJvXpYvS1m#f-if#XlYlxcNdWUrf|*AXvsk6O#&)A$kt(@+#RFK{p9YXJ#<+DGstq!`dAl3Id;BZmOiH6gBZ_u1$OE@7EoXsBd-lK zYn8;oF62ATGeG8HcoNammp;nkDi(_`@OnqJ@m&cJ_1{Qbg*gbxd!7VgWR z@RHL1ETp-S$L0MB37t1T{@DCONN+58E1~x*93lQFq1joHzlZqjamYg?A0f=1(_xzA zW?+RLGsyzyOYZ#)OT?Ss2~YGpxiX#83J|>?qF8+PoDY8d^1kMcK3V0=ngD%%?uQD={q+;8B&*Quge@xHrJ-VbV?B5@=4fP<@8n+F94CbV`F8`z& z%-@_!mJg&irtr|MjrLsmx1glmmM7lGEyvu=vme}@s(Nr&?#iHZ+bu4wm8FFzU^eI3 z$({Mh6w0@(d2n}td~g_a-m-b~o`c_Wc~5%a_uyLmt;Yi|yykE#@Zk4Odf>OO`MIB) zz&F#hCO9Gq?@XIri9QF_blH_SzV!oGCU$2cd}s6Xdz!s{%L6WLXEgUklIOz?D;3@a z30%^fyOnCs!dgnhTn0 zG5Q-@KpyY5jGN|GX5LHn9vgd<kx zSa2qV{kMWnBNluUn{dEZY}X+cyo%gm*_|L+qHrcQZWfFe$u4K=DX)T@14@pY=fGa( zSU7Hmk=+cIJ00*bSGbj>rcfsxNrl&ga4c``!doNu>tGvg1KR{KZQ=$H6*olr#vg#+ z0ImrWnzn%GNpN_fU;#db_yh{4WHSE&$<2L&6?n@E1Vw!2{T8&_u?5^Q3^3J>8Ji|+ zJ7(-DU|X=Bd58-U!v%Mue5S66$k5y;T3!5|rJY*@VzCv<6!JUGun^AdTUKR!s|SH>Jj$ZFxwM4Ai{x^vK37SJ0^cEi4ll!dk}c)Efa~Q zj>%t3;wnUBBCIoV1YtcQJ|kGXmIQYo<|6>7QX^T)rH-W3higE<9YJ7fZATF^@gbCh zox;$6lJ0266Z#^;4@BsXXnrFSZa2pgsFsD{A0oL15tR{cKs5gl3GO-Mga^EwgxlXy zprYXFj}F1NDqTKo-Eu_GsS!Z7ALT?gALXptUK7z^M7uA8(d$5d9}z2>E(TbLsZLOJ z7ep+`N>DAiMAiiHcz`NQ#45~X#jZh42W5e;&%F@gejyA)#Imdx5UGqyv{D1_Xv&Gy zg6v)yvp`~jyV(&D{+$^BmW;W2(qLI%%+)gy>@38%tEU1yOUFtwi#wo<|7s3otT?8v zFId+E(cZ;UOQY1&{2`$Ve;Bda`XD1!#mf2u@%>zgEEm+y=9?#;jpuNQWjhU93*W}} zA;fsL`@pY9#65+rh1S?6jN)zW0QyUE>(hj{%RuyZ&BJh476j5?HvyImr^x1HF=ACL5#TGM}#| z%C|l$3t6%`XFtCs?4#ZK^J3eFBdyj8OWJic}(Iv96B_}elZ`q zZ&)CnS{9DPHXl*HJ3f-{>`~L;HvSRaAFS8Sly?yGyz*GuiJ)cX1clHX?*w?DwgAar zt%hu-nm)&{)xmiWIp(M z&w(JW@AX5S4T<_1B6@vGLHjZwgTqj02?+(CwitX|-!ACmdlB^&B6@v%LGfik25V8M zBihdgpT?J&xW2n^gYh`2uL#lWTL+qD_)^61bOC;OXX#`5J&5sq$3e+?ETF(N#tn#Q z{wj%sZzErQd}ps9pWg?T<^C~jM2sKDdK^bFWIPW17>tgiG3eN751PS7_B>=haNih+ zvBL}Qg%ZBX(T>CyN7hUItTV1}bF(jeXRgK3FbW^#+ZXofwS8yV^P#J&M!sCcPvSf4 z#q#he4HOO$@)s-RX9=eYd9hM{zL57K`KyJigtrR6CFHfvd_NLCCVWa*Bjk0+d~XWv z+ZFKUivapD{q~ar{Z}cjNBV*e^tUVKdw^c^H2}ZKdT_s+4-NbAebxITBKV()|AqMH z#Mknrp}d)0p>Ge}-ry-L1Hc7rk{7Xda-%iQ@CjOt|aeA#B z`w*6AzfEL+LQD(W36BwW7TR@-e0{_Z6rLg+Asi#zpYLvg@?9ugB3vf?iqNia)Vogn z?ZSJ6-xcy6=5ahGd`kFBAx+9m|C4aL@UOz%!hZ-x%k$?w9wBT)LFdu z+1Y)9dIv~8Na*Jd8YTV=;Upn#-rQgFH3Mn%CQqw4@hd_)4#?ju{F?9%q4(9@FaCQ% z@3Z@J0ZhL`Nb^5=zW)*ZefNxb zTKp-0QAm3~`L~5M@{`XM?r%-lW0bG6u!pd>kZu9$8!Dt1fP96JJ^=F7LK^+aUm>K) zpZqOCn)u1zC!~>|{9{6U&V2;mqwh!XDq?!lLf@Zs5Z_Ul-JkT8yi9nq(4LRjukqq1 z3M+)ugjK?7;eLIe+4J%5!}r;vS7~Y5!v1}q?eJcQknQ_yv~+!N-F5llbtlxU!MA7) z>HREdv32$CfJ%#)w{#0)w>fFLB}7K-(UX6%}?)X_Kw%G8Qj5psOk5hTI>!w{TA4K*YmH1UtJw= zp8wz$%x9HqUXvJ^Z&C~%gq135?q2m5;gz-<4o;mPoU0F6wUw7`O#20yDZHAe<2~2 z;)@oze#n^f-w!ZJ>Ge7u-nUAhOHJzKq;%w*ULU7M{b@!BqEWM7TYJ@YLr(jYT%+ z1Rb#zEE@|foS?>TbS%DJGnP7$im%s<<(VtwFOqO1%l;Qxo;Szx)u!-E5nD;NZN##p zEaFp=cQ!*fxdfs{MW~`UiOs#>8Z)8EA>bYbhj(!nn1wh8F+BTh2#ZTpC9un|WfDky!^sH`dpQYe&T>vV#UlyqHQ)riD$2+^ISRCEAeHba zB6pm)(dbpHIpYDcowhhm?nGL^ROD4}KY1g@P z*Vb(gPq{DX{uKBx=+<4zQXvb3tS0nXwnSO(c3Enr{!f&8@1@T77$%t$rTgL4;DcMY)V#!Yu_O8M;< zGwsJc$P@I%7kMA|i@cA%_y%3Pz3Ts6-lzJ_T{KHbPg}s{GvqKVM2{Q)-i}W|AJ_pO z;B}O(XZx&wat9X@9)-@H&bBJ$CKlWS&-pc&Pw(t|dyCEo4n_23KnBm^fDVlbJUJ;V-y7JWulR$H zrJVsfUhf7}xE}dfFYDuR5c%5Tb%PAfhcHb-!Kd++C$4WA-YAM8qrQfSUf*S)eHoC! zjnLPDgo01I1bkdyHS~3XjQV)Lczvru`!XPdN1(5~j&{BlX>onGLm#r5z9OL4w-z+@ zu`Y%j*u=Tci4RO;{I<~Nn**Evc|McUnD0SEG;5VldJ*}K^9+!A7@k1%H2Id;sa_-$ zxPJ_fBgT*8-dH>H7rH+V{-TbZ_Fx3`JqMW&zAj?y@Pb#G)X!(w4A<#lUK!Bqi;0Yk z%MZl&c05;^;9JE>K8^YE*sjIV4zR^Dp*}uCG@G>*`}NvB!>qM8TrZ6ufjB?7P6kmx%LY-`GLVVd8C|CHU^j=fAaM-^KkN zE;Roj^mu>8WXWf%oc{*tQpr~czoPV2Li+{@dcA+*ZpnY3{67)@nDA-IaeC}Hc&G7r z>^cPU9w6URXg@N+cNE`6XxAa+$BXYTEEf(H+VzNh6U5tf3BFSNOd)@Bv)+Zm<-#k4 zD}`%>w+PvDhj~o0a}GA+6KYvtIb9aHEj#bWHyr z;j6+ogfvt$-M#?>(o9YMU?C0DJ22LVI51W$sU$ z0ZaGyFW-5X-`~gC_pkM@Nau5^u5bQ0t!u5dTDsOf2V?26$MrC`S9NgXMe#3QHw*P$Aj_t3`TEG2?MLV{?wkSMd8FFky zj%CQP5jm1Oi}9^raq6W_J;E+!UCa30US7=(ti2NUW{HS>+ z|HXzkLw3ODZ)fqE4s*?A9p+y^E|Ft5Xd>?wa;cm(fMhe$y{rdI<(XqY`WTPy`^?99 zya|%LBa{6{qrOBcuQe~1F#mFD$WOiCfIjgYKG3iR%TdUeo4O0zyznrH!c(yc?Bfbz znEy2jhwyQnM$B(Sb|~4&Wap3_b{WX45F2bEJA&*zhz)IWLt8k7-4s~3hm2(_frWd> z*aeP-d&t=9!9q`+?vQptLBWXyNi=OT?ioo*j>|De@|;ufHkI25`AOuJgdbz!l!moE z9NaB-K!}$Z&Tup@{wR=v*MKn0$kBxHPD+@9XzQqupoT0TgHtdvqhJgbxQu+PMPU>u zcn1hf-TPZ8-lXy-kaUX25lRs8Efj%IPJ9a$u4OIMr4OJ;jzL5X1U^XZ11J)1XPCnR zAKrH3V_6bn8Zjq$cgRtPtR+dsT(JaTp&7RJe8(y!#CC|tJ`~wWDm$O#7O1fUA{Q+o zb~Ac@KEMK1bVNk@aH7(Am=;`BB-scq@Brc=&f6>B=Vnn8{4Q`)YvZQ-n2VbH3ZJMP zls>a_=h9WuWf%7ruMW2&%p zx31m0mi9a|-Raz^RSQm-I(J@m7XHK3!bI#ciPG2y` z<|d2JQMSK1%Rb!L>{{IxX`VD`0qoN@H<`COa%%IvS1ryg4U%cbTAyY(q5Gp9@(J$J#p zsg)D)A%*{9L|@jp-Hd9a=J_+vo>Mt3ZS`7p)8;OiGP^Rf%C*b1sIvOPs>;u>t(BdX z5A0O>6%{T^E>G|Q{0ZhXV_eD z?Y>nU|7qA**(Pic7ue#NP#+sBZKG_H8HlxPtnLwBdrmWU)d(Ne&dTeC_R8+U-ok#u zlZC^DV}z51+&7lzy-%dSgUEZAc&+dT;n#$>3-1;_EPR}Z`{)Vb(?ncQo0R?s@ms~e zA^t7#yTyMX-o~w?yxFUO?a`prcdW2Xi0rlO3+y+zA3T4=w6LA<7-45&523Xm^7j)z zP{=-+dPWH+3oC`Qg}nKh&+OK~i^TJ1F6Gwu3-tED!Zp9pczlgA_Tc{yZ7{{e literal 0 HcmV?d00001 diff --git a/STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c b/STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c new file mode 100644 index 0000000..4988991 --- /dev/null +++ b/STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file startup_stm32f4xx.s + * @author Coocox + * @version V1.0 + * @date 03/05/2012 + * @brief STM32F4xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM324xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + +/* Some modifications by Andy Uribe CA6JAU : +- Added C++ global constructors support +- Changed initial stack pointer +*/ + +/*----------Macro definition--------------------------------------------------*/ +#define WEAK __attribute__ ((weak)) + +/*----------Declaration of the default fault handlers-------------------------*/ +/* System exception vector handler */ +__attribute__ ((used)) +void WEAK Reset_Handler(void); +void WEAK NMI_Handler(void); +void WEAK HardFault_Handler(void); +void WEAK MemManage_Handler(void); +void WEAK BusFault_Handler(void); +void WEAK UsageFault_Handler(void); +void WEAK SVC_Handler(void); +void WEAK DebugMon_Handler(void); +void WEAK PendSV_Handler(void); +void WEAK SysTick_Handler(void); + +void WEAK WWDG_IRQHandler(void); +void WEAK PVD_IRQHandler(void); +void WEAK TAMP_STAMP_IRQHandler(void); +void WEAK RTC_WKUP_IRQHandler(void); +void WEAK FLASH_IRQHandler(void); +void WEAK RCC_IRQHandler(void); +void WEAK EXTI0_IRQHandler(void); +void WEAK EXTI1_IRQHandler(void); +void WEAK EXTI2_IRQHandler(void); +void WEAK EXTI3_IRQHandler(void); +void WEAK EXTI4_IRQHandler(void); +void WEAK DMA1_Stream0_IRQHandler(void); +void WEAK DMA1_Stream1_IRQHandler(void); +void WEAK DMA1_Stream2_IRQHandler(void); +void WEAK DMA1_Stream3_IRQHandler(void); +void WEAK DMA1_Stream4_IRQHandler(void); +void WEAK DMA1_Stream5_IRQHandler(void); +void WEAK DMA1_Stream6_IRQHandler(void); +void WEAK ADC_IRQHandler(void); +void WEAK CAN1_TX_IRQHandler(void); +void WEAK CAN1_RX0_IRQHandler(void); +void WEAK CAN1_RX1_IRQHandler(void); +void WEAK CAN1_SCE_IRQHandler(void); +void WEAK EXTI9_5_IRQHandler(void); +void WEAK TIM1_BRK_TIM9_IRQHandler(void); +void WEAK TIM1_UP_TIM10_IRQHandler(void); +void WEAK TIM1_TRG_COM_TIM11_IRQHandler(void); +void WEAK TIM1_CC_IRQHandler(void); +void WEAK TIM2_IRQHandler(void); +void WEAK TIM3_IRQHandler(void); +void WEAK TIM4_IRQHandler(void); +void WEAK I2C1_EV_IRQHandler(void); +void WEAK I2C1_ER_IRQHandler(void); +void WEAK I2C2_EV_IRQHandler(void); +void WEAK I2C2_ER_IRQHandler(void); +void WEAK SPI1_IRQHandler(void); +void WEAK SPI2_IRQHandler(void); +void WEAK USART1_IRQHandler(void); +void WEAK USART2_IRQHandler(void); +void WEAK USART3_IRQHandler(void); +void WEAK EXTI15_10_IRQHandler(void); +void WEAK RTC_Alarm_IRQHandler(void); +void WEAK OTG_FS_WKUP_IRQHandler(void); +void WEAK TIM8_BRK_TIM12_IRQHandler(void); +void WEAK TIM8_UP_TIM13_IRQHandler(void); +void WEAK TIM8_TRG_COM_TIM14_IRQHandler(void); +void WEAK TIM8_CC_IRQHandler(void); +void WEAK DMA1_Stream7_IRQHandler(void); +void WEAK FSMC_IRQHandler(void); +void WEAK SDIO_IRQHandler(void); +void WEAK TIM5_IRQHandler(void); +void WEAK SPI3_IRQHandler(void); +void WEAK UART4_IRQHandler(void); +void WEAK UART5_IRQHandler(void); +void WEAK TIM6_DAC_IRQHandler(void); +void WEAK TIM7_IRQHandler(void); +void WEAK DMA2_Stream0_IRQHandler(void); +void WEAK DMA2_Stream1_IRQHandler(void); +void WEAK DMA2_Stream2_IRQHandler(void); +void WEAK DMA2_Stream3_IRQHandler(void); +void WEAK DMA2_Stream4_IRQHandler(void); +void WEAK ETH_IRQHandler(void); +void WEAK ETH_WKUP_IRQHandler(void); +void WEAK CAN2_TX_IRQHandler(void); +void WEAK CAN2_RX0_IRQHandler(void); +void WEAK CAN2_RX1_IRQHandler(void); +void WEAK CAN2_SCE_IRQHandler(void); +void WEAK OTG_FS_IRQHandler(void); +void WEAK DMA2_Stream5_IRQHandler(void); +void WEAK DMA2_Stream6_IRQHandler(void); +void WEAK DMA2_Stream7_IRQHandler(void); +void WEAK USART6_IRQHandler(void); +void WEAK I2C3_EV_IRQHandler(void); +void WEAK I2C3_ER_IRQHandler(void); +void WEAK OTG_HS_EP1_OUT_IRQHandler(void); +void WEAK OTG_HS_EP1_IN_IRQHandler(void); +void WEAK OTG_HS_WKUP_IRQHandler(void); +void WEAK OTG_HS_IRQHandler(void); +void WEAK DCMI_IRQHandler(void); +void WEAK CRYP_IRQHandler(void); +void WEAK HASH_RNG_IRQHandler(void); +void WEAK FPU_IRQHandler(void); + +/*----------Symbols defined in linker script----------------------------------*/ +extern unsigned long _estack; /*!< The initial stack pointer */ +extern unsigned long _sidata; /*!< Start address for the initialization + values of the .data section. */ +extern unsigned long _sdata; /*!< Start address for the .data section */ +extern unsigned long _edata; /*!< End address for the .data section */ +extern unsigned long _sbss; /*!< Start address for the .bss section */ +extern unsigned long _ebss; /*!< End address for the .bss section */ + +/* C++ global constructors support */ +extern unsigned long __preinit_array_start; +extern unsigned long __preinit_array_end; +extern unsigned long __init_array_start; +extern unsigned long __init_array_end; + +/*----------Function prototypes-----------------------------------------------*/ +extern int main(void); /*!< The entry point for the application. */ +//extern void SystemInit(void); /*!< Setup the microcontroller system(CMSIS) */ +void Default_Reset_Handler(void); /*!< Default reset handler */ +static void Default_Handler(void); /*!< Default exception handler */ +static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline)); + +/** + *@brief The minimal vector table for a Cortex M3. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address + * 0x00000000. + */ +__attribute__ ((used,section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + /*----------Core Exceptions------------------------------------------------ */ + (void *) &_estack, /*!< The initial stack pointer */ + Reset_Handler, /*!< Reset Handler */ + NMI_Handler, /*!< NMI Handler */ + HardFault_Handler, /*!< Hard Fault Handler */ + MemManage_Handler, /*!< MPU Fault Handler */ + BusFault_Handler, /*!< Bus Fault Handler */ + UsageFault_Handler, /*!< Usage Fault Handler */ + 0,0,0,0, /*!< Reserved */ + SVC_Handler, /*!< SVCall Handler */ + DebugMon_Handler, /*!< Debug Monitor Handler */ + 0, /*!< Reserved */ + PendSV_Handler, /*!< PendSV Handler */ + SysTick_Handler, /*!< SysTick Handler */ + + /*----------External Exceptions---------------------------------------------*/ + WWDG_IRQHandler, /*!< 0: Window WatchDog */ + PVD_IRQHandler, /*!< 1: PVD through EXTI Line detection */ + TAMP_STAMP_IRQHandler, /*!< 2: Tamper and TimeStamps through the EXTI line*/ + RTC_WKUP_IRQHandler, /*!< 3: RTC Wakeup through the EXTI line */ + FLASH_IRQHandler, /*!< 4: FLASH */ + RCC_IRQHandler , /*!< 5: RCC */ + EXTI0_IRQHandler, /*!< 6: EXTI Line0 */ + EXTI1_IRQHandler, /*!< 7: EXTI Line1 */ + EXTI2_IRQHandler, /*!< 8: EXTI Line2 */ + EXTI3_IRQHandler, /*!< 9: EXTI Line3 */ + EXTI4_IRQHandler, /*!< 10: EXTI Line4 */ + DMA1_Stream0_IRQHandler, /*!< 11: DMA1 Stream 0 */ + DMA1_Stream1_IRQHandler, /*!< 12: DMA1 Stream 1 */ + DMA1_Stream2_IRQHandler, /*!< 13: DMA1 Stream 2 */ + DMA1_Stream3_IRQHandler, /*!< 14: DMA1 Stream 3 */ + DMA1_Stream4_IRQHandler, /*!< 15: DMA1 Stream 4 */ + DMA1_Stream5_IRQHandler, /*!< 16: DMA1 Stream 5 */ + DMA1_Stream6_IRQHandler, /*!< 17: DMA1 Stream 6 */ + ADC_IRQHandler, /*!< 18: ADC1, ADC2 and ADC3s */ + CAN1_TX_IRQHandler, /*!< 19: CAN1 TX */ + CAN1_RX0_IRQHandler, /*!< 20: CAN1 RX0 */ + CAN1_RX1_IRQHandler, /*!< 21: CAN1 RX1 */ + CAN1_SCE_IRQHandler, /*!< 22: CAN1 SCE */ + EXTI9_5_IRQHandler, /*!< 23: External Line[9:5]s */ + TIM1_BRK_TIM9_IRQHandler, /*!< 24: TIM1 Break and TIM9 */ + TIM1_UP_TIM10_IRQHandler, /*!< 25: TIM1 Update and TIM10 */ + TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/ + TIM1_CC_IRQHandler, /*!< 27: TIM1 Capture Compare */ + TIM2_IRQHandler, /*!< 28: TIM2 */ + TIM3_IRQHandler, /*!< 29: TIM3 */ + TIM4_IRQHandler, /*!< 30: TIM4 */ + I2C1_EV_IRQHandler, /*!< 31: I2C1 Event */ + I2C1_ER_IRQHandler, /*!< 32: I2C1 Error */ + I2C2_EV_IRQHandler, /*!< 33: I2C2 Event */ + I2C2_ER_IRQHandler, /*!< 34: I2C2 Error */ + SPI1_IRQHandler, /*!< 35: SPI1 */ + SPI2_IRQHandler, /*!< 36: SPI2 */ + USART1_IRQHandler, /*!< 37: USART1 */ + USART2_IRQHandler, /*!< 38: USART2 */ + USART3_IRQHandler, /*!< 39: USART3 */ + EXTI15_10_IRQHandler, /*!< 40: External Line[15:10]s */ + RTC_Alarm_IRQHandler, /*!< 41: RTC Alarm (A and B) through EXTI Line */ + OTG_FS_WKUP_IRQHandler, /*!< 42: USB OTG FS Wakeup through EXTI line */ + TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12 */ + TIM8_UP_TIM13_IRQHandler, /*!< 44: TIM8 Update and TIM13 */ + TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/ + TIM8_CC_IRQHandler, /*!< 46: TIM8 Capture Compare */ + DMA1_Stream7_IRQHandler, /*!< 47: DMA1 Stream7 */ + FSMC_IRQHandler, /*!< 48: FSMC */ + SDIO_IRQHandler, /*!< 49: SDIO */ + TIM5_IRQHandler, /*!< 50: TIM5 */ + SPI3_IRQHandler, /*!< 51: SPI3 */ + UART4_IRQHandler, /*!< 52: UART4 */ + UART5_IRQHandler, /*!< 53: UART5 */ + TIM6_DAC_IRQHandler, /*!< 54: TIM6 and DAC1&2 underrun errors */ + TIM7_IRQHandler, /*!< 55: TIM7 */ + DMA2_Stream0_IRQHandler, /*!< 56: DMA2 Stream 0 */ + DMA2_Stream1_IRQHandler, /*!< 57: DMA2 Stream 1 */ + DMA2_Stream2_IRQHandler, /*!< 58: DMA2 Stream 2 */ + DMA2_Stream3_IRQHandler, /*!< 59: DMA2 Stream 3 */ + DMA2_Stream4_IRQHandler, /*!< 60: DMA2 Stream 4 */ + ETH_IRQHandler, /*!< 61: Ethernet */ + ETH_WKUP_IRQHandler, /*!< 62: Ethernet Wakeup through EXTI line */ + CAN2_TX_IRQHandler, /*!< 63: CAN2 TX */ + CAN2_RX0_IRQHandler, /*!< 64: CAN2 RX0 */ + CAN2_RX1_IRQHandler, /*!< 65: CAN2 RX1 */ + CAN2_SCE_IRQHandler, /*!< 66: CAN2 SCE */ + OTG_FS_IRQHandler, /*!< 67: USB OTG FS */ + DMA2_Stream5_IRQHandler, /*!< 68: DMA2 Stream 5 */ + DMA2_Stream6_IRQHandler, /*!< 69: DMA2 Stream 6 */ + DMA2_Stream7_IRQHandler, /*!< 70: DMA2 Stream 7 */ + USART6_IRQHandler, /*!< 71: USART6 */ + I2C3_EV_IRQHandler, /*!< 72: I2C3 event */ + I2C3_ER_IRQHandler, /*!< 73: I2C3 error */ + OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out */ + OTG_HS_EP1_IN_IRQHandler, /*!< 75: USB OTG HS End Point 1 In */ + OTG_HS_WKUP_IRQHandler, /*!< 76: USB OTG HS Wakeup through EXTI */ + OTG_HS_IRQHandler, /*!< 77: USB OTG HS */ + DCMI_IRQHandler, /*!< 53: DCMI */ + CRYP_IRQHandler, /*!< 53: CRYP crypto */ + HASH_RNG_IRQHandler, /*!< 53: Hash and Rng */ + FPU_IRQHandler /*!< 53: FPU */ + +}; + +/* C++ global constructors support */ +static void call_constructors(unsigned long *start, unsigned long *end) +{ + unsigned long *i; + void (*funcptr)(); + for ( i = start; i < end; i++) + { + funcptr=(void (*)())(*i); + funcptr(); + } +} + + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None + */ +void Default_Reset_Handler(void) +{ + /* Initialize data and bss */ + unsigned long *pulSrc, *pulDest; + + /* Copy the data segment initializers from flash to SRAM */ + pulSrc = &_sidata; + + for(pulDest = &_sdata; pulDest < &_edata; ) + { + *(pulDest++) = *(pulSrc++); + } + + /* Zero fill the bss segment. This is done with inline assembly since this + will clear the value of pulDest if it is not kept in a register. */ + __asm(" ldr r0, =_sbss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); +#ifdef __FPU_USED + /* Enable FPU.*/ + __asm(" LDR.W R0, =0xE000ED88\n" + " LDR R1, [R0]\n" + " ORR R1, R1, #(0xF << 20)\n" + " STR R1, [R0]"); +#endif + + SystemInit(); + + //Call C++ global constructors + call_constructors(&__preinit_array_start, &__preinit_array_end); + call_constructors(&__init_array_start, &__init_array_end); + + /* Call the application's entry point.*/ + main(); +} + + +/** + *@brief Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + */ +#pragma weak Reset_Handler = Default_Reset_Handler +#pragma weak NMI_Handler = Default_Handler +#pragma weak HardFault_Handler = Default_Handler +#pragma weak MemManage_Handler = Default_Handler +#pragma weak BusFault_Handler = Default_Handler +#pragma weak UsageFault_Handler = Default_Handler +#pragma weak SVC_Handler = Default_Handler +#pragma weak DebugMon_Handler = Default_Handler +#pragma weak PendSV_Handler = Default_Handler +#pragma weak SysTick_Handler = Default_Handler + +#pragma weak WWDG_IRQHandler = Default_Handler +#pragma weak PVD_IRQHandler = Default_Handler +#pragma weak TAMP_STAMP_IRQHandler = Default_Handler +#pragma weak RTC_WKUP_IRQHandler = Default_Handler +#pragma weak FLASH_IRQHandler = Default_Handler +#pragma weak RCC_IRQHandler = Default_Handler +#pragma weak EXTI0_IRQHandler = Default_Handler +#pragma weak EXTI1_IRQHandler = Default_Handler +#pragma weak EXTI2_IRQHandler = Default_Handler +#pragma weak EXTI3_IRQHandler = Default_Handler +#pragma weak EXTI4_IRQHandler = Default_Handler +#pragma weak DMA1_Stream0_IRQHandler = Default_Handler +#pragma weak DMA1_Stream1_IRQHandler = Default_Handler +#pragma weak DMA1_Stream2_IRQHandler = Default_Handler +#pragma weak DMA1_Stream3_IRQHandler = Default_Handler +#pragma weak DMA1_Stream4_IRQHandler = Default_Handler +#pragma weak DMA1_Stream5_IRQHandler = Default_Handler +#pragma weak DMA1_Stream6_IRQHandler = Default_Handler +#pragma weak ADC_IRQHandler = Default_Handler +#pragma weak CAN1_TX_IRQHandler = Default_Handler +#pragma weak CAN1_RX0_IRQHandler = Default_Handler +#pragma weak CAN1_RX1_IRQHandler = Default_Handler +#pragma weak CAN1_SCE_IRQHandler = Default_Handler +#pragma weak EXTI9_5_IRQHandler = Default_Handler +#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler +#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler +#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler +#pragma weak TIM1_CC_IRQHandler = Default_Handler +#pragma weak TIM2_IRQHandler = Default_Handler +#pragma weak TIM3_IRQHandler = Default_Handler +#pragma weak TIM4_IRQHandler = Default_Handler +#pragma weak I2C1_EV_IRQHandler = Default_Handler +#pragma weak I2C1_ER_IRQHandler = Default_Handler +#pragma weak I2C2_EV_IRQHandler = Default_Handler +#pragma weak I2C2_ER_IRQHandler = Default_Handler +#pragma weak SPI1_IRQHandler = Default_Handler +#pragma weak SPI2_IRQHandler = Default_Handler +#pragma weak USART1_IRQHandler = Default_Handler +#pragma weak USART2_IRQHandler = Default_Handler +#pragma weak USART3_IRQHandler = Default_Handler +#pragma weak EXTI15_10_IRQHandler = Default_Handler +#pragma weak RTC_Alarm_IRQHandler = Default_Handler +#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler +#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler +#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler +#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler +#pragma weak TIM8_CC_IRQHandler = Default_Handler +#pragma weak DMA1_Stream7_IRQHandler = Default_Handler +#pragma weak FSMC_IRQHandler = Default_Handler +#pragma weak SDIO_IRQHandler = Default_Handler +#pragma weak TIM5_IRQHandler = Default_Handler +#pragma weak SPI3_IRQHandler = Default_Handler +#pragma weak UART4_IRQHandler = Default_Handler +#pragma weak UART5_IRQHandler = Default_Handler +#pragma weak TIM6_DAC_IRQHandler = Default_Handler +#pragma weak TIM7_IRQHandler = Default_Handler +#pragma weak DMA2_Stream0_IRQHandler = Default_Handler +#pragma weak DMA2_Stream1_IRQHandler = Default_Handler +#pragma weak DMA2_Stream2_IRQHandler = Default_Handler +#pragma weak DMA2_Stream3_IRQHandler = Default_Handler +#pragma weak DMA2_Stream4_IRQHandler = Default_Handler +#pragma weak ETH_IRQHandler = Default_Handler +#pragma weak ETH_WKUP_IRQHandler = Default_Handler +#pragma weak CAN2_TX_IRQHandler = Default_Handler +#pragma weak CAN2_RX0_IRQHandler = Default_Handler +#pragma weak CAN2_RX1_IRQHandler = Default_Handler +#pragma weak CAN2_SCE_IRQHandler = Default_Handler +#pragma weak OTG_FS_IRQHandler = Default_Handler +#pragma weak DMA2_Stream5_IRQHandler = Default_Handler +#pragma weak DMA2_Stream6_IRQHandler = Default_Handler +#pragma weak DMA2_Stream7_IRQHandler = Default_Handler +#pragma weak USART6_IRQHandler = Default_Handler +#pragma weak I2C3_EV_IRQHandler = Default_Handler +#pragma weak I2C3_ER_IRQHandler = Default_Handler +#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler +#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler +#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler +#pragma weak OTG_HS_IRQHandler = Default_Handler +#pragma weak DCMI_IRQHandler = Default_Handler +#pragma weak CRYP_IRQHandler = Default_Handler +#pragma weak HASH_RNG_IRQHandler = Default_Handler +#pragma weak FPU_IRQHandler = Default_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, + * preserving the system state for examination by a debugger. + * @param None + * @retval None + */ +static void Default_Handler(void) +{ + /* Go into an infinite loop. */ + while (1) + { + } +} + +/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/ diff --git a/STM32F4XX_Lib/Device/stm32f4xx.h b/STM32F4XX_Lib/Device/stm32f4xx.h new file mode 100644 index 0000000..92431db --- /dev/null +++ b/STM32F4XX_Lib/Device/stm32f4xx.h @@ -0,0 +1,11849 @@ +/** + ****************************************************************************** + * @file stm32f4xx.h + * @author MCD Application Team + * @version V1.7.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F4xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripherals registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ + !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F446xx) && !defined(STM32F469_479xx) + /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, + STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, + STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + + /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, + STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ + + /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, + STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, + STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, + STM32F439IG and STM32F439II Devices */ + + /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC, + STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ + + /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */ + + /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + + /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ, + STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT, + STM32F412REY and STM32F412RGY Devices */ + + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC + and STM32F446ZE Devices */ + + /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG, + STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */ + +#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F446xx && STM32F469_479xx */ + +/* Old STM32F40XX definition, maintained for legacy purpose */ +#ifdef STM32F40XX + #define STM32F40_41xxx +#endif /* STM32F40XX */ + +/* Old STM32F427X definition, maintained for legacy purpose */ +#ifdef STM32F427X + #define STM32F427_437xx +#endif /* STM32F427X */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ + !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F446xx) && !defined(STM32F469_479xx) + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F446xx && STM32F469_479xx */ + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER */ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \ + defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) + #if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #endif /* HSE_VALUE */ +#elif defined (STM32F412xG) || defined(STM32F446xx) + #if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* HSE_VALUE */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F4XX Standard Peripherals Library version number V1.7.0 + */ +#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F4XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + +#if defined(STM32F40_41xxx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +#endif /* STM32F40_41xxx */ + +#if defined(STM32F427_437xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F427_437xx */ + +#if defined(STM32F429_439xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F429_439xx */ + +#if defined(STM32F410xx) + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ + FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */ + LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */ +#endif /* STM32F410xx */ + +#if defined(STM32F401xx) || defined(STM32F411xE) + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ +#if defined(STM32F401xx) + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ +#endif /* STM32F411xE */ +#if defined(STM32F411xE) + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +#endif /* STM32F411xE */ +#endif /* STM32F401xx || STM32F411xE */ + +#if defined(STM32F469_479xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */ + DSI_IRQn = 92 /*!< DSI global Interrupt */ +#endif /* STM32F469_479xx */ + +#if defined(STM32F446xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ + CEC_IRQn = 93, /*!< QuadSPI global Interrupt */ + SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */ + FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */ +#endif /* STM32F446xx */ + +#if defined(STM32F412xG) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ + FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */ +#endif /* STM32F412xG */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +#if defined(STM32F446xx) +/** + * @brief Consumer Electronics Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; +#endif /* STM32F446xx */ + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +#if defined(STM32F412xG) +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +#endif /* STM32F412xG */ +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +#if defined(STM32F469_479xx) +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED9; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ + uint32_t RESERVED10; /*!< Reserved, 0x42C */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ +} DSI_TypeDef; +#endif /* STM32F469_479xx */ + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +#if defined (STM32F410xx) || defined(STM32F412xG) + uint32_t RESERVED; /*!< Reserved, 0x18 */ + uint32_t CFGR2; /*!< Reserved, 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ + __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */ +#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F412xG || STM32F446xx || STM32F469_479xx */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +#endif /* STM32F410xx */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ + uint16_t RESERVED9; /*!< Reserved, 0x26 */ +} I2C_TypeDef; + +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ +}FMPI2C_TypeDef; +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG and STM32F446xx devices */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG and STM32F446xx devices */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +#if defined(STM32F446xx) +/** + * @brief SPDIFRX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + uint16_t RESERVED1; /*!< Reserved, 0x0E */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint16_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; +#endif /* STM32F446xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief QUAD Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F446xx) +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + uint16_t RESERVED1; /*!< Reserved, 0x0E */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint16_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIF_TypeDef; +#endif /* STM32F446xx */ + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +#if defined(STM32F410xx) +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; +#endif /* STM32F410xx */ +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */ +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#if defined(STM32F410xx) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400) +#endif /* STM32F410xx */ +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#if defined(STM32F446xx) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000) +#endif /* STM32F446xx */ +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000) +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#if defined(STM32F446xx) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00) +#endif /* STM32F446xx */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#if defined(STM32F446xx) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) +#endif /* STM32F446xx */ +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) +#if defined(STM32F469_479xx) +#define DSI_BASE (APB2PERIPH_BASE + 0x6C00) +#endif /* STM32F469_479xx */ +#if defined(STM32F412xG) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) +#define DFSDM0 ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1 ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE) +#endif /* STM32F412xG */ + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#if defined(STM32F446xx) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#endif /* STM32F446xx */ +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE) +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ +#if defined(STM32F410xx) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#endif /* STM32F410xx */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#if defined(STM32F446xx) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#endif /* STM32F446xx */ +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#if defined(STM32F446xx) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#endif /* STM32F446xx */ +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#if defined(STM32F469_479xx) +#define DSI ((DSI_TypeDef *)DSI_BASE) +#endif /* STM32F469_479xx */ +#if defined(STM32F412xG) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Filter0 ((DFSDM_TypeDef *) DFSDM_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_TypeDef *) DFSDM_Filter1_BASE) +#endif /* STM32F412xG */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2016 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_CONF_H +#define __STM32F4xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f4xx_adc.h" +#include "stm32f4xx_dac.h" +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_rcc.h" +#include "stm32f4xx_tim.h" +#include "stm32f4xx_usart.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#ifndef NULL +#define NULL 0 +#endif + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F4xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/Device/system_stm32f4xx.c b/STM32F4XX_Lib/Device/system_stm32f4xx.c new file mode 100644 index 0000000..60838ae --- /dev/null +++ b/STM32F4XX_Lib/Device/system_stm32f4xx.c @@ -0,0 +1,1212 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V1.7.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F4xx devices. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F40xxx/41xxx devices + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | HSE_VALUE + *----------------------------------------------------------------------------- + * PLL_M | (HSE_VALUE/1000000) + *----------------------------------------------------------------------------- + * PLL_N | 336 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 7 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Main regulator output voltage | Scale1 mode + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 5 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + * Supported STM32F446xx devices + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 180000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 180000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | HSE_VALUE + *----------------------------------------------------------------------------- + * PLL_M | (HSE_VALUE/1000000) + *----------------------------------------------------------------------------- + * PLL_N | 360 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 7 + *----------------------------------------------------------------------------- + * PLL_R | NA + *----------------------------------------------------------------------------- + * PLLI2S_M | NA + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_P | NA + *----------------------------------------------------------------------------- + * PLLI2S_Q | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Main regulator output voltage | Scale1 mode + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 5 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + +#include "stm32f4xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/************************* PLL Parameters *************************************/ +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M (HSE_VALUE/1000000) + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 7 + +#if defined(STM32F446xx) +/* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */ +#define PLL_R 7 +#elif defined(STM32F412xG) +#define PLL_R 2 +#else +#endif /* STM32F446xx */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define PLL_N 360 +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 +#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#if defined (STM32F40_41xxx) +#define PLL_N 336 +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 +#endif /* STM32F40_41xxx */ + +#if defined(STM32F401xx) +#define PLL_N 336 +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 4 +#endif /* STM32F401xx */ + +#if defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) +#define PLL_N 400 +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 4 +#endif /* STM32F410xx || STM32F411xE */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + +#if defined(STM32F40_41xxx) + uint32_t SystemCoreClock = 168000000; +#endif /* STM32F40_41xxx */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) + uint32_t SystemCoreClock = 180000000; +#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F401xx) + uint32_t SystemCoreClock = 84000000; +#endif /* STM32F401xx */ + +#if defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) + uint32_t SystemCoreClock = 100000000; +#endif /* STM32F410xx || STM32F401xE || STM32F412xG */ + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; +#if defined(STM32F412xG) || defined(STM32F446xx) + uint32_t pllr = 2; +#endif /* STM32F412xG || STM32F446xx */ + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL P used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } +#elif defined(STM32F410xx) || defined(STM32F411xE) +#if defined(USE_HSE_BYPASS) + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } +#else + if (pllsource == 0) + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } +#endif /* USE_HSE_BYPASS */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; +#if defined(STM32F412xG) || defined(STM32F446xx) + case 0x0C: /* PLL R used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_R + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; + SystemCoreClock = pllvco/pllr; + break; +#endif /* STM32F412xG || STM32F446xx */ + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F446xx)|| defined(STM32F469_479xx) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; +#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F401xx) + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; +#endif /* STM32F401xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); +#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28); +#endif /* STM32F412xG || STM32F446xx */ + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ + PWR->CR |= PWR_CR_ODEN; + while((PWR->CSR & PWR_CSR_ODRDY) == 0) + { + } + PWR->CR |= PWR_CR_ODSWEN; + while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) + { + } + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; +#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F401xx) + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; +#endif /* STM32F401xx */ + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +#elif defined(STM32F410xx) || defined(STM32F411xE) +#if defined(USE_HSE_BYPASS) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE and HSE BYPASS */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +#else /* HSI will be used as PLL clock source */ + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } +#endif /* USE_HSE_BYPASS */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ +} +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) +/** + * @brief Setup the external memory controller. Called in startup_stm32f4xx.s + * before jump to __main + * @param None + * @retval None + */ +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+--------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+--------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | + | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | + | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+ + | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | + | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | + | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+ + | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 | + | | PE15 <-> FMC_D12 | + +------------------+------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcccccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xaaaa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xffff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xcccccccc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaaaaaa; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffffff; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F40_41xxx */ + +/* + Bank1_SRAM2 is configured as follow: + In case of FSMC configuration + NORSRAMTimingStructure.FSMC_AddressSetupTime = 1; + NORSRAMTimingStructure.FSMC_AddressHoldTime = 0; + NORSRAMTimingStructure.FSMC_DataSetupTime = 2; + NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0; + NORSRAMTimingStructure.FSMC_CLKDivision = 0; + NORSRAMTimingStructure.FSMC_DataLatency = 0; + NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure; + + In case of FMC configuration + NORSRAMTimingStructure.FMC_AddressSetupTime = 1; + NORSRAMTimingStructure.FMC_AddressHoldTime = 0; + NORSRAMTimingStructure.FMC_DataSetupTime = 2; + NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0; + NORSRAMTimingStructure.FMC_CLKDivision = 0; + NORSRAMTimingStructure.FMC_DataLatency = 0; + NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A; + + FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2; + FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable; + FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM; + FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b; + FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; + FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; + FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; + FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable; + FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; + FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable; + FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable; + FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable; + FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable; + FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly; + FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; + FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure; +*/ + +} +#elif defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external SDRAM mounted on STM324x9I_EVAL board + * This SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001FC; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] = 0x0000000c; + GPIOC->AFR[1] = 0x00007700; + /* Configure PCx pins in Alternate function mode */ + GPIOC->MODER = 0x00a00002; + /* Configure PCx pins speed to 50 MHz */ + GPIOC->OSPEEDR = 0x00a00002; + /* Configure PCx pins Output type to push-pull */ + GPIOC->OTYPER = 0x00000000; + /* No pull-up, pull-down for PCx pins */ + GPIOC->PUPDR = 0x00500000; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xcccccccc; + GPIOF->AFR[1] = 0xcccccccc; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xcccccccc; + GPIOG->AFR[1] = 0xcccccccc; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xaaaaaaaa; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xaaaaaaaa; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000039D0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) & (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) & (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) & (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) & (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +/* + Bank1_SDRAM is configured as follow: + + FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; + FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; + FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; + FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; + FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; + FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; + FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; + + FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK; + FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; + FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; + FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; + FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; + FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; + FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable; + FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; + FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; +*/ + +} +#endif /* DATA_IN_ExtSDRAM && DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/Device/system_stm32f4xx.h b/STM32F4XX_Lib/Device/system_stm32f4xx.h new file mode 100644 index 0000000..fe49bdd --- /dev/null +++ b/STM32F4XX_Lib/Device/system_stm32f4xx.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V1.7.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/MCD-ST Liberty SW License Agreement V2.pdf b/STM32F4XX_Lib/MCD-ST Liberty SW License Agreement V2.pdf new file mode 100644 index 0000000000000000000000000000000000000000..d61f43008d2c9b3d59d4726b09854c0c7933436f GIT binary patch literal 17797 zcmch92RvO%*S8>A^b$hC(Yxc|=)DuYcMgu;OO%M-dnbq%o#=un(M1rVMhl{sh#H;m zkb7@(Z=UCU-uL_7-?z_i|IX~0HM7>5|C*V-X3q?@lDH%@h=l`#`peSLCv@rm#{l0KZ=tXzor>vs+FeP7E~GKQ36-+YrF+uQ+a2*5BfI*ulTW z-LU;fUJxsY{kJ#}2k5srHZb>Zah%}a__DEb{+5>w%=KGdHf|8dKg(lh1@rtC$Hwzp zUUqh_-|}*@{;n@4i2E1aT$~`5Hc%%FG#Fs2FsuM<+(0EK=#v{*xH*6-_VzA-8<_wq zKnXh&Cl3eMBP=`YQO3^99sq)=brTlXU6 zfZ2?V1^G>QI9Rzjpr#xU2-w7ggM$ZR$^izkK~11+JUpflF2Nh*(VSf%PA)$%X2n3G zrj}5YgrN!(#8eq1eCOaxIo3BCibS#8#`lT1*!tLI0Xfr zU7Vm0TMRU0cb(WgOAA*mTuz+efE6)4`yU7v4=~5&+@FTT2_Q_b^;$PirNe| z5e5ddU5)2}2m6%2Ql)r0D)UwWK2w>=9eFy&g%fyJ$5~s6YHp}l;?B|?$5lT2{Q8lD zTviO%g|J>71{%z4|6uxu0pHfu54lxf*8ZpLuuA?zc2yUMohii06sSlyLbS9_$-qeN z?$qsEj@u?XPQWb9Sxlq(tlhwT1)6C|4^#p$gV;G(f$DVLD6evk#lp((43eNPJnu+= z`^QBO)Bv#kY)7{U{t!b6Vh(i%z$^*|o0^9M6etF9f!Nra18)-KAjVJ|X8_l2syx&M zVhT%yRrSsDFQviS%O7Bf+1t55?OdDzY&QV?QQ}QWu;QFx34btBv3G$%1YiZqLrpCq zqW12(H$`&7dJ8TdHhrL&lfA=lkt$GUdsinDn6RK*d4A!4^ZY{_Nf>{aO{l4{!FrA# z5~y(iK!2#G#tC4%l^sUF4Pd(w8>R-#zU@s^p)R^WSmy;)gSxxu10~#Dq+n3EKw*VR zse%A(whVk@@g>Dot$07EFew*b~d0K?o2S3${PD!ec~h&u|9;SOvE6j+ zf2aJfa@_K~>3?sz-^lZ)6l{N$#0``7&)6Hv8|lHYJU^tr3H{&-3;i-A++zDb$3e}~ z7V4}3byKmoh1e;nGK<>VnErb_Ks^5$kDCfnfdT&mkDEUK-~QPC%haFwZuGsW)tmo6 z!B`oEJ>PLOu)ab8efM7%0A4xwM-Gpu`m=(YQ zE9552&HwM_^8>ygls{;1M7Ra&){J06{sPTyTl;^8=HH{j!Tq06`7t*AhRUBR{IIgW z6ouh(6TZRc)<$7f@`Lgx{f|n!N&R7$e^%mO`22y_4FWe6`6qTa<=#}*O*aPuaKl1> zrrc2dK=2l;8+>ou#9w&+)k6N{bqf+qwqO5mLHI-7Kc%~o`X+p1D>va^??2_aN&hqc zhVP%@o3j7p_uu=!De)#3?EcjVZVd4sM)0#61KxCsqBng#GZ@ybGqc0S4G=3g8-Rz0 zTmLpu0b&aU{yO>T!DRxt2}`%Rdc4Fm%I=!r$_%x$2s!4!PUQW9coY2!hcpVjYYKz|#f3VU;K zF|hzD*gM%mY;L18fAHa8W&JrO+yeFA(iQfa$jr{l1sjfFuz*Gcy z*ndlD&c7?o%JuJ+zG?J-*O!~^e^1?NSv>pT!#nRDPLAM|aaR5(b^ng>O|$q#-M`)x zfT|(@Gl-2d6sV~5M?h5`z{!sR5;3PzfaVd zi!73v)yWHA7ki6+Vcscw(p6zeX&#TSo_D}Gwchmkf;p9qn(LUyoB`J+Dul&Ykfg5!Su+O%aPSU38gHNHM>X%D?GkDbS;@H z$mPHtev#t-0%FqAUcPX0ywLVx|Flg1u`gw|OkZH|TT2G$7!B7lsHsA2qI6Uq3|ul( zbFhg$Dg&l{ZcxCY()()1LQAdH2ydmSIIbX$OwfCp``Fb?YCfFMA=xi}ZAFk*cSIHu zIiRq<{n=-OcL86bq3v~&pPvc^S`o?~-6~q9@8<%^`usCZI@)y)wXKwA-=-&Sb_&Q{Xi1^0^s$t5!u7Y<3tbD`qtsPSejWNX0J6!WD184{{&_90UgqQjl*Gb@E zVG%wd31R^8eVvW)%Ay>?J8TAhO#)n(@lQKAEmxRp2+Dzy+|36SCB8A+@ZaZnQ*z9A z?Mx2K_Cy`~QW7Jehux#yigL88!3?;M6T-J=>-`Lltu`y-j=q(+p$AHHUQR!17;>-& zWLKW-=_ho&PH2gL@(yXNDb~r)wBwc7F4$8n~BZY^m_`#)auDgH@ ze&Ib5FMsYQctn8vC}N1k+f+%TJL@@b4>;ZJD_1}TPZ^4PzF4#_pB)&*P9n%Lt_o*g zTY6)zV*%dVhjzVIt9MfjCx5+UIs0CG_db<}&8U^}&XF5JZ$0>{(mPSHijA0&B-uL~ zCM4;340S$zEd|BI;NExTlvsWTX#P9eK?KCIW!%RLC8}jgmC_RsyU=o>ILpyz+Rl4U zTbuUWM;RJ|#aTdl!;%XY4~bphBb z0sFt+zOM=GCEf3@HFopQ5UH}BuOB59A|pBtIz0zszs6*GEKk+(mDAf^{tHC}GL!C8 zV3rDI$Zp-l9B^UyaFMwwLc+0s)O8?saLFtI)a^R5_KaHLlkZH5UJ>QpPZSFNd|?$M zHt&*yqnWTu=t1-0ifv2okz_J4f^rHa_fVw5xl zyV%L7P7j)+XE8D)aEKHgg_o0Tg?q%DnBZhRfW&y`l;)P#tG==k`4AzZEbGdBDbrL` zxcaX4$t$DxD=qD#Ywc#c@KTpn7sY`c7xY=@KtGC!383FyMyBNAT03R@am4lU3b?O| zRbo}4-BtAFa%wEgw!*!DG z6D+QT(~^9uCP;4QT)p8yD*W!uuFP|8M@Ffqu zw^*lSJNnVHEB@B5+EltkqXlWb*Z$hwHU821te=&SH7L^yU*8p|-x81_2kcf9;C)rU z!Z?p~c8Htrz#-HFKS7g!7SqcdSP*jL$*m*4(eMZ~!ArH}`0C31%gDSV4_Wn`{Wfsy z0&Q4~UqsI(|9o!bv4%%9(aHUTk-myefsm^G6O-)!&UYIgQgItI>~6 znMP)!a%VW;nqfVc$XiL~vBG0|fW_u5-RqRA|4e`1ih*wwS9^!!~} zph?{)S^n~+a>kmGv>?Rd-0x%I#4TH|QT_c?&B^3UbmK7PILU;a zD2EUHN406`Y(CH=M_r?B)@(o~WJuJg<;mK}d%D z_rVur9}uz7&9xnnV{2(d1ufOLiv-IMc`c~T1`>3K=M$Jv&o%VYaAZG)SLO;a_-s^Y zJ9fB@1-Wyz9SN=3V$C#9boYkH9I?*6KnY$kyHLHKc{O3EG3n!gtfJi^pgb?kZ-glk zy1L8(UE*^eEIpTKkJ%eoc;X`ehKVyHSwp5|F?p3e;o#CMWi5oV$+Cd^5+_+?0|_@q4G^9S9$;ght0nGi+I%=-fdL!M9D z=4BB7#gyaiG}kXLtpAgVs(2->((>*;S_Rm zf`2%Le>h64zdA~{Ug1wq0VdK9caZxRPvQT@5B!^JbkORU#_&J#5Pmwmf6a#en1#4i z^?!RZ^mf|m7nkBM@8kyO|36cqKOMk7=Cj$^*kPXZZq0`hbOG&9HjxV$~05-QYCoNLPHczmsvx!G!nA!06071sE>_13rCjK9I;gfK=x>f$wiK z@P@$&eENNC%j^nsk&+hZfRMzFK^Ev8%uh8)5@prq_zWjqa+f9IIk~g2^otCKM20ZL zaAb_O6YQh7#qfNqo$I=8?(SAkhN;&Gg(w_T4s?$*@=(8R`0zKXRiKRbzA^wGN|GeC zwGt2@YY0N>vHCrHj~80~`6v+<4yVS#i!V|sMF6Bd4UWaquWy(Xa?se^}{ZOXJMoZLO5 zePDgK5bN0;#DTq^a$PzX#;&~f2Wl?NTp9D#S?ad;miC#8dKm=KLyxQ}gW{{A zjHRU|oNL4a4qjMFlYF;$Is0*+%899Wa^dA+Y;(GBM5(K2RNB(;0_Lj#?_;EJ?;@nl zYr?mHct9edLm0*0|p^C3ESuN$%QFuRn1A2~PHD{HelIWpF%G~PYO8B0nF;0~o{Rgu| zu>kI1XtUUfVxtx zA{G^fBca%iVb6}aI2E362Us^1JW}75?2V)U%upxH0htiq$=ZeYqqJ!5C|m^I&D?5Ex%!H>*Bfx@*jM}mz?;(ybWoffqQ*4*3t6#zC!b;pjUfrra!5L zmB7MX8n_}=pFP5PI1&8F3-m9fM$pQfBb9K8x>QLP#3?Io>6U<_)uxLT3amH+8*#R1 zT@`hcF8GUY9E0^n9ssUJ@$qFPIRTHmlOLZ-yc{YXZ5ksI$?ZkJ#ui4@i|H^3jcAkz zGKPyw@hbfqtI@pP%x!d5DEiih9(kfi8CfRA;1P#+qUD%Z?3_pEd+!f9VmQSu&aDBB zX~)J~3c)7L#8D1G`4vu<`hDRXBp)qI_C7oFqKBW?9TMQyzEqDJjI$3Aj4#17eoxH6 z&bvXe1Z=aJNsic+YE7@)i5_&-;=DH%l=KFfxm@faQ@yK*17hgO*Of+icb6x!YHAfZN8DN?j$VS$PULZI81*=TPwac|)Rj^2wvX02x zrkAlZ#P%fdGO-l{brE^^4W;bvfbk6%X$RSREQKWdN896$AEk3b8?sGf-B}i!&$%7k zHZqZDXmG?6mJvF!2M)fyytng8w@N5DgJe^G^MksZvhc@144#}3H|=J3%rsw?6zHLOlsnLS0snAtD@FgYh3K&N;P3{ z9qCMG&ZfD=@s3UkyO&?ccdCH;A5X)~M&U zW;#oyapXOAP@AfX7ezfa-(t*9y%m~GPhK!)Xe=mFv`1zA7Prpj^qW6F3B&r`%J5;I z?ATQ>{i|Htu4N^MDACYDZ$rh>m)Jom$>Q!dg4Fdb2kw;#j~nfYdxm;b-hTWv5kyt5 zHX{LkXb-@z8h`LY^q$e9e6GCx>2W6n^SmS~LgB%(-DzTuG;M%fgr7_pBFPI=Rqg8w z{&|d{$YD45TuKO}nMM8%r9Gn2m*E74N1c_F2a`H&Z;A}bWdX)C01w-GJzB$bXtho37Tl>eYkLAUe zEvxF@Emm;c121i&Cr=+yCFF!y8Xl_K;UsV{fLudJvr734d6|{+8mNjphNWI?%FFb*slodv{M}$$fIU_|%me%QGA5 zzI-?JkLccS-aLtk|0H#R()XCe$5B^}09u8H z9GhQ-gsjX&o|P!0n&sP}}ONmpoA^gEjku$9f!A;e)mj3P~_n-`ZM z?n#=8A$ez(T)V|8IwAb=Q9`d{-*rN9FqP^e& zM)oAU-ysZ}i>o8r0WqYSZYktxaki(QmA-@czQq-^bK>C5Ys*ha=}VaS^!^~@u`c-A zffRV9^xi_>;+Gg3QuT@ZApG#$$}5)^^9Dfx-7e;_qbZ7u=j^g)U~@GOn<>NOl^)R- z=g%TD*Ay~u{5|l<8#97VP2Z&@WJ;{R3GEAX(7aD5FAQiTrEr)gk-{hAqZPBnh?lr~ zu=h$zx}vTg<%E=-2k6#^iC@0(Ix<6qyDJ>@mWXE=q!Sb8>forEBG|CDQ}|e5o zP0M_%=EM0qXjD^_*voIE2jSDZdK+g;N8I1REw?b_zpebFG57wIe8vOKJN?&9gzy>d z^Btn>_SwReF-w@|8rFzpuGSA?^O()=Sg%YZqu5I%TfFnQz?tFA4&_@aIY&2d$m#iJ zg`8zp{oHf)nvTlaR?0d?1o7k*Aomg8r1EInI^ZH`JP2!YT4GL#2l@V8_V*9M;0f!d z+VD<2#Gd&^HqtCS|Gr@bYz=hJT(y65CYltm>zsDcWDw7=JT1ONN z^)h|iv057~z5Q zbwq6`QpG_TrQw}ub74-Zo4HDKId-1EmM8tPwCblfx420AB6PcZ7)5aPRT0`Mx{)zD_? z+_N)D4?E3EuFaT`ya2sTwq-Q8!U|er#ieH3R?4sEO3l$Eel^d%(zz39^t>>RfqNqp8|#EV-}^BZys>7y6*9%5d#eU&uf;&!LW z8(hgaHp?l`Lhy_X5&FD8L7%g|#}PMKmiuXLR-T{hsxptHm&y^j5(ScAKiKHBOD!t# zp~yPy1)0y=L{9O{QM|?ZGHfN3Y>ArZ;aPJ{;rIGdH)pm4rP;e8=X#DEqn|VB+?i=o zbn1dY*eJgK-dx)>UVas!1%Z^E#(@tUJ$*b&m7lNb1~tngPJUP5dWR2MImM~1w@IWh1%fBGo!jH=M*RD z@w&7TuEs-oqfXU`3Cjm@0q4^JEz1OL@zX*F_q7TYK&w}w9&)w1uAx2k$CJ--2CK#i z%Bk(BpOby6JF_mT+*&y<1f%CYf7$gqAQkhOdQCuRM$UGBp-R<7X=rmPqkqYk&*R<^ z8aL7hT_our+QEAscALg_4DuogpJ;@g1-0`^r+ACRzL<;e#_8Y7VO#3Wx#Lq$IAQEl zZ!Wg{)RK0eYZ2eH^eXmMtH5DWA12P_S&U`+^=n{NZ}sSz3H(E)X2#y#gLeAe@#V)*a8P-UzARXdT84X zgr`sSd0o?_7A}U{OdR=?lhTt%Pf11l+C^K5d8+LxXBi{kMrO_a76O~|N&a;!@~R{g zu@X?20#OT#tC1F8grjvcDHQj>o6*)4nyxYMVDzwcEK)L?x*=!ojy5x*xCRWK7PaaTmMZRyyDNN&fz>yn&nrIL0-{}f}=%z1R z7s$#?#v+>_oAsVsNw~I3T0kj)@Kq9>GSKs$Nj7`n6!RzcK7}Zo!XT}PsrZzwykb;5 z)n;gs2yaDs(wZ4B|Xv`R((AIueeRySC?FXzQ6+`RBCyrt@V$4-3NC>p^&{8y< zU~qC?{t1$^{>1Fow?eqi9<-`u2jlP_O#KX645USPKK6UWG}}+mxRtMqa!U(LHN?dg zFE>n=KcbbVuu3<$XAx|*P@kZFM$yWmhez3bOXv`rx5kuo(fKa;aobq@f{{>*BO^ED;?Om}QT zq@~Ix($)X0wZ!}k6J18X>VpldKQ58iC#epJSw2O&t)j>pIFqsug&~f9NYeiAGZs&% zy2TJIbEnB>R18!1o0<`)FduMDKlN45=4!l~U6nmm=P(TCjc%w$Rls^z*ag{YFCzD) zM5<-}$@V5;Z*bTf&P)%XkEsPtb_6cLj3Y&t?qe@$S9fJRp+H|sdqt2-n!1_Dr^pAJ z)1t<*Cl&<6<*)8ptrcwrC~(mkz4H4u=s#K1F>}4Di|{P5giIVW(?pBEz>I3TDkGH7 z%y80>$f!-c&j9blQfsYtmWJnuTc{l$F*EeN(S&Yhpp^Bo8QtAXBoxvvpI~d9``kr1 z5Aeq{eUr&*hb*%dM&W?S2q#8)oy5q`8D2xAd0$S$*@AL___m_{4N45gPwi_PJ~g{E zDy6;;+9M~)_96;C1M95!b}p(>ZCg}ve!&fXO|&9{H|Ir>Au&pWC#K^a3cg~gf2KVV zo=xf#ZzI(M%fZmWP8;+|y87%pzHJAw=xq6$nl2w)r6cwE*~#zC)#Kp}YHAg7j})Py zyq&RpmUrAhmoCp2WUGbqctI=e8jhNHPa{EZrn*<3unP`+U$4e1QL2pN6&x1o-~Nw_pxa-%f$~!RMTTb>DJUUeC-cQ9W-Jyh{H1f%2qc z!rTyNhmL)(>xF2Cjx@iTn6rIt1aT6Bo=%Ph9`WquNbWJdjuA5ZwL9{6oc%{|+~1!k zinT||-a%76-MeQ@N;ppV{PmnXzfV+2|Da6H*~fg03#US^3AtcH9S-{9S`o}%4x&yi zoG*RU$MgZgiEa-rRe3dWha)uhSN&h{)^1zup{f!W(CopX>@~^}WpUl*adA~ca|Bih z@I0Cn`F7r7(!`bAIY&Dk=NWUwf=9QHr;9Pe-in4RXyyBDAQb6SJe)s`irxXOfAy?c z3sj1}a}@u(_}*lsb0y+Q;Tuu!Bn^hyIXQ(rYRp}D$1c3bA75<8Stcw(k-yYz-8BwM zP~FR2oEreaDKh1xYkh;JVDP5oFXJw}m@23Z=HXrYWC^#&Qo*Pc?&x`NHV2hHg~+=- zuQ$z#5SsTxg6AYKWBq`ZI-D5C&!5x#u$1a@WqHCFt?lzbA%)+1_yAvuvQb{hVef{& zW5&e=(YNC-bQ|fzql|saq#_2)Mlbl(o2X-X)O$uV@iA=w&gvgztu~_1~%U2fVD651dv$90>>nw9gEkK{_F_q$Y=3twsjF0%V)sIH?+ zU}8{;{03P=s7k{%Q?uA5yj4eENB+HaH199X3EsGQwaKUYp_hI$Nkzz^(ccYLD@6AU z56g%ocShKq$Aq&@eNRy;@g8zDybTLL89Ap3o&#r7@3mZ(4~xI|{Rp2zaGLRu)Zq!} z4mM>IQvTdyu;Kjcj-4uV?#oxF>MRnZnMfn6OAu`*O`hXn+vA7!yF+PO6f5=Hy6Iz6 z$yx*~-$GOo#wd9=xOWyz?1*J5yvV6HkuPaDgInl1!goDf9A7G&^{k+hGS-U87&w1$~MPrWX6BRAlJLu@{yUQbk+}meu#>X1MJdFFLmwVMT`biAgOvNclkQg)mc3 z_t!O}aYRrT+uSS?lp(lBN~rL}oA;WsXhc0`ad<2bA1+7?TW)>Zk8e6)1V^bA#7WL8 zBhsS8c?(qbh_l$&Ar1DZ^P!p~Jou7m`JMuYa>(;N5oal5O%_0{DAs|oSXjkA3B82Z zC@zCq(1nap8SH~7xDO8hu8?$>tzSEs@;fn9$;%zitC-=@tXCQ7d~jeeL+C`VOA}Vn zOs5WH5C?y^B_6k14m8QSl#= zpqq3IW}c-)W%MISIq6HJGzO{S!VkQezP=+J+a6fkp6}F%tSqpXRN!Y7 zW?NZxpqOO7ez~CTqJKa8j$du1eGFvewOj9TM1ccu-;2Gpq7p3N$Lbl5{qeI&CR0P9 zC*Nt2;kekbf=hhq7*)MmGX90b`SUBOf~&1FY>&k4mWE%xquxCK@YPg-;y-=Gn^nd? zqQ&f8VJltPfsZXsopo>aH33urw;Kllw;LMtf4Z*DKeONN@A!uc$OYS)b+aAe&rKkI zeg4&wm;31nD&*SpH#W_&OAhxJKEfYHQ8hISmj7CdO2M-d<*WhN#bdLj;1x7W7Wh0L zhPPcg2%AK#_`o*JWUI>d!0nzPkL}5lHs6bZ2|b^AkH{>cw;rXUZPcmHdHP)C$#ayd z^LanIJ+{_dSa@)4mlwOA7Ty|~!JqT|3aHf>!hjK?pMKgmu??Fp@{=2(UP*MvK$EXC zDU4B3diC59ZTgyYdnWLXL+4_zP85r*P4L&PZ#fw66fe&lu{Gyg62Q@kf^6dpMW>H} z5Sqw%E!%>wVWBHznP85dPZ9U_c2->GMes*6N#+=o@=?Kn5kuRPB8B92CDZbz9R4oX zn0fQ1$ClyDSf6s;P-3(vNkKD|RkBrLaEd_OS*?#7#l0T36ggKPA*QLa#!{hBU{Iz- zb=T-=x5s$&bnIQE!}^`Xw${{Z-CFnUS6^8swz(FOQ%;$W8GyLO_lXs*W{%Peo!+;J z7g+?MO0mrl%OmaLh+>}p2ap&>6I@%>crH>)%fNHfvne9i%34xd2@1Y!S&fc z;b}XZ<`-tbDpuKRv_*bn_y98sO0fGOzbNYmFP^K!;I+w;u--4(qtKIwIMRMx)w>f- z87DZdQ;P=Q$ZH89D|hcXNZ3=Rocd!VmuFew!*`rotk?77qFZ*oU8zqfL%~XGDaS`W zI2uDXK~2Ed#D=r=0MDLt(fVac)&^`IuUOti4 ztxo7Vz?saQJr>pY+@^qA@p7j$q+OW-2b%OiF8`F++8zV7Bd*9yxy+V`j3iS%DeunF z@h&csr8&|=oe$%uKGb*W{UwtKbW`;s5*_*Oqu{(sPg1qXZf&KP-7gCd!jb&`Xck3A z`_97M)K*A=+=K9pi+kqZ-DnRs)%(_RHRowji@#^eO6PRH;FG38p$m)C`h0xc9YJ^w zM4;&}E!!u^|3VRWc+&X!UHW##K_AePtF!;^PCE|U8a>uw7Rn@wH3dq7$Y-JGDCa6>Q_U} zeq#R5crSDDH^-Qsu^M^Qr<&2qzd7X~VYJNgR>SFXfCdwK_UmdOyO@w=OBzMV5E;HE z-z>p+#Xg*{Mb-^&qx0frh<{mXq&@ab80)(f3PvlMGkql^rT8X8W8q8!xt`kClDd_=1L6yIrCuiHVaMm%}dR_zWYZ zkd>srV!gR~D$Gt^^K5TKq}DPhtbj%70|c2shWbbbw+jW90!(S{a8|p>mnqTtrZ)#_ zy>Mu7?n6d|n3eKRNjBNHn&$!G`R83DL{}nvD5Y4?D^TIF3wN>?FZlgppNpQ1uo|*_ zoG0ySd_SVy21#$zEaBfRTOUBe=aeF2X?>U#FDcY!Am}n3!6g48MklIzhg`B0?$dllC)PEn7sm*^)^ajw*qO9Ee^ z6t5+C2t2CGBDVP`G1JyJCThIcMCT0GV>Jy4Tcr^UU_pV40?Pe2pRhtgv)(>sK@icd znu(lCe@7V9-L|#>G;yM={4Wy3RFW{9d=)M*M#^#1(0n7^AJNB-`VH4THCFME6|%FY#3JDO zjsyEh{8GKR#+SY`32hx`g_o$vB_GY467>+J?2AIma1Vj#Zd86@-aGb4B=@4T)Po0Z zoG&(?V#cq~k+qEJ@;t(#w&KHHv)VsUtM*}hHuNc^%7SFHssy{lSV@K@FvXp5y{Mz3 zIIlm6G-E6`VNxHwzG*y4C1T%_Gf(Ph)N~(N@le7^R{c#XC0CU2dGjmh?Qjd+9z$8L z501MH=(;H<-5DAffIT@{ebxG9o-&;n-pf*EtwE!RTx>9T4^m4F5+0(Wy?Xqh1weeI zGi7n#@OiaD7uF&*nM8I)>4+N-zFQ!?aubEP@oq)b)m~+k1@vQ+Gr&OB7VRpUK5F^} zvO6C9@+(y0a)+sHxE$Bsw$$Klc?{NkM{J&^HGg=|FZXCs9?wT@jeLZDt3C5m$uV|< z7f`FR)r-s$tZkiE@(*c|Q_vmedW2ek#ws7!u6FujVzo$Xnmf55^Ghg#vuB#r7I{$} zN14@wt=yEt_v3l4E6fujXP0Gt^DmIUcZoc6L|_7+9QBM?4&a1Lrj}nl)XqjcsY=5; zXAChxB%;txyjI^dXot+s+vSEzxc z^Xn&!kOT#Tx`?T=BJMWdOUB`M^Ur|RRUdSyJ`x6aLD_M8O-!D-)e{ZL)JO^$J9-@- zyxxCN0Lf2f_qNU<6X5Asi;A52O4_Hgn~>7HWrx+3@W8Y6V*4PsWXjsj928oXh(*0J zm!3)XxF-?M`CF}~yl~NhSdhO-tJ8JZaQ*P}mVmVK~S;tMv2`!a5n?Dw}WTQ8~i%w-{{fG{=E%%C2@kEJ1s?pTu*qdt=_{ zb3uK$ND6e4I=4#Lx0+w7IL>O#xiY3|4sF&P4#+U;B9zUz7P?gTzU$Wv!yn|+^1MhePc0-P7~)@F85);tl>kDX5>a22)+!gsf)Iajr?il+ik+)A%kjC3z0`z*iL6OQ-&$=|Ls7>{S&J3BrT3Sh!CV^@(Ko z@ZFtv92BN@%lJvILV3t4AB^I@zUp>0=8vqAxZdiQCA#`hq#yBE{UTEPa0Qj%DyUIq zAV2$I_v)c2?(>s;Do2L#&t9y3mC22!rpjN^HUhf#Z> zdPnIT-Aa3(D~4K$@;dTO6d0x}j%2!ecMv%aPSKH~s`JD)nbF66^F!x7$Fxed7~E`*kX{M`aReeL_W z8>4s8aB5ACVDv1fueQ)5g|tOX>P^j^9xn3iSG?J*-JR-R>3ymh8Dur?!fh=M8@>oD zTa+@xOd0Guo_HB+VMn{Oo{t3HC6DNj{`5t?hN!w97T)vNvw95jY|az=`7%FO$dAcO<-K&x0jK~urSj9FhkT`iN+Q0ml> zl-GAtrx+UNHz{16;o%GDebb^ZD}UHeI*LtM9bgaWqY2_}Qk4i$fSb)fXs4Z7fUrr! zaZ76TQ@qJjceXR#%}p?)`@oNq^IeBrqNk&Rn}at|O6JWD*-7BWj7 zLY-tJ;B25EGKy0AT($kc@4RH3K4M2T7%}8uIDEIec7J$Y^7f|Uu>I$B_|Qy6$Sez` z{R_#)hkI&#ivjO1N{@-?VVmTk5En~(yZ@R>&CoVyr~!)9>)HfAF$*qJu++ zmBaJGn$}^6WC1Jjj%VX^VqMcd4sZ55*l7e#_NJ~TP$xPZ{?FKKk=AU)9f&8AdUo_b-OxYIe1IL` z@YfL@H@hV{!C=@S7O)dPZqMjoy*WALpT}Wvg4tj$@Xht}_zzA_4%jEuzsK?LaQu@F zwmtf{V>4iQxY%yawD^
© COPYRIGHT 2016 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f4xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_adc.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_adc.h new file mode 100644 index 0000000..a30564a --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_adc.h @@ -0,0 +1,656 @@ +/** + ****************************************************************************** + * @file stm32f4xx_adc.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_ADC_H +#define __STM32F4xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. + This parameter can be a value of @ref ADC_resolution */ + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion + is performed in Scan (multichannels) + or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion + is performed in Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and + enable the trigger of a regular group. + This parameter can be a value of + @ref ADC_external_trigger_edge_for_regular_channels_conversion */ + uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger + the start of conversion of a regular group. + This parameter can be a value of + @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment + is left or right. This parameter can be + a value of @ref ADC_data_align */ + uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions + that will be done using the sequencer for + regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; + +/** + * @brief ADC Common Init structure definition + */ +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in + independent or multi mode. + This parameter can be a value of @ref ADC_Common_mode */ + uint32_t ADC_Prescaler; /*!< Select the frequency of the clock + to the ADC. The clock is common for all the ADCs. + This parameter can be a value of @ref ADC_Prescaler */ + uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access + mode for multi ADC mode. + This parameter can be a value of + @ref ADC_Direct_memory_access_mode_for_multi_mode */ + uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of + @ref ADC_delay_between_2_sampling_phases */ + +}ADC_CommonInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_Common_mode + * @{ + */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) +#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) +#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) +#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) +#define ADC_DualMode_Interl ((uint32_t)0x00000007) +#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) +#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) +#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) +#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) +#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) +#define ADC_TripleMode_Interl ((uint32_t)0x00000017) +#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_DualMode_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult) || \ + ((MODE) == ADC_DualMode_Interl) || \ + ((MODE) == ADC_DualMode_AlterTrig) || \ + ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_TripleMode_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult) || \ + ((MODE) == ADC_TripleMode_Interl) || \ + ((MODE) == ADC_TripleMode_AlterTrig)) +/** + * @} + */ + + +/** @defgroup ADC_Prescaler + * @{ + */ +#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) +#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) +#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) +#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) +#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ + ((PRESCALER) == ADC_Prescaler_Div4) || \ + ((PRESCALER) == ADC_Prescaler_Div6) || \ + ((PRESCALER) == ADC_Prescaler_Div8)) +/** + * @} + */ + + +/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode + * @{ + */ +#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ +#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ + ((MODE) == ADC_DMAAccessMode_1) || \ + ((MODE) == ADC_DMAAccessMode_2) || \ + ((MODE) == ADC_DMAAccessMode_3)) + +/** + * @} + */ + + +/** @defgroup ADC_delay_between_2_sampling_phases + * @{ + */ +#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) +#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) +#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) +#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) +#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) +#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) +#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) +#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) +#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) +#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) +#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) +#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) +#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) +#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) +#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) +#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) + +/** + * @} + */ + + +/** @defgroup ADC_resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ((uint32_t)0x01000000) +#define ADC_Resolution_8b ((uint32_t)0x02000000) +#define ADC_Resolution_6b ((uint32_t)0x03000000) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) +#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) +#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) +#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) +#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) +/** + * @} + */ + + +/** @defgroup ADC_data_align + * @{ + */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + + +/** @defgroup ADC_channels + * @{ + */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) + +#if defined (STM32F40_41xxx) || defined(STM32F412xG) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */ + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ + ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || \ + ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || \ + ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || \ + ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || \ + ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || \ + ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || \ + ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || \ + ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || \ + ((CHANNEL) == ADC_Channel_17) || \ + ((CHANNEL) == ADC_Channel_18)) +/** + * @} + */ + + +/** @defgroup ADC_sampling_times + * @{ + */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_15Cycles ((uint8_t)0x01) +#define ADC_SampleTime_28Cycles ((uint8_t)0x02) +#define ADC_SampleTime_56Cycles ((uint8_t)0x03) +#define ADC_SampleTime_84Cycles ((uint8_t)0x04) +#define ADC_SampleTime_112Cycles ((uint8_t)0x05) +#define ADC_SampleTime_144Cycles ((uint8_t)0x06) +#define ADC_SampleTime_480Cycles ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ + ((TIME) == ADC_SampleTime_15Cycles) || \ + ((TIME) == ADC_SampleTime_28Cycles) || \ + ((TIME) == ADC_SampleTime_56Cycles) || \ + ((TIME) == ADC_SampleTime_84Cycles) || \ + ((TIME) == ADC_SampleTime_112Cycles) || \ + ((TIME) == ADC_SampleTime_144Cycles) || \ + ((TIME) == ADC_SampleTime_480Cycles)) +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) +#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) +#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) + +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) +#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) +/** + * @} + */ + + +/** @defgroup ADC_injected_channel_selection + * @{ + */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_EOC ((uint16_t)0x0205) +#define ADC_IT_AWD ((uint16_t)0x0106) +#define ADC_IT_JEOC ((uint16_t)0x0407) +#define ADC_IT_OVR ((uint16_t)0x201A) +#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_flags_definition + * @{ + */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define ADC_FLAG_OVR ((uint8_t)0x20) + +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ + ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || \ + ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT) || \ + ((FLAG)== ADC_FLAG_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_offset + * @{ + */ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_length + * @{ + */ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_injected_rank + * @{ + */ +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_rank + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); + +/* Temperature Sensor, Vrefint and VBAT management functions ******************/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +void ADC_VBATCmd(FunctionalState NewState); + +/* Regular Channels Configuration functions ***********************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetMultiModeConversionValue(void); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); + +/* Injected channels Configuration functions **********************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h new file mode 100644 index 0000000..5216c0f --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_dac.h @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file stm32f4xx_dac.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DAC_H +#define __STM32F4xx_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ + +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h new file mode 100644 index 0000000..6f05c37 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_gpio.h @@ -0,0 +1,564 @@ +/** + ****************************************************************************** + * @file stm32f4xx_gpio.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the GPIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_GPIO_H +#define __STM32F4xx_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG) || \ + ((PERIPH) == GPIOH) || \ + ((PERIPH) == GPIOI) || \ + ((PERIPH) == GPIOJ) || \ + ((PERIPH) == GPIOK)) + +/** + * @brief GPIO Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) + +/** + * @brief GPIO Output type enumeration + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + + +/** + * @brief GPIO Output Maximum frequency enumeration + */ +typedef enum +{ + GPIO_Low_Speed = 0x00, /*!< Low speed */ + GPIO_Medium_Speed = 0x01, /*!< Medium speed */ + GPIO_Fast_Speed = 0x02, /*!< Fast speed */ + GPIO_High_Speed = 0x03 /*!< High speed */ +}GPIOSpeed_TypeDef; + +/* Add legacy definition */ +#define GPIO_Speed_2MHz GPIO_Low_Speed +#define GPIO_Speed_25MHz GPIO_Medium_Speed +#define GPIO_Speed_50MHz GPIO_Fast_Speed +#define GPIO_Speed_100MHz GPIO_High_Speed + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ + ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) + +/** + * @brief GPIO Configuration PullUp PullDown enumeration + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#if defined(STM32F446xx) +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#endif /* STM32F446xx */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#if defined(STM32F410xx) +#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */ +#endif /* STM32F410xx */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#if defined(STM32F446xx) +#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ +#endif /* STM32F446xx */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#if defined(STM32F446xx) +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#endif /* STM32F446xx */ +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */ +#endif /* STM32F410xx || STM32F446xx */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */ +#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG Devices) */ +#if defined(STM32F412xG) +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ +#endif /* STM32F412xG */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */ + +/** + * @brief AF 7 selection Legacy + */ +#define GPIO_AF_I2S3ext GPIO_AF7_SPI3 + +/** + * @brief AF 8 selection + */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#if defined(STM32F412xG) +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ +#endif /* STM32F412xG */ +#if defined(STM32F446xx) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ +#endif /* STM32F446xx */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG Devices) */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG Devices) */ +#if defined(STM32F446xx) +#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */ +#endif /* STM32F446xx */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */ +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ +#if defined(STM32F410xx) || defined(STM32F412xG) +#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */ +#endif /* STM32F410xx || STM32F412xG */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ +#if defined(STM32F446xx) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /* STM32F446xx */ +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */ +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ +#if defined(STM32F412xG) +#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */ +#define GPIO_AF10_DFSDM ((uint8_t)0xA) /* DFSDM Alternate Function mapping */ +#endif /* STM32F412xG */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#if defined(STM32F40_41xxx) || defined(STM32F412xG) +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#endif /* STM32F40_41xxx || STM32F412xG */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#if defined(STM32F469_479xx) +#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#endif /* STM32F469_479xx */ +/** + * @brief AF 14 selection + */ +#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#if defined(STM32F40_41xxx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) +#endif /* STM32F40_41xxx */ + +#if defined(STM32F401xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) +#endif /* STM32F401xx */ + +#if defined(STM32F411xE) +#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14)) +#endif /* STM32F411xE */ + +#if defined(STM32F410xx) +#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15)) +#endif /* STM32F410xx */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ + ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ + ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ + ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ + ((AF) == GPIO_AF_LTDC)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined(STM32F412xG) +#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14)) +#endif /* STM32F412xG */ + +#if defined(STM32F446xx) +#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14)) +#endif /* STM32F446xx */ + +#if defined(STM32F469_479xx) +#define IS_GPIO_AF(AF) ((AF) < 16) +#endif /* STM32F469_479xx */ + +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS +#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS +#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the GPIO configuration to the default reset state ****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Alternate functions configuration function ****************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_GPIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h new file mode 100644 index 0000000..15fe00d --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_rcc.h @@ -0,0 +1,982 @@ +/** + ****************************************************************************** + * @file stm32f4xx_rcc.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the RCC firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_RCC_H +#define __STM32F4xx_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Dual_Mode_Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +/** + * @} + */ + +/** @defgroup RCC_PLLSAIDivR_Factor + * @{ + */ +#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) +#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) +#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div16)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#if defined(STM32F446xx) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) +#elif defined(STM32F412xG) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#else +#endif /* STM32F446xx */ +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#if defined(STM32F446xx) || defined(STM32F469_479xx) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#endif /* STM32F446xx || STM32F469_479xx */ +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ + +#if defined(STM32F412xG) || defined(STM32F446xx) +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) +#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) +/* Add legacy definition */ +#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK +#endif /* STM32F446xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source + * @{ + */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00001000) +#define RCC_HCLK_Div4 ((uint32_t)0x00001400) +#define RCC_HCLK_Div8 ((uint32_t)0x00001800) +#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) +#define RCC_IT_CSS ((uint8_t)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) +#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) +#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) +#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) +#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) +#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) +#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) +#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) +#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) +#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) +#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) +#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) +#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) +#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) +#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) +#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) +#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) +#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) +#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) +#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) +#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) +#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) +#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) +#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) +#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) +#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) +#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) +/** + * @} + */ + +#if defined(STM32F410xx) +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) + +#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) +/* Legacy Defines */ +#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE +/** + * @} + */ + +/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source + * @{ + */ +#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) +#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) +#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) +/** + * @} + */ + +#endif /* STM32F410xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) +#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ + ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) +/** + * @} + */ + +/** @defgroup RCC_I2S_APBBus + * @{ + */ +#define RCC_I2SBus_APB1 ((uint8_t)0x00) +#define RCC_I2SBus_APB2 ((uint8_t)0x01) +#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) +/** + * @} + */ +#if defined(STM32F446xx) +/** @defgroup RCC_SAI_Clock_Source + * @{ + */ +#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) +#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) +#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) +#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) + +#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ + ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) +/** + * @} + */ + +/** @defgroup RCC_SAI_Instance + * @{ + */ +#define RCC_SAIInstance_SAI1 ((uint8_t)0x00) +#define RCC_SAIInstance_SAI2 ((uint8_t)0x01) +#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) +/** + * @} + */ +#endif /* STM32F446xx */ +#endif /* STM32F412xG || STM32F446xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) +#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_SAI_BlockA_Clock_Source + * @{ + */ +#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) +#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) + +#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIACLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_SAI_BlockB_Clock_Source + * @{ + */ +#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) +#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) + +#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIBCLKSource_Ext)) +/** + * @} + */ +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ + +/** @defgroup RCC_TIM_PRescaler_Selection + * @{ + */ +#define RCC_TIMPrescDesactivated ((uint8_t)0x00) +#define RCC_TIMPrescActivated ((uint8_t)0x01) + +#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) +/** + * @} + */ + +#if defined(STM32F469_479xx) +/** @defgroup RCC_DSI_Clock_Source_Selection + * @{ + */ +#define RCC_DSICLKSource_PHY ((uint8_t)0x00) +#define RCC_DSICLKSource_PLLR ((uint8_t)0x01) +#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \ + ((CLKSOURCE) == RCC_DSICLKSource_PLLR)) +/** + * @} + */ +#endif /* STM32F469_479xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** @defgroup RCC_SDIO_Clock_Source_Selection + * @{ + */ +#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) +#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) +#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ + ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) +/** + * @} + */ + + +/** @defgroup RCC_48MHZ_Clock_Source_Selection + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F469_479xx) +#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) +#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) +#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ + ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) +#endif /* STM32F446xx || STM32F469_479xx */ +#if defined(STM32F412xG) +#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00) +#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */ +#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \ + ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ)) +#endif /* STM32F412xG */ +/** + * @} + */ +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F446xx) +/** @defgroup RCC_SPDIFRX_Clock_Source_Selection + * @{ + */ +#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) +#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) +#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ + ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) +/** + * @} + */ + +/** @defgroup RCC_CEC_Clock_Source_Selection + * @{ + */ +#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) +#define RCC_CECCLKSource_LSE ((uint8_t)0x01) +#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ + ((CLKSOURCE) == RCC_CECCLKSource_LSE)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_ClockGating + * @{ + */ +#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) +#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) +#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) +#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) +#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) +#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) +#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) + +#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ +#endif /* STM32F446xx */ + +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +/** @defgroup RCC_FMPI2C1_Clock_Source + * @{ + */ +#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) +#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) + +#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) +/** + * @} + */ +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ + +#if defined(STM32F412xG) +/** @defgroup RCC_DFSDM_Clock_Source + * @{ + */ +#define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00) +#define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01) +#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS)) +/** + * @} + */ + +/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) +#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2)) +/** + * @} + */ +#endif /* STM32F412xG */ + +/** @defgroup RCC_AHB1_Peripherals + * @{ + */ +#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) +#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) +#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) +#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) +#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) +#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) +#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) +#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) +#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) +#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) +#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) +#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) +#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) +#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) +#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) +#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) +#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) +#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) +#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) +#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) +#if defined(STM32F410xx) +#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000) +#endif /* STM32F410xx */ +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripherals + * @{ + */ +#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) +#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) +#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) +#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ +#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) +#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripherals + * @{ + */ +#if defined(STM32F40_41xxx) +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F40_41xxx */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) +#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined(STM32F446xx) || defined(STM32F469_479xx) +#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) +#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F412xG) +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F412xG */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#if defined(STM32F410xx) +#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) +#endif /* STM32F410xx */ +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#if defined(STM32F446xx) +#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) +#endif /* STM32F446xx */ +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) +#endif /* STM32F410xx || STM32F446xx */ +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#if defined(STM32F446xx) +#define RCC_APB1Periph_CEC ((uint32_t)0x08000000) +#endif /* STM32F446xx */ +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) +#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) +#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) +#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) +#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) +#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) +#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) +#if defined(STM32F446xx) || defined(STM32F469_479xx) +#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) +#endif /* STM32F446xx || STM32F469_479xx */ +#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) +#if defined(STM32F469_479xx) +#define RCC_APB2Periph_DSI ((uint32_t)0x08000000) +#endif /* STM32F469_479xx */ +#if defined(STM32F412xG) +#define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000) +#endif /* STM32F412xG */ + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) +#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) +#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) +#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) +#define RCC_MCO1Div_1 ((uint32_t)0x00000000) +#define RCC_MCO1Div_2 ((uint32_t)0x04000000) +#define RCC_MCO1Div_3 ((uint32_t)0x05000000) +#define RCC_MCO1Div_4 ((uint32_t)0x06000000) +#define RCC_MCO1Div_5 ((uint32_t)0x07000000) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ + ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) + +#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ + ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ + ((DIV) == RCC_MCO1Div_5)) +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) +#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) +#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) +#define RCC_MCO2Div_1 ((uint32_t)0x00000000) +#define RCC_MCO2Div_2 ((uint32_t)0x20000000) +#define RCC_MCO2Div_3 ((uint32_t)0x28000000) +#define RCC_MCO2Div_4 ((uint32_t)0x30000000) +#define RCC_MCO2Div_5 ((uint32_t)0x38000000) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) + +#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ + ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ + ((DIV) == RCC_MCO2Div_5)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); + +void RCC_PLLCmd(FunctionalState NewState); + +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR); +#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ + +void RCC_PLLI2SCmd(FunctionalState NewState); + +#if defined(STM32F40_41xxx) || defined(STM32F401xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +#endif /* STM32F40_41xxx || STM32F401xx */ +#if defined(STM32F411xE) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); +#endif /* STM32F411xE */ +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ +#if defined(STM32F412xG) || defined(STM32F446xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR); +#endif /* STM32F412xG || STM32F446xx */ + +void RCC_PLLSAICmd(FunctionalState NewState); +#if defined(STM32F469_479xx) +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR); +#endif /* STM32F469_479xx */ +#if defined(STM32F446xx) +void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ); +#endif /* STM32F446xx */ +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ + +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); + +#if defined(STM32F412xG) || defined(STM32F446xx) +void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); +#if defined(STM32F446xx) +void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); +#endif /* STM32F446xx */ +#endif /* STM32F412xG || STM32F446xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ + +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); + +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */ +void RCC_LSEModeConfig(uint8_t RCC_Mode); + +/* Features available only for STM32F469_479xx devices */ +#if defined(STM32F469_479xx) +void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource); +#endif /* STM32F469_479xx */ + +/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */ +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource); +void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource); +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ + +/* Features available only for STM32F446xx devices */ +#if defined(STM32F446xx) +void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState); +void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource); +void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource); +#endif /* STM32F446xx */ + +/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */ +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource); +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ + +/* Features available only for STM32F410xx devices */ +#if defined(STM32F410xx) +void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource); + +void RCC_MCO1Cmd(FunctionalState NewState); +void RCC_MCO2Cmd(FunctionalState NewState); +#endif /* STM32F410xx */ + +#if defined(STM32F412xG) +void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource); +void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource); +#endif /* STM32F412xG */ +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h new file mode 100644 index 0000000..128f6af --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_tim.h @@ -0,0 +1,1150 @@ +/** + ****************************************************************************** + * @file stm32f4xx_tim.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_TIM_H +#define __STM32F4xx_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_State */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + (((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14))) +/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)) +/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) +/* LIST4: TIM1 and TIM8 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) +/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) +/* LIST6: TIM2, TIM5 and TIM11 */ +#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ + ((TIMx) == TIM5) || \ + ((TIMx) == TIM11)) + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_State + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_State + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ + +#define TIM2_TIM8_TRGO ((uint16_t)0x0000) +#define TIM2_ETH_PTP ((uint16_t)0x0400) +#define TIM2_USBFS_SOF ((uint16_t)0x0800) +#define TIM2_USBHS_SOF ((uint16_t)0x0C00) + +#define TIM5_GPIO ((uint16_t)0x0000) +#define TIM5_LSI ((uint16_t)0x0040) +#define TIM5_LSE ((uint16_t)0x0080) +#define TIM5_RTC ((uint16_t)0x00C0) + +#define TIM11_GPIO ((uint16_t)0x0000) +#define TIM11_HSE ((uint16_t)0x0002) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ + ((TIM_REMAP) == TIM2_ETH_PTP)||\ + ((TIM_REMAP) == TIM2_USBFS_SOF)||\ + ((TIM_REMAP) == TIM2_USBHS_SOF)||\ + ((TIM_REMAP) == TIM5_GPIO)||\ + ((TIM_REMAP) == TIM5_LSI)||\ + ((TIM_REMAP) == TIM5_LSE)||\ + ((TIM_REMAP) == TIM5_RTC)||\ + ((TIM_REMAP) == TIM11_GPIO)||\ + ((TIM_REMAP) == TIM11_HSE)) + +/** + * @} + */ +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h new file mode 100644 index 0000000..2199b76 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/include/stm32f4xx_usart.h @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32f4xx_usart.h + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_USART_H +#define __STM32F4xx_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5) || \ + ((PERIPH) == USART6) || \ + ((PERIPH) == UART7) || \ + ((PERIPH) == UART8)) + +#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the USART configuration to the default reset state ***/ +void USART_DeInit(USART_TypeDef* USARTx); + +/* Initialization and Configuration functions *********************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendBreak(USART_TypeDef* USARTx); + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/misc.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/misc.c new file mode 100644 index 0000000..5435ec8 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/misc.c @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * + * @verbatim + * + * =================================================================== + * How to configure Interrupts using driver + * =================================================================== + * + * This section provide functions allowing to configure the NVIC interrupts (IRQ). + * The Cortex-M4 exceptions are managed by CMSIS functions. + * + * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() + * function according to the following table. + + * The table below gives the allowed values of the pre-emption priority and subpriority according + * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + * ========================================================================================================================== + * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + * ========================================================================================================================== + * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + * | | | 4 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + * | | | 3 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + * | | | 2 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + * | | | 1 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + * | | | 0 bits for subpriority + * ========================================================================================================================== + * + * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() + * + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * + * @note IRQ priority order (sorted by highest to lowest priority): + * - Lowest pre-emption priority + * - Lowest subpriority + * - Lowest hardware priority (IRQ number) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c new file mode 100644 index 0000000..63aebac --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_adc.c @@ -0,0 +1,1745 @@ +/** + ****************************************************************************** + * @file stm32f4xx_adc.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and Configuration (in addition to ADC multi mode + * selection) + * + Analog Watchdog configuration + * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT + * management + * + Regular Channels Configuration + * + Regular Channels DMA Configuration + * + Injected channels Configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the ADC interface clock using + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + (++) Configure these ADC pins in analog mode using GPIO_Init(); + + (#) Configure the ADC Prescaler, conversion resolution and data + alignment using the ADC_Init() function. + (#) Activate the ADC peripheral using ADC_Cmd() function. + + *** Regular channels group configuration *** + ============================================ + [..] + (+) To configure the ADC regular channels group features, use + ADC_Init() and ADC_RegularChannelConfig() functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To configurate and activate the Discontinuous mode, use the + ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. + (+) To read the ADC converted values, use the ADC_GetConversionValue() + function. + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Refer to "Regular channels group configuration" description to + configure the ADC1, ADC2 and ADC3 regular channels. + (+) Select the Multi mode ADC regular channels features (dual or + triple mode) using ADC_CommonInit() function and configure + the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() + functions. + (+) Read the ADCs converted values using the + ADC_GetMultiModeConversionValue() function. + + *** DMA for Regular channels group features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for regular channels group, use the + ADC_DMACmd() function. + (+) To enable the generation of DMA requests continuously at the end + of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() + function. + + *** Injected channels group configuration *** + ============================================= + [..] + (+) To configure the ADC Injected channels group features, use + ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() + functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To activate the Injected Discontinuous mode, use the + ADC_InjectedDiscModeCmd() function. + (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() + function. + (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() + function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_adc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) + +/* ADC EXTEN mask */ +#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) + +/* ADC JEXTEN mask */ +#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_SET ((uint32_t)0x0000001F) +#define SQR2_SQ_SET ((uint32_t)0x0000001F) +#define SQR1_SQ_SET ((uint32_t)0x0000001F) + +/* ADC L Mask */ +#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_SET ((uint32_t)0x00300000) +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint32_t)0x00000007) +#define SMPR2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_OFFSET ((uint8_t)0x28) + +/* ADC CDR register base address */ +#define CDR_ADDRESS ((uint32_t)0x40012308) + +/* ADC CCR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC Prescaler + (+) ADC Conversion Resolution (12bit..6bit) + (+) Scan Conversion Mode (multichannel or one channel) for regular group + (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for + regular group + (+) External trigger Edge and source of regular group, + (+) Converted data alignment (left or right) + (+) The number of ADC conversions that will be done using the sequencer for + regular channel group + (+) Multi ADC mode selection + (+) Direct memory access mode selection for multi ADC mode + (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) + (+) Enable or disable the ADC peripheral +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes all ADCs peripherals registers to their default reset + * values. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Enable all ADCs reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); + + /* Release all ADCs from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + + /* Clear RES and SCAN bits */ + tmpreg1 &= CR1_CLEAR_MASK; + + /* Configure ADCx: scan conversion mode and resolution */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + /* Set RES bit according to ADC_Resolution value */ + tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ + ADC_InitStruct->ADC_Resolution); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + + /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_MASK; + + /* Configure ADCx: external trigger event and edge, data alignment and + continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ + ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_ExternalTrigConvEdge | \ + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + + /* Clear L bits */ + tmpreg1 &= SQR1_L_RESET; + + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfConversion value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); + tmpreg1 |= ((uint32_t)tmpreg2 << 20); + + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfConversion member */ + ADC_InitStruct->ADC_NbrOfConversion = 1; +} + +/** + * @brief Initializes the ADCs peripherals according to the specified parameters + * in the ADC_CommonInitStruct. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * that contains the configuration information for All ADCs peripherals. + * @retval None + */ +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + uint32_t tmpreg1 = 0; + /* Check the parameters */ + assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); + assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); + assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); + /*---------------------------- ADC CCR Configuration -----------------*/ + /* Get the ADC CCR value */ + tmpreg1 = ADC->CCR; + + /* Clear MULTI, DELAY, DMA and ADCPRE bits */ + tmpreg1 &= CR_CLEAR_MASK; + + /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, + and DMA access mode for multimode */ + /* Set MULTI bits according to ADC_Mode value */ + /* Set ADCPRE bits according to ADC_Prescaler value */ + /* Set DMA bits according to ADC_DMAAccessMode value */ + /* Set DELAY bits according to ADC_TwoSamplingDelay value */ + tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | + ADC_CommonInitStruct->ADC_Prescaler | + ADC_CommonInitStruct->ADC_DMAAccessMode | + ADC_CommonInitStruct->ADC_TwoSamplingDelay); + + /* Write to ADC CCR */ + ADC->CCR = tmpreg1; +} + +/** + * @brief Fills each ADC_CommonInitStruct member with its default value. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * which will be initialized. + * @retval None + */ +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_Prescaler member */ + ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; + + /* Initialize the ADC_DMAAccessMode member */ + ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + + /* Initialize the ADC_TwoSamplingDelay member */ + ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group2 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + ##### Analog Watchdog configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + + [..] A typical configuration Analog Watchdog is done following these steps : + (#) the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + (#) The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + (#) The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog on single/all regular or + * injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + tmpreg &= CR1_AWDMode_RESET; + + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12-bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12-bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_RESET; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} +/** + * @} + */ + +/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) + * and VBAT (Voltage BATtery) management functions + * @brief Temperature Sensor, Vrefint and VBAT management functions + * +@verbatim + =============================================================================== + ##### Temperature Sensor, Vrefint and VBAT management functions ##### + =============================================================================== + [..] This section provides functions allowing to enable/ disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and + the Vbat sources. + + [..] A typical configuration to get the Temperature sensor and Vrefint channels + voltages is done following these steps : + (#) Enable the internal connection of Temperature sensor and Vrefint sources + with the ADC channels using ADC_TempSensorVrefintCmd() function. + (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using + ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions + (#) Get the voltage values, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + + [..] A typical configuration to get the VBAT channel voltage is done following + these steps : + (#) Enable the internal connection of VBAT source with the ADC channel using + ADC_VBATCmd() function. + (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or + ADC_InjectedChannelConfig() functions + (#) Get the voltage value, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + +@endverbatim + * @{ + */ + + +/** + * @brief Enables or disables the temperature sensor and Vrefint channels. + * @param NewState: new state of the temperature sensor and Vrefint channels. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); + } +} + +/** + * @brief Enables or disables the VBAT (Voltage Battery) channel. + * + * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and + * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices + * + * @param NewState: new state of the VBAT channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VBATCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the VBAT channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATE; + } + else + { + /* Disable the VBAT channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Regular Channels Configuration functions + * @brief Regular Channels Configuration functions + * +@verbatim + =============================================================================== + ##### Regular Channels Configuration functions ##### + =============================================================================== + + [..] This section provides functions allowing to manage the ADC's regular channels, + it is composed of 2 sub sections : + + (#) Configuration and management functions for regular channels: This subsection + provides functions allowing to configure the ADC regular channels : + (++) Configure the rank in the regular group sequencer for each channel + (++) Configure the sampling time for each channel + (++) select the conversion Trigger for regular channels + (++) select the desired EOC event behavior configuration + (++) Activate the continuous Mode (*) + (++) Activate the Discontinuous Mode + -@@- Please Note that the following features for regular channels + are configured using the ADC_Init() function : + (+@@) scan mode activation + (+@@) continuous mode activation (**) + (+@@) External trigger source + (+@@) External trigger edge + (+@@) number of conversion in the regular channels group sequencer. + + -@@- (*) and (**) are performing the same configuration + + (#) Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + regular channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + + -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions + results data (in the selected multi mode) can be returned in the same + time using ADC_GetMultiModeConversionValue() function. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables the selected ADC software start conversion of the regular channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Enable the selected ADC conversion for regular group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; +} + +/** + * @brief Gets the selected ADC Software start regular conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the SWSTART bit status */ + return bitstatus; +} + + +/** + * @brief Enables or disables the EOC on each regular channel conversion + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC EOC flag rising + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); + } +} + +/** + * @brief Enables or disables the ADC continuous conversion mode + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC continuous conversion mode + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC continuous conversion mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; + } + else + { + /* Disable the selected ADC continuous conversion mode */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); + } +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular group + * channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel count value. + * This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_RESET; + + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group channel + * for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on + * regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param None + * @retval The Data conversion value. + * @note In dual mode, the value returned by this function is as following + * Data[15:0] : these bits contain the regular data of ADC1. + * Data[31:16]: these bits contain the regular data of ADC2. + * @note In triple mode, the value returned by this function is as following + * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. + * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. + */ +uint32_t ADC_GetMultiModeConversionValue(void) +{ + /* Return the multi mode conversion value */ + return (*(__IO uint32_t *) CDR_ADDRESS); +} +/** + * @} + */ + +/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + ##### Regular Channels DMA Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the DMA for ADC + regular channels. + Since converted regular channel values are stored into a unique data + register, it is useful to use DMA for conversion of more than one regular + channel. This avoids the loss of the data already stored in the ADC + Data register. + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a regular channel, a DMA request is generated. + [..] Depending on the "DMA disable selection for Independent ADC mode" + configuration (using the ADC_DMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). + [..] Depending on the "DMA disable selection for multi ADC mode" configuration + (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). + +@endverbatim + * @{ + */ + + /** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @note if Enabled, DMA requests are issued as long as data are converted and + * DMA mode for multi ADC mode (selected using ADC_CommonInit() function + * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is + * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. + * @retval None + */ +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= (uint32_t)ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group6 Injected channels Configuration functions + * @brief Injected channels Configuration functions + * +@verbatim + =============================================================================== + ##### Injected channels Configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the ADC Injected channels, + it is composed of 2 sub sections : + + (#) Configuration functions for Injected channels: This subsection provides + functions allowing to configure the ADC injected channels : + (++) Configure the rank in the injected group sequencer for each channel + (++) Configure the sampling time for each channel + (++) Activate the Auto injected Mode + (++) Activate the Discontinuous Mode + (++) scan mode activation + (++) External/software trigger source + (++) External trigger edge + (++) injected channels sequencer. + + (#) Get the Specified Injected channel conversion data: This subsection + provides an important function in the ADC peripheral since it returns the + converted data of the specific injected channel. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + + /* Clear the old injected sequence length JL bits */ + tmpreg1 &= JSQR_JL_RESET; + + /* Set the injected sequence length JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + + /** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_RESET; + + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Configures the ADCx external trigger edge for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge + * to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for + * injected conversion + * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge + * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge + * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising + * and falling edge + * @retval None + */ +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external trigger edge for injected group */ + tmpreg &= CR2_JEXTEN_RESET; + /* Set the new external trigger edge for injected group */ + tmpreg |= ADC_ExternalTrigInjecConvEdge; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC conversion for injected group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on injected + * group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); + } +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the ADC Interrupts + and to get the status and clear flags and Interrupts pending bits. + + [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided + into 3 groups: + + *** Flags and Interrupts for ADC regular channels *** + ===================================================== + [..] + (+) Flags : + (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost + + (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate + (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) + the end of: + (+++) a regular CHANNEL conversion + (+++) sequence of regular GROUP conversions . + + (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular + CHANNEL conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection + event. + (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end + of conversion event. + + + *** Flags and Interrupts for ADC Injected channels *** + ====================================================== + [..] + (+) Flags : + (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate + at the end of injected GROUP conversion + + (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when + injected GROUP conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel + end of conversion event. + + *** General Flags and Interrupts for the ADC *** + ================================================ + [..] + (+)Flags : + (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage + crosses the programmed thresholds values. + [..] + (+) Interrupts : + (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. + + + [..] The user should identify which mode will be used in his application to + manage the ADC controller events: Polling mode or Interrupt mode. + + [..] In the Polling Mode it is advised to use the following functions: + (+) ADC_GetFlagStatus() : to check if flags events occur. + (+) ADC_ClearFlag() : to clear the flags events. + + [..] In the Interrupt Mode it is advised to use the following functions: + (+) ADC_ITConfig() : to enable or disable the interrupt source. + (+) ADC_GetITStatus() : to check if Interrupt occurs. + (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt enable + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint32_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + itmask = (uint32_t)0x01 << itmask; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c new file mode 100644 index 0000000..44fb9fe --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_dac.c @@ -0,0 +1,714 @@ +/** + ****************************************************************************** + * @file stm32f4xx_dac.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral: + * + DAC channels configuration: trigger, output buffer, data format + * + DMA management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### DAC Peripheral features ##### + =============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + The device integrates two 12-bit Digital Analog Converters that can + be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register + using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) + The timer TRGO event should be selected using TIM_SelectOutputTrigger() + + (#) Software using DAC_Trigger_Software + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave using DAC_WaveGeneration_Noise + (#) Triangle wave using DAC_WaveGeneration_Triangle + + -@- Wave generation can be disabled using DAC_WaveGeneration_None + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_Align_8b_R + (#) 12-bit left alignment using DAC_Align_12b_L + (#) 12-bit right alignment using DAC_Align_12b_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + DAC_SetChannel1Data(DAC_Align_12b_R, 868); + Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + DAC_DMACmd() + [..] + DMA1 requests are mapped as following: + (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be + already configured + (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be + already configured + + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using DAC_Init() function + (+) Enable the DAC channel using DAC_Cmd() function + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dac.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + ##### DAC channels configuration: trigger, output buffer, data format ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, + wave generation, mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ + DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + ##### DMA management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be + * already configured. + * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be + * already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c new file mode 100644 index 0000000..744939f --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_gpio.c @@ -0,0 +1,611 @@ +/** + ****************************************************************************** + * @file stm32f4xx_gpio.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * + Initialization and Configuration + * + GPIO Read and Write + * + GPIO Alternate functions configuration + * +@verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) Configure the GPIO pin(s) using GPIO_Init() + Four possible configuration are available for each pin: + (++) Input: Floating, Pull-up, Pull-down. + (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed + is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. + (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open + Drain (Pull-up, Pull-down or no Pull). + (++) Analog: required mode when a pin is to be used as ADC channel or DAC + output. + + (#) Peripherals alternate function: + (++) For ADC and DAC, configure the desired pin in analog mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + (+++) For other peripherals (TIM, USART...): + (+++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (+++) Configure the desired pin in alternate function mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (+++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (+++) Call GPIO_Init() function + + (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + + (#) To set/reset the level of a pin configured in output mode use + GPIO_SetBits()/GPIO_ResetBits() + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + ##### Initialization and Configuration ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } + + else if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + else if (GPIOx == GPIOJ) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); + } + else + { + if (GPIOx == GPIOK) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* ------------------------- Configure the port pins ---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /* Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### GPIO Read and Write ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Toggles the specified GPIO pins.. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function + * @brief GPIO Alternate functions configuration function + * +@verbatim + =============================================================================== + ##### GPIO Alternate functions configuration function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternate function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) + * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) + * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) + * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) + * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) + * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 + * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 + * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 + * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 + * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 + * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 + * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 + * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 + * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 + * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 + * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 + * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 + * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 + * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 + * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 + * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 + * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. + * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 + * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 + * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 + * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 + * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 + * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 + * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 + * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 + * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 + * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 + * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 + * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 + * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 + * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 + * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 + * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 + * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. + * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 + * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 + * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. + * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c new file mode 100644 index 0000000..bab7712 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_rcc.c @@ -0,0 +1,3022 @@ +/** + ****************************************************************************** + * @file stm32f4xx_rcc.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### RCC specific features ##### + =============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BitNumber 0x1A +#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) + +/* Alias word address of PLLSAION bit */ +#define PLLSAION_BitNumber 0x1C +#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of I2SSRC bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x08) +#define I2SSRC_BitNumber 0x17 +#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x70) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x74) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* --- DCKCFGR Register ---*/ +/* Alias word address of TIMPRE bit */ +#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) +#define TIMPRE_BitNumber 0x18 +#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) + +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) + #if defined(STM32F410xx) +/* Alias word address of MCO1EN bit */ +#define RCC_MCO1EN_BIT_NUMBER 0x8 +#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4)) + +/* Alias word address of MCO2EN bit */ +#define RCC_MCO2EN_BIT_NUMBER 0x9 +#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4)) +#endif /* STM32F410xx */ +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CFGR register bit mask */ +#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) +#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =================================================================================== + ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### + =================================================================================== + [..] + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. + + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface or SAI interface in case + of STM32F429x/439x devices. + + (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI + interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. + + (#) CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + @endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469_479xx) + /* Reset PLLI2SCFGR register */ + RCC->PLLI2SCFGR = 0x20003000; +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) + /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */ + RCC->PLLSAICFGR = 0x24003000; +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ + RCC->DCKCFGR = 0x00000000; + +#if defined(STM32F410xx) + /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx devices */ + RCC->DCKCFGR2 = 0x00000000; +#endif /* STM32F410xx */ +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; +} + +/** + * @brief Waits for HSE start-up. + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t startupcounter = 0; + ErrorStatus status = ERROR; + FlagStatus hsestatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + startupcounter++; + } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * + * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices + * This parameter must be a number between 2 and 7. + * + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(PLLR)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24) | (PLLR << 28); +} +#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24); +} +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ + +/** + * @brief Enables or disables the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined(STM32F40_41xxx) || defined(STM32F401xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx + * or STM32F401xx devices. + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); +} +#endif /* STM32F40_41xxx || STM32F401xx */ + +#if defined(STM32F411xE) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F411xE devices. + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM; +} +#endif /* STM32F411xE */ + +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLI2SQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); +} +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ + +#if defined(STM32F412xG ) || defined(STM32F446xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F446xx devices + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param PLLI2SQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28); +} +#endif /* STM32F412xG || STM32F446xx */ + +/** + * @brief Enables or disables the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLI2SCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; +} + +#if defined(STM32F469_479xx) +/** + * @brief Configures the PLLSAI clock multiplication and division factors. + * + * @note This function can be used only for STM32F469_479xx devices + * + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output + * This parameter must be a number in the range {2, 4, 6, or 8}.. + * + * @param PLLSAIQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLSAIR: specifies the division factor for LTDC clock + * This parameter must be a number between 2 and 7. + * + * @retval None + */ +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); + + RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28); +} +#endif /* STM32F469_479xx */ + +#if defined(STM32F446xx) +/** + * @brief Configures the PLLSAI clock multiplication and division factors. + * + * @note This function can be used only for STM32F446xx devices + * + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLSAI jitter. + * + * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param PLLSAIQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @retval None + */ +void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM)); + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); + + RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24); +} +#endif /* STM32F446xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) +/** + * @brief Configures the PLLSAI clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock + * This parameter must be a number between 50 and 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param PLLSAIQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLSAIR: specifies the division factor for LTDC clock + * This parameter must be a number between 2 and 7. + * + * @retval None + */ +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); + + RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); +} +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ + +/** + * @brief Enables or disables the PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices + * + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLSAICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCO1Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source + * @param RCC_MCO1Div: specifies the MCO1 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO1Div_1: no division applied to MCO1 clock + * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock + * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock + * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock + * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock + * @retval None + */ +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ + tmpreg &= CFGR_MCO1_RESET_MASK; + + /* Select MCO1 clock source and prescaler */ + tmpreg |= RCC_MCO1Source | RCC_MCO1Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; + +#if defined(STM32F410xx) + RCC_MCO1Cmd(ENABLE); +#endif /* STM32F410xx */ +} + +/** + * @brief Selects the clock source to output on MCO2 pin(PC9). + * @note PC9 should be configured in alternate function mode. + * @param RCC_MCO2Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices + * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCO2Div: specifies the MCO2 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO2Div_1: no division applied to MCO2 clock + * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock + * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock + * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock + * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock + * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + * @retval None + */ +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); + assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO2 and MCO2PRE[2:0] bits */ + tmpreg &= CFGR_MCO2_RESET_MASK; + + /* Select MCO2 clock source and prescaler */ + tmpreg |= RCC_MCO2Source | RCC_MCO2Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; + +#if defined(STM32F410xx) + RCC_MCO2Cmd(ENABLE); +#endif /* STM32F410xx */ +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + ##### System, AHB and APB busses clocks configuration functions ##### + =============================================================================== + [..] + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. + + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. + + (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency + of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending + on the device voltage range, the maximum frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| + +---------------|----------------|----------------|-----------------|-----------------+ + (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, + PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| + |---------------|----------------|----------------|-----------------|-----------------| + |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| + +-------------------------------------------------------------------------------------+ + + (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | + +-------------------------------------------------------------------------------------+ + + (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | + +-------------------------------------------------------------------------------------+ + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0', the maximum value of fHCLK = 144MHz. + (++) when VOS = '1', the maximum value of fHCLK = 168MHz. + [..] + On STM32F42xxx/43xxx/469xx/479xx devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. + (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz + [..] + On STM32F401x devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. + On STM32F410xx/STM32F411xE devices: + (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz. + (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz. + + You can use PWR_MainRegulatorModeConfig() function to control VOS bits. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices) + * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG and STM32F446xx devices + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices) + * - 0x0C: PLL R used as system clock (only for STM32F412xG and STM32F446xx devices) + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @note Depending on the device voltage range, the software has to set correctly + * these bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above + * "CPU, AHB and APB busses clocks configuration functions") + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * PCLK1 and PCLK2. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; +#if defined(STM32F412xG) || defined(STM32F446xx) + uint32_t pllr = 2; +#endif /* STM32F412xG || STM32F446xx */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL P used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + break; + +#if defined(STM32F412xG) || defined(STM32F446xx) + case 0x0C: /* PLL R used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllr; + break; +#endif /* STM32F412xG || STM32F446xx */ + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ + + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 10; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 13; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral clocks configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the Peripheral clocks. + + (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided + by 2 to 31. + + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral + you have to enable its interface clock. You can do this using + RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + (#) To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + + (#) To further reduce power consumption in SLEEP mode the peripheral clocks + can be disabled prior to executing the WFI or WFE instructions. + You can do this using RCC_AHBPeriphClockLPModeCmd(), + RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using RCC_BackupResetCmd() function, or by + * a Power On Reset (POR). + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) + { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CFGR; + + /* Clear RTCPRE[4:0] bits */ + tmpreg &= ~RCC_CFGR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); + + /* Store the new value */ + RCC->CFGR = tmpreg; + } + + /* Select the RTC clock source */ + RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +#if defined (STM32F412xG) || defined(STM32F446xx) +/** + * @brief Configures the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * + * @param RCC_I2SAPBx: specifies the APBx I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus + * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus + * + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source + * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx)); + + if(RCC_I2SAPBx == RCC_I2SBus_APB1) + { + /* Clear APB1 I2Sx clock source selection bits */ + RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC; + /* Set new APB1 I2Sx clock source*/ + RCC->DCKCFGR |= RCC_I2SCLKSource; + } + else + { + /* Clear APB2 I2Sx clock source selection bits */ + RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC; + /* Set new APB2 I2Sx clock source */ + RCC->DCKCFGR |= (RCC_I2SCLKSource << 2); + } +} +#if defined(STM32F446xx) +/** + * @brief Configures the SAIx clock source (SAIxCLK). + * @note This function must be called before enabling the SAIx APB clock. + * + * @param RCC_SAIInstance: specifies the SAIx clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection + * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections + * + * @param RCC_SAICLKSource: specifies the SAI clock source. + * This parameter can be one of the following values: + * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source + * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source + * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source + * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source + * @retval None + */ +void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource)); + assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance)); + + if(RCC_SAIInstance == RCC_SAIInstance_SAI1) + { + /* Clear SAI1 clock source selection bits */ + RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC; + /* Set new SAI1 clock source */ + RCC->DCKCFGR |= RCC_SAICLKSource; + } + else + { + /* Clear SAI2 clock source selection bits */ + RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC; + /* Set new SAI2 clock source */ + RCC->DCKCFGR |= (RCC_SAICLKSource << 2); + } +} +#endif /* STM32F446xx */ +#endif /* STM32F412xG || STM32F446xx */ + +#if defined(STM32F410xx) +/** + * @brief Configures the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S clock. + * + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + /* Clear I2Sx clock source selection bits */ + RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC; + /* Set new I2Sx clock source*/ + RCC->DCKCFGR |= RCC_I2SCLKSource; +} +#endif /* STM32F410xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) +/** + * @brief Configures the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; +} +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ + +#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) +/** + * @brief Configures SAI1BlockA clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock + * @retval None + */ +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; + + /* Set SAI Block A source selection value */ + tmpreg |= RCC_SAIBlockACLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures SAI1BlockB clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock + * @retval None + */ +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; + + /* Set SAI Block B source selection value */ + tmpreg |= RCC_SAIBlockBCLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} +#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ + +/** + * @brief Configures the SAI clock Divider coming from PLLI2S. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. + * + * @note This function must be called before enabling the PLLI2S. + * + * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ + * + * @retval None + */ +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); + + /* Set PLLI2SDIVQ values */ + tmpreg |= (RCC_PLLI2SDivQ - 1); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the SAI clock Divider coming from PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ + * + * @retval None + */ +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); + + /* Set PLLSAIDIVQ values */ + tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . + * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR + * This parameter can be one of the following values: + * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2 + * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4 + * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8 + * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16 + * + * @retval None + */ +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLSAIDIVR[2:0] bits */ + tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; + + /* Set PLLSAIDIVR values */ + tmpreg |= RCC_PLLSAIDivR; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +#if defined(STM32F412xG) +/** + * @brief Configures the DFSDM clock source (DFSDMCLK). + * @note This function must be called before enabling the DFSDM APB clock. + * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSource_APB: APB clock used as DFSDM clock source. + * @arg RCC_DFSDM1CLKSource_SYS: System clock used as DFSDM clock source. + * + * @retval None + */ +void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDM1CLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear CKDFSDM-SEL bit */ + tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL; + + /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */ + tmpreg |= (RCC_DFSDM1CLKSource << 31) ; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the DFSDM Audio clock source (DFSDMACLK). + * @note This function must be called before enabling the DFSDM APB clock. + * @param RCC_DFSDMACLKSource: specifies the DFSDM clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source. + * + * @retval None + */ +void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDMACLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDMACLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear CKDFSDMA SEL bit */ + tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL; + + /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */ + tmpreg |= RCC_DFSDMACLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} +#endif /* STM32F412xG */ + +/** + * @brief Configures the Timers clocks prescalers selection. + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. + * + * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * + * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + * @retval None + */ +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) +{ + /* Check the parameters */ + assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); + + *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: + * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices) + * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} +#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices) + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) + * @arg RCC_APB2Periph_DFSDM: DFSDM Clock (STM32F412xG Devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices + * + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2Periph; + } +} + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. + * This parameter must be: + * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG and STM32F429x/439x devices) + * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices) + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3Periph; + } +} +#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices) + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices) + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2Periph; + } +} + +#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: + * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices) + * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3Periph; + } +} +#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices) + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) + * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Configures the External Low Speed oscillator mode (LSE mode). + * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices. + * @param Mode: specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. + * @retval None + */ +void RCC_LSEModeConfig(uint8_t RCC_Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(RCC_Mode)); + + if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#if defined(STM32F410xx) +/** + * @brief Configures the LPTIM1 clock Source. + * @note This feature is only available for STM32F410xx devices. + * @param RCC_ClockSource: specifies the LPTIM1 clock Source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected. + * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected. + * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected. + * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected. + * @retval None + */ +void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource)); + + /* Clear LPTIM1 clock source selection source bits */ + RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL; + /* Set new LPTIM1 clock source */ + RCC->DCKCFGR2 |= RCC_ClockSource; +} +#endif /* STM32F410xx */ + +#if defined(STM32F469_479xx) +/** + * @brief Configures the DSI clock Source. + * @note This feature is only available for STM32F469_479xx devices. + * @param RCC_ClockSource: specifies the DSI clock Source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case). + * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode). + * @retval None + */ +void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource)); + + if(RCC_ClockSource == RCC_DSICLKSource_PLLR) + { + SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL); + } +} +#endif /* STM32F469_479xx */ + +#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) +/** + * @brief Configures the 48MHz clock Source. + * @note This feature is only available for STM32F446xx/STM32F469_479xx devices. + * @param RCC_ClockSource: specifies the 48MHz clock Source. + * This parameter can be one of the following values: + * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected. + * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected. + * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ + * @retval None + */ +void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource)); +#if defined(STM32F469_479xx) + if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI) + { + SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL); + } +#elif defined(STM32F446xx) + if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI) + { + SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); + } +#elif defined(STM32F412xG) + if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ) + { + SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); + } +#else +#endif /* STM32F469_479xx */ +} + +/** + * @brief Configures the SDIO clock Source. + * @note This feature is only available for STM32F469_479xx/STM32F446xx devices. + * @param RCC_ClockSource: specifies the SDIO clock Source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected. + * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected. + * @retval None + */ +void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource)); +#if defined(STM32F469_479xx) + if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK) + { + SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL); + } +#elif defined(STM32F412xG) || defined(STM32F446xx) + if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK) + { + SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL); + } +#else +#endif /* STM32F469_479xx */ +} +#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */ + +#if defined(STM32F446xx) +/** + * @brief Enables or disables the AHB1 clock gating for the specified IPs. + * @note This feature is only available for STM32F446xx devices. + * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock + * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock + * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock + * @arg RCC_AHB1ClockGating_SPARE: Spare clock + * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock + * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock + * @arg RCC_AHB1ClockGating_RCC: RCC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->CKGATENR &= ~RCC_AHB1ClockGating; + } + else + { + RCC->CKGATENR |= RCC_AHB1ClockGating; + } +} + +/** + * @brief Configures the SPDIFRX clock Source. + * @note This feature is only available for STM32F446xx devices. + * @param RCC_ClockSource: specifies the SPDIFRX clock Source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected. + * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected. + * @retval None + */ +void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource)); + + if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP) + { + SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL); + } +} + +/** + * @brief Configures the CEC clock Source. + * @note This feature is only available for STM32F446xx devices. + * @param RCC_ClockSource: specifies the CEC clock Source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected. + * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected. + * @retval None + */ +void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource)); + + if(RCC_ClockSource == RCC_CECCLKSource_LSE) + { + SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL); + } + else + { + CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL); + } +} +#endif /* STM32F446xx */ + +#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) +/** + * @brief Configures the FMPI2C1 clock Source. + * @note This feature is only available for STM32F446xx devices. + * @param RCC_ClockSource: specifies the FMPI2C1 clock Source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected. + * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected. + * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected. + * @retval None + */ +void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource)); + + /* Clear FMPI2C1 clock source selection source bits */ + RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL; + /* Set new FMPI2C1 clock source */ + RCC->DCKCFGR2 |= RCC_ClockSource; +} +#endif /* STM32F410xx || STM32F412xG || STM32F446xx */ +/** + * @} + */ + +#if defined(STM32F410xx) +/** + * @brief Enables or disables the MCO1. + * @param NewState: new state of the MCO1. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_MCO1Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the MCO2. + * @param NewState: new state of the MCO2. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_MCO2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState; +} +#endif /* STM32F410xx */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: main PLL clock ready + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c new file mode 100644 index 0000000..9a88106 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_tim.c @@ -0,0 +1,3365 @@ +/** + ****************************************************************************** + * @file stm32f4xx_tim.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * + TimeBase management + * + Output Compare management + * + Input Capture management + * + Advanced-control timers (TIM1 and TIM8) specific features + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This driver provides functions to configure and program the TIM + of all STM32F4xx devices. + These functions are split in 9 groups: + + (#) TIM TimeBase management: this group includes all needed functions + to configure the TM Timebase unit: + (++) Set/Get Prescaler + (++) Set/Get Autoreload + (++) Counter modes configuration + (++) Set Clock division + (++) Select the One Pulse mode + (++) Update Request Configuration + (++) Update Disable Configuration + (++) Auto-Preload Configuration + (++) Enable/Disable the counter + + (#) TIM Output Compare management: this group includes all needed + functions to configure the Capture/Compare unit used in Output + compare mode: + (++) Configure each channel, independently, in Output Compare mode + (++) Select the output compare modes + (++) Select the Polarities of each channel + (++) Set/Get the Capture/Compare register values + (++) Select the Output Compare Fast mode + (++) Select the Output Compare Forced mode + (++) Output Compare-Preload Configuration + (++) Clear Output Compare Reference + (++) Select the OCREF Clear signal + (++) Enable/Disable the Capture/Compare Channels + + (#) TIM Input Capture management: this group includes all needed + functions to configure the Capture/Compare unit used in + Input Capture mode: + (++) Configure each channel in input capture mode + (++) Configure Channel1/2 in PWM Input mode + (++) Set the Input Capture Prescaler + (++) Get the Capture/Compare values + + (#) Advanced-control timers (TIM1 and TIM8) specific features + (++) Configures the Break input, dead time, Lock level, the OSSI, + the OSSR State and the AOE(automatic output enable) + (++) Enable/Disable the TIM peripheral Main Outputs + (++) Select the Commutation event + (++) Set/Reset the Capture Compare Preload Control bit + + (#) TIM interrupts, DMA and flags management + (++) Enable/Disable interrupt sources + (++) Get flags status + (++) Clear flags/ Pending bits + (++) Enable/Disable DMA requests + (++) Configure DMA burst mode + (++) Select CaptureCompare DMA request + + (#) TIM clocks management: this group includes all needed functions + to configure the clock controller unit: + (++) Select internal/External clock + (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx + + (#) TIM synchronization management: this group includes all needed + functions to configure the Synchronization unit: + (++) Select Input Trigger + (++) Select Output Trigger + (++) Select Master Slave Mode + (++) ETR Configuration when used as external trigger + + (#) TIM specific interface management, this group includes all + needed functions to use the specific TIM interface: + (++) Encoder Interface Configuration + (++) Select Hall Sensor + + (#) TIM specific remapping management includes the Remapping + configuration of specific timers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_tim.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) +#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) +#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + ##### TimeBase management functions ##### + =============================================================================== + + + ##### TIM Driver: how to use it in Timing(Time base) Mode ##### + =============================================================================== + [..] + To use the Timer in Timing(Time base) mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. + + (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit + with the corresponding configuration + + (#) Enable the NVIC if you need to generate the update interrupt. + + (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval None + + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else + { + if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| + (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Counter Register value + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter + * overflow/underflow or the setting of UG bit, or an update + * generation through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group2 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + ##### Output Compare management functions ##### + =============================================================================== + + + ##### TIM Driver: how to use it in Output Compare Mode ##### + =============================================================================== + [..] + To use the Timer in Output Compare mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function + + (#) Configure the TIM pins by configuring the corresponding GPIO pins + + (#) Configure the Time base unit as described in the first part of this driver, + (++) if needed, else the Timer will run with the default configuration: + Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 + + (#) Fill the TIM_OCInitStruct with the desired parameters including: + (++) The TIM Output Compare mode: TIM_OCMode + (++) TIM Output State: TIM_OutputState + (++) TIM Pulse value: TIM_Pulse + (++) TIM Output Compare Polarity : TIM_OCPolarity + + (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired + channel with the corresponding configuration + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + + -@- In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); + + -@- If the corresponding interrupt or DMA request are needed, the user should: + (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + (+@) Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified parameters in + * the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NE; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x00000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. If needed, user has to enable this channel using + * TIM_CCxCmd() and TIM_CCxNCmd() functions. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} +/** + * @} + */ + +/** @defgroup TIM_Group3 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + ##### Input Capture management functions ##### + =============================================================================== + + ##### TIM Driver: how to use it in Input Capture Mode ##### + =============================================================================== + [..] + To use the Timer in Input Capture mode, the following steps are mandatory: + + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function + + (#) Configure the TIM pins by configuring the corresponding GPIO pins + + (#) Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + (++) Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 + + (#) Fill the TIM_ICInitStruct with the desired parameters including: + (++) TIM Channel: TIM_Channel + (++) TIM Input Capture polarity: TIM_ICPolarity + (++) TIM Input Capture selection: TIM_ICSelection + (++) TIM Input Capture Prescaler: TIM_ICPrescaler + (++) TIM Input Capture filter value: TIM_ICFilter + + (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel + with the corresponding configuration and to measure only frequency + or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) + to configure the desired channels with the corresponding configuration + and to measure the frequency and the duty cycle of the input signal + + (#) Enable the NVIC or the DMA to read the measured frequency. + + (#) Enable the corresponding interrupt (or DMA request) to read the Captured + value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) + (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + (#) Use TIM_GetCapturex(TIMx); to read the captured value. + + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} +/** + * @} + */ + +/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features + * @brief Advanced-control timers (TIM1 and TIM8) specific features + * +@verbatim + =============================================================================== + ##### Advanced-control timers (TIM1 and TIM8) specific features ##### + =============================================================================== + + ##### TIM Driver: how to use the Break feature ##### + =============================================================================== + [..] + After configuring the Timer channel(s) in the appropriate Output Compare mode: + + (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + (#) Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts, DMA and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used + * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, + * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can + * be used: TIM_IT_Update or TIM_IT_CC1 + * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM1_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + ##### Clocks management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_InputTriggerSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + ##### Synchronization management functions ##### + =============================================================================== + + ##### TIM Driver: how to use it in synchronization Mode ##### + =============================================================================== + [..] + + *** Case of two/several Timers *** + ================================== + [..] + (#) Configure the Master Timers using the following functions: + (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); + (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + + *** Case of Timers and external trigger(ETR pin) *** + ==================================================== + [..] + (#) Configure the External trigger using this function: + (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs(TRGO) + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize + * the counter and triggers an update of the registers + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO) + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + ##### Specific interface management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + ##### Specific remapping management function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. + * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input remapping source. + * This parameter can be one of the following values: + * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. + * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c new file mode 100644 index 0000000..5d4dd27 --- /dev/null +++ b/STM32F4XX_Lib/STM32F4xx_StdPeriph_Driver/source/stm32f4xx_usart.c @@ -0,0 +1,1486 @@ +/** + ****************************************************************************** + * @file stm32f4xx_usart.c + * @author MCD Application Team + * @version V1.7.1 + * @date 20-May-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * + Initialization and Configuration + * + Data transfers + * + Multi-Processor Communication + * + LIN mode + * + Half-duplex mode + * + Smartcard mode + * + IrDA mode + * + DMA transfers management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, + UART4 or UART5. + + (#) According to the USART mode, enable the GPIO clocks using + RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, + or/and SCLK). + + (#) Peripheral's alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) using the USART_Init() + function. + + (#) For synchronous mode, enable the clock and program the polarity, + phase and last bit using the USART_ClockInit() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + USART_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using USART_DMACmd() function + + (#) Enable the USART using the USART_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + + -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + for more details + + [..] + In order to reach higher communication baudrates, it is possible to + enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). + This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) + and before calling the function USART_Init(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_usart.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ +#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ +#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint16_t)0x001F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) Hardware flow control + (++) Receiver/transmitter modes + + [..] + The USART_Init() function follows the USART asynchronous configuration + procedure (details for the procedure are available in reference manual (RM0090)). + + (+) For the synchronous mode in addition to the asynchronous mode parameters these + parameters should be also configured: + (++) USART Clock Enabled + (++) USART polarity + (++) USART phase + (++) USART LastBit + + [..] + These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + else if (USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else + { + if (USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : + Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to USART_WordLength value + Set PCE and PS bits according to USART_Parity value + Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC : + Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR register */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); + } +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @note This function has to be called before calling USART_Init() function + * in order to have correct baudrate Divider value. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART data + transfers. + [..] + During an USART reception, data shifts in least significant bit first through + the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) + between the internal bus and the received shift register. + [..] + When a transmission is taking place, a write instruction to the USART_DR register + stores the data in the TDR register and which is copied in the shift register + at the end of the current transmission. + [..] + The read access of the USART_DR register can be done using the USART_ReceiveData() + function and returns the RDR buffered value. Whereas a write access to the USART_DR + can be done using USART_SendData() function and stores the written data into + TDR buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group3 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + ##### Multi-Processor Communication functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + [..] + For instance one of the USARTs can be the master, its TX output is connected + to the RX input of the other USART. The others are slaves, their respective + TX outputs are logically ANDed together and connected to the RX input of the + master. + [..] + USART multiprocessor communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode + transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) + using USART_WakeUpConfig() function only for the slaves. + (#) Enable the USART using the USART_Cmd() function. + (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. + [..] + The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_RWU; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); + } +} +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @} + */ + +/** @defgroup USART_Group4 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + ##### LIN mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART LIN + Mode communication. + [..] + In LIN mode, 8-bit data format with 1 stop bit is required in accordance with + the LIN standard. + [..] + Only this LIN Feature is supported by the USART IP: + (+) LIN Master Synchronous Break send capability and LIN slave break detection + capability : 13-bit break generation and 10/11 bit break detection + + [..] + USART LIN Master transmitter communication is possible through the following + procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + (#) Send the break character using USART_SendBreak() function. + [..] + USART LIN Master receiver communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() + function. + (#) Enable the LIN mode using the USART_LINCmd() function. + + -@- In LIN mode, the following bits must be kept cleared: + (+@) CLKEN in the USART_CR2 register, + (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); + } +} + +/** + * @brief Transmits break characters. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= USART_CR1_SBK; +} + +/** + * @} + */ + +/** @defgroup USART_Group5 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + ##### Half-duplex mode function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + [..] + The USART can be configured to follow a single-wire half-duplex protocol where + the TX and RX lines are internally connected. + [..] + USART Half duplex communication is possible through the following procedure: + (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. + + + -@- The RX pin is no longer used + -@- In Half-duplex mode the following bits must be kept cleared: + (+@) LINEN and CLKEN bits in the USART_CR2 register. + (+@) SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group6 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + ##### Smartcard mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + Smartcard communication is possible through the following procedure: + (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. + (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. + (#) Program the USART clock using the USART_ClockInit() function as following: + (++) USART Clock enabled + (++) USART CPOL Low + (++) USART CPHA on first edge + (++) USART Last Bit Clock Enabled + (#) Program the Smartcard interface using the USART_Init() function as following: + (++) Word Length = 9 Bits + (++) 1.5 Stop Bit + (++) Even parity + (++) BaudRate = 12096 baud + (++) Hardware flow control disabled (RTS and CTS signals) + (++) Tx and Rx enabled + (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() + function + (#) PEnable the USART using the USART_Cmd() function. + (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. + + Please refer to the ISO 7816-3 specification for more details. + + -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + -@- In smartcard mode, the following bits must be kept cleared: + (+@) LINEN bit in the USART_CR2 register. + (+@) HDSEL and IREN bits in the USART_CR3 register. + -@- Smartcard mode is available on USART peripherals only (not available on UART4 + and UART5 peripherals). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + ##### IrDA mode functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART + IrDA communication. + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + [..] + IrDA communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver + modes and hardware flow control values using the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode + using the USART_IrDAConfig() function. + (#) Enable the IrDA using the USART_IrDACmd() function. + + -@- A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. + -@- The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). + -@- In IrDA mode, the following bits must be kept cleared: + (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. + (+@) SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group8 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup USART_Group9 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to configure the USART + Interrupts sources, DMA channels requests and check or clear the flags or + pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] + In Polling Mode, the SPI communication can be managed by 10 flags: + (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register + (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register + (#) USART_FLAG_TC : to indicate the status of the transmit operation + (#) USART_FLAG_IDLE : to indicate the status of the Idle Line + (#) USART_FLAG_CTS : to indicate the status of the nCTS input + (#) USART_FLAG_LBD : to indicate the status of the LIN break detection + (#) USART_FLAG_NE : to indicate if a noise error occur + (#) USART_FLAG_FE : to indicate if a frame error occur + (#) USART_FLAG_PE : to indicate if a parity error occur + (#) USART_FLAG_ORE : to indicate if an Overrun error occur + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); + (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + In Interrupt Mode, the USART communication can be managed by 8 interrupt sources + and 10 pending bits: + + (#) Pending Bits: + + (##) USART_IT_TXE : to indicate the status of the transmit buffer register + (##) USART_IT_RXNE : to indicate the status of the receive buffer register + (##) USART_IT_TC : to indicate the status of the transmit operation + (##) USART_IT_IDLE : to indicate the status of the Idle Line + (##) USART_IT_CTS : to indicate the status of the nCTS input + (##) USART_IT_LBD : to indicate the status of the LIN break detection + (##) USART_IT_NE : to indicate if a noise error occur + (##) USART_IT_FE : to indicate if a frame error occur + (##) USART_IT_PE : to indicate if a parity error occur + (##) USART_IT_ORE : to indicate if an Overrun error occur + + (#) Interrupt Source: + + (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty + interrupt. + (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (##) USART_IT_TC : specifies the interrupt source for the Transmit complete + interrupt. + (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. + (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. + (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection + interrupt. + (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. + (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. + + -@@- Some parameters are coded in order to use them as interrupt source + or as pending bits. + [..] + In this Mode it is advised to use the following functions: + (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); + (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); + (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + + *** DMA Mode *** + ================ + [..] + In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: + (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request + (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request + [..] + In this Mode it is advised to use the following function: + (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * @note RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * @note TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * @note RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * @note TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32F7XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/STM32F7XX_Lib/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..c67c8672dbf9fdcf4bf64a22791e24c9f1688d1d GIT binary patch literal 179946 zcmdSARdgK7vaTzzm@Q_qn3*kRvY1&dW@gD2Gcz+<%*@QpXfZQOSN7a2IbP5i3js^~jb^w69wY38QBg>yI(t390 z;#Nl1A7*|Z0t^X0x&gj^eBht~R)&9E{5JM)zW(^26SQ`;av)%#lQcE7*C1f}ZH|C} z`LBlcuZI0k!$|+T(IWV#&EMVs!{�JHUs{ztqbE?5!Q`3;^~Y+C;3a9DX+p1b@jE zVI*MtZIn)giGbtx!Pl>J-|Van6aWqybRW5*Qv|p;(1}}qBtzh@M)0pj{I?7`X@H@r zo`AKB#>Y^40u~MyS|&yUc4h`z4n{44kHD-PK4jPv{0W9m)Xv(`=I=EBIiXXaQ?%2w zvbXsy*T9udP=QVe;ACn5kQWvBu&$`5Z~xKduY~^t z{zTV=8(Tji#CR@66Et-;-WKQWT-Rz-880gnA6h;;x-6b_lSJ>^-c z@=rCVxmjE98F@Ry;*D}X5&Ulz-l}JVed+Ui4HqXBU@!3(g`XUiJ!SK#=?tT=u6}&) zhUxb?{hUz7&};=OU-bykY8_qNX=^#XJDaH$FE6dub4ygmHh;M;gWPekQtj_O@ZHv$ zI_MDL?nE>;c~jb~14I7gammxgrVd38@&@m+|I|V|eWd4rpf<5n+PUz`leZQgk*L|% zI>}6-9n^ohTG{F$MF_&=E}u1LYX?&8b$LZY|4Mh<^O{o~HpZunb?R^Ox+bO#P1El- zRiLY0WiNF7L>K%xI*xx!i(SlrNf3LEmYVyTKbv%FLxSFsVG)ry>?x?TWz)u?evE|u zY;!wfSEz=QD_gg8;Qg?jNV1Sg%r*kg<6>{Yzwq;MYk!O!%B9x7vo~B1D6;YH)TWpX zYi6gisB0HraxYP+75>(sNfnfoo=__Mf(Kj&$=Q50*I*S$C$05+8(tc%zxs=oxqiDU zuJws^ps3N@j_+K`Nk|(0@o>2##Ngura7gdjS{0O>(`9k`<~9{~OFUt>mu*0cfzbw8 zAepgbE&6lnLg2-@b%4M?Y1=|-?38^}u{~m$p|s!7C$3TyE|ulV1*XR)Ji@?wj*{?0 zy~g8y z`qaBwg4ARt=zqFe2T$akOZ(!Zb-O<%cgghv^YT!t?Pl*%V);5D(inlH(>}ysr9DaJ>qwzMkCIo(=eWZ>=^j;M4|LIq*v+*>SANLGE>* z3zMgeZl*k-D@tRxG{U8?Z*@I1fyCkloq-+HYUU)XVms}9U^2FT94nt#gjV9i`et23 z(VVz-C%IjGI~v>EPXjh;vFb8?zCv86DN?|RMbuc<8IHw<(|V^ks>IVwT^v_J{6rD) zPf&vDEQ`ti#jxodEyJO0TCl;i@4*P2ny+h)E=(l`(lUFaUkBM+f&L&AcusbaT^#=A z6~6!0qVynDuPllWlJ3jOrfEvJiP;LZF$QTsR9iU=mVsmbi`u{Nu6hbW`HOX;EeC^21`3gcDCac?9#z5jJ z95ebt?t#LQwz;_s3);Ib5Pr-rVv~Y|)>Va4xJ&L3gzX=wmrs019x57M2vw~57_JbNFkWVt#m2xFr(PtRQU%|ja^t0!_4E?#x#Q}o z5|a#^>o{9`Q4%g2s3&+A*{UT=qI@igBD{3%O}r;BJjmnVM`8T@yJWJHmOSQQG&M8C z{^}9D$ELctc~flU(zwGq83Un6XR8T=EO|5qGqz9|Xfx%>v}&EtwXr#!^IJAJY8~C- zI~0 zS+U$SZ)qXkES=8Gf25wXx*r~mx{O-pTZ~mw3SPs_-_!$i)f+{CWhZ5VmUdn=`y;pm z`fzR z4(cRj>o)I=w*T?VihWsXC|0kZ`75717GZ0Tx?!iw$=eYPd)l&T3&dr&#DG7AgG1;s z!o{J$$Px$l#z@nzVl-j{GBhcz3#7AC2s(5G~_Hz zs4`oQUHe~(b*(2D@d{(MA!c=8LlNn@-+(835ofcZ;>l-#HAPDTC+1H3=21pzKk#`x2ivOK zvN6{@G>c-5ATV2A8Ad{Y+Zr+eJGb%~^yRC;=_;W|w}jO*1iUIP{rOhRfSyE5ng?r{ zpE|olj1uQldET2MR}1cYh9 zj=lT zAG)DUQ18wv`_kUjl5Pv|^YD<4=27*VpK7x>$c&@zIPzeGmM_jW*$0jGZT9YQLGCRr zxIu>VT$3u>PM0RK+XP1>P6^sg8^{ndqE|U@b`~X+_&8mieCc@;7Fg-n)6}2$c^2;9 z!_k0(L*;2Sj&3Lqu32n{aK0PP@54GC%T@8L_&F;2;FQn18Joc`;SYfp!XQrS$a>^N zwZ!*EXcij$&5itQ>pBVps_yIvWWXe_h3hoUH!2B|4&8V*Dwic_PSz2Y92x*Zxw6*0IUClO z`5yrhMJqn$t7o)noH>;DzB4W3V-Qz*DWKjAHjtC03}}hrKH9uLPU42Y#k1n`j1L#X zf4=?GY6x9E7 zR1M6+6Sve-_wKeQedeYnj{c@6c~#XxW0SHlSzWujgbl`6lN0dLU0>uvVtaU~%g}m> zV3iK#O8<-g1YF{?Yc%9Y(@d539VYh|+U?seRl>1%NEmLuw}sU3#Z&jnc9LO@U!%aZ zPOCRiN%`2b@!G@XtvN5muG)sKk<8!rWa%Q$jJYQ}<Q}p|;<0sUX=z z6w;6Bd2!3a^J;2-|2h)zQN0 zSTf4&egTc7<^`@TU2Y9w=@til&OqM$(r~c5m3x|tP6|O}VChS z^kMR_(6dp;~K@3A4W02_nZNdJW4FexitIr+znoE&Z>}(ow9klJ!$ya{T z>v2!%v*OIY*`l%t=^ngs_@&GXmS5)d=>U%fO{qbGC^A1j?kK&9a560S%_I!Zyu6TB zuhdECu24Kn*UuP>h`@GI3;u-)HUa`McXi%Q{71QO8s!Xv^_(Rq=_if31jZcDtv}vw zlG8CoK(DONd5+lBS)vK|PG?T&Gmi?pfmPLZ=PCWFEznn*z2<22^kK`qpcd;tv0uxq zz}i`&weOp4_@EW+mtftfT^3E0knA(88Ih2pwuG?OPik-&$hH&c$1_;qy=l%s zDQyVk?ViuQ@~z_ck!NT3G%CZEoL54fwKvNCLV$A^&cbuwaf-gwDBbxpAYvSAq1-IO z3Dpwr{;I=%Lj%^)YeNG8eU=OdwPKPpr6J3Q#VlUIfrBOORJw*K>>hW;=Rg!&^B2ti zS}FfpYw!ZDwK!8Ltj09uLQ$fL=)^)XBo|B)z_~751ipuZs&$4pDNS`d8r{P0_?26xj`x zZ|fgckAA&RyMAme8A+L%>#vjNk))!~9%ct-WaB`Q^^msdPbI?KA+)rvE1b zwf@l9Mf{%2)VJOV&`m{ga5IvnaR}1vTZ1?^Jqu77QcU+umSG%yc1BiRds*V@EL6EF zqXiYMB?{i($m=M*1K<-`5*m`{|Ri(09}eh+UX6{gx!6q>lO zgr!bhsC(G5!D5qs5WtBWZVYn*saB}gM)D z)N_-k=7|^Vv_g+VJ1izm4c3lWZORsV^~*6Ps-6ZpFKX26t56@aOj`y2~FJp7k z6tA^^p>VOs48GcXQn>6TdsHyo_Tv@q*VopS_Y8t|%YIr(Ih5#fPj}Nu-I55lqNh5Q zNG@-w568;dFT;WaJj`;%1~ zoX(Mj8)2Ta4cL&L*U}&@x_1MJq7t3tD2N#qO;wmHdI@OWgqkkZxN+I&NB`q2rsr7Z zbp<#Hpc87DjTA04{ZXbAxgsG*dre~A#lRea?VTvd5Q8b)NC(ZBGsX<$+xdRS@Xa?| zFyGY`mn@O`grVlH&d9uuHQ^YyJC-;^e5vME_B(4rj_(%y$mzI0-k9y$elS%>mWe9n z-lHIl=`8c@Q?NNaoDG;I)axaEdtP5A{qgk4QqZ%*SFYPTiu_zF zapgJuTKEoId@qSdeuL7mR(2>m;uAvMc{UcN%DTT&tz8_MLD}F(a9Pm81!-VrtVuzxeqB^EBn`6)-YM^kfLYX4F z%&iiq%O@gdiP)aT{q+?uj;Ce&e$D}=fU#TlaaA}KJK+|d=9spom?Gds8XS zuxtXj&lY`;?LE>(Ps6z-pr+DxBZd>noqlKyW@w|SH`2ah^ELeSx%09IH*?g;#d8i! zI58T1Qb0>O70x+`j(A+DGd7;^h7oTTVXv;iy{m*A@g6ASx%^l_Kh zVQQ3BO9;8)S|ob__^2s6W-8V(l?}&4O13bk51gWu#`-Jfx53K z4h?W4Y_TsyCDU_SqGZHoo`+#9L?{1n^+rjYi>qeNq7BKH)vYV+xo>s zT(vx8c54+rCK86$mthG`-Qn4j3fOj5jh}ErU>ei8zk;`S{=^=dmaFsD60+>~yW6zU z48V(2{d_to=j|ZEfg*gsg)a5YnpRIgrSFbCQI(#e;LYjGpj=SyxRzG`$3cjE_Iqq< zesZDZP;D1({?sr+Uuk*>@c3PTsx+I$AzQ_z(MBTTQCBlF>Y%d2<(U}KnjYVQGi>n<{}8XgVawm} z>o;%u8`b;)ZNE_zor0sj!*A-Q_yNoQT$RzY1bpBrIsrXoK^uN!4_Ynfv8`zoJI9S^e{NZJEBBpls4uU3nb_7g}AMozKju{vkKZYAR znAj6AF#Z?p`WKx0J@P;F{mb$na`s2uUxGd`ld=78^Wq=4(A0q6%Gd%xKu^bSZ}1zu zanQ4TkgUIsX&4#kKd7RO7{Jun#DRc~k)4j;$@q^D0%m504_xT-*9jvlE6X1@Du4B4 zrl+S<{jX7sEc72VOYe6I2$+~YkQl&H`D65-?gD=R9L>jQg5SOf80qQhf4lj2Q1~13 z{YQNNQ~nwMk$(X}Az@)E!H+2Q?M(ka7vc}G{2vOz%=+JTVEThJ|B3W|5Bv|E|I0f3 zyRiR#LD)X>_pgF{ocyC8A7}qv5EjON6oi3|ndyI5kiV+H!uZcBu+TGoRDp&5V~R0< zRDp&5gMKjQsYT|O2E{XdHF?~6g)@ME%>I=Iq^ z{a0{?dLN!XynW2@KZ&JNv{te*{mnu@^!!;H|8)JQ&mZ3!1Pp(KX%YNO*q-Y3 z7hw2nbHe|b4Fe4S7XLpVL;sr{1FVdHX3F0WF_*Mco)s%>j_PyZD}+~anjD$y`L#4y zSazrCL4MLy>992jV|<*A?eyNOVY~664SckUK4q4cctamg3|Nt>FHTC)W$viOg@LK3 zV{=Q7^-s48g@G%lOOJ&kp+`4|Lr-Tqva;=KT3)X^e@Ng6-A|p%QxxHrV z9jR33*reA6Ly8NOQH>qxO2>A0MBiT|9iJbf@%sU;i`TIOks0lV@#Qk*c)a>b25$yR z1IOSQhB*nIj#s;vxdqJui5*|P9GZ1U;#F@hpnjtO!xaS_J&U>?5pw24lQoaZ5^j8J$iwBQmLDC{~2P^(mYnrcQaeEXsfS}BOM=CqMYk- zgSEKRH#JWA0@5{TPTw*cQw+-*4x!vkXf^x6wFhSAJC2bv(t-lMa=!h9q4YRC&c(fYHiDSJ3SHX6} zzYdVAT73FOs95cDgr7)|i(R^4oj}#3if!oylldy&RqB_BHLG^b6nxc6FEC3>$4=g= z54#vqX_!9aNFp{Dx)D)QNPPG3=+>g;oy-{-vc88-|qeVs7Ho1|~@s{gDc>Xr@5Ji&YKS0HqLUaiADI9thOE*te4gA&vm95 zFu5=-p#7s8@_1!_k17<`_u0=HcW*W244??gWh~Y%=3h7WyqzlLJDR;;b>ZG?Axh_Y zi6h}TA7b6)j>s9NYF*Y1!M0k8bo zx;#~%=;FeMf*IaG+LxZ zms=VJI~Y2x9iY+xnk`pmKNYtA!UpS!%}|;}K5N3U6%7N@QY1}&k53i;H;v<~f_uB& z{YpTqSZhawFOG-pEH(>>_Dfx;x^<9jbMLgtHYgUnT|P&n?N(bFFkYabw4wkO{O*X=M`CXaeu^}<{8 z$ir?vT-7XLhhCX4=7p~vMe6O)8N2~!L}&1S6!8>d|HdIB!QEw(7vIc z(0}|{_X+Vtb}2oianMP59oQHr?fnR_birucrOuS+^yqJH8c-|kqM!&{BTTkSMehQ6YAA%q_+#>a3@4M*lRyOpB z6Jl(J9e0Rg=cUdB+ci_9z0-}F!K4?)tS#vtUyHteu9nu%Oy1vg?kaTBc7j{2cckD9 ziP;KNzYEqL=2RI`zdU*4_*Zbs+I3Z?#t`L9 zt1Zz2riMmWCw!pR>ikuP+Prf;r?I&L;kste`j^<+;;(?Hwk8?EVg zpIB;>{Ifh4_PXE^L8X-ASFBfuj*P@#x8eM;2JYb#TnFr%d`HXLgS5fnN(l2Y*|Bp9@1j8kS& zDCXWYUv-Qo67D>99ZP}DptEo1bi3R$p+KiA>7eb~UfaUHZUEHYJ3@&{ZtDJ|ubHq# zfjTY9XL>h7ONd~p+uWgAKvy1rSqWW>Hz4`JTxU03u#41M948{k5A1}+$MIx2^tk<6 zdY=`AHbAG{0RsJgxxJRX6ue&!`Pv>9B9U3y9{6;Q_sQN2U;VlwqX|I@g|)j8IAklF z-NQH)&SG!a)sx&>SBDpz=d2z6=u1g{(Tp6q>DxF<2ZHihddQ{MWJfMht9fD{WVa91u}ZZ3r@g64 zV9ar!lqI$At8fVS6*e2A7nU4?V?9KfIaU8dAEA$ zk(Rt;ni;S#E?P;{6khJ17&9Fsj}?DwIi?}iI_1BK^=9;os-!1pt3Z)@KgUW9p4FAp zp3$BpEUsYJQsW*p3=rsh#qRN)%h%5Th|H^vCw>msVp7oI^SOWo0$FQ!k4lHs8DgPg zgRRPuRYkD)upb6*8G6u|qzqzVt(dO;&{2Djg*ItHe$bZIPo*#YKqoN0-%+xd`l?g#7)QgFvN2MaKl4*^Z2 zuS0^^g$TCp5gJLMC&M>E8hXQp2D$H6P88EL!%1QCLa5jVvn<-SH;`#@IwbcLr1JqT z^~Z6o9S8+o=$Q_S?MU`>wJf2uu4XC3!lEdYZXt*2fGH_?_2{@XH{hG1DJqIzQ+CPHi zw`mQhwOG!y5g1`-M@5 zTh?y7P<}PV86kky|H!QCf;6q*>R=FyG&Vg%%G?^oEpMClBF9Yso{_%j?lUV-q%>R- zd3T?yJgcTHvg5BA&F~`cCHuJ1l#8@4fH_d(d$Z0Z;e29o$?1iXAwFp;T+MR|N?h?` z86#NjL}Ka^aPdQl{$0dD!Eb6h`u&}f;Q=DxtEylkmF7h`}` zP0WPx%f?r6cDvR7@YAr+pG{5=$CZ#$CWSAuu2&tyB$&1scktzr9O9SdBoq}6K_@?@ zj~9P^!qKV;q}Dh?Y=I?))jJeK!Hp9mut$*MpC%**Zo-x^*y#pQ_tP{0AD^u9!!!JK z%$V9;DXlL=QVVx8I&lpNAp8!@k-{yRdS%S8Q`v@OZ*i48uvW*}bp%LL4MDxuYw5F68pr1eI`wqTyZ>__pb}%QIbvrk;6-*=Z zVp)u49l}now;$e>ZI81HH#Hk@QLns+FeS}@TuUM<1QhG(ES{r?MhwHK$RYqoH-y)aQ)<-z${V9PsOLi6n1wrAW0;;N%vqT5=|hl!Dwp9QBc%6l&90xj7xsE zDOQXp+l#2jl#*k@*VM&@w1(Z|5%AI{N<9k{PI)%S9 zC?EtDI=M_1;FF$o zj4_IdLyQUgd)h|&dj`??lxz=Wrkwdm)j%ez!h5#iJ+cFu ztI@5ookiFVSQA(axh!EF;a_znj^HC8+SbYhX)#m;pt%+lnsvl>7@b{!Wzi=>z6~D8 zJ5BcZWf_t!gt5By%gv@9ybvkfVE~DeroU$CE`VC{PvK z!S1#wa%5%?KW3D)GGk6-?(}OqKN_AHi~-w?v}~ax({OI}VurwtCp-w`NHW7DB7eI; z;p}E3b6iv?k-dO#4G*(2CgF>!pfymZ(UBok$W|3A>+B(nt7K}lOQmwwj6=6P3TT9J z=TSUO@R3&`&DYP?AGmlCQF^B3me>&^j!H8I^5)Y>tW-#m;QyezT{CfR@=>&;^&b19 z0tG>eDs1-8`pl?t;I4rIQ`9!8DC-3S{*_P)bs-$V)6L&fVjNlJ0wB4iNrt14WFwTF zieT}frg}Jchi}O}1g>xhfB5&1sk%Q zJ_oa0MFfRfIKN;$t~IF{0frsiI1?x&XNVN90pl<#G0YG(UZ+6vZrRZyvmxGkUk2J zQDc;c7tOUayZ%iZHt)QJV~X4y+LK>k5kzmVCygtDaz?0ldcCNF)t7^VrCR@(4aK)B zz?)@$X}~?8y26sz^wqTtCqnhTn#BN4t;v!Tu_)|?pA2HM1@lOK^J`gNXwZ;;g&AQ- zG+_kUav>_axfsb}-8@VWA6bss`dtqcLaO1n1&L@P32UgHE2({yF%x&-J&ZJRA81bt(ItvH0;+YyE z^Vzp+0b7$ErKf;v-p4U@M}5nr`P;ZbL;k z(&YfvVbe92nrX4{#j$(Nd5S5uGlz8ytxcpZQ4M+Ae1)AJuky)Wz)F*gYxoo#m$k)etTd|hlN#rO{}LObEtrLmgg*3b6TrR}JmSAL<>Ai?N*R>Ytoq_XqZeF8zLjk>D?0aV! zvoPe_Qa(irdOg6hOn*fmppx_~y-nE1QlqXbOOo(d_2QFZklv1-y?%CqUsWTz?aYiUt(hOj zp6hk#tMPf0d_LLRIr+m{fEQ@C7j3h0S=CvV?*L#}P1Jnm8x$)bxg*`DEr8B+HRwDV zjA3sz3Icr7%YSUEM?p6pQ}-a6^E;%)cg6-n3lV3{#(YPp8PdR4R?|q$;Gw!w{QeF0 zDi?EEzCr*Ac!>vqBDAs#iMRc|^iTvs#AyoV=O*(Z-ix$TchAeeSK;@8M7Yi|Hc^gKYd^T2@3?EF*MK!r{sQdCu%kLx}p=|Nt~G$!-T z*d3jO)}a(DqNbYIpKhI<$*>+x2>ImljR@7$hOWkEPN8oD2`VF3+?ibHFf7EiX}sLh`F z&<(JT4_nTbmapF_WW~AMPjV-Mf zsFq}D`~pS<=)sIlt3=#8;cTl8ji>!ij*wf=8D^JXOAQ0$`p zWuXJ?OV@C0k>VM8xGk=*>>N$RGVA^479=fQzVv)5I0^DW9uo!-W=|B!H^-EZyPdQ` zUEzw)^XBYJM&odL5(G~&JryAS@SP8_j6IUz+6h(BU08Xa6$32IBrc0QB5-IRUel!U z(YFs4yunH&3IU>_T=dk0LY@7ax%zX|}L3r0$dFBhldZ)p~ z{Cw~EbAOp!#;Mr-Y=PVO4aIe51AMws71cX`@Yy#xp?2+N9xmAU-KLs0GIxYZY@W9E zlrdCMR4av61(u^zob1QU>pCs)5Be`X=-w_=xStmlQy~(s=aVI1NA~2wB+Ij&L+*=j zT#*)L&Ro?;6k%+-ZBeUrL{cPb2(d@N(jo?puFIfJLl23t$y!FYM!9D&j9in4!0mxM zmQ=y7-fw!$UH_N66&U_wJHY>yob0c6cmL0DGRA-7WdGbQ@IP}hHU=iP-^2dJ$$n~S z*kdrql<#^0WOtyZy^ zFl<^ct&(R)b+PzzFK@x%E)MOy8{M7l-O0UPE)TD48k=4#-8D3M+nT)}o@Yuo@SJ4n ztk*X@+c{R(yuI$q*g3dp-fkb{X5zwig;kUQBrwV<04*D3r|QLXJl>~c{LqO={3U(O zz0h<`9P13cbF30u>dx@BSMxm8aqY%Z#F<#T1A}n zCJ^2-ekuuT+2cNCoo{r8dj~FS64PjyTK+6Qfj{!_#Zj*5fycO-N0|s~l?rRMP#Q{g z`K4p7o}l5*^{aV2@*Bwo@exQE{!ium%#NR=6IYREss8d6v7tZ(6V=bx6Ans|n+h)Ag zk{eUm6mh=UL<1gPZn?QMrGF6T$ODuVA_$nu^3YRjI7*F;kGElYU|-0;Df4;3lzBU_ z9`kb5+O4O2{HeSB3x@a=s>z|^_}QW$NFbOzG`D(z6i@-;&3Yu2AeIQSUqTTdTa_gk z!&vY++$LzWRGw9_znVsmf@i8o#M|9T^4QCjHJ_wS|N_3Jqe9cr1aMC~24Ddv38 zxs4_xGQx1=HA3>L-F2T6Pq0;^Q@pSq^q!>2rVDz7uoYU9DM__Nq?*eO*Bp|Siu+9z zBpi?#QdE-rYiWEu4X0JpGb~YM$9y9aEm5ahGk$KUc@BoD!xLDa!J#ltMFX{SnX??^ zREX>K*5RSJ%~^-I1AbPqWV_xB1XdL+HCUy)>ZO1KJq?*hWFf-(e+OY?BQqiBhG7|E zZ9-^92%vDVK{w%fU|r|pxo4?7h9M8Xo*Kp5e{K$?h5{`u|4I1z+#38Mh z9XnG%tHf-I*KOj;L?6~gNY^HAu0CPPLnki1&}A~0FmotsZLFI6rLuozfLg;6nl#xd zR#?-#{nYVSNsw1(HKFW969KWxN_0-}(0|8R~>k>5DC?%*G^cg5b^89xcaIU|VFDj`1#pWPfhv z$Z_j$YX52~b?@*fYyiWWUc6Mhz*<@^1#J54CZkR?L4&k@%!W`WDe^2g^R+%faQa5L zK0_fy`2) zTi8`^ctU(Gl47SnNFX#O&u}V*muoIm6)@|`IZrDHYj5WOS0n(^k;hr;8cPS-rQP0* zpEo#)Pna(&laqkHGuzrF9NOeX(95n6)@ocM=(E3eOrv0i`Y`mA7sV%ka+W|l4tWaV zw1rkf8baajQ-o&=W@13hMFAy8=pbRSR)YL6;uhAM%c>}^*t0j+`Ba$9B<8$Br%ljY zFv8gzULd_H90WP}ByZ1;KrXF=c`8R^bQ6Ya+aN@PM=V!!pwjWYAF7MRog%*LoaI7?e&23t}=F zzg86_YGKn~6@k6qmpW{XGbfnPBwiuL49FEDs|YscA#bsCQrSk6lV16QlvO4I%e56g|yfcY$ozA`%FYcos(j% z4y}+M1&|B|D)`Y-L{c&N4j}fYP>h%F&Lg>j{Yjmz8Rx6A3Bko9l-mhjS36Kh?E~il z6WH*aPG^ri0*BNklovr%pEC#*gsa_lzOoNgaF4gXAu`PpbkC8f;OqR$?yMD+-?t=2 z@5a(vd(e*^8D|MuviBK91bfDH16C0g&|izO9~XfDlKx6>D}hr2PlWWf0JC-S##~Ef zxZplTMe5@fuK74i^o|+~no@AUL_(s$m>xS_&h!dIMT+$+;}ut=J%K5k^6qh=k*BL) zn-ekRlT5tH;9~mD^8kGEQr$5+!Me2u>ffUGV9$e>T3Hg z!&CK7)yvkf2?t_`B08{AG^BZlA(3(zMjL&c1Fg7WFiA*Gwi`rU7<66GCA~#a0pu}i zwQl-G600^yIaF_l;6I9tkBRMbm8B^(2I|o1d>~we0_hoBDQ;o}{MA-1p)Q?6Qv>`vERTWglPyp#Gw*L=d|OK=x*bi{`M z=1=Ld(uwVH+jd^>JhyphnPhfxK&oyVs`7M#o%u4`c3VT5bo1;UxXU$AL#GW-15!Vb zCHwy{_s&7GeO>xz)vc;qRkv*0wr$(CZQHnI+qP}nwrz8&zi;$RzrX2@iHVtsnAj&X zcbq&s^ThdQuUMb8o@YHx&$YG-cSm=iv!6QXg%AyiW;tUp?rHE5@@PTDhJ4fY6SbSV zz)3-AS^`Af`2g`&f?Gr->6iZc7P={OR;djQODF-)j*)>P%gPKl+-TP6`x;!3Od1LRYqk22hCvcI7XI386SW6gwZeRy=eudP2QRk?K?So9+%XzImliPy! zbfhlS{6(l@52`w0^wwl=%-$D|u?tg|bnVeMYN*@c9FQDIsF|}V zvs6s*^SK&4B|I4NEMi_XrXxvfHO#NE?z>oFF2pXA5OYgWUzH8?3TiHkQcAPDCc#%__wrU$S|a+!9QMoY z#jZwNG9E~8D^8yce#&W%IQ?jQ5xoLRlhW5b0--23gp!Wj zd&V1(rn_8b9CqBD$r!75ZIbx$`R8-7k3uwmVI`oU8mb^Hya?o&nMRj(=^@V#1Q$Hk z_=Pp~EWfWKi^@r(@uG^N3trkR`DnXDZmX(rcaWSIaZHcG4v0%XgW9rEFi904l(@Y# z6DZYDr&xrG(B~V7P`c2qT0ZJSQN0^As!a`E z3|yqF8=H}!lp;}Bz|Bup6^~4K}855+~+b-kkmbmjf(dinj1hN zYV%1KVazY4%4xb!u&lSPwij&HmRqhXl=oDe>H;P%NG6@|T-;5F5{o${s%a1b$F8hi z<*PWP8tLLxjw)qL5g*1h@sc-rV0of*H{vkCYy%g*C^Z*n+ltiXV!3t!?(}!>HLmVG zTACLW64Me>6AIA(au zkg`GtHkvrTz|54h8W6%ekm07W$xS%$l5{@m4|NUwcPpz!Aj)2xZhK)9Y zrPHu8wCDj^%koLL$%l@xSJvhg?Q4roBF9|5PpkQp*&3p|Cxn8fxz&xtiRyj0gi^Lbe@}Hq+r}-skrOg{8$9$;D4R z`|)aED4bHEU0Bg}VNp7)T?G|F2`@&F@jl=t%WYQzk)U& z_q&pFjgn9ZZ^0HtYz_HiPERMU1(lyxs3c-$KS>b_sPxf+&Nh&Mb%+3b?iqW4oxMIr zu|R)LKoI`@y@Y4~D^^kAZ_|fqd=%*yab{|S2NeOivSeLDoJZc;@4c(-nLI+tMy=H$ z!Jjak7s!v*pEQkSN{aT`7WNCq5-NUwhrV!Akf$mwy#TL7>Y!KPptqfTNVsnEMXlI zzabVJ6p{&;$;T0Gu&XzVUJ8)nd?KAmH|FpSb5Ivk^$tLAC`JTbhhF%e)KIdygKEAO z%#wUXE0Kg4*fV#e-8t5m7c*e3)HQfd3V!Le`%^JxB4NylbpJuI;vIi-AS`Q=|FEL2 zU(tO!Z;5A!QZA#w$4`+?p*cSYblzt}> z{|IPyROnqvSh_tOBwaCP&{h>;e!A+_3OT?NO#kYt(dP5SlT4^T zgPTi1Xnb%*5S17mf#iQ{jHjFFy|NmOsQtm4r=w)MhUuR40_-mTHQ0BpW*#>i*&;TQ zIo_oobLdsj+A;U+$*-PDa(mY|1xKXCKZ2JO(b~t+PYG+s+Cw`?^cJm{+ z(dAjLaF%QAnjs`;)R$q3nu&mxEnZk*!Gf2D&dETJM{M}z9uY>EoZ1*pL;dkI8v-eD zZx{p@>Wct#K!qL*P^Sto{>&iR{USNJU1up>t+|-vEfyUOr7RC~i>w4vNUw`F*vmZ~ zYIg8{MA!G;aq}6MT4g_Z#pFTaZa@G!4IgJVtTtE5lD~_N-U(ij z@Y)}H&Tg-b^lKg3^b-9;6>+=VTBMj8eD;yRsK0E$2S+m1LQRLMIZ5bj90;_7aa*x< zK$TGuyHgj)uh~0Es^JT4EkX_SN!V9Rxs)#GwM%1C{DcRr(e>XyiLs3Ymo*m4Rad~^ zJb8Ii@|8m*V4mCcyIf15Dk$EK5GpCBdcW0tPtjW@ir(rX}$$GRXk?&3sJ3);&7 z1)35rm%Xo2s94AuC$})HZI@XtkD!<1GPg_bdc)2-k6$}AW{Iyu^rT7c+dE4#jVh6s zbRoUu4Fi=@K}>p)NcHgpw}GW&qUtH#p( zxLcs(dQt}*{@L{h$G5s>fO``<3mU3XpP$^Hmf0}->ozQpU}YzXpKBjx^D!g=_Jv zy4BZ_)e+Mr1?Ee!M@=Sk%_SQ`Cn;OCffV4SoQF?cp~q>-Xje21p=evzfwxk6#l;!7 zFrVPRi9~%!nkX=Zb|pX-?NrIApr97;P<#RG)NP=Pcy)dP5#t6@B}#DOEPPn4x*|D$ zKlb&#P5nXpVtIK5tITe0V{W(C#m=s5E~ZI(%_7`1tIP_D^w5vXtG%LHVmDT|--_KI zEbCB8;N%(w&+3`@U6wiu-uWibu9d!cC_KJp-rkn7{;+8T%kMEnZtU6sCFw>LBB7~f zH;+Bnsj^Pe!zy8KD@{Sa`GGjTl*ESt_EnXb3Z~q`V*C)eKE}uJQySlZvx&jzkUqV{ zGp)wb&In)6e$QlfmM*8wz&Yu-M=66%ahNh${({(Sm7QAM7dUjaPxNOU0Y$Ba)$8`m z(n|F)UdwN;g4R=~KRsBcXIDkL#)(F%I3TdH9}*SPgs*9gQ)I+UVZxveOSc2fvVy_z zuD*#WoXBUy`Yx36r4!}_4sN=G;5DAoZ6|S|WjnvFi*>t##yhQ@3_AVfWEzkQEitsL z@Hhk~K2%Z^-Pxx()~W`CcCKS9EC11vog5b6MSSWj@48DpjSF0*d(HTqM5>2vt9G@O z3}Bi@Sp$lCjK{4Nd@u>w>1JbhjldyV} z>e)F&-LN{Hv7ioI8a^g%j319{4fF**lP?E%7%i!8xy%nsrFimc_S zkPp;Ot;(vjOjM1}I?)(#5wT`CVP~`g4keU+DJ4h*!YA7_lcR&R;@x$8wNkB+&V#$q zk0jL*;iy3{j58geE2P4YM>%__qTS-ZAjh9q$eXe#D{THoW-3l1MxI|HQdt^N+y6bN z4sii;!R?%6O4V7Zt}*N1-=O2atv3-Cv3RP<&PnS6z{0836M1~}NNe&i__R2hEvJ)9 zn#pcabsFlc))o1<#zrDqx-Md^%ZYUzHDeA*hkAJ`iU*v# z^0y>RQk@;ba8_})Fx6zT1MR&CmvVgx?W}>6HLC;t5XeENZ1f{POD8zS+4Ll0Kv)hG zEdJM<*?Rm4=XSgw{LAKW6!ShQe_@O&OM@a^B5X>J!mp(gWzTADt8Y-3YL%8L%~T$T z#i$Em3p?Q%_xq;d5$A?K&it_SAduB;eM~acAj=(>xLBca418?*e2$Ixx{sCl(3I{U z6$;Q|4f7pZ`_ny^m8yap%zPP4!ObyG=JkzB!KFJpqJAg zPw#;94JqdD4l~+md*S3H+P)k8bpRkX*xue*Q-c(hdgUO3#TlHFg6QteSuqq zPPUg+RF{;nCCA_?C99PYvnU^I=308Afk-RoR$0az)ix+fK!W;jQcE-Qe{% zX;+7*Ub-FImgV=wVZ?Gsh3w$!g{C1X>K&O)@%#OYy?3tc28#!lV=IPCJZEBu)eQe) zrSku^iL>=|C$RcWzR(o5slYicAS zz^`7zi;V$VNNE|S;q@>m@&B;W&wsH}sQ-hNUP>{k;TBvfR&U1qrr0S{f?N{E|C@?! zL=?#?Efb7;Mf12;)2r<;|JmFYN1*lT3}x{!yYqJGNKEpKKH1&Vhy(GGa3l9CLuosn ztQ-PJ^3e&f^v0h~wmp)_0`7c>6lq)sdGH+2qr<0rbz|F#WmHP3NiteKzxK#S6)6`B z$DCPL|3T1Bso@PFc{nKP%Xi`%-p#64P_XMI>p%nQmy_TZw&U?pyYt+s@h$3auIO&T zF0tVl7ZyYsHz}uFD~C4TwcA|d{&NEif*ZrSKa7|rIJ9Lt9o&G0-$u3Uq~zr*`CEDv zPTw1G4Ahe(DRKd*=$Ni7Y)soYJNt7xp|2a70n?#W(7SX%l-axc>iH49=p7L-Z2pqc zRi2>PP7?PUIBSh<(3e&G*TFLkXvB$NCTs4?x2RkF_1~8-FS=f%>g0=#pJ zDwBb7Ci@^fdxIt{sQ9rO^t@bI(YC{!sKK{`(Xo!YssY+J$4BuN)`q$qjDcSnb?C1I z@-_E4d1e5!2ul;dsP;IRb^=4+_zwCn-Wl}cC9f^%%m-uwn-5kM0U=bt zny|JN9%>sfq(t->I=0t5W<A$k-eXPO^w3)bnbDk;;s1NI3Ptow~Tea{O?PwXk;DxZCJrxhPR zsbLTK!2)BRZB_4BjoWqZ#aL?EWM#lB4fl#%Ph-!NSI+fh`a0YY|0eLh4ilOj5Jydlk!>7%>>u``w%_K8n%m<1Lj3fZZl~%loP7NJJgDn zlhLNzrv%DoQ)7C?L#sxZaUyx0D3@%3Zj=|ZC}W?U@C|IO82KD~&|ljK++e_P$Q3?^ zfMIt}t4N}RGMsC@0d!8SOQ2v>i{-;eEv$QDV0`mHu}Z$pH72nk9nb~)7wa88Ii*NE z$&t;a?wzs&{IqjBoj5ohdbyM$Ae{~P)M_cqi)6Cuo<-QY^bWPEV*9#{Wfs=Fpia9Q zb}h_Fl{fbQn2a=H+h)D^*IMiKmL`YDA0fW%Nki*AX_2K|xC|-p`{4%on4QG^M%BD zA}lPH7}7~kOS@wb7H)52&N+h?U3PtqB+mN9w--7mPm_WspfaP?crR@Gq_Uq2XRdU# z#%km80|Lw!83NhkK;t84EAaeLN$Z3wH+2pt9)IfHT$v9yEc)Ps*PN+l3zT8@AxXf7 zK~Q*Ka3iY9hK9i!p!sO^;mrif)rO?EE0Aqu!;45*AV15SFwct5M^mk-8iM;DDmOoo zoO6jmjXNv6=h01zTtqgkAG%~gHhweiq5m{M17+A|HGZ$Ju2bQ|ETiHlbXKj?`qI{} z7$D0&;A*-2;?UEfu5Izj)nV&|nqYubqNjN-y? z76E5YJW)G6vz%)95!ljA84_PvMi0Mrf=2Ks)TuP^eYvTEA}YZ!`N^>n{_iQ zDrmKIWfQ_OkUUjOq&xj`_YWh=B1#gWf?)D4%Hkne@@*V~yHZ6Ipf8HZF(^f}271A^ z)DC@Uri7qS4b|cY@ zB2&;}sa@((M9dQ1xrY>4v;dqpKR2OLx=zUs4g+2YVl;UDVQ3%Ovxu^j6ZzhcP}Hi$ZkRBGh8aR}fM2=Kj z6VXwYkYFR-sozZ*f1W9r%DTQ^zy3%9e6ikpV6PwDRJu((X3EofPr0`O1knq4Hwq=2 z6N$@d_*F*T>YZi>@g^}hlm`@^f-Yig;(0tj3`9D$))b9v3*(rYUBQW%NH<`rkLB=m z+{P_T;AB(#1P%UKou($_@e;h$#pdM67|v$Gs=snASNR(28KjFOTJh!$Sqq*G*45Kg z$AXyaLwhqCV+Y0PA)-45!__^fnn^K&z1q)=Z(PQ4%$(?)cTt#!4O{@%m18B<_-fM3 z$387axxXiCF#sLPu<)w+Q&j-6%mTZvq0XxXb4AM`+AGwL0UzYdB~iH7#0mv^qA58w znUQOt*ZLqJ2-SzD0M@Y2>Cygl|2G=_k@m7_QYv436@H@5;ORVQajdN{2gKocis4$E zh7SfF#OSYs{c`zy4$m9fK2M$Lc@9-61E{qS{rQ_md4IzXk^~L~RRI0S%-(CJ?kVdk zYo<0iU;J_tZp8GGffidW50&57FJG@yR<5(MZchrL?Zq-_7=~}MoQ66y&pjfu$ z-_*6`P{D0s(QA{rW!Kc225-Q<1iCoEv_Y-jR8JwIRxMWV$UidCdEWjl()Xh@?P8UT zec*Rbqx2pHm$bKLg3G<{#;b8{4r^x(V}1iwI%68 z2j?ISE=)|t&s}*Ji;f3}AJ%Hf7pvnvVkR0`GNLiFCL0y%GYb!{9Sy9dio;MSUnWF_ zHDVx_Unr_AD^?uWG$FDBwr;FsPMhi#fvdB`KQ>OYT48%B(*cWEJ^H(i4Vn4~ayWej z#yX#anyIUxdMXhPc%IYy;~9&S_0=y;nOS_I-enPsIbZLOPjlD0M(`OMt<-*UYrlV0 zY1L65T#JIbT2Fir#uXP2wI!xJf2IDLg?Rpeb1$dWikny*wBa zEV2UHx%katU+U*g$|he_L=CcT_qPnr$Xv=cj#MG^P+)?mBq}u-hWq=M8p;GbXNsNc z>Kd$jM5-=}sYiXw0tDj)Oo_Ev-$h*fcuES3O9l<)!^`KidAB4?F_$iLm-D4BP8#06&Z%`37Z4~Sq^M(4yT_|8 zAE`kcyqXNAJkGOEx-@!of=)_zHyR9wz7ia^U03sLf3u;7j{6n(-(7}M#~5bfsYQW4 z*~fAz_l6p{2QRUfW@ykPkaINVe~*fMxT~45q&)KZ*?@p#^>cPE>MIF8_6@;V&(_R} z*Zu`(R1MjMyGSGB@euZr6Jq*lrN$#{b9z4Dzc62k&~D5H(j=5g(SmGdv0L2AZ!Jy^ zH-j!_pXfYcb7ZDkZMphukKjATQ~aSGvV9#8a=QFUVvnT0ZE~9gXM7b@pT}o%%a>v}uMSSNMyX6sqmG2)Zu4t!LR`Sxw zQ_IFc738nQm8yC!pq%8WUT^faWmT8pK;#dwSQBMFoNnlesi2Tx^g6=9N_j5#ZX(OthIH<{7!%} zpQ}o4^kgTBv3Z}!ek*?(0_*@TH(Px$bf60oYh{8!w(3i;ul=#Kb<LI zY+2Exe)XIM9T8QMskZ~Kb(@Q0q*vdZyH21@iVM;MYF9)Q1uNM1!S1#;R685aNWsMF zwKfz`NP~rXW;Tr9N-#_Ga~1v~(eDN=rLU*Xh1XOF zVMFu&q?qBmwn@WeyApKc4PN_%m1q!G&j)WAadK!Aeo@J9x9cS&Y7HPtu0Je+?UVwY z%DpbF1Or|QP-RAA%)+mo8^0ClKmQ{gS6f6Ogto~N^Tqpw4KAEqSIL~dBqF1Lm%whY3EPY^Az`n`eb+;6)pYG$AA=%8 z-`dBn>Cus2_df-=fR4nQVu&N%KkaH(a{OP+7MyEVc;D?M2d%d89ExZm81F!9k%^rD(Ij#t*{oAe?vQyA>uxuF@|GHbCES=xL z;^zbDMh;{>px<0cvSK}-M2Sy`ZuR4A3c=qhJKVcoYteUPgICds-Gr<6S92eJQAeH8 zrKhw#oG(;R7!KWKbKk6<`|1Hwu=F*B+1`W*G)l1&_`M?S2frwIg1NIIXQSTw>Xl`T zU=M+E^0>PZo2>ugN!t~3yf2u!v6O?ULJR~L?N#;Xh}I+Lw}nfNEO|eM!y~`xcXV-N znSKQsT*bw#ox)6tbp1RCM6v?(^c}X5Ws^XhQa>{Rl}LD(V6oeUBN(WGcur;P4tXht z^7H-WjHo1dDLaS(mJQ6v|Kdk`N%BU&Hy`BCfdog7_TW@NV>U5f;WrG-92^OaG8zYa z#W@wpI;gn7$G^T%VX+&-a=TsKaphqgh7+VF+HF|!T~_c{eM_WWpl&%I54w9s5y4Jk zbYetpJ_r6MH)}|bs8o&7ePi0kzUkS5>1^v}RmUFR))|EYM#X^JdJWJ_$Pn%OvSnv2 zbV6KC;9XwUzjCp}5*9s>`d-5Z2IL7%Krb2q`;0V(`rR5Jw`X-(M>k;9{$bzvdBR&P zu0({mW9H$_OMOEa&!KPro%ZHc%d(%z0oOBuN5mPhDp*|mA*bq+nt@k|;_(HBpxC*5 zpjgClpMa@RIIJ%9{OCE&c`T#0J4)@NjEoTrRQ}YG%Co%wYG8FKv%64MvSCJP-;_*r zY&tJcS5$rAnPG7?HApnv%&E3H-DK`nrEV)bYN!Xmf9=RM6*Qvd9q~n;vYBHmS2g~M zcnVESxRFO?zcP`Qy);p*Es{Y2r-W|UOmWrg6X>5FqWdWIMvr1YK@~3C^KK(64hW6S zCHkf%EDs>q`$Bwyt=?CGQWb7!A*EvPjnnRBLQj7ku*S#W!a z_V3lVuL&s4njD=^eQy)Iw5y<%K~O$=>;hM6TTToaE@+ZK3&CRZmIYDV1vnKIx&j+s z&Jg9^JBG_Cfjddt8sW8vJUChKx1GP((yQ!k`2ptBF5IYIW3?U*_exVX+sNSp8)cUD za>2N$bf$xnaA95kqNIL-GP7)3N`k$Gxb}g4pR69af&4MdGq!gxZP0^2(bXaI*6HdK z_OY7;&=B=9syvz8AD*eg4s@DaMGXd)jvJDurkF^U_9RurmeP1mKLZ=Eo8x8}HO@2ApN7i`{! zicJZ!{jFwat$n8gVaiu(r8nVM4Z7}t@QTgr($_q8SOS(NT&6E-?ktfhiv;Rxz+A&R zREe=%3{>MxROf}-z0UhC>Zr+Avda>5 zX@{H&kRbr6E&>~N6X?nv;N8Ca&Z)tL9PcTG`bFGsjP5MCrN58wf2vWL<<2L@QleRb zqw!XWm>Z#Ec8V&A8AhcGq$4XOk7OraL;$@kvOOo_;L(Q#z~A}(QwRO!4h*J7wLu|P zA^e27z-}UBzFH1Znl3q*Oe2rq?cub~r|*3I*Fha-!i+~uk%f@C{*}R72cK+q+sZPo za7{_V-4N1BBMrPiw{<{>eWLa;g(@;A+*YXAWQ6P<qVaaH!qlaUl(Js6V(}YuF zg|r2aG?vB z6F7TRa)$Foy7rTpJL=*yb)_(#mKUDx7M%*5CO$XSWNQJQ>J{(i5OkmMvx&ce5jNaO zkVs%rKel8Dj9z63CjO!?onCBTyD3e~1c2gWT;4BC1Sm?^uAy>v&Ran*&<6P$`(^fZ zaJu;&@PB~}v3d6XS)*GoFk^giKTGxW~NCBs2ct-xu4 zx?sZFU*=ZUT5b5?n!zX+Yh^#R@LSgVj`a^OHnJGk)Q8h9N7|3;6nPh>@_S}$gc$s; zqY$FA$1d*C^IDsf7!WW(hgvZu|>AU$6VXI zcf*h+A=7^hjY#ju7_S~Bn?#GwD>O#$L{1iMz~P$X+SYWBUcEuUS1N$hf{Ba0=ZHhp z6kl2vaNiI%7JndwP#_mlEQEZ{@Sn^pQO<~l`okag`f+Qufg2RAMk5;y!{Z?xCa^9q zZfq8^54=^U`S(;sDbe!>;Y_YnmF^Mk=gXpTV9qM+ieQM%Qk8^TO81+nHEsD0eDn|RVn(}uXplbS zFD1kF;Gk2E5M29Rt!J^o4B;(?O1k>M%|}Sux_jgd{g+JFcBVjqmG%D6&i6~s0A#Lb3>9}Ia{IG%q)X0L zZ{zpgxh_P*=@RbF`egnEA9YiFR|P?7tC-ABFhLQidsV?6wmT7l^dQDYu`L<*+e4$EqMIL5cS^#T>qbgMZ^$e;n2Upv>8Z)%7mbWKl z6GX)l8p2>enqpmySuwd8?rj_H`>k5rv^0}1CevT_)TpbjlUXkIKg{nRhCj~E=k2{~ zTQn+B4$bSm-;=O1G3$M)bz#e6IH+ML_M9 ze;P|X!=UR{wF*pVUOq6f4(j82^LvJYd007(W^pdgXx=@FcY1ZY=XIzVY*!wWJ1RU4 zzQm2`dX**$n^CVJ^rJTfiv^1eO8KR+zL85;t4)qcio1nDIa9TSGNz|swq5e>E}=zZ z2j#C3ky6W9pQCt@z2xxN*zlLHmC}sul7c(jqiZq1o8pOHmW zq+Jg9!In-E=P(@#k^Ta$7~zv)CZpuSKTDM#akiLm+xaZZpZ3W6=;%jTmsVBh1vobO znRg9!e-7L*3`YOtWbV?Wl~lo47YF@o@llV#+Ow{TBr7rM2Bdi~>)mohaID7c?^(Bs z?g^DKoxvATKVSsl4h2OiXY_Y+0*(K0OSyYOHZR)H!(d6eAFW!XsmKD;Pk;Qbb$Bm} zK*S~f{!!Jxd%}J@4MwgV(WE3@3;_|54jkxvr8@#MZ>j?rv#b8ampw@X`+yTQEu$(A zm~K!-s*5MvofxPOZ3Y?PpN^m8ztQoTE0V49hDSM)LSc&|8AeQ!8;ac>F}Hd;y1g?W z6M#n&R4*zJAUMIW{4gSIv@P8l<)qg<7T;T0#HGEG_meicj4nGx@TM%OnllMIjPKGj zd1>{BfA?*4HY0uXeO8;^!<-7^u!si6g?Z1mfVwS-gf;0DiH{01SgR;ZfxbKA3hw~`mkZPhIzPU9I~{5gMa7QbY;b8q2hiZ!%BQier08gOYJ`i(l=-^# zjhGN5A%Pqv4q8zLT7hgQj;9zIEAyKuI}er?K5Aog9^9Xl?568<1RvrEWVXu{dv33; z@z)0$QxuON{{;0kO+X3}@_8$=CShXCLDtFW;ULfU{^;zj7c?39Ure91FNoQ&MLt>P z^NY49B#5e_ny&9+_Y5`Sih$>W(NS z9OBe-0_ySuLR;MnruGfV=wh%Y$Hx|&?*5|1Zz1*|E8=uip5bqQ3D6`FTM$dlnEmGe z?1pvq$8}bupGj>3fqluIh6&0hE;GX^qGs?Hi4OBmIqH^z>ZTr!WKdF*O#rn>?lC?) z4f(E)T=`3?SQO)5v@!eBZP%NN-gzTc^x$r9$rj_k`~gX{TrR|I`ziW^S_`r;`r(pY zedmaq)4oM0ForBhgEbST<6QtjEaW4oX@52o3eir!jgZEB3@_;nM_Zu={G{ru0mw-jAhU!vr3J)0cE>${ zpNTm$!$=TYi?tfYT=iKxq)*zWyi6=Cm`tKr5pntpUh9CiFFLMuZ(_U_)nsVC^OR_R z60G(j+vYX|dIyP`V0!XtFQ3)QZs2w_Hq?6|UQ*RocaLy)7|}_`biv?B!4&w@A`8q6 zTup`1B$3gF)cJ=w9ucjXqV3_T8L8s)bim4jUGGPxwb*I%xAG=1-|C;hNu(waev8RV z{NePpr354s7&uEf2X3k&`93Ypw>q2~YJioa(taqErQ#y9*`y{64&IVcC5DKVV0Ps( zkWI`qqfLKoX?!6TP!$XQ;j{F=tEEvRMN+{nn6z=Q7PQLHIA;OOc#QE{k;!gN4q#eb z2sPa6egh~Nq9k7!zb1YvMPRZjDvh!E6Qim^ehfHMTiM^3k4@@6-PMj6z3e8s#o`FQ znkrXP&G~2L#-1reTWd3#pJWpmt+CNWLLRd1xq9^K3rm}a< zy7F0>#SRs(TGa?yV3jj=D7I+q6E(IY!s>@gOW7a0y0Q6{gML&;y);=hki0tBjx+Jl zJ;(Zx+pq|HC=B918x60tiqf-dtB@>g0mGsbd97NLrd8-L3iTRw<+{Lb$%8~gU~f62 zIC;@fQl8Ocp_rR2w5lVWT?vom=De_kZ`PmrBv0gOmg`H_2S5R-sg%N0qFh11lY8y! zPJ%f`9hRC(2|w>jcdKt@LqkierNCsbu7BoRSri0qhHFtyXiE296=wvIGUjqNgit@+ z^}570Q53LC7bDGdxxg)jFN_Gk>trZ>_9VR(;VD+9HvBb*DFlbZSFLI^7xKyhes1W) zrX*`CXeB1r2N(CfONN%AKP{{vu~0~qFp=g7`#7O~enmHezI3B&hVO1^baznmxj(u0 zd|wA1C(pQlw@E`_DWf=yNIh5u&-DWai$jXN6jVq)i z$%kwFW9lLxr68t&D`;eC=4@oIr*CQW)A>ci=j3Q=V^1n%WoGGyD`;<|_j69*=i|o( zhV<(jKnlPNzyQD=zy`qK=Vc7w2v7xp3!w5dw+Ar%nb8B#0?+}_{^uey8*9Ozn4eUT zot~DCiI$a~g_ebmg_enemY#%`mgMI$DI3H8iz{U9Z48|ZjQ;Qa{eKPA|1k&owd(z5)_EFF#PX?`qE9E}8x{=?qm#~jAm#L*O&j*X7_--Gx= z)pctGF<38=J)Ad~jm76A*tx4;>H|V>e0zF>0b<4ig8BseqBqYT=H?eGdKb5de!!K1 z3Jx5_ZRO={()(q#LmUX@w_CD!`vG<>53?=se`Q>=puQFX=TiKV1cyilW|ym$p4 zzUylS&MW?v;Pkf89Kw-p^=CD_NeK72QDhwrjViRHWt0h36^=~7L3o6o9l?~Z`z`PU zc!0Sc>ZX6jt!E3uH?>0rXjiDqx`reH_(zALOGFai03WDcZ^ejzEwVPWHqsPOgi(#EZCxk> z-ijdvHLnn}L7}S^ZQ}`@H6=DRJ=iYe?`afKaA>k!CjK!L>~oV^{{e{9mtPaBbeJ;s zdi=D>6DT)ISe|ex>wb;n<3J995Q3pG24OLw2b|Qf5C@P+86ju*)U+BQOphbfUDc{Y z1JoMYRu!quq1;Pz1RTGv7`Xco%K`$Nw=m^CtP~hhM52jBCQK&NM{f^I@1E9=jqN)$ zH8Ux*wHcG+QNDMOIMHf4S>p2U43OUgAnv%%UL#>8sWcQZBl-mP9CNUWN%*i}C$}fmF<7#g zC$1-)vVgKE6=b1CLQ9b_Q1D|wmyqs2f(iOOz>%BGY|GatB&z$_6zZF-hp^dcB$1hrkvP$Z!k9T_<43kQLaf#5Kmcc0Fyr zM1bXh$iIF}6F(h}NtB}E42WWtM*7YWK|*S44sO#j{f!86aYyQhq$(V4ffyh#2-!du zxqbU`dN=@6)L=oBr&1RgymgHaC(F{2SjsO^8MRfD>xpe1SyR+P>VKPj{#_tB;C^89 z?!egPIN%{#x~N#b#i9^K1g!mKv=~xRG_js!&L#UNL1|TO%>l?8HKNQvbdbV4bdU#W z%ZUydIhK^L%o82ZL5VK^1ME?Rv`5)fWoyPwWH>1*+`frxe?(u!cZBrtCE#GFgEF4At2KmEV zCn@=F+h5kionrAWA{WjD_*nOY?H zK_Pz`5`I-)f~9%RMOG&=`3qo2N_v1$KkC2i5acBLOv!XVPFaJ}R{Bo6JmPe0`&9}^ zM@*5eZc5JrgJvifDl`w5;@FETpE6zCqJwtE%~`CSI%Rs(yce$$ubE$}jMs+Gm`{Wc z5KAG&F8libE+A7rt6s{D5B|NNVF(}sON+LWr2udd>2~R+F z6oJ|cLLody1ttNTgiFb%>R$uw2kIyC?*mN`F^QB?Of{~CP*1EcE|3UZ0zQfGpA&|9 zqrayAZP5Ipp%2BU6jBYZLDVDblMgHelR$F)_i?$SwW+bbTJ=?VZh2yPVR`lxWW618 zw3bDne$I})eA^N=?DQUX{-W7j?Fil+t80TIb#KhABfT|2lcq91T~Wx26dO8O;Wa)N zo^6Xkbv$Z!5b6*|5e`Lt^+Mb%l4AE*l zarXB5BU-hD>638>_S%cXKr5Mie6Qxxt(x`CF(~BmY~A(ppvV2q=tj@e+BT4~Mxw*b zJSlH}y7*v7x83r6PVi;D@sq&Qo|tCF#?;BkX2#eK$MJM-O3{|i%FNcHO0%x2uBPs; z3BKJVuNm2g7&bX;dV85!Uy}34(W2>X%X&^#s{A%Sa&9V`Ei$3;uwk9^U}?}6=pXt7 z-fxy{K|;7*DA0@dNhE95KdWXck9ti@`+ZkiCedltT{)v(~Ma&z_ep_#oaz+DXXu;Z^58kC6EXSeS4s&D&= zFX-$l#CVLGrfa(=7B-LG5WTi3wT=fLXTOS|I4;gky4lZM3Kn)t-lMEvyMJSIzrZ;1 zije)cG1k9qxc+mK|DQK<2A2QDfG9{|+&X|3w&Na&yC?)~oij}oj4VcQZze?i9T1p? zOr9^RNCKNmULU+-GcyxS!-8e9DYe35uj{;NB9}yoDk!*$>lA(jFsjj!l_-z; zoviM=jx1q6?a1@Q-IQLfQ5q5MxgW7z8^*8}?h-Hy^H~aFrjavlP$ey$m51yR2x=rt zmLw|7cMP@@@vPC*x24G{6~v5b@t(%rnd=s$l3Xx z*@w`$tJOx2yPfFKq<~ZKk|~eNB9z3$gSoYj(EaI#+q2;cBxT^qcl-GOPp_uy@nDkk z^-E2EgWovOlhfJvPES7`a11om(;N4HW9%)1+X|Mg(KsS)C8fDF7*D9wmlq>$McHaR`g?g;s-UHmeHCV&{2YUbibn!S?{-H!O_ns!^$%X(OST@M$COx z`+?HD?K`iAej0e%Q4Wl1tG3Wipa(KkcWg$T)>H)rEY(6^Tpo20GJQibtD&{guQw~H>VUQ^4xNan(G4ePMiJ)#Ap?Gd)XzH=<-2ANNNeU@) zM}vu%&*o^kSl4=}AvZeVDSY8aJ2hAD(O6;23Hh1({btiaRqriia7SGGOb|+PlIybs z(;Ob{B?}6Mcm$nu*&+t|s${l5L0pNXH=wz)==33vw+D8(m*`-&sgjaYuJgW_F@mHG zmAf{px83vjh?gT<_>9wR*<$FGH4Vc4w)+~%_`#NZZZWSOG%z@wx6vN9{IgE@X&x<0 zCtaBa$Du3Bk?$q4EZeuQr}t8t;@*&D7Kay$LDNV5;Et1Dg3W}i0rssg?GU0ew#j+Jnk@XV=Ukr(vZH_DElf?R7F)M?p|+0xc}z2ch^zoq`ri@9(=r z8%AQ{+pTtez38lI?GwI9AMpDR>=!5nJNaz|elDn+ZcuTT#ZMNkXuy{>ky51vZ&U%B>;w1-PE~!6qFrGxChj(m zEro`<8dAQla|zm>w*gO9M@26tKu>F%(^9L1%J*|p3m`#e=7O)Qzm+>LwbQI#6z zpoX<;y3_52-X<;c;yZK_IP!h)Zk+44t~@sLJEP`O&`aM6Ze?n2Uap6I(9e{!O>pO6 z>b0|3VXVl{SnknlOch7liU_FnVr~se=ld)7j>&YBF)SH}{W7QwV!ELGEE87^g_ltT z_rDzpew*HClZiUjhsrA7zh2K~`SHH(>F<<3HM!%!g^zfYj-*5RlhBgLj|TU0dRPN7 zydOsjdo=5giTBzwx&J@E3IE@3$sQ?}e-WFJ@Damred&fzuuUGUQZHX@T99+p%K&ag zfQs%$HuG&z?1NSFxUWJUph9c!wr;sW+ipSmp307@tfbas0%|yxyN1hIHHTwK>vcb; zj-Oc&jKPMQJA+MdQ&QoNCwDKj=B3_yaBa5!A3D|M6xN^3wryXCy*#-T=pAUy?fMxoggVXP@w=S48f)zt8`3fvln31)tdN+VjLauRd!{I4Zu`EX%3MX`w%rzr7uyMX{bz_wFGj}gvFJiT5`uGen_LxgsRVI zT9T&u@ey2I(@4s3kVCGbRh@1S8j@Eh%U|10Bc+jKpenM z7v48qFDN~@?qt7j-O;tlTLqoRZ8uv$LTv;+$t6+$x|42~ZyhZZ3E`KurogkXb&`3BPwv6kvx95 z!2?NlU_Dc+waxg>)VK(Ora@mo%wEXPT>NCc3W`6_pRrC742me#e4}^@6aijOYF=R+ zLU|?O1=F(PKgF6=#(FtkU`KgFOxBcBma1)>DnG($Y|*rk5R z{49T_;D_{$CJgV9R}}gvJ>dmm0XsotAbu|yzsT0Aj^NzHw%HdDoeL#D)JDmPy%*s# zSofE=1pN>{F~(8Gx#3Db5&zKl9Q`zdeE%8R8AY`X(K->qqNRf)E5>fHjk1#?5Ctd? zgbDHo+5tZ*pCP(Q1tmWU-3tunyl4DH^GfP0c|kU-U~gfY;eJ&oeyikyqEMEcs-;Nz zJ_?Gj+3!!&J_;Yhin##6V{9s% zq__3?xzhQ0O7swvbCTVok^^ujWGUnqOq!=%%yuXxL_#JB|w(d;%Y9u zpg=YoD;UvS2FDWXUwG<2M(J_d2az7Ce%qy0QeI5jxK6Fj^6)7E;K6(4{QYi?!9F0v zqw?xK%%j{#pHuF#6h&bs2tyt#Ty%T@_vZtJhr9>Xze|yEGW)MA5ycPR-7ahw=)?Iy zx4?f9IGb>XR#HLG_!=9fHX`%lQReH`poRCLw5t4n z6$uR--&voT*kU4Yjc16LSs+&-KCQ9i;1yDb&;1s`Z>YXYOOJyXSqHx{ut%Fb8j~<) zi+V>9JZL&(&hkr+Lxrw~CE+<$cr-s2TPv=ri^)Y(X*G} zW%<~;lrD8fYX3Ylsej!D<#l(#qh7lkWE+6{{t}Y^Y={@Xcpd>z-DlyWP^b*g$< zHF?QrhZUbNnl)(FU^Y#DZYPoBfa6G^OCyWcvSUx2HD$|arYIuAA>(bNs8KRuqe@i& zs>_k6u(US*9p!<3|CI#T4{ojS&sB)2KX1{t|E*%G^VAb)ZJRS zYS;YEdPG>HSH}~f=~T06%p_3nT(ED-tieoQsBF#rXSix{E(#p-&YR;j#M!h_b2f64 z9v0ebHAbQz*N;(vZ=ds_|Id6n`u-n~d!Gi5C6&W@QEGt*W7^6^OSEmqOUHB@10Mln z=I&f)tz_YgwrynGNoUfCoeM_JYiHI~5Z73rKDtmjo7pm|9=%Y>d0I^oKAQdMOLX9Z zo}cbC{cl$PApo=MqfqCcf2o2({MF|m;yolOY280qX>6opZ(Iesh3nc}i{jtFQUMv+ zXD;nYAk4DKoPDSEq@0KbAH=d%YtpPq>!xE{j+(_vd8K<+%{vZR)Sz1Mc3aZN71=L? zd$bBjAR|jI)T6@u6-eAa~AH8t< zoxIL4Pi96&UQy%LxMl~mX*+dM*UN0on=NhA(Z!5r2V+=+@w>laks5eF{Y*TbnF1-u zr=o?!Q}lWMn|bi{?1D%GrD$;ADbTo?n^RuEaOEI_n?B*9(Pd~`OU*vySk_ahB{+<;v4Jb?U-}Ptp0;%2~%Q@-ZwmdE0`K)9>gSqYUc#Dj96_ zKafF?{1>vM2m|z8c>nK`wvk~{}RJ5#F zPo^Fx9(hFap2oosp(_8KYmB4bd?d7TT1S0&o?^p;{|$~Q!2xN}tf|ss63-`XB${S{ zCqvjTkqgaib)1tq7wlvuzh5^&%`PcjRx4KaEeqnKwPYGBZUCGl7e6z>CIHaMgWy_l z=EOi3T+sW;i2jrOUinCZqiLC3jF1GG)kXhhKN(8z@)%BY$mus|jcN{&@?wpPHv87h z$qV~k&M%-R78aje!?2YD=Wv#wp6@a^J@rdvtsSH1ZofA$+wcl9m{nG$Gh>2_%i2+| zVFI!~Ee3}EaX|9v3&fy%ihuY}=nDQ9pI84w?l-CT?1Y=sziu~%mel?XW(``OduQny z@V-31{mtJ>$6@Py%dIvn6+|n^7u?D#X!RP|bM)p@j~}*l!D~u=v$c;NCJ@U{{gTcP zE*LAg89uC$O$apG$CvT?7l|!zkNz7Xq=?d>@D+ZdGmKDFEnJWhg{Acio4RV&^w{tA ze#eJ5Cn+8qZ7zlI6=ih};-)f#gbNmKS&$Skz) z$}1(hOpbWLbn-(18GS_{n~3}y-s-Qa=`+zE8Nt1_Ch49sUISM3M0P}Gm zh2OV76BGC$syp~uoUEjbl-W2E)RfLHRK>04KP1Aid_N_SFzd(}30}CnTU~y}4WCK} zjN|-+E+FcIh3?b;m;w={{{^QFpvr%t3-P~=1jMH>;7Pc7C&@nbdL`d@tKXA#^3TL> z)P71I!h}1EcpB+=Ddd08PEQX1LYu9UnOf5dNrfyWxh3?+c(gv|$Gxmf8`NC*^R9pX zLN7S^s`lgfbif4Q8fkC}$AU{K!CjJzWwQ`wl-TwIJyUP4B0 z=8EHElJce;MrH;9 z_w||)`JPehbCxjqsE%7AQ;b0ZKCWz>{|Et6OGo^_%Lw#Go~MGKa%YFw)14t>Xv2-_ zyY5)(p;KsQC;bzer=cS4ZmC&FzkW?-pbqwa;bnm$c*-_j z`kb4F8_-k4xW{W90rm)3B3Gin{G2@ON5YAYW#{7w&)JSDeg0L`^m}{(ITJ|11KBE(;06 zdoaoPce)xxY)UpBUnCMF;M ze?vky9UXVJ0Ljp#q#XTEAsFt~46=^ElulKs1hfS6xgWT)v25v61v;qB!E$y7QK1$Z2poJdlD5Bt~y%g40?n)r+CTPOtG}54EKCY)S)O%W+9lW zJXe<@+f1<=9R4P2P%hfTD>0A?jn(CEgMiJ)2o6VBXhkBqiNN6BiE>U5{LygQHLL&;drfA)#vS$@P7t<7+L#Sw) z+!f5n9(ey8_Jc|L0)d@F^vV@T3bXoWk+ptZu);*)tD9v86cX`2^p+II99zu93abZ=TGc3_?)q#>{ z{}d2aq@d*f3#zU_W|+;|x~6u(I1xOJ;uVG-N@lo7vz?b{HGaP5ra~0@K8HjoMTyzz zU(6-Bl9F>n*@p{x;+TDeljwDf1q=6&rWKW>&&s(HT4V8SZ3C+|ry?x?3r=wB)vVp6 z*4FoWlLz_WoIQ6Tj!YWtlF909-e1L2mR};ZP5;zW0=;b7Hw^KNH+aHqI0fB zJc3XZ?-2e9sim0jre=it>)kA(4&rvtLNjQk&VlVQs$(z`F3#djbAB~*IYh_`h^+1Q z6`^7(=&tDgEo+~J1-mSIo)t12GQ66;$VPzArFU~k+cgWL!Lh4NZ(8D^1g*M)VoY1+ zF19?@v4W6w=Fz69wKYS{R8U#b*g%SAhmiI4*ZP9CaD^I8s)!Kv5BmP#Gjx!(|79t( zQr0R>1%|b!9~Nngf`5J7>?;GYx`m)7Wxhhxg7`cSgjrlgpA_%4bAq=uZNp+w7 zZ47yGJ_BcDS08SuW61co{xE>125cF1S$i3=L|hKbHwUb@n?zEszsJf0o?}+t+lWPu zOtAS22L=aLD{L!fsoD!QyR0ErU+bUy3VM{;4Np51A9r{C0*X^bo{}H*9K%u0aVpWL z@m4V<$z{WHC!{7DGA0`mF)?aK8bfp0Mh){BYRjd?60$psQRvJNNGuR>jG-($FpbO- zejREqO6U|3s~+-VF16DW47#1-DG`xDBbH!K2Q?(8&0MgwF+p@^r)b-VeS*P_FlgN4U6^&#_~-zlpgSW>e>a8Be`lZ0-cN zi{r1(w|76pI+fDLuyZg~7iKJGwwEy!;U$JIvR5I6KbOJYw?$s+mPUW$4%4{^<@DC3 z4v(c@LM5m5t0#)JR|agEO%u(QS}uD1bfjCsuHMG5t*?+NhNYYU6FE1OAIUo>te>Rb zimCfbnNk5jZhJaW3(_ctW`tEt#M5|%*s)^w)%Q@A&qI4JES>&7DfC=@Woi+YM@x~#iQ^Gki11pZie+kN+Y{7jRV$h5+< znEYkw+8sLgDA8zb-xqkQBt0HP?vd3$tG2{R-Om!}7^6MU+WY9EJ^M1Bt-uk6&zGFK zXJZ}*aWASSavu@lWsRe$RZ?pWe$kEB#>U7FtG+c_QwPU}H@D@Wk%P!)+|UkX@gAD? zZ;7QzB0@OEu$Z#eT2u8o*y7^YYNM78rp>si9hf@)F=|kbBxZ$lY-V-c4}BM@;n?9b z6SScALgARF?}s7uGj>c`^x~h~BU|LA7nKgLMoJ$ZdnyT)rJ;a{HyIwjX5&*>GeXVH zA7+jr92O=V2D6=U`m~k$vi>i4K;Z*2SC5PuUh@}q#4NZ@#p zGbNikv6CjjT23hpB0mBx7HY8yjO5EczLKv11-Ce7{TmhSEF;4)YTE*92jP ztL`UnCAA$VV&9#%uHPFq>y*X>@ZS1&MC|GC!kR>VPozb0PQWZM-5Wv^jXD-OAU9Mu zEcFWPe=(Hbp3b@I>osmxw4K&?HEotJowj&MGXkaa*2ym;_GwV;8W(HHw564#C)Xgv zQ@1rTK)>|!i>NZm7GYalQ>!^TTm=@U;KV-EuuhC6s@2&FWH4P9mF;}Zn#tN)Whtj4 zFpm}`Tmf-*K*O^WiFt|8RFCx9pFrbA<(9sx0f?*!=HaNSE*Ykqwvaa1SUtX zLbv!Op0?#3!H4tnoGufQ&8qHku`x9;>>8Z4d0cj;*G5MjT`#(%Wp97}mQq9ERb<;3 zUn8+$(N3bJI%Cit(Wp}=X#nnmMkB6Q_YpYMOPAB*G@ve* z4No98CpBxTNzp_IS^F&D>Y_H|ej$5z|R|sFFI3O06MOw^| zW7k|8rnyzps#J|Kc9$%vm8)RI-X-Y$cx8+)QyZ(wm-jH`k2bA0n_s1pV6{Glkb}6p zMmA?%R32LswIL-mq#ZY_fr>|Q=jBW{Hd7|N71n9x%Z)aOHoInPrF666_mJ*TVoAHB z-U~YL52SLM(1HtVj^xs;nTJkRZ05KXBnQGtor%>ABu)O>)sP!rcRsj73+~bu#a|7wEg5a?cwK6hynn$%MmR=&g>4#>swT-g zNv?udwj+2eL^Jf#3ncydu9{+AS?Uj3f- zo@b3*6~;L+o}_5Of36POC6P6Xtu7xv53^+3G72n?u#-{dsmg_(Y^ zj%g1EVwexL+}1PUO~(zTW{fKsmo+pwkTV+DEbCQXA~i}nrfwQ~?=*>DRR|ox6@|zc z(X{S`V(zff4b@_BK-a+;MDxs&t%{{%V^T&9N7C=IT-!RfU}NNAZDF`aeW3OZQpie- zG9n~4mgrg)vT0~DY>@bp`4(psc`DonE|%+6cdM?Iyx~`6UUyh^9Cz%wRJq`})}3TA z@eq}TA0vgo6EUw5>ys@;AORLc5>vvE55;4Sem4tc(-{`So-WJm__PX-%x9Mn(8idl zSmvd~+PoFlt3ReQsb^1EYZ2s-4fOVw$fsS1D^u_*co$1vFY6B^PS0hoK=kR?Wbiad z;08Oti{mpKL`~1G?YfmF+ZXjpOB|Yehj7+Ek=LRXM(p?lrADiyTuLdt&%XH+@CnywGRYc@S63uRSsKGB} zS0dQxo#7ZI&NGlTAdpG*4j19|vt*P@m&z_X?&6;7@6c;2tdWs+Q*I(%w!t7pC71YS z;@A@FgB<}%Trz!7a%!v+^vx-gM$DDcn!h!zc^Vg>i+K^7r*i)SaO^I0=Z)~tPBn`v56Az94cHqU|ux1-2wWmfQ%AxS=!|W>aZJx8~ z^+?{clG3Lr7F2+!Hc9|Lni#OA9aFkvhP@eDpjr3LjK>4T+YzfAFi6_9$C*EL;}+_9 zcC1q3HC)7mC1(;L{*GnzAVlc&###dLV5M|Yr{fB*+%PuH*i7?pd7H=l*<4|Zk5LJu zeu2!iiwaa}0BJ1h_1+)$G+Q4=zuWrDTFr~pzSqoxvMs3=Ql!jOgZzv$zJp_%Oyk6s zMhCTR1f*V~zkCpCaIEwU_uz#u+kM20jZ>~Y_(!B(dLdv^Oz4|4+StDO7yH6^s4lF0 za39q=U*=?ZTNosb%2BXtL5|4u2~jQ4fJ`E{`%n$R#f5^=MShG^2%{h?3DYu&57q?9 z2%~-n*G^PcT2WKk$b=7W<~qsw{`o-|3UV!>74%if&b{OyVsrD zJ-@MU6lVc)7@^wDU;jaRvgzlJ4i_9@?xy>@!Ev6OtCCjT-s;G?oI1uv2bS*sN^75H z?98n9B3(@SVtL`$VDR6`-y=?>qv@RSg_Csamg#FSjRU3ry6Bvbj&+}+CZ@W-ctS%l&P(qr&FLRk-Uej| z$u-${V;g-+vMk{n;8Y;JBM(m$sTK<7UX3Herf@CCxfx+yTmE-^LbmeC%4T$dw}fM1 z`*hmG@@iEz@ro}KEro4h>I7n}^nC$op3hD>z??@vvR&a)-(O7Xnhbp3uYv?UAN4t= zD#9)RlN;!$&!Jnn(e5WZriCvqoVaedae1{w5*l99j`!(2_FP?~3$0+03$141XICm( zJDom>+%(E%+|kCfnnp2b1ddr7)|AG2rrVmjdS9#jroc>;LLsYGm-8FAP;2p2Rdm@g z)imxnQ5|@8TvFF)camh}#Z|+^+)`JJal2E=$JDF;uwl#Xq%b*rp{~94;MXVB$B##< zuBfW{_G9LoGM~P!M;Gy~TVzrent0pzp6lWwVs#|e9_XY-Hbw6u&?NJaK0861wWQ`a zvZC#Y=Po085!BgA?Rk?f&&inCU3`4#UAyJbyz$G!L2oCFwzSH${G~Ap>nFFv3)gT6 z%zYT1{+Nxm8|c-&fOQeH{ph=;?G{b`oH;*V(m)vRsxpqymJTTPVEOV{y;64Fg*33g zPdca_!>Ef8ZJkVc{nSF4X<~yb_!7Q-3EnWl?e#YAIN2e+){x$^Cit~KX1|7d+J)`s)q#jN8yLC^jZt9(sJ3UHthh|Nu> z`t^VsvA>moe^Afj6v)3&duqzZHr2XzUhUYmVQm)Mo8cx-ym#LE6|bTDY-CJo;hBIt zN6B;^Jy;>SN;tzl2lOKc3z1&G%lKnItZhzXNAcR={&J(;?S^Rj&c}h}%~czc+Ca`f z<}%1bU0CBnIl#pLmG_E^bqa_~+fGOw5==mbm;@OQVIYXaw`4vuVV#OV&IW}7_Sss23$5^8Z=FL z%RLu>x1FdY_O;Ka{m=AtZ~W@Ub&B8DR8AKS^?Y;S{-1~!7Ud{jxAQ`&gDC`W4+(kL_Y^ycjw)PIefWFh#&41Deq-T6^g*pC9Yb4Bl~~=@Z0_JtMrKuWb*>| zWJ6fQS8XaLLSaJDxfwp-c{s9b71cKMTA|S;osjnDn5-AQrbE@aD!3}% z84zTXPAXY&{dAnZRzzYTX^U>Fh(50xlq`vT&gwxLVZQ$LT);m=X&*fpBW6QGhppvu z<$4MigDFP60V&xZp+HxIqy$--57kwciMFA|>{yADM0X$i6<*e)NX30#UBit~O~G(cXcCv-)a+#2x$a|sX^~=YlV$&AjcmI8hS%_%615Zhtp{)%usYXG zR17#a`04F}oKpzw4C_IC(!XnDFm zGVE+q0UusAjFsxm52zIjYq4vueuxe*Vl}XO;U``_myOV|&WhrG;PVd*2*zXY{6h!i zdm(@^r_=>^US?&#^ia4i2)p}1p`D!_Lydf|JB46{>RnN>$fI<+NYMm|)g~NTbilW- zYFFU6{?$B}P1$C?wq;jz5Fkx8!csfeHV>0pbFM?MxkY|5rEl^YR19ZJk!d)%CL1#yk*b1@Z zl!|l1VTb(bWwf-7`AvGwGsAVeJ}V;8XNV;%ST@JG)<1G&3>pLdSM zhXZKBzsun&qoTlWjiD;faXU^lZ!+_CrnF_MZS%u=tr+V;uA?Z)7 z)?kHSp7iimdN@<4wMa05F0NX&+a#fKin2RZJW}c*Ovz%o+U?Wdw@_Eu_j>d)?c(&| zaq1VBRDi+06e1p^LNOj_>8<0vgS3K3Ms+syq)x2ftGd6Ys`}Nzq|i|(p>x$adUL;H z*15_x(I(Zk<}`QvR$Uz08J@G!yyY4-?8vwhlgF+b37{N>5hNw=d@F$a^LbR>oLP!G z;Fr4Oc=J^k6U+-$Qh$xIY__8ceo;Fi<@f7jevq7xufG8lVKcxV9l(VyJiGvByHNK{ z@KGkN{ud^-MUFx-OV@&Pc2E;98nXF3OeriZxXs{X>=X~u0bMEAr=mgzfLN_iY>7%6 zJ8wq+>MHwSEl*3Gf9T+c4v#wfM%UB=;nNA0AUBJ}Vyt_uqQB!=i@s0#Wy1pRh3<3n zsq{^<8S91aZQiyE!^-pTBBP}lZ=GdZi9*3J9 zI69P@x*r*?@88YOkF4mOyXNaRe|uc^x18uAlf~h(I2veumGdh3`9Y0455lz>sGT{dSj+YS^&3R^6XCxGT1a9Yg7nX5%UhU9}%n@V~2N zpo@MfxzGQ-> zuprp-O+=5ddhZYw@-T# z=yfxrW+JMxDE3xjOp(yUCSXX+!MUec(7faNo2JW#^Bp(oilL58jwv@{rq-*=u%6Ss zvH9TAEg(kd=Yvily&NhmiY-iEL+;H&4J-bP&#-i*7*KIm!8PmDM0YSK59*&C>#@!v3$z3hO*24{&?->yPLD{JyJTr5*(?ht`D{5-j;dB1hR22Pf zT;%lYLm1(MEy5X+&jB}z0Gb=(XWh${!yU-cAYDN4WuGQinCq2vVhn83+nU0mr zr_}yJkc;Rlt)cW^nYiK8ScaK{W3r5_-Z`e{PV2NdYB85CvN~V*()9iFy+?Qb`EGBZ z_S>czUq`1t6Hflvx>>9bkBOUyLz^BL=la)8N=<*hx4h#zKwjCJ-!+ZKZPP|LN6oh} zh>5dMkOc;jMe3U{vLv)r3Y}Q>(Qhxh8`z5Qc1V;=Wg5agzqwUT`W=rbSby}9;k=RAI$7U6l8N-#boiAY)9bdw1KW>(T3a=&LvD@Uf$b@vB3XI%U4_tL8l4YcJ$^^$}`4hx9ymP!$P7b)b zYxT{ciYW1I&yiSDr6e}X@j?ot5TI^I&H{N~(qWKF$R3cHlYc1Ga}px2F$7!~F*18u z_%I8T%*G%S9BnRAEgx>d#nOmPWw(}axOdRM&-v77n}>;G!EqJr7%f((&M5Zc)a{r) zk}h4FoP^(0@ZR3s@U8w&9#R;~_7YfskI`M=h0*Y-m2X3q`VuPgQw`y^$=bvjWXRof zfoQ8}xH?=0eat(M;Do)%J)}01uOg?-xp5xGiuZ(HRz4qv(Ne*zl3YnQwn#U`S)$#e zfy%M?8Od}`lJV~K?D*kYkPuJlmj=CyAMe*oMFU}qy;$#`y_fnY(VQadSLBvshS&Md zjJv{=f`w{qxkM;A$T=8x4b{yNoKW@{hdN(E`}8U`&l((hb{i8Yw~QTmM9j=eN~jnG z!S~dWVR5AH2gPG~3{e_Mnlh8pfcYWhQ7-%98Jl{h9hiFPP`fP+?P-#N1=Jv(*xf$) zy1B1!H=;)BF0dA~3KrOKjS{V^AUj?ar&40`6Ghl6?h;hd(&y(BX&0VjnO4AzFOQD# z*dmD`m~lZe(Wq0f0`ra>s_d!!g2a9y-GW3RmvSn#*g#PNi`s(HVZnJUS0q44C0|C#g7Nk1apJ+UI4^v$iM+<{5Iu^Yw-ASFR zR}|FRhvV8gvM>ub8f3q|UP>sW3y^iqwWuN8$>z~X- z=^weLKfJeY(mH(Gx_vZ)xu?iM=~NJKG53v+9`BM)nq_IBm#kt9qi?`pbzD?y_QNuc>ouxyII;bf&3Rr%?` zxo(H(N4Jyp?v&Hpxdy7;5V$l!Ur<%OD75N4ef2iY#X;bnpj32S@&0G0`}(a5~17wAm5z>s(Z%0AlnP`sCMo3yYpfPg9+c;C*afJ6z&{S%zmw*F?+6Xi@P23lq&lIhuCqUH~E)Q`I1 z(?FNtF9Ifsm9{1DPKhJQkG%$&K9YNVX|z~BfgQYWunP7bJx(6|q;0yt>ECz@06Bt( zVIZAweW|iGeS?;oR;R~wLBZ=fmgl!%ivS!TuOf}tvP-mxR2n&qBOig(AgXdAos!G` zX&mmcw!Nw*j7}tK{Y}~jlJi2C+~^l7UQ2`tLluOwc*-7|vQ&&28+Wo!zJ9D6|0LP$ z541LA;CdS2z0+z(tTsxB+v~;*6kNx&T)hC__njVlAuNtiX-#snd_Sb$^6acOiR^u# z-p>;a8D5ExSfl=Y$!xRB2c3;ScLaDoa8_nnR_3PiT-7*97X@L}g z=xf(TG~V_?5_CroY4}iR)+we`Fq2ulMn~j99i}*};ix`*s5hG2sVKQ&EyZ6Clj>Ol zhPZ~CoKk{{n9Z1byRROae_`QFG5mdoQUp}&XH-7rnZS0ecGuDg7nvVEQ?T*bWN@F^&eV8pnWtBBQnHn`O74&T;1eeq~D__`QYr5>ku zJ6`}=Sv)ho?Ma{B|%wZYDZ)ku|<+J;dG9a7Gs>7bb;ru|_;h%}Ui z$&^1RLrx;!boiuPqi#!X&Ba^f^hb5ObnBa+6Q&;)a~!1&zY#5>&ahUQ&XLX& zacqxRUzm5_jMz-vNEh|mUK;%NM@})LgujL6O~IL zp?7_5VD+$nSHD@Zt_D6jnHD+%(Oh6*;+XJtB8J4( zJE{1LxLLi&B+8RR;Td$^wlH+9w3!_r(7QVrnOIx z(XEC@w@D?UM*FR{-kI%^btCW~z(qWUI>DX>efrqa7yYWyn1AK*-9M)6^4iB*8$S`3 zK~4jit=UQ%ihmXI#mQ|PU?;FfXzA<$ypEqN@bfUI<4|pVd=vfaLLVir4jy;ZAGC`K zzWmJ@mDm~!0|Mr=Y^bss87;mN^Dgg*AwZvad$JF4C*Z2$4_uL{mt0MP1NP_bJSwGY zf?8>5*hk$I@Dy&!5)NUn2|MVl>37!Q&y>WIil_M{0EA`&q>d(M z!{LSE+&^s}ZMnki*nwX^wJzdY%31-pJl^9<#FkEKoUTVkb=ziD)y!!~)sna>#j7zk zT>WO7+)n*!x0tuAu49%8?KG!tgC{HDtRYppZunLp@0r3kWS7D*rqhl^HY*$1&Zs$9q z-Gj&qZr7La-c8o0+i$nxw*9^BzkeKaTgPMt9K%_H$E0`v z9{^oIqQBx$b8&|3(>$y${)HK#Et!B9mSmt?nMfQbTX;e&lFV~qQ516iR_F_9gp4IY z5Ml-xoKs;Hht+ZFbalSkstT$M(KHKctnje!7gqEC9@q4R)fYMQL@L1|ndZ}%L^2Lq zUQQ-g^GriIqUCx&-2?n8hhc>nnbM#VbkHuFBa+bl1G`5gWwR>NtV&A2t~B-C?T2Pn zrb&-RGw)HU(WGQ^!Q!O*r*}J{nV)IqL(@&0XJ6@~TYQn}fC{TIjjyn==`cq+51&ti z!dCFhL0PTmT4~-o1ET(qgm;h)1W9y2};x27^4W^Dfn^2KlYt-L}_loY(6M zl5oChjCGFnnt@5eB+Ep7yfMu=**ncQAuus`ulF&c`$HV(2&oo#JPb(>jWVbbq+HY_ z(Rm6w^b(Cb=;%wi`nE*X5@FO6XwAp@_Bhp{coB8@^K!X>_-lS0~r1SKI{KA1^o96)_<`Z%T}D4Q<<7mUlN#! zxgnKdi93Bcl|&*2wEJ>)Qu<)SEe|%HOuw04gO}`oGBu`hW%?eW)8?4Dd+xq;PtVI7 zUblSeU2ZEy&ZOS^g_D3BH!8t5nGa8kKNTl_U!9w%d3*uQ##{xis8}ZS_a@>)gnIAb z_!wb~cVs*zjE_!=&l8q#i-mREI^kjTIQJZSiTe}!ljk$^nfEhaAWul3GGU0or-TQ6 z8{>b9^D$3ZyvCD^kMxbq8(uIxIyyc%bjdH2UZ z^!+*RSAEzG?6xzQMD*2!LBS;NbNR}I!2(Y>PYEZL#C;wCi4o2j5D48tLQyDW=ZIVs zk}QF^(?>Po%pupAi#l_-9c__s=9IefQ+n`9Vix>0% zT)iOqS=5Tud_8oZmn-uUr?m4k#?n{94_tSsH!9U+Lb;`^qQi;{cB~uRIsUN(L zZ|r<6{rm^J(x2Q{p4x5Ri?K?qd zQC!C3Ohx z^}+&J`kYMTMdfL)$Lox80|-z^l+g*BFO57+)*kxZ;v+{JO2&`rJ$-Qek0}9JbN;`Cqo{(o z&Egr{48Db1$n&w{fm|~0a&DwFCVzOr6-6V8ui+Y{sreI2?s3|pwA@6;yC~O)9-cO#8z=@)qAXK?f2<-7u^+m(7MsS(H+W0=lvsbM=&0+#7iLwN2LJ= zUsV}LGr_p5{TBuA36fyUW9=U*j^UW#5h$@_W~oB`EuoNyV}33H9FfYD!00B$-hM0Z z&in?={;?vPRTUz6`JtdJi9AO{94jh>W1>Gq)htf0ptD;piIi{fFsb7;PRV&Fn&U5Hdy zWh>4_>?;_VSNpPceYeZ&;k^u`lrQ5`_gJUBv25Op*NmGwBz?z_XR->Za9 z`?jq+o=y(J?@wx7yz1N&htuCYhTqkHeBZ<$wp=lMcGP=)qVCz5^Ip60=HIQb-FyFv zDPyav=adZDb=$3PwJiLSBDDhIflfB>c#mlnNC*ZTv46_V(m`6<{vTss0v}a%_I=N} z`@YO_XG><1%w(HLfJ}f1(Oi@rA?&h6qXNpJ5=6iX8mj^>MQT4Q*0!MX;!-VJSVXP) zl+wEJf)#1SBD8|yLgj5Kt-ws)bI!dJg7*9UzL2^1%w^W|Ea!Rt=l?uOxVv{dxdec< zn8*OYcHrS}Cmor%2f_0Ve=nq}e=RtP3k9c;catXkio%X3duFYqlqPq)NZ}lnR<6b-P1}@zO}w9ZKEqP-+R_ko=-MOt)Z=*n_9s2#`cLX{rU(nO@{a z@F@aSnM~`OGxO&U{&)V|f;We~y!_A(cK3xXNAee*T@BPP=;jMs-`IY`o1{vC645$0 z6!SR26&_d3VgV(Ph)$wdQD6aNYme+Rj_fn*>d>4w5n58zN!GHUnyREzQmxWkX;mH+ z9u(IooyuuNPAFp)$Us?u9??St3QC^QOExu;U0C#NNfZ+T>lXx;LMj4TKZLA^-s+2l zgtF0D0+Gaw>gaWhTTllkFv?Fl#V3vKU+l$;1f#5QCQ>> zYH-q7i5}LEB%Ks#$wdNjOie2Rb#4w>2jHOG@BaXn_llQZ1|Hd)dlO|Me{5f{bSYDH zZYZAfFh%i;acluTcFL=$abgqDb_V1W38}O_a@S* zGe9Jq4rJJjGMF8#j0#L-Co0neGufHSyuc!Mk#bi+X9F0mumogkkjSyAiAc>R-V;xL zG0m_n_`SRAm>&@vTWPZ*}(FicBSgiwIhO#|5#`baDtGIU)O1p%VZ6tXPSq=blV zM~p!t7)K>21swzE=1?pcw|Il0(yX>>K^0&U4 zf473S{rR_%tu{UJ_*Y5#lUyYK^*e05=t-(L&?XHB|+Mp_-P@C!;xos!S_B zNd}w&eWK*^B`6X3Kaqy2nowxJqR_}A(KLiU6)p9YP#XXNq@4-HQJ}I5T(>hJt&ut< zTG|D6ZNJWQKD!)=>u`**#(sk~(1RQ)L52N+H%qYdNsl>$b+#pRB7CalR0|pqwQadX zZ&$LHs3>MBqaR(zTG=S<>3MRsa?ex}*t+>`H+)C}S{Xwq;Vi(xY$%$wFvlR8^|>bo z6F8$;p){Js)xle17!d1p;<2m`1->-8sanu(^jSgsasg!sjWmNsGKOV(p;WEZ%F0Sn z$>o45DruA@Jc4+n_-u5|XQOL)1kvb{7(5Mnj8Wu`oMj!j=qU>(A;SK7<#QlSDC=_- zsQ4h4gXz=xN8=@Z0{J!Y0{l&W)g4V^uK^F_Mql_A%9quTEzSedB*|O76fk#(AU4p< zK=kE4-)7lZu|Ib-G+@H$K;wgm^QsWh`9C=W(SWH$2MejXP%YJJ%+26t?q>NDj=@UA z3B1U0B1emof;kKcN%l*U%+Z`k<4`$>uhIz!(82{cMdknsg@C*Zh8&FzG@(4+H1 zmo2+}4cK&HTka=FN?m`+&q0CNR}@X5fE+a8dQB?KTs4SPq!ns4X%xi8nHTbNe)vO- zxs2>O$;6l|s7k6oyv(T)Rk1p(MyjjS>guf8FVH{QP(7l$MQy2`tInxz?fsCtqUvYC zry?(?fy%<3U!K}a1a#ZsNTeZmt|cf$JJwhI0=v9 zc081>sm^4XY|RK}c+F&CYI?RXC%sr%sl2UxtA3j{`)4%37`4fa-M7Rax~}TBDp(b( z)ta9g$Pza=-?ay^f-;+2802@^%>Bk3=t(oX#<65 zq!yq%=xxlUPn^K9?(uY?2&(Y-Ha8_K6hl!Y@h5d1R9lMd(c%=TKlxXmsc=g?u7D(G z3I=eIdRaNm@fvh_tLQ;==2f1if@j?c)T=L7rQdHAigHf zHTW8XjghN^S4Uce7Ili=61+AtSD3Hftlt{EHPRXXNI7gD4*%8nwf%MY)1qVXu6Q`X z*6OwX-fWZZuvhD2+1c#jqJJ{y48;g&3;x#cUJo{d(}0PC zCeRFMfKxlHv;Y(Li?DhDqAGx-R=~ol0*I>Mc%TDo7^qJO4tFg8RKK@CfD;T(D{dxx?>ZC5uc z+r=Hyc0~y)E0j+mt(9J<-=^QA(>g#d#<{aMVS%)wkF|zcPaUI9qo7jPW$NN*jG>R7 z)CA(6N~7reCFOJ+tyBP$bFqLNBAwwxCJ`c&5wSpWKM&%36AyWf>~~1`K|FDy;^WXa5(3@n9 z8H!|f)aB-aNzMidGHOcAsDo9u-d`WP22Pa5`zOS1f-~7!;*I{+SZDko`=Reh_=N9- z{~P*$h7_(O1r&>{a{uJXwAC zaB*gAPtIW5=u^3#Mn@VrG#)3A1ioFgGrYT6QjdKxa>lN}Fd3p}(aC^Wd+z!0j=2Z# zYyD~Mwp`++I~M=f^LH(Mdc`jvIsfcBKtD8Y5Y)~Mh1PrT{NKHY-`j&_HVS#sVq|9l zB(n*Q9j9Ue6o<92E#f437Cn!>O`IhQ0k<0lnSkTYcsweKk@`35BlevCY=r4!HH7=b z23eycgJR>X8R7A<>#bWN*Tmkw z=;7LM@30eI5PnMex%z@CMAS-kbGS3igzD<`+W?}QPMg;@OSwf z#!fL54Icw!D|}m@0U5F-o{q&cYbX$Qu$hD%6`6?_U{{jhx)d7@RpW)&fA_W~{NC2Y zmt@%?jL-XOFba%M887`h_&K^@c|-%tjV*Wqus}C9()yS#_J!D$A_DMo#&!mWTK` zu_#su?N| zEg4cZv1DS^9R9|V8>?Dt+G`G1oGkfU**6uY9pnPL;FgZcn2#qbiIJdslXaw>>ZA@( zC~SqxoxW@=rb|OgV~P|E)TQdAR48=728Qj}t#-T3)SxMclWK@tvx!@?yWN^i+!`(t zC0D<6-5P!rE*kaRnvH{kk))1vkq%N+X*~IczF$A8cj-)AZ_=C5LPsn{k6_vArKE6? zptf$ovrc@Q9!}RRD#7jzrRo>m+nH0wcRXC~_*q)lF)f?~kQHua z6!vp=eSs+0v%+rnCb{obi~}u=M#U zk#VWMGpF_6{4i)dvKD|x*0x`m`|tfre??cn-}%OSZ|!{x=e#Q^ipIQgKe+xCDu@(6 zU}s4G0uo-Qn0k5$y<26-r3O2ku?15x{WJ?GJ;w5WSyED>Q`axkC4x>71j!l`bO=$u zk{tb51R_o>OhVZwv7H#fj}u9bO8Ub1u}DO`z>qRxO!6o9&+Z`fsxbs+w=?}Rn}er= za6xc=aC5LL$ONH3%Imd8gt*&zgLfARSCRWN6D7ifdEa%*Kkb=Z4 zAqhFh1cr_6!3!XrO$du6-6KLImr3Ux5)R@_nOLXBX?#lKlqgUIWS11iEbgU{QMVOkEXAy2)-#)#PUaZHbuy+Ypb_L7Y0?YCY0~yvw0ab>yUtvsE=J7X_IX-6UYmi5`ZDf^dN|M&d zATBq_%`%PYf=++@jXe4wNfcy~Q_968Gg0uDk_D2J5Zji+KL5)l!+KgZv0}`vA7fwy zu8nFMO-KlqM?!Gn;<~z(hTztWXo8`a3x*U0qQ*xlS0ivMsk#7gJ8a;+7ThObMMwVT z(th#&{W|IfJu!m$;{Er(z3WMB#AD2i^XvDFo{8-h=>q+4%ms$mJ5kP!t+>hDG?CWT zf3RmcS}YWExikT(Fc1p^!XqOzgGuxf30hpjM^LQO+pG$VYMt&tXNx5l2()|JxgTBO z7=~rI{^Bqs3hpv#inN5jLpn@<%JCaHP{x(>DIv=Z5S!Fybt*HJo5D{Omos;=Pl|iF zKQM>57z-OZHpS7uf?SJhiiU=Z7iKi7~I3M`9NmX>#=NXLXba z;^O@@6hkVewxQg^?E&IQVogz26pD%(F&}tq5vBzn+?pV#EhS#355g;KqdZ)e>+0NE zLMU)sgZT8xR)dg<(TUts$Z3mQ;3Z3i7S7hVIK^NVvcVf+XA=~yrCLx=vvUO(Nz z5(h;J2>K6j3kfpy?zwj#_w06`>~vCSxzX7;yN*4|GR^34nx*6H0=Av)Vj1MkB}lst z9={TC^Z^vvtfN3DN;6?kZ~yO$-oB`Zw|8aj#$$pPj1{(oySfUS#Gdb>#xR%qF6_K8 zbmSHv0CEri;F-CvgOnk-YbaNaVx}_iJ4_cnQ(*s|DRe*klQUXYGb!dcb6ot3eImhr z$ev9=TS%0Np=d&+>9XP&7r-F}54f^O*pLpSz?#(h6igvMrlr=Hz+_0qMyORLf$2!b z<|j4fq#qXkq9!DH8*yVM0qD#E@69amhs|A}#Zf}3HBk^HFBk28xhQ$LDCS_B_~oKx zm5h?aJBn?IEY48{zi_mG{6+EW1u0lpmI4PTfH43Vr?CCe#QuuDXMe=wQbBJ8zEFsf z&p3Xv6uY9(T$4O*&OWOt-(q09Vla*f!udsaSair-i6 zSIj7|)IedO_EHzzSBH=yY|`m~EY~EC?zwP3-FM^M#ZScVe&?4jZY!H{#e)CSF=gh} z_ck!)kB_bZX;5dI}NbbI1oA(>IyLl!LRv)7K*t57gQxxQ?z7=#91K{bIByy zl1a2BcSlMi;@6SLk#I zE(om;Z4PyYm=F!?0zqP%XFE*OD;W5X0hjchfXnO=a50`Gb~@H~1Gq6ZX(rJ9gRJlj z3BoS9nkEG{gjS5!;O;0a$eE%fNW4UIM!CspQJ_nfCuCfh)`q<>k+O&4_7L&PXYM%C z`t(>s>ZqPK{PyRV@+US8Suncq^4#rk#jUptdhER%sazf0b&{z-QdFrhn71Pk@(7J5 ziIL$BC(iA76ej;+@lseB#tj!Hb5n(zxH*E5F&eCfV0~zaG0GYh91@zr&Jf2NEmli# zeCQVT7ICI=i*-wIW@rfrh#adGW^LX$$g?k4fyUR ze>?$mJRq>r2AvD+x(UJDZ=u~04GQ*w`oh!^!<`}ow^P-)J5Bx_$M0n@|5`+0D~C8%mm^%Ij` z&wq2<2Y3Ir?U`K3OG|IxxM}en&*tYqVc;0h3-Ign_ibE#?kf7_ef!?}-N8e@!z@M#a#7i$WP9=_($AI0 zDxau%y!Qs_1?Aa_4VBxFV%$DSh1__Ts9eIG zW#roN0Dpi4>2ZcXL?WpZ2dtBirzboQan4B)zd@=CJ(#idXd$f)_wm4aWaNcX2y`>h zY2g@e>pPup>(MzS?e2u7aXZ>Jvh|H~8B7_*r|zx*wi`V;6_*v4vHqHJ)36MmL35>Q zB1(ysd=#*kp+m7B-7V3|qEu;_st8q56jWA-5|?J8RNN@SaaQ_bFL)~9~5_sQl#1FC;KVfpLR%+1Q} zbC%5w25Y1DzwyN6IeVAy{|HbTAjE#fg*nQYg(`ItBG zD!a}R?Z7b^Ui&e$nsnDq?2@e#n!&;RI=+)qZ= zL`Z&*eAzMlca}i&D^vvUIibuQCVW9$NOIb#v;3K~4sqAn23@RyB7}J*E=B|5RZwBSXem3?uElcqa}ht6CxJDok?yY5-?aC6TSoz zz@YEeb69@z2oj^Vd7*WV5w%WeBnpJC%BJh}>I&mTt8iC`2T zNk;--dVB$!6(~vI0M|{sPLit7+H_C$H6dT`tY-mLYGx(u-&Hd!qBJuj-~&XSZW}rS z?<`>`Lo6=IP?hLF;!d$Nm7#*@fbJc3?yl^Wp%UnzD^*mbST1F$dTBT{OqvWP!>Pg) zaWXQUeRb)*m#lqxCQR;`(GB$0KjV1`Aik}32L$DDHx2NYPPbV7osh!4ec zfv=Hp7S9T~3RzZ>F(K$k8qE#5?Mv@VQ?=dX^!^er2q{tWi=sr)5T;z#GAl`xUfLST&^2e zG_#kME@LL0$49#O<8s6aCD>O7z_0W3e{(z)52e3;C4VbZp1c31+a@lCt1y=C@)~y{ z?XZ}lLjApkBU9piToM@P%6kjc*wG36yHwXi@!SpcB;YSOjJgZteHXA?_pbBy&># z+&aUZ6Js)|aZ||A;9Qy>S<=bT^3*meX*y$3roam+UQcN_jnjBq1xiZY)pf|}kG+(N zw6B`vYAW#iI7v3krL;Mb886K+=bOvShfK+o7^I6>9Ijx#OWChYpQ&{Vg^c6)pS${_ z->BoK36-B`MM)A+jv^VRiTwMhZ7gM>m}P`BThg_}TP80gc+;}dEbnJoUPE$DshVF^ zH36kNX-V*-r(=GGxI+~-9ZSb`zmor~p#t0tr(LDhUEn!K zN;FI0Ht8PBb%m20vDpN-nfI8utY(rU8!TugI5CZk>$&aVtnch>5)y?+pJ{0cp|}S9 zVk2t_{bz2!XLTky{(n&WdCh3VH$29-QJdovrgW$YB>`XSI)-A}W0cl)po8kICoH6+ z-F;K1j@q1=KssI=*uvvZnCL>ugi)L82vJGsI<|#RxK}N&I{_{xJg@_Wg6Or8w>q$u z?~Pw^D>VS_cHgP{#k-$pljoUT$F@lcCP5AG>IS^h#DhDmELCHXg5E8@i~L&`&&K9Q zIu~GvLi~x(CItp`1r0{!U)}ve6I1uXE9>en-?1s*@#+gze?$)EspIB5@YdYgclW{B z=MTeW+b`_Le<&EOL;r(3jRF4btwRAF$Q%Pj4st5eNS#FFdTp90CFwL5-KkqZFAcjb zQO1U|)AXM*KNX(Tex`S_om?mXt}g0MFdLzLVnB@;^`Jq%7p#_rTI(8SDnC`8qCElD zN^9kvaF_CX`5o;&<1qc9_`dqFaYC}Ji!}h2sfSdfPy>KRI;jDWB*=Zg24FVF(QXw0 zCz3ha-l9S|FZWr;87J<|7Ygz+}&jFZbA}50s)o? zAwUQrd?x0_NMnk~M+_0OOB%`dCWIurNeEC%ky@%2L@A|yP^1(oQmaT25u^BlR;*Pq z)nf4rMG-$y5e0?)|7PypWVP70Z{PR-f8PJ|u=D(8&Ye4R=FB-~=FXkHyVt3uB*(<* zPCY(9F2>``H$0ZFB##==_tm~hf9abXD-(5-t}Yw>{uqExb*lbiQYJGytj9KTz!0f??w6o z*P>pF6BhUWsq6Y)E8|wiUzc!m^j2qQ?1R1bB)k`WG~sjCnb=bap_Bn(k4lVpru4JL z6vSK;qs1h5i*Ifs#C88XYC=qm5sSGJD~IHS`1m1l(Fr(+F)$epaYo}dI67WFGVatR z14@Za;iFRartp;A{G$6}po{#3-Ml2$fA9ZFgg~Ny2RNAQ_=|$r*Z=Mb0$|q1Sdz$cav!kmJTEyRUan zFYCw8Ub$YDe_{mpi63e{!|(lPh^6@KMr_vE|c zcJuuX9>=oHA8$OH9|eL<8lb-Eek^|~h+#ZEYE*0v%Za{}74kyIrBO3u%UB67armN& zVjEc%uW~d*{gAaeei-$0_EX1oQK#4m-Y?ma#)dgYMCCZ{aQuzgxsSVrde(oiJmqeq=%tL^Lu@8BQ;0NDf0#hYF|lof>0TUkQe(lZV}&B4_8`C%~+g^PKTyjtSo6MNEX^S|WlZfk zq%Lvv*!@zAQkCZ4{sp}1S03_O_S%jZsRS!|_x^r4QI5oZ{~;G=JNo3P+pg%u9G(F5 zP3)Oi#*Ab71@dRN%szh1px)_xb8G3@nOgOkN1GQlu=m$!4t-6>nerb--6ntk@ilwe z)(lN)G$22Qjg!CsP`{B@FT{#`Uzhw1h|Si@p1$cOxl=q#`;7ZU7dhp9ety~Q$@e7l zkL@4F^VjXK$Mfgx&&Bh-_Pz1^9{WA<{C4~8@qD#?bv$2cUmDN9a(tD*8y$@a+~@Em zaKm9F@Pv4W9e1Wq(qc}zwNu>f;>^f%QJ#FGK~esw_-6Z$?W^sYoyAW~$aA}lJS=qb z`}7^_ZfEw1jy%pNPt#U&#*>q*S1FqR*(hJvcT)XXPOQAGlz&U|VeB{l=GpwGXL)Z= z!9XCu0@jE9fc3sWy-}}^uGrBKTbOsCTw3qK^I;=?E8sV&FZ1#tkb9+WB;La)s~;uWq-@g z@3lW}=bt**FC4#d@K(oi2fxBmgPTMLb3g-DhX<$*Gbg%C-Mv%YOE!MJsM{H=UY&`2 zwH<}cF6|!Kg(c^bR?7G!qQ&ap$s6wD^0rvW2btBILBwy>0~X{_56c`0@2h{X(`Ej! z{&>$n?u9qk^Ue2!^;Z+lZ*AuNthG4;SA9n=?efgOfqQbNdYp@e_OKyrE0gcKOL~Yn z|CktmA7k?Py@HL3J)&NX$1nk~t!LxdM{LO5WY!V={_{Gb-|5>$MNb_@-&N=Bo_6T$ z9#+^>$MG-JanKig91(S5|AjiS^zok9a2@qT8>|pRMGp|i5;W6cjCJc#DYh8WnM>1M zLnxo}$4(qe`Ms0I#?V0GGcmXGf%40bUa{&OCUU{faLt~6X5UriKahJ)a@H2=>9L{m zVX_Hw>xku!nY`}Og4FQ?rzb}5%zb=Db^I;v85cCz%G67Cds|^1?WMik{0!kWe76cG zv_9H6ZNBX?+XLcR{XzRY$CRisQP)LxIX^V|8H;;@Yo@!Odv{D(%)_zCv4?wA_j)OA zYJ5%nw%!*dCM4e7XLQntd<}ZMZ?w)?>izpqj$#1kq0w>J1Q;f^yrn@bH+4`yM6q<6JDKo;Qy2G;lvMf zmggoRH2k;1@6U(x;e0qB{!8JB|1073^Wl8>Ul>kZ7=Pi&^Wl6rAI^vK;e0qB&WH2i zd^jJ@hx6gT90KRV`EWj*5C6LY$!{`=FGcKU%Sfl=q|xBeYQz&lhY;r>PN0O4p9YhL z{K3eVbdHL1Lpu@YDcXyYgUP4jG8OMa{xFIO^+()G#gg+V@Y#u2@)@Q0i~=7S=c%|% zo!y0!V^H!C;+V5vBJQQ)!6-9M$uy&E1l8^Y>aXGfDwZ53 zP_`;rpmGXTJVnLR(E0=_R`eB$o~`IoMf()bGQ>G(r2uiPqI)U2Kg#5w6&cG`a=>54 zQ&gF0XfX$zC4Ge|Q>tRw-&}B8jW`x%a=}f~{S`ex#e-Fu0u@hDIn!XdTyT^06)G-O zaargi%2RsCQ+mq-&jQ4~6x|=3^T6|mh^2&iO2Rzwlx1Y!^T1Qmvs8YGqDxgRFXBt- zQgFVMcF_>JLdkrElJ*MZOd~IH{D^xY_NlWzb+%09m#O?+%KE#Y)kBDPA(o$9{xHcm zG0RVbiZ$h#(dtOjoZR%DMQc<}&selAqKu#sgUS zyZAOHpZPaG<80ShG$Ubqz@jG2#wm3x_5&3RO+fx-CD`m51 zD>@!@oIPLB2@&OctNxmFVnlwjs#~n+eyS~#Xa9&Y10(3cs{C9<4_9=PqDLxviKHD7 z@;f5hG9vPga9{2u4`o9mqiHOt67o|G(&^MpO+Xthq863&Jsbr=%eVsh^{PZB&Rk55 z2p%d%ULESUQL8$tL0W^-3lLYMZuB6n{i%B(}vmqT;-+adfJ!{ng3DR zl5VO%$=iX_O_0PxGr_r5wIt7uR5CWhQ|lG~8S0E5Ia1Tgh;saN`&g}5E% zt1am~=tB-ogk)aSY{#+G>msD>${teVeoOzgO4c@&*NnJY<+rHz7AgBkz8>TRl}xf^ zl~t$4I<8QhT2$-vQL0UyleH=pk2cGSjaEOKx}`8{gyjfElxg9ZGJg zk#qOKJeFmv&|16FNVW3NZ)-x$`3;-y|2=e``o;n{u_Po;a=Ts`=A;hVOxfM z_*^{*xBicET^L~_*%PxbZK}QS=#c!)zE&frL-o8_jktg22^HV4dX2J9vlW}YGU;|4 zwW!#mq+QVM%_bjNvJoZznGa>&>B-I-J=Rm=uklQ8Zfb5@)KcU5UURUeIatwF-`tex zxwx^>Q(Rx?Z)^1w*R<9I7t~Z|UL35iX!O*#dMZ3^!HVjd`4z!=p61%`<`T}#HER~v z)U`KO1aoKC1Y2?1GcI%Vcu)HD`l?`aYjbVeu%7(vELCHANjKXP85IO8I_jJ1JTq%+ z>#J%!BR$2^!4$CT4q^+dcCu7J1rR zYdmd!$Y0ys)aGex_Egumwlv~IMN_q>C0LKlDx9f7TG8rhsR_=nZ)>Zm_EauHwHi+& z+H8_6a64V`@eY zpPvPvGe?aa9o5>c+P&IC+FsxRZI5^Z1$nj=g75r>F`wfvF8|d|XJ?LNa4WMu5$3cI>zXW|sg9KWfhBc8EuN8v+zIGYtX&Uasv>$6f zCax{hPJsSg`x^8a?JVe!2AOSSYsFfn&DI9G-L?qyV%uWSKeXKhdX4QDpx4^gg8rrL zm!Q{)Y+_=J7)zQMCnkWNC@ut@rxy^@FVWGiK24tvdWJp=bcuWwu0C785_G9v3fimB z0bQoIfo|8^K`+odKrhsPN?c!|{|xlC`gNeMw{Iq9zr%h9Y4$Dl`#|qG{Z&U|qQ45_|u{xujF4CNCXFBL%PTU1L$2xxp zdaLsu(A%Alf_}`o5A+kxKZAb8`4{5OXPw7DzvuiA`5!qy1AW4I67(0&FF=3kgyx;6 zoTov51>sJy{KWAS(APLt zfc}}|I?&fUeh&IZ=t^qoQ%fft+86;k!-;!nXO=Td_4j?yA2>fyeR%@$lLpqO#-GqH z*^5NPeO!Iemn2sb=w#V1t3T1Sj&+i#2v$^*r)p8KktWpzYv$1me@$hO${Q=%nlSpK ziCs}#;GqPJtPpfyBd0~-UPtMM)M%3TJFbXhhIBksD&D5zXI1>>{CV@|(Mc7bl`+#*>{fB2 ziU(NzKUd6=@`zOZ&KI%^c{c}nqtSaq-9bWHilcbwr8j!ihmt6n`cgkiq5d?02I4Ax z?t16SlXq^mZ=^Bc|6S=Ytcc4nA2wpvTSC{+N?J?nX*1nLJE@cQ;lA##^a>rJ59kDa z&1}qIeOWpi&kEQyR>I0ykgZ|2vQ2Co+rjp*$Jo>C1#or{V=G9$BSEs)IPTBi&%;SMN5{noKjTOH}1-^_lgP>u1+DSVsrzKWLza1oNoj zrH1z!&d!T7kLE3#w|3svd7Wnc#-(ODzrjqK3REda^MK~;<|)nP&27!sH*aj-rE*;@ z>sz+B>}xsL@XSZGX=!*HLbz zwaVLA#|^|{T9k(B=@q8KZrLoKm9rMMoIS%iAIpP$3BR7N1vc=_dx<_x&Tl6jZE1KJ`+Y?X&!9LkuYA?4} z+qc<|IC33#Ii7Sp?>HTm5|tg5A5|N*HtJ;b*ytV3Y0f6+O6NM~M&~x?5hKnhFlHNT zjh9^HigsnWCc9c(x4JgFcDVlPI_Y+}v)yg(HSXQ+r`-qLZ^qbSQe!e=ro!9h?w{Pb z%L^T1pM+MkQ@~fD)tmuQp+h_xh{1WL_8X(rexuwalzW77r%~=yGuQF{Hl)JVUzobHnlG%cg5sxnB4!eDS6~RVy-C{MzkseesX6|@|Ams z0~CM1+BKAWhH}SH?ib1(Gr3nN_w(dFq1@4vdxUa_(4}?=O)dp$Z&2?f?VHJcK)G`!_WB${Eu6Fd~ex9aUmaWRYJg)ZacSWrp5jqkz%C7@Um-`T!mv6-Wa{ zpkx%w2))Qgf}04v2=DTPs~=qbJQ3|dr{D=slWkD~%C17$Rp4F-&V}Gy2+6lW8b4(8 zLqLgL_i0IeOs3@^PHp87Azqs!8= zq*dy=a4CvG?xU!`8ZsV*2983`qmc6`NBj-~rNrVZeyc(SP9E-Fmkj zUi^j~bjzns!=Fw^YJoUxvH`Z(K!dE2qU;Qx8wj5ph&B#E%0rNHAj<+q17nmQbbd>l zhoH?vkbEFVeV!1S0Zq(+RvVO7`y(BIdBKBo7lewSoz;8@@`h3;Pe-|7$R8e>f$MEp z(pcyn(puiX`a5j;Z7IHK(?rncw(BBgSLuH{p#2@-xC0z_K>i)j`pYP_0~+6fQahmW z9as}UuK#hriUX$(w7(PFI$()y;Mf5fI#Bx%q~C_xhak@ea5w}G(zCXKLkDE*0EZ69 z)&c8ngXd#hk?SA4>0F+a`YmsgwGN}!VbnT|TGEP#QTi}SA4cf|u-J2`aTqlY!%EMg z)?uZ){iwAcwf3Xde$?8Jw)Ugue$?ELn)^{>KW2gOxR+zz`JMH`b<)gwXk|avEioY- z9;wrvp$^&x>2f7R>N13aDO3*bxEl>yek=KB9KGJri3xI{d zBJkJwbm(G+>ggU{0e$*$JRiE@s=axTD%#Rem#HC~pALPO08*z{!Jqs}E62!TX(6o3 zE@E3Q6e z!@2197W8`y??B!nTrFd|3=^!8B;SId@jyc zD5*B{D$vzPYmi@yv<{FyS&y^-Z9)+Rj4__oUa1t zNerxgK$W=)Idg#u<=?Wr8mF?qyh-_crA zKVi)`TiTZ;4p?XReEY2GwM|*wA2CBkhsU(iz4QyEcg(S-#;o3;WGqUKLCG<+4fTE2 zT-Z~ikE&r>=_tmGSySqu!}2hDx5gr+56c$SZT+x5d#oMSWfywzt+UY5Ro2mbrM*Us zfPfm6$~IElVf$NG*XC|{!Ws=r9zH8u;@$nVcVF>(W}dm2dFHAsew4aX_|NVVIE_<# zPb8mlk^fmq^4sBI2pWw-u+bO_k3mY zX$QIw_fWC44jbfuH5%=?Bs1N&ueL~6XbM^)GWvAFF>d(GnU(o=L#WfA& zf(shN?L3-NxxrnO#$$L4rSm?#4-MnVJeh{`emsRn@PT{~Ja;f3Oj$gQr_pFWj1Qx1 zK7x;+F+7uJ(pWy0Lw26aFQy5+fEUt5dz>oAG@EULgb>2n#9&j8u34Dz*9B=?`AOYwL zcz`q@19d(^nhi`;=UDKBI?sZqkxl{%fT=(cFq>E_%pNEMDv8>+0Cxd9h_&xV`Y^DM zRkUmh<_2x8OIscZ7T1;st6Sa+wkUiZTo7;sH-f$^P}XXww6fI*d=Oj$T-&lWnBQ_Y zurrunmlezpJlk5*q6Z6G_5=&N%Nz`rA}=3#`6mCm8v~nz<$-O%@|Guq#p?VsNMA$R z)9#W8y1eB$QXs%l&yBJtfvqkO(Yp9j>sVbv*P|99S8=RrVpU z9dd4he7jmH(AkOSkWo}f6%$N3^3S_`vHd%fR8-us$-?PmW`L7^9F6{Rz^{ezWj+2nyfHW?g zA83MqEQ4=IMAB_NG<;|<{3lCcCG>eP*brC)-Q5hR*O$$ zPlO?Ttsxe)Wu# zkAM@>@1f5r(Ax}oUSWN3tQwQj54dIHr(l!EFb=G=<&oB<%Kw#5s&NqZ*;2G8(^M&= znU6F)H$?iZ<%7~6VWSr5bIPZzvETNk)$G4}W?`lqHT^d-~o+41s*YfL3UhSoa&oXQs0?6)VHNk>N`!h`ZhCGeUF)-zQOFLzPlWxzO}qSePfuW zzVFKfm&f_X9M=h280|srK^m()q&-CAw7uG18m~R7JxUX_C$uMMqPAZdrip1ZU(66Qs7VxwB5D@JqL^Ali726fm@Q^gP?U;NY85`=qc%|{ z%BWqGi*i~Z=8C!0Au2^BEfm$Fnih##;itu-K{V2jM3ZQtWg;lr=qF-GpF71z>D;(BpCtr085O8SMkLEJ!V#f{=d z`lVPS*3de!R;;C8iFINf-7FC37ICY%m2MU5#d^9;Y!Dl0z1S!=(yzrPv57W_&0;g% zF1Cm*v{7soTj@7qo7hI1#9iVp`mMNI+)bOscCnrA5Ie*U+9Gy}o%B1gOFT$h#Y18* z-7Ov!kJG*43GpY|DfWv$)BWNv;yKzQ4u}KvkmwR!^ssnQyhwY+-^AbO5%IEknI08~ z#36c2yeeL$$HnX7b=oHmi^KGUcuTxRPl~t2+w>=KR2-$J#4&M<_KWw$`}DNZ=2gFz6D|$hk5h3c*nXb`Gy3p

4@+o^W>VaQIc%93|-p(KNG*_h^!tqtqn=-d=u+P zT!V68ks|IYu?)9gDIVL>k0=}KbAavJrrH?-=5b@HUHJo=Ju!NZ;x~PUhyl@wGlLW zL2z5;pGF~e-0znVa7d}ki_51V4%6Fe7`tk|4aGvLp5bdmXWHV6O0013@JGQ!{tt|-zm5}cg_`u^somabd8&t3SK)Vz@I|&+%Ml!~#Luk&v$H&o! zRs7<|=QN7A0$l;$9OMt51u&;GANewYwnFeil&9~z{v@$Rw`FjiZt-V`3H@tAX)6Vp2Ua zccmrQECq9V8)kLO=4cT@W)b0?WoM^Q#_xoyEqVN5+8}} zYjY%>w;0kViZQHV-qOVgcbT&<^vcy2Ocq;vg7`k`4mwZ!+~H)_a0U6pC}h_VCrkWB zZsD?`n2X=7mXE<|zpPXW$o&rHeSh+Hm+@Hh^LEy8pt!(21g$hEWV7G>+hy$TXjAW8 zr^=3xxCU<8Wo$y)L8hZ`mP>fV0EBO3kg>POb8Pex^7btB*vHkO>& zO0~2YT@Tcsf}a?y z1cI~&W8&8#ba%)ct1#A9%+RkUOA|@lPj?pz;?_r%gSF=1HdF%$)Tyi`vxgYZp&A}- zttave`>7g3{V&05fm_8b%lovc2HfGCf|BvZcYdFcz8BpJzN$mTMvohytgb(9XPq|F z*_vaxw*9%;vs-op+L?cC{5VqaCk2TZpeGB-BKM6ejGwTKzcD@1&#s}uar26LvOZBD z2u3?+tyt1W$&abH?WZ9Ku@4$UxV=wyXRm!8Tn<{R@DVul6>cWZ2)%P7tYsDja(m)# zz?=Or1T81d1ykE=>E^v9na#CQ=&-L>TFBB?C!2@;t@FX_+bqT_LJI#;_K~6R%+&_f zDCC15tY5eDXzkP;DuCK7+?EHD*6%q!hoR6t)Y~h+vZ$E=Es?Ky=_;^R=>i6Pk z2YA1`5*P59MLXfSuP{M*2QHN%E&!V{=H@~aGnM!|Aku!5yMR9M;j~}uhtF{xs;%w& zpM|niX6>B%=^Xf;n=)_gyM=3i#@T1QTO_$h;gdZZI0Sw56?caoK#=;~fkA=Ne&`e5 zWZWtIs+BlH2n5b)5o*mqDOd3wz*gba zaD<(c7-#xAdV*l!u4|p1wcO3#pulPqHHvU%)3YZeSwoXgOf9OAbDA_6I$P4^x$E}T-ILrJa@)}y@j2t&2&oWOF`{S@(ZO~oyw^R znK?a|eSUdC;WNxnPh2M0F++|qiC1h7Sz__boXggFn3WJJB4_q>K(j|JQ%*%}lvHxi zxXc}eP1Ku<_n7hn<|uyH82`8C{aL}`q)@3*s8s}J3bgo6l{0NkGgSDTjyO$^-o*fP@KZx{UTE>PBc8-1Q1Kk9o0*#h?-CcB2|c9i23&+ zj?S)m@PHNjHP|Tyz4}_{Gmj=K=i7T*VDpf;DOrpvN-uxrDTqj;3{a;g@uv^b!y(fA zi^=Mi=b(Hb?^*hmG~!r(iN}PpE4wDVelH{^=#2M4RrI=~wQwPFiwTlilCh>O?oH>z z)qpBZeTUPd%6^7T5kzy0utT1L5WW7rgLaK=tD-9@unjJv9l8=B(b{8R!2S9_;xxb0 z{p(k(yk%9g=C|}|(CTEX?^cWQ0_?kRw!b3WQOO{6cxeg+2y|f{;G88+v3=4H-Ek~+ zydM$2w-_4?e>Kmo?ddz=)cA5UNp*zh&p-V` zp0vCK$GsO9v!?=mV|2F~i9@=Lt<2LTj1N%6@f^1ea#nv%Wc?EUrhW}h)OR?|o7ua{ zuSM{U-rMxqIxeKFC~hRn%ZS5QTfrYvq-ips4SkCicD9pB{B!D-@$Ki#o*Wi#O-txy zUA!gl&wJ}19`;|8z=8=AGiOi521R4@i`rWe?WQa2L@~oq{Exs&QXVwjA3H-Hze=KY zR*BA7cnFpP%rc`1C`@aPZO?wSc?V?>KNd>t!Z~2>wo0~n1&OtjU!9A&5cOR!$DG3U z-Ql6Mfq3@AcChSGYVKaGeJ+~psd-YX>DKW)cwKExO>XzKQjE4OcPu%e7)+0tW+ym! z>8v`^&c1)@>%FqZFFR0FjTDJ1#rAw8y~t_ZrY>Nq#+rTPdQ2I8CL7W#;+;$HV$jcZ zB)hNVbzDrhnbBpB9%C`2b{c1#+n4hrkxUVk@}jC%bhWw@$hVNZe+q5ESb}d27$Hh1 zgGFg!OjWTwhWIJ0cNs51j$ki>1vN$dg>NA{%dy$(`j%tyl@(6lXRRA@u}1!92E|+L z&v7l}KTUD+h&b#t?C5lTzO03`y$ShDPG?wk$=`f9CRRNhx+?KAk0ByW?jpxFtScF>7B36Icx@lL zS1A!unT~Fys+2b!q=uWpd(iVBq@yuGC;g!L%)d}d#Oe0LatV7kHFs`IownQY!$<}6Z=v)zdzPH>qMf z4fpCygpOWiRr}lf*!z9F<#NIu=j&HlJmoU4T2b`D&mo(jE50cDNku0go@cB+wfzEl zl0NgTNttoK#5a`J8*0q)4JGh~Y6IO2ULjrVe;xOWdBefK;h5iWkeJQlt0C~S!vpqx zjZBTfb_3ZneqX}=EU!@dO1Goh1IoDmHM0PCRZeJn_)gJt>+J<(foJuNl#y`rI*QEs zRF56oB6H7&jBepmDnC!=^P#$K=0(itmMo90pl))0jOZh|x8QNnM+ySJsn7dYy2**D zh~|?#w#Ws33!nG*g-fDR5b-8^Y$pU zzYUx7rcjxDgCTE|AQ7 zo7|j&$TGnrmy?KAPGExSTx#*Hi;9R=MqmOpx<*l8g7jR>%q_7j0-BuV8}G%LuHfrW3kSavTMYRM*ZIA0S;lI-FVDfQD!$@@P;pK z5@)+ru~o4(eWxN^$b8r_88q35Gc;Ic##-`iK%$M2?xA@+b~+mJ2eu=rQh)jgY&FxI zs)y|CgP<>{MbEW6JjQeQ$(%s)(V3&|kHrU}ICc*0ofP6HYlD<#Q@!d5fv+p^_m>I7 z={&Ahbi&hgYUu~52MH6m8C^%$Mu+v4yT$XDt5s`iUy%$e)T(Do=JTy?;N>*(9MAGE z45Qb423Lw_7Ia7I+Dknu5{o|DY$Mwa5C+t3%33udUm*iJsJRrG>(p4Kv~WKY$r zZ;R*atm+`C5Q7n+LNos2c?C`FnUQO`)<}Jw$#IttCbl1!$gd%QvRhbY(2QU}DORBP zg(vxhcn5q86QY~i;zGt98Q~J1s#FUDD$&Og(+;ON>{4X))O16&v#t1BH{m*u21pPY@;ytV8#(yB&@E88=Zv)oc_%8NkHr@RI~gUsG+UDqrB z+@V2@3mXS_hk8pa24tMnUZYLR$>6r9lU@VAq>B-Et|rDN&Ogh6wW{{jHi;|Wf3w~I zy8H+@f8*a56-rO3>Llaa5dB85!CaiEtFyKBUK}5-sXk)7apPZHvGljxoi|uqT@ZH* z_icX}7c$Y9`+iJ*!}>`5nCm<9GHq8=G0%O3^H}b?dh(kXR3>(V={@DQqunIxUVgYU z>b$InHan@e<<;C;p7nXJ+(B%~fqOykn5seg#Os!wdwIlxeVM_%qMaNyv;$CDq_&wx;Q+Y)pur(@58E;m#*9~|TEt{O<}@ajQGn{MY?js*>}y7&ek z4X_L_3~LTuqD6G&agF47aYno zCG(Dh4CEe<+?d6opRO8N%`G0;QVqQFI7D8$8hcTdHQdk;T}NSrC= zw?=NnSXvkyY&2ztP)f1daRf#*jNjZsoU+1RCE2aT6 z;svx3wBx=TV--WRg`oV9$S3OjJVB%AWcH(i8tPt$`t`-U7RxkbI8uEfO)w| zJu=(GebRBal134-6Sqkfuw7lF5}AF}KIOQ3L8BB|W#?5QP0NrjLk!Q@Rg6WtJyT4W zuHl1>>WVE>LcgvBQ{0}ei5~@e)7(`Y4P@*pNlMQQUaE$PJ4v>?oDGK3YBrg;xz?@> zFL&J9kL>)hrV(g#$IGs{aVLI>hB3sPMv5_3k>($t?AL|tYTsBt%yL`jy@;H2w_;Wv z`)T#7gjD(|EBUhI2|4>9p$o!@g?l$4tML-6`*5VIK@;-`Px!0-@O1g0S_)eV!i+At zGpTLwkWW7srisETS+364P zT{-IkdCEnNoP5H3t4mbuHkFNfX7fsymlgny&f%!R9H+~OBgx;ytj@oQN8Tb1$2@D^ z81E>g_y*kP4Y&8J_A?B#wY@!d9a^HSW*r+&!1F9lp|1Yjdhfc#V`sC|H?m>2!_6j! zGz^`R$2ekdnqSA}K4inl(H0T0K~~Me6csTd=qRmggfnn-Y;=-H_$8!c`mZ{diGJ2u!*x+c=WLV>fs(HTExPCsvE&5sNVw==GRB&h1 zq3oDhm)Je!^BR0(hh5?4_1*?H?s0iHm1PvWaPM}(J@uw(3|W7tvSk%Jhf*a-ZX2>iH+)Su=T1MKnx>?8f`1##x7 zaprzfnY1KhHE##SSo)VtOYuxg`Ak}hu^LjC8cLXSX?Pkkm>P1J8fq995*VzwccWx5 z>GJS2q%baIFfLRu>0}j2y zY5E_6csTIIg~Cq`mTUzY1rj6~(_u9)y~OX)$PwbMDYq2P_{8 zImbUz9Hq(A&r1%xjQBBC2~7IY@(lSgdNe;voQ>|eVKzAD6a_AWEdzJOx!=3Jax?e@ zgj7^IKqIXht?z2y(c<`phWK{|9=(G1i{CX@rM@|IbE{RSOdsu7ah0SlLmNvH5~~mq zzbcT;n-#F0b2>v>Q79Yp7HVXLFYG?ino$gZGo}_rlY8;2|golLKWJs3m+a<$* z9E+)0ZVE%2-gQCY{%vH4tN+6bb2L-q;hv|KJtxEG--UZs9nPcnRUSLE>=9<6W7s1# zXpD7V=-wZ={G`I+w%2%=*f96^LO@|+D%M(Fh>vsAQ)EBh{;Epd(Bj|BCtiCkmai}q z{aqfP-R)^_0JFD#h_N`Y(dbmCI z@f(0!UUZ@1t7sURKL$lCK3DF!tmcHinngcEGi0&d6vv3OtBkasuE(>xnbGxy3D75} z$fTeh7HF7^yzW|!3J?uKo;TTt=h9f};(ZNzm)MP?k4$hyIb&RZy8h-+P5whR{UOHn zV~npffFL1`5o?fCYp9i))YFd7H9d3GdGxaHlD}frfPMD%5mNE!r#HLnHFo{HQZXy# zuGY_2+ke44({9tRe7k3m=6;`xvYFSHxNOg?(H|cyP86VU=q=Umk%XO7+L-9ydy*Oh z5qgdoT|5{9pp_%7iLLbj1izo~UkYDJjw&NGwTZ1P#sss-Lx^XB0R zk?HX9;bGAAMWpIa>k z$B&SVC&Fii?6y2d`iMnoST$N0rgt_Ld+nXUU6$EO$>@eq1W#5lsxfqJ%Oor;XOi3w zR4)i)eo#(_p5lgbP+b~HQ!cC66xWF|Zq}*FO`b?R(|4bK=V38n+9*+e+ka`4oUxl6 z&5%Gb>+Vq@BbMkY!hgEGU$EF_k5EpbyxJh6Hk=$x5JvnthK zX$!2bR({JI?-6V@cxG6r!s?;tYps$eD0ww-(%3$QUP#M1>|u~i^BuhKdxXSF83|~K z3dvMevVi#g-E6e;N0q1|)R}BP3si@>!wF{YLmB>C7~elEx4EAiXa!VMPvc zRJS2kqv@6CO1WdLpoHv5F0j^8j$MGHH~&kd>v6j#t1P;hYTrxEi!Cy)e>CgFD=d!a zxAr9P?h5be*0BA$#2GZ?1PTwHKB8yCfhUidB<|S^`s?m1v&hY&(}A$oOOhczbEo;) z=>v^lK0FZtkcA)nC$n94{!)Qo-4WeMMy>V?shieN>CHu7Wz{rEc+DBs5^=D(AVU#pS6vQ4`m0hPq&bf1! zQ2}Vg%Lz1CycF4F6=*o}&aq_mV~BoB`aSP~pbGedX=C^o!@HCBs`~aY@@{B3`lAWn zgw`3q?dC#AZfW(6p9L=1`cJ`=Kf5r|@di4vn1o>MdveIuor1MS(tKGxo^2)|pw>FI zEJH^NkGx!fw;mIL5J$t}tVa$Mvx~mbfo0H_%?3@6-A03&Pn#rX7%Jwgp%sRF?<8Pf zb42r2zLb!+&PzJ>LO#@Fr>(ct;;M&h{t#dLGsA&|ywzi?C-V6C^bK*IZCy&5Kte%U zL1w0B1QC{J`o4@79qhqUIqpAnU#GsD4VZ%_I}EvUtw&4KRX;9 zRPiX;&fcjTKv^Jud!PI5edN@A1=M>hJXJOtBYqL|kgi{qQ1EjSYvY9PIo^r9KM`3A zX#3tSe13dOzVcPyQ~I~|W@nR%Uy8Qc$plxvY(_1igRooHltO|o=31(kpkT_mqf~DK z+$Msf%waS9_t+I;+!YA-16lJ$N^4-nennF&7g5G@Ar0KI0eYpNp4)u<+dBvgg< z0aN`&jiY*t12;BK4W1VF9V*kcsbgOE6CbhfQz7ia)gc5vX1c`?z6y-ZqIq_|9YSi# zf$0Q&p9DI;sE~(u9WB57z(=Y#NPXt;T?i6Ma$H=K2qi^7AEPhZcuNztJoE^2_L%LE zhNiE5>Incq|NdJW-GXL^ySo6>*Md`B0>v6P>QI9)9C-B|6Mh0u8IBL|@4NU+yLH9W zF9>^-V?Mjg9hSStBMC{sayJ4z^_A54UY7TjIWHP7<8?UO{eYcNG^op&3#*E(PWVL z@Ez`J=<`UoUCP@#%&#EByl(P4!EY*riW?vN{6=)%;SeF*v|icSY9$NY^JWHlI*81l z3f%f~!0|)wcVhCxmAKI-sLe+liW+|!ygs*Bw^n_1nGuW4wvQ#UJq_&_0loIzG#Au} z>4#i13hKtUEeFqf>Z$(XqdCDJ^QDgP7_Q{FCl|j?Nz;vhD0Z0f`gS;^4 z#ZW=p8;Rp21sk7!Ze?>N@D6a&{G&`bR1oCzM_$p_?+8@b4LrOhU{R>M`xCmc{)x(8pE-AaT`?@Dt-7cxNhR5 zQHw7eFYRmqq5I&b1kEQM^eyTEQuv4l@|^m2)yxc&2v<;qARKXW;PGko(IN+W{0&ZE z9j#eokP*VWkAwU)`FE=vPC9To*FA@Aml24FykHj+fNH(PpbiAqd(0Ox;AU|AEwRaE z7VAQ^SDsq?U85;<$N-j=pmE|yItKv*Y}+dm@;*Ax?t-S@PvrZVLXO+*xe`*BA2ADb zWYyV(t$vIjg-^3jg>^*WXH})^;Z13&2PGt-l;Li2#Nj6Hm`Re|o2b#1VeB#nlTp~m z-S!~&O-A^GF+vQJh3S?l9_OXv1-z3yiUq3t-Vx@@iX} z6L{6}#aJ3oX94nZe$;ud>dcAvdigdHekaIq`aCr9v)ne`NP@=zGF_iu)k`OHTKcK^ zW4F1|vroTO%jT6llTRGMcRhdP=od9r+kn!WRxL9(yZ&>(Mq_B(4~qNd?a%r>kteWl|>nsWBp( z<47>t5;pWaY@fd3UBB<<>ZI^9vwe_%HV@&BsbGh_l)PsONkZehlbB11rQ#lMmJ&DZ zOgdKzEfUE!OaFxT2~y7)3OU2$YJNrAv@w%|%pAw&PhJ%S-1qoVlOLVE37i?rX`85} ze>va^c?#vQOk4}Z@fY*0Q3UUrb&yG(Aw*qvs^Km!J72Nvb)8}< zX^VZ#Ib>IhD4bg6UXHaxW#45?04w6yr*H|D#|{k`OftL^p~^9ddcN(+jj zjsSJeN}?*+7IVoeXh*ny`IX+QAkRA<`HHZG)N?0yI5Ycu7dc8j>W38Unrr8j_otb@ ze!Gpz0mSWNY~qWyczxx>%^H^yU!jRU9*3k8p!xCmhP&M&LMO8L7bR4{QTvdZo(q1> zx+++!iV%o1rb^kr7R4DEx8^&(BCHc9>`ASRoVJPn)JcCn+l12-LulXQYTA84E{~SR z{sSmm(QMF$>Y=B}2c27*;f-g&#q`ntWD{u%W7!u;@zN>d&=P?Z-iwLB2!o0DJST(W zD?DDwy1V9EzOw<#b@uOy{-IPC$>ZW8$?uj^9_@o&O0s@2OoBWVtqq}d;^1$xqNVE# zn)<3s-k#I|X=~*F{Bd%|ez`+`3+Uyw8-U(;nYH)a_2Z0qZ=@w|W$iued)Yha)yhK= z&8z71v=fiT7k?&2Huj=#2th#EJ=BCvnzd%W-f%@lo_H&x> zI=&HjbQ}7+zNk^|#!IV81*ON^nk}o2Xi1E$F(HB58UE<{F5vki4-T}4dW;VxR+a*{ zjZ{KKqst@!bwt1M70<)3`!(1O9z=?php@LuSd(HXNM$kmkN@Nj9u7!mn)}e{Etjj^ zxVb(YL1Gqp{hSi0P+CPx!S5pJb~JpV53H)D;}ftyW8zP8aEnPpXBQoP8)~2`VRSbx z{w4B#CU^>P{TNg>p(i+}M6Ns#)afQkUAFUkbxFoj{l@PT)sAEr+h-D`BtSWCbt#Rb z1|*)y(BLE?YPh_)gnR4&;)r*s{NTB!w27TfmGqrf09P}kP*qu6vRo|+u?3>BbfoFG zfU%NCYMe-{lkUn_5$QCU^*H+(_vcHXg$-&3?)DsZ4Bw!xM|JxUt^QoTsiF3hMd92?CYU~#%BBkF&f15GYQy08+=p3#dwjDB+y!`Es*rMGLqm1RGopJtW8we{3)r;^MS&5DE^w z75=3mj>v=Yqc zRhQtk?BDd=k3^>+V*g>H;@^{Js=8i2((okmh^uu;V9_GYV8!r_L3+!Y8&_p6UC>{R zrs&*RbF~$&MCrPEaaHNrs|~TL^;BqDHsge5lUoiDzC9bd{ZlttzC2Epz3Ie39o(&p z-s;#Z~{9zxxsP@Z<3tIw@NIu4kpd`m9Hf(;L?%!pDC9j&e zXPev@{2ZPHYYVi}y{oIGA{}Y|X#vJ={=BALG)7pCP*4QV+~Q0n$sy_@P6uhn_?NrX zD_-KlXk&L#vpU+IF}mlnTP73b*@{!=(ICmqNLMs%T{|>cr*@dfxaOrXm7#}RB1uu(Oh|?aAQEl2lqd|_Auh~aL%P&Aw zUS#D1`P&KVLz^sIq6_@8ITWW;G;mIz%IJo4{L!c-bZ|`X8pYG7vzjiKYJS#w+@!+7 zD`#%{Lh{_Zp2fqPLMPlX1thPx`6tbqmTiVUw#JU%$G@m!g*V#& zNATbDZ(P{9bV#_kxc>oeHa3#K@K2kSm4y3^Hj+e&zlVY(7xgS(*8^L zKjZ$J2QLT5fAQktew&HwZKnTP3m4Bnwf~azjqkrw|K|$W{?7XboNxHQ<=;8~rTe%1 ztBZf||E~Ov_OD!j`~DmL>WTY*E0LS`O|k!5gFI|+Dr95RBhe%IPt)-JZ`1r0iRG^? z-oF1%%kuX54>SDJ{!8EH4{m+-Hc|7YdD^nZE&*XRESL;TNN|E}kMr2GHc5dWcJ z_P@*h@6FG~_Fr24R|o&cl8y7tI{!J6_1}>K0?ZPYHZG=4%n~+VT}%O{#`Y$r%yOo7 z<}Ma*JCcou<-Z%OB&=M#Z|9qk5DMbIr=dssk?#ke`02(M-qj-=wh!|N$;_x9WJ%t2 zV&HrwL3+f8#}w(ONTDE~PnUa7Vu1yRujGhZ3u?wm8d$?{SJkyzwk~n)nbBSZP0#3& z-tw;UQ^OX&w7f39Uf-QBvQD!moI$LMZHruIYqd*Y#6a*wXXx8aQ2ysFIwjUe!1YVvVy)2@~e_mL>a zUs_-|4?C^424R@l-6j|#@!)4_XSjV|?xFdO$+=j~28wU%Ykvm}2i>lQK8!x}qPX^w ztS#1V@aWhVRq)Xtdytx=eXU{nj_(4OTsSwIwq>PO{uX0Jty@!JcR{2u zrLDq0tBPF`?Bif8`@?_D`s6rLEk`&Am-~LU-YlB%H`4XEP(IgV8njk@h8N${F8faM z%)$iDiECAv#h8Nf3O-^@IYfoGQ*(XWBO@-nigW4pWJZy>*;{^NYD_afCH$)0fLoCM zE~Ik%hkdJ1OV>sAK9LEd+}C)ex46bEe(g=WX%%fN#`j7QQ_TBrNU|GBbzyiML7nNP z-{3yUE`;1#F+B*hBITKN*@=;gqEgL3`s?V1hvNZ3U>dIsuyB98K67(f(#p_Wpp%-Z zewg4C{N%Ju`QRO=_8)JQ58#5ZOotlIC%7AbAv^=q`sXRzumX>V)x@h!&1uEuP>+WS z>TSHb#{xSsfgY8Aj!AzFVENX}Yk?QM+k9IS<13Ricjob3(c(wNbFBZ%;|h~f4;jXI z6?HL;ARgFvWy5(fF#I9nP9Y^Iqy1tYT75{=M$x`v=h*Oom22e@uk**=bKr7UwU@OK zD`u2$j$Qc)o7onzRik3mt2+LL%n`p0;^TVvW6$HssM=E)`rV7_MV8}^matOYW!qHL z>r3uqlEmX{Q*2AM)oiJd=ky?U0(PtEwrmoEevL!Nlc)3UaHg8NHc-Gh)cv6bvp^w5 zpvYn)_#Ey&M*?+d1aE`4BO@kuOU`Ak6sLN?;?E)0s6?XIVDXfcof;tPFh$TizTf+a zZZI5UYf*0d=A+1fw8+){9*OXIW3)jm)rA4~9xt*LpAwbtt`ekVnL%!-Xg>JBfiXfkFJdFON(7v?VJihWfcBEQ`uXd zI8~G6g4#5+v|i3^WcrMyGL~ww7B27*?e(k#4s#I=qob+0h8353X%FaA1UVIBB0iR_ z8UNHt%wx0L4Ud+qS|(&h<^9GG)bx1wicuhNg0d_zjOMA zietiEn2LV23>NDt?=be4MAE2%P1+cwuft;%v?eqlgK>=c#Wi#{=6Yfhxz*Z)oESM3 z&jTIA@g?YbZ(i2&L5BXnhE#x}n{}mR8;k*G55~TX$3%Ki{{Gl}=vZBqxn#gK%OANO zX0b5H#mPa2o+0X#>Wr~Kg0E_vRoXFu6By%6wKXNh!T2;ro{6eUeTd#@ZqX`wkBIX; z>a+{!()7K#TZwLJQ#0aAYUSFcV|=xp354hBMt5|A*a0%EvP9-4cVAkVbi8xak$m|_ zb@(DO)0~E_LN+GUK=XlL7`wik@2Fz&u$jWWy~C)b zoIT=Zlfb}FCAlpgA5m$8H53Vqujh!ssHn+TQJv!P1?e-hh4jrXvtWXAe8@)>b z5e6%KcHX^n$D)kxnqlbL-=V$qRxQw;**@JrE{?8tCx8JDq<=t zlcncs<^pL@R(txa{7%V{*f>g=KVDxuxxmK0<;7E}XD$h&)1@s>)tVQCHO0Oy ziuB|xAuH{qVJq$rlah^LwSFmoY>9NW%JUlewQcRiGihUHxmlVoNt&jzfHikza%sgC z!y=7`^2vyxKF_KwIa59XMNcik$hnF`j`HQ~{jHoadJlV98oh*f_rZtZ$TKgqwmW!3;M6*F(-Xl8!K&U~-brdE!n=H`DL?Y+5H*$2tG3pU zxVMHwRv7~5lFh~Wte?Py!y2RqsZKjnsz&pJ-yBjft4IPVao!P`Y7Oyy2Yr}2 za3{muFO5{)2~SdorLWySimaT^97uKpS@vTy(-j`c+(b^_P}K!;nx~Ne zFqh2Qg(Yk*RN|Qi9?BeVDN5 z;zds)$5t{OebKqLozC#PQ#T143uU{vFmr0{d%rBAERbGo#8g5KbI68ciRz}RiKrti zYH$XEH^Ruxqlmu?PuF*B(8eZ=Y(!S}7!i<^NM9{QInHh~9PUHrt4W&;@Hr>Q{dmGc z26S(~eytuX-$aQ?@XV1&jjre8aMnngKVQbSXc>+Y!jY)O66X9Aq3vQ7?R2A;h%AI_ z6oF+f?U;|10Zb?D*$3Jr8pUB1NLML?P=KXLU@?#@utpX=5iAc<$+JiRi-XK)Q*$li zjmoeJq|oERUqD{82f6R1l@(N>(eqfd4@o0h6fTi(9Ay^4ORVl|`y| zWls{&hqPxG=tI?00DKYywaK1`V-d@qbJGgNZv4a|mO0m;eIe_~%DWQ*2}_^1V)@5! z2-3cg^ql5-Xn=x%E#y6mz!u7$G++y9&mr(h0W_QIp$1x&IsZ(nAG0wFY+>k;1-8)i zAOQuKdz^s+^gR{19ugn}ne!SfMd|ZgEJZ0t5l~;Aha5;UZ;rW#94NrhBL)

45<* zG57caucRC+ux_Os>#^LWs}wB)0(wqR*XU?AZqDQuX8kb;){qfVvbtAwXS{9wyq+ zqzwVu(FCIcEdJcR*bQ@_O_EU>mQEgzB%`o%)mcJ22eYqX?UBBlyKU48F{mK%rv z8-y6J{}CWj*@ZzwUk7fB@)GBt^<1%1uKmq_8K#k5weSywMPDiaRQxj~# zI!*=-0U(9#V2+Tdes&#sH$s|9=sE&7LPi(Sv=bncQ-1#o18f9NQRNCc@C?safmi~l zG2|)7XaR9W4-{ZBa5w-ntXHMd5fFl9$}s*3JdRcRjV9~h2N}L}yd+1U1Q$hj-Kxff@uAI4t&_|^8W z)sGO-UIR>s+!e-n#MTA$_@#+Y)SedD09{awsg1%bHBu2>Q2GjX{2jP&;F5JvP^Knp z51r0Cd5@G$Na_k|{26eIe*JS765srN&ko!ib|XHS9|Rt+N%&<4em|Z8aR0ch;PQD~ zA8Y`abkM)lp&eudaI4JA1Gq7kMO*~OT>-Ng$D~c6fqL@FehMzw33}2laN~C1p`uRH z_~!UM3~)rz5gEvdbR15#E@ICId>J-Mxged%Pctii#ST6OEQZxds67921{Y2Lst&IM zs2qxzqi5jBUkC8z6!Apf76w@mD)TER7yc0a zUieT1C>x)`S3-ibrW&IHOMq(uZ=115A4XZQwlu03A+AeTE@^WXWp=5}2@n?KU>HAPnU^&S&-edU{ z!BU*d3c*q+Ifj}cnl|Q549yt(#D|IMiHQ%@yl4@Be%{l2b$>1pLgjg_!3d<%TuJn) z^mG{?q^*$S!%cENvDbb~lT}%k4F0+Lt{_m7rGTkmq~yX(S$Y~wl0@NJ0bBI82&V`e zK63SF5^zx^ng72)ZPTe<=#g9BU+ z#|5seiTlI*VE7;`rB?aE`e6DX`k+3D2DBF*<8F&0J|p_PAq#qvSg)jiK>Op5C<62R zrX^Py`fMs5{2;uJ)d3B3Hx@+pL-HW?K)d7Zw1=sLZ-+NwQY1-uIiFSoiBvfres*HL`bJv&U+N!g~dH8@D4hk(#^b+fdr5B(jG#?rB%FBFh#%h_n_W}DM^R|oOtZLeO)w5hZEV|$t1;9h7S zT-n{|XCDsrGiNMS9X(gPDqmVUooXzu3tw{0ZMbMXY5ATVXSat6bZ;m<5%8WT{8N8| zai?YJSi*^ia!@QOjwFGK<_J`RKKs6(Tj!{9R~^`35}cXa1get2%}XD)nQAYCF2BE;aU7tBJm)Q5v@zr}`VEOux>u-@NQd4g0jU4*Tp# z$@$3Lu$(h9= zMO}lgCIilKPe-e9AjhCG=P?G`5v5MaZGaZ{_mf% zFWZZbkUXZs_fo65EHW~F$l?3S=~k7=ZynI|nDzmE^}p>7GRw*DME*QgE1J$8(w^-6 z9+&9yGmg*Dfgv(dh`pLu<(#%ln7uPQFCuRBO*XIbNKcJq_)>mEoIyAXIZy3WRjf zu5%etSHWswxxgF+xV=NKgDr+D|AaP<&IKFOp|g(n4w(z)>JvFOjCCMM9?2QJdIyOS zw*yBNsuoHa3_~F5`UfNab@&w6osO@sSNjrayQ~PHaH?oboekh z@Fz^RH)k+(Fbe^wO@W;q?~LB9!_@@Hzk~mbG#Q}w4uJ^f1N@f&+|O@tV33TEYy$AB zU;rI&h+yIKawkAa}_M7ZTVgFT~L_g#;BJ@9}sU=1D$hZN`@&=}Ylz#GULFc-K6TM1hU*N)%^ z-vakY;z8_z;_=o4)`P+W(}Um^{|x<1Zry7AaP!z`4UT!Z*Tt2O7dO!ZpJ1!t=uN!tuhqHYc!iaNYsH zfYQKRcuiPMI8B)5z~R8*0J%W908k((04)$LK)>Uz!?Oe2p=g9Oj_`;+k7)zn0Jm4Q zNSsafkZbzleC!|lG*e=XYoyf^>y|88Dj2XF>#p|A77^Nqs9{$G{<>jhT#<{!ws zb4{Vn$G)+xW7RkO*CPFYnW9(xkM=nX{)dQ>a_Ci5n`=G~1)0 z#(6>N`0X`fDL^;RtycJ$){PNVC9}Y~Q2H`d8A7>WWNG5I(mFDL$Ts`n3eBhHg%u79 z@k;@HBhAx{)A7n~r6jj_*dLH;9iGfst+|>Z)x#$`%pV{|~hz5LeT)xw# zq4jX@2>>THr2-*XuXMb?yC(79pw31{fg+FLYN-a=~Z$^RYPPXUdbeJ1i6T z{?m*8YJLL@{ae5MsGW;aa1T9>ZVu!Y#;V~fdy9$G^DBaBU1NScELEOftQ784TJTnp zvJ>(GWjVC%g4)tof?A)@8d6un_DW7GBcMi&Ku$vA6{ex<>SngYn<{VZIKWGO4YURd zS}62Qd6<7XhAsORzTlU|6}J(e5^m)E0U(^WK>tGIP3E~F1*Th2<;%}8ZZ{dLA)Ln@ z5U%tUiCG36n_mO38Qed$_B=u-mmrw|ww*WBLPBe=6K?D841|}GC+3gnA=Bt(F|2&{>UE3AskJ)gR1IC%*HtiYK`>jb+p%*bs1~jirG6%*u6Yc zaaZ8Y1_4hmyX`6c+SbpO!V~E5$u<$}TOY2QN0oAvGSrlBPZ^=H#E`_AM6T~2=xJ4> zCY;6FIQ%S6L%O=Er;^UMoP_B<&}Y~#heS@fgqk8T{>HOP{}CZH*ZO#Zx>C?Bz2h== zxf2@JsU7(dvrvpUEndjlI=0rwe02Izj5d3)gfmT{n|4&l*ueAvr7|-CvFHbeEKg=4 zQc)46EC;z?_qVgFH4KzByd%#(T7s~J=O#??Do;mx z5`c$>ZXrCmOrV9^H7|mljXT+d+@OQ6x%>ubN+IpQ&s^6S{ScBN;V-^@jwXtTj0Y{>OsPWTxp&i5m(vdx;75ky#j}}R zm1Pgt@iLvv2zZN2(uogYrao&13wV7F3w0;D)zD25tW47<+O~_;^Kw4p0LAk;J*al$l9ROT~Yo%m)@GFPfy9g(=Gh@ThErJ z_y@X1PghP!^H35Oo7C$Tgl5gzVro~O}q9#s`8M9%9-b}e4n(`y^zy*lL)7 zSYzipe|C3ifBbU(+N=CQDT9kV^A6^|GA4)!o`Mv9LP@pV9G5gu&Gv>QITOFI*G7?& z>jSs*7S0vIx$7n(dfZMME;s^^qM1AJpQf=cH6FmFi94u z^zF)|;A2HUQ*cDa2(c|B^+0~+1hOdo;_po0A334OF|Ia4cW(|i*YRjxV9_z=Jvwcq zTf&g`PI$`vvf#;*2}w@P7G{_N43mXcx0l_ZJ;ofrtF6AY0~{Z$_+ufiT22^W=4>H& z#>En6Q)4#kWdXJ5Tfjz((>{Sev=Q!#0&d-N1zlW+@Wb2|NHtHH_Lwer!PQURxWJYJ zJ~^FVHNE@tN{XYOxqj%X)=Y8Ms4_hcG?>~HI=kwcyWgUHB`0<+gB(oTh0i^YdA#n; zy0E`^JokSoEQ=LAr+a?cy8eAzA*w!L?4^Qs2Wm9TXi!%TSvAOZn&P-S@w@(`Iij*sIW2 zLehAyYcuBsR=U!7YTqtGr|}oN)K&u18W_CqA8l>Gr>$uXwQuhS*-w;N=HznU%vwG+ zKzaFJ5Ap8dvY?&9XD??k>2*S*^m@h2UwEsL-cl&jCeox&7ZbCOzv;^Y|l8a_4vTWNSkzguN}nc_?Q;YeE! z-ILgofBhoGE%}VTbgmdqD-w%IuK&oCzY@QJ(#=1Gf&-GPhAnkkeZ-hn#CYA9RLn?dO+=Qf z2H0LS0?rPV_+c|E!-_rzMO49pF-zE1i>%jt%fswKDu303$?Jjj(Aim_ijIj&_nBo> ztExxIzA5N>G~k+CXCjqf$MDGL9JqFZZq=&HeGP2IgBJNs=b3#c0Dr0FvVQwSL|rr7 z$n{>akjJFFT7##1@_TEtNt9pML;a_gYV{+~<0)$lPrZK2PXy{b>ou?PIqCN$zGLb> z{(NOSl5yR>7hL_cWT$7&@DCtA@DV{%s8=NA+MFnwJ(N+85Qz)P4;`wuZhw>LE#uTX;s{ zvesG+-N;R5;KS~xScv;c>;3$1yORq7##BHH@iVOL$w;^i2I-HO1Bcsb>vMpWt8U$` zu~7NG3~UbO$>7}ebTxE1PKq^PHLtwGt9+*XwcIt>Osd&_Peivr}W`Wt&herkSSs!yJ)m?@jNZr@kPV~stt znRbISscXEIWho!?ETRF0yQy2AQ53FBF+ zO2GOTlAv#qbK6qSG|-CbC~w(^5~yb^l6H4$gxJ{GqlT<65Fi6#7pG^H(H5CAV)kQV zn8~f-Nh%OCb)LA5x#!Emq(sL#)Ko}=As(7?**fH9b8u6juD~l}HOvZ(?b2#HOk35= zM+oV3hMP;yBDr1113bC)KwMi$&^`~tedhGF#yN>(S$Gk1)7#Sx0vF5d{RG34v+#_4 zeUmgG$>V!2ChQ?Yk`jCS%kX=EQH{@)6FTPa!q~A~Esv4BaEa%|Pl=*+8ke8ycK45G zOv`jb!9Nhl?J*G-|Lir+prLWT46T!>V;NZY+V6E4b9~Q!_0ygR|z_XC*G-)-Lu07Dyy=QVNU;=A*}-> z-|vonvidx1iF#X#(NNE`iC|KuBO%5&-N86cHmbSP ztee3e-yPIF^GUV7#Dz<(*5!GW!0OcGqlwO9SH2NOd1_lD$ehYlVSDWcJ6FiQ9> z4q9_VQ6adxckQLfvNl&IDpJOsy-&O@Tz9FP=-Rb2BjC&mnX7?fE}xQ+$ZnVfM<`-`=E^*yhOnd5RMgYq@0s25@*{9$Eb|6#W*VyQ7f!=)rr$y%=Z3+)XeX ztMaz`88dvh{i*++j@J5FSaf#nVER$?)&26N%W&{Dg-7gYmwc!^PCIv}++cmaw!(V} zCCdqIS3fb+{taf5(d_K&DvgLVRPrnH|04RLcI&;Ki}mvJEF-c8+<%ulHzrE{3_hbo zdm%o{h^e9JziXcw6UBY*-VmjDE;`GI<5;VH_R$mdCw!FY^2d4X^_R0m8PXuzTWc2% zUN?k!!QE&_HW*gXpqY(d7=g_8Q?|dgy0NPb%v1ne+@E|tiV?7zraZ~?0)Iq_gZv=bvE{yY{FHsGhS)CHy?DDnRQiZH8o z0{Mzg)~^Cv39ZKzg*2!eGp@XRJ@ytXa$7lVCY@E8w2G4%H6#q{6hoa6I9EbFvHm-P#d1+(uoz?}O$R?~@gHj=&2aI6WoX+9tUjR7oLudlJss?G_K^8XL0VmJUop#spjwudUo8l-6@ zNg9J~@2`a4m_}>=@T~g~IenWh#pjUd!s1}d!oKNew)R(H27Rqg;lCV{_1xx?vUFDgGqm1d4kk* zXk#Dg0`(?BwbU_AbMIS~_lL|H@kY{z(K4l|TlR9OS6?A72)w)RhD&z0wvIC6+ClZd zB-&=Zbjk}0^s?Npxmi!st=Bj0% zlh8fY-0if_iZ{5#eQR4K7sy{R>H!h;v*oiU=Rf`k?zk6>H%worAUE7CJ~v5yX<PQNtJ3YN>= zBwbF#rNGHrO-5?akgy_%ekDopZb2cR;c38Y1%G#Wi04S-pt?%dFb6ubL-o|Yx)<%%CrOaUsw$Ec6`u6V4z0(2 zB!6)As!?CCOj!}tK^5T6X3SOE(N`IB$|?yY2jRH3)~9$X!8+LALm-3 zK>Ce`_vEVXL>k<5RhKQQk)f;f0MwCc;mTs|tNhNL-kxmha4>C9s53NeFr_=R?2#@r zc*)&mA|`>Fag_X>J){!gvCx5?n*&h^N~N{LvZi{YBr|uOCSt7_y&D z1x^G`h&6}}27g8J75_*kl#;;ias6#>lg7dP`mC+HRJz6C3VCQgK3is#BHa^G;c<7F z(K?40OY#W}n7*Ho>7R%ESx#F4@C#laRzrJ-WlTq%o>%8}F3Q}pT(ew{y|)l!{M{al z=P=qF33lcoH*ua7cUH0W5G4f?pb)Rs;dV}9xFUt1=R;B(U@(nij454pR>?DFY~xxvcoBKx59$HA16d}Vq(yEC**yIuB9z0vThbZSI|_v{ zgQMAeHR%ANmvyJJJ35k(EUfwLv?IePr@>S1RC(BRn4vybnbB;$^ebToUPDRCckd8V z>Ru-DTgTt>QKFRMo@+RVTLkDhi=^#cJ6ds2v-`}wG+P3cDTnAaa|&*)ji^)V3sLIx zEt#>38b*75cz|3Kc_QBNn%e*Ar9SO)oXk296*$Vu^wdd4+lxJJ-2<@;ni1x(LN0>X z!y8s6Jnf5PM!Jhkf$7{3{&^vewT9Que=;X)upcMW@i=~6sT@u$s5!qEAzf&8H z$OX?J{udt68BWh({;TNHK0O-|UF&7u+&IS1&6G6RMzm|&Ahci!<1wG-`cylvR&P~0SS$BWz-W7ZL zfgT332GA{=cpA;!g!bs2_4WoA@TFreC~h)x^yBr#fPJbM%fp{b_qm_K`8$QQUiVHt z#d|hfwcK~}bBj1bxodxV5@dVXJ#+24R-BbCSTDL&$V0OnuOcob$Za7DyVsTUzrMR1Sqiqpaa$BsH>4{qMbniuH=9N|_BWXbnd>PXq^LQty#9p09Q2{4 znN0Jx@fr%Z$2J&ziD^qK1^BGk)I0qc@9I6;?nBe)54s&n^QyR6wzqzE-MT3@bKzU{ zgnI&i@|ED0FwL^&HW{;87Q(^c&g3kb)4R;EX|kf9;HSRApMsu*@s>+pmDFYTc-e(A z+t_jIo@8a0^AK(kMw?b1gfaFt?#gqi#9op1*8iynqsL7Hq0(lRts(}owARmHzyva z=trwGC=4r#3NSCtccxh^Z9Zh}LYL+d)QL2s$zxPlg$+i?$G$q-_tfsL*!Ed0D(0*L zj(?;v-~XWGzR^!VPcSw(03QDysg1rY>}$bmmoeVsNovigmf$=r=WSOR@m&;m7VWRy zRV+7e=b%kM3h%S}r#LWz%(HQ@sY8EA{5FsMT)WIHlmafu-hrKnrIR_^<}+`546hnjEUG#$%d}Yf3%HQ$E+KVl z947ZDyJcwa6Y+9;(nG6dDVD8g$rHm9Kdqk6l9d0_N34lBraQuWLD`>4?dpmV`LbH* zs#GR6^t91tX*^CiDO6Q5y`ISDx<#VLw&({TB=J9Um{DDS@fY^wpDA>lqeT6v8Se8 zdT=IVxnHW>IxqjiE)DIbgJVKiEMfxX zXF+p%Gu_~k_AIH%07Uvff23$i{SDMbp72nlwo$}9kKNb%jH-j^@tetsCXdXZkF z9Gt4P@}{3XPkvv=@lAuJIJMvM zCnYn4`}u^F*@l;TrN8k;%3|>r$@Vdr=U)3XA$NQfdl3wBlO7+nt>YZsOf;OB#U2LS zX<9$WT-($&X63BNWu6>pW0ngSsSO}{rBnKGsCRzIQG!)Lj)*Tkk#MgOImtX(r z^{cz)=57aUuZSmchA@hBKVor4ve&jSIellC?JTUKpa|~YK=HuI2`YYX*w^F72ZOYM z?Sp{eKor|Cr;IE{AL#$(W2_i4S-4Y4fGpTBD}Zf!_#0n0pFIqQi)9E=?NZ~ieGqh= z=@H9E$?&@xGaS=ynbyw{+HSv(N{sGKmqSwx)L-j;F+#CJsOZCRZt0T5kz>2s^JM#M zir=BG1)$C-!x!fh9OhAseu5t-T)KI;^UU+nsok_Cn%^#DkPTtdyvI?npO`K4!M!8f zAytjsAPpYN!TxQ3Z&ebM@g1&)(=&FzO)OToSDPr}?fQJjIe+X}H^^rVnYEMlmieT; z^NQJLZRp1R?pb8*1<_->gBpo~|7_rG!lWbK*+8HSrjQd^u_C`33{3nObQTVij1fS-aN8U}X2^3(3ErJB(LTDHu+xdD{x*xL&2*yWLGf1X9L&-` zdI#!=w7(~?3lJA3{)G!~@T0-!yJXA4N0QxdV(!DTHMEkmAp;rM+PG9eaWjR8GL(4k z_y1vbeIciF&6;*(4*|W;nsQ_g0lr_Jbd>G?iCq!mKpk?(t`?W?g+60iLLs4!uda?a zqoO9GLXIy{Qc`Gw{F)GP$k_aJ$lGy^HlqVV*R;Jw)ljv7Shc9ti)r`Lk!NggQ!?*G zdbBM@f9FG~>y()Q)rwwPbi!qc6tiEjj=qPxPIe0%7-wHr{cS%^&Xgs$YBPFs0?>$S zL!%eO`)v44HB3jWqqSq$OW6V3vr~9|HfijnfRQlbTH`(@KhVdrOlqRyo#-i!J}dsM zI{9?!dj|JzpXylGI>94L_t}YxvTTZ3MJ!-(c>PrO;(_tWWtE$kmZ0!|wzbeX3A&?u z*-WdyRTs1Gq7plYMuXXaS>fEH-S@l3z86&$o7we{Q|m=Yx^392uEN6qy37X; ziIyWbl{1&MJ2H~*-1}5Sp<%6r%$QD{zFjlOB=*1{qFB!JR|x)vHaM)7e_B|4r4lTV z^Ly;;johK)54-nQe(#UZ9WR}8(EpgdS5oA;(Ucx-F>P?cy6Ja(!M*`CiDsnate+y) zxd=1wOie0Z-1%ob^qB4zv*0kNMx3TBuu)QktaXTMy#X126dIIW8%S_#!RVJ(VE-@p@&a5^D%#6P+-xg+Kls3|_S zDm$3YWu>hSg3#_ku@jR7AuDqq;^oJFPu5mkmN5z+$^P$hTE1u(&icn!=Rj@F$c!)3 z@&y1K?!=OGNyrClT9v=8V>t-p&xOI|bvD zN*Y@C-7rMR!Rx3*=n_WsdMMpSe9-}=>()dla~)$wc+p`%WAx}yM>dLz;G+%1G#K74 z1qV*~kS}b+KRVQ!5GIXDTHq?XfM)_Nu=ZWLRS2tLf?}` z4ftE!V>r=AViB{(l;LwuZR-V$+-{0nxND~;IpVtQPLYA|Cx=ftbz~tDXZV5<3oYf# zAJJ?Ks}kqY489WjrQbH~$3xaP;T9 zZ>Er~KT<22(=iF#}eMnApjTW-CMo&un(WZ z)Gs;T;7dm%c13Zo1(#CN^d3=P|m#-$TE@DE?rc?x=5wlr0VnsXT0($o7rhWJbzbBZN z1I#GL z|K$BS6m$HofSASSV3uQT*5K1|c%gAzFERUlc;5}D{eE3HeY?yuBt`5S>Fu3c|f4z1j8wzbVUK&I6ONLG=4fzkT zFd<_w{*P{32f>lNHO`GaHZ(t2?V80J#9473A@sOUm}S8-#==5~aqv*mls&V;9ZwHf zgOHdr92>Z;_Vf$<-2u%FZV&R+0NxGec{uxSjay+Gc#TiP|Ec=C+0{XFF5gkALVG;3 z7%*pfL3iukt3qlEV118uEhcgt4zh?R{xdf+S*wM_V!Yd);<}Clcmbx@V=bkf+l+Yd z0E9?6b7F|c`l2mN`)b*@7XFiMO9!Qgb|an9%_I2Ta{3_qC(ks*ZQ$OL`k?xU!#u(} zZE(*2RaN=umm4I`l3!1_rNdeJj;fjYkHW=ed6=qMe2!K-A-!#jgl3xeJaYhXDAH;d zGMA|d9-v^E+>^@%#oUvT$?KaPln10LkhdQj037G>%&Pa0_K@4L#`l7^U!3iiQM;C! zwdZUv+7GWMh#bDoNRMszF!#sHgGJ_PTnCbO8oll z;ua7)jv^pI;u2Ufj%jr8&Eyjxyf)+0jyT-jo`D z(1RDHj#XhxhBm@L!J}5M!yxah*J1K)sEy02lqhru46?9VbJ@YR9`zR%pt zU2i0Q*)400+yX565*q|+Zjdi7VeSFW-N9kuiZQ>}2K(N;SNfne&&Xet5s-rtNw(zJ z+Uk(WDafcMPFLX?#$_a;xDR;LpCmds_f;pL=CVAUaBI{v?6^waT~mpE(ulD%&8GMN zxlAQ$;htgnXbbY5G5O|N60IZC@tFt-cgOhX19(jU!OmDyM1sQ9-7#sUccMqz$$!(v zLtYw}GMsMxiw9~>m_>j)xCi5mObCm$161|aAV}d%cOIR!oAHdH1+hJNZUe&ucQuIl zjK?Nf<>nJHKC19cd94SX!HD3c<$dLZKSV$_?4TXc8n}g9vwZ&n%HkfunATpgKKK;b zIOwo>!iMXI;y(PR$CHhc;I+#_jr$Ta&t)^FN--d?b8f6)eVBr;a1;Z8;6`s z=FS|xGxg=eYfQdxS6ae9xp}u3Rdso zc(eRF>`Z{R*(BmMUi#X$IW7GJ2LN)Z9L_0vWcwEMeKW~G1)`UxI8=6DAElKs z-<{^N;*Et5-&Qv<<>;+LUpS{o*7-&>*1uxm(TfG*{BOuQk0e#@1fd$V%!i{IJkDEW z)3earyA&wJy}Vu~e*16Fl6*_(QIA!5y)h%wvKUTsP!b>epI|V3 zRuD$W-BPk4g~4j=q0$W^`B$v(h0?FPEB_fDp}~5V?@V~#iYoOCNAiUt&tY$%#)nCJ zk6U0Z;^iy675JVfhU#wk;aRw+J^c0t`-NhYmFk)5KX9)iDH^pe^Y)3pfKuwRFv1US zB95vrN~z6x!e{PXMb+vM884d8i1S6-7Dd3_r=`nVk72#k-mGekQ}^-|l{txT|JGe~ zpCNB|2zcPl!aEm&z!Sa8`zCfS?7Y9zNcBfzSazie|IKdMH!*NwXZ@WOy7vJs#Wy>rZ~N@hs!0LIVZ_bGud)qzsb2^s z@txammR{q&ub6O;`PVH{=UJvZrD>6XuH5<&ZD~n!6QZ|wV8hNQ>193;sfFVf(^$%R zS)zr0bdn?$`N-!l9~L{$+hI?7^K1EBQs|!~59nk?Rqi7vm6H4lE^&);|9@DU3{-=i znL;gtwfB;|kAu`f&BU;49B?jF+A<%qH~rHO%pT3dKKlV5xzV71&RDSife4215~u&W za1z~8!)jWS0IiU4=qH0~G(d+U4=7EKCB({0@NuIpv0_U9ULr!py^EVGnoG~%u zMwafmojv9f8Bv&aSmLG*q-4oU4 zrl`*<^t~9iJ&xYjJdXB0&%TE1$G^$}?EI(c>hIA9#nptm5YYNrynvgm=U&fequBU-N{& zizDqLXXkN#7bDzf0FGB7V*C^OxMc~Nq`T|c5c|6Lh_L25uN>gz14uV$n}}(%RT>KTa-&IV7V~A9jFVXhtDQk>RajedZq|T zm3wg*(p;$j4WC;|ALMlj7|O%4u_0Ds*xu*>6X{Rv)Ol&uE&*U;Rtki3`Un|VA=Gsh zm^e5OypBQ`3WPKIfPc{{!HHuy|7Q@tXP}le4=IVpPJUa!A+9DJF@&u0Uz+E90sXK- znCp%(aqu2w9a}IINN0Qz{bE9xn~vCV!5(BiTkj~4&i{KW?`*?}2&tRT1F_wGYtt%= zu@`LbP=UB-{Ws3mVqTgZlzN3{?(ybwIu9`Z#PMl`2CM%AF~P3egKLh}=!C-#D!o$p zgz9=~j(>~pCZfJxHkL3)_Gpl?9{QFE5#j&TQVW*jZu%eK`({Fv90SYGrhgY|VRGh8 z{{m>kHWOmye)E%L>RWb%3h0$|!;&LK-~14mE|*yOcj%M5x=zoiXv+MbibLgMOxJ&c zBDxWPZ+OHZWumeshfXJ#DylfL>sWY=w-Ye?kgDC-TvK|4nA&ANPVNFJkcf4x}IGJ=Do;J=lk#$1w)^idKjWKo;Sc;N+n zc)j`buZsr$JBxenR_8)Aw1uQnt>tUFtr{ScZL!qS-mr1bwx*z}a(6v{?3 zu>bo15G>S$DV0Jyp4U_jCB0CUp{`H*OhwOc`bFAXYXw8guJq|Se|-CZ2!2&#DN5|amfqffn0A~uKo zd$$lM@-HJ%b!JcTARj@uFOHF3tW(US%N{YcgjeoHH6Jd}~z ztZB!PaSYEkITy|SaScxcEb#|B*0yLRyDIbT8JMZ=^!-$O0P7t@DE7g8z$=1xMcj{h zpc?s?WY85JwYq6sX)UgG2(5N8vZtP70Pdv610@w>GUE=h`Rn9F>Gz806nwi%wUwKJ z;8Uak{;ns|STys2R^&9?uiiYsxD`)=t_!U8a<@v{BZ;57%*Gx%qeomOv4E>M%v@jDASu6UYd^K*_nL;(; z{{oJBKffmZlKzNM#FaFu{LA37?(|z}Ipq+RGQ%fKzi{y-HZixc zI-aVjXN_2zv1^8?<-+-$+9+L?cT2&tzb@%ldRt{F!AT>~pXe!bg^NpOFACesr9)a^ zX|Uqz+m|_Q^P#bw%poRzrSrjd(igwT5)os?`)Kt|=i9H(AVZ-@%KqD4wswao4WLzZ z5P=eBiZo|R-HJqPDIpmgaBQ1jHJy{(`VCXFGZ!>`831Tay>3diNBW%@Wt{Qg9rh4N#k2t3F_B zs}Hbn3{-#4c_*m&jht>E8rMvkKV3ypBPkKzVjzmste2RBN?N*SAcBZkMUl2=AcQF0 z0d7xmeVJH~6Y$IsFYkYR>BHFG7`*nxSnY@IS%abXb;LMB-qaJI(~)V9erx6A7Noz6Pq(c;mcRUoCX$iBTLU z_8O#-wcn?1SGnJC_HTl_8P_N7e>xiRZ}y>S1t(N%M*hYqS?ZWCmE1tYOQB~X_D(MO z7CMPT!;{y8m^9yUTPk@%J8dWaij?Sf**-&>U%dHVxYp+Rk1sgx&@s?Mi3i@$7J4aMSrB~w|0)vQ}# zR?BrrKM%lke;6MSe(xjk4!dHZeJ=XoZsB=U+ah~dr(JaQNN{awb!_!vVeG;a(D{8T zT47+6Aad78tcmvF_m-hDs8=fzP6K?S+3#LoO{=Gh8!9@Z7Q)Z{@jH9R-8*!`eA;lq zu57zBf3HVpnoT$cfZm&$LLC;r^J=_ZlSfP=4Qka{1(T?a{0A_?PJ54W>I3nGD~Tk-g)b zh>UR;qsMV$DN<}St{-JosppG`KQ<+5E-rODW6el|bz=FVSt(C?V=kS+Y6@RBCuKif zmlCdp0A`=IvB_p)ti_h<#@FV}<(^{SXZfbZ(ObY+ds?<_xL#@#p8%I5aabtL<`J}} zTU_6buL9NkB%#%9V8v~~zWgaZIdETW}5Hho$4()Al&)*m$O+@q>uv#R+c>F@`quC zk>~f1To35a``|r&-F0xN2x}LpqW$zyVQy{mG*{mn$=|V@0Hjh}?!_b(yr=2G6PJ97 z|IX{;bkOaDe__TrKifN&Nnqkscz z1q*n=elq6ptUJ=PwUJ>NK<`*jfBx_l;8&kCwuX(uvv}@4zmU4PFg9QBe6rZMvrO)G zEa!Ht(_FJ^_gJgnG{9n0btGbMp%0*g)SKGXnyyxv@+{KaEYM)Mb%I)68e3i%TVBjp z4Igt+EzWLfCfXx3m8!PgIc6vSfNQ2XO}d;bgyS@Kz;nyq!c2t1sl$4#AZ=Z<3XAOy z<}%y()|}UP+YYFD#Blr-x&!JhnA6TCw4aUO1!}daw2W4_=#Pv>F7TgkyUvagpaDP# zwc6m+WJ5-4iUpw6bu-n;O*bdU{A+wAJ|^~d2DO5v5OuBnMU4IJszr0F{*G^*DFFY| zR#HbaJB(qetDS;-r`Mb|4Qf2P3|*{*8>vf~N&|qg`AnsGx!SuY8$XdurN#j|{<{zT z_PX0iWQMjI#g!Ms#E(vh?OC0Ky0?oYZ4F_ScXh z?0KYx)aeZ1nmPXW;7FS}U~Q8$^R5qZqDhR)4m*bQb^z(_b1J*&YDLy!g`3S>a4j%sEzxA1 zoB>&Ss+7Hp!k4UWq1RxHnu#*>4 zQBaB6exz)Dfr=Q{5J(zBV~;t$=!={m8=2oLd!sF|p z6$9X3DQ&5iMJn&Yj)I$KqW#GI;<}`*Is98^*49FwxwN6yQV^u0HQiM}Fl%E0aht8H`Vq=qUq(M$ z!#ttlwU}R=?4?s#eC4%hh6&=f&R!L`(kN~eXgwL%&0amcY>=>b-8IPs&;OVse@%1T z_dQ#4=8imDU!5CrueJP}D=)*!8-Z5BqwXu~keSV$>#ClT)P1mOoPx>11=T6)+eR%) zA>F8^k4moB)5_(-FX0E&y@ugT5WQMKg;TE7(Wv^B)kz_Z%a(eGcII^|usxV$bgIr4 z;1TBt7?BJ?&EN{2@tMWcc)tA|PV+Tp|3 zw#c4TE{1p%R-zdM=?meDCWuf4Ph2U)w7Si}_PL>Y1A(WdGmLlsEDZek@cY4m?7Z#X zJ75oK5fn^T?EP#!7sc(K&fc#gdhJ^EGgu*Wp$@!9n&mdzSXG*>e{yVTAtOk-c(sxb z#q@RGcdzy1J#w#o<~g#jZCkvW%8!Fgd@5&UyB8(C(}jX+_%DQXl?3HfxK-~{sd%r; zc4P}FH696t{Xrtqk0}O(`>ufogpbYf#Y9$!9u-99i2MZ9eJ*3qradJL<`X9_9d`Au zL%$7(Dh}`F$mK2{%O~53gkx4ph40GLOVtUPEMDXQR;LeCpV>LLA=55E{gGzUky)2o z?iCM%$wOwHOjCTIRpSo8;Wu%X9Ssn&=^{vFFSA{4S$^JXrnw#CSkGR;)AzcSDFsni zF_^iyG37;Kdq8(br&RC3KHfBd2QloR?>WJ-vSFycXy36(+n(zvrpTV!ErP1K8(6k# zvP-Jn6587fb!bRCk*-}C7-D8xHc26cI2CH!aSg`+z!OZo85`2Vw(Q+8fX0bqo{Sag z+9gZP6KvO;0l${;@DpTKshyg23Rx@nq&(?Wm)Q*))BlIIw*ZRk>E48skYEWA+&#Fv zLvWYDo!}PSJ-E9&48h$Uf(LhZw}HV1mv7$RyYKFQt9G~c`>MXGr_X)*^u1j*(=|P( zPv1U={f|~f$g+5D|BW=gitBKa9;>Owq+3uW`=~mvZ)(&c?QG+SvmUD+c4wDtlXc;= z+cYMNe3z{2X~KG&Ni$=c7xsFmtl4S8a@$dirkQo2fKhspY|(LoUK^0M)tgI}D52e$ zr@iEq^N6DtQHqfj z4ODQx#LN4!>p-(tU`3SPpRHhBH>9&hRQ?g9yGX)xmmyr%A=G+aj2EAu6@fI=oW{<{ ze|DJ_S#MC{VwjWr%rV=WBc#mApei?3B&3YNfFb@_d|E`lLCkXDS$}dB(jptX3Te`@ z10S7bA8ER6a@gT7w72c1m_RUYMv{N4->g= zy5B83kMCdAbhi0pyDK+nC)vGxKA?%WsIw`wZE-gXRFrZT5^() zn-whoWY3H?tDpYKnK3R=pKig4K5mx3OwXPfY*s%-0O6WY8*CZD(ZDrsXE}(f?ZLs1 zs`Xc9@YD;uWLHYAR5dNHtpL(T5-t6pM;e62g>1r;40K?}8KO1TH2s1!IQ8QTQsJAp z$Il%;Xau9Vqlk;|H$Knr7K0>#4%<~0{8d9A*M2n`S~Vb_){e8a_hnBLfd&LYC~hg) zUr$C9`lY#XiTgt@481=VZ>eU5#O^qIe=*|O#e1}_sB3${t^h+ocU@|qtZ8+S`KbPYwL2lycCRS`F?2)=?Pk|dKiId> zJ-`!*S6&ZjelV7IB@g1GL;ixIdV{P&R{}z$Z4Vf!Itmqaz{%*-!?ej+4yfF&nhWQK zA@7ALjlW0rjbho3pKD|Wm-30|l`+!Gl)BFZ_5yD%xk>pm1yPH)3nqlZBm3rVC|c;( z(sKfEEnHt27ye`v>hzKyt2eYS9($X&)YtLPsZqv>eNxWDpraWWp*2y8rnj?rxoRL4Iemd=*bSdxWoJWakrO#gFljM za%a5W{kmeWx_4)fp#`&f+jY&K&jI^(TlR_QF^q&@%W<>wZR)NQ^N0`gu_ z{zKB7>#vg@VTWsfoNT3V?MB=^rYc5=u@5QR=;p-Tc8S&^pX`Oqb{xif(cRJf2Knwk zTh-#oDuqIAdl*N}5dMXb;(?%lqq*Shs2>?5hV2^Ky3?=gU{uA;qLG!BxrT9)z+f?8 z)*$SX5H%fBdGv>~L^C0qx@$4|>%oehV(~ygLuYQ&;_R*GilAaH@rHt5-=&ByC|%ZG zD=qUi|9ToH@bm&*H#XCr4bP1FG2ofY5T|(!$xq(%lOMfDl@bJD&V}%EdL8^ zyw1*U%o_67+q0`OQJ!pVmqQCooRw7lF=k4{FeAD*^rC-WQc*g*gO&6tsJ9o#nH(Cr zzP$AI{z6PVF%)`z2^}N3A)!M;_aL`4-&nKTMZ& zYXLf!-p(dB9~MF!)Sa_13C+d9jllYfBYHaC(TIsUU_Ee$NeYaNUUBlVoVTY;p{5Ld zgy_rYNYOUwGakw=Du2Z07R%TlI~Md^_ctgWgXQp~1uZeSKk9#71H`!u38h4$?UC%|0}jghSKYli@7+ zf&gr_ZzlzU;jm?H>1Ey?NzxTa^=PLS@sMeRaHJUg$Zn*)7M_!A0z$$hfS;*-)C2=oJJMLNay>Yc_xp=9Q-)+i3279=%s6ygP6A2UtBn!HXM*hwX`4FKF zMiTE1#9r6v-UGe~)T7t;^m#w*@=W*$|* zH!qH^pQZdQDc(7wVT?w(%P8mYVmKsOKz>#PjkD!#d;8q32_tBJxMuw?jMX`r6*h~h z9pjwkfSq&SmW9!0^Z?Z(f`(fA|NKTVLi2@?hfsf5Q|QnwYY#7syyu1;G9roTyK8Xy z)D?>`VfUxMrlO3VepDBuYFIZ4!BEVM43rt=lUQrVdMiKJHN3=?zG}~R{wJGxV{E+z z?rukLEtV!N0`7tYI=XU0)rP*Tv0H#=*jPh}xpL2cPqE?5&GQFMkHt0JBqzVcwWYFry=KBf142)4YKhXRJgzp&8jpgAj&oC{Si`UbCQp$UWi1FS31GUn- zPl$Qn-(yh!`taYB!h3w0dwgkV7KIn}d$^j}XKl7S7c?C9SH|4%|Y7Ohe;e4zjsZ3T5A2-9&E zAnAN9Ak>-mw=sZ-)Dvxk;<_I5^T0{RvD931uei9_%wL8RJnsASgS}sQw2`k!B{-QS=$mG^ceI z5?JGZfw)@i}RE>YAnuu_+k`hHj85$z%{ZxbtsX7gYD&nW~XPNZp5kyY48fgh)+5&Sm zq~HkKL(=|IcvEUgvXPM+ElhD?aexv4Llxswx)9y9xf<4|WN}iLAakK##(I1c4)blK(qs9M~yhiu$ML zIB=p_3~@MEqB2?{poqXJ%NbWeNVMxa8`~?v3M35I_1(w%VIH@c7(q~`G35^;><+e?z zv!d|G)J6M`4Ln{`W~vbfRTU)!P|K-|AYv6cVWoMss!AbN@>a zk(xHBD!t?TYMhYmdk2fcDMt+L7?Dvmg{uj|DxvdbEknb7bU~qTLQ(@v zaUYr%-Q-#|LV^PgLNrrW0~Bkv%|BcY0Pfs6KA~%yTtBoGR$~?-KNZhJpDt7`Nv#Mb z*-KNJF8YDg!uvW5gOr_7W$*v5$~R(6gIh4hCh7FqcA{yj_+hdhkxwV6eOhtkmEzHR z`3|UF*3222Jq?&XTdx*Z3@)5LH7s2an!mQLF}HXzsm!f_D5fHP=G$L@cml>tM;N~Z zLL8g)2fty3dwdm>+$Rs1tWC6X@jf9 zlfwrLC4e#Vv=99=7oB3F?t<~x3s+OrbX7o=Ttq*k)m;7uhE}KA;$nACZzD^$=3-*V z4fg)Dd51$b7ZLqS)2^f@pD^d!FVM@t)wRi$p`qqOEKuwr(fP`H+hAn#i^`~mBr)A4 zDfwNvCxsxIZ>A=Wsp)YnP7fGzQ{>4WuUWRBi}gw(t6|Z(8s^9fxzCZyJ}Q+)muO;{ zhVDXE*&*wUyzKp2Owp1VJ8dj6Y@vMogrT)^^f zXiM`;zXMLt?&W+<8R&yIlEDxc^LwrzWR!-iz7e_G|LNZ?B-zw$+jcF`%YpcOD5<9I zIf=RY+4)P)r|s4&gAkF2Y7zfb0}Hj4`(;5v&Pkbu%i8LTTA%Rj^-MH9*Z!(F1x(mq zhK2{Vb#@oz`S*Ipm<4&)L4a}#R<7Sp#Q5s}WZ}BQP6n$DA6|aI`az1dE#487dWrbY z3Q@MN!{lFUjeSjjes$n433fxZG>uv={#=<~Z$-4d0jhRGfe!Qvy`}dS7IHpomkTwt zE<#1TToZG4KAbs8m%pQ^O!-S&tH%3g(_+mpJ5HH?yvGVSqiHIB1zq#qM^66hUs5v$ z)6leRYeV9v1YDCLA8##;o}t>~yPIBrZuroU+w-adEs zx#C<$5aKm$EJ``8B64&xu`B-obOAANXcwHEyy^6Y=uO=1>{E7%vL!6nr?P~vt}bq< zHZL4=tC8%ZHcu=WG&puALdr%!enGAqJYBQNcI!3hJGlhLeG)M4Hn;6NYk_eK=uB^S zKsg`qX(3i&#{8!z(X<$YJ{-3H*p+D-FN*m}FaKqoi9?)I-t~_OZv?fGi|=uLWAGi& zZ3meyWS%=~2SBagb!(8;0Z3qg6V@&6CX-JNRt&%Qs`SFz^GaHpq1vMz#I7|5O=dzLZ*?Nm+x?{b;285kD8<-o(<5zV{4gCp6 z)DLx9uTCm6zb#MlEKiaw ztr9G)!l2NMo+{!Dn}2U}@~i1aIzLXZ^~Nj9roj&|ihTt7V5658{F&X}|26t}GwuIY z=-U)%tRBs$N!XMV6r4#53h6)3H+-GVWa(U1pC9sVqn0aVDV|9}VmB3a69i0qpB)e0f;?Oj15b{DSl{iH=hHpQ(Ty( z+oqY^R5@|V@#-s$_%!{#s`Kop^raik+vesB13nhg!=0aEszC7yVeZ^%>V6+n-F7Ek z@kokZm9Kh}E{RT4if@6t(`7ZF%`>Q8F}X_xbhx~`r1Y%w5g&-+vC}t^A|@JD6YC|3 zXML%$$%xn(K0W>8wmXAAQ=iUlpTQjLu5AlMSk10<JXhbl$>nZmKDGdh+Fp2`G z{|5yq04Nes0DdR{FBE_s3eC$)B;HArieh<`k?0Nuoz}B8Wp$8{a&u<1PXmvKzg{H2 zX~UpCI)t%2GKQf%R)K{rH9d5ag7J2aVwxg+RHmE7P1;Dzy%4(7A8y^3(f=}y8%{Gl z1VPt1-lb0G8D=Y(O$aPd8C#&3j^E%`7An>mpPrufTu}yf&#A~yZgP0AUE0_goIH#Y zcAs)*gw6*ivpeGZbhPgYjTXq*Q2qZi5sa6WQrnLb{ArT9+@*1b5 zEk%nVux;(*Wp`)}r?O}J6s4&&TS&W7FrcgZU@zYb+H*j!E%v z*-D1b*?{iu)9Y2Eg?${$p9M6R6#0QJXM?EMEuuG_eL8kW&D!1Vud}}8koKbcX03(= zoo-C+wfq5223M$rr32jjF@#T~7)nNJ;BeJSTV z6&_C2dbOO7BLDI&W}1V0^g(^T)7v7+qvG31{mtT$vIXF8jBd|WyHbsl^PpBv{*;y+ zgEeBG03q+0sKsLkdrO;?kmJG)N5fWuMaks);vq=|Su4Kf=&ytZ(|nI2k4Cxyqrlx+ z6=s<6iOm7L8n*Rw?c!a9CQQG#+H6zkb`sa90_*uYJ>PK46TTaZkt&|upe7fkx)@wa zhiyKWK4g&B?&j{_f{NdVB$F$N-_CMr^jvR4SHqJ|9R3u(WyMTe~tm{1Ja2|{^Nz!eED2?H~?z#&#)OMkKo?gf%Z8l` zN~bxrSLL#Sr&>Fvr`tL^yUC--O`7V35v$51>-}$>L?y|LmCn|M_p;Z?+V0KwcVSD- zsXkuI|3z>;Dmjba>>oYdzaJDAE%?VXB+9ND+j(;@%u?R_#el?2Ep7jEf5p)F&8(Rx zs*q1&u5azV#wxmENPE;VA+FJs*TP>NacfQhy17K)!_n5>GHI?iH(rMK$5;tbI^?J> z-D%L$LCYtdg8Wi+2UrO)1BK}R*b8HfvvQO938HQq@MY%Jj5elu4aHA-AAFY3bvCb@ zlhtcg1J|J({>mF9FTE+@oRlMFgpHi=)iEqR3YP9as_gBjxK1}Ne0}tW7|mwsWOoP4~7dou3D?#hMHQ9 zotvm7UD-Alr<78(3-E~P;!Sr7Gp(1+DWo(~xbmIPp9MM;imC1R*@`YV0fb{0o&h@jiEof3N&MeKW;&Z;`n!(i} z&-Uq6K6Ee85)krqf9XrKC{GnslgnV;;99YO*Vx3Sh3QxbP}4d5>6|Cisy6zx%-)_R zF4~IaR%@&VX(Id{X>5XXcQCxUyvB`exW!;XBFe z@g$^`J5yiiatZRQBO1IH(uKRc>E?a|j=f!V;P3h|Zx-^so%2h=eR~p98x~!1vq+M@ zU0m7T;0Z9h|1~Mu=9c6&)WS9O;Bb!Q2zGxUNe7jO_N@!7Tyk3{$lp2?g-G4b`uPbE zR23WPNVfSVoxJrSIzE?_FOGbjwsFtNmn%sp0p)(Rq@@6sW}5)E{`=fgepA zYU7&fyxU;p+7RRp0z*u%^Htw7NXQ9wT^Bi;D7>c?$r~$<+K`&kh4+5u=^{Ld+Pn}#VUKNb7 zo-b}by;afUn?m=&>#y-82i+(58@v=UZ<4Ru=MK|7Z#sg&Mie}V->hPXkBIZs+nh#& zqnU%)8{exD#jCFN&|Au6lB4Lj-@Kg+;3cSk;v6gf#u4=p9&pytpL6aCIJ*w_S+4|6 zVggsDfh$`k;%<>)o~;(nK_#yGb!F{(s!z{v`R9CF<P-nWl2pS1OXW*}y zkA>7rm_A4Kf$-`-OHfczX+F@3Cl&n)`1OHys}C6w5lgA|T?9sajPu9ecMpE%=kjuL zBn`#gZ|CMz_4Vc>>jKx=;PhpIOSG7uA6VBBROygZ%fW?&%Yl5#gl@kP&!sS#2oG_K z@Xn>kwAIkv3dzo8K2?94krl3DHyPQYj=Xk^qeE#$j4Ow4m6^(br{_Y-JoPqwtDa0v zLTt)}Ez%*X*deeF*81TkeeU;J-n3a6W+8*ouz9*32`JL#ho2+a6VEi8Ym zT_(*n6)n|?t6N37F8XqW=$S(~CCZ*$v8qdv3L(9{3v}9Q$`yaLdUZgy27~<9t{8 zAc>7op`n$FS8sT)UnsjwwYT2%eyJ{7;A<@q%`1n&-;k>TZzQikyS>ciCvW`C3Ce3i zZ>Fa(@FCo?v+c*)$xqk;J~T=2%k=Tzl$Y+v2;__A`ySqmV7I# zp#Wx-Or(U@_iOzOE}^liO$Nr4jH*XI0^jS<;e}r>c}{Dxo8b?9+WF8Vt^1A9D04s! zh`UNwh0axL18i*xJVQeXYXXH?P!a8Z_BX&8m!jKHu+%k2Oz{qKKKh0z!x zF76m#QlJbF)P@yD&Kt2Y(cQxLm3wrh{yp`y)HmH&vfks^S@b&V)PIJpuD&Dfo_zY7 zIT7kE&?Q1aPL^Tl;P(v zx%lAL_~W|YU+bbO7=TwlJ({RVPlsj2rI+ROnI;k#Oi=(Df)u%^&3^^2w5DZlQ(p$o z9Pc^;9|~)7%p#y7NUw zjU}-Ev-LYa1NQKMQJgMWY8dvOW2;C9_2Q_!QOUC?5n3N64daHAOfnX_s<@iunCfAf zgi)7O1zzO9iHJ+-y|`ZfD@97V^&E#$ben=6m9Gj{34Xu!ylx}f=^WvSLaq3E`8lS} z{7YHEQW0-y)lQA4vddkIrv&7Re_li2RC?Y3>G}ht&U0B7Kt2c0q!z7O(81239u0{o z3Af77Q1vM_^GcqNwaRx(c~m>Qm{4z@dk>~{k-`PHPL8)rI@=;@xznxGg~IsJd9X+v~WxxVp!U2(Osz*XIaTNL6>|pKXzCZ&zU5 zKH7A^1%?K^xyOFY4p7h!&6AxP@S=BTJ=%8p;`zy^gDSv0&{uyk&u?neixmgs%T*hk zXu!69>{j%ae6<@hOWF|xiSkoohj}1jk3zLU4d2q405RzEt;Y-bJ3+he{gLh)d0`P^ zojuTqhbKtUCSt4|Eb&J12^&jN$5NKy@uSA+gN=KOQwwYG`cd{YU*{e0P7Dm$h}|IW z+F;(4^cF$5P_gj&FXcP)x7sO+p7oEkE@7*^;WQ@F?xn zpCEm#z}4ehR%y2>Leq%z-+aTpZS}s|Sks-5>$(P_Jh;Cyo^igy>Ie+Lz8(Y5i)y1)))$8<9@Ura9Rg z#AWU3nbrMu&*BX#z9X2&I8a4w(6{zr{=GWMqhRIRFM-TSlR?9VsLM=pD6{)p%xv_G z2Jo^W`}xE${~Le`X0U|Z8cau>-H)-ovN`#G4~AhA7KtD7>Hx0{P@T>TnG zMl;%=y(^ECXb3BBj`VWIk4!aCpI=4?B zY(MoVP{=sf9`4fU0B%vV+R|0%c4*o!M%}hH-mF{$z*MBA$T=deXJ++YBANBSulF{M zIDxS?<88aHW^*rk87f72u0#7Nd%RDIRrPi;)n9&cWP9t*j*;rKzOqx5xpx-E2=9syUxBdC5UtiRs4l-X8AcPvMl zIpszp2bMjM55iFX{7n=~Rk7};8kk+!I)8D$0dSQ27Ed#g`h7f_WsKS5d=a?jL}1%5 zd3Y-e7F<%n|1E^w{Tls%clWk>uciMi7)QQ=-O6@ETPJt)?7mWbV4QTZS+MY?^Li|K z(N8a!VLjG8mR+Q!>#3UaEbz-{cg$~`|Jo_WM1i4{3L*;fII-(a&u`9aO|(E<+GfvC zXk4oh(R)n5QWkg&UQkxip2S)2*REf(Im8aU64Rm({z3vHE!w$l9`EUBfR zUvaLeX*|{xUvlQtbkTGQ;rJ}JRgWe7RcyJ^9~o`gMmV1&c^wx6IiikJ*i0#F9XsiZ zOnsAZYu*PhZf+*-T!9beXN;lb#UR~9>6{V;1)H1v*meOZI{7GqyEF+`6| zk8bSoB9k1JFgq2{nPudI1f`1=(H?IQJlBh-%1UO-s2i*}XSxe>Y5cK%98T2*|CsNd zQm!dCZNT&SiR4`MrLtIPYS--tlPsSlQ*wdN(&(%&uN>wPJbPW->|Znm^59viGj?TB za^gIb4J^;nZ2h9|OsN3Wt}Lcv)vkbQAkdq`K>pYp>87z|cF{<|U^cr8%k?qi7@E-# z-qp4k;5}*ZwP1Q#m+vt0nsbd+1V%hJ- zsi@Z}Ue@7WryY=Qok$z%G8auA?IpjPS64-)H}t_@ldq6PpXj*Hn06bwgJxgR6rN}Q<^Y1ByLUK}m<=lRBbWzWa-w=24_tv=SoPr3L9jcJb>Oh1$edg<1 zRtzALBkwrgwZfM9$Kh6lkeHU>MWlRD>5B_^l?JQ|0Vbq4&{`!*0aC;TgLzrCR`lPf z%EF~QWaULRn&($rP{1W9_U3}B#0A+Z^Qvo!mR5M$kiv}M1>Zumf-z!Db`=JtDd|Qj z24TzYGE7zNN>yunMPC(srA3Lx@R71{tIy|qU@N+0jnz5MxfZ>%@0o6;dU0!&uDd5h zjc~_a^ZE@Yxht_(C?zn|4|%*{2`HtaNoC08eI+kpya62&xKD3tFu5|C?85N>YmmaS z9|zaCO=Y$WU|i7`eXUOu!AqOLHB7bOl4<%Y^5Jh?oO3TQXaIxqIiV&nfng-BhFTQ& zdpbu_ncr+TAVa@=QMqLC*hN*Wdhyi3C2-^Wv1h@C)BuF?g>Od(qW;%zc9o=F&n|RK zp%eX5&y&maM8FfpqOWm4DANhhFYMZ$faz6DM&<@ znc%)4=JyG_UrM>{88B%q4N*rLjwHl?*`~us1`m*`u+ocL8XniMkI*nwUc;69z=}ZfMjuxyJPSU=F|8GWW=ql4 z_Bi?pWh8zjxREtbr*A2-?kKTN8yewl_BJb#h6d6g!>K$N`lclie4zZS=$`Ze^!aOS z1T`kwxVRH7qjn3|GW~6`{gQ^v8m+CkC*7TE=0Fb`GMsGq>HwiCJwDuG;=2#$z;{b- zVL)UEE8z)dZGF>GuDmMx&Bo`sPu~azKbOt&+|a5BY!ezcI$(5AN@bAjvvw+B{sBmG&hLee0G&HX!aFutnO zDmF>d-+9JRH;+gomfVhN9^pz$Y7yxYXAq(!fZF`8`_Pe(fn~WTp}Lc$hw(-LCi{}& z-4ZS-B$2j(u0MtbMWO=RN|P$p?;v6X5Q*~Xuq;b~=Z8;{NloEgMzN#26!e#0hQ- z`9Pyl#+#%+vg~n+VX&CdSQ;W+qXZS=kI<*7zPg6H<_B4D{ZJ8U@M_>w&WRC}M-5fs zH&p7C?I+y%eZ1+WmBk3bMAnC~d z+rYLI-q&xR93n|d4X10UP3T>J2UGN-Niks##jsNM7)eI-#h8Q=1{1jce#fUToL

  • YNJcs zLHg52yA|Ma<*-(DQKsI?!Lu3mSW$4aGmz_p;~t^>kk8xIZ1>S?jy_p|mbv*ntcWL&x0v&4x_t*hg=-*3E3y9}(uS zGiRsg{c={dnCt07`<-kB|4t-V+t+SRWn{r)c6Sdwd9PPMP6GB7yaS8&sTV;kq4oqd zPI?FSjIG9%vMgfbc+WanQ8DQ9-+~*wq zD#UcJ%KBC6`yj8O^fv*v^$v6cVkx$QG3V5_!I*O%NpRv0N~C`@9ig8lxFuYajgK-t z`JRu3v2nh#*(cH%>lV^#UPYK-s|T!+w?x1@r$X2ZwC5Yhc~k; zj&dFFIvJOEa7m8%m_=DyKQ3wc&NA{fzMm1Sdtn5ZkuP&Bc39_Uj+x&x$SN2pj?cjH z#k}vSbKm|MQ9XI^6ULs$%cj4o7DMR@rMNtrs(qU=_#FJbeIx78%8QLH^(P3-8f9x; z5t1e5^SNSyuWSE2G1|~u2e;cAe!SBx#%se%dXFt6Se0BcU1u7_H@2D)fkbklY<6R5 zUWIt`RX22^Q$HP=zWmN{_ttKy`CvPTj^J*rxVeBU*9;H%fHT+F~)Bfamz0^j9tLBa5aPIJKzM!q;g znU<7sK0+1|(Yx;)KMa_Cps3Tl;LHQNIb?-Z=29HcTw7n~r=v2ljpq!^I^_qlP;F?Z zqIAwZC-|h8wpY~E(zmk?_7eifn;ucUB)@I=xpIryT2{H5v;D0)5Qy4k>4!}-#5pC3 zOikEb$6E8ZESi;WxaFK3=rCI$yZz(|u`Y`43q54U>kN6~?~7u-`|)$#Z1LSXQ>GPV z`gCo^Zh=J6!w!>a71w7&wL#DG<>gv#F#D77&?Vb}t|{2@Mc}D2Z>=B+zqp>kV8~me z?T*N?%fZ3yoJ;++is6p7$}8~rEM0ZiM%Xt((baXg!`=wbp0J9#=6diJT1X>bBZU3Xc_K>1tW^{$>1FI=?GZhU%5L zpEROrykPjvd6zurnD@w#^DsuhrJgX$*vt3JMbIfP!bCRtom*{jM3W}LGpTPA*@oXv z<*WIllW%70>YAw_OJaC?J!28fRGUi_Y8s6h@x){LTbh$R&z1$@bz18k#!1BG&`j~% z1~=uv&lS)elEJtS#2K19%aXd!3fzlR7Pxuf@p%4dbv>I~a3R#5&(RH>Y~@irs%gZi zXGq4G9hk3nAlTQN@AeY)%AH(x>ZvYzO+4dy4B1%Na4cTRtU5rgDaf6EGFmiixzM<- zwKRMrS=gkHF3dL3GsyMyQmh%&~1%8S|coebv5+`x8+VS3?lb*FB;A9A+ce7 z>MZac>li8p9N2I*cR%b|kJOrGr6|W(!(j889$3NV#H3&-NfI3Yu~qcYe`Oaa46xFI zF?$j^rzy6BIbC*HIhPxuY1nnXx$AZi*fD89?J#$tH-8?Dsql#BvCTG|U||!&N%cAG zKYeL$PJDnRQ^b|jL*kJj;?l7*k1$HH|0zM`#lY=J|FkrIW~QW*K&4+j>W60Fkq)s1 z-Cyg}Rq(X#HlCp!&7fC9h}R>seh#7=c#u7*2kNCxG=aw1v0stB8SOcC-d12Yx}T0V z<@VxM@4D?qFKvcG$a}2O`3zk`HUK9RcdL6Jt}2}B)m^{2X>LuJ z0l@=tq@MJ?#}Y~3c)|Bwi(^!8!yRwTo4$6(F#@$t*n{TdvC+tvo67umPZCqrLSwP# zIKtvR(p-ZYiRy!o4YQ3;3LS-?o@15}b&##s8#rUrxyGapxk#R}iDu_I+yW>jpS^JE zZFZ+mStPG?)M6^BUn$OF12h~IT%Evw`{S2E?{b&k`!+1mKcI(?Vf|j_*mW91I)C=D z_#-kqGgfzK7UI$4ZE8NY-q_PRqMwrNE5cx9wvusv5OJR#DGamPa(@b)nBfF)-Zyb# zl2<3E{S;&;?w7RT<1+}dYT-DHIe4Fn!Hbnux$5!KjSm&Q+?NgQ2uR~ z$zY$l7mqLJ(7ZtJ_A`MS3h3mN&n)#}4WYklCAQn}>*7wmV#k7?)l;r_bar!!npPO5 zj@xT-Q=(RJZ{lmV;~1}rmlStSEmbn;iEpvZ-JuL-wZ37r9jn5)5??+7U{n82VD5Z$ z%+ZPQQ5JuOlCx^)O!a0WOPi_>4cCkbc!`}#&PbEea$6gM6_(IaFii)H2 z=ekV-UK|B<|w>A0A?nnWwJz5XEH9e2oZ zcVFjjFu?R`Z+T|}zJ|ZYGI91Go%?Rh)JLw%*ogul+K@B*{NZ_tBlfBGR5+Dw0&zBb zf=^HKFuSVxT46Dj!<@nLU3==fEE9LPGgFi|2eEr7p5&CI% zjG$?5eJgw5;ueP`a&_P73_nzNaDDyoa8nOako;icv83P0H)uTQK+b zGT58+3|l+M`TMs>3|LGW7ZT}+WP?FOCO+mu;YWqfVYU2Qz4y^mN@Qm5OtBMVCChL;^#s*MENE}beRx%3UHQZqe7Pp6}~YKhkG)fNiyyH`A& zcki@fZJ!;UdwNF4|SHjqRM5&nk5eNN94Qwq349{FhM zL44{EEo3cFb?LjXiw7p2`(kzFzW~M~HhHPK?12(L77GIQZPCh2j@JZ8`=F#|xAimT zsatexo$unkbQY<1119=o-=xfR z0B9Xu_kIF+m6>L~Cxx>|=#tP%Fh=NpD-&l7*QG3ztO{eto|(P^=0naYGc>`rJC3K7^16ndjp3n{&77AlkOj&%9XlJKVy_E=TUhvQxd6+! zr!~5PRbgWP-GXAKW}eQGSHJ6Nu{=So?+X9qqvdrHWcEP3GMAI72U%7?CS5Lzudm*~Ni2oPN&{5i+_bFPJh(q&`-fVt&(iovS``yWITWH{w{ z5C)mU%og_Dn1mj$8G6?B-LQuqWAn-hjT%1kAkRj^%nqs02>L7Lp?QE-$UJoEk81K#iBd8%`Z!OXTV&sJ9vBH71B z4d)|+<$OPiJU`xSQdTioHOzFfM8-Pu_d7TUC5RFMGVpYfw10yyf0Zp?zH2>+e1yjj zgKb%nVi$4G;YMM_!T)OX^Lxb0!lUwCCB*dn=|pz@Za%fuu8gUNdpdgJI_Jg{wak7{KAm;>CMv@L%n_**WDTBRffLMh_{Y7s#?YY|zA zp@UC+F|pdgzWNN1=WA19h+-5gSL%xXhT_01k69DLJ^57J zxXGjeYH_So3MEHrt%M4=Iac`5kvi)9EPA+yt2+KYy1yfF)nw&L0FMxUm}50lwJQ@2 zt!Ok;7Z1u2A=#YZ4h|EfBz2XAAUOuD&mPvJE5FaeBHK=eJ*9*s7eY;7mfumZCq)mZ z%I^)tb%^PU$mr8DiDzaGTVJ%lGE_@GFqm4;`DS(yHm;F^C3tN1Ugk6fNr-`zSBA?( z9D=lbQ=hI_5N_gPM-^1X1W9whTl0-p-7~E3B~ll+gJRG;{}NH>7lWh`u4o=GtUR;@ zk&@J6L5x9w}ttN(!73tot7&T|&xGK#{lf2e>_Zo-Di(RL76! zw-!8j+vQgrWu`uVM2K|XQ^+Nuqjpi`7dj?n1$Eesx*ZukRC!}lbW?2(%?~@WUMa+@ z#J$F6Ar4z!p-WA~{)16{4o4$oxPx@B*j776K3?_N#%=$d+;YhS{ zUGR*+dcE)6aADs1&PJaaTiK;miV^7PSgRY=u|@s2QI}D2m~IboPn&76paIDdeUEE& zJPvA@gp3ij!nqk&uR(`DF_gOR3a1Q-2%Rja1Q9@(3{);nlTi^bt&-6gD9xeGmr;?g z$jSDHTHVhu$2hox(=?(Od+6BIs)t0x37Th&^S{mK=OfI`yn0 zC9N6HzZ7M*Jm@=Ha&uFTlp{4=R>xy`(o-K>|768|IQWRmOcnG)L3NRpstoSnqb!L9 zdPBa%mLdv3`NIB!`0p=qQYKA|nI0g?gUQ9Wkz*of$qvaWnByO+7AQEFdrxpLr3%a> zIKOna)Ku|1tl*VHV5i!CXfhLAas_ZHEoSy)I=7l?OTC{3mY8b8_cVMBuq6FBE7HPp zA2@;H`jJm*bm9lq$oo?uUWyB;?FZwxJN2NW9r#G*k(w`25&r%(LBiki>dBW%B);K= zlU0$2!zYsA_>m9Co0Q?xU`PwgSba;zlb9j1ROM6VR!+kcj}VI>6Ch6zb|FiTmn$Qp z!J-Lqzm#&AQzldXpdl+EL-uJ6*}hkIka+wxM7D z(-5I;D|r~WswX=OU1l{z)zaU*gzjQ5&mFXLm$^->JQ)Z0kvt0p(LnFd{d;*MRq*_@mL2^ zsVdVvQ(2N_TdAX><&)VJ9n___8GOI~X#2N$+J?j_whNB+?(_-O?|XCM)uZqWi3!mR zifB=`ZD@Jy(XA@l*cHofw>iRiWZ&?b`tzuo$a9$i7p|9Y$ls~0Qj9gy=bJ=~M5s;hES;y%VVwe0xr#;fJA z>-C*R@lov2mzUa{h$Kr-Jmo)br~zQIXI(#G%$rnCN)xl=>Js3qwja{4-3?dCzLx+t z&Gn5UHTqASeWtn3sEjj_r1fHN5#_QF<)nH!CQ0vLePNeB2^#qg^PU`Pb-L*?0d#kH zJBE`NG_?4FggcD>Tz5rQhPhwwXhGPw1`QjE9Pu9K195C<%ARwW5} zF}TItX5NLygW?2ij3;RhZN`JRJkNLc6Ml+Y|6F3h&v#Xnf7PkZay1K9H9`R+IGn}7z-o4}jnt5*i}s=@arkpANYVQZZ9Goj>UUcDCO z=*Q3|xfcRvh?(l9!=?2y1Z4JGhjHWA`uI6)pKp>tL=DX8&70;EQ3+=i-#Q<;W!ev1 zX3C%+BJiX^Uu6*TgOuf<3{8ZZv|pA6O$0t47s2udjMZ}eG1g-j1Nodi9P)LZ$ zMYnnp;^a{!+gY`E>ZptC@KTa1TRPgNPb@UjmIQI?*n2rwM0Chl=LBcDoj?3PBwb@% zW#8AIiIXQcak6bUak6dOwr$&!ZQpF$w(C|m*VFI+yx3=X9emDUO`N0U` zFzBEB`H#hZr!JlC9`VWElo>Ox=Qod_axNdwHR+!A$>kZ$fzbZopaPQ1#q*DTM7{qy zu`M4YFf?8HW%dbqay`t@bb<^@y{Hk0|IB!2WsqhV>sM;ga`AsRHG9T;<<`r%Oo_A&iF1+R8&hFH!Z~MnCRNE%D#?|c zilwLdBo(QZs6o@-=6&4BKVlYK(F<;Fm#+N#8|YI0afcoo`109FgtOqwSN;hmQcZ+; z<{rVbV~RGNVA>1A1O0#^0`r`;7r6rsoJHa(qyXoSt8vr0<+;dx@%M59v&};_6D7Za z;_^4S|F)R-;Tq2|^X@55MD>BD^p+`in@S<;xA%!c@$m((4lEg?R0wbHJ_AURp_?!b z8j{V6P8eATkjq8N>_ASKdO*GlP(JxT!i3`g7JZPs`G)J^hjstWzVyRT?!BZGLkTVq zSX1ExO{?_iSo%aDIH(&L!Hr=zqS1-1>?Z6uoHrHo$67mZtsSGunaJXtYhh`$w2DB`Iy+$PMPF$e$+3Tf!EDUd zZu=Xn_@W~v)e(~oW((X}nZXAb)e&ZE*M`nayb?90w{dIzX|2*3unt&!(1g#CVp}7wH!4G9BbfU?f zFv<=vjnfP%2=m7Bqe%quR%mhwk>{ zdXiq~RW1!=ALPNj!(~wJq0a}aj&SEYa$g~rMvEM#VMI3xA2f_m<0%d+V-TUiP#id8 z6p;$1G$>CSN)vT+%^)rAqp5R~LiU7I9AGnuPy;UxEBYc-|MUOPkxB|Vau}^H`mreN zzeF^}|0Dlzr@>boQ2H|bm-;_8ji?z}aX{h!&v2VYl;WWqkp`yHpT0K+^rO&0!~f|4QP27{dOjbfNR~ZswMr96iuyh))M*4NvCsMlkB6aU4E!`-K1w_KYzYc>G_rA+Gr3AY zS)gnH`^c`Nz&ZaUzqG^?&xhjII4O_559a;)3bHFah}6LWJIseUi}>`4k5%-(Yj#?-;9GxmDQhoTOzyTO1Ak1uPJ6I~N9pLGD38c=QoS&$E$MJLv5`VNMSTv<#$ zK?L86`Ho5NIgQ`g-LXh#j?oJHS0{W!KM@-{$GhRKWj1Bd+q2o9yAOx;sn6Wm?yhgI zd%3ocW5GUoIdYxfa6dJ7e4(Zr5P7G^Pu!`VjeUNBqyy92&g72%Qhum9H2x8*-kHu)zNdQV)uFK+y|nzWVAmMN z4I%A`nueifei3nVVA61gfpm{Sff$x4Su|%(2*DHkvzQke&%ELOYXI&NX{1s@se0Fo67_F zVZ`0o2}yTI=|m}8{;Bc4T+8=BE?d!EwgoA<{oNNx@|0-XyH(2ng##)+kj@h`MWXwz z{ov}qt=tVKl`W3Ul_>hK9l-1kl{Knw<}2$RgqHUuWREtSNJaFdzwtKWs($);$#@HT zgDt(~zl6@nypJ9)mh|KvRLEAy_Rlr!NWsn|qUDpDE9uI8!l%fT(F<}rlTDXzt9Bz< zD#$AQ`zU&WZTzIaA(;*!e@4HsM$8iD;z|U2==8wfN_|NbyeH39{Zv7~MwaFMvr(vd`SL`9*1>u~5nHKHtpPq)97WzN(L~#^fT=A*>e%-^u%^>@pkB#=5?1zaz z12kk9XF#k0n>kl83}3+Nztc3zwCMBz_cZB@4n7-ip2m5v-irsEW!oT(45qX|%D~ua zS@m34N%JK=d=mr{!zDe$FH$wFl?x+jzNg1VhG=52r?=!W?}6$LpS^;*GXQonkjG!S z-R?up(P+H`$Psvapn0hlz0uwddZ~Ue{P%5hx#8TkW*fmdLn|$MG&okzK_8zC^XQAP zkzrE7G@QC*5De64)MdYA{IrG>fMfV3><3|2)5Wx8@0R?Xu*ao`LJw09NsoW$=gyBE z4m~gi7!K$(u!(Ob-yMSWe#Tnj+hJ=|qw04H;^D~ki`cIpS>SoUX0Xj;0rejhKZZQe?7+^Jm)3|{ zzpF(p(SxTHK6D^M{6)hRK==#s@7o;lIaIx!_gpnN7V&b~X1&WK@%ho7$G^?*H{ag; z?CxU5heo@21)WQ;k!9O_uRB>D$L09M2%G*aDO@? zCzFoT1Pssd2C%+CSKt-fq; z)8BDer**vRQNE1NF*vAidb!OR^RI9!n_h8Q-{7*7=AKn#wxd;u1>!Z>?1Z?~m*BU- zJmD@)>wA}%K)Mx+!SSpce#<#WhPIih^1{#~UQnG(@fW!ijD_%O7)Iz^AV#8@bIBDd zWZ{NNX`<#O-0|dH_r{m5TxGUv$-ew0vK8D3on~7D7IVIel(pdagQMyAhn?v3t$&9T zb#6CrhpFIJp*X{k zvzq$0T1WrbE65^Z0{WoRC6-lYs;}!%RP$}=Uu;_Q6QY^K9V8A8KQT;+KS(Ulv{>MD!I1HK+GzIT7|0yeDuqfYZI8aSTrLsO)u^h z&@sZc021~l-Nu*Yrvz3Sc5|sCY6rcC?0sPYFp?VrERPmscoH|RRDO8qxZf8 z+@{6IeAkSt(@0HS#<6kLkTHM`r`;Bm{Y~eLJ6P(R+S}9!T$>AR$!)U5sQOiB+dZAR z?nqOpA9)F4vc-6I;89x`0D&9&z)?y5p#5FuG8200qysT)(^V4VR7Hr}?^?h+(_J}5 z%H6xgAMW+)Tk8EEIBNpz`6#ud`gNtNe67Q9ytRr|^YCP2#VT_DddjE=qa7$&Y`X?> z)YipB@XEUba2#HddZ`v{F1>m;iO?a|4%X#^xY6CRIH3&h6bN_jLxGf|JW_RhR(GDo z9v|6k9tq8m7}2#tuayL{>p9#8qcKk@ec63%B+up^SLn4+8R6%Dq+(mPYrEz`OErtb zJY+jv_|!MwW8vI3_96MsV8C*3tZ=xDxekBbp0bqCJ_8Boe@##2Gq<)7&!*hvZ1!MM z&Zp$xWi+G^J-41Fm=XYcW6v7BPYR9#ij;B~v~O`!$j!V@63n+8txh6L))WY3GphTO zp+Q+%72CipD8MBroY%19ceh1mT3J|$Y2zKWX=V2W8*Y}GHmkCfY4d80vja-PUdKyW zj#WpYoH?xqmNDiGoD^DMW!#avu#QfJsmIk=LxzZCCJ*_+eIo1B_3;7cWW5MIeWPw2 zBJuUNoZ%PebF3TMbDf>_CGZ~C%Ke^-r9vRs=9sH!Nn_4U_VPwk+Cip_i(xg?F9#n)Xsv#%45p;cDi|wS%V(9v#ki#Nz4AyI3m83r)$6k8Jkhl z4)3fWu1WQT#>cK!+8LX@;%$m&!kNfcT3XVOd#|?7v(Y=)MNh9af7h*z{wBNb0;b!1 z2?elNhxVFunQ1BS(C5BT?emd&1vZ{G8}=lpH1s^Az}aO*HYfIsC)FA2tQ)0+(9f>c zWPB6MI|!^QE-UFf0voh%$jvlqQoTv>EY=%qf|lM#*D!Dz&6-jw+;oruAo(uhSr>4Q z!R8-XHkwdV^_!4W$v^D;2YTD)t*^}xQY--uRc39w6=xJF3%-5E3I#P1)an@CO&Tr6 ztIIR;=9_=iCDiw^DL0q%l4)JNC-EK>FziqrB9q`MlVRV?l@gzrx#1NUPf%x|KC%$y zsc>3n3B{9pY|6-(0$=Y=c~0oh;)*;tyNF3xM^Bx|fT=E4sTwDhB};y8%5$3)mXmtMD~02m27Ox zbjv9PyOUVy`EKUjgegXMH>%puFby!kG-hO-x5!9E@~U@e4>wwdM=B9#a>q9#&*78 zPWm$}CpG1b`@w#0tf!z@rkz~%Eb*e!w}o$U>h;mQd1e2=!#jj`)K@OiQ1*df>0q7t zz{$IrcimMd*L3=hU>J5J!Ef9Rc5Tx*-S5m{ z*p2A5T{d5--{4L_U8Gn&mtol2yy8G~N zc!ccqm?3|hY|a>3@W|}vm}Y zmv`8aS!x&$j-P^CGO<()YwBkVkfOxS2in=_h!t5Y>X&x@_)yBYEA#5dH=-Ma`?l>)x3XFWo=&`=yhyvN)$C@V=BQw$AsdN<6I1#$VJc5 z5Kxvq-+ZPgdTeZJ!@yne-HFWf`vfG%xRXxNzKc=JRp${6;*s-~T?!-|H|D9;dfP>1 zkUElRm0q~bnmQ`YX{Tiu8qM;h)6%N~!oVt;RP@w1bT%!31N?YFfp(W=1P-c6@tf|$SKv>0aaZ7Z!^>WGJPWMgVu* z@ChTtBM||^-zi7}OFM4c7q>vE#UILKA8bM+ZD?ivUeNHGy;?tUOA2l5HflH9P-fA4 z3*|!^ZrHI!vmf;UJzP1V*H4z684e?v!p&fLK8E z{-g@rBb&6|z`KxNs^}9746)EPI40Un0FC~vitlc{i|`F|| zOypMQnEf!dF%XhsFPpnY`lj9RlCF=Tedc|DkIP-DUA<3=)_m{xj)Tj--4EVf+{vkr z_j(%KbAGfbOc@XX3?@v;Yiy{b{!mujBb@0gIdlsQ=F4<2b$Dso83){M2D>slaro+ zE!@IZYlVu;Be9Q;aWE4b6mhy0Wyi25AleQsUTMCgb=4mfB8Cd__F(_f{=%zbh>MZM_$q#Hm zj-_16tEptwE{U10(DZz?uR+G@N>ICQ@-vKZ%Tm5cOEggYRLGl9x^nLM(Co~)`6GY+ z5I7w`{gaOdyK}cxWtA{uOW(bl!rgVGp`lyR}>)mFsFjjm9V4J;vgSVxK@r4>q&2;EOs^$z8CbE&?%X9uk-y8 z7T?7(!flG1z`jy*{(7Hg-u>FS)j)AevxhmUZ1~AFeb3Bfkn1&8vAixpgv$aW7>(}3Jxj*O}EW6xnf2-#(Hh`P= zya^QZSjOOtz_iRx8(V%&3QUZC^LLubU{fTJPn3Zd0h2fl^T3uS@JmxP+uc(6TO+o< z9~0wt^fWjPw)F*$Rg)~==vAgTUj86)DQX`&+1Op;M{Jp6 z+S!1ip<>3_f}x}WqIr)vr@CUp*@U6HV$9j6wzOi&*}k^1qSx8HwtzZ0CU?ZOJwsa+ zOwy?lw^Fov9#Z=b@UL2B`Js1+F8h3G2gADVyxA5oe$vjovSe&ug?JV(?UaSvDB6X7 zlUFf5TY-Bo>ZOwURcXYqa(FF`wXuYLC5?}JihU)Gv$5J#$d2k($!==Lj>ioBNJwz8 zww}rFhSfSU?1Fbfi^sFXx~0kJM#EI%gm+nm&+`Ra&|-7rv|P3|)Z3tK>d^wPbHcT~ zjzQ5cpLE^6QjvVbr~b*XX5i>q}xcFxO|X08Ov z!JS|q0_7kg8wy^p{xp@k>iVgGGw)GyC~sJ7Nt5LExfR9Pl`2Fz^tM%z?_?-{-6WS% z*Z3$(v8*=Rfknlj@<ud$9`!tAXk%^00$lwi+m4X0Jv47K%WuGQo+9WOg}Gs~W8Q+hX4?s$ ziO;0tY>Px@Zn?2j8@0UA;b+_W7!-qrx%nzI96f#|)Z^+YDTKN?;7!7?JlPgIuGO-} zi=1&G<0Kn0abs@R_N-$y+?%b29|6 zK-jE#F^;v@L0aed$DnOHI4&DyR3R*d6n`i5t7g@XV9>UZv_G%GY z-vRrI4JMfs3M8uT_Egoqlhc390W9UCl5b2yyUjobnxD2fi1gob%0@-fN$YT{S$> ziTHN)ZY#IPYE}vjRj+%;5K0a_xXRwUhv42ffY?z|cm`+~KP7(LiJ1h~PG}#27Z~vw z{pzcuN+Cw7Jy&B@A115C8Sw!9VM`xqD7zr5_n$N(Ajet71yKTjzgmOV4+uq~_r^&? zl&d__|CN&@Xa6hnDR_Yqj|~*Wj~);6Og0)|9cW5;;gH_=`E0SVZqHBF+j?i;GO|5L zJ5&`nZpWfaDDid;ZBLTJBfu6%Rv*KHisv4EGOGD6*()$A?&mMk>qLfU$Y+E$0iW@K zgwN5^^oIi>vK;p~eXN%#RN3oHBYXpmG&-{AQiI#NsGy(>GQ$V?! z>@EJj0#}kuvFfQRR65@w+o5KZ>T@&DdZ@QVk$L95NaYx&Xsd-X!aJPIL@-0nlZMoW*+!)@s_a-(kNb$d zJT_#1nUy2G51%z)VkaYG!awYtjiaBtFWSa?VRFU2@uxY3kF%G}L98{muEr6wEwVB? z^T@ie)1-d`wq?vFl92IywZ#y{5Z|a9^-gYL z|DuC&l~GqOcBu0waeX2qC=KtTD$RDtOEEvjo!lhWzjq^esy6B!ME!t*_e-X9s0}Gi1Di5)+;K$X%*BeI*{k9F%D#>9FI$ z$UV~A2o8Fkn#ihgw9s>{y_i%BU8V@bJ)K)W4m$j*aj!C1k7SgWClt^vKT61R+;d#* zOd)C*SPE}|YXJ(#^WyPGKVTRDJswl&1PNT@(&0+FSX)td|@>JoDF8N_{`U=1b%m>_&*B^p}bAJ!F3YRC}0zyM8xYy6NN>9c>{6NLc8LWNzi|PC8;SO z8sn7_(eG{^*7TGL<#t4o`-*7%1v3v!_^}_8V?`oLAwD33`!rAlo!fN3i+31Ef<9E( zGD-$SOcERM^-qxbpyvFGPr4ll#Nq@aO?>+~wtwI&FiON90EBpkcEE_a21~+yvt5ym zR|iTaNcupM#=c>U9gke+9VD(FAlY5Gj(ieM$0<`xGtr<5MWm@=y-M7E+|u{1qza7P zeB3&aWxGf5O!G|f$mk3l^H%7wSoM%|Y5rxsV-=OuF>#8D=?r*GSl*q_u3;h~PVguW zJteGRlo=AiPWw*w7hC@VK9QEe!zcR<{SJd!3NRMMRCr+d9ORq!rspK zv%}s1dAOF_r#5}f;kr1%cCTxk&y!V6BKpPaAd7mR6E4H|G>9y4DG^50K^nc7PV)=~ z>5QrLVkzcg_4zFGUZ?p+BaQC>@>(z?QklOf3c>J%nj@&N!6^A!r6?A`Q2FX+=uQFh zwLcJhiJyXN8E7tk4h41feW%#(liv-pli(oE!lZ*u4WjPrw9{@S-N3l|QL)D+PdO9; zV^E()W)i_^08k@Ii9nYtALOc&-vBF;UWg={rD_+h!3ts`x)4>3sYK0gWyWDObi7>r!p|baFzvcq_;9~Chg@0C?FD?$fF9@t zbWOz>LD$E%zP|D9LE@o4vYsx#Ko^rM4db`ZVaIjss(Q9Q-#r~kK}VSR>_|PXJ;P5s z+yc1?ZeJ)`2%sa4BipoY|7-BedFLmufr^#P^E!5R2F00Job<>E5g^wm)F+hrp5_w< z5NdnUb^f>s^$liy*HNLrNmmR@6X(7|Pyi+mR}S5}0+Quh#`mg5>9$@aBWetj4<5U0 z_0xp11r?L>T4h+rTnKAs<#mf7$R6oa*x<4$6?&R?_ZerY=w`Bc49&<|Amhn)FcEvWd8T!T+6Sf_X;nm%OOg2iTf~a_y78LzIx(BD!1?{gz)`IKar<<$u2s`z zNljQ_v(Q&fM_{!nmld}GmkBo=Hb2a~`1*j@YZpQBe6#p0kWtFi`j`){(z<%H7_OP} z3liywf53R1CRq7;O-#StBJ)+M)kKqFvv%_h4Z~UzO(oHLpwUY6nWk1l8(P}c`jG;H zsP2c%9%Uunvi{4Op?wUThB$d?5eK2X#EYU@SGA#FMAA#D9zwg!9^YIMyl_eq?SX`Q zu7JPN6D67?X|6!J(nq>Hr7{ew!exmZJ?jr?g}ag&q9z}(`%Zpv;ZR-`hQFeJl4w2& z_0mu3$isX*nX1XfW2PZm4v>vTKPhM4gTMEKSO`gi`QZleKvMc0ES(|p=EK-0K*k;& zPsAmpmAgTE&-hwN?Ed|C)G)EjBDHPe%Xi72vMbaBil8&u3&U=w9aIjIXkXaR)UIp) znDTZIfZ5SB><95&57K{Aqeg#Cp#HIdMY9wo zfe|P~gn98qFp5N=DTaMF#|N8~B%b;4H$D}KvN%o@|Ay$W|K{?Y+qCcJ-dy#gx23mb z(|P54N2d4V=3|yOXzMr&XL)3LDP<*hUB0tn=kF+s7LJ68%VO?y(dMA?v@+)Mh6r?o zWiGdp*8yEQy-iq2z)%8b-5S1bq+wHi;ZQc+ESH6xqWEt>jMISlTj$Ub=}{pZX+Gk1 zbCU4>YmkP53~R6hf1|>J-;73l_ecf8ptu@4#gC74S+$GYPHX$o~BXX#ZYC0S@S)(Ujk%j zJ)B0l1t*q#5xaQY$4CkdN1n8B+Y09>5mQeOdr3;(>QXN~)0n^<%q%&DK1FFxw;-Vb z2Tr;SD@4i;Tc{uW9?2T!EzU=yC4Bx*YZ^9n?uGbWOHIZ_C4|-r{BbG76V2ww;Dv$q(F5!`V;6Zd#vQuwZD5_VhT$z;K_Bm(M7mpabX5f-)ds&Uy5cbQsAaJh z&i?Wk_tM`snW55~-&KJu!)mW)yfl@Ws*^#jht4+Lc`+FxN^UG!G3VhoH+{^zvvG>= z6g-&tnk%?DYAe`Nw4E3(f>WFmmN3V(hsei@yU{oIc_=x9O%!G@9dVd-JaNv*bs{dU zQ;?o=)(M;e&jsy+)58`!+HH%JHC$(sm7hj|=O(qTEB%i67npP>ZaEK>+X3MHgS~%t zAvdn|JX%>ec(g*Wr}pz1A;dycp@&0MciZU8`RjFi!|P*)9lX@DVlJ46*2?f*qe9Q^ zqWG@0a}{L++kj^@Tcd_&c~j0z02K%CsKt?|jKA%*{ajwLUO%&R43I7(@Zm4Rml$ui zLXL4>Gu~$liPYyO7-V6S<6`=dqQri6=;3y zW2MvmeA>C4&TjW{vvN06a=WvAKz{%eZM~KETu8X@Z5VaHcZ+z|iJ9ct&HeYK=?+jG z=thrGIQ81Tf?pNcwc6?QN4J%Izf1M)Bl1zJ&RcZ@Kk_xgR9)=lpn9X=4Q>jyrh~dh zYd5-%S7iou3x(!~svT{_DP&|nH%E0KTwe#WY#mn*SC%81Zz~-V0c!o2>z~V03&p~2TVBGmqei-ud%U?knXioBg5~A?l zhWLLmZ~NFzdj*LtkZk!3oR*^=)HB@4J`rNuWUzVet$-gS`j7*5lWj<)6!u5X7G48Dj&60?eo z6E%rY6N$MYjXdzHWJWFtV@E8BVgE6TUH%nwSs)!hfALsQ6<=I1HUb&bP>>yuvA~cq zTu?rOzEKgb6&k(vm;0+jDzSW1DdAdIDdSqjiBqGjydq26i6Bc;DQSj^6De2JyQUK_ z7p!yC@HReP|8g95cF*n4GyF-Ihln*H?}B;3(b;soTOm)oE#Dx8LPtS!d0G}4Y(K4~ zjhRw23KlZ#!8iGwATnXhV21)pA&{B7Smn^v_d3>yr-9H{Oocr1Q_2^;uQpu^4fpo*%DkG>^Cc)#Gp3f-1*eo!9)PQP zn}}lQhgyJ~ZYBNv*E;_G;f2h*LZ|FH3!qRlXIXr`Z23U!5onWajZiAjUqwE)^iOw2 z^Pc*}xofk~qutZP{lzVTw=9Qcnqit^8fzLtHpV83b*|R4*xkhA=me&~okg|>m8grt zV}#d08Zdla$bRGck&}$Jp7>eg1??%t_cP7#0pV*m(hD|E{=1Na=4u9N1w6sF1@kx3_uNlp zFD!tNsXVFADqxg;jeZT&f4L%U3%2{&XWPyk9>^o$x>?d{uH+x7un!*y2MgIMeC558 zx~&f+1M3ASyYMP(ut;xV8jvl$fwqgB$F8dbW&f!>vV+2V)l=4PYD zBiG|lOmncaaYdZ9*zwW!?)K%@WpxbewDIHjRYYf-4+~fC3+)f^tNn%MxPOZCVqaV8 zOGED1V^j0=w!xM+{9J15&| z4Toi2DRgzDc)QMfn!9@tSeLT}X695*Vo1v_29S&{10Psu`KM&W=0n@)EdVhX3w?ED zo!5Ml%!0R7v41X(&QR}hV;DE5a%M{Gy-t|JGXrN$PBQQXV!^N~Y6s#Sa2u4a`49Oc z%{Y**b%RPY?|&Xn*#WoB9@Tiys%J3cQ>$JS&UD)V2?nc0HAQZ^dA2iAFD4O(%Fl-{ zY_ySE9SM8?qMTaJJMMX}GGBb&^K`^`kDhdk2nH#%Sq#NCj9*~p?9NQ@9gQLzFo*++ zN6>RNnI4_G(qFbE3<09R!+-1<^)_ujfvvkQxUqZq=XGu#ZXTX5?ob|3gsCNwN8*q0 z$6gOnpr|6Y*+j`zjo(a5`}b1A>nGAV>Q_v$k&bghDdG)1iWllTln+U5%kC-TZ~O3- zHR=9MwzvY z#(YrKvm+q-dtMQF1U9Ph$Klwl=weit;%*H{6%OH%YI|0IZFSEh^hZc>DHB?+(Yf32 z=`K2k#V%roe(%4`2|BC~#}0aI_8naf;Llg!FIcw4wo*NqKcM>ZCn5 zuiBzsM z*`+xSJbb#i8V8sI(sS+roJqXnWjzp$zq>wZs$wy{P$>edlp27iG9#D|v~vkwlHP}a zWI)rE0&Qlp zdS=MGDr2WhHi_diXlqaZ_?TxgpXo3vZa*KJGn%J13Pk$%WPOX|aD7wcuGvZZB4L~O zT6x^czsbMBANHnq9}9|okiB1cb$plkbo!*}9>2alws3c%y=i=oe24qnvCuNNzC(XU zzufns{Nel&{Xq*z{(#l)x3M_kmreT=AeYKT>GNHj3H`KXs)ilBsgxIYvMy2)wL# za(%08Gly%Lh3o4)f8oIPynDI}CWLF@!fss7(d)!v6zMnIG4ul-LbLii$vLM2b?rFG zxWpst`s4BV#3L66|9=MJa1flCgNw7m%lpDb!p5$Ni3WN=AU)YJtGQwFKWAYa?%5Q& z(gM`WCvG!#d1p)~zY{r3rS0$-U(T@(fn`Oy1F=-$N1#Sn_1~^L-2^%m?W+J8@ytsn z>sJRO#Z!+vw!>exUzj2E?w3MIQjaJ$-PAc&Wx)3(dNNJy*;?-0X~_#=aqXY{+!583 zPI$yMsO?wN$MRcx1yOVqi4+xZ*skQO4tr;=UR}|PlIp`&E~;YQb<&QT>ih=wDEu{Z z+jx8#zmC^AT|s4q#RJQJYKY?-d#uD5cZx605vOeS+r`L`VS)vsH!lX7BnLcX>k0)9 z^19kQx=Q5Mmf>t+tUb-@OOH52Th<4OYTnJW87AwbLze5r?*eRXI`z^&*NdJT<+U5* zudNoKan`Llt)QERqXO+)%#5 z%jLa zouiJNV24%GOHC0$yswg1FvSOB8bjxwT_rrjEi`4P1`I_1`uR9-qoco=F0MtIQ zhY8av!_WU5ZR9^z&$V3-liyn_3}cOtJNc+B42gN??M_N34IRamRDz{#w@IHZE}%4;>Pma+-vB zInH2Tj*tVxo5)2=#ghAEc}&FOC}^zbIdI_)If?**Q%*6)!qj0)t#XmL=iw*t$14&_ zluP_%3*u|294;uz;T{*I$o6BF`GqMbKjZ`NRf%WK?Pct=e)>2x{_uvb!izZ$Ko^}`v;2(R##TL_4ae!KIpD=rZvAfrK?MQuBbv~075#9>Z<@TGNZ zNE**L|M%|a*ik#}zDGj9X^ynBL4a9N=O|zmO|<1McfxTV6!mEtmD9w#{eJ8leH(jU zB_*wj1k_cEb{?xiFVcja)hmE6kSd@lu(w~fD&Q$76J`!GK|Mr$4hs<0F9;Tn3{OF> z`mOQR`os)%R;55foIAWc%p%MpJmx3sPgay{G7F;i-`lG|&Sh%hWzssIjslWW!JL`w z($ovh$j&(|l$W2Rs70{u!>rL}X(yI_rR#<=SVAoR6rm$@7bH@s*OF=CETMlBf#2lA zD5x&TXoxft6MFle352-+&5`**9lxdf6L>|$`_ytn}$to z0_uHHzWP&q##l~ZE(Z~O>h$3b%q#t|BDh;5an9tPMY!$Gj@34t9=_NzBs?QL&OCU$ z2Y7dt5X=f3E;nms&a-W@jUUy!3qUp-tb=KmRZTQ+G>1`CP%vl^WDG(Fv4S2z(qDamC0=D-T$8(obS(J|Y-`!qWY;qa zOX%6j)yd(>{$H1WTywbnxP`cexTv_Ch}_%c&n&}I!?>YGKR5(qN)6);DN8r%=IWXy z*LGGeR!pevtWvEpo2s997eL&ITxVhYRO>Lqzh*csCKojDmT}p$BId!)b}ytY1wZM0 z?f=Agx5oMDYMsP<4S!v&+C5B6kKM1akBNzL8wuxq^EGZY;ohq#mypN6m*SVKj7t}- zA1L>$AeY?75|?Tp+y_l)n*ez{#5cB?@pCe9&HXKP%FiyvUkR#Wmu6exoy_jXrL5r7hfN9{DX#s+D>Tjc z1&52P9_ufwP-{@}EZGO(*8SFncT=lFYh(&CMAUcH@;Y4BbQu+|HV*GQad_n^Pz#mx7lFD9VprhcxI-wE!aE`~=P{n({D=^VR$ zhkrADoe3?95l`!)2*8eU*%?KP84)TJ~K8Ke&6m+XyCNcumJuyer$~2&@ls> zQXB6fFA#;#ocBiXEa?R1?O=Gjq3E?L;Fdg?vE}G-a1&rMfiX~-U)Y~p419yOEQqWf zKXh3XU2qC_hQVdiBVoQ~26_+x2=Dv(Qicqk8L!a`vJI%r$A$sB1owXB4Q+&X^88Qc zoA6o}^c9GAoU`u4jZ%OlhqU!U3xn+w1WK$&f*s8{g>_U2&(5~rE0#2wnM_D_iTd^p zGL4d-FSslDpHGbY`Ci>`OJLgpAEZrTESE>V#2;M4RkH>@p-(O;IKWBgpkt*72t$-} ziqr|oAD@x4c7G&(NT=5(LP!lYaM`ie)_B0V=8}H!ithiqVeKjGNnKdw5lfNmq0%F* z#a$U&sUqmIOiKG>1~A**mK%lU$6rx2__B;lgMyF#Y;3}eQvQ`7T%|e6cJKTD5Ll!4 z(HX6v5;XrKUAwRAgyG$W0${gFOHlbA_NeHwMIZXL;mRKv4y?<9)$FYbwr$0L9V#)NwB&GWU zzu;gcFoy_tSv&J}2#auR^+Zf?R8WvM>r=yLArPKe02k_M>oJT93nD`{oKXB%*JQXu zKbw>DDuA+&70!aOuOFje$V4(4M?&0@xXQHK(PJTelz7t3rrB_iSj%0~ReF$|qCcZar=F z=TZE%4y5lWP#RP#aFq-OlWqPh@i%`&Ixp-f-NA^S9&Gu{kA)UYTJs=!fe%KDS=Jj% zH%P{}U#wLnrJzk{MTv1o_gK(ze& zwrTQ`%9yVM^`Y*PPM?Z?@3%Xvx_>@ZZjVK=kYWDY!RN-@=?OpP^=8R&;s`<0-} zkqs9|B>b<5bj$s(4Ipq z_Oi|^;-%+BeM2+CC`D^Ws^o`nt}4bokK$4;>C8ck6=XHkk_NuX7EsaX3Qfm2uFcf0 zMYLcfZ@ zRrjAJ6t=so*_GV*BTJZa*y%N>D0|f740DL3UNJ0bN-FWF?$E>3e0TJePw+Qizg&pd zhYNSX=B!XY=wHd%JM>_=jIOF~y1k&>9;u>!!9X=%cLI^uAXE8wj=ogGM+bQXJv3Zf z-Qi7ylV`?GOM*($+rNwa_3RTj;V+a&>|^I0Wk{OLUDKT}5Kp*KE$D?$Xia;HMg}M^ zU!|y(yZ9NR`WKHQTMn`cy{4s&uB^C2rM?w&HZu(0y}1KSkuQfBExsRfg_wt z>%uIT%O)J!rwwnG58ax3r9X+Py{ZvudZN4F2Tn>UlfH$;7ufjqbua<_%5dIpuyd%O zss-U$DlWS4YU7~ZI4?MQ#TY=UJICQzhX2RiSwF=Qyjvf4cXxLUy0`>_1ef6M1a}Ya z?j9V12VWc(cX!|5?sECwd*7=2H@v@W_4ds4>`ZmlOrJf^`9LW9p$J3YHV#{*4;E{W zc4+Qi?3DKqsUz4vfsb65>ob;|U=wCQ#XiJuZN`KHR-a~j@>cX~btAGRnEE3##l4@~ z1UGWk)Z<4H`V6Ne&}3n`{dFz`?(Z;u=(hkC&M*o>PP1D=^>K>OfaMbBd< zmO2{bw^wx&Qm*J1j)_->hEz+-$kC1o=xf&=M=vcvP|o1LKwjMXWYPF8zknPl=b-NJ z=J&cSIAO^3I7>??m&;Q!kSN?@6;4T-I$3&2k_u{F+^W&$x6C*Xov4XUrHQawiOZg? z0!Q;&U8ck(>ghGph~)Uds(pb28jB+glWQ7_GaBKL$9)!RbdbWS9ah zgG&o$i)>v%;8oLJM6i%n|(jgE%j!1g=Agy zi`cbBkGzpUUFya4$e1tYdp^npSXXgtp}!JjXHdq_<*K1Hp~iyD zCSDQpq4m(imUZMDt z&-NHKs9xYLVdmWLL#&0}{i11rP$-Z`P?+C3T^e17I|I{YsN!+si8|4k$+&s)3_ zf~o%1uAYfyN){P1T9XeB^s8=657GbK*%x1MU-?elKl;hzRX;Jo?S8kSYa4qf=!@sS zrZ%iLj)V)Ofyg_keC-8`w2TKQ<$0#d{6H;CdZt_aOm<^DnCpLc0FkaFK7J;m`9UzT zY&DcWyEhQuLmHP9zH=$(Yx$*b=F5*fDu3j$33RF?Q5X?+TSl!sqWRf{X&tn;r9`Iy zX|j#zsH{+=PRQ3ay&%RvV8$EB@iEHffqx54aB0ZK_6UzmA|JDe=@(%II{g`S@zlcN zz1Am3buo@~8&b_59yt!9iG}!y;*OL;WYD{=cHYo<1|huCeu;UNLAhJbTk5`Ls!mj; zZQH!+!#b_Myc(vF?4%4@pokM|YIiqdT*zHFVPMW>o` zTVgL%*=%=|e_IeUki5AhwMN*tq!dMdqEE;Ve}x8F_OFI}M)P~I_KhwhtdCvr@?Ax+ zJd)Y2hGIY9RXd&NY&|;q0!x|r@X6kB{0`f1`SY7u0f~1tp!2tw{Soi^OxYRiA-MG} z{FfphuOrF3OYZ$X=5hkx794H1DtJ*hEVn&U5s&0aI1pdKN4ZuSenhQAe!e<6#cO_y z4bp2jHuW2}1wB%($cY??rUCQnl6zT$?kvXJ5;AU$&u~oimII$QUv>_5vD)SQxkBpq&3g2O@o^7D z+Rms<)Vew3_pNBM_oS(f(z$KXow;^vm`6EZUA{LY)3$gY6B)RQsq#0u2E;c*yXRk* zu-MYU-iaThrcYX@i1`O|g0XQgHxT(Nietu&QdBQ>^p}JpW!Voz_}z8Pq|>{WP+ zv=M)R=so7*xAWg0{g;1{i6D>npS}{@SncT)gK2qykaAqlZIERd3q4oC!-(d*&i1@Y zf>lrI(jNb4KBL5ij-jVtDKA-XqRYd_e*}FAsxu0KC1z0wwqTz0meejn3)-ilAy&_F zg3jYbgJSFVdJ^Ji4}dSL8+HP|z~-kiV13;JhaAFtnv$Q2hWD+0_t%_&>z1OR`L;~7 zBLY$jg05>wwj3YkXb+SxlbDlP_9eL=1P?)WPgyD-i^@P|OB%T#$gD;s{%xq8w_I+Z zUGpV*l#HX&US`C2AA!$D7L93H-eDeMYx60O}^e;@(Q;&W|H z1Z!OA0B!vV$o_;_eDTbEatL414Nmr;J9N*1Cm(K=vNJPIYvg1n?xpYR(+0mrb)#qK zod)nCHr8R+Us2SWlp=qsXT;k+LF}QEI@{lcQ;`$~?Cy6gCw_PiP5huFN1RyV7!$SF zeAN0%))E8v=fE?>A|OvODj8n|nlQfa(ESpJt-~in zOjr_l3bpWi$dgT<@P<;wrq~7=qqU2AM8oh4GFQ$A7`_x75l^q7f{FKRzW#w?7r&+` zrg}6p!nzdRC+u=!{%%Ws8$e|Oy|`F_o-c9ac)6gKlbWLT zhVcau&MDFZX+Rs(Ztn-_cx;nJ zE^(KMV(z^m*kSHh4x~cMPt6Fn4wi9c6xB5c&*SIDrbi>gnZvw)It#LC+Lv8 zrhA0kR^zZ$>*XsrnrL0i_o^horO6EJpzT3z?LZ_GYs!`h#LvtdAmbK+Y6C@VK^umd zlj6B*i%@nAbe7xQflfj|i}9Suz%FQnYpu?+1%t?`a+dRiF#oNU{v^c`+OX z-~<|!^<&lrP~PW$B$wx#kgf#V+=#r$`$74l?bp=ZFnX#>>;ZZxd(;yfrv*@6YpRvv zF-=N1NP;FE5@*EJA@+1Vtw~&of{Gj{9AdTcK~=7$9Fz~JwUE(4MVh}M1JGi`$lydV z3B+JT(4S76S+_k6n4UiRH`B$mRP4^q|7`d%3HT{tN{WdMfM^O#0wW?Kf+GS!7~+X? znefn5zr>})q{1Rlf}_SMD7YA-f)$`7#4Io~&GRfJ#85^?s-D{~-e|i|^e;Ld0#0gL z&P}fF&hTfr#kv+j2fYX#g&dfoUaHcJSZE}NN@#F(PZSz5%9caY(8?jL_ z!9AjJq5M&Xk}jAS`xd?Z?2`#A1Jz(RtAeYYpteF&49{dkBD3tWTZue3dqcKSV+t*=#uiG9XOCVs>%x`&vs<$e4a?xJ@uuTK8! z#cj!Z4!UfTo=0f4DBVMx{3036TQGOl)v7hf&FQ zo8-43RV=R5Vwt>RIGf};U9f=JY(waJXrfFF!D9Qs?Sf5oxcuCno-HYv#)!%zQA1-y zwW-{S7}J29iFw2qJM5X8$k{|-<-bFfgzC&E0%Nb6^o6J?%DcH|#d;cO^!=f48^wR? z7RuWuLmxKr@SnIfcE}`!RV$(}i~_9xpoM5zjCg(U#D-sITP;3cZ=_pRpVAGU4(O*< zS>e9|aaKogtjuNw6yT~nwde4yD@k}WMr10`{$?WYi;W*_HHs1=^+mNr4K|Rrv`Hk)F9j7a;58xL## z!cl4Lg;*>}S7Q__EaFPW9+;$ME`{Mq4q(K-g?hEK#&q(+Wtb%xhK`3rT?j_a5Rvch z5a9>;2a1M}DgIcZh-}}ro+pJBWN*^vRh}Xo62dg-VvsO4a%{SoGXcL%+KGHsoA->@wmJju( zJ|-N$Kg>mwlT~MtODIQ>-9{sQ_$p;(@F#T300Pb zmpR>Swz{pSucra7`Ae)T$*q-9wHrcG__zYR-}JGqCN_B8VPc+tQqX9T+7vN2EbL?m zD^c2PQ=+Ao0A(OZ1W7QaWln!OKJWvUUpF2AC~#X<4B`#MN4X~4h6+(acx4Icg9D-~ zF@l;n2$rEoxO&NeW3aBxYy zHU!WSbky^iiN9K;N&D3S>ce0fSzI|xIW71cH3x|$R(Gz%zz@p9tJu`)1&U*sm|9YZ z@@IpX=)YJ@esWK0b1Mf(JJeG+d)BTi3D$qHL{^V9KUau(LF^EDpEk#k1_b`C{=eZA z0#M5fe~L8$p!7hv$90uD$SZ1js{10!04S~-F;Pf4_MuAX)ZTKhQU`UB<&gw0IHEL& zy`FC5E;iUHyWrPwhEEW%N1>)u6YSPCzvE_axX*WdV6$4#gZR`^f?S~gqnf(p#^APT znt(yIyVQ?O1(w}GvRgY?R5?zP=1EBlmg#5=&-f0X#2ELB&{{mAra!^lnD$;yj~thr zMw0UzknK=BDe!r4?`ZEBO$%_hH`5{h0#+Lp2qTHp++;k$>hMqc{%^3t@4;bm7&n1Gc}BQf{V2(%IlMrIHuE{c8Mm^z4Q7inK* zNeR*)Ee9HyPAq=o{_{(q$gf3At(Z3ISrufJBhSW>lNoss45cU{iQ~FfP(BO`%&&=< z96|!P+&qm4q!$Pbmr)rz?K)u&h~~{-zI0aOQXS+!*&hki!ai~jx2a`UK)PRc#VM-R z&Vt4$@`Ex6BOb4=7xXBc6GOZPE&}(=C%=`S#4--$a;icOVDUkl{JFBCDAID^CI~J6 zS?4bhaSzeSI`aS_Zx7;j#t}uTcGRWkdZ4(!jquW)$I*uN?4`(uWa9w;>Y3tVu-ksw zP6<{(4haGzus~Nw&lVN@2yuWKQQHo5EF(&h7TXG+y$B-QF2LPHX(t5-^}ubTK;3g% z_3EnNmWT$6K>0u=5JKlf&)yZ_2LTbP(R~qpZzCF2mgfG#KBCoOU*dnI3zq4A#MAX9 zy%k(;B=$thQ7)`uwb2OPr@Op>?ZUVu;=|G?mk|1YX5se82(KS5~Cay5A zJsUyTg%iZX;X(0`#6_;~V5D*lGEbsMp-0JrMpW=oA$*#U)!_e|dcL$AjsJJ*#s2%x z)cZx>MxpDAif|$K^VHU=p8e6_i`ebzW~bP=kXKJ6tceomP-3B?rwhrAie8ZL@hW4_ zRFF&0Lj#i4CfX$2bojI&RS@P56=^dDeH{LcLA<5}9m12`wkLH5(kqP-C54@ZS#}Qx z__n&Qbqzi+1NMu|R`5X(WceN4KDW5(`SM$!Pw#LB*XsojJbB}q3=M*rL)pnDml;*rY$2+Y2Tzz8ogRH@Su`-p&;<`Ca=3Qg$CLaBHthGxns5c+GmxFE%S z;tK9c>9=T~7Xo2b7n>bmN7st|HsP{ddF(9XVM{%UxhWIQu} zdt?3yR6!xsRrB5{u?+_XfGNi`sjH6>t5wIoT+s&IyMv4qmk-Y2=1(O4i)SG+^Q$$% z#%NXe7y8U)^vM2Akng2sR=Wv2|C!1&rWGV=dSF+e%k)EnI41^~m6`ijDI#}PEOGj4 zEVU)jceH!v>*p7GqJQOyPNR~_ST+kiXmaNL_1CM(Jfhv*d|c!{6gTzcMV!~-aVupu z35^r`2Gfe;T{X+bRwvfeiYmI$xAN0Ilq=}2IN(u+H^}D6AnX%s=p*fc^?#xencDO6 z5PxO^3TyoGP#Mll!CzG;QArVLd!M3^ zY}V1eqY4Gk&ktNsoHdLD`7;ZKC9mtmEz88$pbR07ig`v0QX!wQI3TZKG822adU_eo zV2Ou<98kT{bcN9~fdza;JcQoC)7^Odb1m!IvxGS%+tm=IP%~wxbDSX z8Uv>=Ly|69TX6lNRzne0M88AIJ23c(R_pdCl>+BLpk-R>L;Ys@@4BqlnL`K*3$FyA z6mAly!A8O?O9EmjkC4XM=|!u{WU6QdUm`CbQhAST)eR4BK}stnsBQ??xZpRB12Y>T z_}Ay z?uk)5HA3Z^35hw7KQBsJP z5*wp6kS6U_jFM-VPp9S^f!= zxGjCnKWFQQ{}aKWuN4~Jf{IszQi+;x<;{3Wm{LAaH2Bn9dnlv~@?IF$W1PD~ z?{b?l_eT*kizKG%B#%feo!ge3!P>S8%s*ZQgbdRC|4o<|D_V}l8)902u%iQOc{*3Yf0W3dS&5dPGj{yE~g>1otj z8P&V7AQB@S`A@RcG5CUV`>PQi&r**k0Fec$dT%U)Woe6CHhEhcv=wpNdrgI!Wdo`7)VO2l=*fd+OIghxinHw}lyg z9kGRBdm9~JjnvQ)Nxvs;=1LT&AKDw!agA*v`DLd_em!0qx`g2_WhPGVXTl*~DV44z zWq=uPZdZ>LU7yD$=u7w9l?M^3D#mNU4mP3E?@X^T!P)svMDpGXaVqiY1F>{y{oc+p zQaPTBSzCX;%cEfbmCjEsXME|_dpcdrkfZ4dH~vq@xbFentJKYxf<cIRoZtAn0i0hC zINefg3+ily2Szi{jM?bN%?7dQk9*9i!=B-Ue8|-*H?%L7frccn1R>XQw|`hJxt@gx zN}_|XUS%nCNbU6@0zej~-AmM8C)KM}IWlfp(^ zvhCC@L2AS9R?vs*GdAuC8oW`!UWkL4+J&AoH*LDvLy4r@Uo?r?;#KU!HRuN3Jl8nR zUuP;|_LF{|ymmta(p>m-A?Q;Jyp zw5htjFMF*xwud6$+>L z?I$~Kk*cmEY^9XOKkG{Ay9&bQS$9#fSZj!`Z=~hOcLjV_zZ`o>_f=KeqvdT;BX40A zey`34W~tdagT=jr;ASz7zv?rFK4&>*{$<=MM(u{ML$pIbMLLB&-73{^MnZ>-gHwW- zgkghWv!AP!6*53xM_7kjhh0Y(o-I{Ocko5ZFrLQyjEKeDhVB`)PZn~kvxPc=N?vvM ztBKx#S;kt%TP9paT}EE6^?T5?KNau6?1>MY3v>yJ4ytO})x4M4{<6)s{l5PP(6KBV zSQdyM_^&6sCqjH!$-hRi0UKrr0vRG2+;^_zWJG8LRYz5aR3})sXe*-(Frqe6+h*>$ z?=draSZZ%MJHCayhetcNc&zA|`8-E*Aa|fkAhHjb(-{vs9dZeZ52^*y;{iP1+~tDd ziQ)<8iI@R7emYa4*a86=(!+0rX~bysLgKfob#rH(;g!23&JGBUa(hB4Y)PXC3kb%^Q&)e_@ z@f%SZ3D?nFLK;2coXP1RYU64{Yr`)?JVH(D#UkhW?7l}*pLqG>nxS=Ah(bO0>;IJ6=I z2rnMTJRbu3GrD80>QbDV-UCbF1NJKdBC542U)8tsf1kt9-af0}<_qE#?|#hJ!=%2_ z$E6v_eQ>^;=4*Syehg8Qrm46BpIRMEP{tuP7BU`~rvH0kE2=Mn&gwxVbq3a+OJxfm)PAPQ?u ziO*@K;5X{AFL|Bl9Z@^y#=rKrCpBpO&e1+vw?y+U{?wdoaq2m1cG8PGcta?ZUNck`!QdMa6)Vjg&>9OY5r zWLxqYTsvUa9Cgd<=v4Z1)800DvLO-`zc^FgWVxzMuIgip)nIS?7JsWiDw~GAw;t3? zl?GL~%EYSvtwybCL3aXC8^0!6_dLoil!bXip59o$!0iU8Uf`8V8 zCn6^EwRPMRY$DhFPwgd^s;Qfkj>L1G$XPIgxvtY{7=yirUO8pt_nPlXL#u^Hyjh!r z;2e_L3p}h_fHJOInD&5G_T+9x>1}QrsBCI#FQe2wdD_y4x3uDoi0>Gfg}^E$y?|+d zVx#YkGtA?rK)!T*v&UchCVu^k-D@^o_~2XKJ?)3ZMPpqH+o>Pg{d>)CGWp};-@WAD z=IOLsVeuS7LIaprf|7C>Rzk7FRlxz?S#5otZKTvDO8a5u3fPSt8?+y9F zhiY}^R2iMU8fB{{w}p0ja&5k9VxGlz^Nk`WIv%hjCI;m5*I!Z*B6uDVLROt1_Uk$N zT{b6tMT|iy&MXG`=vf{)ng}=^o!=38P4c&RUDnN$?|#;?p5JcEnoa5m6ix=dbEYgt zJDHG_M8*#eH;Iqq_*hYgyUm+9QPHdZs&YXc-C5OJ!xGM<|6y0QJjc3bz1LJfDs-0P zt_fQfGS@5bDkzX!9iB_3gkDuNH}}sPuzTz7{UbFeAG*I8o?LeA1Yq>HB&W91Zvw2 zH>RA9#qTJN)X*!!`Ma6QMz3<2RA`+cHB>bAgDaCN2SU}&H8L+$HPmt0sw*oieOtU$ z0VC4tZW_54D!l5baax}|CE$NP+RC4j`}7o=wa(gFkIMy}5f`N0c9M>H?})a_476%p z7#Gy;_Gc?wjwj6LKcQnlL)7okkC1nNy|c;HFDgCSs)N}Pke4ZEfe<{5aS z#;VZg;q}C0)%N&R{CpLlvC@-e+bxxc2UOVYFSTi;X_zy_U9^<`efp&G3m`ZZYavkV~mxTqbZIFIWVYN+~; zDL1e_;=_xv)jfHt`bY6#Lcywl^AM;rR;%2;87}+RKPUS035rc|4 zPKlL@d`c0;((KBFo32m|<9?Ids_L@!MHBsjtE-?YSy{(iu1O9Kedzhm&j4En&A}?q z(WK^~NV_nevwxC*BoK|6eTdiB6sj9!NcSTMMf!w=0 z-xv*b8fV20MBLI*_1xp{SiB1l$e;Z_hJNOm^5oMnS>i7Lm~~}rt+CI3zq!UtsshV@Vm>*&-Nrfvfah; zfaY~061AeO!FtPE3=$t{^uc&O@tN$Y_W>lhMSbEIZ+8i3n0Wxj17*KFk*%Ei?0@sz z{~U@X!!hn>_A!f7qXQ-AG7?6#5bTU+GD-* z^uu^9&=Tz_PvF$&FybP!7$_U}LME`|v;X@dQ4J`o^mzbO{OK>*dn(nqw`ekf6QBK@ zi^LnCEZZYl8`x*R;UbY4DEsG`Ozr{TJn;Z>+oI<4jekA#*)P3F-13WGzXl{7_|U99 zd>x2SC7I$DzZS-B5}twyJ<6nb$rFH%*9(^A+D=r!W<0#$A?m2lUi>BhLugR_&)8iX zz+-#zmFZzSZ#{c!yTy|L{Yc$EUiR|kneCB){0Q4ON%_iJq~G$1B>xE6HyEBae(8lzgp>ur_T}|{fB;03j0;yO7^aqzJz;@JrF{3lui1a{MhSk zXyxhj^*+}fvZFvBy%*a)MKUH z5xOa{G_H=krAig_$3ly`WQ<7_GH=4gQzW4G#1l|<1-A(jy{6k7|KWL(@3nrKcEyrc z!s~D0zcha1nRovnvFN4la}K|;$tm*Tan{&0FRb4llYWC_FjDpCV=!Us$@+0=X^L{z z==FC|B>X6YkIM_V_zrt=TFts%*_`c9aAwYUuH5`CC%WBe3Y=2t>L$=Hw=5E0a%qnm zyhTGT^{_@jEivZNn>u;0g89^q7>E>2Z$Amgdtk}u2$9mO+sM2dY-=pVQbwNC(izuW zNRg6Ep6E}>gC|^M>B)#}q71ev0a(Cpoj8eRIA`)41}vd%N&(KbnF!Prq&7tX%NCks zEaS+nNNdV?R>g?_$>z#_nZsL^U$YWAE68`%e9Cm6VQvv)ghR6kL>0GD(qG-IM`XJo z`-lE;!uQXGzv&SE6@IP#{)_%9y)&ZwaIiC_d(XZz*W*&TGdbW;{}uV-5YUUHQ17wkbJ}$;;?wQdBVzSoL*9VCCVN_Z&-v2o*C%3~ z-=Mr^dD?g{@Y3nm3$!w9U|-WZt#WVoo0zPtUE@35I?cYna4+>6n`~%2i^$#km8-3z zsF|)jLUe7dqb5RaJF?mk=c~DxIyK_m0JNhZ9;JEew4)&&!{3i?i1d~Fk~(4LvLf*} zg?&uRjCn=(@65;QzW~zPZl#7sUk$o3wuUNSMfc>|vGay-g+zck`^t~|L`M+t*--Q; z?UWrJ6m)Gb@D)f6Kjv|OA)tLf_XGQ1WLGO(Gw=y2cg| zS4v6VHxrOnN}bzx6_E62vK;kt2I^7ZkFxKlJ14%%`?KPYIqtU{I(Cm<>~pp0{YhXx zV0!A(V_gC@U&FU4{YkfW4q0aiNXg!}Xp?qGUE6nWlYFP~7|lOmdx~CXeE@Yi=dZJ) zgF>#gyuOm9$?mIoDUhYp@5_0~=cQTh>v$>UrQ`2Qd&wE3Y3*xdvN?`!nU{9bHk$p7 z0p&16HSDtp{P3qc0!|*n1?r#0f2v?xMMcxAkwRKL9*_y#R$~Ne|-O>07ZkN8n#ET*RI!Y44(6yKb+fm#C9yc z_39t}@t9jzJh$+u>X_I#KmQrv?9ndT(Xnp0zHx5wQ0}u1_?PEC)qb=wcCPV|mAzx& z;n>>U#<#Jxq41EFeIT=*gArPtfZzl|6DSk|dxE9FW?*%&D_8++2i61of+fHvU{$a) zSRQP{0B~hZ!E7gM$9!gW<-YY{;C5wB!5u}DmJl#T`eBTDSV!vK7gUEL8(Q4oTStr* z+HZ_Ii5-Wyg&Bu>ggP906M7SVfr5{KkAjc1h08_)6w;&dRpuA*b!@e2)o%4{m1;Hf zH1SmRboP|@wDHva426(+oVy&qtiC+GwA>N!e2(ezJFQ2@Pz#+bSQf~ibh~|iM;0wx zdH}4aWY35=jIhr^R+n}=^PS6t-$p%rAw5KYgch9K^AgVO8TH3HS!AsKQC9De+uQDz z)_p+hipD$u`=Zj(AiW%fuQZLQi>MTXZJOFo=JWKa$1tA6C?rHK(w?>$BBP-y;ZX52 zKX$cpKbl^aGQ{gYEG|3d*J!=CMwNbA_-dc-ZgHn!x}d6OS9JJxfZrtE5Nt#kZer-d zuGNe^LPWOq9Ohf6-c`Yyk?K8egi0YR-*g z*EXU{OGhnvDqm%a+vlu){jsxpTjS2M^80H5%j@v{+@99!J61@NkOMPgU{Wvx<1Z}n z8SisB;SIzleV#vdYOBfb@P87M&!ST zFD|cXEq`<`Eqw?vSL;ZA9JfD-wpk2~{%z;b=Tw;jh&rXFwnWmGJHwl z!@(cLA0=<+R;N(sP-k$}D*p*S|DHGvD17`_*z^dLPPDUM`d1iUXldn~K=WxxM<;}( z7FWT9Rl$JPQKyMu2-Dzz*VGyej0jxeHI1wKBXE?1f$M@6(G$?F(0a1j@$mlfc77u| zWeHfUI4AUeo)@^wdr)6cU}nLI#YsbAmNpG-?vpXDs#9D3;8=}&bLu=;@Qh3Us44Hb zo^ncG+UE7D5taUo^_0Bs=Yb=CF~$K#I6XGJR=&2s9;SPapWMLl(1|{cmFwLcwT=^C zqk0wxFbf9YXXEmIK+g!k5KQ;0FMiV6*nUay*Z;OX|2vJ16#-2nj^z|$_Lc5@8eKI4 z{&(N^UDSTc{6|U1ae9C;bq-Cv0$j4342RA*0#_8_$bJIixRr%)=D32{HHgQ8i92_H zZsDeFoCR(s@9^n&I)W7m9LQry<(Jn3p+&0hD*G2>evrgI9$DYJiUE7kK=UmL=+B~cvY2J`Q+SRv6OW)s*CHNtg%Y(A?t(-fLqT}E->|b!+Z6f~ z`jBk1sk5ll>g{sg5U(ZSzsm}uZ-Z~4Zc_}>3_=ZNPiC_*qSp)HuztINP@OdZ8rgk# z8lnq_b>A%L8^ZxyvYE)I$&BXm{0uiKUVW6A@#FAl(I=Kar4}U?q2fk$M|68RbqZK8 z;>K1-SNjlkd~|&H8IjXN`x$k#bhP+cqm!h233b?YNODqX$C7rEh)UmnW=0?EZX>1l z+y&X{8M0wJIO*u&3HR{}p_7^BY@j-FOajAo1*k73%SU}c;ar?iuu;wyzrFLkAsa8| z-top|wB~Tr$r2u)#!I~|19>QCr`G$41Y(7NK!RxPS{co{4EZaoqod+nPgm0D*0CW- zl4;wVUc&xdKF>Yg5DJ8lZ$ehG>PBeeg&lTii3E!gycUYuYKt-UpsYqbJL<)xW)tGZ z#cI?~rg!~)HS`Hcuzs={nYm7WG1V=k@h943KWr;P`ZkwdP}NV=KmDk!h%MV+Qu;~D z13P}ApG(pT2ZmoFkX3zESEq5Ly`Z_E)ks25vKf(;i~X&s`Viov1goK93|0t1dixuU zm;1swKt)NXtzLIz_gzhv>inBaFIB&ReX#HhKC*09B+{P}Cv-3L(}5n6f`1o%%34 z6Z!ic>%v=mAo;(h{6vYv^AAaxqp~Rx6E3QlT=v zH4`4Z2;+PQ5rkwKnZ@L0PJ#$JxbzXDJL!YICSKi24)F(NOPQ_XI1nYed}}R{O8zlf zL$kULdrmcT#OAUTLFtj)5u)ea`buvSG-HZVk3|h#-w*mOK_W#$&la(VAAvRVB6uYR z(=8{A*?)n-K5*4BK6W1?wSz*Sx6v*m=K^ZL&Oi#iRX^ zL*&swg&Gk%sx1a-A)8+W#xyUO0l<-I=fqC`j>@o=|3iFq+=IdvLiSb zW^#^~BRZx46pQQB=Y+?!HpdFQ8mfwbiqcJj4?I)ek&LtL}2ji!*WlRUu~^H`p_3H@2i`8exk=QB2fvU}^E0rSnY$ z;-OJ?1a3>{nxZf#wvSAf6MO3e4Wz(;XHu}8F%e48hp}RoRd1!Z4^kr#)5#L?l7Dt09wGT&oH-!&p-%^4f!BojUj5CR(Go)86 zY+I1tP~N(vCKbJMqP|rkKEYlr2ecT?019I+24@IO&43QvtlWBwbl-kI4&*+}do1I4 zNe2n-7K?<5bvM%diNuMH)T0F^mQt1Jd8rojPHHyTJzvZ(#efDmNQpQ|i5n%!GDyidNU0Ge$rUAOgA>jl zCFvX`i4-L%JV=QeC7Fd2-o%LZ?>otC3IA_dCs5#S!eiHNS9wsdHT6mu;A(2om|$Cs z_@V)GIfR)fND~7k_v+lFko~tfo^!fh283w8!t1<=HWaflz%EGtQivo-ZJBSWj+|+S zu`>)E;aydx*NQtVhR}3y+4RCY7+~WV?YARkjw2(gat}ey@K8jq=wQZb!43biPf!j!Eo$;8))Dm9`twqIoC zW`?99k3TYBvCg&MPXI`TaJt~;_mm#qW{C!0a8hmsMD?jZelqZ08($2*8krL2#H*Uk_`4yXny+zpT(%hnH6*J@t2mEI`yz#M zON_K+*MTmRX|b7$aM6v6x39nfYrpBzPPIYmk1lr2x!YL}55X9vQDVb4NZamnuHY*9Exm+$x9wRK})rq`C z4Vo5m=DFkYDdkS4Oxco{&0A15Z6-EtST=2{Hf^Ev7SZJscxudSg=s(JSzBUs9onqW zGuh6Z0IPe?O~a^G@x-%aj$%IR5%;Z}XHM9wdt&N52pbEmh1%laukff>%tX8FPhr!5 zyT1dtrdLOq4AW&m3o*Ze@2_@OOw-%8pU`+Ys(Y%u@gksvty3rp4`v|(*jNb~Cz2qF z-9&+#2D=d1HS{YO4s$yEBy5KMc&?L!JK`xavuFPs63rOx$y2;9s^QoYC2;a6sufm` zQ>!o48M#e5qS@yY#w>E~;UMY}CihS1?RWKey?52Z$^^!FoE(Wi-x=m{J0&D{3Vy2dGv?s3A&D2Nw=%8coFk!!mi2wx zskv0)QQ^^eWO~J!z?r~h#bL#*!KuN0kAg7ht-2AeojAE{fAs-Iee@9D&~>)LSt~Y* zNN@x2G9`s#to<_I37WY%i`6)&If~WFI`X};x~-?H6_O{rY~&W@7BTJr5&hFGqTXQH zP`Lel@%tj7#rU(}ct8*KX#(|}tsa{j&x{+J!=0};$B)`NcIDoDmW=zn>Nj-k1|^TX z$M1Tfl%aE_&sJ%@P|VQzPoj>F>19%JQxC1r)`%^qjVu!nr|R(RS3t1Lu}UYI%<)Y5 z(HE>c50>W(ol8-ZGIqROD@Ux=Y?~(XW@}NRIsc}jEFqN%K*eEh`Qc7VvFlsPQ~j-6 zz%m-$Zl?pYiRRYF2Y4{xEI!{CzP3Ob5c*v?@jLRj3V@f5GOCTTqKz`Ejk3LsGO3NS zzKt@#M%m9s8QMl!(q;;7K2OH#(|P&&bbi2McyaEvpPesT&3{;tk9Axo_LfrU&-C=# zf}~lzxkW_9{1gRcC?hD1CWur{-#DMFQ9(Z@VqSjD~!_G0<@-znS~6-}OY-$-Wii*xR!E_VmS9StL(+|K*a= zmnnY|eHZ>_<@KvbIQf|JHvN^?tGd6SXmbAG)DH5a1TcdA@Y|F0E0#ZDcd+3|?cvgu z`KydScX#U6{B7$GZ((xHYTBMJ;$VKH-xQ`j|ytvnv!(U;l zR^X+K`wSxpxZjD=Nq3P@?8CA77`N#8hk7nD(ugY4ijJ(F301}MS8M5AG1VW_1$NKW zi|B{^=+N}+e5 zJM<$_k%>5l@8eiEWV5Q{upEp3=1#@+_8{u|g|m9C^5f5RIEdF=#C*LyFf9yF?0#A9 zviI~Mk82ssS{ikJ;v@axHFzvEO<$o>G~nK*`ydzZ@HF%xyA^_sR%Qhbw#0U z-WC%6Rg{#o(-#0GNE;3A3>O}Zd}^Ql?a0MSkva*lQ4kwO1haN1nQS?T7W0973atGJ z%Trt9Z$sjN&KLzGFvor&I1KQRqyPIA{2=l_{r{(r0shG~9L1bUEEC~79aKsr#Q#4{ zQ2G}9)3Yt547|$mY~z4cOM-2aex-%zpNUqFz8E3o;{xQclJt;GuK>xC{SU#WT)e*f)?G~y28xp zwxN*c(mIebXo+jxtZwRoja(5r4d8kL8-ale{Z+OWIX{MU$=@eNXt9 zfyeywfQIVSv1O*f39q7H`y7nrHsu-#Fdq%iAnV&V+;If z5+6D0jQTblTD@`TPy5B-$>kWONi+I{72il^7ZCMpmW ze;N%B%%r&af)$Ey&qn&P^3*#Qfmr(TmGtW`R`x|JiRV`8`05x04(c(p=9CtYK0A>7 zpQ!KHEy$(C2)qh7ylJAkwG}IIDvkUY(g)T$vB+%PtY#Ybix5YfFTJuhd__X%1kSMz zR%lpR88WfNmW3X6@tZA9v&X)lj2sX#kR(RN{J|!3Qy87pt_KO$O;ME3b8Rj?jY|<_ ze|Ia3E~(e_H1n_zlKGu;O`?qX%6PrZ?$Z~c{!TOZWRs1K_FR;M78$6uu3>_P zQyAypxAB$psp=>u9=Zg|lm_#Zon5M|0d6 zqGI!8{FR(%)?a>lQ~m0C+|A6qVTH?`n}ZW{ zK4fA)qI7w94^`_&3}87@t>5OSUQTcE@Eg46GGDhEDnufoD>RUMiY3!OBB&FB`*->V z4}6SRHwHY6g_k7p^47ya51JPz^1l_9E?aN;#X0S|Hms^`p2ds_IL<}!UnU0XNT?65 zsNVN1N3VeooRaUpC}=tTXqJ5QHq3#JPHU^N7^j1(Hp4+N2Un@isMb$nli-<07@q(y zeV5*2RSR$~rs!N!ZmxragY>nC@-rkehL`a_j+kz5?kq*tdhW@bOlyPwNF^*R+XpV2 z2fi`hSl1j-8ObN8<(9B&Zhjr9&h2FJ=tVP_`M5Mp&veFm;oRwbCqG?X%Wmk&5;tHP z5SI=QH9ef$RH&4_)cnYvP>orB(ASHV9s7*Y!`d4qpX%&c9wogV@yjdD<2)!@R8y_C zF$l44_C^pOBAm-k&5@z%!J;(QJzWbV;g6!SZ4-N4OJHZm;mmf?;j=+`H ztjb%8<4k7tN+numO*cMfnt0EC>*=6fEq&zgxQMF7)L6)kp|E36-7DKY9PoQq@}(w` z)y~*{CY>h@D2one@5-pk*sqIAMr`vOwz>*NVI|(KPW~&OR6c;M{l$9>KWYrQaWM66 z`BSBh4e|VtVfzw^vAGmibG9%UZ`)sw3aHIv4Vl=hMW zUk7G~Re$JhXlbaI0^iVly`d%E)L7|-EN^KnLpFI%eu}k5#g9)c5J;R%M;ymE`!gk7 zte*S95sNd6X?eB9zEp$vUvHmy%5m~V-NP4k&QwPij(rwM=1XSUx=@uc8m*oipq0eP zs>5(x?!<|D4CBz^vh28-vBWPW&-5xpooQv3QP?URUcT9$x6$7IJQ6%{Q~(5%+PcBJk}i=dlyjHyZMC#Wmf_j$l_?o}Sk=oEQkG zz?k&N1ufu$8#%)o2p@z8_st7ozbsp({S?}BnvK0gv$hF!3f;SGIVcvR^@rPz6+9#C z%lTuq3+2n9(Ymn$fq2NxkAvyq@9i%^_Tpk58)?nzcymV68@t>fc{+K04c6m^y788l zK*ZI&-{I$aeI^#32t|)QM|o%7Vz^hnWo6?Yl0YA>M-y*mGM4=FgY2ng-sTNy_Zst# zZArli9Arz|IgMz@d-B(kJA5M1zRj_)uk!P%>(5Bqpt~bO9Irh>q$fC7rmXDcf4*M} z2MvaNK9vr`VJ1Uk!&ZB4n+0&>p}1ImJhYawOrq5T8u*O!cVC@J(AGZB-gCb-sMQ%9 zM@tYoWx1)`dAF-0&HTpcF^6mPznswuAoPLHoB-z`+<7yRduTWG`y9=keFtp77=e&O zuzI=SXywDbG4z9lVXwbyV6e*Vt1`hRxl_0)H=O9OXn*OUm-KVvjkz{8$-?2PCE~2F zuDeZasi(Dj<+_(_rk*VuK3>M=Tk9q210~ar@?G0m)oz8rWa``;gBg$Zl5SLTY6yfz zu?qCgKywNVN#4GrEAq9TD!BziOk^8MP>5|cs*?UWqeAVqw0^I0?N;mxvEt739>l8v zs>HBG_u!R7@sA7}?)Z*;@A6%dLal+>!LZn~vR4l!-CX`M(03XyCD@Nq?(&n(|2V{> z89@FOwD{x{%0M>YGbiSNQCU7;wEw=QECV~AjcUJi`VCCdx85^62M3t2^Lbim!^8j3@$#;7)|{2ZmagrbR!jZ z7prp=YIZi_ZlV=W4)vg+ z7q7`IrMp{Rgx9UO^?5~ocvI-gn6)G7!)or&h8UjkQC-&SS51scUT~#1vb_ot)|MQo)Yq{Nz zj_;dbs%r{&jdO`l!$a2G1jtWBGc#Q%BSt*Gk+||}G|N#%#>Oa%*R$IPTx7Abi7n+3 z(4ddAWc3}As~z09oM!LuK3v>}!%t_VeLO$!j7zR;3PPUh{}?ut?s{*+?auzIkz)Q1 z#6jlKA5!61X7_|Kx5kdDhf}b~FCKg>H=N@_q!JP3tn3xB6R8K{ZV8TB4mz_NUJkpo zR{JT$_wY%x^pB?{JqE^QHZrp%581ym~p0un%<<`j=*Ss7tdp&#BDeu06KT zYT?#sD=ZXoCfV}eNRFm&-&rAgsAewHJjo4C)Mm+Cmh^$!fr}(-Q`OdLE^Gf{m^FEC zU0^6xvEntq;Owg?xGQeoy`Xf@ItP;>vzT*ela<4yzG=do;>us<&WBsRw!;sbTMwcQ zEM@f@hpcVhS~qGanlp-(bkr>;h<4JOekwe(xBtR8Ltt|2tH^c^z9nI@wAG)w_M}L? z$?e8XCnkB(h0K&dhXBuQyz17`WsJzp`C1a8ABJ5D+(J7zd0X!!9H1o(Uge5A<3Non zQ}gqw=_7e<7dwhMGd?nO586p!%lg;*(VtHe1yjss@)N@OGHt7-bO@4(p4k(c@T}Ee zW;N=f&ijbP!xPxREji|x#e%aEkz3s3DZ?2b?bLJZQ?(3>Q;tGYLP`dYHw=VHxDCR3 zep=0xg_(#83S1BC_f1!0q6ziC#NTnWf_?eZ@-6dMe~iE4>{}FCUuBk_3d>x?T`wDC z2y+i=x6+G$OE?j$`^F&iQc6}#rFln`u$=9uIMO^SwFP6w$FjF8&Gmw zofx>&6|XV=0iyQ3bq~BB(j=zs7-B52em%&=R34OxuOq{QJo)R zv)IaYIkai4`48Adrvo|DcKYAUxH^z#9{TzDIfv9IN3`;6c_Y@1%l3YRonO;!=z3|X zFL@~pbv2R^$8i>6a@cVRhjjEQz2Pp1b}2W5x{ns9pMU!cYqe=Mk3Ae6S;PsR4Qw8k z5=^k373M%)^d9QIm1;pk@5r_+@fpS9axjt)rxFy}MWsq!ENYbYm2^e!xqpo0yfkF! zp=9uL_?&Veb5Z7%xAx%7yBc@1QK>lW+Ki6};>XPV zlp77y#o6S>mHVTFavX$@IQxgH{_KwxhU-Sj7oezv;z+G8!nqOp6sTB9~ z-g=rjVjdQEfQWr+l()e2gk^#6Mi*$a8pl{sQOc(x?@ivNQBI8-4Z0rnF3KrVt#{=nZFh@#7DKCW0jK3g>~knYLI}#w zb0bHiWanx?u!?X*9Ue1(w}EGPVALk5pz{rK>$}C1QQF!4@b_{k&be~??=I)ss#r>P zJBU;wf2Bd3&(3C{;xl9Os>5g+3HYAF z0~rbaQLEMQm&6o1jmMtSS~5s!?y^OaLH}GEkDU8-R*QszF^P4kB^~p6Ag`02XVZ>X z=lUjR$*1Xc@eM7!GS1b+EIm~1!%RuVP1OU%h@(&2+|}BNt_%EIt&WU+oiG=RN?sOH z{22*me}Zyv&Uphg8@-TND{g0XdwV_7xLNnRWp>TayO|x9>nqXB8*Pb4cDKe`1TSp( z6b72><9TQBy1K_?_KAYoT2t6tA9_{iXC{^i92T|XSs!YOvxp1j;)XGYOe)V z*Y~MSLuw)+dDGj+2YwFXy{nZPaz@f}+A?Ma4En0F-WAmDj1g(4-dw@uLz#ms=p|#L zt5^1C!m_MiM zw=ZVvsCiyNHWPYJQHOggbZfDpO>TADb9~v`^lH;hhw&-}8b4vRE$6AVt(i~wwtmga zL_WRxWwXa)9;Cvg+i`98FBrLGyE>vOM`u9nBK!=;v?E_#b_2@F-frqf-& zyl(!m!v*WPMrzXIUj4FaA{obOOb|i8GqVzfq-(YX8>@dUl*^FZTH&=x3?QmINlYm9 z;7@dim=AHEHmFy{rk{{`ar_QzBrW$z_|xbZO>nR_4ri7+)b@*Gb;0 zyC%;~Gnjv(J^xfz{&8YH&4+xdk^GaD`P6%ifz)^FxY_H$*SRgF2vPhD2kfoMQdMWH z48K2~(94ifX-D(|R=TH)r4>CLh+MxA^2-|4 z00+5UQEm(1fC4z601k4yr`#WagWSd`%K0B|4y97q5M62O53aFF{liu{lO4kUmB3E)5iIFOVMFuCvf{kUKd zr2`D2bbvvW4lucYqud{*0}P^c{Mq+VZcFI^lgA7c<-hLdB!^2`NS%@AC30XeiRt{bvjeqNn?R$xh_Hi={i)-%0&7<Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
    + *     typedef struct
    + *     {
    + *       uint16_t numRows;     // number of rows of the matrix.
    + *       uint16_t numCols;     // number of columns of the matrix.
    + *       float32_t *pData;     // points to the data of the matrix.
    + *     } arm_matrix_instance_f32;
    + * 
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
    + *     pData[i*numCols + j]
    + * 
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
    + * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
    + * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
    + * 
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
    + *     ARM_MATH_SIZE_MISMATCH
    + * 
    + * Otherwise the functions return + *
    + *     ARM_MATH_SUCCESS
    + * 
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
    + *     ARM_MATH_MATRIX_CHECK
    + * 
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
    +   *    A0 = Kp + Ki + Kd
    +   *    A1 = (-Kp ) - (2 * Kd )
    +   *    A2 = Kd  
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
    +   *       where x0, x1 are nearest values of input x
    +   *             y0, y1 are nearest values to output y
    +   * 
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
    +   *      x1 = x0 - f(x0)/f'(x0)
    +   * 
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
    +   *     x0 = in/2                         [initial guess]
    +   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
    +   * 
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
    +   *   typedef struct
    +   *   {
    +   *     uint16_t numRows;
    +   *     uint16_t numCols;
    +   *     float32_t *pData;
    +   * } arm_bilinear_interp_instance_f32;
    +   * 
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
    +   *     XF = floor(x)
    +   *     YF = floor(y)
    +   * 
    + * \par + * The interpolated output point is computed as: + *
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
    +   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
    +   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
    +   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
    +   * 
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h b/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..f2bb66a --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc_V6.h b/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000..d714e9b --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/cmsis_gcc.h b/STM32F7XX_Lib/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..d868f2e --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cm0.h b/STM32F7XX_Lib/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..fdee521 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h b/STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..7614450 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cm3.h b/STM32F7XX_Lib/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..34ed84c --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cm4.h b/STM32F7XX_Lib/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..01cb73b --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cm7.h b/STM32F7XX_Lib/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..20963c1 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h b/STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..ca319a5 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h b/STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..a0a5064 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h b/STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000..4d76bf9 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_sc000.h b/STM32F7XX_Lib/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..ea16bf3 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Include/core_sc300.h b/STM32F7XX_Lib/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..820cef4 --- /dev/null +++ b/STM32F7XX_Lib/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/STM32F7XX_Lib/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a b/STM32F7XX_Lib/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a new file mode 100644 index 0000000000000000000000000000000000000000..0f4894e47844d43cf8c6759f0ef3753c251620e8 GIT binary patch literal 3136980 zcmd?Sd3xo3UO^ZlNu(&c@_WBWt?jAnQ8r=`8Uqph{Ot-IUp_R2@b|GVAY-cFxZ zBACILVQ|4+WQ*XEdghlAO7pJetf53^r-8M6nUX7=#`W`EZTv;Rvw zvwwb?*%x1A_Mi7L``^7RW!sA^rR;H*(i&zd=dQ7oYhGn32Pl2~UY7E%T$b`N4@>#t z7g)+S11#ki53!Vg>|v>{U$WHZZ?V*i53tnX2urn!byYb@>CeJt(A>n!cp zuduW~Kf)Xt4>5;3z#L7X#P`?|bLiiHbuh;_o{oRh)2EpHI_Vl{PkjIRT9&SVpLvC) zt8Yea1IxJlMV2vkKg;;1<;3^t$5@8`rS@j1Z>IAwi+=|lENkL%wyj{0Ww%BX-~FpB z`@SWX{plsd;r&#{AkFoq)*IEAkhgtqy znB{+mp8s)zxpq`BS5Jt!2KF%5TLziyfRnl2_9AmVa+0~ecrSB(gE80Z5mvD6X;v_3 zX9e$EW(DFTD@=Wi6<*%Q3LhL~h2LYWXxj=ay75(3^wD3kqF=wxigWH~#r-d^;;{%T z{`Ub^9GhXq-=+NjjikS=smmEBnyntn4`lD|! zR{rW?R?)PFRouMFD(+fj6|<*V#hJ%g#dq)y)^WlkTf3+Z}wJ?H;G=4~AHEv4d5&JkF{=7Gc$^Rjg*z%W58XvYP){V4ho^ zW}c6~!aQH}G0%@3tTuC!)s~!OwasBx8+e@69{K{Sedq;N`?-f$?O$eCUHTHMtM6lV z*WJ(Rj)qv>dtYI7pS+CKEks$}kLdbpF00=@&*~drVD%S2&FXKPWc3f;&+6x9S^aZ! ztp1m)to|R1tYPOvtf6+9H3aB7xXK!ar&z<-tE}N2kFbV^BCO#PKGq<@tlCzGy{sw2!J5j?XH6ZC zv8I7tZ5?1njY}6rcY7XuG$&lWmgU>TUOJmfzxSZQm@v zqosAT?ADG=wYRixs=RYk)oq(l7X!#qPqvdaCj#6W8j?!Xoj+Sk1 zj+Sd~j#81_oP%wxn>I(~Z)lFn-_RVDZ*GpR#?%~Li>Wy(+teJDYif?JqLYn}9=&#W z-{BF=G()1TC6ORuHgU)3fdhv}&O0`8aPJuArks%*a%GD*6WMU?6$izI{ zkV);_kf*is+|h}vM{d9P=z)=l*0h78k&y#hjcE;S@mL?MEgtJ*w#8#LbXz=C>uZar zYME{ER2$DN9-g(q+S)Uh)J=&wf2;Oy)$lD^yhT&DXyfLM+q_j;bFLoQKN^<9dKJx4 z8cst7&0yn{KuhJcHfExk8#2+x4Vl!y4SCeM4SCeG4SAg#)sd;d5;NANWur2!&eSra zoK|O3rdDTDrmV9mPuAI#C+lp=L!C`osIw^xbv9*fFa>fd85fF{UwH zjA_$iHyI@3M3+-T?r~Jjy%Wb|r(@^TlU>G#2M-?`p3pLAqlGlJO-iezlGaiN>8>PU zEk&a%i^^0&R^A!K6B(*RB13!K!O_Eq<2BI|x}o^Ew<+AXQ86YbU0 z`t$JUfxTlR<0BJsrG^~6y>S_1snMgO$%V8GLm8Q&7m@zq*zkeTNc+AMnq`sG09$h+ zd-Uk-BV*&*-X4FfH_@y@&3sdKT!rzmzDlGgaBz5hVsE^1;}gS&Ml=@zbv-gNW=x_I zi9&i~_Ki-Aji9E(hxe-aY|K(Vq->UN@4n*`6C+~>51)t+N}|R-^o6c9DZ4#6TbGeK zTMatnEkoBDA8gtWs`!?L^se6Unz%MKzKObSHkPeg_v)`P3Mb8y4G*?#=9Uliis=GI zm3p3WY&Of&>uHqJdty9%nC7{h0=k&W8pYJr^EMNZ&sBeE&s8Exfl)x~95r!ek)-ZQ zYdJiTB zE>XLU+VtL%hQ#oixHct_q-~SDq*fY*lRA9EgDso6O@!nrlqoZScsf#B@_a|0TQl6^0F)!(L8y{>{VzXE3c?YQ)<1|8W!_;~h@{)1*8@Wpud>wNHMqRS9FQ^b*Fr z(W7Jx!pG=Qa>pj+814vgj~{l4cYORlHpFg4~h7zkkH>^Fz-pyy4g)C70=wHw5gf~y{4KPpBO8Y7a+B~7C(pT9}@Evwz4roFPAo9IvKgUz0+E=)Wk52A&T zW<*h5$sUB^VN%Ns?&H`9ZT0cFkZ>!te0>s`^7R%P^k}!6C{hnLYSJE7qAH~q zO-2?HL8)Te6RnVjBh+e(kFh=oi40XVk)aijr}eiQk%AE=$a}4f5iAVvO8_%@uihi? zl{kq&J8L!v>LiElY)G}Yd)xIm9gGl7LSntfC&rHNpBQgC)|{bb9yxOC=-vsOr^Pd= z`HF_t#Z-=DedBp?`q`9|ER~>^b+H6@+}5%&ucc#SUYDMwlb2K`Wu)ToHUV>%pv$K>l)ZSRmkPUJm z!7=FrZOl!mH|E9%*N|zh>V`*~s?thrsc-YTnsRlP$I!KSc|1G$#d`K;^-X?umU3Iv zz?5xdhfI}AdX)SkmJj?vz0VeH(qkHdYc|@q1K==!5bM`WynluFl5HNG?8bnjQPoC zdXlPPu*^v{G3FbU81oJFF=TJ7(uRjyC^T1WQ%zcCLc?bJpn1A&kddU6KFKzFdKUdH zYSJhC-c1yk*Tq&Mh9++!V(x$~Mb28?v%e!wSe>OiG#T@HGC0IKb*1ar@F-D1^CLs; z43D&1WtvU$ZaL}Pn??Apd<0bT%Y)p z4V58RO7dLE@6dA1T4b(4gU;|I=Cq!ZD4F1W^f&0_PNI~alPHy-eDqTB78qKc$V-$= zjoL7neE{cBrWc)=`i`U!P+39w-bhP@kA4UZ;PF-->g%*p2=^qR8 zutbWn$BN{Wly-UXunXCFjM;T*##U@}Z#AT;urrZl6p>Fqy-H-v~AN8v=90#swe1*_XP}TwDynOl3uFE zjmUG@|BjU1{=f8kNfE=AF_Ov?o*w%UPmi+TH4E0 z(AMvGKV@1g87ZTrUp}%{+S95i!^R!`Bx$X5qsS0umZO8F@Mp26hzTxEFA43xhB* z-el!L`6#Y@I9d5VgYv&a`3jU@LZfZl@Aw=t2JpX6(El><$V1(f`3bryV_Bc0PO-Oj zV8AWuF1kpGOLPg&vQAP@+uN_#Bzkm-!@9&NmUSWB+dEEZ5_@!s_vsREu&h7QtL>d1 z(IoECB|b+t+fa`;EG+BQR1)cmX(BVa$O~~18;MZD?)#Z0@{}&}m$*n8%gVtl?8cO& z=KM+*DWtUaqU|i}I?A>8)Mz52E5A{ef{bR)YhpJmw~(SKNz zxKfvRn=aAJvL1wl|9zUoZMwwAb&0(!D@X%m=X09GgSx~sx`bd^Kc)F$4}4dX_@XYc zN;k4Kr>NWBiUyzaCr#x4=pvbvt2NllvfhQBJ=aB9)F*$_MVjIwDJ*L*UUVLe0*RE+ zMK<`VxJV|;dIS^Ye7ufC0=mdVT!cC$hjiO7c$+4&A0k*yAEX<-+fLKH{lbrH68Gs6 z^ST6e+g~AZ(KDLFtS<2*U4pvpy?D#O%bLVDb&1z?3F@|1bp6HY)F!IxE4oA(rQ_X3 z=8@SiY0yNn=_0Fot}gNhb=xPQ<ILwscC^ zL;E$63v`hax`-f=BFyU1`!tb|F7k*jl17X4X^7nNDNW?Px`@z4ewxj)j#0vX>$fzK z|IkH#u8WB6EDPglKm0pQiaH8oY+A*)MVHf+2m?ng1Y_(uuFHgX%cyK z$@(|c?XC;7oOn0gsFyj$vX0Ze{p2A{;u5+@ttWMf-?6MonsWBL->pd;)+HXL8`+UR zrC$0eCG7V+u8F))7x`LTgsj~?7_d{%Ya%ey@;(2piwNpScpmoXA2g8{=#u58R@&cY zr$$hd(J9$2l%3LyQL&`ZT%>)#N^>RqS?ZgVHbZvyujpw?moeuc38wTKbD%hd8*}DS z>O5o4h&7a4Otg?C+Q%&COTmBySBs#(f)JL!$8n%QHJxxttNo1JpAF=vrlm@;h4 zc^)z&#vFJWDWk@mucBQ?j5!A(bDJ@TL-TQC&g;;8XSSh+PeA4#V@@_Y`|ZY@e}m@x zj5!}csrMLju=k|A&zKWKsRxWXt?2m=8gs6Po`(%N%(BC>J9}rQExRb&Ne``6EHl$j zN%8~om@T^}vp4hNoismGJ~XQQ6y&Gwv}9(IP>O{TY1_0C^u$MhNx`w5bU`S+n&FaR zv0S_pa+&3nZqB5s*B*Zb&*~!#uuVRpq0crxv63?B(NjOthsN0OIfs^`mG$EPme;bk z(HxdAh0>P&J$on~;?UUe5jXvUXJp*%iTFBe_Z&KU+&yvZ*x_+E9T>Yuj_eybaA4%X zp7y40cdNIhP!#dq$7$KYaYa$ets^`$MBgN7(;mwc{toSyNN9 z_TRYgP-mDLQWBcCj#(fl6zCYxqAHs}|j~+YfZf$KR2z;}< z@yP!0@qS_pCq^QTN4h9I5juWkA6*Yp{=x9=9gXAR#se*#$idIq8fo72hla-vxEl{0 zxMO(iU}LMh@ya%LL1m6LAuT;WJm$RKHDr1F8QqG-*nx$%(Ny)+PSa zQkulnVN4EDk_2Yw;bSxw@_(3W#`5tWgl_UO^K93q--h2->c4o6>z8$)b|t^b)Nb_? z*5gOVM-LqxIpE$;Q%bAnfn&!hz$G#6w9r(KZne-h{{j2v)u&&38QU*cp|S1iRq{ut z8>%Lo7_YLqFZEx-8r3PILXD?f^HfkX7QaqSQo8v}q+iC;#NSv2q*}7=o8;?;tCNu~8eKVL=FWr}O^jV)%~CG)mz))ws5YBA)egC|^kun8J56(n zwCJxlceU|1yosOgqvtoNjcTag5AlVq26JP+wleg5^Sd|vURf@1V>c!K5{If$;+2|e zZT=*3l{GN^j2RW!V6C8WFP&7x`#zyX(@pCntW`Pj<7Rz_)8~^?A@x$9~mD%Ha1@Sf5BT|=YUKd zhU>^IO>~=bp5{1Q-o;Y4rCpwG&2Z${b1l0p`8JoOz*1-_vJ_iNtrZs5G=Aa;MK02H zVobY+^gHrACRh`k0@k!|oIFNyW11+~mol1+iyl@7ZV`;zmNMGPz%XtpqSSP5DWO{* zS~*)O(M9kFa<-B&nu{%Ew93#t+Dam^1h&a%hBBxRyK&$f@qh z7_g@OgbPQ=Lv11()kp3V2t6`_`|_im*{K9wG?dL)Io(5!;H3PR zYu3&P40Zk0QSch@4J@1Mtyj`nZ7~F zH|m=)=tCdq`tC64gZ|C*p{tGh<_!8!FJ0eylVUxb6x6l_d>2n+O z!-=9qSFn=~1kKdd01r7R24f+bmu#jlHy}4WH+eLE5`4=|ma~t&an)Fp|p|8uN zFKWBGF;tp84$^vxLbRU7m@X3~cv=FRlYnDosV z^mz>WzG2dLU<-XXl{JpXf@E8G$fk{rRK(}Yy<6zZ zAUUJH6@xzb_qx6olfH+x(AQ|vw`S1iHR!`Jps{|BZJ}?_q>puJ<90sjqMupC>lZQU z`@$CbCQSOA27T=YeUF&*J-vm#X_G#;K_4|eUO!>d_rezXo;2z68uS5r>ErP;rH``Y z=a;1KPlkb{r2PEEq%T1F!lVTK*F#@j-~X8O{g6&DKBcLU|JU`sVUl}0ZMv|_`bU?0 z&Gg>6Ud^w;dlB`bzc-t1^fJ)#FzLI%kfGleDmly{e15u(u@~Wxs1M}u-EES4GLQZO zwJxM&Acxa_s$y7w)R4~@PK5Q3{@xvwL2~iW2+8@Wtp3sEaHXXg|2#y-XNKx`0p*-a zUlf78!4MhswKp?%qwcKIGhH9uCVhj1O(5QnsX;;C;q7B5h~8j0$A!5*aq~ zo|B&&DoA2B@=%kX8wNr?&oDiQrPy9G*ksV`HVJ z=kNp)9~*OCVO~OwTJ!&#O$&t4zQkkBxav&vmPy$=GOTNUk4tip0mp+D*@4`4b-->oh%wB~N^8 z6hWD+AC@`su}RBnO!p-cbZ3(mFp*_rJdu#k1E%yjru4aSn~RyhgXXi|16sO)4X6@Y z+RlPW={$BvQo4e@FDdO|pGZo(*^^0WC;LuP+QD893g5|7A-5)|CE-DP3eR@z7syN}p>=Ut>z& zYDz~<=|@fJCroLCndl$9|0PrURZ}|Mu!lk(F?RX~=>}8!TvHmMc=`wOhfL`^P3iZV z(g?ZJKPdktQ~G7Xfnk137VGyMbo|7J>m*_8ga zDgBZu{U=j8!?2}8e~~GTI5_=-=NFmM+6kZO(5LEvmaWHAXr!lpDrP=*NYZ(_xXd>SY6ra9 z$+213cxY`bqmKT!?icD`qx|M4<&JPwQmx* zqfbV2NttgftAb6o?gP`iXn@{ipv^;wUZ!y|z7(VPCi82<0Lusl>cXvS3d5H47F2c9 zH=9O6S;P%}Wzwe>vRMq-#@C{YH@sIj_2$AdKdH0|)G+3$vvUnATW{9*0_$5uU3sPrjQ`KU?$Z7ThC zCI1eUzE`E+snU9X->1^=QqLziSuA{gS$# zQP-!{^;vcOzPkQQUH`1EDHctCuDVvL>&5E&R&_n1t|!$MXBueVC)M>yb^WHg{!m?4 z)fK;`fqbpHUaGD~)b;)9`h>cEUtQPL6<9#_r@98!_3i5Vn7V#lU4N~vSu_z*u325L zR@dX|`XP1win{(-UH`7GZt^iv{ycR(sIKo;*T>ZrzAEI_)HR1D5Yp}Hia>6p?^M^1 zs_TNf{z6?-(logmb?sKyo7DAgb)8Yyr_}XV>bkD3^sg()_vPcdht7sox(U~t7;97M z0IoL@r>D|a<9Y*Q*Q@jaT!$DNRq5Mty`HhVRC*HEw=nikD*Z67*D>~}NSVui{FJ=C3N9N@SyzqWv>*rT%o`dIe!Em9E3} zavE=y?!)ym#?DdcD{!U7c#TR2alM4G5tSap^{4P>(5+6QXo>B!xmlE0u&C9`q81;E+6GvFx;|hT zVgXx_EwB(v!{`Po(<4_369$eb1-+k51jqFL@=)KQVDP|FXmBf9d+W z`8TU}`XBGPo4+HF=l@CZ-F)Sy0{{3wPV$#-FZLh)=}CUqKbQHR6({+ZK3(B|&!Z># z{m<<7&)sv9zy6ZP-*fXxZeOqWdwNgue|0wd?{uByFL+x0Eq}U;PX{{umw)Fj{>t?} z|9?Gx7k~a}um6d6-NpUy^!r~QzKeH#bUF&yVd?$Z@&Gr6!OYh_#>b}wc)<2%$g_qv! z|L8YP@SS^t{_{R^g1_VNe*YCmPw;~$5Be7ZC-_(2JL;d#Il)goeAxekUqtv5v&Z~* zeIdfH`qG&HzI!A5#;1<^*RP52Z#^IJf2ShCAN%oLe&_G+;6MA-J^nAp?%)gSQU5dV zrR&{q_xB9l!Nb;j{rOdQ@NeJuPXA56yPf|i<6Zu=uinldeBY$M=-%7;`i}SbKXm!+ zJnaMT_1~FyJ738EC;!)9I?gK|exLuYPafwD#Z&$d9XZZ_^3i|xm$V<}9c2&tGygWh zTV@{e?-LXJyY3JAEAE}(`Tz1E|D^*H{2%TQ`+t%-!S9=S*#Euv8JkBE@ z`=~$rnsNTq;z#`#<&N|Jet5?J+ZV?8yIlY3Uw>$fKl6c)`@`3c@ket$;lFz47|(hC zC;g9p=QduJIqSdv{kQR_@B5Vh&dYA&7VD?|j`Z933nw4O9Q%?0d#Pw0bMA{r=beuYLGde)6J4f7Ye9@@u~GtpEPk zZsGq?_niN(Pv64d`;l+?e|Y09{5P53_WxV@E&Q8zJ@5bJmq&TsZp>o@A}U}{3|Da=wH6|5Rb0@$p7J8 zhxmV9^P>M-v4i|X>?i))4jts5^8D04x&0u&@_`k<^UEXrme+pf&wT3$|J(jw_)pkJ z_&=WerT>P1KfsT-{mTFNl?V9E55Mdme|10qGW)gv@#+2iZ3lnjzp-yWfAYEC`tSPb zKEB`kKYr)i_wf@C{ja~UY9D{?FTe9oKQqjKbK~#*?>RWk&pY!6{~uC^d0N@4{^vg# zsJ`O7a1^5<6m?Em#I_wvQSy1(WfdwJu`U;RIJ@8y5_$KU)ZvA6P?n_u^T^2WFF zC%^i4f9%gU^C$A(@L&GG%{;Y-@oO4y=D&QI@$YQZ2UySP5j*hc0Ty@jr`tM?R@5@8+pS_3cuwKH}JP#n#w;jc>}-i&#C;D z(i?c^zohYh`TP)n;8F*_W?+bac#8%6_2L#>hSgaGXoiXz;-?V^6xYFe}CXD z{MLsv`9Esj!k;}ii$D04>-f@dviM_{T*u$`z&76U<7@eky0dxjt=IA&uVnM5{&o$& z_g&lhH{N{>|9+#BU+lVu|JV2E`pK*LttWQyueV*z=Sp+<*A}kg4?mT|`!BzW*M)ZS zt{)Eay;-^Zvj+xw_gpTY{oR%P%h&AUWp`f5fB5HJJl}pLfAqt7eCnUB;AwsN{M~t1 z@SKTv&q%4}@4o3={)>-R^YHRH{4Jd| z{Absm!-v0J!+*3C;3)?^e9vV8e$L-L{LnWz-}O)}fBhWJqjhz>=(L}|eW8v&)8Xeu zZ>i^h{f~Zr$#3iVd`&;!9&O;ZnLa+6+sJ>I-^Xv5ZREZ0@8vJ`Hu2ijUjCPFH}S_# z_V7;(H}l8;(9M7K$7X(RsGC3ePA?z%iH}$0xA45HeY|A0gdy{PfFh{N)Ea`1@~f=YO}Zhi8z1EXtrPbU+t$LO0%lcj29Q zH|l`8piZb8>WI3c&Zs-ufVQAbXdBvywxZ2wJNf{9fj&XsppVd3=ri;k`Vf7IK1JW6 zkI~oYbM!sN0AqnM!PsDoFjg2dj2*@hV~H`v*kX(^));e)J>~%B0_Ftf2IdIn3g!&v z4(1T%66O@<7Ume{8s;449_AqCBIYFKCgv#SD&{QaF6J=iGUhbqHs(0yI_5m)KGp!% z0@ei92G$7H3f2tP4%QIX64n&f7S zwz0;s*0JWX_F)5H3t$sq8(tOR>`(OiM3ttXX@`>_XLFTkFFy#ad!_6qD7*gLR? zU@yU*g1rTM4E7rAIoNx!2VpP5o`k&#dldF6>{-~mu!mtU!=8q{4SO8+I_!Da`>+RM zFT|dRy%BpP_DbxT*gLU@VlTy>ioF$kEcROLx!8NL2V*bBo{YU2do=cH?Ah46v4>+X z$DWS89eX_XdhGew`{4t?7l2Oy-vB-Wdvl_$=^U;KRU|flmY920jja9r!%(ec%JZ7lKa&-v~Yud?oly@SWg8!Iy$h z1>Xuj7JM!ET=2c%gTWVrPX^x%J{o*A_-ydq;KRX}gHH$F4n7`yJ@|a^{on(_7lcm; z-w-|`d`0+-@Ezep!k2_k3EvVvCVWl!obWy2gTfbuPYT}@J}P`w_^j|%!-S?+YIozA$`Z_{Q*&;VZ*uhVKj?8oo4qYWUXhvEggO=Z5bM9~{0od~*2a z@X_I`!)J%@4j&%AJbZfi_VDrH>%-@V?+*+BEC5UZYygY^tN_da>;Mb_ECEabYype` ztO3jc>;Vh{ECNgdYyyk|tOCpe>;en}ECWmfYy*q~tOLvg>;nu0ECfshYy^x1tOU#i z>;w!2ECoyjYz2%3tOd*k>;()4ECx&lYzB-5tOm>m>;?=6EC);nYzK@7tOv{o><0`8 zEC@^pYzT}9tO(2q>V zU|SbqTwq;bUSMBfU|?ZjVqjxnWME}rW?*MvXkckzYG7+%Y+!9*ZeVXU41rT#vH{-*vvgZ`)SID_$^@i~L>q47F{@uKlN zgYl#BJcIG1@jZj_rSU$4@uu-VgYl>Na0c^%=EoV#51KD$Fkfi?oWcB|`E&;JiRRZC z%rBa6XE5Jr{++@6qxl%ae5Cmq!~CTA8pC|0`5VLhrTHAge5Uyw!~CZC9>aX6`5(jl zr}YrSdZ6_Y!}_5062p3-^%KMTq4gBQdZP6e!}_B27Q=d@^%ukXqxBfWdZhIk!}_H4 z8pC>}^&7+brS%-cdZzUq!}_N69>aR4^&i9fCwmZsJs|rKgMA=-5re%T`w@fvAbS#n zJt6xNgMA@;6N9}W`xArxA$t^qJtF%QgMA`<6@$GZ`xS%zB6}8tJtO-TgMA}=7lXYc z`xk@#BYPNwJtX@WgMB3IACnxw-EWVy^X=%lKqXr{*pb8!5))+ zj=?^Yy^g_Nll_jtev>_q!JdfLk#-^?H4iZ7qoxG zuz%2g62pE%`%4V_3+*>C>^HRk#IXO+eiXxgMEg?=`xEU~G3-~gf5otW(S8=gen$IS z4Er1HcQNdDwExAh|IvOJ!+uEnV+{Kv?Uym^m$ZMzuz%8i8pD1{`)dsQEA6*2?6T`!ns=G3?j0f5)(Y(|#Vqeop&)4EsCn_c84EwExGj|C2uugFit2 zK@9!@`3o`l3*_#5PZ#NdCBKN5pKLjFk%{t5XjG59Ow zzr^6bkUtZHKSTaa4E_!IJ2Ch>+E#o&LDKNf>OM*dk0{u%jeG5Blbzs2Cckv|uMKS%yu4E`PYdolQX z0{$}j z&jS84`O^aaH2K#8{x$jA0{%An-va(O`QrlqIQi!S{yF*U0{%Mr?*jfi`SSw)Jo)zm z{yq8o0{%Yv{{sF$;Q;|WK=?oa9}r#;zzc*Q1ULY~69RaG@Pz=rAiN=fHwb?S;19wh z0(gY*i2yz!ydr>C2)_v67s4|Fc!uze0KOr-BY<}Z{|Mk8!b1Xhi13jBJ|es%fR_kA z3E(HfQv!I3@Rb0*BD^Jlw+Md;;4i{s0(gw@nE*Z`ye5Fx2)_y7H^OrQc#iO$0KOx< zCxG_|{|Vqf!h-^Mkno`ZJ|w&-fENir3gAb=lLB~>@TCC0B)lnrHwk|V;7`J%0(g}0 zsQ^ADyefcK3BL;9SHiObc$V<30KO%>D}Z+i{|ew=!ovc1nDDUxJ|?^@fR_nB3*cwM z(*k&!@U;NGCcG_xw+Vj>;BUg?0(hM8xd1*Vye@#(3BL>Acf#`mc%JaR0KO-@FM#(6 z{|j&cbT7aG&@%xJfMf+Y04giM0gx^M4uEtEZ~*i!0Sfc72%4uJL|0S_G$qRfc9fP5DL4uE_a0SsJ}fP5bT4uE_i0Sv$ zH~{jc1vmimtpzv$^0fsx0P?*BH~{j+1vmim%>_6B^3?@60P@`hH~{kH1vmim?FBdh z^7REc0P_6>H~_)|0vrHg0|5?zuz~;wK-fWm10XCRzyT1p5a0j^YY1=vggpc}0Ky^y z8~|Yx0Sd*hPQ?AS@%m0T8wk-~b5g2yg&|eFQiF!a@QZ0AV8m4uG(d00%(W zNq_?&EG57J5VjKF00?UdZ~%n81ULY~VgeihVKV^^fUueX2SC_OfCC^bC%^#^wiDn0 z2w8KVX0KC$K;I7uX;D4eXEp2lmH!0Q+Nn zfc-IE!2TFNV1JC~88yDZ{upmye~dq{Kjs6lKjsIpKjsUtKjsgxKjss#Kjs&(Kjs^- zKjz;VH6MZfF+YL*F<*iGF@J&mF`t3`F~5QRG2emxG5>-6u^xc^u|9zPv0i}vv3`L4 zv7UhavA%%)vEG3FvHpPlu^xf_u|9$Qv0j1wv3`O5v7UkbvA%)*vEG6GvHpSmVGn@) zVIP3~VK0FFVLyQVVNZblVPAm#VQ+x_VSj-AVUK|QVV{8gVXuJwVZVU=Vb6g5Vc&rL zVef$bVgG>rVGn`*VIP70VK0IGVLyTWVNZemVPAp$VQ+!`VSj=BVUL0RVV{BhVXuMx zVZVX>Vb6j6Vc&uMVef(cVgG^su^#~YV}Ahl$9@6qkNpGKANvWgKlT@3f9yBF{@8zj z{jnbb`(u9s_Q!q&?2r8m*dO~Dus`-UV1Mj)!2a0(fc>!_0{dfs1op>%3G9#k6WAa7 zDX>5GS73kax4{0`e}Vn69|QYie+Kr)ehuu8{TtXH`#G>b_IF@^?DxR_*#Ck3;ST`& z!#@D_hra;q5B~w!AN~ZeKl}?|fA|}~{_sD5{o#)Q`@=s0_J_X$><|A1*dP83us{48 zV1M{K!2a-mfc@bQ0sF&00``Z$1ndw03D_V06tF-1D`0>4TfqMCzkvPWj{*C`KLhrM zzXt3N{|(q5{v5DB{5xQO_fB3h+{_uB!{o(%t`@<@n#*dP8g zus{51V1M}6!2a;Jf&Jls1N*}t2lj`54(tzq9oQfKJFq|ed0>C|_rU(}_ksQ4{{#C2 z4*>fE9{~FUF97=kKLGm!PXPM^UjX|9ZvguPe*pUfj{y4vp8)#>uLAo6zXJOM&jR}c-vavs?*jV+{{s614+HxH9|QXXF9Z7nKLh&% zPXqe{UjzFCZv*=Se*^mij|2Myp9A{?uLJu7zXSUN&jb4d-vj#t?*seGui^vbGsq~u zK$e9L#V1JJc!%N}?bL7}!j1}J_#~yP)@j-HKV2&uhNX{M1 zASnDdJNl4}8LLh)mAtzgY4 z{!FeVtSQB>$+dR{Wk^>sa%O|C6==HbL=&(pJD` zDE?5|64(^QFG^bjo1^$gX^UW!6hA3#6>OH`FQqMmO;h})v~{p~ivN_h5H?ZqqtaHw zW-9&^*dKhVw5_nQif@&+7dBY&vC=lfMk~Hn+HTlz#pg=f4jZrdUTOQW2Pi&R?hV)@ z6kja&4(uU{PnLTN_87%C%e@DCkm94|-h@3$@zrwg!XAdb40{^(HtcbV@0NQX_CV}~ z*b@~$F8508nTkJ`dnxu*#jne~7JIJZ-{oG6Jz4Sda<9got@wMnmt#*?{Jz}lvF9uP zU-|;@3Do(3^cCPUsPhBqOTed4=L^!;fX|`MAEYk=pG2KcNM8j$i#orMz6^XCb-p2e z9r!%z{6qRe@QKvU>7}YVg_A`Hl4D z;M1w|9qH@A=TqlD(ienJsLqF^uLz$}ogYbG51a?U--c4JWTq=@R8Mdne?6EL&KMbPp!_^q^}L1Tb;j2UmQNU zI-iriI(&9@ekXl-`1I<0Px|`s`PKQK!~(zs>U>aQ1z-ksekid7Foil_lvo3pL!CcL zECNiT&L<^S0cKI>mlDeW)2Q=JiFJT^)cL2xLcm1od{km3U?z2bDzOwWl{#Mq_Q!dv z#9qK)>O59rGhj4zUMsO1Fq}HimDmm#Po4Kl><0{}&VzydB}P=|#S%LLL#p#+i7kOK z)p@hTp1`2$JX&H?iBYxlYKdKeVbyuI#J0e=>bzTGUtnN$9xkylFtR!?m)IE?TAim$ zYz>U9&f6vS1_oE>@e-Q@qpS0JiQR$W)p@?e_Q3e+ydT&<3JyTU14wQF&sDsDD>kKm@j0jPKt$z6d1Q1L97-;(1} z@h+140tcYtVI(&O4nW1rNbU?AfQqNV`jQ-*ino#68#n+Jk0ZG`Z~!V^M{;-I0Kny8 zJ%if=2cY78B=-jnK*a;WK1hyG#S2O95FCJtCz9MEH~Gs$VH_$JA9f&)L*NRJ@qvj==$_crxrSl4GX*Msm*J zp0WR^cr?jPg9A|UYLdGK2cY8FB)1I?K*hUB?i(C{iieZjI5+?mFDJQkZ~!WvPIBwu z093r4R6L*L_Q3&w>&Jc%?jIb0iU*Wu1KD76J|c zXCv^B$X}9YCMteXo~3{TQ1O-WtOXo^iocX+G2j4He5O3B0SBPsH|1FlH~==D-1{ zcwKpR2M$2R^UAY5Z~!XaSDyWW15ok6@@x%352cY7^iL04jc8p5=oBQ1SiptREbJivO3f z0N?-+8vuR)u>#-#5IX?=0I>w%01#UMegUxt-~bSN0R9272;cw^n*e?Su?pY-5W4{W z001(>%egm-%-~bT&0R9895a0k18v%XZ(z3dB-?13+vA_!Y!jfCE76 z1^5@lVt@lcYzFul#A<*8K@L7m$0SACs z7w}z(eE|o6SQzkOh>ZaUKx>7AFGK7MH~_@bfKNkg4LAVA+JJ9E> z0L1EmuT#I@k+D4B^AOtu4gj$};QJ8!0}cSOK;Q!r8w3u3us;W1h}a=;0Ei_5pNQBZ zZ~%xk0^f+(BX9tSMFJm**d%ZOh*gq&CB-g*10d|r!Dk}22^;`ooxpb@_6ZySVxho? zA~p&f0Ai)Umm+ow901u;8B;~Jm4ja;Tg$-#AodFUD`K(00U$OD{48R%zyTn33;Zo& zxxfJ+whR0&V!gltAodIVFJi&K0U$OE{4iq0zyTn34E!v4P+K5G#oD0>lo213)Yx&Jz$@2o3>)S+#3JH60y3Y*i&!-h(*PD6k=1s0g$iCabAVk zRd4_@mX$aF@@+ZJw-DWxKS0Z*98~|Z| zj`K{!HiH8o?9XxDiP&dw0EmUgc_?C|!2uvv8t0{modyShSZbW7BDNYF0AVc|bB)+* zoWBwlXcvy9cvF;+NFe`d5u*R^3l|(G8KWf3h zh|MaeENthrg|*FCSmvyS)z4X2(Y%HAE?8LFqJ`BgSy=wEg>|i1*!EQmYhJUkvULmN z4r|oyv__pSYt-wuMjak&)Z?{AT|R5n7qCX{1J-EOpf#F1WR125t$?y*H{y|!q9&lc?t*rF)|w&?CbTXffuE!q*ZMYn}) z(Z;YXS`x8E`zLMD$|+lP=d>-_He-us&f22&bGB&Fye-YQy6ge3+a7Ru>;aG09&q{W0pEZ^BdCT@d z=ZZa$y=o6Mt=R*m>-K=(krF6(rUZ7lQUWdRlt8*CB~a^42^9EJ0^I{Cf!%{Cfn7r> zfsSBGU|T39&=^h$ltfYj{gWwy%BhsV&gqmu+e}Izb2cSVKbI0HnokMzE~Es~7E=N> zODTc;<&;3zN=jh+YD%DaEhSL4o)X}W)CIRQb;0RMUGTb77aX3{1&=p%!R1R`@C~Fc zR1Kys1S#Z>A-&UETR>rCoG#%$_B-CXKI;e6^s z&tmFA^-}6W-g4?f=Su2A_G;=v(^~36>3Zsd-;uUZ?o39mEmnY4w>*|dfF zxwM6%`Lu=J#k7T*rL=|o<+O#am9&NJt7!|(YiSE*>uC$z;c&a14!6_gaC*gHp z!g+_gXVKxVUUInemL2ZS6^A=})!}YhbGS>_9d5rP-CgcXckgheyIVZz?pklUyTF(3 z?jA^Y?;cEd?;1*XcLdYj+d}E?#&Ej3B$Dp#pG2B`Gm~lHZW}L2!8LuZ}#^cSHarrW4 zd;=LXRf8EbxkDKY0F_kfsGo3NhI-4<5H8xPuY*w&tE-P3#pB3y`%nDX7Wd-w= zvx1!~S;6eptYFhxR#1$Vf%1zSAZg04VB74rVEx>-VA1@xVDI9#V9nCDVE*#9VAsmF z;P%yR!REDX!Ls#jLGH+2aXYhDoUZH@uP1xOv1|gUZ>OLb2@zkPG{Ai)0sQubhd|_&W5nlSsZaX`zD>viYccvXWHp(opn0v z=A6#Ld8e~y(dn#Says*tozBixr?Y9z=`3A$I{l6v&T`idXNzZtv(~%AS>W5@>>k+R z+&#F%xoc>Lvm>;_*%;p8EQ#!J_D}9`R!;43?wsD?Y@6NTte@NAESlfp>|Na9tXbOO z%wOK&>{{L7Y+l>pEL-2<&cn&cyp#)zMLuFK+aUvV9r$TP|j3)C}*l6 zoHJD%$(ib#%$cf~&Y5bR&6%p3%b6;i&zb63%$cfQ%9+Yr&Y9|5&6#Ri%b6-&&zbT& zc21SMc22c;c23oLcTN@fc20EV`(>tfy zW_M22&+VKln%_CqySQ_zW@+bC{_@VLuGO7W&1*ZS%GP&IaYyc;+m$=$_2dqEyt#ue zU+$o9Aa}58D0i?ulsniE&K)d{t<_=a&=MJ{c<_^})mv?5@H3xm|-r^ScIn7k3TTEbSW1U*0v?wYqDtd2QEV+4``@|GIHc}vBSyrsU$yrqiiyrtIJyrsIiyrshV zyrrJSyrt^pyrs_7yrrhKyrt6hyd}RQf2rJ+ztrN%U#j)yFBSOmm%0b?mv#^3FLi|S zmm0(QOC^!~rT)qMrON62rMB7prTV%2rK0)#rQXH-rJCjZrLNWdrRKH#rLy(>CGK!} z-7c5c>v4HKK9|=w;PO@txxDQmm$xD8@)k#2-o8nfw_@7mZJl*_>*ieE!g-gsXVK-Y zUUqpqS6$wwHJ7(^-R1Q=3cTg60&k0_z+3Ap@OBRrcy|vKcsoJ`-o|i&wF?Vl|0 zR!$dq+hz;A^>YQ@qWJ=E?_zt`oU52FoNJveoU5BJoaGxsFiLTw}Ost|U@4*FRY_S2C+*R@(S*SuCVSGHa>#~sCCx2rhp^%RFazT&WNpg3GLR2*&(6^9!l#o@lm z;&8=uakzE1I9xYh9PU{x4p%Q1hdWn`!%b_&;nMZuu-{P5_2UY)QC&z9ihcSQ4&TE(v$7mV}$vO2TF9C1LI;U30ri z*Swz6HIJ`!%{NfGRy9<*)*dQdYlxJt^-Y$pRZN$zwa%8V)yaIRWFyWb*`4K zHLaJf`5k3z<*u@|7Ejq)t*>mYd!TG>_fXkdN2qMAF;ceHKUua`IbF8aHe0q*fs zZr<(aS#&$9m)(xeRkx#Q-Rm~_&Fke3?y8vddMYM8zKTiTK*eO$P{m|>sA94qQZd;# zT`}1@TQONTUoqLUSTR|>Trt_XS~1zQUNPx+RZg~eDkp1wm6P2Am6N-NDknQam6MH; z%E|ue%E`9b%E|iq%E{iv%E_AL%E_+P%E{*S%1Q338t{6m20Xs10pC#7KzpcapdnH< z&^KK*&^lW+P&Z#S(6d-IP`z9=(79SQ(6nAP;CJmFXz}bGsP*k0=pNcV&=J}_&=}c0 z&_BIdK>hsgf!@X412xOL2f9{w4>Ygu9^kI(MX#rN(c`OL^bJ)nwuh=08zR+< zebd#8t+UmOb@SDWJGF>)>pIGJyf&U5vo~ijMOalPuDEA z&DJc|&(|#WF4rt}t=23yuh%Scm&fDvc|5)$kEcE4@ias{p1x_1r*+ojshjtBdX_z& z&Q*`6Y2D-TyJ|fxzFJTBP_3sURO@Ms)Oz}-YdvkVwVwL*21t zS+B2d);Cl)+a9W$ZHUy(_D$E#w$9hh_AJ-UcCOaVHm%pq`d#(2Ex!8M?xFhGj!^w< zW2Anzf4Y9QZN7fCce#GHYqfs1dA)v?yBb1XUqi?@)DUWqG=%!58$zw~4WXXphEV5f zL#S!JA>?;8hFW}$q3)r^P)DRO)IZ%AYMXBi^)5Gtx>g%Q&FhUJ?rK`~`kGdKLrtsg zk*3wY>891z`KHyL<)+on^`=$7t9iA>*Sy+2)V$geX&b+t#luD)rnt99P%>RI->I@i4}zpusBJ=Egrh_tx+r(0ZY^DVC412Hr=(}HqCwQL%vA+ zP~Uv}P|tGvQ0IF4kl)ua)E(&<>Ywiz>Rs*_>RRs@;=ayhU!-%nZ@zQ6XT5XT@9SFb zj&v>e&vz~Nu6Hf-h|kwI@ALJn`+WXLx37P`+t<6^?cs z{OkP@{>B?`oMQChd*5?+-~76(@3ZIJe)%)6c^{iTa?7t?DZc386K}r}U)&=P&maR? zltEeOcS*za2WLcoaI2 zh7LT34#-0X%HxZB7PNIBd%edv55uZ8x|S6Y>7CB zWyTJ#5bvx_Rv5Cd8^adX6S1&6qZXDrX<-*mSy=V7g&mx+u)J9dd&``Kb4ptlVW~!)`0v;jyx-yjIrYv$ER) zR+c_sWfu=xS?!ROjRvi(AY^4XgsrSQVr3_yR+chpWfx3Y+3soU|HIUofV+)Wci(r{ z-F0`}UD=gg$<3l9_sYty?8>feH_EQ;%C4-}rL?$Hpr$N!TS^TSaCetN>jJSnly+R0 zg1-VCw}oN~w1y7g0;MhkAD_;fbL4NHhvyk)CimJ}-uJxc|Ns9^=t814)R(Lc9ZuDT zR;O!2_p-I2_FQdfPrf#^v``zmUaSp`mTE(%%C(`XN^R&VR~OpM*M;T?b)j=&U8qN@ z3muf}LK8||=#EwwYSrsPyZkv?i_N;wRjV#EY}bWOICY^7Ze8ecq%PDHtqX0B)rA(s z>q3_jb)kV|UFc}4F0?jX7kZGb3w7q|Li_S{q2-0T(9L39XuMPxI$f>{g)4QT8LmE} z@%0f=sE=4;eT0|lBZgcbk(K(0qt!<^y*{EF^%2RekJwgyM6l~4rc)nL-1>+ct&ePp z)ko&W>m%nA^^x9WedJK8KC&uZAGw>YkF@3LBfInUktK!t$hBg9WTaFdIa#icOjhb6 zPq>E2CcYsuTWE-!6&oVmQbXi`+z?r*G(>J|4UrbTA+pnGh%7Q2B3G=2$dKI-Iqoz> z*1HXnN0Ej|W3(Z%E!Gg3A8&|UOf*FLlMRt0sfNg!bVKBRwjt7yYl!U4H$;{d8X`A} z4Uw@@Lu9(#5K$`)k!M_EWFy}gnI$wv&WMeXE~zoHUv7-7P#Pn*w8luY-Wb_oG)5Mh zjgiY%V`R{7j2v?sBkSD8$irx3WNWN3GB4g3xsYg#^d%c3hf|G_)#=8_y=-HoJ=Yl7 zlW&YHEi^{17aJp^rN+pqa${tw(inNlHAOb_O_4c5Q{3*ldbiwVEQsc2nep(-hg@Hbovsn9e0|w^=`BFDB7%Ti#2QW2kBCR+_bET#L4mZ_#E6E!r8eMeCAUwEc36wnAyq zZs{%B4x>d|XtrpVtrl(2Zqbf8E!sM_MSB=+(YD4~w0ZFs?LwkO>r1w1hf^)u>U4{C zFWaKE=UTKq`4(+yp+&o1Y|%zbE!wGai#Anh(VlXx+Gf60nPYWwo7+VVoHcC*;3jh9-r)8$qzTxr#2xVEguw`E14Eo+HwSzc<(8gg4! zR@$ykwyb2fWo@f1E7)yW(`m~pZd=xkwq>`(+Ol)wZQ1jQwrp>*Eqf@{mR*%@ z%ihhkWq0S>vP%kW*=xnN>`19Cd$Qb?ovgHFpK$HjO?-QHw$PqEE4F95rS|Lrxjnm5 zY0uu)+p{~3_Ut0FJ$uD!&kot`+2c-ocD>u4eH3laZi}^N=f~T#7ZdH-{$zXhNUA-% zCf%OBpKZ@}H-*)w8CwoB^B z?w32VE0m7xExjYV!|2E^G&{1Ft&Z%V-H|=!bY$1L9odJ`j_lT0M|NJkBYPpyk?l)% zWDlo0va8b_*?YN;?4Eo_c4?s_d%f6^9W8ZaPnA2eQn%GrP;^%q})NvsbOo?6BRLJ>hg_H@KbI$I;I0_E=|jLA*12Dbbl7 zNOoqAraH50)1BD|xz6mqd}nrfp)-54*qI$Kb!JbOJG0?RXLg3;Ma^$%_&p8Ll6cXO zc~Mq)(b0KPH+WGpdC|6bQLuT@ba+v5dC`sX;+7aM&W-cp`2;WaCVBBtiWgUs{hb zqf1<5c8OQ4E^)~25|2Aw;(E7Bd=%{xx5c`|`SC9CVxmjzPj-n%QeEPjbeDKP*Cp=F zcZtgiUE+;mmpE4H5~s^uqFU(^pK;ydM!s8|C3K5tq;7G)+%2w9y2V?1x46UT78jb` z;$^E_9JIT|V@|iY&g~W-M!UtWv2Jl*yj#4G=ob5u-QwX?x41gpE#Av@i+l3j;?hF5 zc)i#yj+VN`Q{`@Ps?se!<$A=;e2+Ls=n>CJJ>o&RN1RZ4#5;PAxXb7f7n?oeRjWrF zwtK`APLH_3?GYbGd&KRr9&tguN4%8i5eJez;?Y!(xHjD*KFIZm`|>^F@E^d%OVeTgepUt-AaOB{Fl66@W*#G`0m zVq2^)F+bjyxR~fm^e6igM^b%>HR-;@{ajySZ@w?Ftk9RZQS3{MmHHCX<-UYk=}SE0 z`V$-Z{=_VyKXFFtPwbcb6DySd#4Wu)vBT(3EHwKQm#zN9pxvK1=JY4lx&4WU(f-8N zSbt((ygzXv*`GL^>QAgr_b2Y<`V)Kd{fVW8{>1fSe`2)MpEy<7?am9< zl7e7eD+<;~Nw7|q1#7Y*SWmb?YZE_c%@zi&v(lh-KpwPKDudQ-ebCxz3|foKLF{)@6IhI_3;n>)avh zVRXpa8XL0a#fPj5$sy}-YRFoh9#99$op6S&4eqe@I67=?j}2Q3;=|UZ zvVb83Ri}$8E&Mg@gqgQ&r`Idk)k1w z6lGNw zJ3mrfQWz;-D~%LSmPd+{m675TZnU_GA1%%nMvG^q(c%Glw760kE#B5gi#v_c;v#dj zc*Pzq9(P8I>)p}fqv&XHTWqvAKR#N#m>ex0NsSiQq(_VQbECz*`O)IC!f5eEakMyA z8ZAzjM~iA@wD^o0D{kb+inD~V;u&eIxL+PCu29B`xAd{%4r8pi&>SmXw#SOcoU!6M zcdYm@I#%2o8!OI>j}8?A)d9iJ=d9nHNd9jPhd9fp@ zd9gL=d9nMsd9l6ud9h`Md9fR%d9ms8yqH><7kkFdk8Kp@$IeLeWBcX#u@%bv*e!j2 zY=<#Fw$Pj(yKK*o9dqW#*17Xz52N#ATjTR%7n1X1hg0)otJCvi_j2=Nd-C&ROAGU3 z*Guzbr^@qVQoU|ZzP+kz5P!`1Q=nG=Ij0Lg9=7QK&dqM1kvmmy? zT@ZU5T@c$IUl6;LTo5~&S`b^CUJ!ebTM*lqUl3bfSP;8eS`a&3UJwgc7Q|*a$>pOlP4DalxsmW;bO$=IEjj3ouh zxK@&klV!=6tVqTaZlSSBSZJJ;78(cSg~m!{p>bPZXzVl=8jH+@#ua;^aokyGtale0 zkD?2WZSjT1#pFWcNNS<6CcV(OpId0`%`Y^T6&4ydN(+tY@T z`9;Rk!Xo2(X_0ZNyvUfUEHa*Qi;c~~V&j~&*f=OJHYSwC#vOgJvCCX+T(uV)C!EE` z26wUXIJ(%_9$#!+N-j2zrWPA((~FGNnR6{ zMxAmp@o#xW~6?EX&{0m*sbu%kr1)W%*;yviv%CS^i;kS$=DLS^h$DS^jWpS$=hT zS^i#bS$ zOs!V39DX@xvpULmWM74kD~rMyvCDW8#6%KMd-@-2O(yu(~6 zU$$4u$DEb&I(Mb~FuGFS8eb`2NUoF*r&h|V(<|kBxs~#s!bhg!~{k zA@3_p$Tv$9^6Bz~9Ii~rGu*0_Cag+X(yEl9tV%ihs+4Z7O4;_RllUY$DbtWK?WSEn9DSEshcSEnu}SEr7oR;SjaSEughR;TtBR;O;1R;Q-Rt5a%a zb?O8@kFQN#O0G>EO|MNo$gNH7E38f3EUitQF0W06D{E6ToZ@JL;#iX67>eRJ zy5i`j;@Gz0n6BcuQN`I3SDf=n#W|E#oVz*2*vG>zy;wdS}0~-npf(cXpWToy+!m=a{?Rc^F;qY>lsXE+p4Ghtunw zd%5+_p2B+PdTG6Ls=VHrs;qaOavPk@!UpG@w81&3Y;f-A8=PI{2Is21!8ze>a2`iD zINReJoJ+|K&e8M+=Rt0Rv#+qhxmnuaoG$xb)XD~DhMO#F!erT!Cd-C0S$6cvvTjb6 zZF{n8x|3x$I$7QlpDdqGPL>a)C(CzpljYro$?~<*Wcg%eviyXbDsK{|%4emi@&RS4 zd|RI??=+{%SL~_sad)cxC^}W%7N06#Oiq=Lq^HXFb5rHLg{kt5(o}i6JXQAl|K(?# zTHYwAss^y1KwY)X1mM?|@Pq^Xo<7l|NJsvJ!N`}iv)8X=iT)4ci z5H8;=h0CWa;qr{2ah9ZUhN5wfu5r4laki~-rmJyoRO7b9HST;;;|`@Y?ru)wb{916 zT1n$hRy6Jjw~^ZL8@U6@M((!0k=to*NlhbY&y=OxVPokv4Jrl}+3&eG|9C+{9hBH*v?@P29uiCT?qd6L%rG zi94L$#NEqn;`S6aao0O9aJ`Rcl6ENE^{+?)!xjVa5r<0qno+y z@y*<&gJZHZEuO1?v|(< z-x58a+!8&M-V(i=+Y;Sf*b==~+7dlk*%EysY>l3kwnh&qTcfx2tNj33q$+aeRC9QgVCrXnK3}L2i3=UtxRnW@&r$bY**VM$mOj(se`8b;s0o z+tzi{)pa+n>*tfYekiT$cXPVFyP)gWO1gfsqU%qD9r{^mhkiiWq2Jbb=sV3F`W1VJ ze%#%mKZ@_rFD7^BN76g=`?($Z-og(3MrnsWUD=^O6L#unq@DVHWv712+^Ju-ck0L7 zo%+N0PW?i1r+zrSQ@@wnsqZQ5)UTIz>Zd9@^{2uv{hYK*Kd9`|@0h#vtM)Gagu6?B z9N(p1O77B+rg!NNa=Y|>g9^ zdQa|tZclD+VNdQxX-{stvM2XU*qb{e?al31_U3MxdvllVy}4uV-rU3Z-rR-c-rV8z z-rT*y-rV)l-rT9m-rQ4RU+$c=FLzMcm%C%`%U!ki8!M0 zI-u;AZkzk1EB1crxVv9^6yGmhOzxMCr1wkr3;U%TrTx-$Wxw=HI3S%-4oJ7m1JY&t zfOO0~AU%v9kS-(-NQcu0qFTO4|0Jr0E_?y75EF^XWs$yM;r^Yo$ZU zla)isC&J<6S>>5tR}Lqi2}hD= zlq1Po=8@!O`$+PbdnEZVek6GzeI$9Wa3p!XbR>DIawPdwIGQ}C98KOak0!6$N0TSq zqshndqsdF@qsa$_qsg14qsh~iqsbY;v@ON79n-XJ*RRG5bd8m_1!NW&H_AT?cec3&3 zKa3x@FQkv#_X@}D>!suNsmgKtsc^zRr<}0wm?!M3?g{&G{DgfeeZqcFIAPx`ov=?= zPS`WT$&#gx$%>w^XZeNyM>dbYn79wC&H=HS>;sewt1>_#XVJe6hBqE zm_AjyUpQ5|Q94zcuAC}86Q)aNlC#i-bm^RO zx^%}pUApR?E;XN8CHv%-b+S>ayctZ=<@ zR(PtM6YiMjgsbj3;c@(&a4CIGcu+Ve+^n1vW|Z@B$2=dm-ScrbeLjA-a6W#maz6e< zxe&i?UWi|DFT@|kFT^jVFU0Q`F2rwCF2tWH7vs0gi}B0u#rVVY#rVC##rXBg#rRX@ zQv8m2DSp+x6n~t)6n{{-6u()y6rWLS({XLnP21+(f^A-_*ya=EvU%IQY+i9Mn~&0$ z&HIJR=8ei_^Oy<0!Q{}38$GvJkPG2=26t0>#D_6}KP#9y>O#)z3@!AQMl#aC_GHxDBP>uC_Ghe7Vfw= z3y;$`3lAzc3p1{xxM@eZTXB>p$}Q!#drNtgzNOr++)|#ox0Q$K+seJlZRM$ZM|qsS zqdchGQD)q`X}5AW{lvYOew4nKzF)bQe&*g!KdjtOKXo6ZA6FivXDY7y#C_;KsyuX` zRUWxdE05io%F~KJnHBzuK!yQw?2zRErXyrpfNcrc9?17X#tB%bko5{f<_mL=Va)#l z2bcXb%!7q77sdW8{0z*=u%8XT19KBo@Vns?P>zD~B$TV6d=cfWC~ro&JIWtY4ii5g za9J3emGa5>eS*9?<@ULd7UF#igW%6!6#Y4kl0T2}#eBwWjS-55%up_5g}53!q}Mp1 zs6U%A=g(x!hY}&aCK)nnQlXeXmoZ;c3<))*kXcg>#r=7Vg&L{Gs*!6F{v5_)jZ>4X zacfF7>6)@Xtrh-a^Adoe2w92^kf}gk0%R?Kxd_<{;3Ys7V-hkMz-EMu2J#Xhy8*le z$a1iG4#0MVj0f@(Ao~FfNXUW!6EX~JNS~JgSrOnRKz0Op36LcLrX*xbfH4VK6JSol zyaZrSLKX#>l#opUMkQobfLRII6<}CGmSqYuEx@*fj0^G-!oa?S3=HxTAR7aW%-}gg zUIJukfT;=D8enWf)&`iHkiD6L3=Z-VAe#e>PRQ!8c^x#r19=IM?E%IoWPO173E3ZD zfI=1scnOdVQXwPcXN7G3cnL5s0eA_JHB%vT2JBhLpdl{-vT4Amg{+zinKk4kK$Z=dwvcU8A>#(D zTgbd2F9EV}z)OH^oC+B^T33*l09iU<>O!^-7`u?QQz3JQyadSN0WSfvdB976tRC2 z?U2<5W;>W`e(m ze}=pS_TR#vL0$s;S@1KFm%x4({7&R0u+IXY33&k1>6(lC9r!1_Y8Rn>|Vk>MP35C*Kp6N zPDEY;%u8U;2=WrxvxD;z*fWK^1oo`KGl#qcn3uqwN#rH4XBD1V|OPF3GCg)c?s;D zMqWY~c?qm`h8h)l32beEH3E4FZ0&$G1bGQ;ZGklgc?oRofi(zu32beGH41qNZ0&+I z40#D`ZG$xqc?oRogEbI&32beIH4=FVZ0&?K6nP0SFM+MGu-3wwi@XH37Q>p1yacvZ z!tTurf1$haqc7YlOc?qnxff@&S39R;k8VGp_tTuug33&;uc7hrTc?qnx zf*K2X39R;l8Vq>}tTuxh4S5Nyc7qxYc?qnxgBlNc3BfrKc?qmGgc=cf39NR68WMR4 zthR(26L|@&_JkS~c?rPsVl^uA5?JjDH7xQHSZxb6F7gss?F%(9@)B5WjPnv$&5XPR zR!c)ojl2Yym%wUn6VG4N(?5v3M64)6Mc?s-n31>{?C9tz6oI#P7z|N*PFM*v|k(a>EvT&wF zUIIJo!kHI&3G6HkXJX_fu(L9pnUR;k&eAw9ft|6DmjJ9nb_PdY0y~?-869~E?CcI_ zc;qF(yaaZ}M_vNVOJMyD;wKPKf%pozkm-x zya?h);Pnak62zMz{si$T@OlTl3gTA~&w}_C#JeE=1@SP5k3oGN;%5*~gZLW6+rZ~3 z;Bnyd#%3kryadMYAf5;DJ&5-~{14)R5FdniA;b?Mo(SPa&QP@l|mB2>2_+V_3V1HWcOl*joc)3SLOdAa z!w@fq_%XzjA-)XpW{5vSJR0KD5U+;#HN>+az76qih<`&o9OC0pUyt}X#M2?Z4)Jz~ zze7A8;`0!%hxk3j^C7+u@qTbW3wS`p2O?e&@q^&(4?H24iuhB+qar>P)?aK^BF;;A!LvfX74fc!e?>ej;$u-Cm-t!4 z(;~hW@wSM+h4p2I_*}&6!g@4AJTKyV5$}umU&I3=J{a-Bh#y8gG2)BC*&ldgSWgE$ zGUAiL*&ldi#4jVB8P@9o?+ojCk9cUrN2C5V@zaQ>=Cjq|yb$o#h`&ZWHsZ4puZ{R^ z#B(FQ8}Z(V|3*AG;=>Uyj`(rJlOw(y@#cs>M?5;>(-E(Z_;tjyBfcH+?udU!JUrs# zQQw~UdBoErz8>-Rh`&cXKH~EcuaEeB#PcJ*AD&+W{vYuGi4RD;K;j4D`8ePU5^s?B zgTx~wJ|Xc6iC;)OL*g3}?~wS1#6!gMe!xq_et<_jMeG-N*gpvPi^OBZenY@(#C}A; zbHsi{zc zC7vku%L3jg@kg=07Vt^2|K<_D6#H`l-xT|I0sj>HdjTJn^eN(}Vt+8;t788!;ICqT z(IY-9_8$X&EA}S?zAN@G1O6-aH$CFRV*fMX$6|lfBfc#0W{E$G{nda^OT1d_#|AuG z?AHdoTkPk;yaeb0c*MsgU5@y<#M8xoalqTfesaL$#eQ?Z>&1SwM?7EbSHrvn=mB`d z|0NzU_Pb$T0`vd^elYgOJ>m;v|2*IiV}Cv16J!59;1^?mKHwW;|32U!V}C#3Ba(eh~1NiN{QQX4D@7elzM50pA(*i-7-(`bNNqM*Sn;N25Lx@TE~d3HZ~f zuLOK*)L&p;0^?VsJ`?b*QNIcJ*QoCVd~DKTiJy)7P{7wl{V3pXqrT)3pBwcjkNDlh z^G3bOL;Wh?f1|$Tq23kn!ch-nvl4M$0_bG{ZyfcsfJaVza@5}femUxM0pA?;JCFG1 z#6u@OI_m2IKOObKfUl1FVZdKUeKFv(qy7l<5}*g*5zn3Y?xZt*b9`)9MSC4vZz_UlaHsIZ(o*VG+iH}dZJLmNs5zu@B)Zc^o z1vJk9_4;7m0nI-^eLt9wz=c9Q9}00oC?tqJzd-Vt1+vd6P<%Fl=JODBpM_}n97NM+ zAX+~E(DvDfj?X=Gedb}r_a{U{p{`gc)Ep0m1{0xBLoyWVONB!1=}>4i8w%CsLZO~~ zDAZaAg@%ivP*W)s8YqWCot02%oU4iOd`*NCY9fMI6RDSKBE51=q)n-bjA%8HTD>OH zZPY|s%$mrMRTF8nYa;zlO{BxEiHt>SB3-eXNOQa|YCK=7aYC&oh_zb1RIByMwOX4}tBvTj zTDMWFwV1WqkX5TS+O=B0Q>%5jwc1#;R_lt@YR&OlZ7@-*H6&}bzErK&p03qKv$a}X zu2$>G*J`bWT5Y&kt2LEswSjW2)>*05#<{vI&(~!+p)Mctkb zUL3OO#YVec?04$L4!2$$i`I)>v3jvNUM~(N>cxg+z1Wwk7u(bI;%Kg3?8(=Qt%Z7V zxL7YXmFmTTa=qADsTaq&h6K+yBsifVAxI60Ub!LBrZgl*^oB&Y(U52{8xliSL!!}c zNc1}mi4M0RF&1q|bj2DH&GClBV6q|6mug6~ryCNZxrRhfz9G?CXh;kf8xl>WhQvU* zA<# zjaGBK(HcxPT79WTt3BOljpiDyo_wR#T4=O}i;Y%OsnHrJH(H&QMr)jFD)M|&krSGV zg49&(m79ufN>gz}Zz^^hO~n?osW@ae75km0Vu#yQ9E&y;yJAhn=6F+aFxgb>OEneS z(@n+ETvM?p-&AZZG!=(SO~rw7Q?awsR2=6x-e(>1g2eH?GRLY(Ub#8erZmS!^yXN%(Hv_rn`1s-AlC0R$2#2R*jThV))jA#4JMmoeW~VH zd%8I`nrn{r7Vhog9jLu4nG0wH- zd7(8gNUix^xi#OWwB|?j)_k|wnjf-T^Zib1zQb+Jk40PaUGdiZV6rvemuk(or(5%* zxz>D7p*25TYRwOnTl1Zj*8DivCi`qcS&-V~UZqVQ(c9#1vrQhd+vI+yP3~~pPxq$Msw|{oD^243|2bfpUk_ zS?O@bxy~{#be09Fv)rq6mPho?a<|!89j{cdM@EZSM_ig%U=lbz+hbZ2=q*IDi< zbe4xpo#lZ_XL(%UIYHvNUWMmIbe`)rd2Yz&xqg@D#-cpe73aCZB+vDwd2Tevb3Fx~ z8!qwOK!xYVg|4U|bwzuXuIPx~740^=qJAzu+V6Hn$KqYl!DLsoFWnU#&2>e43SH6R zQde}K(iI&Sx^+S7)_aw1eZ=h6hwN^>-|g1N;@$dSvRm&J#b+(4x#H!k!_K9f%x zF?*#UyI1OWd!?~>uQZtKmHN`X(rBSq8ZPxp1C?HBT`VGt@npZ-mmG`t zB?r@e$}TSbDfHS{W{k zyCce2dPEtmj40#oXnL$NnjWu=x#J=BS0wzU&c9p#`U?g!^YOj>x%X_?`~Ug*eknto)$r`}^%jpPKy0 z_p1KC5C7JeC)3|%3}@y8T>6RcO)mas)ejhZy>2S>uZ;Q3w2bs)eroM&RexZ#WpwKQ ze1S2dnfCGH_`<1IU#a>9e>#87)FQ9y8+^ydHcfr!<5mCQpKjbY)&56SAK~uLpO|{b z`>TG!v&Zcz_dQi#;kUnack0tGRsDt6(vhj_&#FGdcm3>_ryk#``VFsadfU|N=c>NL z|M=y1PI-r`{==5f{pQqAb@YGutRDFqy-~C5Z-|VmY6F>Rd zN2h+TVJ7e?es%D#re67B)vx$Af3)E4uQR4M)2jaVy?-;c>ho3q;xB*ob5k>)U<`1k zZRJM)VQT4z85^8wUcYjxFg5j#s;}`g@BP=QKYLvDH{So3Z%#!oRDF)WHTa)XFYm4T z9hV*buc_&^j7iRXk4xV5KU34=RsZ9!=YKZ!>BeVFlLKvTS!1ml{q75`4m6QZ&uLIU z`bEY(XIfsvMo!iKs_KvY;i*>>AKQuN={gW>+mOIlZ|5%x;KL69I&vO5P z1?q}ltNJb9c6E`;-C#_3rgffq^HO!o?yCRt@7^n`-&$DpVSeUg6Y94ctA0%5)ivtD zZ&ZDm*S@h%6}_rIv+pO9>cQWt`ZRa&n);o)RljD_{LSir?5+AX_iWgv>QdFeDHuD{ zj+)0z(*-T(()r!$`hQ|N~#5SpCfZdGecQ)L;Cwst@#+e{^2`%9|P6pJ~>!>uvS7 zj#ho4%X_Y>-omOs^bcpV{X@>;R^TmnQG3?|g67H~Qfn57YzK zs{YZ>9e$)f*iiM69y#+=t#7INNoTK#sQ>d?)mOUnlfR(u|4`LmI$QfiwdZ!#XZi=9 zd9ymHR{f@5(|=igwfRBdJAL`px2T`_Qq_NI7{8*<{oSe$^`$Sqq`q#m*$T`vaO22Z z)!~&@U+PZ_Z&UyLCu|l2^BAl=@oVazf4b^Z<-ZzJM_yvH8<;2IUDLm=e%Gk_R=uyi zQ(Z7n^{>9odbj#_Utu#Kn71MH_4lY>em|QH!8{NBXX5IPi&bCi=Zn9oE?89cw=S@L zTfOmJHe-T$C&aJ4R~=8W*%QoDkv{c4b=~c%@AZ5C^1EtgqUwMB^s)D=fAk|Z!-9D; zCSLo1TL1B?A2xjG_taPJR(-MG%6~}x(L~iBJ8#cN)VKbC&B$QhkN=xXs&7wK{jxW= z{DJz$^{Q|7f%k{%mljq1vwiFTSRMEeHiLtCOLlzhPt?EtK-EvnFH5OkKUMYBUj4|Q zsh5PRzt$B0Ts{5|RiEuY#y_T}f3@nj{dfK^)L-0E_1(TX`j_e_e#&NrFb~W}f1XxP zeXQ!ky>b5&>h-HtKki?={z>&eXH|Wk)ww@rGfkLpcgyO(R{!SrtNz_w@-ym}PO=#&%-i!1!+)z9o!0_C@7cG%qHcJ( z>g#T_3c$Zu-^4Wb>(E$7kqx^OKQ`%*(@05ar)WoUsiX&yXq6} zIsTejx3TIM{@~vh)J3nenKH~P^~Wp!S$+9EY}O3(P_201zo?(psy^an&0kfwe&>bP z3N*zJ-1%2kekYq*!@O8;`|8)!w{KvxY?w#ud)vOQPJe^VxMAL{&;04Xsfm}We&Y_| zo9dwz7Xsh$=Vrd8K7Q?m_X{-0H~#(K)!wJ)10V8x_mtFGv(JMT$vk6!^5@@H-~YE& zU$Q*-pX$4>RQ<`bp1rRAwEbM*Q;z)Gch%QYRloA?ZQobtA7nFqm{;wWe!r}K=SOVT z5A(1sZ2N&a`#mo_ZJ=c;H-4z**Ra_@%=7kVU-0|h|Hx(rF)!RZ$$SJc6eRsGH%+V>N+`#{zAJo``HP=De3Y*rET;MKSNOuh8h7oI%OLU&&N zzv^F0RX_9(|K{iFZ+xcei~e~m6#n|@sz3VUYEAfqKVdVHnD=kw^_uWk-&OTXul&v0 z@Y|PFebbe#b>Z|YRsZz$AJm19TU8(RJKk3xzE@$hnV9GB?9PU8bFAvC{+;aApGec2=1TEicCmCd4J9?K7XuQgnIy6V$@?LBSbe=4)t zRm_w5=W2U+$(yRaZROwF!*6sS4*c5}-qsP`{y{bai+MXYtm+JRP8V~cr52Vd<93)icDZ~0bt_|Q+-OfKd%{a#;Bn14&v z|80DtC%m(#>H{~Yd&70VTlIt2*Y<@sEUNm#4}GXF{G*StSzyfLx?S%NFAi6I;$Qnt zfB2g@Ham=YVuiO2ghvikedGVVObCDZpV_Q2<{!V47sC9xs*n6#w+8(T1)ELAJhz9t zhr-RvU;V-#EDguMxFPV@yT7z7{PNDK&;Eq4JbdqEHv5lx+Q0Y*%fo-U zw(7h8*GW12OMhJT-#_`h9RB+3b%786k58`%f9^M`e*9bI72(ZoRbT!qk(J?{k*Yuc zPx*=P*M7)m6f*Dq!o)3t>&990aVDux3&o0@hMkQ_;u6)>>F|DIWoAF|5hx`(bM}tl5;8fVCXf zbjnS@S`TYJK+S>kFj*}EH3{WB zpjLsJ1^r~KmVugvavxCZK+S{xGgb>hO++~msFk2*!ugr3mV%m!av@M_LCtmLg};r} zVo;M&P6TQ-sM*jD$7(sK=_oe>wI0-b=$~V?Ak>7EBY|2GYDVM)aWB* zwKmk;luv?{UnGRn!oSq;u?l$U|C9GvMWHv?xqIP;-@l${0P zOh`EzI4i=LG5KQtC_78SnUZofaMpw~C*^D4EDC2*^sTb9Dx6s7=5wqtPE#n%HzOU8qU<{qh)7pICE1z2hQSfCP&{bJFCN)o$@+xmWMMv z<#yn#4`+V#@3LM1^aLo!1HA(18KB>n^%9_`K)D|1H9*e+{lTmk0X+%I`9QA%dKTy> zX1xsPX;AJ5dL7X7K>so8g+Nb)azM~4fu0Ham02$ZdMcC)f?f;sTyUN$>%~A%hH^sC ztAU;k`k`4b2YNb`8-iXB^nB1i&3Zx56QUdu^opQog!5NfF9~`|lq-T>6ZD+WpUrwv z(37H^5%j8{XN7)l*2{vP7Uhnh*9AQ<^nbHn81%#_hXlPc=$WBkob}S6r$)IX=(R!5 z4gKY;7Y98#$|*sw4tjRzM`yh}=;={z33`3d^CON0^a7zLNI53x6++Jt{qC%n2t7s0 zH9@ZtdXDIiXT3=1Nm9-UdX><#L_a<2WkOGra!=6fgq|n*?^!PtdZLtrf?g@~Oeqfq zy;SI_QZ5R5tMQCFb~7D9ME(q zHwIb{Xg-*qVOkJqLX;x|tq3$D%-b+62{a|jm4Vg-niJ-8m=*<^6y?l7s{+l6@@AlA zfu=>dGtjy~^P>D2XknmjTY?xHX^!f+k2gHqZ(|Go(BlXo;XHVh)OFji5PVK8k6Pph;5B z4YW$oEHO{Tv`o-6Dfb3iCup8HFPLeepovlr4zyCxOfj#;v{cYkF~`NUR?u829|u}2 zXtFq0m}#}3*-~B(v|P}1F(<~fUeJ6gKL=VcXu`mhfgBxZ#h@8eo({BR(3CNU#DN9n6~s?caYMf;rUqyae;9LHqZgryy5| z&s#9h8nl1^c?{-UgZA$~ug@uOh|hB{7aO#H|9KDchxk4`ryL?^|Ni^(obrhHK0U|x z>p5uu{`>Zv@`<4R`|o2gryJkb=ag5(_xU;H7V&)#=6&OO5X=Dw?cZN7o>QI?*OOpw zIB5U=dK1hO2kqZqkDlZD^c>f#An%ClSumFz*SjG9i0k2VTpu&IUIz2caXrmYE)ukV zf4vRnq2qcS%t;6B-(RnT`RTZxXDBxb+P}Zv2lLi(Kgdvy610DRzX;~D<9?E%TqS7# z{(h68d?oHj8OmAWeih7r$Nelrxl7Rg{rxUO`AggngE{h`{rmf6Fkc?`(_rpAX#f6x zo1uIr?#IELdeHv;{W?Q=P2A6ex%Qy_`}=){@|#!>WGKgp^+Ja7oS^;t^+bkpomg*V zDBlU%zh938IZv!tGL-kkdL~1;Ppo$`l>fwfC__0=te1j3C}{tFJ(ZzcDArpU%7=pX z@7H4)%87#Z@7HTVUKH!O4CO{a`}ga;4CP0$9?VdV6tsW8Ud&LQ6zj(vb9O|hQMQ0^48f4|<%Q2rF_;SA+aLHqaXyq%$ZE}q9Tl+y+6-#@QsD6fm>`3&WDLHqa5`x(mbVm}~5IbQ4+WGK%I+P~jV z$WX2q`wc<97qoxBACaM)FZL^fyf0|~em^5axnJyeWGMd&+P~iq$xsd$`z0C51B3SO z_fs;I3&ws+hVsGKkI7I@7_@)CUlZhov7eKn+%RbWe!nL}`C;q_Whh6C{h|!ziLsxQ zp^Ej8-wfKn-;c~t&Kdia8Ol3@_V4#IgWNOrJ2RAj2JPSPhi0%pn!$c)kcY;8YKC&r z*l+bHAC3K3k8;wW{rmk|kMh#k&-Exb4cfoo@AW7@js0Mca@3&x`~6~%^3>Q*_9#~k z+P~j#_OSo#VLv*^S%dcP_p5`vHTJVT%3Xu@@Atbs%3otYJjh{#_V4%0J<4NaKi#8T zHfaBTzdgujV?W-*{=5g;zu&J9^4i$X_b9iG{eF+~+o%V4l;cLdz@t1jX#c*R;8Cs{ zw0~c32=d*a{rh@^M>%iQD?G}3gZA(186M@nQSb05{|(x|uZMV)14q5YqdYk3DIVp* zQE%}m9}e2Tug7?l6Gy$qqr5n1|Gu8%QEnXd9*^?ls0VqJBS*c+qdYli|Gu8&QLY^I zCXe#vp#A%Llt(#p)T=zoo1>oPQSKb|E|2o(p#A%Lm`6Eu)XO}|ql5PE>uDb9YaVF- zzTW0hJ{|Qqk8*u(sF!+_hX?K7*Hb;p#iQQp zQ9d5De_xNS=Hy@KwI1c=LHqahT#s_|sP}r5pGQ5|qZ~cz#UAD9LHqah&-W;|k9vQQ-$y@yM>&4<3j}$7^b>fL>qoyqkncx7LXh)E zzk)}3fAlkWl>0}&Ly-SRKZHjd0Q5@)JOK1lc*F%jzeT_YKtF~@oB;G|1iS$Ba|GM~ z^m};34?sVNM;rn4iv&CY^pkkR6+pj9z!yM2ibtFQ^s9Kp8$dscN8ADQyLiMOKtGH} z90K&q1Uv%t(|E)sK)+4ECqO@rN1Oum>jb<4^z(ScEkM6dz%M{QkVhN?^b2{!GeAF) zM_dE+8wGp=(Ej~3Dc~HSU&$lh0s5H&?g9FpJmMdqA1dG=pkK-(9s>HQ0xkmjtvuo* zpdTyXB%oi*BVGdfxdLti`n^2jC!in9L$0WYeld@D3g{>Eh^v5pvw*LFel(9b3+Pw# zh_`@#wt%~Uem9T!3+RUnI1K2Q^N7cQe!76mfPOoV_zdXB3pfqv*Yk+ifPTJ!+kk#Q zkN6Gf2lR;JfPO)bcn;_%47d*HH}r__fPTb)^MHOuk9ZI0XY`2sfPP1h_z&oZ3^)+z zm-L7Sfqu$>3xR%1kN6Pi#|$_T=-2d!7lD4xfE$5+PmlN!=m!lr66hE8h$n%5(ts<0 zep8S566iL-K>wu4ee(Zpgfqrf8Vdksg0r1ez?GZNv{oVmT z1O4CuM+5!h9`Q8LPabeJ&~NS$UjzN<0cQjK>K^en(9a%lH_-3y1^kT{e)xdHfqr?9 zcpT`b54arYxA%z8fqwje(}8|{k9ZyE=MT6Y==b-C-+_4mk2oHf7x0MZfq8;}>w$R# zkN6&#M+i6{m{;(K_kno^kGLP0ckqb+fq9641A=)8k9Z)MrwF(pn78nV4}y7&fD?jw z4Uc#snCA$%A(;2@h#!J^kbonCc@d9zBA6!$xFVQ0@rW;id6a-Nf_W8>cq5o+3AiJe zckzfnf_a#LLy~@xm+^>4f_a*NOM-bDkN6~*#|bzknAh=$SAuz-fLnrjACLGYmZ-RNGfOCR*C69O~m}d&OCzyBgh<^gwzuyz}h=T&!zuzS zzu$8X_$ru3^N6#8d9{GIf_XNNxGR`<^N7EKdANYXf_XWQcr2Kw3%D$pxATb4f_c1v z(}HtS(-qIsJ3~2wpCKGUCFt6zmF9!3R0XGKoo&i4w z^PmAo2J@l;PX_a(0apg|rXKNSFpnB=W-zZB@MbX2>JfJa^R5AZ2J^5UacD3vTjkNb z$kTenrNO*yz^4K2-`C_k;?!VXH{jJ^p4TI84d#74;@4mv*dvY&=7j^E4d#hG;@V)| zIN;l09@!(#4d#^t-VNrNJ>uSA-Z|jkU>@2d4i4s}10D|MsRJ$!=B>TEFXp>=n8)^r zlY@EffR}@LZjZP*nD_RUznCB6VIDl-=wM#lBc2ZC$vxugVBS37>tG(;BhC)y)dSuR z=Gi^s?qJ^CBmNHN;R6m2=H)%&@qqU4Yw8|xc`$Du@Odzg?-8d5^ZFj~dN9u)aC>mbzYO_y$Uj6rCh}8}uZ#R;DjW zlO?|{`G(2AOg?JzbCa)}{O#nkC%-@C4rtyJ%|W1f3N)92=0ee&2%0xRb1U%t6wJ|} zc^ov?gXT=poDrH=LUT{B{tD9^7MkaRbwMy+hUV1Jyc?REL-Va@jt|WPqPar&eg|`o z@OcmBE)oC1e-4=!!~gfp6X7$dnK!}z^UNavjAD2O{GZP>bN}}-?b`qSOhfiR57Tn} z&&M=X|MN0!)2}a>#^`?^ruF&Xk7;iH_hs6b|NWT;9?15Pd&wzjZSr6O4AFP+`-yhb~_3sz!t@`(m^*H_e$$E|c{bfBr|9-RH zn}7dV56piaSTD+dK3Gr4e_mK`#(#cTkHmkTSg*o=zF5z|f8N;H-GBbr8QT9W>@4d) zpX^NOKd)Ck-#@m8`|l&$Oa1qg?P>nKVtb4K{=Qh__s+1j)_=d*n&-do zZ0+&ie}4@Kh4BA>3jaOad-(6+-ou}Vdk;VFIsSaO_wf7R-ox*Qdk>!n?mc`yxcBgR z;oigNhkFm-2kt$5Ke+esec|52_lJ8A*8}c7TpzgiaJ}H(!}WuE57#q;*B9-4W9v@N4WR!e6r69pBbND_FdpR;q%SDD|}~s{@JyFYl80wyH;?`@cm)e z60Rw}U+h}LHOKdl-3z!U_q$^AQQd~?Pf*9=`V`dlbiSZ-4z6$PS%>e7>tApV#`Q7i3*h=0^hu~+LwzIaU*UQj z^z(4N4*Hw8o(KJ2TUuSFQ%2l6A}ei`^Pa6b+FD!AVU{vF(p13we2)$qRJ{vG(taDRV}`~9bWJ`)Q4 zeCF>$Kb!gWnxD*^sQvNG+`972ck8}A^B47BpP6YW%xrJ`{0!gp>6w3O`uNNTxR1#tSb$#MlP519S z%XQB@dwb96XNP;k&xZR(pZ#0kPo5_G|MBVdfz;Cp;iab);q24rgX^BYX{ht*_Tg_l zX&w2?Ctn!(l_&2UJ^tj#*up1+8ULHdzbpRw<1@2PJ)Sdr{^M`W{{Ev6&-sf- zm*zfwB+c9Os5GzPQF4Cn;iUyHJ)AG?eE2P?`QZl_zT%!)^k#Q_vF3hd@lPJamwfEO z;icCebS<0n;MHaSbpI{O-+q6iyz%}U@{jI)e8q?E-B@|}-u#LBd;dD|(Yx@N-YzJIZ@+cjPi|@J-*@W=>o?x|(1w3=j!gcd(=;{5 zNl(3e(^gO490q}MVf^6i#Qs}nKfnLK&Rjll^Gxl**R9_^ zXj>D9zH$1qho(r;el~XSrG5kOM+O&0e+W%?aI6ZO5_J8{8R_(!? z{%`xQGoSZ=^Thrioc#^smj7wKe{Oo;HUHC<&d=I=&i}Muz3_GalZSVI;o|#tZS%j) z^GoK=mHxN;u-&<1(Eqk?^}qGcE{|-#?q7wkT={$dip<@bzWQj(T>mQlnt!$a_u8XP zXZ@@9+3U0ZA5UKbPG#GDUoxa9l9Z@KL`ley6e%egUqTwpA#>*8oaZ^mJY)`KY>+WS zQW~U^q)e$qq@tuzqYSD4-uM6a`L4@*y}jX_=f3w|Yi;&g-}a4gni+7aQ=TGPHgL+f zz3Sk^dA5eb=?{7rZrKjEkq5Uj>65T|AKX&qF)4K(xHTKNy;@&R)%kFnHgKyK{RZHM zrIq)=Z5P6=|MZ`N3fR6e5vrj#pcN`ZaDzKk$t9?k$-sW7oR#Y$po*G<&dTyaRp~=@ z#X*(b4=$GGf~wPj>SI6^UWRHM4S5TdDY^O(RB0+yYZFxMc<8c~vQWj=P|dMW)mNap zhr;xhFNA8}3{`Ir)gK34PzBx44P7zG7=#X4F02LJVgp@6LHFcB7hQvHdJ0|jm07ls z7rIOWx=kIr&JeoK9=gyUx-lBMG84M92)eWuy7dlpZ98;t4|MTs=;rs()nB2z$Dqq6 zq1&gS>;HfEtN!~(dHkKG&P`8JeSgNNMSs3hd#2t~^yF)*ZlZ@89dD0h~zcTNAdCL6z`5II0b1u{8 z6U8k3Xv2K-L5nH=L7Zv%ev*+o(#>dnSH<9Y7st>Uwr4QjZf4ZIS;+V~G!(XR=t`LT zU~E{)YwNJ#SF&M}uf{`dUp9s24Wx$lzc>^s`a(K%fB$GmR^R22XU`cSBF}X~EPJ^^ zvU=_Z_dbgY7Ja54e6X80IPYn5(5ojAL6T3jgPb2v29|bR3jFfOJy7|PWMEKdZ@|rt z!~o8Y?E(7jKmAkM3jKRq_xVe-a{9YIyy$oFfsNl(%X~lGmRjHB`!>FP%{;y`&6US| z@9jI*&@}18-<0QLeRsQ0N#mgR_?>WXy*rZLnYV9yjoh;F(zrF{nb45oIdF5Mr{c{A z9+CC-9?x$~xGUU9a*w<&<=%I#&Q0l>zFXYY{-Z;69!E9nrd>0xB)ERPyv%j)$F^WqDqfocaQ?dlQ7(^c+{oK>R^E|oqGtrg$x6)Sw~ zGcJ6yn=bdVb1eU4+gj#gt5P;(lV5t+W?t#D!~P{EhX;$B4;dG4J5*nE>EOB|*@M~V za}V&H7dXHuWLuA(`?25toa6rPvrnw{p4G9seWuD%{fxL}<>@$!wWojWJ6&MAPpsg9 zd1k({xln$#S#lnS*@8UR{}OZCP5E<`O%ro6O$2hLjMK6Y8;fK&80DOjFj{?zWmtUj zwZX=dS_W6M^7iUvP3gB~TIui4ytHRHW8og(4AfiHOPA8^ zOAFcQoz}U7J8jL5+|&>qmDKj_9VrsqT~mCuIa8Xn3X(;%wk5l4>rblN8kWSfRXoW; z^JZe<7Q4jn8eECm8l}e*Hk%ypQ6Eo`QZGpGQqxbkrus9UQ?(%8P{lAlW7AaJfO2V^ zw6b-ar_%hmTE&~OQyYC^w{Mh=jaKN7Y2A<(Be-F2%szRpn5^{;(f#W}qgSp|kG7K= zi#jV?8})Xrf0XoEwJ2wq$;e{q`pA(r?8voi_Cz{M2}GWk?2UN4`b>o6YL5sz35|&S zRXh>>E4#y&ttAOCcZnoLrg4uzSvi`-tv2FwrDQ9ewjaee5o;8d8sVhLxhW6 zykw9yD13{xT)2R>Z!yhE6tZXCU!=>Ly-1F=S#Tlin7|laws3$RTF^`{UvQB&`S=+<9BH0Q54TJvWv?f2s%UH-k9e)DaB7W+0vn}1!%IzB4Ly7xtw_4l(qOYJkw z^7&N2D*bqi_2$DMOZ)>D+w#3EJ9WgE-TKa-&GRmotuuU&&3OBjUH3*T{O8c_@Qp(O z;qHTl;U%xT!-rq-L`c5Uh_HR>5s^1=CZhjEZ-nRzfyn*+dm^*?*pbhk*GGyxpNzEZ zRg22%@sH|#RvRVyY%J9jC^|nsMNwgZqyFM(4zxd#1{8Wp6f^JJeLh}9bguZ5z<1)>q z$9?Z{B{nqKCGt1jOtii$o>bBpmNb5+KS}S-w&cv)1<50~I8!ukxuzsEbfgU2R7q95 znVT9}&z<)ChIg96jlQ(V>w4*Z*J{(1u1TJVyPA4psE#8;v(7goWE&FtpKn`bBVvb8Ce{O3UqS7d)K z`~2uRzVnPiMj;>kTlRVTbL-%5>WlWCHHOa|ELK0`Us4HQz4ml|>1p_GVg;>bneg3( z@~6v_;nf!8DZ(qaR`BP#R3^f^5y&}Rl?LxlBzvGb2j1=KQ!C(|->TVo((ck#cp9Co zqS`iiy8W47FAu}h`odFlWDM1%!YN3eP=XWbyQY^OdA$!#$s10KJ1w$47fw$lb>L

    aea=fp39B!=uZcjg9 zs^ur#W&zx)VY~#~aBpiV+_p8``usRfsDPUtK2QzPvC2>xUmm4FmF$IT;fj%j%6au9 z6skx)`e64MR8=ihmp@dQT9jq)Bvf5JR396va1T_YK%^*CX8(&bP^BJFtr}3ZJQ2gM zx}k~-p_&7rs&_+mi-p&{`3lv352`*Fs^1^Fz!=EE)MmICM+8oI|G zx=0tgNe;SdAv=+>>!wTjTaGSI~< zpqrOKS1*L_=7lcjf^O%4uAfE!1MbK9e~JA+DrRBJEbEwQYNdGU>_^8Ysb|s$IM@>K zLq|EOIf3b4sbT5Qb8bC+PaRrznbWQLHMMCL#dSQohYIV}~4>4wZMH zm*=8GEp=+vnYou#i>N)xM|p3wXHqxjD$o0|E}G(UnVLr#`BN(8jq{UK?Wx0$t?~t8rPUl zmdsxCXJ0PUQ{et0i_H|XsxMI}?TrnyI$+=8zm{6e$d}87-=~Q)cP<_jF3Or@a0wMJ zNj%cc80hs7`8{357&)T6RLdrgp;@%>@_vQPA8#+m}Q=u(}9j8P@M<<;#& zVMp2X#iV4egw-T;h`rbw8}`;XP26~^b=Zmr7Aw9?$%chaEL*uTW;|51zkg-YU{k1= zcmAr_`Je%7>?CsM913kZC%M}Ap>$})_P47g9Y#Z#G3O=EKD-=a8R#r^fQu1wh;Qwh z9s!+@THTQ~7rtR%Ugbu#eURMz^JB9{WEH1^5&8Mz1A&lB7rZzCDF z!liXX%%0u=`~RX93Kt{>*fww9s9Cu^z_4j*&p2&G+jSYA$b5gXrKd0uLr zjXb_pX;SLvxhjvP{q0eYSikR>(u;)6yJ2d2B(JT}wLZ`1%9rmNoO8GP$gU{da_`}w zxA!#*&A&n6-cN7yY&|I;>0PK)w>2{Dw%7XkF59X(Y`m`Q5z$&?Gv%52sYxrRB*Rnu zyRY`1p^cuWtR%KC=6~SfxT1agq>Q~s=k^etsZA5^D!13{5K~EV|8%NzhpnuXyGdKf z&dx=3ZZ|BXbc4R@yCtc#={mObAC+dP)WOhc%D8p0kHg_V znI`44zuTv`Dx11a`q+CuX*bzkeDBG>=i7JJ!=L~@vIRR3f~s0bWbH1K2psbID>e&E03f5X4S&%w{dufeay z?}6V7zbAfgd<}dpd`*09d=L0u@IB#s!}o~q72h+ycYFqX7JMdrHu8+{toY3M?05!v z7I-FjHh4yOR(NK3c6f$(mUyOkws^*P)_CT4_IL+)7kDRlH+V;QS9oW5cX)?*mw2am zw|K{R*Ldf6_gDj13s@6a8(1S)D_ApFJ6Jb* zt5~yGyI8|m%UIJ`+gRgR>sa$x``8263)mCb8`vY*E7&vGJJ>_mOW0G`Ti9dRYuIzx zd)R~6i`bLco7kh+tJt&HyV%3n%h=P{+t}mS>)7+y`-lOE1&9fV4Tuql6^I##9f%=_ zC5S1AEr>CQHHbNgJ%~YwMTkj=O^8v5Rft)LU5H_bWr%5rZHRG*b%=S0eTadGg@}oW zjfjzmm57;$ors}`rHHABt%$LRwTQWhy@&4|&6)ri@M-H73c<%sEs?TGP+ z^@#b1{m22x1;`1=4agD5704OL9mpZbCCDkrEyyv*HOM*0J;*`GMaW6WO~_HmRmfS$ zUC3d`WyopBZOC!Rb;xjmVM6mB^XMoyeicrO2tst;n&+waB^1y~x4H z#mLFX&B)Qn)yUb%-N@m{<;dyC?a1-S^~m|i{ip$gzN-GiKffCE_=|tPw)fmLe*X5S zeSh%lm-R0CgWvDW@SZ9B{ty4rllXe!(sdK~`qvMRj^q2WJ10Gk@6YMqq2Ks^FMFLB z!}q`Ack3^Fp2Q9D4wU{!h2uveAm7I`x(zWWmN4mp1-k_&nLVOquA1qct0Vl-h9COy8co81K!`% zC(HMEpAyokBY3|eCtKg)eK+dyyurJ@U(=hSFR-3j zf&2ThzKdhB`mo;5{CM^p>tFwx$aCz6kO9kH><>QstRC!_XS;fzVgJ-7iax`B3f*$B z8~f|8QQlMRx5W=%J;DAX@Seu-AZk1B@iL&TF3uZs^5Uu51+ zwIJSnda2uj_;bxJ`99*2iF;o&;*Rk#^hk9hoG+w&WU&q7WLHxREYl_IYre(xyhyM}n~{Xpp&;(JeK+*QQ;WkN%B zi2skaYStkiWG~COg8U#@{Pi;OMeB#Xmytj0hl*;EPh8SCYmr~P|JYqZzTsPSs|NY! z;lC9%$VXdpnHQ0tMkWTTk*^MjXjdbDiTyrZg?x7L6lWFk+vzzjmB@E)%B>a1e<|w} zE07OUK4)A&ejEvzE=Rr;c0D?&bZ$<98H{Qg;j?>zGTktjwX^1tGP(Q~K)%D>p3 zLk*z(tNSc!fK@N|o<$ANa^dzF)Bxf3>Ss^`ocUXM8Z|&b_}bH`0SvyMEdprS7I*e9kajuxu^k@KPKj&2JmhZ$UzOD zeLgK4H9&8GNH%H!5AB>&r~%eW-`23V_pH48Psj;}gdr~&pB zw`HORVA}1^L=Es#Y&ZioKzg5V25NxXJdO<100*2?PoM_KR+T(~8X%g#HXSv9!e_m7 z)ByS2eQBrx-aPP5Lk+l8X)kpbS!Fs#|8Z{r~#y^(_&Bq ztQy%HgBl=k7gr2wfM=}@(Wn7Fg@#6>1~_c49*r8{vBg*vYJe}{wNa=6jQahfPy?je zszsp&_)l;$5;cI#XniDVfOC`VNYnraH|>c;4bYz>5Q!R~YEy3nY5@B`XChDo1pM@f zKn>t6t`UJ6pd*kc0yTgjXLmSifT}x%;iv&tUkV6E4ba!KI~+BDk)l{QYJidYuWZx+ zLexDrY5)!YTsCTeTLu1X)BtlijM=CGd``-;Q3F^xbFonaEO8%Xp$3>;e2aw|z?)Bpya12k%YdBx2%YJke+ z7irW0-YvN_Y5=-Ajz$f@|0IY;4X{Jeg+>iv&|*cS1~AOgr%?mAmTsj{1Kj?hNTUWg z79>NX21r+5L8AuH-n4{94G`nDkVXx_7~rK*18g|XMWY5N4CJ6u1H8|jMWY6Q|Izpl z{4;6*{Cm^@`1z;-@as_n;P*offZrcA0KOh-0DOJa0Qi1T1K|5Z4S??#H2}VU)ByNA zr~&Z#Py^ueq6Wa{M-71Iff@kM2Q>hm7is`JKhywto~Qvf!}$^o0OySw0M8#a0Nw{` z0K6a60C-=h0r37%1K@q42EhA84S@HJ8UXJfH2~HFY5=Sc)Bsp7r~$BkPy=8+p$5SE zLJffRh8h6t4>bVRBWeJwPt*Wduc!gAeo+HpJ);J|`bG_a^^O_<>mM}$_5*4F><`oc z*e|F7uzyekU_YS-!2UuFfc=IV0Q(O$0QMtl0PIiH0NAgn0kD5j17JU+2EhJC4S@ZQ z8UXtrH2~rPY5>Fs)BuPVr~wc^Py-;IpawvEK@EU-gBk$w2Q>iV5o!R$C)5ClSEvCH zzfc1po}mUnd_xU@c!wGQ@eefs;vs4P#7EQsh?l4V5I<1^AfBQIKzv0FfOv}<0PzgBk$&2Q>il5o!SBC)5DQSEvDyzfc1ppP>doenSm_e1{qU`42S!@*!#f zCHfP9M@0Qna+0P-;>!z z><#P@>=o=8>>cbO>?Q0e>@Dmu>^1B;>^_zNJ>`m-Z>{aYp>|N|(>}Bj}>}~9E z>~-vU?0v)l!~($c@O6 z$d$;M$eqZc$fd}s$gRk+$hFA1$i2wH$i>LX$j!*n$koW%$lb`{$mPiC$nD7S$o0ti z_!9u!!NENk+(p5C5ZuYYy$IY*!0jOX9XUQB+y39)7x_E|IXh0TZq923-Wj&Z7i<2Ut<>_h#eEav>6V&;6Ou94lSFVsrT&y*?WM=Bh) zDlT)rqeeL2QleZ#lmTp7P+TvmYOWX55Z7}`7`89;xVxzk?#EO)cPBMKcBvjxIz0C& zf1W0)i0oB0Q1j>BptjDfqr6~qdD*+ikr8TQipAhqr7LS9Nv7Yoj04B1sfj9 z^U^4%c}Y~}ym+dG>|wDf`T0!BW_~c00-GR>^S!BG^W7*JK4)q_Y=^}29ir;_tf)~w zGfDzBM$GtkQ<3~Ts4M(isrO`WONlaEAWu;XWT|1Qfj9zTatXr(d{6KcZ)R>0C z8<>=^G_#8Ai!EjfE#YJ8E}6p&fDM`ACEpmmOGX&;L|!s9VQa=iq>Yg;(#Yr(xyImt zO&aB;MGVKKxr~gZ>5OKwUq&39DP78up&-uZf50uM`XmUC9+zPIlQohVrj^ z8MseyAdB4%taWgr-UahTf4l8v29myBUX?uht2TSiLFq z64`xQ7Ah<`KU7z8IwSzLj?PQI4(XPB9Ks{j6ru*3NX}BlA(>LALYk%GLw=L}IL{EP zH8vqJYfM7w$gZ4n$Wm#kkloV4AwjUkR4hFf+#~%im`A23SPeFtoMo;CXUdcWH_Mz1 z9wYm7A;A`Fj|NArwGOT&yLB4D!m@I~J7t#z`@vS!S=ou8$Fd_q9CAHDO0X$qCwDn0 zMecmiEx8jxqh$ZiH^^w6eGp@vY0w3-i?<!7*P&)mOeYstp5v-^FVF zzB;gx=B2jBH%Cp`_ko(Y?{BhK`0bdfdfzdodegBovSXNajC(Wtn9^pqV>YnOmauu- zv8$V9jty@XJSGGiZrU0{KJFT=J|{J5eeRJx#3-MYTfBS>wpjTD!6sbc7FnN1TNe3D zZ<+L#gY7sA&4=FMnl;{)n%UlcWLMG6TY0OQx9!#~-U(ZAZ*iXYo2}oy1hzf*(uB=A zmu)3pY1@*$8ny*`eI)ygyS#R2$$NQfE%rJE8+c7xgPz~CT0F(ID?N9^R-Ugm!!uvo z!SjK(zULU(c@*(9*gowMxP8du4B3CI@|f73;UT3H=3xvQeIYu#JqmT?Jvw!SJSNFr zU&S;8bE*;Pl9l?KDAlJawIR8%aBP z8}T@0k$uk=$9G1hjthJ z%nqk8~3*k>K z@LxZXUDrTB({I(z_=ARY{tsMtL%kW^MqGTA^Wf^th(XdOdNb_ zxg0iVx52x#g?Aec@4Are$xgtNJb@>wgeSwDStoc>ZFpi)i(0Zj+X*L81}72;Cxg4R z8gNp=`wHOH?vTCOb8wPOI8iG&S=_PZH;;wWE`?KnNcL_0;UYFfsFGx;mMW;4 z4zjoV1S+W5x3wL-`q0$x_mqOLGkbT}Ps6=n5$lXS|uz~CVRmz5HEr6D- z&`~VtEZh-RfKKDqcZaTvCHum0(1~`?k?MP<$?otlbm|T0*fi)|+#}Y8PF}M6E_C&4 zvQvBtI^7#OewUspC|VCdfmlF;LO_MvWY>5vAce#(AwUfU*uvHa6gdKD!U9yuAv?&E zfHWO|IE8>bxQ}cCNVI0>en2HZvYT88NEHf*WwK*{>?uzIl63;26#}y1&ayEeos>=n zpk5W(Up@m!7zl`Huw4W;!Z!j+>H}Ij0BSPGUh{51QgQ7TK-EFA<9rH`))NqSht@9G zCbt0;4g@q#22?H~yU&_{)B@YSd%XeV#y#i+Kyq6^bmgsXWGA{0kiHTSKOB%B_oL-B zC%vbE5gq|E;I4EKFogjy#>y>GWN-Q&Fv&?^6n9`2+@TiI5Cpc70oK_D?6VJ8$PL(t z4Xl(!cB{*PshGf6rt06wp7n2FvIoFuIlyeVbFBkRw^%I>Sg(NWUnc+)+5jUes*aIe z>~3JnVqnZrU{2i2Ua8^-Y#Ix!nn!lDU4UsdfN}XYeI@(aRlvk-U}SUU?PPa*9GLn6 zFm?_wH|}w31Ct9XwF0ZZB0Jqt!1PwY_;QLHV5->;D!?4nfD5RCP_pYSw6OrxLJg>f zdt~q13Y3Jb!ry?Y4Fcc{fZvgU((nYup|!!9?1K-25~%@25&_Btcf+OSn?S8R1J&}L z?1{UAlF%sWtRV`L9K2$bAz zP;^VBmB~(e9VopRP<&QvJjs6gZ%~5Gpa?TT8RD+G8Yo2`smGuiUz5G{08o;;peThU zmw~fF8dT;cP@6iSI*rLb`wvi}cR-P*f-=S3c12LCvn0wvwO%EA?w+7zw}GPNU-gmf zyqAO04F$!kzfv6B8?vB+RY48wfGRd3yYOpP909fL1FD$;>NyrvbULW%0#MauWJf*^ zl(q*bZcVWsvM>J}lz0g!@*q&=xI4dO`7%)JQlQ!u$R52ZDEU>QMxg4g$WDC%DE$MV z_~n+-WWT-{CV>o?2pnNDz+HQerPp9uXoRVujqKfP!Xzp+uN^ zPLTcm448x*VIopmR6}<8J77}Eg^9@xCMVqMpDWl8)6@`5Rqx4;zcx%-3k0T_FJSV* zeg9yX#Pnby6JEHS?EY87q(;HSX1G9!_yFF+BzFZSx=5Jp&=VlRZwAwz6-<4Hh(BOI zOoB3eZZH*k6R$uDOo}!zG0M+p6W>4!Op=)}Q98k7i5`Mk^Ri*u%!jG-Eb$Yl!z9Yh zTLDvPHSrdB!KAtsCf50L8;H-K2qsy7m}qr)9um*N08F~&F!6@KQ35}#sDbZh#H$hVeK)oH z`wnW!_pQXYaq*iHMSqj0jK0Yb566eE%c;7r!c^4Pg~ZRX`s*C(+vqg2VRVd%-i`yK z@0qfrL(Jb_`iajY{YwYa{>y#l#xJ*t=cDa&4Kw?58PoOiIpY7|{(OS@>g z1=0Ex$mIXz#q9s+Onf0hA1#@BAB~y9AN7bwiV@@t{P%;bd66nFw3+=1Um*Q5uJO z!cvFY!t93b5O2!A!LqRS!Gf^d!F1wN*)qron>Xka_Wbn`;#moLZ4{>WS|@DDYgOW3 zseL6L7V%0j%`7!kN%a@@kFT04ZMd9Vu(0>Evq3r|t#N*;I5D~g{ATX3~ z;3)CCl)W$x4Sk^#y7$E<;(hthzby1x|NPL{{^=0(!N~T%4jJ!z9CE*}iFjgM`ieu; z`%Z<-?TaV=n4;&NA%V|rLiC=S5UWjy91z8tm3?*r#P zeiqo<)kHixpbzsUPy+Hd%D#W|P`A8tJyYp{AQRl}1^zrC- z-V0dXSrhQ7qkwpNk~%^I>^fWmlse3bzvpTDhJd2>OIxddL)%s2 z`*CPX@mFbM`17>65)V*W>vn%etGvH)>oVd8`tk6qU(>@rzs!fte&`L_@-WYj|6#1( zs|S9>Clv8O-_P=ail6L*Rm3yY-ZJJ}(DKUHx8=u%?mK4Q+;j{*Mick4j%(z(kgd^?c%nQq+L z<&|2rif?E&1sKAH-|jX z|HOT>%A>D7!=tJ`jCi4}>vwx7)XRHt)e8|{ROO8U_lO&J-K}qw5RVk+4L|qi*Y~?u zUe_XiDeLRJ?i;UvapSuF*bTi?)z@;|qOY;s4qiJ#d{lF6>__Db^IuLs%)>` zKB{`P@F?HaSmLj`T4#DRsZQmnQ{A$o=(So@_uBRSmAkGDSBi=6%KeI$>y9gCuFI~d z5)W4M`OY<$ z*v@g69EoRZ^CeklflKq9M`}JFLH|}}P4yA4nzSQ&HU7lQHFk0Hk@kzCN6ugT#yb4qMp$m%k z^%n$*Z_N8br=9+VDm%#wNyJ0;tlY@1x?J8auAHCv$+ne0v|U$~cM7OrY$J&4}^Ty;f9j5!>3Aoh!@SI zME>x)lKF?ZOWq$sUs`=};i0VJ@I$`Ew#1_*SG@cXck#r**G1h2(XWhB^%dj)fmeyx+-FL$1WhB z-+W*GJF`vsx6ROR_dUpEHr?QNCPk9?%JGGm5`xvJt3~f$5GSog*Vu(J! zIj8m;zCEdEc<&@H@%+V|tTS*wnQUNm(uMf{7M&C^_?b1jw>#_JUi1QHXZi1CWEt$W z&5|O%z%^N2`g5~N^gm>>h)1w0Q$as1lUqL^^Ti(Y3usC!Tho)2i6_!A zsZY}&sZw)OQn)7iBe{~~G(RU!Z|P2av<1DAMTtRMk`oQK1ShT}zDfPWdm74#CpE+p z-HC_t%W)x%p5w!tZy&$98U2*$$89z_Hx$Nb5kDv^W>DTMrbhlyOoTjo zLp5Tg<=4jiUcV&f{(AI@{)l#6KNzjC{!#RN;u)=ozOXJgnz1e++KBi^k4BHm?T@}C zwh&vLY5vdaBZMBV1lrW2!C9x}_a~1kr-t%}&TYHcee5@)o$MM>^wHj6n~GMm zSBVy}N0*_eHjSOIES7y>8O4?({#rM7^HO_u#!@S`Bk|hmvN@J&vO7hT*!d#pyIsZB z6cJ(16IsCSU4kCmKdgWyKUlg;KC*;}AGeoPCH#m*3EyWK5^ruD>%-zIR^8%aR`g=@ z>1MGc7bmm63&pT*387~>T5jg>37 zk>w_czFtYzTtP8bx4;tCIRW(e^0KrAI9Lk={?IQLqTlx`9lY=Zt+((EElj+>J#_Vg zE}B}`2d=XG^#99;9=4(NDaOR_8UPxp|G~Cv(wT ztVesz-9c}it4+@*K4T5Kh)0d~=h;N-5YMp!J;1%5F6Wk|L%7j@yoMI$UQG{it)i>B z(2Fca8*quzqFhVq5l-|aFQ&se7tyAig7iw_QRb(w&EcbC=FF!ph+law{f&c%Zs6di zk8_}RnUh}2F^3+TJ%_$K8-2{PX&d;E2S4)^tOB5?IRic%;X?^Na6_OCoQ~P>;R+w< zdgS~!o9_BMn=Swsq{rVm^cMKw{mV%|183y9X>R)1G!LykJ(pfU{Lu61l0STO;2(Zk zmw2NE=~q*W=!&VubQriQ_e?FNMW#gQx07OY4LB|7$yKz`P>Y0xEdWdu0dN7U$r*<^Y;$=&Tl+0u$*j`Tlpc((p>r%(Ozrd@vd(W=CU&7iw}vgm@JQM4yGK{bCS(er+$(>*`3 z==0zX_4{##*7;FH3;Zaj2f#5}{{0Fa^8E(A`}-Yw3Gr>W(HFmU(e$?-+K70#-_Rev zexU2Vex;+pZEF7Y554*;2kYA?FRK9@sK-Z_unvrhv1CUjS--)Rdhg3dR{9q;mi?D) ztc}F;ZNO^#Y|hI5e1PRj{NG1e+@F0|Pd){+&VZxU=Ti(z>r*m||5FyLA6%}bAB$N* zAFEh;AM04c#3O#6b@9U^7X6`@Wla3yA6cK?|6pBv|A!R|4q40h3)s@{McBVaRrZ`Y=Plw z_RF_7*cITyWxVZV8@%mfFMm7Ceh<#vx;Ino=r`Qq7HyKIj&n3$9-GL3a3-!Nl-+gD1nEgVVR-uoL*Dc{oh<|-By!O?X z@Q7EF;bz3kzBuCh%T*D#U&=?MfJ@l+<*o>Ymu3(}=tePUNgU%Se|# zr%3fazsR}7ADQ4@OfpV9`VYzM!xIqi@ehNAu<|V%$B{pQ8K+tqsDt=qV9vU zIjd(^luM6AlzPvRC|=^HkBlmLb|NbHSz(ku@zys*edvA~b-jByDjr53C7<21UT};ZO2Ql`bGIll z8l3Rfce@ie-2I%$ahEIUDY)ZH8aE|{H5w$DG&&|pk*tFBq}Ds-N%?o~Ci&jM+=5?8 z%kS_fkKSIB+z8J4%-a^p?zg>?wQt8HFD7{gSCent>Pk+z^)cBA9QYcy#8VdBQcW3b zFiE)ruKa`sc8YC7PKruHZ3-{RJQzu-xyg|lb5kt!5XnC~Qt{>b_( zsn+#fsS5RT(>GpU zpUy?H6CBd3uQAi3uboUkNOBZ9)8}6Mls<5k=fovQ5{SFH?S$=B>l3P115WUfe1(b= zSL+^}NU9q?;Y6|)R%9%y+miAAie*Lvq!46WNzQP;Ql7EnN=wEvlEJ`{*?f6rX5MAZ zOn;Kc5Rke0a$4p@ZB=F`Bp4Lce#m6j&dsu@U6UnGavE&2`YtiDYA$7G#X-`6-KFlV z&6j>=30zuqas<*3Zq*o_%&c)g=~WYVQjcUg+&ejT@$Jd>i*rt$hm-{7MeS1-7i~^$ zxX3ugO)?&?ow`!pdn&1V{FF1vdr-|@TD>p(Yn5Mi3nVO@uDX~VQq`4hR`o4=9m#>% znDe62IOlSuS56WnF}PG#&<7CP30eeR0x%_tpx&QHU%F_>4GLmipVc*EC?xmTVP(weOiI!Pw1b1TjGAY zp(OG2DM*y?FX=jMQu6ckx{@VlxJfRB^_lwOurpc3`Dc7dM#Y;ma>d+dxr=4bzJ@f4 z`XbM>@DqTuenpqgnvm>@iL*RKV&{g=Yn^L=)Qar$QRf2Bmz*;@-+E4gWLgLnjufgE z-Yv8)JPq534EU!t{7Du5s}RY$P=L=ggRcmLuf*Jo2KY`x=f%$P6iq-fMmN05C3v+I zcvVl5hw-{d7Tyi_S-Ijjkf3oJ-eo?#+c0?7)+8r`8=hnxJdp`J8D?gjf+uZ&Cw^O^ zPx3Pq;3Ul9L_*+XFiWEePU=Ic4V>CmlB;n5PLc&DS_CJH85`fr0^qdw!KrT|c^h$X z6V-4d&&sPI;UgJt$s2CV7;a60P*L%4N$lF#v@;tNzm zJ5)slR7WCIi5FChF;vY)lH0KkD#;8gDg-JEGdx3DFdq22C7z@SL-TZBQ+IJAOO(78c<;y$r`x?NHK8r6QD*X zq_ETiikt*AVFIc+kPH$oK$?w!IM#qXm`73xNc8;rc|fIjl1*X_NEHEyRe3{#0pB@ zpsF~@IB^1`O##HcaqB9i$rJzz#{e380V-RN?2|@7>e1W$$;$z`F$cvLkUSp{z4cBy z$wZL?q&ES?4+G@Ke3Yk+TuB_j2pfPIFe@b*n4$(4 z`T}gz1FUl!*rya&C>_{{0j%UqvQ^B1saU{R70nAs&dOY1G8JGn2VgeLT&V}9`*`0U zSkH#!ulNEJ762o*xA2lI7Fl3QOJK|hU{1_sdG#P3*faoG)sAGeWCGJR0ptF7xRB(v z7y}bCfRW2uZ<6d59$;z}U~C6qZp?9M04D#^rVOmUl4QCB1Jf4)<3DYG1Y5~BK?Rh7 z8ps4y5J9qDK6TiDS}*|Bu$kn(6oHcH?wlRV`Dhf9f%-vZJOH&(2dblx%$vtfF>G(fGa1=X^Ifl``&DgvsBo8-#GgOa)qit0mm6Ums-2c;DZimT*VB*~lM1tq2qip&L+Sr#a? z`=HdudzOM~<0UyX(V*n6fTDZX+e$KN^g!tag5oQBoIIeg5Y%QpsLm>qXTt|dbSo%Q4^XC}^oA-(M~!nKx#jbR$6V*1j5q^rmi5!7ZSM>p>M)lPsL)uTO$nP6XA= z2K5{OD%uUyv<;|gbCQu`2TD5?6nEp049Uw`14`Ti6nQi#bIi_p|7IA}dLO9vPLiWj z0ZRVm+iFntMI=+l7nJ@vQ2bAaDUz?F4wHZ@Oa$358DQ4V^gCUc7BpdMP$IcIjW9|4 z8WDl1VgXDSTN!gCdt6}>%7%%k?Xv;N^4SQJl08gJ=`cBAuFvl;k}yq) z!Bn+`Wc)P1r1fo-gS8qaFU(FH1NF~roAGV`p%Gipz|;Z_WVePsW6FT1$n}xSO61a*G~q?4N`?k(gh~UQ!rU# zhS0xXjxcT7!qj3R9^O$reh6N%am)tUrHilbj(dm}KK%qOBj_L^6jY zVA3^%i8m4^U(6r+FtG-v;ngq|uOeAQH83f^ofL(sc`3;y3WG_y0w(HLQ-UO;NEasU zK$y5o{>&$NMGIgO*M^Dw7)<7vUG!|46Q=e5Kec0yQ2|WyIL&kZ-*k^tK2G~M_5Uy5 zNMh_C^=pUHtjL~!)KIkJto23zD9A*g$vx8H{YNR7P0hNP^Ovg1ke}@+_LrLT+=gT& zpkFfW)gS7w&E44x*ZiR}&Wz1&-#10QezTTjDxj}YBy586b~(;*+Gm_PSJJ@YW%iqL z`|xchKdGnhCzWy3VvaBS2lc)rW{#QgcdB~i+Dxv}>wjM;%5f!UvgKzg;It`cWcEj@ z@kKbvazH<)_Q*SGtN94$+;4BGgNdSCONNK2s%8U{`GCI9xhGyyFV(8KJ{i5BN<4?S zmi~H9#hnu-*%0Ut-3z-I{`?`_|M@(oytK=?&))B(?2Zl0qN=TPuhiF3dc9sGlLCFIe|}X{S<+ADru$V; z8hg2U!(NtBfu8Cly8`{InjvT5>vDL7OY^DNj&@$Hd)d^;r&%Q90)4ItjcL^1)lTy& z&m~cXTQcWKAB(3-|7)4ai(1^prYb_^=f^uTsr=(M^R0)1srK9yl9_?N+37-W>S5il z`A^=vQL&9Oe4L`rlymETzW?P*`D-1boOY1FX6_v}W z{$s)mztjm+e-G#_l&V}v-O~vs*&pcteP}y}TEqKdp{Ce0^TNmifu(oHnAe-MNk$0z zgoS$FGxdYc38?HEV%{+97Pyz+&&*ggmt={cpIB{a2h--Jo1m!LeWrG7uArCBZRSza zj+q>+z!f#jpkAd#>qpC&MkgH?S(Tq-8d_w`VKHY*^=W_W0v|D3ct+Rz>Jzj39nc!%@j7rK4!S6 z?vi}JIZP@mfMl$o&swMC8-p*dcZv7;5ytW9c_N#VUovP9O_Ifeer%R3xIA?7MfiIg z8P|(CMK<|gW31=pAek-b+urY6#CU(pajEswT!xHD#?mRtbVjyo^Gv>%Of=1yGe>S& zZFT_T{hkBM-siY8h7%G<1`PVZ4VzE*|E5RezFZGViI6p$RektI`j^9^b}otMZDw zLQiyglB^x{+aKk<8k#+~bCsfadFcF{SrTu>^Fy8F6iFrz`tnx{M}%HdOO+_T5EzfqIrI}o`>-@_?qqBu2*KeI4 z`g>GY^6dWUkl)(^NEQ(00aWaN9TL^rEvdT|oG$Zuq(1UDg-q^HBbh;%8{ipG93oPf zDP_FiRESbrv()ai_>j}1zi0B*;v79g4oh0C>8Y{_$=wvQX4eOkkVV>cGr4O?QpzDL z-KEl=YotQlwRTGf3JHgJD+iIRBFrlgyfPMC$lD`*-u+$hy^lOHUJHAIhnm$$rV-{E zoD;hm{LLd%MmV}8xJ#{Brg7k8aO%|9On%#|eIdaK-WF@k{f`D;m55rqfNdRI*jl^x zf4Oe94jRFy7YfV%Rg()oQ?yg|Dkq z(hE#&_S{f$StZarJ9j3RZtpLFz;yYk4GV(*2DE;ZRS5j>F`)j870IH)Jc?Zz_W~|X zg3kx`e9mXTQRo^k2vAoMBAHc~Td{FbXn@Fn-WvnvxCHEbnzu1{&^%zVY1>S`U8C!U zfN@1RMZrbO1Nbwo6lIEe0-}FLkqj)%!KlxDObeDpi++hRsSY&ZIYFR zc^NM%Qv5k0a+Dr4G5o#C9w=o!aP{YTI6jk;H=MiO|I~MLWp{UZ|CmX(@~gGW{39l- zl>e8Xm*@7?FK&=;)9AN8zvu@Vn>3Cz`vsJ`kc=+O>1bODJ4OH9-L%{?)~{&U_f08P+lRgf%Mxbt`Bpm>_*%p7WAj?$eC56_R@<}M-#28h4#^P191-=bJ-!hmIcni` z%Dx-r9;op)i~DLj{GQ44>#6v5Ea1AS`r4SjV~Nk1>bH!Wj*WgTo5}g>FUdM~Y!3J4 zBbw}E(f^b-@2+<{*7DtkWS3!n$;!BG$FASJx>>AS=GdXkVF*|fJhsSLh-92$&Ix5Q z+*7BWOyo;m~X7UKPJe=pfQti#w48QMQ{7M4bF7Q3~ za+TC1nQoZtvWmCF%lLiTwg``8uh#m8Z8f(7y>enc&g2({EAR4JI(vuKdNX;ix(ZLN zO1s5gN&lUi$u+dxJLvf!?3)%_y2W$V9C7Weua%x@)NYa`hj}t-rVP)^*7@4hh=Zr) z)d$*6p8B3s{9`jYhzfclo*PaYY+rtA+M}u?aJyjtkca4>Gc);!vhr0PF{%^W%{4PT z=$%qJSsGy;y1R`@h8^bEFgbU7h$xAymXfJVJ@w0FyXHhHO&s|q-YDY=ues{^1H9HS+X}L2^Oh|Sf=I312OoRc%TjM+muZgifJZrfRwTUuX`?oqQNZeRJ&&g3;t(h6>F z|NYke^;gI(%u!;OyZiXjdbhnKvk!B7UJKtodTD?Dt`XD1qX)HHb}<;SM@7Yc%;Y=T zoi#mr%QOs-l-2JtBT;CigKx?zQXifzNs&Lw8*xKP=h3G@;m)$5WeR z1!7)MP`Q_Drdir<9Vs){tlAs9+v8PT?fHghaw50NO}nUOsqc}sd*!0kX1C{kbfe3_ zSlmp0`?ozM7tsliQc6qx_fn*e7PSH(qVV8l~Ed9HWe>8S=;tGzAtEFj5%ZB6qpOcx-t1zK%uG8{9i42D;N*YgMN8dGZslsu%}1)_cnzDb ziyqm#N71mv;g8eb1N%wVBIYgWMKm~N94axKKV9JDY4FH!^%1s{uENAj&ZP~nu2X;K zZllB<(oRW9-bPZMJWjGYSu^>US?Mi~lk9g!RC1}KwBSPHmtpaatI||S#v|rDt(Gx# zbU7Aj%>P#2v8vSp8neoeB2!h3I$8Hu@3 z<3~&#R?cZKc~YY2;6DA<#NmaYgZ4*0k}Zk(QWuwW+1sDCHVqZKXn)R?Wy&X%YQJwy z@l5V!W|yh`|KsUQz?-VJFMgY5>YS!inkH>k)H*%t#H$Fsad;Y0p^88l!~iN)5$gk? zh|si5VNk*xnXC#@1+^kzMVcD{F^)uiU=YO$s1;EvDz6An|L1rAIr@ESp>1+=&)Ivg zz1F&C|1jzIJJzhaeDvFyt~;j<${l@T+4cW_R;4(v>f2TEQU7dOc;}>w)=~fZcI%y| z)-N2j_}VZ3KBx1*g#M%AZ&wVwY4>HLw*Jz8;2Wl_QE%rz_V@Xn+lGJOue$2(fdlGZ z@~^1;exNdGuHRIirJs?>Iav|$?APhfeRu7<>;nIU=IM7ix{dyChp+qlyw58C&U;pG zJaJd)pUwCDM=cn1(~}MN{IsXHe�UZavh{=blY3&l)u0u=AdqvNjI-q}S<@FWnRW z`+U%6U*9^i?Mvt2vM-m69AfbdHlKQQA%kt?eAZIw`s@qLt67^+`VS%*dZ@$_uu{IWefg3XY{^+@|MKSEtJ-`D!>ts{2qfA#NkNjINk z9`RyTw{PslM}}t)at-b35goo|j7L9;&%|frGxAya%<}wH?gjURd&52AUUARl zxvJbt?kV?{d(6G&p3C!ASqs*LwPB4|E7nY&!^&E+rmQV%%v!VNoXy7haO?&41bc%$ z!d_v|$a7oSOYAB37JH1n#-8IWH_n@5FR~}uo9t2cDtlI*^U7XkPqVk#ZJl_{A044w%fDyn7U>dYEC;3o+kx@GdSE_zJ~3DjOb9jvBZ3vdjPl%Kuq2og zYzf8$Yl1oDdB$K-Fe%s+j0#o-v&wUh!Lndluq_xDtPAFq=O2TG!Ng!=Ffv#f%q-7E z21|pf!Pa1Gur`=mo|g<32a|)%!RTOhFuOcQ87vQ`2it@3!TMl+us`RE(hJZN&>PSr z&@0e0$a9zJCFm*WE$A`mHRw6ydCc@8^d$5q^eFTy^epn6W_lTV8hRUg9C{sk9(jH< zy%0SSy%9YUy%If>JlC0Cik^zziXMwzi=IoK_e?KFPeyM>k4CRX&nC}-rkA6qqqn2S zqt~P7ljlRz3(^zP8`2}vE7CK{bED}c=_%a13w_ za1Qc3Y`6$G3AhP33b+b53wcg9Tn3y5+y)#6TnC(oJU<&Q1Wp8Q1dar*1kOaBs|}X| zrvkSE#{$;^=OWMBhKqrdft!J&fvbVDk>_y3<-qB{?ZENC^}zYa^SR-I;Dq3Y;E3Rg z;Ed$C-Ec{8N^nbXOmIzbPVzi&xF|R&xG6X)xGFd+dCoUn7MvE`791B`7o3+o{~In0 zP7H1gjts60&P<*Q4wnX}2Db*s2G<7X2KUB!$Z&CRa&U8SbZ~WWcJdr?xI8#LxIH*N zxIQ>PdA>MYAeMbxu-nlW>%9m2j5w zoN~BKI8C@sI8L}uI8S+gIb0~5DBLIDcmXNM8l=Rslu(ovBI^&xytj-;bP%r z;b!4z;cDS*Pyqjmr7daKUiGaKmuKaK&)OaL1fu4VMh347Uu& z4A%_jEYDMii-wbin}(x?tA?|d=d8nJ!)e29!*RoP!+Fc|*Wtq9#No!_$l=Q2%;mZ4 zaOrUBaO-gFaP4sJaPOSQ4Hpk54>u1-4_6OoFVAs@%ZJm4+lS+a>xc7~=ewf?pb4N2 zpb?-Ipc%+>-_a7#6wnsX7|8$lyMD?u}n=gOm{psAp(ps}E}pt+#EaGp6@44Mqu3>pnu4VsNShaN2l zO$TiUjR&m<%}1V3j~0X`gf@gmgjR%RB+so!OF~mZTS8+(YeI8Ed*ZxxU5gT$6xtLT z6d_+6B+(|(DA6j>Eaf@zG%Ok z&yN<2CX65v}`nO zv~4tQv~DzSIe!2x98DZ;9E}{U9L-$LB|u9@Q%74zV@GR8b4Pn;9sycBnmpP(8a-M) zn!TK3fR>M@kG7A-kJgXoFWmq7e1r5IAN|Fj-Sw;f;``NCJ@6MlFXtY_HyQup^#(lf z>7Ts*+4GzKq$o&hf>NvywoICQBGu+=k=RR?U`z_}! z?A%y%hV@wY=(m5cJ_D*=|AY0Ca~R5F{r_M+2QPB{!TLTn{Mc#MoAV*{^*=f5H2Wc> z4Lr^MSo`ETr`a!ZZo`R7+q>CM*Zn!KoBg#t?(1g1$$1XdQ-1p|`_VUG=YQFsZ5M?8 z%YNltO7`#A1DE`l{rt|B)2G zweol3Y1r=C--)k5FZcSLc;h@w;_r@`pZ-QX`v2Yh8}WJh=<&Z1ubi7n{9bi)`ftSZ zq&|sXiSO{0FZ@cpKbxE{vGT&}etXwq{7`@1p_Akb&fz3~)Lr=aN%G0uOT8z_ zFVQOtPm*usJc{++&A*V3Mh_1BLVg-?fB#>|S8`6pc~2heBA=zKYwIGvUDH0hi+m^N zSA22m+%EFrokhQ#AV1#NTRTC%lyfb%&KZ7!e0sy?i%yVVAN=~iKjQ(A^DdgN6VF(P ze5_3x{WJM_*(;Slldt6*j5!y4^b`4f^Zl!SBEN5b@qwSn_i{eQpeplE)C2R({~V`2 zZ2I)M!_;&jb)W^Wsxj#@Zgfc-@14}whQ+%&skd@ohriw5Nj<*N*RzxQ{Mo7heNVlXb36*wRo_$36P*uyPkq04 zdDZvSdpY0Z?Ad+afd>k=t@{pqP&{G6ci;s%_v3W8?K|+q(YL?;7JQL->XmQ78*(1V zuUFmnEqLVO?2>Q6C$oS2;V5`T&I#GOdCpPr%m=Fn9|hl}&p-btct_3;nJ{tJ5%AEa zM;0FeAKm=Os3YJdIag%Y)V~gcr#1&aJ`BD(cjcPH;4L|CD+pnYRzX8v^x%B35z;}H=DEtPzC+CxdZ`#@c9&DIDvjcp1-M)bx;6={S zWp2rY$tS-CPoCWS_SfLc2QORnHF#6bGr9M_J--Hz{x;^XLpna)_wga{D(CWoUvG^) zd{ex%KM5WFwv zt33PVhA-#`Mt?B*3;Khfw41-6UyyTGrf>iL0R6<0=o<&!9`{nXvQxAxOtZQnD0KmC@R_p)KzrTgi}Zm#;@KKirK(U11gugN(u zJ&umwM?d#PgSwCY?!t3z`{?&LpPBhE8yt_ncl0Op%W^KwL!TNyp`X4oe}A0*`ue*! z#Ob%?yqeoh{o?fFL+=$QeTe@2-S?00rC;aVYUbEOpWo`TrK4Y?J+K2EPQ%wUtgzu2^a~^a5`T=}M{nhV$ z06#K!(25V>OXOUglP_QU0ep(@yQ~l3S2{1~cptun^St3-o{P?WA3o+_@sRi7XNFC^ z=zaJaIfutP-B5i zfp3%Zg4!l`?1qoK>HF7r!_Rf!GiNt^otz`oIqo03;q$IYG37krtD151$YjpLD>?nNd*JlrF@T=njZ)otXa^6wD^?nULw&kX)HTYTM$uteVR?b2C zBIN6p%=)xPsQu(ZRiP)7yR%B`a<_2?G5w>IS;CK)3`U#BgXc-;SKbOHNO_W zfnFi!M7=-u-EHU@A6>C_8~VmMX^(9~?~wDO_I-ZtHuR9|`Hudko%+zEV2)vaRSXa^BSSUmo0o9<#af^)2W#(a^jt=rzneU=G!L6Rz2U zp7ZG`+ZOblMYB3zNAHpIsczY`;&t?({`HT%jy`m5ubW>-FOqYs2JAbv89iz1wvRWX zFQu$|VKaJ@oM-jmbAvadM=gH+ADhvqw#Utz(W~T~tMhuk@fvzoUERXh(6{!tk9`fj zi}?-AzcNj8yoMh3#m`->=wn}xd#@F}OwPqx@#N#J=xKv02ezWGjrjVKR`fPGFYBJs z;%OzJ$Bpf^?N#)-c;UiV(d(ES!5poQvz}Mc^OhK#ucGg1`MT^(OSt+P#iV=%aspeR3mu zDRVNI>t(Lkun|3V!99%|(N~@8hHpe~Wu6B5>%Di`HloK~5efuJMa7(xLBKq*)gDYP|FP3w|UX9hf zh@O1^XP3N)zTEhu`9<_*IZy158`@jYqsPn)x1dko^y!2a^lIjUFlTJZ@{3#0v#nX? z7WD1xMc-^d@0Rn&j=mkLf9HDi{6THI*Q4*>=XiEKdcT}+ zHrz05JsyBt7xY?>2jJQsdF$~2$hl{iPycWo9)RmTFRsG_@PKXhIy?Y!9$L;pbsZjn z@IKc%JOH;JI{iEz068aZfOE_9cmOuszUX;80G@^8pT`3r=cnD;_oC+VLP4n)U$X1zBzB)vv>eT-q!C~JOFY&+dtkjKZ^%of&1HLJOE1ryPEL;$hmFX z{~c(?1Mp4CJw=>cyxz&vR8Njnon(Ci3dQ=wfpMnX)Eyn{BF2sB_4pbsh*X10OY*8!K+hO;sNM= zWO$@zFAm)W1j1F++*-@kc1Vfd@d& z*?W9?>k2#oTkl=60uMm?@JTE10Lb}!h4p<_-~rgbwrm9+fSvmcEARlwxqO#Td~Z1( zfcAr%mg51KGcdFq4*;`z@Bn;2VaRek0JB`zF2@5fVPENTJOFZz-+=n>mf-=oY4rQc z@BpkG@yaqh0CK)xQ`4kncmRrC8MX`$K#F?}f>fO}nImf``Ba{`xreCbj=0BfSTOYs2o+jVLQ9soH%@VP&t zOYi^;?)kzJJOI&&^OxWOV5SfrfOjq*yaW$G?Tgng!2|Hg<>xHH1Hh~yecs?>#~0%P zNc8-4F&==XGjA-$10d%Rj(umwVmttwc0I5d55WFU2Q0<|Amp_TZjiB z@$*#+@c_vAipKe-g?Iq2{q?7(@Bn->ZvRtw0OZ`o1xq(Pg$E#fedsAX0OuN}JcS2< zSxk5Uw5|P~!UJ&N#Ven}0}y!C^%NceIj6Dd#LrLS0XTY5;z>LJ9gn^JBpv`czwwRh zmp+LH;OSk{p2P!i-r%uM;sKCz9o5#};%L>4Rf)+xp2P!i;T_pe;sIdR6CQw5RfiYg z0ho64hYRokygPQ=0z3e64&=74<}JVjFzU+37T^K+YUMo(@Bqm9kiKWGT7U;&M4z$+ zcmO;KDI{oYUcmS>+^ZtB10B;Z7Iv)>!oF}>PiTU&K032mj|V``pDg?QyLos3mMr;n9v*<=(UEz00OVZC zu~&=JH-rb^>fTNB@Bo~9$M|`80OY*NF1F$9iL=X>voRfLSE$;{M09_P&`|V2SCo-y!pdl z=imWYb?@OhcmN*D`D6|r06B;Aoz<_*!2{rFSThF?z-<#3%)tX7=X0L3{J}YR08Z>2 zItLHH5W_8V@BqlUoyIpWoP!6Te`V1eJOF*Ro9EyGkn=qA&EL(&17L{ln~ewHnbq&i z#seVdeEu?R{cJn{8|N*XjR&CYrCGD_0Lb~Dea^XmHXeXu^@C^Q0T_PdrrCG^X02a+1G7ArYoI9F-viB@J0NZzplhK3+ z;LaCHXW;>078xFZ5ib~K;Q{z;=WjE4KIz7j-_67WAm@~p%==&_9)MXV+h^hd_~qf& znRo!?{L%w!md(TiFyzkQOgsSJ6i=Or2Y{JocmSM-{WI|Ze0+G|OgsR~PTe#U4}hF^ zI%>#eGw}dCw61(69)N|${F!(F!0k64o`DB|*=TqG&g_40 z1|EQ{_VyWg0B+g#+6+7Za&GF4;`Aas0G5KMX5axhGpuO_9soH{bz1pDGw=XpH{UY@ z4?yCIyJp}4kaJd@i~G*N1F&M`6*KSv+*y6$3_JjG{_28%=FY$akaLH51|ERKv@=b3 z0GP>!2jIHg@0#!cd^`DI6CQwlzr>sH05Gc!55Ti!JDTtSG=BD46CQxqS8iy+10d(P z7LHlcga@GCy>pxJ03_-gn(zR~`L4zRuFO?UuaSm0~I10d(VelYJ}O?UuK zUeKor55V;O;&eFS0g&@xKX|0P2@k-+p+!x203w64oA3b0IkEovXB+VVe7^J7MmzxR zSwA-70g&@!zxnDwBOZYAF`qQz0oZpY)`$l{&Xrv^wyhBlz}vlB8}R@PJ*TA+4}hFE z`@f2CBOZXvexXJ@04t{l8}R_hIkdgcozjR0p#P#r8}R^qCr+Qk10d(qwhSEJhzH;^ z+g*)#0D|A#)`$l{&aDl#S2yAT_%8O(Mmzwq?<*Ve09@nz|9Q68_|I#^1MvQvu0}in z$1f;s!~-Db+;(1@)`$mS*AYV_9)PQ#IUCTQcTLW}Jy_Efzyn~v`B(rCz~P#s0XzV5 zF76%ABm#HaNk3JW`10d(?p7}N$zyoke;nDye0K>3_0XzV5?(TZm>;N8siK`j|cmRI9 zY+3*hfSkvB;K_*rJODMr>jHQHCiEE>zyl!X^hU3_H-HD=*dTuZ55TTjBLa8;PG2fCu2qT~`J00LVGOBmUVlfCu2^r!EcP0oWp*y~hI}=L3JAetrNCK;CQT2JirM zKUf~X10d%H|4{4--~sq=wljbSKr3xl<|^~D3gdgB3*^O@NX^MnV0{ecI7{elNT&TVEt;Q?TO;Q?U3;Q^5IoY{|f0N9^+ z0NAg10NB5H0NBrX0NCGn0NC$%0Ob5<;sFl;@qq_`c)AYSnR$T`x)Gadlq8xH{Sjt4-_mnI+J0U$r%0U%%C0g!X2$tQRK$S-&R z$TxTZ$Uk@h$VYep$WM3x$X9p()AYbDFAb;ZlAfMv_Aiv`QAm8Hwkn^#r2Y3Le z4|o8m7kB{V+-&Lz9sueK9sueM9soH{n|g!?fck_7fO>@oK+f5wp5XzYzTp9&-r)g| z^S7yocmSx6cmSxEcmU*FZt5u>0O~6q0O~Cs06DLldW;8v`iuvFdW{D_&he(6;{l+) z;{l-F;{lNKy}<)`0Kf-$0Kf})0OZ_n@B|(J@C6>z-xE_f&w|D@+yLbTP{B!Uy9suw$9suw%9soHP z9XyQ(0DO%H0KAO{0Q`*y06dNd0DO)I0KAR|K+aJI&*K3A-{S!Q@8bag|KkCmAHV}Z ze}D&oegO}FoV!jxfd_#80uKQF1|9%8kDY!54*>lM9sv3kJOFY|JN*nE0Qws|0Q5U} z0Ob63`XM|3^hbCA=$G&S$hq$HQ+NRAukZlSZ{Y!u^WN#l@Bq-C;Q^pu!vi4az|+s+ z0ieIb13v-~oUizyknZfCoU%y}w@Y z3AzVB@C$eV;2ZD&z(3#tfRDff06&2T0KNhb0Q?0W0Qd|%0Pq`l0N^|D0Kk9X0e}y| z0{}mQ2LQeV4*>iL9su|hJOJ=3cmUvA@BqNS-~oV-!2$SE_&q!T@O^jy;Q#Odzz5<1fFHyI0AGj) z0R9jU0DK}I0Qf~b0Pu}?0N@|-0KiA$0f3*x0{~x%2LS#O4*+~79su}FJOJ>WcmUu( z@c_Vw;sJmk#RC9eiU$Dx6b}G=Djop%RXhOjt#|<7U-1CI$KnBipTz?JUyBC-{uU1a zd@ddU_+2~z@V$5d;D7M|zz5?2fFH&K0AGv;0R9*c0DLkY0QhA*04BjV;{kww#sdH! zjRydJ8V>+`^*6!;0Dp}K06rTJ0Q@!{0Qhb^0Px><0N}&%0Kkvq0e~;Z0|0-H2LL`D z4*>i+9su}uJOJ?TcmUwz@c_Wj;{kxL#{&R=j|Tug9}fWhJ{|!0emns1|9Ak<1MmQ# z58wenFTewUet-u6Jpm5@`T`yR^aeZt=nr@R&?E2wpikfdK(D|9fPR4o06hZ_0Qv?V z0Q3$#0O%ih0MJA50HBZH0YERo1Au;l2LL?<4*>cK9su+fJOJn~cmU92@BpCC-~m9d z!2^JPg9iXT2M+-H4jusX9y|c(KX?GpgYW>L58(koFTw+WeuM`AJqZs0`Vt-h^d>w2 z=udb6(4+7GpikieK(E3BfPRGs06hy20Qwdl0Q4?A0O((M0MNtm0HBZI0YERq1Au;p z2LL?{4*>ca9su+Ie!vlbRhX(*X4-WwP9v%SnK0E;Ee|P}U z1MvW$58?qpFT?|YeuxJEJrNH8`XU|x^hP`Y=#O{+&?E5xpiklfK(E9DfPRSw06h~A z0Qx2#0Q62g0O+510MJA60HBZJ0YERs1Au;t2LL@44*>cq9su-KJOJpgcmU92@c^LD z;sHRf#RGtTiw6Kb7Y_jXE*=2%UOWKkzjy%9gYf{M590wqFUA9aevAhIJsA%G`Z68> z^kzH&=+Afn(4+AHpikogK(EFFfPRe!06iNI0Qxo_0Q7D=0O;R%0MNtn0HBZK0YERu z1Au;x2LL@C4*>c)9su-qJOJqLcmUAj@c^LD;{iag#{+{2kxpXZTruhu`Hj^w$!v$!qf-ych4udvgt33)jT8agAIn*UYu^8Tc%GCO#XV zk}B>edz(GZUT4p<_lW^wftVmRh!J9im?3tEA!3P`BDRPzVvU$1_J~1Z zk(eYliBV#em?d_JVPct>Cbo%jVx5>L_Q?U{0&)VmfgC}uAZL&}$RXqsatgVH97C=l z=a75ILF6KG61j;SMXn-ek-NxY`^bUhLUJOxksL{`BxjO4$)V&@ zaw@r%980bx=aPHL!Q^6cGP#)?O|B+qle@{`6rc0%`)aff_-r zpk`1zs3Fu6Y6`W58bht2=1_a6LDV8@619mMMXjP{QM;&N)G}%swT&7_t)u2q`>27` zLTVzlks3*@q-Ih(siD+TYAUsr8cVIE=2Cm9!PH`EGPRi+O|7P8Q@g3*)N*P%wVfJI zt*7Qw`*jb1zye?bumKnWtN>;JJAfg;5?~6j1sDUY0p zGcX!h4a^311H*ykz;s|cFdkSB%m?-Z1A+y?gkVE3B3Kd32zCTRf+fL}U`sG2SQE?% z_5_21MZu(CQ!px670e2D1;c`6!L(poFfLdZ%nSAf1A~RZ#9(7EGFTbR40Z-XgQdaL zU~4coSR2d@_6CE4#lhrYb1*ts9n21P2g8Hq!SrBzFg{ox%n$ab2cQ?AC!jZ=N1#`r zXP|eWhoG0Br=Yi>$Dr4s=b-nX2cZ|CC!sf?N1<1tXQ6kYhoP6Dr=ho@$D!Au=b`tZ z2cj3EC!#l^N1|7vXQFqahoYCFr=qvQ13<4u&qeP=4@NIWPeyM>k4CRX&qnV?4@WOY zPe*S@k4LXZ&qwb^4@fUaPe^Y_k4Udb&q(h`4@oacPf2e{k4djd&q?n|4@xgePfBk} zk4mpf&r0t~4@)mgPfKr0k4vvh&r9!14@@siPfTx2k4&#j&rI)34^1ykPfc%4k4>*l z&rR=54^A&mPfl-+2Y_Cko*n-_Jv_ZUJw3fWJwClYJwN_`H~_c+I03i;I0Co=I0Lu? zI0U!^I0d)`I0m=|I0v3Tzykmm0Ve@B0Y?E>0cQbs0fzyX0jB}C0mlK?0q4Q<4{#uG zA#fsaBXA^eC2%G@KLLjVmjb5(w*tok*8=AP_W}n47Xv2)Hv>llR|99m^BZtDa5-=~ za6523a6NE7JpTa)1Q!G+1UCdn1Xl!S#PcI?NN`DTN^nbXOmIzbPCS1C2L%@eCj~bJ zM+H{}XT|d?a9D6za9VI%a9nU*a9%wB0tW^c1}6qL21f>024}|eGjM2dX>e+AYjA9E zZE$Wpe**^x7Y8Q?HwQ-tR|jXu^E+^OaCvZgaC>lkaD8xoaDQ-saDi}waD#A!aD{M& zJU;}72$u+_2)78w2-gVb2=@pF2^Xnzl7gFrqlBx3v*h_DI83-qI8C@sI8L}uI8UB` zf&+yMg%gDvg(HP4g)@aag+ql)g;RxFg=2+lg>&WkD>zuVSU6d@SvXp_S~y#{TR2>} zTsU30T{vF2UN~R4UpQd6U^rp8VK`#AVmM=-AA>`NONLX1TZUtXYld^?`7=0ZxM({q^XK_LGyt>!Gy${$Gy=2& zGy|R=L_vLo^7q2s8<_2{a0{3N#CzUqr(|%RtjW+d$($>p=71 z`A0Mmv=B5Av=KBCv=THEo}WZRK}$hXL0ds%L2E&C;rUB67_=BP8MGNR8nhZT8=l`p z!$HeI(?Q!o<3Z~|^WphVG$6DfT@w=85E>C$5tMFtqRSG=U36N(6Z39(6-RH(7MpPc>Wa)3@r>z3~daJ46O{!jOS<3(9qJ* z)X>(@*wEV0+|b_8;LzgGZ4-?X ztrN|Y=bzC)(L&Kg(MHio(Mr)w(N57&(NfV=(N@t|(OS`5dHxy=7A+P{7Ht-d7OfV| zmgl$8aM5znbkTOvc+q;%e0lyG4HzvLO&Dz$jTo&M&6wxM(U8%S(Uj4a(U{Si(VThy z91R*R8ciB)8jTvQ8qJ#L*U_-iveC5Bw$ZrJy3xFO{v8b*EgVf8Z5)jptsKpq=jYMT z(bCb>(bmz}(c016dHx;^9xWbC9&H|t9<3hDp6B<`@X_+o^wIXw_|f{&{1s(!N{`fS zMz8sR<)O4Q=?gMl*&B0u=f>=V#Hr-ti%vUcI5S;K+|IIR%6pu<;k=6TTQ0b;V%&9A+O^l9r`q)zmFeBA{%Oug}=f4Ogd(7WZ9 zGyOcbHQpZWe`df{cRXM&h`-w)zBgL@OnSq9@$>%arPKF|-|s!`sCcc5 zpV%|??x`ol>zf~+Hzj?_tok#P$4x#k>H0}8JZ5^#KXKax>x4o7Ui;{gy7TJpd1S@- z_a8nzuE)4r9~%GQf(JI#wvUb9f9Sp+?maQ)5A^4Se9vtL`{6Alkq2cF%2R`fa)8L9hGfkN!3F#tUxv__~RnBDJmWkUqcm ze)5|0tG4&*fA!Z_j=$n;<(!_m|9JY+vP;%obYVry1r_ISIIqXK&y+jMmbf!rGn}U# zm9izVf@~fd=Ccf|;IPm$1{onj&>}MxFnG!ed zUHs8GA8vmCruPoMJ7G`OJ1_3??))LTK)WLH#g18TUAg^8+wwPV+h*DteZ66`=QUI7 zhp()7`MyoPHm1LHxTSr=>KCT3AG7YZ=c}H(=vh~D{xdmiv)AOVE?RZ&%F3s22oGH` zarxq9TbF*h#ImH<;s+Kz8~SRYd*SG(Ha^+Cpx=V#`Df-0n-`gT;oPM`Q*i2>Q?n<{ z{$tjRS-G>GpV@on{uz^JxMu8Wn$&c0)8WSE#xac-H=YW_0&4?P0z(7UfeQnLf%JeO zpoo9d#n%^#zZ)vPw^sbjsldhJ=bIZ3H(o4$e@~N3yw?61y=Oi@GgrL+AG0RSJ~eyl z98+*<@WQ!~xx?n2nb$nO--7N18=oBglzZV<3!e==u&CE!%aSjbY+br|*~H~TSKJV; zeEQs#MXPdGXRpawoBxcf`J!j5p1bY&G3%zUU;RS+hQlrCFZJ4Z-=-BWfB1^2)$>}z z=IHCDt+#Dk{>G8EE4R;j>x&&%L>6d2M7=v-+?Dmtggpn}z3IKp@1OJG;*X4br^HWu zGWN4?{xf3#fzN#h5?=^B_SLAbzw3DT@NY+^eQWuCacAkVjXzfXwCCqRT}OYJ_^avn zWv4FeZadxY%$H}!|B3g9f6B!aoSDhZ0pY{I3YhGMFezSP4b)|SVmh<&K zy>#uPvo0O<@Axjugin6lI)P`FIrnYvto4ueef7FYb8k5?>0tkHljpwq$K-tRJo;rX zrcHV6ym?bN+iSRK+T-VqIq~?~)VrsK4!<*%^QsQrI`@gqA0K&wv!6Wo%$v6G{{7RA zEpbohEQ+&()=b|c&LrBsD6Qetkg5h|d~im{mR=hgmJiz5@RT_3Ci=k-4Nd2qYT)b^ zX29@&{>hxg-sd4H~h>*2b%KCYAN<+{0kJ_nzN&&B8C zbLyX0d~QBJ_ksJtec}FapSWM#H|`(zk^9Mg<^FP?x!>G(?mz3mday3659`Ewv2Ls% z>&SYtuB^t@!`;h&}zGQ#0 zPuZ{RTlO#enElMYW`DEK+3)Oo_CIkzJP;Se2XR8Y5I4jRaYQ^3SHu@_M!XSs#2;}; zJQA10Cvi%=61T)JaZEfD*Tgq*PP`NM#6LI!Eb_d-GcyGy8ZB_u8v>i15%}&off2!( z`vg`6?}C{J2;2>JKUd)Y-J*w}4_PjHnG(?t%@RG;QPG!OD|$QnLwZd5)P(4D>6Z&c z&wZ2V+v)w+3jW}A!9iRjc#J863xQ98lY!UySa3tP2!1IfI4XE9xUwUHZ-cY@K=6L8 zf;)Uv@Q-kq@SqG}J>;EA*e{_RQLVG~JK>t9) zK!=zqv;_2k34+symxo)wOYq}x++PTu`ZB>a!xzK(HVEDp?sbIFP~kwE1&;|Ad0g;` zaDwo9aC7i${}3D*JQrLQd=s3}TY~qwTyQt=FK{U53myb613m&yVSwNT28!N(z39)s z5&p7F&a5}<&id;*me>#M3-$;5g#E(4VgIm?*iU`LzG8o|&)9G5 zJN6&@kp0NMWPh?x*{|$d_AmRG{mi~*f3wfo@9cZ_KXE`j5EsM;aYDQhH^dKdL_85! z#20Z!yb*WAA8|-L5|_j$aZ0=rx5O`TOgt0U#5ZwHyc74tzt{pQ|K0s(gE}|oy=!yN zG^nBMTl#$WTZ6joz2$vwINqSProY$cqHh}1H*Y!9C;VB1dg-phz6*CXsFseNeRE!G zPYIJ{^=+-2uKr`kH+|2$VY)i0>gT>a@}{d3 zHviH0wT@}3VOeVRha0DS>~J>kzM)I*b8)$eIfsM|K4 zTirVS3H9uuit37MpHQE(^{l@9_o-^wb9MDco2IIJ$6s50cGOh$pR2B`j^s~OcfNCT zb>TaYtNx#FuQp70Tumvst9oYX~@5BJtr+kTm>e)HY*>UZW(R-@CJs*8F|RzIFStJ<=ClDg!nVD*aI zC#jZY^Q-q9dQ3fcyRA)D@tX3CI zQ0v#OslGXXg8J>s=IZXH|5o2w_I&l7dH+`J3ty-nvhY!L_v{y|t!a;{|9N6l_5Fc5 zwfCd1R!{i-5%t8F&DE8)kEqA*+FHFfFhsLUb&M&GzjNGqIiF{QZ%(-73u(+c-W8{76A7hSG z4}Ixg^|33ztDf-N81)V1hw5Q{#;9+7@ME>DX|y_J>Ce^ScSfnlhW%1~(mYDFl>JtH z&P{&xgN{>zA-hMttod}cDKb*M@b0tKkyCf8n~VOc7SD31N55CpcSns-U%TF*I+qSt z`>sw^YjzJ)XZ~hXA3Ql!ZMxO0K3FKE5!tGoUfsLq^|qu$~esDAXBP2F?looZ{TUG01O9qPrkdFre8 z)~MIC=Bs6o4^R)BDo{gD_E#-^id4fhx2w?xhdSkz+f-#|vD*FCt?C{_iQ4dPKQ;4u zmummy7WI<`xB7a*tJ-&zs`nkbS^eNtnR@Zzo7B@i&rws4{!4v&?78aiM{ZPKTyvhP z9KJz4|I;4oMTf3e(@htsb&2cL!M!e2zleKO)BP3d*mqU6VCh9_$&PBZDSEMb`jx(F zzaKAAQ=9v!59D8_Uc2yG_0YBdP}e=tTU|e@r+R(uHR@ZlD%HX}t5kQ(x_{gvvk#;f&z`I^7ud;APP%kS{JyaunuYx3H>2k*su^4?qn*TOY%ZCoSQ z$~ANCdd&@oMUUSd6_pAYH z!J4o(tPyL)nz44QA#2H+vbL--Yt5Ro_Ur-n0(*kJ!5(3+uxHpi>>>6NdrIG1Vvn)c z*mLYX_8@zaJ;~l=kFr!Hq7`cp`Ms6d=k?Y8L{0@Fz{QeGpU%cK9UQfJ!JFhR^ zubuZ3@88b*i|c9Udc^g$bA94^+qqtG{q0=8_&n`=9`X6w`F!H@w)1(#=Wplpi~G^e z{Sf!3o%mk-B!up8yim+Z{ z{UWTNSkDOSDb_c_`ik|Au-;<*BdovJ4-xi**dG!0huAL>_KVm*5%!PRPZ9Q$*k2L$ zm)LI+_M6y$5%!s*xwQMx7hCy_Pf~s5%#}` zhY0Z?;v+(Qh>LFY>=e{ulK?qaKL*piv)0z0jx^qJC)94^dAv>WQc? z8udlg8;yD+>W@bK5%ox;9*O#-QJ+M;(x_LWereP%QO`8$nW%3X^-a_}jd~~QpGN%? z^-!Z8iu$NgA4R>?sF$LCYSd3rPc`bPsIMCJRn%LJdMoO$M*S7_Sfd_``m9l(MZMOj z*P?!F)NfJGHR`#j?;7=8)O(G3FY3Pr1`uCsU;yzw4GbWDRs#cw-_^hX; z1_luKMgs$gd!>N^#J$tN0ODS1U;uG%H86m<*BTf=+Qh`pkL0mR@)#NOAy03sGN zFo1{+4GbV+MFRtf*wMfMB9=5TfQT&(3?O1n0|SWI)4%{C7Bw({h)oR)AYxSm1Blqw zzyKnaH86mPZ4C?{VqF6Rh}hS_03sJ?U;vRDG%$e36&e^o5&;F+Nv)`%x?0;%M@j&e-KB)b~ z3$>s4q4pC`)PCZN+E2Vu`-wklKk-QICqAkD#4EL*_@(v}&(wb6o7zvjQ~Qa3YCrja z+E0F<_LDED{p1g7Kly~(Pky2HlW(Z~7Aqe(D9apZY=Vr=C#zsV~%i>J7D@`a|uf9#Q+LPt<BuAe(EK)pZZDdr=C*#sjt+2>MgaO`b+Jn z9#i|N&(wbEHMO7mP3@7 z-m?ZtJf^P=Ym~%m`r5IENj#^oEo+>_d-~e52a#<7ACh@x-%fxgN-|MkX%qQ``o(sqc$^Jmk737R$|Dfj*a!Rtl z&~ptrC)t1Kxrm&U>`(MuMb1k0FM2K`rzQIvJ=c-*lKqdK3(1Me{z%W2XLRZ|k*}8l3FMsr~fldab5rC;NB3mQ&M3?Wez|_S5fE`vYKrBp;w- z1HPZ+3v}!N21xP=I=0~T!5UzIB>$je5imfKpU|-i7$C`C=vW2}kmNUXtOEu}@*g@D z0s|!Z5gjXm0h0WQj-|MtU@I^{l5f$m7Z@PP$LQD$43Ok&bnFHONb)&4wgUqs`5qnn zfdP_ykd6((07XOE5r^Z_=?R7$C_<>DUwukmRd$>x2z1p_4c zE*<-V0g`-}j*YB)_ZodSHMg|Eu?cV1Oh)toMpwfFysc_mW_MB)_cpnqYt=|E%|-V1Oh) zt@o;60D4#I7riVPAjxm*y)GCa$$#s;Fc=`okL$fM7$C`?>%BA>Ajz-my*3yi$-nEp zI2a(w&+EN97$C{t>%BY}Aj$9Ry*?Nq$^YwI02lyn0DJ&f00w|N06)MbfC1nZz!z{0 zU;wxW@CRH37yxbpd;(Vi27tQ&zrbaH0pK>kH*g(b0JsnE4_pWs0B!_)1XltE5cf_6 zKf$Gd0pM1^S8y$00JsFaTU3{Q}$}7yvGjegbY03;@?izXA6M27rsC zAAy?$1He_%ufSb`0pK#}XW%x$0C1i3J8++10Ju>4A-GY!Kl*>Yl>SKt1Hh%yPr;3Wn>*YFkPX7#-4hDc*r@t1pRs{pVz0-fg#e)GvZPqz@xO)0^xO*^w zsQoJayr}Iu$1iHX&iTXr)Bh*$1AGwsp*k5CYBE0%BPxH#_xKq&6Ml!^DO#k6q`*^3=T!Hmn({~LQ(Q76~$boD1{zHv3eE7QKKm7 zK1Ff*6(zG)QCxM3l3lMTrQ(gPLB(SWDIP;u@z|RckFiDZ$Oz}A4 ziYGmxc$^)IC$m%WxVjWicDLdwRZuPr34I)lz_cFC19*b3FKF%1k6<_fkID8 z!0Js2IBHS?>AsYJ)1MN^tW62H>QVyP^(leUK#Ip2Oo`e;DN#c>C2DU@i5go{qWP^U zQFB{Lv@n_ywZ>ASj(AEmJ&_W1cBDizJ5!>ru9RqYcS^KWF^Km!D7iL+lIk!hdF2Mh zRAEpGDh-OI%Agc^3`&~UpcK~_lnkFiDe)VWtXhNOt}`e(^#-L(SZJ+5gC{p+@T7(f zp1fv*$JAo*6to&VmNtW@C~EMe#SEU}xWSW=FnCHj44$k`gU8)v@Z@wGJY`C%$7)Rt zg4Wcir7bmD6itn$#Zsfi@ziKWA~jmlks8hF zOpUs`QlmNDsnIgUsMxGVtIcLqavesiyWtRxdZV>8U{oAIqt_NPD#c-=*WN6Cw#DepZxyckHlw#NYV=xTMz14o z^rk0_UT25Vo7rjfy1I~5pCR55vMR#VVsGkJ0yrl7stJ0R#VK} zW{MR?O)+cC6m!H)vGjx~=Ik)VGCNH%SC=W4-EE4MD&~OAYPROu%z<2o*_u~w4%#Zr z)`Cj2)ly})7J1CpG_ToOTw}Io_{`Q4zuB5qYqq-U%+{QGv$ZT>4mg5lZ*IsOC=Q#w zdClgaqs8nkXf=B+ZDwy#)a*@*nZ3nvvo|AQ_Lg**y;+@Rue;0a&FMCK%M?r0X0-%! zZI)=R!xGFZx5R7}mS91pC1|O#1dBYDV4BwwEUvKxGklg{iQf{;sag1E0Bn!>2~y_mJe5x3T)C#*Hj4r@(j zr?tk_Wv$8Xw$_wd(?T{|S|H7l7P6P8Da93Oq5R6UKyg)CsL+$9WO&m;j+(Skx-Tu{ z^rwX~Yturmy0lPseOjnAkmgAbrp0ZcG*3o2EpBg4^QO0?#q(R!ycun2@xo|YO?oUX z?ue(w(-UcNXGdB*vokI3>Pm}ecc;Zmt?9O0N4hPqJl&I9k!~xfOpoSPrQ3?U>9*pU zbX$fm-B#jHw`J9)+uU{Oww(HOTUju@CO4EG$Oxy`@UX#2UhR&(vl*Ty>d_?D|YcX&_T^1~YxOP^MB6&h*)vGp){+OkaL$ zrnRIk(^nYHv^is$K1V#$R+7l{IXlE_bY}WoU75b@?o3~)lI5{mv%)r8mM71V6}FdW zdF>Th;rz-hZ(dbaxX_bTWA|o-9W_}sdA_W$)1T$D*Jg!Xby?x;`mAtiAj{(nW+iN) zEKf-|D`9WW@;Y0x68WuJ-jcSgL}4_m#u>{>IO16~C5fzrvm?vr?958Iy0Q}4-C2oJ zB|BiZW;=3i*?~Mqwj-}RJ7}-Sb`(@*2lJ}39Yvn(klmZ@D6Yv4<@vH5CI0NNy*At7 zuFH1h)Mq=&0@(p)Fx!_K$_|u-vweBZ*+FMZwy&TyJ6O_|?JJ6Ahn%r&UvWG;RFcT{ zm2_l>ot@b}cUQJAr#stMrsPEJ)|_yzEhn1i$O-3_=fvz4IpKoJoLF8}PPoXE6SsSF z!o@W?@jPEnxWu26u-E2<-E}$Pocf$_Ss*9s4CW+qLpjlsa84qxIVa|9$w?Hn=EO?c zauP++oVYWVlPHeo#7h!6iIR?-gtIdz;qDS&cjqL^thRCy%wpEAt=wK=E6=aA1#MNf z@|vYV-YkB<#pcg% z6<@d6{Do1Qk{7f29dVl{FJbdLJ8TYnr_Jx`vW4y4Hh-x#x7=>a75O{2*Cd$~Yjc}jb-6)jeQtB9sCf2ZuEQS6t+9u5JM7K54o6FF zM}BK=*wL2TQ5em&<;8M49P!+myhLt?vm@8x?9A)Vg-MJm5id}J7?N*1)?r}Km z<$2}yaz}-|yr9zVcU0NSi#&Fv*lRB@uCaTHefIJazxcY=Uhb~5$L#g?^0I(kaR%*H zXUOhxhVA}5apleyyT72-?svA?{Y6o`QWCTKi{o}rNy6?g=@75cY4^Lk#Mj++f0>eJ zb6E2n4qIN0!;#mVSDxo}ROB@mROZDTRe8-to;+KzH?O(4Ca&*lu~Ih>)q8fQ4KL%f2|(UR9u(3+QUwB>aaMe}SWvAmArc%Innc^xGk zc|K=nUWdCYFX8OY>nOA4m*?B^l>$e;_{{m%f~x$ALXY^fH^0JBlW!~VkaRu|sU7>u%9nLRzH|JYjE#mvF`BryZer;hi-{y+t*E-_)Hg_Vw z*4dHoaCPR_y1Mcm?(Y2BQfonZfvvz(;3)8muPPiB1r@H!0&hW8K}(^xpvB=UXmR=r zDx9?iEv`E8b$vlgX`sO43KsZXp#qOPT;O*%7kFJQ1+}i$0t`dw9p6-Ayx z#qBMuD6T2=xP65cCH}&4cWq&XyROjht}m=83ls)i!NO)&s4(CT7dE?_3xlqf!WLI+ zVbI-HSX&e=47p;3wZ-wmkULRWThdV&c6Aoky1NR)?(V|cGNs7ovKBd9wxSxBqsZqf zFRFD^6xF&ai#i=uMJ+|1BAeS=)KXkiRO9v)wUqdaYMr%3E$+IaPG@~lOIe^O>IxQh zxI#rycetp--CPuNwG?%_T8m=twxZ6WXi?l1E9xwc7scI)qRx_zqJ*onsMFn5lyG+! zb(T3Cen+Ll>!@=0T|P&pv({1Rs&hD;^^VHYfJ5wIht(N!C?#Qszqr{U_OPSE+3F}S zX><79QHRYL6F(bw*h&(PI%kLY{Z2=ntIOeYc01}yt;OZVj$*&FqS)%LEDjb|6$jnk z;_?z-ajVl`Y%QrRZgtfa2TSUUTT27Q9%r!F>kJipO2Wndl4kLHEyWIZtN6ODIP8uV z*EnOvK4-jG?APKhXGgK4q_eoo)m0oW=`QXnt#a16e9p>}T4$xZ&gm$rcUG2#oKa`k z8FRKeJDhFKPVuKeNz556i94eu31?kNhqJk)(^=;huU69StShT1@w%%@Vs3AVzraHt^mDHECmW4{9C1LS(ONr0jTGCO{R+4ZhO1erqOS;_MC0%7!SGmjKs&rMk zYF%EJ-{o`Fx$0e2r2&^x8g!MHhFnTn*i~NE?6Q`&xGG9pUDmQTS4COWWh;%jDof)o zTUo+YS=Qllly-{W>vB2Dx?T09R(HAE;jVO7xm(;`x8Ln^*STxm6=n7Aw$gyxQyO&p zOG9o?S=j9_Yj%4}Tims!t!{5wo4d9w>aHn`x$8>f?wYcMyRNLm?JMnc*Ozv=eP!M5 z?ow-Md8wncveaAZFZGqymDZP5l?6+iO9cWd3zs&RwU!3U+Dco>qTlASzTFuSzB4Kthp>y7A*^xb(FQ1#l+uq zivM<$CCa+Wn2dehq%)OG!v#$AkKTvteYxz@lYQ{teSESHR+D|O z{9^pm8X_lnw4f_v!U7CoYHJ+PHndM6~EDM@SFW9ev?1dZ|P7vj2(s!b4N;tsUx++ zVpD8Jo55zbrPxfiRGTHFgp46W$Q()unL?={ON~-vtTEJ>Yf@@VHK{e0xDq$U4RLck zC2oqR#x0dfrLodbX|7DEG*zZnT3VG>W2>Rn+?vvAYE5mm)G2kwIzyegE~U;?ms)4( zQo4*?hAwkgN|&iCwaa2vtVXLr^lB+qlQq?92`WKj&=52SQ-Y>oYS7|Uyhg9VYxbsi zP2Nnq&lOxq(2`gb^*bp{{Q^KZj zYS`jad`6$aXZEG|Oukf~C7~pY2}8o1NJ*FysR>J!Qe~_%R0&q2%2btFWoc8|jBSQC z!BVuD+EUvr^-8_5-cWC@PpLQ6r`B7#m2P9Vq1)V@(rxNa?Y0;dqtR$EnvE$&lQGq3 znW@Y)&NR$4&rF$VnwdJ&a-(vi@kYaq<{MLPG~Jkbqh+_U+qm1X+q^qvw`q6k?*HTI zOyFa@xBvglKK9s&*dz8eme^t%wZ+;ZmZ}g+5Mm2Kl6ewAghqslB81wd#M)FP8T-;$ zirT9xsH&otG8EqPEyQkeV-!tB`-ZR{@+%w&?mD9?Z%NfgA z%Nfd9%9+a9mTSw+%Z8rJ<#zrKzQDpSI7u&$!RJ&#=$3&$Q1rU7K#6Zk%qNZkTSFZkld; zsl7D6G`_UHG`zIDG`+MH*NU5q8;e_u8;V4v|i?3 z#$MK5hF+Flre3xJt-xGhEU*?B3M>Vt0$U@kk-3qvk+qSbk)@HTku6KhGG`gHtXYOE zOO`3i7NJF$Ba9K&2t$M=!W3b9tUWeAHa@mKHaxaGHa)iaXg+2iqmR|c;A8PI`PkNI zYs_nmYpiPwYbwkv- zEdQDQvl%s`*=RIcjRvE|XfoOov;=d4F~OQ(NU$WB5^Ok-2d%MsHNTP>}Yxt6h(wU(ilrIx9dZG*PKyurA^y1}r)vca^$7N&)n!;E3p zFhiIn%oJw3tKBup_ZYhp|%^^4f74-4eJfV4a*JF4O=^{ow=Q{owc2zou!?ro$a7@(0tH%(0b5t z&~ngp&^B9}ZJuqMZJlkHZJBMFZF{S|HNQ2!wZ1jHwY)XGwOKW**=n>}tp=;bYO>nq zYxB+Xjq|PZ4f8GYP4jJCwXWu_#;(?`hOU;brmnUV+6nUs;|c2t!wJg?(+QiO=4bXZ z`dR%9eilEIpKY_Y*}U1f*}B=V*|OQR*)~QSV;*B1V;y4{V;N%_V|$=IFh4Lpus$$6 zuskq5uvO41m@617SSuJRSSpw**j8vO%qxs5tSbyFEGtYaY#~~RIm8%Z4KajRLQEmH zE7}$F72_4_6~h(F71I@4Ypu1pwXwCewV}18wW+o3fOf!qz<9uVz;M8Fz;wViLz`iq zVVq%|VVGf=VVYrkrM)u0GQP6DGQ6_9GQF~u)JmF58cSMB8cJG9no8PIv=noSF~yo< zNU@}tQfz&+KIT5gKGr^lK9)YFKDKk(IrBN=IqNyYIm6()WS(T4WSwM~WSL}|WP74LF+VXru|6?8u{<$7u~pNm znX4JAS*sbUS*n?;+16@n&1;Qot!oWyEo)6{ZNs(U=HbTS*5QWXmf@!1w%gim^KIj8 z>utkr%WczbTc8$b4m1W@0}X+eKvSSCPs=ms8S|`phCEB2DbE(C#hK%ban?9PoF&c_ zXZxUiFn=(9uzoOnuzWCmu(?~6wKS<)+%2_?4W+)ZiPStsNgbqFY9pyBppKxa)KyY1 zus~`AsL9+fb(+*}QqPHxL)|B}pwx#_GfEvPwWZXXwvZZB>QW_F6-fOmHLcXSO71JL zht$L3?@%{OEiLu6)ZCKmrZ$&)U21r#>!sG0`d{+WoCoK^`EX907w5+LagLlP=gRqV&YU;r&iQi>+z0o<{cum* z7x%{fagW?5_sacp&)hfn&ix|?$OCeLd>|*t3vz?}AV$XUH3Jhx{Rj$Rl!z zd?KgFD{_ncBFD%xa*cc==g2#9kNl$t=mUCzexN7l3wne8phxHvdWC+WXXqPxhyJ05 z=p%ZGexj%7D|(CmqQ~endX0Xg=jc0nugQPpe-Fu@56QpJmA}uGpUah>&m~_<4plxU zmt3oSZXP*V`JOy-x8!r>`}4^Ak_#q3OwO1*GPz~)&GP(t$-|SICtptvpS(V~erf=z37`&@+5zeb7mka;VjzeutVK>U^mE5xFOCnor#jwM5hx zQFBBc617RxD^bHlT@$rVqF4FUL{TS2?G*J?qJR0+U5P&CQ=cXJnNJ;;=xaXpaMZw2 z_eQN7^=;I&iJs?EdqzE)=)e1a`7{5Xzvt)pdH3(h@AEl)9-qtS^F4eY-^=&&96S%t z#q;r;JTK49^Yb3O5AVhM@t(Xd@6G#j4x9()!ufDcoEPWD`Eib%C+Eufa?YGL^`x9X z_dqQw_rm>9$I5+iZ=(P1d*nX3SMHa4ruLS5=l+oc)rK9CdS1-U_fkR#*?xkA2> zGvp1qL;jFM+lM6GBZ0y(QF^(4#_)%Kxuz0K36APwh=0SPdS6(cmQ541R*i;3`-Q-h#pW z!~f^s@pt?TKg;j%yL<+p#b<)4dkV5uSx-;@Nmco|R|j*?9-vg?9oIc}L!r zcjnzW1NpPN?t?Sq?>S3;o-^k6IeR`&KHptm!(H)x+#%o3-SRx#InReI@Vv+f&yVcz zKFAdBhph3w$RO{JY;p$3EN6f$a|XybXMpT;2J+eYoB_JR8K6U)0lLK*pmUr7y2u&G zv%C2ubeAF38OoihLfI04U}d3XLk*YoqdJHOAn^Le~GpU=DVeY`v0&%5(HygSdA z=XqYc^}@L_v77pU*6sQkLNtxf5*>w&ddF~e1_*d-Ji{Oc+T7X-8_TmKHSg7 zGkWgJ{p`Gh=RV!<#yfiMn|Iea1CKno&xXJE$cy{z_Z(wkNmmsf-~^Q zr~9rr1CRW=?~*g{$hZ5hIRoyVGe8zN17w5qK~^{eWQX%ZmN)}si}OX+I0Iyl^G6mr z17x53K~^~fdG=1+AF|9D$h&poem(l03)33rTvR+c_I0J$+4btc)83sN(qZCwpKi~? z{6B%S_5b8~m`}Hf<3l>!oeY0luTJdj*OiiE7Znea-~OL-`in59?f2x^t2bh2!|QH4 zdUtYR&cyKrJD-Qa@s`N&|0L}zpKeu`gmi%KO_*1&PE^9{N*Vg1;+%elKK(^hg6;Q& zc~@`116N(L?P%Ipg*hcM3UugPl){_jdL#(b@T3i2!Gnl8v3tk~N)$CCfXzl`7)g zQR;nMNv~&dQ@sk~u6X?%*S7SjxQx;V;|yhX#EmYK5qGLgN?gOT&bXAak#Wz5gF*()h$5gIfI%ZDw*K=-F|8-7ajpK9H)ySHo)l8c+vgXV=M{3H{v06cM z5^MR*xnHZ;oG!JW&fZ-6(rlaWf!SkySIs`@i_C=1PO1|$`(Yj5+1>ptv$y*FKFe13 z)U2^}x6L|PH+hy{z45c=*9)F?zg~k`AJ;E3>zn!yqm2ztMvrW;Ioj1AF}ixgu;|!^ zj_6wrt46nL^mgXTMptM4+i2g+fsIpV?rj_~vviYgGbc5vJ+q+6hZ*&oUZ1g`>E0Rl znx@S7s9E@owIYr0npK%GxcSSd{ml!aO1Ib)HK|2x)R`6oqx}3EMpzYf!j&=o8zHYa6%JX)SQ+l=kXv(JcWv0AukFM;UysN|9 z$+nLDCy(e@dvZ?4=aF84haOLnAA8Y8*MK)4NH>JDr|X)v;pIG{>k(XB^EY z)%@uF#F-zRnRxD_6%&1f!Y0lRYCQ2m(3^-losUJ#>AWQ3Lgyh7bw2iunEmmS3Fkk~ znc&+cenNDY;0b5Dl$}ts>#gxoT{n$C-4#7;HGXop_v4OsJ2tLD_r>GJb?-m!Q1{B? zO7*xCKC;K=@O?cZ!mYtA!UqTcJ9b-e?$~$131fTp>^gRB&thYr_B=nPQ?F%XQhN;= z^II?PG0l7b@9deqh9&u=r1=gq{1Od6>_qe~%pZY4*tdpGJ-}_HR70PyfdwR`=gN;`jdH zBm4*Wjffji7?jg8ZIYRs;@Y*a)OiPBy08=C8wGxr~Atn&3k*xX%CW9UnZx2 ze#}$3iM4Vgy?Q3d?c~ZW{X2HB+?X{uLT+!f+~S?^Qavimt@fAOT`aeJOm6%AxXE(! z;PPpageZ}SnqA9^bOei(#EZ1#h}1lpFk2+3&c{PUnwE%E9TVw#6LCQ#ZMI09Z_o;n zzB3|)?aLBsz~!;k?QA>IU?aBMAB^?=Ze(t z73se_`MqeuCeesq?IT4y){2%Ch_<|)@<23av1m|>wh5w5yF{yQPW272iI(|`wuOq; zC5!g$7cIOq&D^?}Xk{zW&QQ_Pg`%x{L~CzOzbzV^Ae!vwKTxzfRV*pW#R>|p5;Qy@sCY@x@#*X?wTlT_`Uz?V33`4mC^}QnG)+)7OVIVWpzN=Lwy)>R z5#+60y}qDukf8BULFFle&I<*lGX<@`6VyH{=v^o%{wAhdl~RK0zJl&;1?Bq)+J_11 z&k*!a7Aue;)*xG~!cnmfSHwy@6l?J|wo8TLVm+#g6=@>Yq?1^czG7WM#mYpAwQ-8o zNfGOlAy#OISfhhtl}?Fu`dO@0p;)VDVzu7K?GOvrtyFojW;MmCH5Tg@AXcukSi9b0 z^#+Ue3ll3iL9AhvSj9N8jtj&}E)i>)E>?4$SkEnDMR$rd-7i-4kXY9vVr5T>wLK?R z_mWuOYhs0e5o`RLSmpa-o&OLk{g+tlXJWNqi1mIYR{XVC^S5Hv{}b!}Uab5FvG)IG z^|Ah|B^TUU{<-+!gLC4C_s$|8{&Q}8|JLbv|Jr%;zgNzg|GjXQ`R|!?=exh0J>LD{ zy#MyTQ-AxL)939k&YU;boc-Tiaz1^1&YArBl+*9^5$BPA4>>>ocfa$^tDVlTUTtwU zf3?n8@K3rk{GTOG^FIrmnJ?p<9bQH`uf3Sy_Iko|ShFcvi&u_tW=rUp{>nSN~~YoJ^973wv@Z?!#XP<5vH*Bd*O~8F7~%r^HQp z?2Ie%I5KYgpP_Nx{_Gof?@^~X{ZW&+s*kG19sHws+@L?+#{Tp0VQkvNE3r)<9*r&d zUAAHTo)L@Rwei7>*q{etvA^E$6B~QKZEThMzOgy?O2vlUdlU1rurMaA@N7)8!tY|v z-OY@NxVtc>=-nwX+kP7w)9tsQmp6#i{dLZWUyslE-|eh9Yj3B` z>3DnQoLj$qK4;D^L36x+@tbq-R}VbQfOJED(Ysv14^(%YH#OIK%ZzqoH^uZyWOpZpXtbLmgrX8QkB zd*+o3A7(^fxIUxGg}pQK&Zo>6c|Lpw{^pi*Rb~XAdl~iQY(do0vzww?osEsUUNA5! zwxDrT%>r}O@gHwaANS*)=_P(#IDOBV(CLHDw3`0zbg}7~r|(Sba(e%?KTjo3OFb1j zt<@?2X*W;Wrp2GUIkoP|T~p7VNSHe9#K5VQPt=u0@wZdP950ws;`rJrdyhp<8G7ua zDaK=Err_)LJGyuB>mzd~%O=Ok-Hz0r{Pghi$n?X9BOQlRBOkg#BbT}wN49gln{+q- z^rXf4D<-wdA2sQAUb9I_dG9AS&pR{mX6}lK^K!!`HqC83@y4My5s8P6MKnFMB;v*o zLn7w=;2Y8GhbI$m9?Y4r;9&fO76*eT-2T4ogyipUjc@(^rt$dMOLAI`?~wC;+#lZ^ z8@J-S#p61E*MHoz1C__EJ#Z(y=Yh@PZ}vxoZ`t1>JY@gBW6k?>$L`&iFm~j=u4BFS z6&vf?dwxvh-eqH|?Hx4c+#c^SaeIFGqRF1jFK+K1^~I9ieqT6tKOFrmd;941*%71r zXEz>g&VD-Tz^?33;k%}c^4`^a6h403&OKqxcTNc_{I+@6if{iO8T@Vb$oE;1BX?&t z9yvPe@rX)U+eZ}a2pFec+|Fj!y9fZ zHvI0^lb^5LI`{LwTLVA0ZhbQ>cgwzE)3;0-)^JPxVTGFuKU=*y6TJ#?eE3Hu?;?^3CPJOTSq(xaT)PgRS4Z8FY9<_Mn&z zV+RFns5A4J_Pg63^ebPH4{u5%Gb8GJROIefNukV^3 z{k+z^>w9r^R^Mf-hxZ-0x>VnatMmKFmcl-3R@Lkiy6UIiwN}OVzW;Ue-dn%^tyjd? zslA$g-Kp2hl}~$qzjAHQ*pwX+bef~}(y9*g(&L>jrb@q3YQ;{Gsri9{so{YoQoRCiEy?MawPZxcm?gH3y_W3i zKuq^n%KP?tDVy4-ru1q*GUa(Y|CF!WSyCMBu6_BS?e;Ghw~hU>McaN~UJLO3GA`it zV&8y*#b?@NE{<#ywYXfH;Kc`9S6>|3`sE^X>obeCw#r=8yOnJGY1wR_ zeB1wGa)ST%WIz9eD?=2kMoOm*Q;o4?X7Jk&M*TQ>E{T420 zYFJpm>8+%KCOJuynk-8y-6S$;Z{wax0~^;%`nQoKX=S6k3)(fxUvR5o#)8;}a~4!@ zIAnpVLBN8M4Js}$Hh4AvoBBV`|G57C`Sb{+~ z)$iuK?tZ!R9@fd6msE#X_KSHZeS6Fs>)U9a&DU$*=Gre4yVSm(c)wO|Vq&cgiM4Ab zB_63cF>z$g{)t-6c8Tk1)JP1hVN1MK{mI-p)vwI0Ts?PgPPI*QL#n0B{io`Txy!1C z&TU?```q(BE#^-2@tIr9$2xagm1havs@zPt=Y1j}!FzW?4eyME+{z0RKC4U|9hR`7 zQr`ssN*xj|RIHycv0}x9q7^L(TPwVX?^5Az{N3_D#XHNp;;WR;j?XEV89%UGYW(xE zdVEURDe(=4lbRy3^vVds`~#2h3&k zPt2wCzf8sTBvTRH*JRW4jTZegqe*{dFzRUrgWlMn>8FLZ8SQ3oG=25|G`;oz4En_n zMt$N3X>s{r(Ko)g>5lhB^qc<`*Ju7$N-y(Y8GYxw3VM%s-unHw)pY%BE#2pBT|MVb zBfbBd=K9muZS>^V9d*Cgo%JLC2J4^y`-%SM)nNUrS0nW1ufp|$e?7R2`Z!i0?vG7^Fw z>`wUg{)vRx`!^G++<%skbI&?A&qfq{NQ5HzeNrB{y--FV_>j ze|edB@RrxSA-7~J`pq8mR^I$#UcgN_o6LDLZ{*IaD4UYLyZ(0GpzD?9zrNOH{>p11 z^8>C$&A)#2tNF98?w{{{_2>CNTzNHr*p-S4-v1o1VC~OC7IgY~&VoCaGZrLV&RUJI*Sn6fbM zeEPzX!Umbo-&?rlT(RWfbNRxu36x_==hJl7mfRI z#-b8GW-i)u=FFl&XI?IPce?uG%+tY(yPS?%{O766#i^$X7PmU}dhyMZzF)?l?Du8e zld)f(J+b}EX(z6ISy{HOmyl9 z)*ZREq}!1asZS3Frluc`Om!U2OnvCOn7Y(uUfRypdgr+R|3}=a=5jGo~fw zwMuKAH!kgFZbsU?+>2>VbFIs69BRKT@zCUDO%H8ecH@Ve%jW%1dU>-Sx-GwXFmCyR zgZr1aIQV$^?eA-UmHhqCuUdZ(Pj=?3B{{|w9dg>Q_~W~2D^`4$wW9NP4^})oP(6L^ zfg$NV4=hW6v;S=Rmi_jXA^U??n)k=9+`I4ll_U4PTh|vItCsApxZ1IM;Ob}D%T}+?zPP%7w$~bScHcDzcBQNd-*s+{ z_bxcP-WhQ_Q!<+GJeN`UZOOGOzU{j<_}kRA@3Sth-JMl--RP`=>ndfXuPfMbeO>$x zpUhS}LNgz2U!S>d`~A!T+v}|_x;o>VumVPsR%av~$Zt>YzxH)X&>do6W_TT(;WAV+cHysmpFjoG%^`_$TZ~DvMtd^fB z-0ZWlq5Q^l`OVxdJ>^rZ-}IGFTq&P?cWc0ghVo5O@{Rf1BIMiatsfvyvQD1p(e_Yz zI-ksVdD4O%>GISA<>||=+bwVMJ}Xt;s;|6V$+d;wo|Cstk+<$GZ(kzATTUWePUOI@ zzH&NVYx>Jct(OyfmOW5Tuj1+@a+0@quaQ#?mD8=Y>fE0Da@t$v)Fb5dn|#Ba;sT#yVK;B+skbmS1gg6hZk)vl8`JC zar^tnA|3lhO5#LXx{1`3UOrDG=*AD5MVcmyRJ9lBvMy^Xk~U8y?q=>dk-kBsVtf^O*H82iCEF5exg;rU*0_VTC}V{v@KJ#E=sgdwvUJ= zzB~O=wDOE-XQpWB4AIu!qP4z@YKjKOiY8w#*e+U~Alf}twA^2`y;$;=bN591^8^Lb z1r4SMD)bU`@Dr3UEc6$|SSrZzp zpizLJQpE+s1fhPo^0T1TenG9T1ihjJ#X9#QKDZ6&fJc zsEb&oHe#I`h?VjYYgJ0DmN9;SSg@RDkHnhY7OQqqtlLSka)-p)?GdZDMXX}0L9BEcvDT%;Y8MylEpzn6l5c!(5vy(z>uwY)ZxCz$e^y`BinCXP-3*;V zlVjQ8z@CiHW!HnMA!qLeyCc|d@j!M=WXT>2c2TI>a{fR6j=$q)_*s5O)tvKLd?ugG zcko?&r{s^^wdm~r;?L}W&(EtGb#{aDdCa%x^Vt>5_o>=-_6G9|?)|ay4DDo2 zKhL0Q+Sx0}Gq4|kXJF45&mdnf85B+9&pZQv&ol7zJcFu%=ks_5wWD6`Dp$4fYIm{P zVXJnTs+xH|i_cU$?$oX`b^i0N{m)srV6;{t?0?RrQm3^&Yd$!$S2Q-T3#Gd3#VA$h zKj(@KuM9s;ee1mH_nC41l-JIU+wzUrEY z|HRA=74~b`|Gw`Wmf~%haPl{2OU-F{+~*hPwn>GSFJ-?|S9{M^W=3=a%e__C2HaJ6CBN?8~R`bhhhhEy7+Fc6pTFzRtPu z{JA2B&ZRpK+5L;|+PK8IseO7;cDAtZW6|h1=ejRLi#hv5Ia_5NEq3{j3C@K_>$+ut zdpOW?uruoB)8hT^^>(J+>|bJ3m(I=^m%c0UkL-FWl)WJ(eHuG6wmD1gTUyik#e%|; zPjbpTKYZ4$)KS?3!)}odKJVkceOS^fbnvsdZkbcPT6HaqJJkD%7dv9k$^H@VHmBko z3o}Z$ZFey4as@+~Mo)Ld_4#^q8TQ9aVu#SAl(;u@8kP-d>x|33nNs$}{>ZpNO`n%# zw+wqs0+08NbMDS5_hC?{xOu-;DgW!5CUNsMXZb&5@65-t>!g0i;&F4myHwb+@@=f8 z?A8jCH$RO1@_o^YDYBD>eJCZaAC3KC%Y};nzR!+*IL5!y(4RA6>sDOh)&=Bo|LPgB zfAsjQ^6})b*ylgyR*q}bC$>sp4R3bY)RDa^-buc(SN^`|T`8zk?9&$Asyy5ICZ^@6 zZB=&5o*Qu*MSEox`4& z=2f%i6kDU!Tv#k^&bqxLYi|8^=A1PLj?~PMy*liInO!1i&abhFwfg?(H)rQZ_iHuk zSZvO}PrKA+=T4mLi|Nu)vR=h(zTfxPS)`>rDbtkSnHS1-@*t+ExY@2nl&B?m#@nJX3 zfT;1azOOmIUg?!K@8iKCa(LcKjsD{+iwAA4cb#G&Wej<7Bj9_s9lb z9XChU(OnJ7CMHJzDLZcR^|0uQ=VKez^LIo?_PNz?^y;e7-|uPHC`on$u?J`Smse-D zt^aSMUn}mL`L5l-#vKQz&OF&{Z)5fbu`B1?yKXbnPEKmlIJEZ6YT*S|@}p)mOyM&I{=C-Rj{`=QE>mSjiS)tEi#B>0^?C6A z=0WcZqD;S*Zow`h_VS!L9vc<8<4lX5xdWq)-1YO1h-e&@^ftl2i|i?4chA$mZ%$uu zrd`Xqr}j+mo3Nr~l|c)qZ>jveB|D5lWWP`DnpV?&A8c*)wtund*S*cHzd3qmTKguU ztuM%aqq4FCXl+6AvA0jwN34h7cVpA?1%U5m0j`evUl>0e!Dt+h@Lz7=fk#+Q^xk6+_1!m zj$g~JrA@N8XvOsBktJGq1Z(@W8~0sgVV_`GLD-57T$D+o)0h#*sNYCv_?l z`fgJC5ezIx&Fvsbx%AS6o(Q5p%iIckpk9xzH9lOM|wrA&$i;ZnuDi-sZ+2I)XR6ry%r7SO`l)wX{-`f1T5I-6>FoE# zk|mOvlf70OWfzq*b^B<)(xv+54~ZCEXdm9U#Qnyjcbw1ayF_+gv9D@kQ1+;=Pxt6o zP;Sbo;s2%gyS%OWsEGIX`zb$Sj?bR3jpO1!8TWQd*rdznKFL_!JnV3BpHBm2R~CD( zX4K0b+2#KJPbZX%99eOmv47WNjYsbPyH9`iXg!tPSbZmNACcbd_x|T1!bij!{RjNq z*l)zN%(wyU*b0{YS=BydhFnMhu*G*E_Upi5&wM%Kj~OY*oLtZ1^CX zBjj^Kzv0_jCWlOVTx|H)jV_0$!GH&d>7xzck>K93(v%} z@r*nx&&;#)4!jHR#Jlm1yesd_yK@Gd1!uz9a7LUJXU5rahMXm5%Gq+poHb|8*>eZn z1$V;Ta7Ww~cgEduhukH1%H49u+%5o86KL3WTKWC@ux&_Q$&okTa$QFIlZMR(C*bQzsSx6yHQ9i3PHGFSj6fDK>-SOI2$9bgDp0;Yg1 zU<_CT=72q55Lg5zflXi(SOsQ*U0@hk2Bv{+U>sNn=7D`+AXo?{f{kD#SP5o=onR zHew^OmDo&dCpHvYicQ6~Vq>wjZksE%7aNQ%#wKH%vC-ISY&NzV8;&i zW$C#qi1S z&G6Ci)$rNy-SFY?d9j#^=WO#s|k2$0x@($4AFk$7jcP$A`z4$EU})$H&Ll$LGiQC*CC% zASNI-AVwfoAZ8$TAci28Af_O;AjTlpAm$+UAO;~8AtoUB1R%sB4#3XB8DQCBBmm?BE}-tBIY9YA_gNCBPJs@BSs@u zBW5FZBZecEBc>y^BgP}vBj!^)0I?u3A+aGbBC#SdBe5efB(WqhC9x$jCb1?lC$T3n zD6uFpDX}RrDzPdtE3qpvEU_#xEwL>zF0n2#FR?E%FtIQ(F|jc*GO;o-GqE! zHL*1@HnBD_H?cP{II%b}Ik7o0I}2Qu*wxN`o{=5y+%LP`xo^e$unQh}m?%5qk&lJ4J05vqXCU$uCcEa5r&Y3p9{FN7 zJ@UrRdgPB?_Q)eU?vc;Vd+I+$UfDf}{N~RHdxAVS{Nux4$oHNxtN%jY*-wc4TN5uo zMj!h6PI-)eY`sw8G5XR+b{L{RdY^88qEEAH+|rzY+X%E=s%u9^S8A`wsZ{{QTix!OKF~@d$pt z9QD83;OU57Yj134XtR`T8b! zzBOs(P4N9}i-4Qpz2f=8ew=v&4j}ko#T(d%Wv=h8V=ve_iT!9>?)5e7N%63i*RU^* zPX%1V-dvTvl-QrHw`X0&9_>%@zKVVNeDDufuvhG^#C~-Pc>go@>_eZmKV#o+I6M7} zy(=gCEwO(On@J8$>|yHe+Ly79U3(wDguUz{J20`IC$89K1L)P6=HuHhVqXK!_qvF^ zWltvdcVfWOpRmWjrThPcefBSRjLu5W8b$o7Ud=CHMzZy@@;x7cqPEP!X)B&x|;!kv}dc6SuVx}dw0DmL8M9l*HkLXs% zf5ab=s-_?DPX<3I@gx2UyFKw=ZdM+227jjR{dcGFZ;t(xc^ZF*{h#bqarp9ijM7Q|iQ@#Gi^V)IEuRHA_2t0)OkQ>=DKP+7Mp(1pZi)i}}a# z&$fn+IgY>9U3QJ)zjgh6?=k$jtG^9BhJV+>U_6Gur+D2uyZRl)A8Zi#`Uw8v<>%{; z;4iYX6#w!0*{6r`CojEBKa79rALKZUzsX)x{LgNmEOp_JhL>&U!ax1>zq|SPt9NDh zDgNu$uC4O%XTR8TI}iW1Z?mL4{9X2=;{Q5-xS5MT+%#`qF8=Xve>Ba-Up^x{RNek_ zZsH;Q>9SumJ%oRKtM!c^@V9r#o>lyB*WhM9;E#9ScJm{``p#H zzsH}ymY)1Q{{1)kt-r_LSA2Fv+L9dNfuA~d$RR$MUH*^nh!@!DO8hW3xbt_!6Q#F4 zJ3xGKw#C{5#2W>&_m%h~=)#-*#3NyaTlN#54EGJ$PrSlzSmKvG&Gzmio|*jL$bG~& z7hiepBi>K>+#O)*=T-vbtPU6GB7lq#vFD{jxx5SSJy@S6co_sj_eHQU$aLL_S#GCBJCH@RQ zUnz@tG~s>04&u|rq47J2SJ|CQ{Myja_b^bQu z;gBDrwhIb zHo^h06BrI)<B4j^pw zxePdf6_%6?IDo{$-WhNJDsR&;#`K53Gdc`$M;Q-hj4hIl>z4cN!fWI=$OW^=6WnD~#17Hs}9Kf8k$W%Ch*%5)M zZ~)^Ll}LpHU{^LAK+4LjC2#}hL_$vht;N8D@DR2NQgHluA z02<5AZ8(7I+x%1D0KSt-5;%Z+^{;&i2f$u#IDoH@#(oJ0Fyw8&FW~^L&Gh{e4uIX= zZ~(F03KqiwT>mj=W5S1ITW9JrNFI-t*i$P+IoG!vU1Y&7BJekbPv+ zTsQz*`INbE0PK*511OmpIu{P$=C$r~;Q-Qyx0nkDz@B+HfKs1W=fVLz%zc&s2XKGp z%>+1rva*XF4j}&0?gTi1c2OA#Z~(!h7bd^~sC@LM24M+s0Cr>F1UP`_ejO6v0N7~{ z2e4#F#RNEj!DB56Z~#}2yoiSbVDCK~K#fs9#lry@wz}fs01mgyj)wz?sFE2E2T(jX zH69LN+X+1$4xrD{De-UsrtM+zZ~&LQ2E@YwoH*Vk9uDBasW$QMe5rSXcsPJF-}}VF z0c36|6%Pk+w9pvu<^U$W(%}HgbbF-30rZ-5TZaSqyYQk82T*kDNgWPg&A~%D9KfzB zdvrK}9zSl;;Q&+~zF~#sIvjw$J6VSVn7%q*hXW{aIa-GU==a%V9S)##^Kcyw;L*Sl zIvhZ+(}Q(5fC-B}(cu7kuL;)S0A9W8tiu6}+ul)!1IXIaMu!79{Gz!I2k>o5BOMN4 zYII#44xsGrS~?uSav4Dg2k>u6ZygT6(XxUL2N1cnj1C8oG@+CZ2e3G{xDE#pd%K7Z z2QWNEYAl2UX!4~+hXZ(a!=%FjY?^7*;Q)G%GU#vse`IJn9Kh_lnhpmb|Izs`{tO4e z-@^g$^KbzCJ{$m_2M56C!vXMpZ~%Ni901P)2f*{e0r0$V06ae&0Ph0_!27`g@V;;W zygwWO=K%-6`M?2iUT^@M9~=PZ2?xOW!U1sJZ~&Y?902zL2f+Qn0dQY%0NfuO0QU(8 z!2QAjaNlqMs_p`LfCE52-~f;pH~{1a4gh(A13=qDTi`U(et{=xyE&u{?fHyi-^4hNv>O~3;<0Pq100K9+$06*XWz!NwC@C6P4 zynzD%f8YSXBRBx?2@U|ff&&1*-~hlgH~{bs4gkD^0|5Wv0Kh{y0PqnG0K9|)06*aX zz*9H?@D&aKyoCb*f8hYYV>kft84duvh64b<;Q+vMH~{b+4gkD|15kA~*aJ8K>;oJC z_5uz7`vC`lJ%IzjzQ6%sZ{Ps1KX3rpBRBx;6C42c3Jw7K1qXmVg9E_6!2w|J-~h0H zZ~)jtH~{P;902wb4gmWJ2Y@|=1Hit*0bp<80I*Od4IBXe4jcgf4;%pg5F7yh5gY*i5*z^j6C42k6dVBl6&wKm790Tn z7aRco7#slp85{uq8XN%r8yo=s92@}t9UK7u9vpzGtHK|I1HeCo1HfN|1HgZT1Hhkz z1Hiw81Hj*e1Hk`;1Hd1J1HeCp1HfN}1HgZU1Hhk!1Hiw91Hj*f1Hk`<1Hd1K1HeCq z1HfN~1HgZV1HhlICL93%H5>r`HXH!{Hyi-|I2-`}IUE4~IvfE0I~)N1JRAW2Jsbf3 zJ{*9mCnFw!10X(t10Y_210a5Y10bG&10cSD10ddj10eo@10WuO10X(u10Y_310a5Z z10bG(10cSE10ddk10eo^10WuP10X(v10Y_410a5a10bG)10cSF10ddl10eo_10WuQ z10X(w10Y_510a5b10bG*10cSG10ddm15kBz#Dj1E#D{PI#EWnM#E)zKieVyLkqlg=gZ~ct)O;XXe>?2i}Eu;@x;h-j#Re z-8lo!f-~W4I3v!AGvn+yL(Y;jfGJ$L$BghIegX|zf$PzMzY$0RF8Zw9MA%n;wGKp*=qsS^Ui|iu9$TBjG zY$M~yIx>&!qXXyyI)QGWBj^e`gYKY1=n^`GZlPo78ajvWp@ZlmI*D$gqv$F+i|(Ss z=rTHuZlmMqIyw*k2L^xzU;@|xMt~Jy2G{|HfF)oG*aF6YHDC_d0|tRbU=r8_MuAme z7T5)bfn{JC*apUdbzmOY2L^(LU?SKEMuL@KCfEsvf~8<8*b2siwO}sT3kHM5U^3VY zMuXL0HrNe@gXLg4*bc^n^<%dzR$c5FPh9-FV~gYgCM3GfZ@5%3l88SowO zA@C*eDex`uG4M6;Iq*I3LGVTJN$^eZQSeppS@2!(Ven<}Y4C0EaqxBUdGLMkf$)X! ziSUi^k?@u9ned(Pq41^fsqn4vvGBFG19F z@$mKV`BYsrz92p!z9Bv$z9K#&z9T*)z9c>+z9l{;z9v2=z9&8?z9>E^z9~K`zA8Q| zzAHW~zAQd1zAZj3zAip5zArv7zA!#9zA-*BzA`>DzB4{FzBE2HzBN8JzBWELzBfKN zzBoQPzBxWRzB)cTzB@iVzC1oXzCAuZzCJ!b`9ER+VgX_TVgq6XVg+IbVh3UfVhLgj zVhdsnVhv&rVh>^vVi95zViRH%VijT*Vi#fQjNK8mNsLLXNz6&?NeoIXN=!;@N{mXZO3X^^N(@UZ zOH4~_ON>jbOUz5`OAJgbOiWB{OpHvdOw3H|ObksdO-xN}O^i*fP0UT~O$<&fPE1a0 zPK-{hPRvg1P7F^hPfSm2PmE8jPs~pR05g`Dqr|Kv<{>fjh`C10E@D0rGl-Zo#4I7^ z1u+wdxj)SIVSW!YdYHq*tR3d*Ff)g_ILy9bz6~>Mm{Y?nn&&ccg_$zUjbSzn^Iw?p z!W|ibj zvp1Np!3+)NWH1YZc^AyIU~UDoDVRUOj0xsQFe`#tSj>E2t^>0hn9slr2Ied9?n+p1yf{DQ(wo4#v$tLdMnN18rpdY$QKre~SHWO|S3FQ$i> zK4E%+>G!3lm%d$kb76nzv89ieURnBK>3OBEmEKkQQ|Upa&y-$L`bFspogBao{y%#B=;NbTkA6IQ?&zzd zcaHuzdf@1DdnmnZ^sCX6M&B8|W%Q5HBSs$>yLoCp*zgNLVuWfg$^;>3O!L^ViO^GK5TUEg8bV*0DTK~4I|#jHMi9EoEFkok znLp?-vwhHGX854X%<4g(naP7ruant3=ruET&~0Yvpx?~QLC2YmgPt=32VG~@4f@VZ z8+4x8HRwGvYS4XV(V+hmW#$YRz-$?CfEhAi0kdMj17^a23Cw;07ntz^HZaQtd|+k^ z7{P27aDo{uUQzzb%ofEmnA0XLYD0(LM91^i&<2^hj`6L5qXCSVD(O289ll7K19 z9syUFF#@(QO9XsjW(XL=Y!GlJPG*3BHO%?|Zd@0e)-<}tef++#)o*vBja@Xsh+iC`eJ1;9aO2!Msm3IGq82>>S2`wuSC;}15{ z%MU)%vkyknn-5OXgAZ2HYY$%1Qx9g+I}dKsBM)}c3lDzM^A3j6+YXM>!w#0xs}7#h zlMbfRdk(JBV-B{`OAfx$GY-bm8xGFW0}j^G>kZ!0(+%d*yAAHrqYd`biw*wLa}5U5 zTMZ7=Lk$+wD-9mg6AdQQ`wTAA;|w;_%M3o#v+V9umfmD=njU1ZnqFh@nx0}Xo8Dn? zn;v1Xn_gh>o1R}VoZen=oE~1VoL*h-RDY}Lqf-4)s;^1)C#gOo)i0#_epLUC>cdg}G^#H~^|z=#71eK| z`bJd$tm@;S7K5KreHE%dLiIVQeg)Ncp!x??AAqXoS9STSzFyVIt9o~G*1WT-KUa0+ zsvca`b*uVpRcEd0rB&Uts$W)h$f}-L)dj2iUR9^7>TOlsEV(aaK-ICTdQ??cs_H{k zou{hTRCSlcPso6(gH-j5sxDF07pgiz;$38bxEUEx^>?a{PSwMyx;9mxrs~X8y_l-| zg1e}vHL5;F)w#e`Ap@%JMAeU|IuKRQ zq3SYJeTAx%Q1uR~Zb8)_s5$~w51{h;DnGCC>?&Wb^4=F*5am8;do?7wEiZ@pLui|kPAFFs(#g8hUQ}LCG zcU1hL;sF((r+7KVuPL5P@m^pjP+jnH&hU~m|&n#yaHG4M>$c_hgZ?Nw{=I?is+3(EvX1;SEdpOt$!7h%n zvL8a`@pocZgl7(PAbUC3AtAH*JF!oK{T%F;@XU)2WKRb>C)m|-U-nP1uY+9_p1IP2 z?Cp3eJ1W@SA@k}3WqyCBVA);anLi!K9uIa}u**Z{+Xu4GLuTDGr<^&}f$a5=8Tf(h z_Fx|d`#so=;hAS0SX1_Vurq^QAMDRy-v_%iJaezzdq3E*A+!HGv2TO@AMD=n%*S@` z0XZu>IoJilevaz04}@JEo;lj?y&&xHU^fW+JlGGyZV%7A?M|BP38^DHKiCz*{txzr zunWX9m)pHJM0NzYcZaYqg#96Ehs+C^;m!Z&-|=_s7vX2wHNs4HK7-HVGx==3gYV)y zJ@dfb&%!hDY&;{+$}SUT!1E5g3-83c@s7MJyH7mx#ocGYnQ%6o5og7&6qy`g=`^X$Qm*yv&!8vh%6$L$R;w1tRl0Xx$ACOMy8Q%WE@#X=8=7L09`;Q z&<%71T|s9&bKKp!gif&=1sy}z&^cz|ql4%oI*D$gqv$F+>zNDRsgdkWL8sAebUan| zr~Kaz9kgHP&xiQ4{QV*RUVc88pZCm}=ks#;Jo)@wKA*h|d>^ye`F?qxT%L#B4LqOd zejd-u%ywqC%lqW%d zuLS2U=kJ~w&%O!nL+&S!`(Y0S_vM+Z&wb``pK`x>+^^_<9{0`cc`$%|7RZChM;`Ja z@{)(Vc;@sYPkG1_yD*S1_F^D!B7g3E3GB;29@(9Ne6mLad1dB37{GoF;geQ*aw2Xic7LFs>;XYv zJ$nhzXLg66-|P=T-}BLT(S7#}fA)!h0qhn51K2YH28izGg8}Rx0Rz}Y0tU!;<%0q8 z-R_+L>?;9}h`fC22m0Rz;Y4AJF$Fo0b-U;z7bzyQ(xe2@L-&*(mXf5`Lm>{)Q{ zn(%xcy3gmM`+Og|&-bJIJP*3h^W}P;7v1Oi(S6j zk9?r}$P0TakRNm(c|!M*FLWPyL-*O4f$k%Z=sxn9=aE-*ANfW1-8*(X@{R5z@8~}A zkM5%n=sx;^?xQdH9{oZ0(I<2t{c`UI0s}nyhwh_~=sx<1?xU~l3 z=sUXa{>Os{=sx)1{#ky(Q-0#La zdhpKu?wo-K57B+_(S25&nFl}7efJI}55Bt3nlty{ulp{z6AwPS?}|I~;J5oOxl<3m zyYHGi_u#)<7LW;#eQ?VPGUKryZdpR6JoW|Mcgvi|{tF!J9}EBs__OFf{(&1SzyP&Z#^X=8v4zhEYrp`H|KY|WFu>!VxUq`o1-rli zk3ZwaHZZ{B@3^rK4Dk3vZfpbtz)H>w>;wZm{*)VA!2plHh3>mC*yE46u^9~T_-ovs z8^b;RoEzK00I;6>_V|BpTYx-Z8^8dMzv#9dV1UP;blVm%z~gTse{LJ(@kiaZ2@LS~ zt8Uu`26+5gw{1hdv2|d8$NzQPLNLJNAG>WO7~t`r-L@1A@c7qmTZ_$A`*=M5xZ5^^ z0Um$dZM(q$k3a9W?dUhQ9t^uLB0)`+$G=LSTTLjoU}USHfq)cLD?OrN97u zD=+|G3%phPgz&|{V|+6(0ACHf#`gyU@a4dBd^<2e?z$6r?}`81z99Ah-w+JISHxbZ zy+rtu*b{t9FaTc@3{d-u@I|pl_@-b0zAE+#-xUlHS?+{A!?y(k@O80wBKw`d0DNKW zA-*vffUk_b#CHY*M3>w?HNG|W6<-?+!1u=f;)}cOvH0fLXMA-qKx3q z@%6y~#s8`~cZvsAbL$iztme=uURceQQ~WSJ;`A9Po>nj@xoXEhg0@y}|`R~O-A;bzs`F2zTy zIb4dDR&%u!Kdt6uDW001SNgUTU#;d?Dc)MmrBeL0nlq(%Y&ADZ@!4t)l;XA3T&FD0 z97r{%N%7oj?vmoW)f^?od(#t1U!&r`)tn>6gR8kkiVvp;k#1KB#;Fbx^#I${VP;3@U%1<}9c@f|{G4@(F4Vg32qX zxdtk~pym{)JcF7$pz;lBj)2NLsJQ?t|DgK(RUSh1?W=r*>cdxg3DsAx@)N30UgarN z-@D3Js6KX;w@`iQDu1E+%vByk^^L21hUx=Xc@5Rqt@0bHPg~_Vs2fIKRlY;@QLDU% z>WfzS57p;1iAF|4esJ>#AA5ne6Do>*NepS9i_3^5_iR#N$`4iP=tMVwS zZ&u|~R3EI$tEj$Km0wYPsw&T-`c758MfH)Yyo>4!Rrwdy=c)2As&7-}V^kle%FC#} zN|m2ceUd6qqxv3IzDD&is=STrOH}zA)n};kII3?@<#VV31OrrFhnhYxK;?H-pPtI| zsJ=Uu?@@hpD(|EE;{MP7*EH4Vrt(0lZ%yTcR3Dnk3#q;`l^;@lVk%Fh`o2`YNcC~4 zypih5Qu!m*XQlE;s&7i=lT;s+$}6e9CY4`OeM&0Nr239jzDe~Fsl1cw3sU(f)#vm7 z^H83?9hHw#eK;yFrTS`AeoFPps63VGdr|o+)yJapR;n*W<*!tqiOOTCz7dtrQhgvQ zuci7rRDMhKX{bDx>bp?+F4ae&@?NShLgl|ypM%PSslEl34^w>zDlew`3RHef^$Dmv znX3C&`7%|e^L)P1UKZJe#UJSNS$oN3Qa2 zsxDmR-&CEq%EPI;ZIzExb=WE|r|POzeooa%t2~{mdsg{6RmZIIcB(E}iQ+2>9uczvIRen#^>8d=Rs=HPBK2=An@_wo=)~;z@UYb^;lBPAQA*Dd|G_6cC zO{*24X)PR@X6~+O<@#xw?_f=9IYQH{;hI)qvZnb(Yg%hv)9gu_Rw-4}>aEnYfJ{v* zx>eJ>vo)i;ZtM*LOn!MJuK+T|;?FNUJm%&k^ zlEKlehQVR1XK<8hW^mLBFgRK`3=VU5gQHwOgTr^Q!O?Pr!C?(II4VpwIQ*gwj@G)t zVNWtRDy146^;Q}j0htCz(X9rDcecUNAjjZn=Q22opE5XnE*Kn*t{EI1?id^;9~vCh zo*5iXUK<>Nno+acjk=eYQLjBZ}rTxFV>T(tsB zt`-iH%iP`MD%a2C@*Qk)wH#q`S;I}P3X@GPzi5-IwQh3RlT5BksU}ywl_pm}rpZ-w ztI6e^ZE`ipF}d2gOs?XmOfH`bCRd|tCRc|$CRfRaCRep*CRdZ!CRd={td;gMYc(sG zwdOUCjWBDraI;o%vRSJeZPwc8X01q) zS*x6C*6Ob`Yi%>lTCuHWtxC38YnWr!+PlnJiBo2+>IJjb_?lVkc*m@jdT7?FKQn7h zUz@c~c8jC5m&H-DlEu-yhD9q;&*CWC%;KmWU~%|&w>Zl8vpDJuwm4diusCet7DvU& z7DwG^i=&NhaTH0iI4Y-F9Q9XP9Bnf#j$&Iajw;y}N5dS8qrJ=GC~?Z-sCvQTXnf7$ z=y=ECDD}|dsQ%32X!_dX=%iU4cDq$C?Pb+#RR=v((tKMpaRkwv(^@@|NdfjNN-bT0TMUt#~qZ&t&ud)2es%QUmwYX#WtEgW{Oba%VGTtBw-?=Nw|i&X?G1A5_I572z4$4+-RFYc z-sqa$-r*Cy; zn{#-Eb8~La&AB-@HwVC=3CbX8!9R+W-2ws8zlbKgAPNLa1dD=yY*6lh{HIv9-K0dj zX$dS65N+C&^2!6$f<)S)$j2Yw_q|8|zV9P8E>3ZAYMPHz>q4BWi*a~Tic_c@r*I`s z0X0q~v^X`V$Ei&tPVJd-DrLo~1v^d^ojBEY<5b3rQ%ioF+79AW7fL`VoRAPCAz^4j zBCv#r;t6S-NJy(7A?=b0XqHMylXODLF$t;4Cd64TAx-lMXQbI!IgoG;z z38>+^mXPN3gtTcSq&+hsrL2UsU?-%alaShOLdtjvX~|DW+d)F=LP=-=PFe_(v@kSj z5m-`Oz?0TEk+fDp(%L1H&?1$zCh4S=W0F>tO^SS7XJkdhWECoNn_ zT0l)o3tG~e)05Vwk+k;Aq?NLg)`Fe1icZpMyGbkKC9NetX>A8ds|%$_1Wv(YND5v- zQ*aqenFyYOCx{fh22yZ^Op#+$3Z9}?tq~IQuCMV%EHHM_A z6*Ntiv9vjfr>O}dO|5}6RUy;l6qTl?=romQ(o~I2n^Rnxn&H#bhLENjVw#$i($uV+ zrV2`$YN}~#QcF|wdYalY(p1X~KWn9_MLSKEoHW&O(^S?=Q_Fsu+6mHB56X}zoRP+m zjI@Ggq%xKk)DSZiDrKZu zIU^O6jMP*!7OG{Wc|9X-85yZ%W~f;!BQ4q)spMp&j+>FPUPfB>Gty3wk$O;;T!6FI z7?QPC(5zL)vgQJwwI+zHwFa_Qh0KzRRMwiJvsRwTS~WInE^=9GhR<3XLe^@CS!zMb zTC;N2Dkxd2sb;MOEo;r|S!>J4S}ik6Em~P?(au^WCu?=waNWyV%YN3{39?oXLLe+u zfBy$V5rn`H5yKH=oIsFOfFQdh06f=u%WvMwMVj;+ajUYt_LE0`Nt#}BsJ0X_1345BKu-AnN zyDm<^MQOrDCCTyTiNJVYJp3^7nO=H5|GbiAZHDNE<6L!&=u-op0RPrY5C4a)+ z4kqj_G)ZFcB#j}H$O<}%l(9(@!zXQwm_*jVBvK(K$rWl6nW86=JTr;Z*hzDRn?z># zNn}HqL>l5Gg-MghtUQSnlu4wiPFk2YiOlPh$d)mQw9H9r#hOGG?MbBMOd=h3(pvE* zk!61p*$F0*9yCSf;3+y69$^KYqRZHnnZu{-95F?&fhoE|PLX+Pita!1%oJT?r_4Mz zMbGe4^oB4+H^eC_Cr#0_@)TWArs$?RW#zOfdS0KRw~Q&eWlm9fYl>d9r|6P1MR(jO zEALIw%l;I-6HL)PXqv>~X&OhSVE@RUsj!)Y-F)gowX}Lm9lLcy;F3{6*o|%?w z?6g_nrsWxaTHX+*<%T#-;nK7`D^JS>Wm;~k(-y8x%k%oQyk$(wEpwVGSkv;NJuR1< zX}RN0TLo`gUiPQuonTt-K{I3#o}r7#jJ<-+*kx?SEaEeEk(ja9z>HlXXUGyYLzn0o zJI~D6HFm}Cqp^DOsJuA=H1!cx=sxwwmo3ZEh8GFl^v0LU0RkCL6 zMSI3BIWu<0ov}*ZjJ@p7*gL_D-GfkwfKh}%P!vN^l)zAtz)_hXP;?cb=q`yuWeP>g zG>YaJ6s@wTSmsc<%%kYKfTDE~g$XJAoQ$Hlf}%i0B|<~dIUPke4HVroQMhcO=z@)+ zMF&OOE-IBh6kYOBbUQ%NE;I{O;aQ}L%rY1{%MjSCSjA`MDlyBff>~yloP}!CEK;Lq znH)3ARM}av#?8t#ewJAmW|_J;3sT}AbF{kXAb8yp| zQx@zwrRdBlZFf#;dUMK>Kc{R5b4nMQhuZKw(njVT44rofY+h{R^KzS*cUHl?vrEoH z9cmuw(DP1?nRlw}yx8I9@vTAZU_r#LtLN;X@Mc+1+<_npiOnbBD4jE&==4x zV*zcM3sl)!Ko{)=wB#(H9e2Shdkg5Yzku!p3uq5oB&+ZuT}2j|6?Bm)V~b`LU$m>l zBC`e-nF_f`)~H3gMlUjXW|66}i)M{mv}^n#vmq=p4RMjGN{dWYUStZ&BGXhCt*W-@ zRP{w>%UEPu<|0+I!q3@@OvzbfI_{!X^A?$9f05Y<7MUKjL;`q;2FQ}Kf-Wg#Y{>-p zk`0I@WeqGT6>^DeQcHA`UQ+VRl2T)r%qF*FH~A%HLs(K8;t~as%b4TO?ycxIZH~%U9y_qlCtbCDLcWE(u0=CHoQ!?k!5EEU3SXY zvf0L$?KZLOtbt{xLN1dXYMJiP%TAtIc53Xh+2NM$4!`Vd2+K}GT&CL6GSilqor1FL zG}UFRtt~rkec9PEmYtTlOm(bfreiNVC1=^`xXV_@3zz<~vlA>kJs1-)1j8^C!w4J` zaRS3u0fz08SlI7lCPrgej=``hiy=70tG)x3KhHV-c zwr65tpO2Y@jbTLx!`dzemp#k`K89@v7}kYW!ajdRTtQZl9J<01*b0`zSHuFb!mff9 zc9&cU`}`Gig*7k-=dXxmd4wus){SCDo|HZLR*!9 zzN&5-tLmP)$`aP9McAuq(OFg7?kZaLRxRMKs@uV;+J)AjGQ1|1ku|uCuDJxZhLrI& zsX(luWw7S%l53&n*32@!=H{3+x5}>3Wp2$X@N4e6u;$jqH8dx!No9G>#g#P|sB36d zTa%jln!9PNxqIdsnzz=hvc2XOoi(@ZuAwz=&1(8VpYyz1to_y)f`1=IkBzhuq`8p zwai=?^PE|=b6CmAVI4O|mA#zV_H)=yki&X#Ud$tTERW{dGM*PpM4m2#JX@jiW}eQo zc_z=+xV%~7^X!I@XB$#ptjT${pyb)6ny0E-UhL?3cFV}KEh}%<>^xg?@@&V=Q#CJd zcKkfM6Xe+*v>x^+>tYpIhpXtiTE^CqD!wiiiFLFJ*3}BRPFAUPvr4a1Rc2kSvFmh| zTeph*y1F5(s||4-t4ixqRbE#M%DUQA*BL@vm)iQex@D}ZEpwf%TI*KTURO)by4rEq znXw55-C(NPhSbqF+%03nZJ8Tv&DyYP_J&(> zHr$T8!PLABtK)CDJHdwAgYj_qj*B>o;{=Y&;fsU=9N#5zs7T>hk;cU$gX2{ehl?C; z<2)`E1stzSxJ)QG4%F~-8ZHAJ$2Sce-!pNfXyG+c1+0h{ zVgJ2}0c2AI=%z+sn=rsPaX@TJ0BmZz(ns1jSEOJ<2FaW$@Fm-v!Z5=vY{D#NTr5Vw)0w5?R-ZMmszYfW_?t6-{G3Xj@1M^UWMEV`{Nz9 zL+_ZK5D8Lacc>1x!*%!_t0U}q4RMEVN;^tT-m#m?j@MLon5MR)bo3pkY3z6{bBFF& zJ5J5su{+L=*Kv24j<*x`$Kf;B@p>ph5P%?dNdhWU1Y8bBW@UyTsw{z(IRY>91X>jc zqAn3Cp@f@igbH**0tP|snS@xj2$!%4x$F=`+a;v3N4UTzq-H=6U8o$kjb*rsl#wc0 zMypsEtA@3vN|cEzDD%5yIUH-3;Tl~=YD}50vSq9mUga8JW~xG&uZv}|DwWl8sMe}d z=7Cz4s#;lX>Sd{Il=(fgEY_^DTeiz`%_;M3w=C7XvfK2_QYR?$U1&Gd>aGZoT^OLd z62Nv5fbWK5?OharU456_B>}Z-0(zGM%&uN#cWJ=w+JN6>fUv9A#a#?YyDE@(aiHw# zK-~?`e^&$gZm88=eb3xwfwk)bdzS;wuHJTcdEo7Oz~5Dx!LHtgDq-EKh)tvdH_?jJ z#41P=ugFcJf;K@#X_A$2tXDCcbcJd%6~D?>=q6VQ$9ff}DOCKrSizc7MQzFzys1=t zpjMQsR?(VzMQIxqf6uJ2O{?NI?F!d)Dt_CoC^fI*HT{ax2`YXUt%h-~qD`_I#*G_|VQ)~gmUszl4IhOw=>Rl6F-wn}u|Y8cz9 z+xDwgGpG_hv_{lGjcGD9z9!W8hE!8)N{w%7HMOJHthQ0(TUO1jIW@lH)!dF>vpPYI z??LtO{-Z9okviN)>rxx5BW=7M-hb55HmECYvL3cyb+b*^sWwx$+H9R}b9KAT*O|6Z z*BfFTYfE*tE!Xk3QrDYmooH)yt*zI?_N%V9%sSh)>TcVvb8V-tcicMP_Uc~SuRG14 zuJ@n@)PWmf2Wh|^v>|n{2GYSBa))T39nerZWFypD!|c!vs>3v_4%?tRTq7L+Hkgjk z@Ec+S>qrf?BRBAl((s#VgXm}tt)n-bw$bogW`pfm4Yy-AxQ^5CJ8mO9|AyD`8=>AB zeh&ZzkRZIr18_6E3urO`ZL$DsasY4gfM^OpX@@lo7y#^jSL`HN#jo;WpAl+GrDPV@<4$H}N*nB-)?}+GG>zP))c)H<1q0L_2H~>u}Am z?P?Moq3N{6rr4I6Qd@4yZKbKS!_h}OtX)l`DeUP@t!*~Nj@6Vpb~9|dnnF7q9dyFl z)eM?K*KcYacn=95*dDq^gsK@qB_sBh{MeQLidJk(cdqj)f6I)S80K+ z+LF3jOX=z@t!uQ5uGxZnRtxRfExhNng0|a|dR|NE`7Ny%w1O^ZhxM`@#>0 zU8yH@wVu>f!>zQg*+qIXV`R`_=>Tt@SY)AN{if{J#BpLw()Js8A=FAMv_qTt45RZeh^~=yNYrhPG`1SX9;8P#O_uyRn#~Z}| zAQt`d^kdU6!=bPG&>uaxp1=LdgX{e-;QzmWAiV8>Xaa&*5Pqe1SUHBN&`&^zegY=+ z6R;3;l!KtlJOn)uAn2VK`U|AcUm%D60wweps1S5qgP^NA1U)h!=z|&h4Xn^_V26GK zC-fV*5OmUmpldz^JqaM_6Ep!L(o@o2uevq(1JV!6_p{Vtqwuwv?1uWJ_NlqhM@1}5R|co zpe1_<+IEJZt~&%>@P?qf{t)y!7=nJn!(`|kAVco}8F~ju5+5dMVwhyXFv(NHciwCW0?G44wF%9 zn4GqU$#rL#th>YHNpG0E<`0ukf?@I#6d_?aLZV27#L)-|un0-v5t1PyBnKj-Kt{*} z6(Q&72)W5b$UQbfp5Y?oO+G?C7b4_WF+!%K2)Q6f$f6P<+iHY7r$xxydW3vwM9A-E zgv?kGa>ftN5n_Qi1@)A5u?_K zIBk!J>&}Q+cSppN-iUb39}%AfBjP7$RD|JC5k*Et932$_HY!s1sK^kbA_qoAfgBYR z)TlT|kBXbjsJO?Dif6b{@g_eiJ{LyCui~hfl19Y^c~mSaqhebf70+p-;%$9Yd})k| z-_21mV~vVS_Nch+jEY@%RJ`Dgig*1{@pUjN{)D3@f<#RWjhX}&HAy^b(nQo`LDb}_ zs5wqY%~d99?y^zyC>J#^^HKAG5H;UPQFBs`nmHwER@JC^T#K4l^{DyCh?*a)s5xy% z&2=Yg*4?Oi(ub%Y#Y_s1nG6v#IS?}iGG->Im^nws z%uOa{?y)iR3>PzR@-g$d5Hr7up|3!SnG15vEGjXxt;WoATFkty$IO>T%=~V~%#0N? zm+Y9i?ZnKk8#6C>G4rk;GhYWW^Cuko01y~jL1Czj!O#&LhAt5>bRWRbTMC9IXc$^! zV5q{v&@m2%uJADQP=KNL5)4hrFqBtdsHVcu2@Qt!br^bVz|cnvhGuLS+Hhc~;lj`< z4~DM$F!VHlq0ev}nnmJJ0gXdVEDoK<t4=!Fo6zKL-tEybZlIS!SSIMh+&(0MHm-O=OFDP|uA+ z7ri)i&yPcIf;jXGPLN|rf?PopWEo44NALuBiAa$5L4tfsCCCXnL9Q_gvce|FV_br~ z!Y9awLV|oRCCDi`LFSbNSyL0_2`xeH>k0C)ksv=>33A3xkQ+{dY`6*Xl$Ri{`w8-C zkRU(9NpcoRk_9wLHnAjm8c&iph$Q(8B*`ySlANcLBonl0VEOnYEJSvYjM%oFv(EljKD&N#665tS=n^@L7jc3gpMAm!; zvgQ{mYtGYIbBoEEEjDYO<+A22K5M=ZvgS7_%f?B{$L^Sw2i>)4g%L*1U~5@ z@HHQSp9Bc}2_6eGg<~*|j==yMgDHFrW{5GE17om2jlpyD7`(}h!F%i&e1;o?Z}MaC zb72hrDviMl@)%rH#^AO(2A|W$;M@8b{L&bMzguJQl061*J7aLy9fL1;WAI&n41OJq z!9S64D$L1KVNRYR@o|bK#wiwzQ#?IRtuo`(E;~*g<;JPY{5bVM7^mJzSv+H~9(bxiCR}l_sbKd4eh`6I5HBpw4L% z)NOr&dTC5h->nI1$)2FLoe8SzPEZ%T3F@vtLA?$psGrEBgrSoXflW#zJ}J?}q{M6$+&JqaeIPw^$DJ_P-Mo!(HRS1 zGZuxnx--@VZ^pXo&seX68S5v4!YgQ)yT(xX2#&&+2o$~# zQ1~s4!fOl)S6CE2#-Z>P9)%wYDEwYV;k<&vH5G+VXehj|qwr$`g+JOTyy2j5!$sj! z9tvOgQTS{@xPZ>WO>7oEjnBe2h*|gyaWSNJ*Vp)g0im*=RwGDp?a zIqHNqNA2r#)MI0g`e@Hl8_pcnaObE~-W+w^pQD}zbJS;Ko+_a8R1=%0PUG{`4Pu^p z2Ii?R^gOl2%u_9Po;u6TQ@8ke>V+^*eUs*?MR}eoDf3iEou|%g^VA)Eo_b}>Q$MVE zYT2HrcAR;t=gw0Xy?N@MKTo|0=BZ!Ef)wVcr7%Y=9l;l*OT>b7A1p|3=>=(xS&%C1 zf^>{qkgo6x(nDcEdM__Xd1XPWsSDBxZ9&@C7o^9=g7nc|kT#qJso^e2r@RH}y1yVj z4Hl%&$f8t07o{e)D4oU^r5nVe^b9OYU+6_?i&>Of?4op*Ta<3`i_!~WQTiq?N+o4c z>Zps-d2La;qc2LYj78~(wJ0syi_(s>DD~V$>7utN-SZcvH^HLx3t6(lJhK(%nXM!E zl68q#vhIT=>n*)xtuaehg z&T`AvEq>X0AuLy@!={jis<9cS6e9h0vPlBBM3CYVinwJ5Vmnl3iGelnIKwcK;yu8We zMWf zKQh+s56-$>ch~Kc-nxCwU$>tG>-HyP!^Y7K8(Tplv0-yy!xrcbdz0C)_t*{l z47Xw5->~q?NeOuqKUm6?scYDL$b~fy;yJ27OHtf6phW$F& zuz#XBQpRxP2#zC{2pqW&aO5q6BNY}$j&V40g~ySH0*<^_aHOW<$O#Qc_H`V2Y~aX8 z2S*w%j-2vv^=%K%RjD@`WxSTTB6Iu?6HTS3qv@1>}WL zK)%TZq@)y(j#@y@YX#(vUO-+M1>}caKz5u0(sK*QMX!L|^9#tEpn&{BH|a9ANgu&C z=}W{WeIIPnZ<$TH!fw*XxJ~*Bzezt7HtF}uCS6lE=@Z%}y{~W5kBv?Gqq9jj+)etF zw@F|3H|eLrCjA-RqMO(jeH!1QZxCDbGq6Q}VYcWNyG5Vnw&+{@7X3olqQA*obV=Ew zJL(pFUfZJY=v(wFV~hS_Z_zu>7Tt5V=!@PKeb3*b-vnFqFEq?WVnz7~UX(8pMfpA` z%5RyXTw#myF|H_I;fwM^p(wvsigHaY$|tmIQn^;LcjhEybL`i-IO7a(`B)8a-e3mQ8xA>C$LMX}KlrYbzmgMtVNxq|((6JE6Ml#lKdtp$-mHTJIpcKNAPX?60vRH2ix{rX4|f?+x9VT+rGkY z+Yg0p`@OPl*VJwMgtl$(>)ZBYW841dY}*ZY+dk!O+t>YV`)ROke@4T+AGTwk#&_%+ z#E$(8?ATwJ9lOQu*k`#N`xd`rzYuopZ%UZ|Q+Mq1+Kzok-?3jAJN6G}$L_g1_C;^U zzUS}QZ-O2B7e=5YPM|bFpe!Izo*~d(mOzhk1bUe#&<6s6zEi@Sph}>}H3Ge=6X+v@ zKtDJHT6YQbq(`9Fd;)zE5a_2c=LfJdO5tUcA<8HR%BaAU(LJ_|p5e;qO}>mi7s}{Y zrHr=KGI~xcqqp@k`qC()-<>krb<5}luZ-UH%joN%jQ+%S84}-RXkwRP!7jtIyUbB; zm$}UEG7p4Z=AE+3RMlPPxVFn&)pwak#xC>0*=6ePE_2e`Wv=1g665u@&YFS7C1Q73R56VZJIArma?(b6SPDtyh?rMuqwARG6+?VJ>(T z=B{61UI!KCCstKRysFSdRbfF@;n}Kkl&dP2`Kt0js4DN&s&ZVbDp&QY^2n$vADpUE zcdN=tuc}=0tICt0s(eCg3czX#h1V2@s3{z%DFRbd_Sl+ohN~$z`I_=vs3~8Sn$lKl z$~mp3+}3N#OQWWIcWO%4ttl70nsV2#DX)W?@)N5&BwlxDqVBMu?(l5gIm*?Y%Y5B= zAk>|AYTY@m)t#$)-Falxoeyr^IqB7%Yku8%64aefXu|U#Up#gMX2k2u1pdVd;p7H>C-3RE?0HB|-CVCog zqBn>p`V2JDFJV5b#WvBiTob*;H_;bD6aA)yIWDz{p4Xb_9leRZGMeZQr-}C5CVJ6p zqWAnJ`X*?izpy>#2)@T$BKDa3V2^pr?lH%>J?09($2=7FnD^=)b3)r=_VqpHv9ZT| zboZE3-X3$^-(#Kzd(3C7#hk`l%nhQ&JOeG}3)^DOaxLZ--(p?}E#{ljVmfMzIj^;t zJ9>+GWwe+dPK)WeE#{)vV($4Z=1tIIeqn9p2;NpM5pCr@Xe)2owsMSXD_8io@=$0i z@71<)LTfAgdRuvHw3Ux;TRG*mmFs?6c^b5p&saw}jdzqAL`QiBI?5NeqnzbB$}PU5 zybwCdH?^aj*E-4_y`#J`I?4~Hqx9U4a?$H3_xz6XCg>=?ui?>d)=u5%xBowsb) zImUIJD}2{^D0H3oYS%fTb)9{^>pV8P&PTWFobtNPb-(L84Z6-}tmmA@d(I7_=R5;F z=L_3&&T>8H7TC9#tpiCyza>`6dkpRgksg&)Bf;t0lp zBbdM*!On0;u$%l5?746R`>Gzn&S^)m+xijgrEvuN?jFG|ct^0i{t@hTa0L5_A7yFc zD9eJQEYBTfFY`y)2g1?tn@5ha$F-yERsAUY$T-S=aF4Ply`$_k|0w$;ILdy)jT}_Q`c*xlp3_dKxAhb1OXGz4-94dR@J^_A{S)fz z;Dq`UKk3rMNtXpDU7kDXUgl4_4}_EMJME-;`cfdj?Kp zU)a;wS?)A;i$9IM5Kd#?)YI5`?KE~rKaIUIPGdjZ)7VAtG?Pt1 zdmo%(-*RWzEBqPup>T$MubpA{^)u{a;|%-JJHuZ0&#+H}Gwf&lEPI1E%RU2V*)QB# z_7;DZeIcA>zo}>0^V(VVj((PXWt?SyxM$gm-dXmZf0lg{oMnIE=hREYIrTm`r@rOR zsaN=O>OMP^C`olf1Ui8kZ_x$tfo8Y|q3%}rAA}+Z1!3Fm%cfq~FUvM7^7u@&S z1$SS+;664kxF5X>?sfly`!u-Ve#S4lH;9YwGjP%U!d-N4@fY0}!bSI+cG10~Uvys? z7u_G;MfaY6(R~wKbbk>v&H@_eIU2vr)A$2{#@}f)epRROM+S|5@M!#+PvcJl8vle} z!WrTc&Vfs~z+J*`@|W=E!X^Bxb_u_&U&3D+m+zc>Xf? zK)B4k(=KyY^~>BN<1+WbyUbnlFLO_V%iJgY3dayvI1XIl1nvrVlfS|}7p`z$wJY3h z{R;QexWaw+u5fq#E8Oeg3ip$^s(+ z?`sUPuW?{s6S#ftCcm#e7xuNU+P-#M-`8Fm``UMJU%Tt?Yp;WS?I&@~W5G3#=dXDW zglpbA{hIg4xaNKEuX#^`Yu+dPy2lXLJq}#=1n#wd>w({kr$kxbA)T zu6uX=>)z|&y7!Y{@cV$l-|`IpP+;))I)gtp82qEp;7W&x{RaNZxPkxhZs7O)8~B^x2L6k<$=wGxxwrgH?xAp#d#~T*9ve5gkN!>W zX>gPKOx)t0fm_@c{ucK_xW#?bZgF??Tih$-7Wc!u#ohC7ac_cK+%Mv`b|2i<-txD# zhr(^`y?$GJY~0p9`nR>G!ENm`aYuUw?r2~5JK783j`mHzqrEcjXg|C=+CBe{_9nQa z{UYvq_rYE7Eq~X0DBShl>vz4!#$E5Df7g2&-1R;a_q=D|p7({n=e-c_dEfMV-Yest z_rt&Ey$SAlzW__{JWD(fSmK?|5|0d)_~5g|lYk{Y5%&oW+$RM7KJi?*Pkhzy6EBVX z#CQKb@jAFq`~(kpUUp!apNk2+xRb`ZMB{@r?N4KO^1*&xl{(IsaC8&c8RF^B;rf{Acij z|02BLzv(adSH=tehyQ|q6TIMmftUJQ;idlGc&UF3Uh1F0EB%Y`O8;iO(tr4`^f$pP z{TF!czZG8l?~T{~$KbX98NBho2ygsv#vA`f@W%fo@Zg=ngAV}@K7qGD5Z;2X##`_` zcnf|S?}QJ*JK+;}F9^bW;j8gp_#V6$eg+?mPvD~=2p^5F#z*6O@X`1QJ_myEIrwUP z4!#GUgP+0|@Xh!Fegt2@FXNl=Blsr#3Vs;BdVb^=_F>{j^M5UW`^W#~-7kgzNBN9D zb3dNnuYNe&`p56c|KdOLW$4qJfAsJE{j2{4`CBjd{%ZQgzhD2OXZIf8=I+p`r=|bw zPan_z>%a4;`|r*@y!dnB!Tt7Mv;XY>uwk3je{ZRG{;P-o@bf#^%59=2%{F_G?7XO=ndj3Cw{^}fJSI9r^G7>yt;;{@%YNhyQ>ip@Sc>&ob-t3;S%d1HN&eb=qg1?fl==0mFR2FYL3? z4*19ee&KH)NuQrtIZEwIY{OynFvuyiJy8*wj&${dOnRk8mZJ&WR;1~AUczs50pOtsO%Rcnk z4ETk8w%!3>d%!R3v-kQ8-ad=(fX98v=N|A2dxw6Ve>LEFZ*qUb_wKWP2mIn*p8?os z0r#1J1Abwj6?nifKlJ?!_=SD8V4pGEXASn5!+rMP0e^hJFYL1k`;6k=fM0mv9qM~n z2K>T<_XhmpKELqbv;BPx_=N}i?jK{oFYNn%di^pC_=SCb@j)2}{KA8>_Zf`+bLpSc zfM3|>7x((-Jn+l(S&n^vVV_^z=NBHtYQQf(h~a==*yk4?#CX6j{OyYx@Cy&FP5&AV z_=N}8u73>&{K7t)^57Z|_=Vj=e^tn`Jg5@`e&In~>DQS<{{4Vocu=?cb!@;d?0bX` z>fnH1cu+U{b#%Zl?6Wry>Ttg<_v`e4U)bjt_xXhfb-%BH0l)A-8-0xo_=N}B>1$}f zFYNP+4>UI57j_0dqCQKs&o4aC=73+^=NBGmx3A#=zp&3QKG67pU)bjtA9%nHd4`94 z!$aQTA^-4@huCMA5BSA@!%H0S6AyWchkV6Bd4Ka44|$A-e8xjwW9YT&w*kL-j)#25 zLA-wR9}jtuhkVFGUgV*#>X0XS$d^3iO&;`sEx=kXL%>UpwTP4%&y`ywgGZ@tcP_XkQN4Ba~-sge{#rs9kidnd9Z`_^?+SI;1?hG@(y{j zgZBA1Z+6gr|K`yi@@WU{{cnHYA%K0-9~3Stlh;~|5H2)RQbWDQXeIZQ+32m_H(79wE| zA`?7BrUZ!0NRT)zL*j@6iBT02VGR-!IwYnHNX%G}Ic!7bhy$5X7cyZFG7~;zrUJ;! zz(Y_38G=U9At;6oL2-NtN)kg*8Vo^MYKV-`L*ytkM8?=5GR_T=Nq&e-3qxd98WJP& zkT|Lgi7|CZjB7(;QXdl2#*mn`hRldPWR5yRX3QNj&^oPuJFl1(tVR!@`hNIXp z4CBLaf*6KVU>MHO!_){fOhwsY3g(8X1V2orgkdTp4@)D;uoP8?C0HAl68f-|GKQs$ zJ#39Q!&cNCwqS4AO8CQ8Dj2phNCX~5BXA6hz;QeRCy5B01`#+*N2pOILdDn!73U&U zl8;bnAwp&4h%~B1q?j6!;#x#X>JcezM5L@8u|}PU6>}q2+>2OAKVqeWh?PZ0kSI2S z!1xG~AV!cB7(p`32pwfdXqX$J6Z{CB5=Q8ZG9pLS5gFD-!t__$ZPjMv*iaMY7B&9b-r7I5$cs`B6G8jM7#$?r) z64zo%QjaNVBc^2Cm=pJ6PSTG#=^*B0aTrSwFqQ%^mf>JF!NY7yfZ2=&s|g)eQwFSN zJlIY6u$u~CH-pEqBoW8bAdY3ZIGg0-Y+8u3SuL(6^|+cg;%e55yGcLprh~YfB@%cF zB=8KM;8H?@%jgL$WhAtWpYT#a!pjgzJPnd~mQQkNA<1R+q?R_4TGmf`=^*K4L5j!- zDL!MQ^h}WQGayZ5g*2Zv(t0*X``J)`@IZg5P=9@XSYLn9zWzuE8lu9lSEV6nl!2f$ z3qcVMf|5K0#RLe-h8lzi8cc;693E&e+Si~7i9;47#%)L(bs#bALSn>&#H0_2u>caY zaLE2bLOvK8GQP0C;f5uMkPikz##gArIQ=&|Oouv*40IU#8y%XkJY>pLmfs2I*j#o2oGa0GK_^<#8UWhc+G~fC>X{v)G!vOhp|y+ z7)!ImScDtKlKe0h6Na&@G_1n%uo~)7O=-j7^&D2C#;}^PhSj(|td2UvYT6xEBi^u@ z^oP}0Fsx?b2n!<-b_9*EAq$L65D_*CB5a0=uyH!VhMHv4T!anv$i{>So0TFiEJxfC zCE}*Eh?~$OZq$glp?}wn+YvX^q?`64Zm35$7DU`E9BMJtWXSqD&||c(M`{F#(<8_z zGlHbK5hTfvATePC$x5LfLtUl@nvC`}X^qHndqf^}M&z_NA}9S3ITnn_S$LF&(NQ{u zkJ1TZl#YT?Izxq;47Hga=rY#Vr8H{8%BY>vM(ui&1CqRtPP%%Ev#P~E96bDy%qE-j<9K=*=<&;fytRH+bnOQ+0K(G1b+*XH-|$v{YC3ZLef7F{bK6zDI=5NVtFzCB zUY)%+_3EtI(yOy?UARxjY}3E@jBWbYv~1JAZ+o~`H*B-2_oi)D)oj^jRo}Xr8QV70 z%;+;F+^_95o3>q3v#HO9?0&85GiKYm-YwhK^ny*Ko2>C@16OP@8me@EnMbM?8p+=N{J+{j!*t~oa*H$%I^=5p)>%>KXZ`Fr&e z?K8S~=YH(xyIgztvTrYY^|C)Nd-Adm?=#wam;H9xW0!q(*-MxGbJ;VOeRA0wm;G?r z1DAbo+3S}5ZQ0Y7eQepgmi=nkqn3SX*^8F_XW4VMO8d;Rw=Da~vWG1D#V32>O$?K%HFB$m&zWg z?25o%sO*2ro~P_{%HF2zXSzsxn6hsvdzJ349X{EUlzm9qdzAe~*<+M_McGS~{X^L^ zlzl?k8-6!grLEmn? z?VzsQiyZ9H!`C+6_QuwIrGD1y%{2 zpLgY&TKIr%5vkK?)Yl5*Yd8t<;c-mzIj{XZs^)$ zj$G~MH-9_Xa#Pn{bL4D~UGcr-?CURbQMWn#qI;8R%bGL&=FKyHk_?)$RmWL*@Iy&@ z+*UnjkE(~0-FLHnsVukO@3~(jV>Wf|O-GLRY_8^qvcA zHzcce+^YLrn!cDkm3Hl2M-KSzi16acI8C&T42v5H(=#|lYK8ApXo&R?etNS{<~|hJ95S!9aV6TPdqo%jh4Staw8ub zo9RbG@2GMY>|y(0nO1U7(>89O=Ce&ZK|@*p#mGf#OKTy=T)oG3 z?iYuQVh;(^Vh&rqgS&UiNYiG>Ije^6{O_3;xk z9csI^d$=EOXv*}c{~olb+y9m0OcNqE{oZY#bN_nv81}j_&1jp7ecXP3JSx+vDyH>! zFRUMt=~Z7`x4+wUZIbC$Gj|x^iYtek7DWzw=fs2DcNQO>=~%n3I@s+vsv*;}*1mp- zn^iwF)3x}S$D+Q)SpFvD!S-A{XULE3wRp{tH`{yRJw^SC_sV+?dA5BPK9h1``;2^6 zK6BK?I2Ig}sE={1IA&2N<5+S`qh7|b=9q_lKkQs^PNIIsx#FBf9gTCzIgNT6=bCdK zbv3R9u8F9xajkI8WICI!CA+4&_6xCVjcYFG7IrOiO-B8VYn5v@>Tq1kT+>mH<67sM z54wom3)~Y?pW|NPo(VdN-Amk4QLp1($ebAULFP*4%%Ef0T*{mp^+M)a=G>?oG8Z!^NBxkwnmIe_h|J~8=}}K)u4m2< zx|*#8tO-$HWUXM$2s)gtC9Ek?Z)B}u%?bOa*jmJz6!k~eD%Py1L$a2!rbRuHwT?9} z>XNL5tcg*dWUXY)3_7B%rL3tzU$nKBH8<#vwidG{NBxqunl(G>n5^Zj=~2&Qt!K^8 z1zj`z`=O|BhVksvX8X8==VQM%+uwz?U$2+#`@-6<_mk}h!`iR+%RX+VgNDzO?H?09 zuhr60V;YV}N7P5d@v=Q0*@q?^&ot_#to=IPnQj`+N4B30YroD{8gB!&5m{p@W2B-Vb-cWKmx!+e$?0-iL;92`MU;C&dhxt6ylf!)Pqplp*gKWR3 zuwG<3b68KZ{iRs@wccd9b6AhE{iwovmF-g%*0XH?s<7T=_0VBG%=Bs2eyx|;K3HKr z^--^8?bmvn?VH8guk|?FPm8r*>$Q(Mc397S)U(5SpVeiDc)&+}JH!jwK3*Z7$n@?I zZ)E#^g?J>>zeBu|?GqN_nM@B4@lIAB9^#>Fzp)T6Wjc9?r?UOYLcEpf<{=)-_A?9d zTBf6ic+N*XJ;ZyNt{&pSY`?S+FJ}9wg?KX4+e5tRqwXH!(M*32@v4tHe28Z=JwC*{ zS-pIShqL|OLcE;q0~g}yOs@~|cD8R^h{rSiKE&%j>i8j^&-R}S@qVW3hkPL0uP)>Z zKI;4-pUCw7kZ)wVf5=C&{qRD*;v)wL`Ao(GLcWu6fshYn`|X8%DcgrHF(e z+#uv**?xW@U&}Z`$mcSi5c0jOk3q->Grkb=#cUtJkWXg3A>^CczJnnj&GsV<`D(@? zLOz@AUl{V;j7x-kIO7u`U-pqxgnT;V6(QfwxJAgvGky{BbssrK$mcVj5%PT>^Z)2) zh(3n!x|wew`W2#2A^H=dFCqF7q7NbZ4+8he{01>!4cArXD~NuA=p%^!f#@5Eeu3x{ zi2i`+3y67I%*P`CkK8}<{>b?w-w#|b%X4Br6Z4jspTs;Q<{L4ui1|az6JkCPoG2m@pp`~V>}(><`^HxI5@_;F|LjAYm8H4JR0N97+=OXGRBKBE{ySCjPoML zj&WP~`z#I%&!5Fr;q|jPDZIZd?uqeDtf`(k>^H^8~JUxezJ8a?voj=w`~20JT|Teao&&pP$F-Q zoHfqNv2RM8XT$xG&6|;%MqV1{yU0f)7mYkLa?o(UX7fv&MtZX#^<8YGN{llv##t2OtPta@%H?x~>U?#fHZS&=udb}mFVns(O@%@E zrcy(`sd9uEXj8teFf!j(8k29UoFKM2Bi~tQ&Ucnt@|~5-^tWyKYVpo$@y=@T&NgwD zrsC>+Q^lHmQ`I{Ct~1{z=Gi9Z*(T=MCf3qf+??;M*plz8(kmBogx-KU>npYt)>q|< zxytHdZDnn-P8_DLvc9;ivVUNvm>|a_|F{m`5)KHpGIii%SY$~;tMwV8V#*|iyq1IN; zD795Imo}DKN*gQN)I()OslKAURA05SR9(5Mw5)1%X+p)C(uAsYdalk=TjlzaxKn9m z)y7g?<)%_w)#lR1iY=v$Rn--usujyB>MHtI_ODn`F{q-gqM>3&<%kM>){6S7krm6T z##F4ToKR7%{aD&7nk(AGb2e4BRjjCNujnt<+P_k)wQ99~UQ;onYMnT3XGMGEdOfzG zVpY|~in^*z75a?&|CWkPRbo4p4VBH6BP#X$+GAy8Wp&k<%GH$7|RO(n()`{_K zu57CmffesrRk^Zib!A)Cn#$&?b(Qs1o%;9s%KlXw#CbOA_nRtLRc)@+b60MzYN{Gp z)lk*0|4yh9>(PJLX%Ch4RV`JU^{p?53kp~yrIi`zW5wqD#^RQ|u7hyT z_1C>KNcT{K?jPN2rIEVdxYuUro@v&-)1v#PP4{EF?#ETSuXJw}*Azxpb?P46pnFjF zQ^jW8Q`}G0#X-7{2I(FeRMAizqGm5J#nv1K8EydMUZN+9W%x2vu&ALaL zb$@IwZ76Q8+*I7Gdt!4{ov!EprRs`?Qgv06?twA7mS^bNZ_zc}UTV^{uDPYuRJEbh zsq0$vNU5`mYq>$!;}~7HGb&b9wCFl)*EPLH*XIUZyIhB2{<`kkD_eB!tf?HM>t}vdi9*Bm-X*G7Zp%BEa>ex$CEF*zOU+=P6yu9KGBM$Ngk`S#oj z&9x)*t98w+$*mW|9+cmZTdnihoZph$oUhBb<@@KG@(uaU{FwZzd`o^)eocNuK4)Lc zGQVo*=au}n*xER01xGnZci*Z_v&thB_7zf4pC&oRwpm$|)PVnW$xF*IkF^-AxON?7$yb|M-7@x$r zB*r5#4vFzcj5}hy5#x*)U&Oc~`n+Ns5#xs#H^g`$#tAV#h;c!T2Vxu$`?bY&U)Niq z*5;oPg?e3g{WW)l>#Z|`VU5C|L@0)ZjHWfGK+H^g(6*uQPbxn2_tMj#5>qqF?99gK> z+TK6Eg0)`P==wrazP30fKe9L>ze4lMiehtqy{_5y#bxqbwB_pxE99?e&yOjrRD7^1 z-(Fa)bzawVVV$0o8+SySr}0qQx;F;5yiUVgkt|hAjbbHgiMZ*`0I ze`WXqueG`X558p#nA|e=N3r5Ji;efbAO<{So5o?!x4JcpYBT-$SI@M%wrzHAeC5ej z_tfd1YkcbQR`>7r{W6_;f8Xlf-)Cs!Hy>;+M zHCDGshyMNLjf*a7bvJ!*MW&;_Il0wcaMZPpe>u0+-9KeTqd&9Ny?(`wncn`+ar(O_ zzt(t$Yjyv9^VY^|hqbzA`m8jDO>TbWzB>M+?rJ=tU#oj?{`VSR+p*OhaP!@ne*c|{ zR`<~J_ccE8{!;hCmY*~}{?DcE#hrg<%$r>QJaYsdMGgmKl4}9=+kz^A1?*)-8Oe z@%(;E-GMj#r!nS@k5n#oUs?Y_W5c^k+_9JBlD5AsaRVz0#^BL5?)%LW_sHiel52jk z#Lc;{G8yr+C9dMg>WqI3`sNb%&+}@MIV+a96W`o6`O+7cxG!JUC*vfI)0ViWZuv~| z$FrBXU+%qqa?S}$+)=P`sq8s`pKYV7fyK|2{Gd|OC?_zgP!`{i&w=Z_r{QUFD!PhT#r;pk<<2coG z7Q1UN+&?+|yv44x<$&avlNY;*%Lin<=TG}Bc2C?oD7ma|v3s`v;N&lri``@QA7UN? zw4u?jE^;HE8k(H)t3~e3vm26nzsSvc^{|W|jsE%~_t|%cC-+^s$R%G&k~bDCawpV| z$T-vMr!I0;`y8G8;D|-;XRD7%n))wtryOxy#-sY=7rDBTCnUrEc9}cvg%gv*e|MRi zKILTdD4<-MOz#OpgA> zrS9@slaoIzztmmv&J^=NpsjuV>`UEVr5VY(5tq6LzdSSX`(5e|+Wx|fzn%DAi~GTz zbCTb_+T!k8H8(lpsTOzBK^K{40U z!R_bi_aiP(RL1R^3(J$?$tCXlk1fwQ;#0jYaW6Gpk&OHM#qNb|u1p?#_G0(&Q&(oZ zaqrtNb|Xh#mF&9wVz=cpS0``IxY%9&o2$*kfi}78;EUayv#v=l+wo$zZl`OLAHTcM zy}#kwj9>ovk%eyXxa*TecP(@W?zSS??dpZD_Qe(E`9SOZ+sK9Prt`m&>^@|nJG9@8 z$-X-+bpE9qGamZH9~QW4C)}J&@(bLr>u*V(yJLaNy?l##M9@x8n6|*}II%rBscC`x zu>NbwzWXn5PjCEM##iV3ZNA%g!Z(uNJw4yu+waz--|G3U{-s+p4tv8*tyC)D`>^< z&A!OZJ?8t#WhYzY zxbw^BHM`n@tCL|zG`lC?Se;C-YjziY_eU9@9{cOLZcP1;lU?tf>+bx+kCQcDp6hf{$PyIA`@clV%dD{aS?>_JTIqtrX)+Af5pX2s;=x537 z3+K2w7e8no8np4h?m5T(^v#Eox8I-b?)~oC>EVZys`aznnTsAte*V2#?wCU#&3OE?=gxASs~$`C z9y-gNJL%`i$iB1OuXpY8=%C#n@$iLi(shp~?|tn;xA^$Z50Cysa_k$^+`wL49wXStpc|*TZ_WQ>a?$i@ z?tA@TO0GL%n!EPJmok6E`L9lOZyon?Qv1MEcforvCo8X>>K?oImCQ$R#=%ovpSstQ zOG{JThfltiEP8&5d$RRUncrfEB~#pcfBtiF_i0nyd0&4$*>kTc?$%Q_nTH8BbH^_x zyC44eFUj5Qlie4ly^-8}!DKgR=dM~eYAoLGJ=yKK^vz_^OOxE>L4Ql0Up>h!d*yGL z&tsp_vMV0<_hgs7C%O0j^Y`S9cP6?oeQ$H-2ifbEiEh7b-%hTcHqjm3@piI)=tS2r z=bz@0GIsRa3GPSFypue0*93RyvVSF4T|B|vIH=1zg@@{v&rWcESn;3aFRzVvog=m+ zJKsOvUAK9Qd8%Mh+l?CU?mX??|=N~1feC0e>d3esfJpMfQ(TZH=fBE*i=enOH zdH1Ww&vo-}&bt?HI@j&?WH{`u>?)JYI+?vP7xh=YsFYM>BI`Ra@<&V;K~ZOfvtf zILGz5qte~ec817@=*x=)bo$VTL+r~8&&vp;|V;lF~r_OS_ z9aoe2hYI7*a(BK}<38N?Ece7w+q&OvKGQvaOPA*i)_C9-&vZXddb{tOc&7WpS9-hm zwmZ``{JFP_`S0=HKEqADwvRjF!ZY0OH}-LT4>`jfF{I0*2D?1-kr;m1jSXP_)o6dP@l>6>JpK&MLHOgIh>1SNs>``v#r#@qzHdyEx@1E`kU9_Eh zWZmiR>yK{dYOg%qz4h5HuN&I-iQAv?2-I(*cJaDkpBlaKZ zN`=q5RewLtJuv#S?w$Kjb7$PyRf|at(*f=@cYM>1Zl}^|?)IWw z-`>?cd9dW|uRhUz>xSLjl_#I*`n|lH`$L}--SR=ZXMVH&Zal$NKC`>q^UM?6UVH4} z-rey8x6kY@4`{c>EByZxMgZr|OT+>xugYE7x}T7LWS?ucXS-IpdD z?{2)Y-c8^0c=zj<>&^2A>wfxM$GOU-d%80wALrhCa!>cr=ZM{s&PlTS8v%{3vnPE$s3v;uZL)C2`|w4sbs|G;zD0b%2}m zcBAtvyJ~RJMy6lb=zezSfo{#djjr#q1Kpdi4tFQ~^1#e@`2M)zZtnR5-0yZ8?#@{? zz_tJ82)Ezc12TW&!zUi$TD~;U?N@n(`_Iz@-NJ_tcjM~1Jdt=A9vF7G`_1uj;axSqu%MUsI?OG8dXSs?VuRajr-R*-Uu|&rjPLSL;*B_Z+Xi>h z=7ZgtzZmAe-!RynxNMkveA!?Z{gW^KbEvzw_7K;4&ro;Sm_uA?`cSvu$}Z0(UW+xq zJJbz1Xo!3LD~G!4FCOCFJLypOOvjMSkIBzG#_t%zSpFvZHhC_dljr6&cr9Kt)+_T~ zcu%}H-Xrgo_Z)qod=@?vpN-GRXXP_TF3Pdsm~d=3MjR`SS@40_vE-O?Y&pgpYmRxW zpXOX}PB=H5BhD4)Ec#SAmz-11E$5hX%{h-cA=d)e1lI=F2-gbNOz@d>T}!&AxVE^) zxYoGlVm&w4BG)9>Cf6v}D%WiE(Q++wO>=E?jdQJY%|}kmy}&)ey}>=gy}~^ceYxCA z+*90J++*Bp+;h>t%e}}w$-T)v%Du`x8-2dq%iPo4+uY;a>)i8EFJ&%ZPGD|ej$p1} z&WOHY<`U)<<`(7{<{IXlSntkU#GJ(3#2m$3#hev=$joKTY0PcRam;nhd6Anl7cwU@ zH!?>uS2AZtUo&$lb1HKyb1ZW$b8f7^XD((=W^QJVX0B$=jy`GTa^`gAcIJ5IdglD7 z8?zR$Ca^ZJMzB_}W<=jLYYA%#YYS@(YYl5o><7SF#G1s~#2Up~#hMj;+^l7+X{>Fm zajbQ$dC^C}TF9En+Q=HoTFIIjd_=aEvZk`Ovc|I3vgXGA1gyoZ$*j$+(X7?1+0kdt zTF#oz+Rhr!TF;sv^>bnYVgh0VVgzCZVut8jCzc?lAhsaJAl4w}i2V|XMTkj=O^8v5 zRft)l51v?tn18Jgm?!!wh=quWh>eJmh?R($f)C1KDPk&OD`G5SEn=?Nzkyhc zn2gwr7>!tsm@W9GES4jtBeo;PBi1A4iyVPikeHCzkQk9zk(e?1{)r`tDTytKF^M&a zIb%NwVo_pJVpC#NVpU?+;LEaDmY9~ zjmVM6mB^W5T?e@oITg7TITpDVIaloeK`us4Ms7xqMy^KA7JO@#%aPNO+mYju>yh(C zu0$?KPDpM@j!3RZ&KT=X$R)`s$t}q-$u-G2V?PpdQF2mpQ*u;tRdUu?$3iYkPD^e} zj!Ujf&KrG5o)bCRZkBj&(8Q(&W_S*5uga+T`4^KMJ`xIXSsGIXbyIIeVuy^h`@YQ$SllV?b*_bBO&~&?3+z&?e9* z&??X@VjU1#2AT%i1{w!i2b#zJq3;V?2$~4m2pS1m37Sc)D?&>_Q$brnV?k>{bBX<9 z&|=VJ&}PtR&}z_Zf^X2Y95fxY9W)-a9yFiG8PS5!gwTf2h|r4AjAGprS`wNP+7cQQ zS`(U6>}P`(g(ihIg+_%|g=Q6eiKb7nhR@uBsh`9&DO$(G<}Z(HPMh(HvvHAGAm`Nwi5cO0-He%UFkomWif`wu#1x)`{jBeS2u3 zXrgGNXrySRXr{5Q4J{Q-6>Sxb6|EJ`HTEAui$#+~n?<8Vt3|U7zD?6|(R9&v(Rk5% z(R?F!Mhiw0MjJ*WMk_`$j&*lv$!N-G%V^AK&1lZC9}-$Lnl#!p8Z}xqnsuz>L(4|f zM%zZ?M(alNjy^`Ta5QnWaWrzYay0YcBQ-4@O&x6=jUBBW%{}&KLW@U}N1I2ZN2^D( zk9CG<`DprR`)K@V{b>G?zrzAx00)ECeP38-bC)N?<0jt`e34Q-Q6(SYRzMm)O4w z76X%k&A@12H87i4rwPk}>A-eiJg^>^PxP0E}gOS0?U}mu{6_#d9?cLXn zvBBD4Zn3`?EDk0In}gB8>R@)U&J~si(}V57_+WjlVt&z&0Skl)!Ukc4utJz&teb@; z!W3bPFh*D-%rW*GgGIt5VUsXQSml*smaz^OmI>2@ZNfNVoiNYn`-O#iF;Unkj1*Q1 zGmUkzHBLFm2d2j2qSs^Nv1f zSU5}^HVz|)mBY+qT{J8mrVd+&vBTP7?khrnI9U8)?*}$7Mh~lp*~dC-SUyZ2wh!Zn z^~3yg_O**Wv-t>#gPW^!jV5;nMqA%lpy$ zTg&^?`(4ZX)%#ydZI?dJT0W0H-&#JOKJQvSuRg!keCc?s<#_1$tmXLVc&+7l>G-Xs z7EH&pgX5{=+rjbG@$TSw>-cw2Bc}7w!THen>EQh6e06ZXs2QVnOy{$M^QrUO!TA;Y z@8Epv{98?#u7?h;2VEZ>Tpzk#I=Eh_F{9Q@*HZ`Aldi80t}k709b9j^{;UQ~*JB6Q zqpr^mu1{UB9d^B{CXL!OUC$j{&$_-lxW0A0cW}My`nQ@j-47ky54t}(xIc8iba21u z{^_8WP4`m=_ml3g4(>1AZynrky8o=kP4{C5_oMF54(?CguN~a4x_>*UebfEi!TqfJ zyMy~%_j?ETJGF3lmNXx9Fdt}s=wN=(e9^&tq4~pV0o}*eAB^vqxr{b z=rkX7FdvEicQlMO_TRyLrTMFa+B(f=9n5E%-#VDzG~abF-%)Fa2SD>-2lJuk$CUX| z^JU6>srfUd7EkkO%6zK%HD!L)e48@gYW}qvJM*Lt6_-fR80nnc9|De-{fgOvC{@j^6?065lA^Nr`t9|CpCw@lZ-Ur1&T$K2p4t z5-%x!N~wiZJe3kpDZWaHuM}^k#9NBLtVUAtSV}ym_$(zpQ@oZEuPJ^@shw0jmlDq@ zzDtSk6z`?Pdy4<8rc&`>N<66eFeN?|`%j4%6+fobS}LAQi6<3bro@+uH&cr@mweG` zFcpuc#G{H&Q{q#_t10m+HJQ|ADxOV=XBFS3#J7rfQ{r94zgD}TcsL~s*NV4O;%#a>sbN+;o)V8MK2M3y6|bkn>x$p4_EYhEN<6Rl zJ|(_ayq^;9EB?2dP~`(D`GE3+l>9*XLQ1}%{2`@QRQW_oKB4>~CBIOPsEvoXVlzdA0RZ4!Pd@Cj2QvPK%s>;Vw@-gLSDfyZ5wUm5K`CCfus`9y%d`|gY zN`9w&FD2ho{+HslR6dxJ4=O)Q$q&W;Q}RXSk14gT$|qCuN#&O*`K9vBlzdb9r`5nJ zA5FS)pDYdc6XH)W7<+myMt@7QJd{_Ce)yyg%PRWOrAE)HU%9m5} zW#!K)wY18oQ}Su$*D3k6^6iv-Tlu%u*eV}S$;XwSr{w2i|0(&p^7oY5Tjld9`MmP` zl>A=#eoDTt{NHMFr3a+w0n!Ij^a1GwDSCnQgOplb=?N)%g7k$HeL;Fdirygo!D@J= zN2KTx(kD{%3F#FndWH0h)cSgi{y!;thS+~<9)L%mPSHE0e^|}0^pF%iMEXdIJ|ev& zMK6(ll2QvSJtaj?k-n0muSjo6(Oaayq|^vYk4e#Eq|c=2Gtz5P^crf0sU4P{lcMKH z-$~JTr1zxgJ<@-yrdWDViXJ3=C`BI<`%lq}q#vc!8cR<~(UYVvrRYo2n^N>9=}%UJ zEIlekkCHx>qEAV$O3|yRNv1YgdRB^_C4DPJ-;&;yqIXIEvYKV-VJUi;^sy9uOnO<0 zUMBr4rIuNGT8f?~eJw>_lirr1w@H7q8fWQoDSDjrxfFd)dR>ZMN6j;}&(iZ!^gQW% zDf*uDz7)Mr`k&QAOAk!Z1Emk9=!4P=Q}jaVhbgtv(i2nkMCpqu`l9s46unXUqt#GL zk4(`crB9~llhP|w^h)WMDYezoGgI_T>6T8kEZCOV*e?6 zsq|B;#g?9$qNhq<_2{e8TRnQK^jA-fw)9w!9xHv;qt8mO_2{+KY*V`}J=de>O5gS9 zyV83-dav|ftLc^=?9qdz4}0`sv44+VOpQ0S-qMpjdb0FokG?Fu*`qgG?YC;crAK@8 zXz9})eOm0_qgPWCPHnjKY>%ETecPjNOYipR-O|6UW?Xu>M-P`i?$O7kmwWVb>F1tW za_Q+FJze^`M_-rT?$O(&zgvyD^mvaRFMZyl&r7fO==IX?J+rz{3Z`3p~6){J>MIE}r1w3E~SLz98P<>%<$xAFPI5Ji@~x#3wv_ zLhRqeE5t86we8{=9-bk-;o%$N9Uk5x{$Vxm;vpU$B0l2bBjP0+@gJ+H7Z39A zAn_p&9}+L}@FMXePp!Rpl7}aWFM0Tqc$0@Wi9cBlzIc>}M~P2)_>_2+hgXSTd1~{; zvphUYe9ObP#JfDaOZ>}f_Qk_IJWPDd!^gzSJiJW&%u~xRp620c;%gqhCf?@ZZQ^fM z<1ZfP;c?<~9zG{t=iznYcb?jR@jMUD6W{ajJ@Gyd?-T#Co&e&39v&z@=;4Fng&tlg ze(32HAfD*qiQ;t)O0r5-^&lKPE@J;bf z5APKJv|35=P!A6kANBB2@lp>j6+iX#A`nmY@Ko_t4__5;_3&2lSL;zA9_!(;;*2fNy&m2x{%buA#DhINSbW&ShsBFMyqF#b^g0kv_V8r! zWe;B#Z}#wJ@n`FSARg`E(c;q{J}vg|;nnm+pf`eewufhnZ+rN*c(;dli+@|s1o3bW z4;LTz@Nw~S4=)!#_w-T_PxtV2@pTVh7jO6QcJX(Q2S7aD!{f#0J$zog-oxv~?>)U2 z#PdBoUwq%g_r?1?ykGSp){{X$dprR8oyP;9u^tbA{?_9G&~te_0D5kZ2SBgo@c`(x zJstqP7mo)(@6F=@(0lcG0QBBH9sqq7j|V`X&Eo;kXZ3ghR2OSKA9O4{9snI1j|V`< z%HsjhvGaHUbSyo73LRUI2SCT#;{i~ADC-fSbK&s-=-hZb06JG54}i{{#{-~q>G1&Q z+W^VP zD0D4)JOH{jJstpEs~!)4u3e7@K-aRz1E6c$;{njM?(qPq?%R4+=w9%60CaD7JOH{^ zJRShuJ01^!?j?^0K=+o%1E71&;{nLMaw|P7On(I6s0M$)hS<*uJw2T)St_GbZ9R2cmOmvdprP|t34h7&D|akfaY?K z2S9VX#{;0b-s1sK-IT`zptZo`0npmu@c?M8@OS{Uc6dAhT1z}00Ie+^4}jJhj|V{g zzpMv{)*_DwKx>o71E96a;{njxhaTQZS{BnwAOm_+trP>9wSG3wb;Mij6!T z0L4lk4}fAPj|V`pl*do0*vgx~vf~_&2SELItVfDsF^>m8v6;sMpjgf00Z{Db@c<~6 z^Y}Rx+j%?yiuF7m0M*f1PZh<29uI(GLyreQv7*NVpxDvl0Z=UI@c<~c^mqUiYkE8Y ziao6di(*la2SBl@#{-~P)#CwBA0e+8Hc>3=@v|zn^>_dj>v}u@>NDW+04NsrcmNa| zdprP&l|3E+#m*iNfMRKn2SBm4#{-~P+v5SC*E${m#o`_hfMRox2SBm9HxEGNM2`nR zvAo9vpxEBy0Z^>(@c^iv(0als7w~uhlpA>mj3D#Nz=_ZsPF(C|B`#0F=9UJOIjNJRSh$HXaXvavhHcKz$di=Ztb8j|V`x zk;em|T*>1BQ10aM04SI8cmR}Jc{~8hwLBgG^{2BQHOj?29suQL9uI(WHID~CxtmuG zho9Ty=T>g#@c<~-^LPMMS7|+MlnZ)10Ll$L9suQv9uI(WM~??UxunMfpxn~q0Z^{# z@c=0Iv>rIhMLiw><)$7FfO1uj2SB;2#{-~T*5d(CZtL*?DA)CP0Mv)Vdgdq>_ILo4 z8+-im%9TAH0Oige4}fxMj|V`xwZ{XXT-)OTP=7t^v7=nv;{i}^?(qO9SNC`Tl)HO8 z0LtY(9suR`9uI(WeUAq~^`+L6M_Pc#10Zd{;{lLX;PC)RJMee_q$POj38XD}JOI)f zJRSh`@3S60(jq(_0BI8*4}i1^j|V{7g~tOREyLphkhbCR07&cbcmULw!{Y&v7UJ;$ zNE`8Z0Hl?8JOI*8JRSgPDIO1iv=xsBKw68(1HfJYcmSlucsu~oW)!y@`}cSNq}_Nt z0Mc?i^&HZ6JRSgPJsuB$v>)p!BrV9}0gyK2@c>9G@^}EG9eF$e(vmzL0BK7e4}i2L zj|V{g(X0oNv?z}UK-!eY10b!+;{lL% zq>Xtz0Mg35G&AaFJRX34tLJ+>0Mgbx9sp@=9uEL}9pC|w7U%H*NSpI`0HoDxm>S(BlD+Ht6vHNGtSs0Ms|m;{lMC=9`^>_f(|IXt9kQVFl07#qlcmSl;dOQHq zZap3VX}O+yE@`_S4}i2@j|V_?*VfZXTCm3hAZ^&=0gzVg@c>9W_ILoKC3`#o(w03Q z0BOx04}khVS`R2`(H;+gv}unAKw7oO10e0%;{lMC?ePFe+xB<>q;-2d0P3q_J)@+B zdprQr#yuVYY2_XdfV6Xu2S8f7r=CvQy2k?`t=;1RP=875F(obD;{lL1@9_XgtM_;S zq}_Ww0Mhb39sp_k9uI)Devb!0_2<@;N-V(R0T3JTcmTu-JRShC1CIwlEWzUe5L@tg z0K^(R9su>Pv>sMs5greK*o4OeAXee=0Ek_9JOE-D9uI)nhQ|XS*5UC0sE?5Kyb=rX zcmTvkJRShC5|0N!?8M^%5KHlR0K`^29sscxj|V{gF|9|ISd7O5AU5O0Xkh;y4}jQ> z#{(ditAr4{1HP#G*VN0I?~L2SBXK;{g!6@^}EmvOFFDu`Q1WK&;E-0TBDLo?T*L9uI)n zn78`aVM{$80I@TV2S6;%;{j+GtMBi=4*U0b0Mx(IdVGn+c{~7Oa~=1mdJOE;o9uL5k`?h*K0AiOO4}e&v#{(d?>G1%Fb$UDi>ic9p$HYQC z9ssdXj|V`k)Z+mVJN0+~#8N#T0I^k%2SBXV;{jkV6+8f9u^tbA*sR9`AXe+~0Epds zJOE<39uI)nuEzt=`|ehc2S9xptf!e+u%{keY}n%g5G(e00K|?x9ssdqj|bqDCtE!p z0I_C|2SDuEdZ39#dprPQ(;g3iShdFkAa?EX0ElIKJOEO)T8w z0T3JacmTx8JstqDbB_l=EZyS)IB`p>#{(eN?(qPKy<3kpv3PGDfDc+d_4#7;9uI)n zy~hI}mhbTZi0ykk0Al?f4}j|bJr;oQ?+3&0VgHPODEvL_pXYl>?4Rd{{quUTe_kK< z&-;P>^ZsD}ykFQq?;rNh=Yjq6`C$KiUf4gMANJ4jfc*gw|~ z?4Roi_RsYN`{#Ot{d4`n{<$7u|6HH2f38>9Ki4nppX(X+&-D%a=X!_zbN$2qxgTKv z+#j%i?w5{m|G@sapJ4yoU$B4fH`qV-AMBs|5%$mh3H#@M?FjcT?4SD?_Rswd`{#a# z{d51r{+SP8|I81tf94C=Kl2CdpZNs#&-?=WXTE{`GylN;nU6Zc`~>@FzJmQTf5HBl z&tU(|Z?J#nJJ>(-AMBs`up`Wmuz%)D*gx|p?4S7*_RstZ`)9s|{WJfjVLpcaGe5)r znXh60%-^to=5yFT^E>RH`5yMq{15wQJ%IhQKEVE2FJS+yAFzMclQgU^uz%JY*gxwJ z?4R{04eJx^pY;m%&-w-XXFY@cv%bOpS?^%~tbee7)m%%+^%C~a`U(4IJ%#?ao`U^*JOClyg8dVJ!TyQIVE@Etuz%t;*gx?b?4NiJ_D_5V z`zPLm{S*Je{)q=+|HOx|f8s^hKk*~%pLi1XPkagcC*Fkp6Mw?~iAQ1o#HX--;#Jr` z@hj|~coz0gd<*+0-i7@W|E3`xhW!&C!~ThvVgJO>uz%ud*gx?#?4NiW_D}o``zIcU z{S%+V{)yLN|HSXGf8u%AKk+^6pLiekPy7%2Cm(?QlOMqT$roV%p!T!mYVE^P# zuz&I?*gyFd?4NuK_D}u=`zIfR{ga=;{>j&1|KxA5fATrlKlvT(pL`GYPyPq{Cm)3U zlOMwV$roY&lV8LB$+uzu!^r{to*m zpNIXE-^2dN_hJ9!|FD1b0N6kJ0PG*V0QQf50Q*Nzfc>K{!2Z!2VE^b3uz&Oj*gyJ2 z8uSX-Kl%miA3X#1kG=u>NAH0Bqkq8u(L-SW=p(Ry^b*)V`U&hGJq7lUz5@G4Z-M=z zzrg;{V_^U2Gq8X38rVPj4eTF12lkJ?1N%qsf&HWZ!2Z#LVE^btuz&O-*gyIa>>oV| z_K&^<`$unr{i8p@{?Vgg|L9Y&fAlKYKl&ByA3Y29kG=)_NAH6DqkqBv(ZgW>=wq;d z^fK5#`WfsWJq`Acz6Se8Z-f1#zrp^|<6!^jbFhE(I@mw@9qb=H5B86~2m43wgZ-ob z!T!+$VgKlZuz&PI*gyIq>>oW5_K&^@`$unt{i8p^{?Q|0|LBvjfAmV&Kl&x?A3YQH zkG=`}NAHCFqkqEw(L-VX=%cWI^itSA`YG%mJv9ybst>vFV_KzM5`$wOJ{iD~y z{?Tt?|LD1}fAn40KYB0hAN?2hj~)#BM<0g$qZh;e(T`#O=*h5u^kvvTdNcjs(Vt=e z=+Ur$^l8{XdNu4H{TlXE4NAHLIqyNMH;Q_FJ_yFu5UI6=t zAHe?M39x_o0_-2&0Q-kO_`oAz|L_UeKfD6=55Iu@!!uz2@D12MyaV2=)&@g8jpjVE^zX*gw1p_78u8{llYR|L`f;KfDU|55I!_!?R%j z@GaOsybJaZ|API)!(jjLG1x!64E7H{gZ;zPVE^zn*gw1t_78u9{lnv6|L{53KfDh1 z55I%`!}DPO@IBZ+ybtyd|AYO*17ZL0LD)aM5cUs0g#E)4VgK+&*gw1x_78uA{lg<+ z|L{rJKfDt555I){!!u$3@J-l1yc6~h|AhU+Lt+2$QP@Ac6!s54h5f@*VgK+|*gw1# z_78uB{ljBn|L|GZKfD(955I-|!*gN(@LkwHychNl|Aqa-gJJ*hVc0*s81@f8hW*2n zVgK-D*gw1(_78uC{llYS|L|$pKfD_D55I=}!?R)k@NL+?#{&@fH|!rC4*Q3X!~Wsr zuz&bD>>r*E`-iW?{^9MgfA~A>A07|;htI?Q;q|b8_&w|&o)7zn@5BD#{jh)gfA9m? z?-&#O0`|8&NAMHabMqR(Z(y&@dkB66dvCnQ;8(Es&SwaI2K#J$Mm{T_Irty!Sa3{& zKf;a`$1M0K>{xP4gTKO#HOD;oFYH`!PJ%zf&K2h@_&4laa!!N4!_GD5JorECTHu-p z{t&xXxMqTXr0ZJJH5L3NcCB&E1^|BKxV z+!MhcWA_U8Oz_Xxy~I5g{55v3anA++jopjfliZu!qrtCZ_b&Hv@blQc%{?CcK6dXj z2LwNm%?->E%oWTT!9Qek33E#D7uj6HoD=*Czm(0L%%QA~M+ zb3Jo@@PFA_z?u;JVYXJVX0Ud!h6F#Etu3rE!Ea`34{K2HquJWT8WsF%wsx_G1wWgu zZLD#@?`CTsYhduh+1kh&8T@j#cCv;BKb@_utg*pwXKOEOaPZ^V+RPdq{Cc)_vxWyh zpRMhz@xkwBYd2Qf(SBU)@ij6$qJ%o6;I z7RwOR1b?H&I>bD||7fugF;VbGTC7CO6#SDGOA%8Af2GA*#9YCDX|WhFS@36CtVYZh z{F@fb5z_^Kr^R~2e8K-|u^=&F@P}HgNX!`gqZUgNQwD#j#hS#N!G8+-x0p2eQ!Q2{ zW+iqdh7EpJi*1Q(yOP5OKfC3&;smWz{<2Yg4Rfzi+ubIeqZ=Tdq&eAN>EO1)vFp`T)}k&*2R1R6!CS1|1Y4I|Vu!2V6+Kg zDxto@v=%g%P=8@s44O=+&oHe9%_h`un3jX46Y4um>p}Ag^&h4Mp$Uch5Yvj#j6(g0 zX-Q~Gp}xelCN!r|e_~n`npCJyF|7*CD%7u-mW8Gj>RU|fLh}msFQ$c|iJ^_5k)f5L znT7fp)6&q?LVb;CZD?+x{>HR8G`UcpV_F@WU8vtNEe}mE)c2UyhvpaRe@qKR6Abl1 zrWK+YhWa7X644YxeUWL6XpW)&$h1f_$xxqUS|yrgs9!QI6HOCs6OA*}JDK*028tGn zCK~FaOe;k*4fRu|rJ|{Z`YO{}(Ol79(O^S8mT9wSw4q+hv|BXXP|s!BE*fvB_cHAl z4LH<;nKq0@9O}hPJ4Qne^<<_kqcNj3qdABAGuXdr(rD9Y)S+I@v}-i%P|s%CHX3)R zcQfr94LsDtnKq6_9_r;xJ4Ztg^>n7Kqp^p2JJa6L;6pv0Y4d3Gp9$*lm9?{qYj3U%48oPjDgnC9} z8!(Pg?`Z4;1`_Hajg7!aLcOH16BtUUr-c2dFqTknY3v0C1B-#lEb6MyG*$z%3H6)C za$q{4zSCF_%qP@;8ViC6h5ArqMKGgKKWZ!qrWEQ+VgJUQLj9?+D40~JPc>ErvkLXA z#hyyM^I~dTwL8Fy2t_ZR{5Y9O}W14a0~-y|}Ss7&0swrX1?ajWxrZL;bn2=wV{g zp*|hY={gSo_0b?xFtP zSUgNV)aM(khuMevePj7B{ZQWz`={O?_P-1dKlk!dw~Za^kXn@#w+pw=zN)HBlK@DF9#lg(BHwl9(Vx6{>=k|7X%ML z=nr9D5j+5)e}s8S@BoDV66Q6*0}%R8m=^^P0Nxa?PrNF407Cx?^RjR~<88qM5c*x1 z_XQ6?=!aq67(4)>Uxs;S@BoB<8s@FR0}%RcnD+(`K7wD z+k*!n^!qUH4<3Nf55&AdcmP7b5c3Y<0SNs>%v*#90Iw1AjpiToAccM;=1poC+vQba zzQVhN2O#t_F>ezdfY9&6yia%lLO&GqM&SVn{Zh<3g$E$?Q(=BJk5%ZmV%{q}0HGg? zd9&~U;MHQj#=C_FAoO!FZxxtHv1P_4L z8~V+d_l)%iFB%?z(4WSo@;YljCQ^xrWr9v%R^d92TP_3!}T-DCa6%ZCRb^!G8ZA0B|Xe+ynfJOH6T zka-310EGTQ#1rNz4E=@7YlsIR^dB-WA|8OypUAw5cmP8GBH|hIG=~00=5@paAogz_ zNW74E078Ex;wAG;hW<(BrNje(x03iO^jk9TB_060n8ahDKa+Vi@c@MWP3Gmq0}%Q< znb#8!K-|X$FDM>>&>zaYqIdxCjuJoOCB*{}`b(MD6c0e?KV@E2;!(V*cmP7bD)X-5 z0l>>jJd3v#4**_Q;@!BePKP~gt;sL;GOT4Z4+dR0TAD4M^ z@c@K=UFO}z0}%Ro5#O7~H}v~5?=K#J&=1VK!FT{dzcBL-;{gc$#LQca2O#ttGw(4T zfY6VO{KP!Uc$LXl@Gj#4P(EXxX5}~LamMRRzN7rdJkWTd$%pVp;{m`cO}>P88V^9| zr$&Bd9_!F=&Aium0L1>ylZ`hU4?yVGX5MW)0HL3odAsodgnn=4{l)_j`oWnu91j3q zaq>mwkLDo{{p8GBjt3z0nlVQRss(IwG-$k)KcI92>lh&Tj;lFwHN3w)MDTP z2>ltYRs#<}=-+6y9C!f4{;kG?S`Rz`q5q@Rg5UuN{UNPZ1P=hUBj`uelHdW5zGO8f z(wpcvX|*TlPt>B|0SNsmtyTpOKcC-m>MS{^(A)b^n7QR{;TAnx}?Ef5}n z&>s}N&}xQ4|In^lB6$Epe^IM7!UGWck6JAf9)QrF)M}OR0EGUfR?CD3AoMr2S|>aJ zq5rAXLg4`j{ZXw}3J(CaQ|PB+|MXL}+A2H%q2H?2Uf}@<{aDdwtwt;KYqi=fJOH7e zEBda(0}%SXTJ0AefY1-tYQyjVP%DOBOzjvRfY49YYRm8dgnqMDdxi%f^rN-fG&}&* zs-ag?yM_lK^s}|vHaq~K->ucY;QxTy*?*B$DARd6wAJ}RI@c@MW!SDpDDGdFE zt=13^K-}Lv^dq*~MEC@?ig*C1U4&my%ZLXc^f$IzM?3(b|FP9V;sFT#k*!t|4?yUj zY_*hl078FdtF^=f5c)4$EhZiSv45-4q*fCT0JWR&o6yf0zGF3>q2IIBe&PWL{h+Nj z6c0e?7j3npcmP5_X{#;80}%R6TkRUGV@= z`wIV}78VZxwXyIqYGv^Ng#Ou9ON$3Ue9dZXkL>EVZMC;}0I0=<$5ES$2O#w8w%T1h z0OENLo)`LiTdgl1fVdwZwZM1)LVs|0q16nB{^3?jj0Zq`(Q1rCzj3QQ#sd)gky~vt z9)QrV+-jHc0EB+#R@;mRAoM%8+Gjifp&vSY)M}(dzjXMi)li3i>hM*ou@3##t@auZ zK4soGvD0XzWo9>9Mh<34m<$5R~;Sz zdUxR8p_d090D61i@1fTR9)P%CD7`@N0MHu*e~{)1hX;V(A$S1jC4!%b-XeGaG}k!% zMw)vZ9sqigXikFtJ3IjND!~Il?-Kk=^fJK%pt;TAZ=%-;9stdK4*wIqQ1AfI8wGz9 zy;AT1&^rbH6ungN0MJ_nf0gE1hX+7&ufqdCFBbe*nwuRS0D86H*P?d|9sqi|;OC;Z z3myP^z2NtX`=-(h20s|RVekOZD+a%q)((dUfL=0q0O&1)zl>fpcmTxy9sVVOPKSSvUOIRH zw6;3@b@bZ710eSA@ZV`Ic6b2j&4WLWUOjjK=-q>Vk6u1_0O;+5zmHx&cmU}Aga40S zKzIP?4TL|CUO{*O=pBTAkX}M~0L1(W;qV{QiwF+@y@~KA(yIs$0KJRw z0MN?_KO?=3@Bq;32*0CZABP8kUP$;M>5YU3fL=-XB^5h4JOGNN9DYiAE1AEtqpRnV zVlRgWfL=`aG3m{O2Y_Bp_%-R>ga<&eoWsvaZznte^m@YY8TZkp7ZiR_dPCs>pjQ-r zQF=$=0TBDQo>KId!UI6BDg37Np27n_FDg6$^rpfCpjg%6S5@rl@Bq-u3J-wTzr){3 zuPZzNV*d{Rt72h?2Y}vK_+u3-J3IjN&cZ*dSlZzM5c_xdYw5Lx2SDuK;lHI97ajn5 zbK%dWSC@GJ)VmA+F1@_)0MOeDe=ohh@Bqa9gy{u_2SB-j!yinqFgyVC4#Pi8FEKm- z^cKTkOs_FK0Al|R|1rJD@Bq-841Y4c%J2ZtyA1!bav6sQK)H>>-%PJFJOE<<4*xT~ z(C`4z8x4Onz0&Xi&^rzPG`-aD0MJ_ve>J_<@Bk?Ha`>;6i#a?1^k%~YK(97D0LtAQ z{%v}>;Q^qx8~$#3z2O0f`zq554i5mm;qZskD-I6;z2oqY(@PEyfY`soUrw(%JOIi) z9sYBA(cuB0Hy!?Tdez|pQ10sRuhYv84*>>8K0E;Q^25(hZ$CT$ z^!mf^ANQB07a;Wj^ajKOK(9dR1*9D~JOK0(!~-C0!BJm8uR%NjV*if%19}nS0iZV_ z^$F4{93B9A7gE1KFGD;4^ftr;AgzNv0H}X(cmU{yNIe9-5%B=fE0KB$dMDxmpqC=` z6!cca13<4u>Mc}%;qU;^i;;Q^X)_KF0KFQi*PwSJ9sp@Mj(QGyJK_PL*CX{F^nSzx zKrcw@LFf&M2Y_CY)QiwN5)S~qB&jE%wYt>AIy?ZANPBj80O&=F2SD1i!vjFCT08*suBCpBUbc7u#Qq)iZS=au z10eSAsDGmuE*=1S<5C|-uUtF;^vP~#ft}k-n`W3 z(W@5^0KI#u-;{o(--`*+m;(F+(40KI{!52RNx9ssceCx&3Xgz*4~ zEja26={1Z8K=$%acB)ydJ0Eqotk7cnIhX+9H#ZiAL7US>$h|O4!X0aMay(Ybz z@c_`vnR-sK9ft=%?B7xEDfZ*=0EqoN>OtuZjR!#N-%&40?`S*#Vo8pAQhH0{0if43 z9ssc?>p?B{@2E$mH#HsrdR0@eDt6`Y0MN^tdRBT{;{l-8HTAAyUk(p|*uSG5R&2~! zeeAHVp4nn&4iA7>n)|xyX&c6N_1LD@Hubiuzjb&3#Nr(Fxb)`610eSAsMi&{b9eyg z=y}j`Ov_9C?^PAq^cmTxy9reKU2FC*+R_Le~rgu0V0I`2ZJ+auL!vjFCaq5l5 z9vvP4v42NBve=}<10eSAs8^hJ)F{X6Qf>BWu*KShrZaq!vk=ldh6o>5c_x3+l#$BJOE<<&U*5zH$NT#v42OszSzC>@E7}c)boq& zTaSNw{o?`n=%bHXssF$B$_=fHe|LQ4^+PAMp8uOKZ~Ok4w=JDh+qs<^fAx~#Yqr$A z_1=Dq7yWnVe&Z^ZTz1~J{Xf6`^5rdm9n$ZB;rAYS@hLxlZ_xU`{$&34^$!mH#gnfz zH$QmR@Ev;pa`u!xo<8zB?XxfV^P9UJ-|q|0O#A0c?&Q1kZ%?}EsY6b`YVq^u|N1-s zI`iw7esL`S=Vu<{cZ^{yf5YGM96T4#$#e4>ycVy?Yx5p>FT5w-8}E_#%6sO$^BMRo zd?r2{pOMeXXXdkW3@+bi&42m#9S1J>C%?bp@5BDa_(zYgdY!*tUis&ZJm0te`TPq! z{|--Xe3sX{@9@$yy#AXn9s30D=lWy6_bBi08!sQ6@_u*T{?#?S|848n{g}^l;UQ1` zkk2<@+&16m^G>^B$(?-ui!bkg2ghLahrMs(7;IcR=xZE~AteCORSeu-o7nbL1B=NPP8x$uh|gW~rmeSu@p z{KRd`I0o}t_Fcv?(8piKG2q`E1AfmjU_8fwzvme6d>jLwpJTx5aSV8Ujsfq7W5E04 z81Q~M2E2cc0iTCsz~|!_@Oe1~e187V&pgKO7{gfphQH-GcrKok=jJtdEnbt?<~{IU zcu%}H-Xrgo_so0eGw@mXOnf#zBcGMe{Iy=WT!90SE9Gz3fAc#ObGhp{Eczg{Cpwr{Hyr~^>gL*`p*aYf7PA(&qu{v^7X$RyJ-2{apF1etmM;xVw3}7e;by`PS6>FF!VhE0jXz7dDHT=hb|rPAhm%7%S84tpdHYt7Xh$h+Gs z|6JL)`{KAa;<%4;H9yqPrG@zq%ErAA$8E3Y=sGI-T+Off7*&OR^jJJB1^ryf#~7Xs zEaqzN*FQ=-7f&l2ct9LDH5*u!t9gx2vVTQO*}ya6!0WPseRDNO=pUuwz3wO*xFimI zARE{(SMw`A%&DLGW!b>H7|1DkNk7=B+bLI*GH%A6ZeT+Qb>hVSipLD{(D9QaWoSJTcj9{ahqWdqyez+YzrD{?h|;Td1p`%h&9AC3dx z%LdluYIfkW{C(d(8XrIN8*$*?da&z)&_Ue9!6^+KRyJ^Z{cQKi$@(E4?2GktY0tyQ zmyH`9$1RBCbg-{t+);;LSvGD;9LFqT&!>aET<@kd_wakm#$6M~Jr>95U>A9R_aFXz z*|_`TxWDO#>|pES$d&dxBBw(cKk*;pz#a8q*C*D&UdS_kc*K5X11t2iePWjl)WKfN z^>t(8sIq|rl&KppG`KFg{Ri^>L`9S7c!4b;Kz&_7BY$9<=4;4=MOa}{sttaH|u zJya~3an%{ew{hslj;p=KwZ=b3X#I{EP!Fb&jvmGPs-?pF3V zcYV#jc>K(9L&_fKCa-yn=NWU}$z_joPuIMnCo7GcIHl}yyM>v2FV%x~a<|Xb?85ur zH0qkNaWnO^P11M7ak^Me=5^j0b${8o8{)Vp;<#bCnn66@zeoL{Y~0V{xPQcP&*W+< zb)ZTgjVe`b{roS-al7b2y9OT6o%sPT{F%`M$_Dn*&-Mn7jsv|0o~=JG4I6z{*}%bZ z;H)^XO4Hy=3>-hYwQS(HIPm5;@TESv8culWKciQb4O|`vrg5O}o2%j0D4lZVugV7A z69@iTKiI+6)%Q5#9zN^8W#fJu$Mvb+dI#UY$$R{)J@rt$I6l<4nn!r&PoH&I+2h&4 zJvILQ++5ASdE>u5Yhu~BL_gaxyEu;fd#>gv-p|WtT~#)2S{!$~ez249l8)^!xcc5X z>%Ovq*TsRI*+8vD6FB`lp8fl>fe*xi|A+&WK&IL3>Mzm1>BYOS5JkTQ+b{{cKCXxblJj;gw#RIj3yki45%26D%(u_yq=@ zc)?f82F};dx%_AHpYOAMO|j3eeQGtNuy?MeCec3?(d?Kj_Bp)fh?*0&*Pn*R^(iXC z;}tw!na`iFeO^CQ?U_4a`-AlPs)uBM=C&DcuPA z(kUzZ+Fw^n!J?!>{=GiEb9sH~*ZO~c^5N$;&zn1a-o)AU(`L?^I={YuOT*Cp&YeDI zVf})+b7#%3pEz%J{nXi$rcRkMb;`Lz1|C*Fc+kOzUNrbzJw9O0+&NPROr1Ds=D9QH zOrEuH%G7gbPn@SqsK5xU_ld{DCw0faB*cn4<7i|ImTadmcY~;({6amo8QQHQAnE`~rK1fs^gH zEx2Unlqs{O9zA#JwDE%v9XkG^gAdJJbjZQu7w{KH&0H{Q>cuC_nKHG-UiRRjJv};f zNKSvHzbJpMdDEsX7_Z;-@GRq}&1{)EW&FW|1`o;2pV{?+#!owBaBlvLx$_p(6MxU2 zdD&DxSMK;z&#XVXUT0$9A$BeX9Xj~1`u_8#&YC)L{?z^I#~nH9l!M|48!%-2VFM=3 zn>c6kjQV*~FP=Gn=G-~;g9i^8+|Y1d{ean%n-?}t)(cE+88Ca8{=Hzv!r7DbeVQJh z)_n1y1Lijmm~!w?9+@?F;(`G>(~UDG&YMy{VEU9xCeE8SU~v6_(+;U0Fm2A<0rMBk zn>krSX3dZ-d#U{G+AY%cl4ZAp9w;Bwby0V_kvIe6$Hz};KiMtc!>h)_)ooVky0*K$R?q7| zJnNq_6?DH6xzhE#*$TiJKj!drk3MDe38TCIJAU-k1q++UpEYD)OG|kCn9(E0pFDHY zxufSUoHu#uxyK)U^#5?=dtQFRwI0?T-a<}Kb9jA!)|xXc445`|UcFY9`eQ>VP(O0s z+{sht&!0PQ{(k=-7Ngve4GKsm5=-Rr1NCFY(Ov7(DZ_G=y{k^?RoJF_yV4H%&*pb3 z*5!B3?~>m&zgvEf!e05@!1rgT`JdlUPrvP& zv*SC-4i7SW2d(K7k23E>`t9EaLUw43#ThwnKoAonf*L*(j=vFddlp#6P4gi zR{|Uc%pw5~KWin-4J65(s(^o>7Vv=+7bsDiv~U3l^Z(=5t{R74AX&q{hJ^3&TbJaJ z%k8NL7^mFYzPgX&cYN)u|4aY)U&kG&G5k$@ex7fm{vW@h$T3O}l#he=^uQ;xcK41CgJ!YOp)W=a+iLp`qzX{jytIPxLfifo}V0dOt*2HzMjvOdN_XPbQ|~P zxAeO8pM1V~-N!*1^}qNP-vTs(hxN_A-qZoDl`t8<;<)d18~47zUD;vDjx#i&{P_<2 zbmuHlkGo&vmh~`hXH6{S_F_LT=sepM1U>yNzqVOvi8QujcdPEPu9bEd%yd*+cd6+`CwbCf zy*Igp5EA4q#j8en2q8dth!heY0TdyCC@PgVf(8f>1Q7)hkha*O_0`rI>Z`W({ic9P}t!*s=h5CwqR{y`>nKQd{H$fs&)aoR&zjNlyoSB`So!ve2xZmO! zl{#C5-y@zA>^;6d@HV6HV-RmBJkNv8aeGYPx26Q%I)qzi^}Q2|clfD6R=cwC>SOs% z`4Xo0KpFEL25<9ij&~KChIt(eeI-tSCEIB{+vS~kT7Wq*Oko`3(H{|uclM0H!z)(k zY`kL-57io8`adAvv0<#JOhpKDs^4ofGw_a!<;!H$>ogCUEVLB^c*i4rEj-Vcw+pX@ ztM9orfwzl7b=1?CbHkI~p7-21K~@b?zgrUWZjR)WUK>||lr9PgFdrjZj+@YN0Ui|D za$Ic31zv7U?o=4!u_a`ucRECoH;c*L7R>Z{F*!y~9f#59m>d_vaRDAU+4(yUAjAv2 z7BP7XCpF~-F}d@iCFxtnLe{;eG;)3=GqvttKd+nBsh81V(B}^a};RzL!b2KAzf!8Z0?-dC_1$cwWzN73@%|r{l-Z6RaSo%IO zd7qfPZ%p1dCNGQ0v#mIR*DogT7fatiCg&XF$OYbjn0!Da1QmD#V{#4*MUGG6?D}z^ z%uGKhCLa_f28AbdOnzKUJ~$>H9Fu=OCg=R;$OYbzn0!bi1Qp1eRTLC>6%ixyVKIJ0 zj2{`}D`Whq@SQ7xcLzQ#>>Wy5LlOFC+ae5~iAq#Xc?)l{)tDjQ+@sx093DkQxc(Pf zUi6iEobN48^6T$?-|~3XC_;TdY6yYt0_At6N@I~lPUnT>`Z>b_Y|8o&fcsv@5 z@IG<0^0ZwQ;rTq$@_2PA!r9DH{smwW+Q)^Khms<^ztkyTBm5xm0p)pT6`{R7uRNbL zMP6U;4dqRFO1uJnW#Ttxk#~&8$<}nVp%meHG(`C|Ql8%4WaatIQiS$it^5|~E%F9? z7g;%U6ybg4>&j0TzO#3`^6dGF@I1n2jd7B`m-meFYee3|`@5Cngo^Ndf5-ATp(5`{ zuL$K3hgX>*ucddiy3!$p}2rI(-CFe2IO@}YS^M1VY-Wu|s_oiFEoP5e#Z21iNcHUac7n1MhU1oV{?*-m< zmIoHW>V22xQSU`~KK#`3Qh)8et;!>N$Xj`TvU1UfMvqa02D533XJ^j?2uI|yW(aV2 z&K*0D!4nx-Xb>txQw>687^XoehkhCaa?qtgAV)VE1Y)$LK^O|!$l!<$!bpktE|#M2 zT`cFYcQH?9?^2%C-laUfy-RVPdl$a%2{%4nWN+25xAWiIiSOl%_j0OxImgCNuJN-n zr;|N6iJEZ&F#72>37%<#Ic_}727x@s27x%i24Oh624OOk7R$Pk>0~DK`e7Dp|mJBjx;4VK-!QSz{cb9 zY&9;==Hl|Pn?2ScxeeV+F)*g*OjO{`|02>S?-?{!3e(IqbMyo~bvLSQ)G#EE?4 zBl69Pc!FY;;ujQWEAst?@s=pAQCzRMS@D~SH!I$*c%R~fijOEhq4>1oi;C|mHb?)T zc);_HA|n63#4Vn8qVlH`>pX9n@@t7d_PlG9|1R-Ip2zVorsq1U#1B3173JR|-tT#> z@!X;O2;vVs@AJx^Kt$o^Dql;y*Ym!rJk8CCdpz%cn*LV#7m2rc-aE?Y;klT=%i~c* za{QJD&Hb^1mhCW-jm8dN4y64 zE00$rFM&pWC=vO0BYwm4Mkqg#_;t@)p!|8nt3B^ZNf<#||{A?bfb#LNHRm4BUh zh3B=zdkyt}j(9o7`<3rU{F>*DSN;pc%RFzn^6QD0dfpc0ZzJO7d_wtWiC@L}C{KfF z;wz|6BI}cQ3EGYF6~uL(H&ywwh!=U@dgZ@HT&w-jd7js+tWU;uz01n__3d+P-(v@6 zGNmFg$KIu-{rmUNWcrnrmYMj|^Hz@>TWMBR;O2+pNGER3(4Ev=$dvh-?uu`;Hr}-D zm*w~T$L@;Fm7TYGdkO=8Pda&Kr9X61eSY<%`sCCk_(}DJJp#xk)wkdA*!CkTAKhLu zazuS$^@#fXssGsKy^>$(zw(sdes_>aZ%rIqRi8Z0A2fdZk;4zKPYiu?+k-FfzR-J! z3r6t|m-HXQ(LWA{AER{TK-XanF^1B(c9&gcfX^K-(QO!yi4?~G6Ny|j4=<38c*}Z>!)i_S^wKqk_y#rb_0v z1%q;MXdP>aACkc2TtYg@VZqdN(8-NH`|eaV=}UYxZ7(Ouugjd|3pnQb_(1dgN@R&n zkOw$FJrBwKQU3y+fls4@_59I0aI7GE6s2Qs0*RLDHLDr3(DP4VWORI9-WnYIv6TKD zzS;bRy*+=z3m``z6R>@hZl|PYb`Td#KC1iJimDVB)f)8VP z<}gQzb_=5k%PjKHTPw=~c=;I|@+8SzCZVbpl0?`R5?x3LofS)ybBg?l{(h}n!ooIL z*pyr156w60oVw%}`K|o&oU4ZAqe4^RGNwchDg}#{(q=If*}Q0x6WQj?{mD681(i<% zWsk%tFdc4vwB_>!=NcMck&&we>3dZKij&@}epOv0#zRaZOdu4)2VU)pIuZj7Q&V?5 zh>7sNH-Ru69>YY*IubJt!-sa{jK+xsX6buVtSk?Nkya6Uh;$NxnFQWalbcD!dq7;2 zYARFl^nC9Wf+^#2U&=TR0V!{V*SBLGNmJyB1m+)jOIFvBFv=M$&XyyA%xyt@NgNl~ zQq1nk_f94ZhDWN|0CA3{6^yF#c`B9@XE@TVBC_zlH<_SOt3isRde#VXG65#G37Tw! zI)T8=0GE^_4?H{T+Jj&mUQK3L3Qx_}H6~+eT<7YO*E93-7GE`ooG#&s{QOkh;fkJi(08BKNx%nA*B&(wO0meuxg7HojU zB<_aQFDsI=P5~!^UOjjXYmHmzdfsNN_BppREGVri|X zi&g%sSL2x#arn}#jp~jUYk$_HM3*~j&5vDAWEbRw%N(aon>cckH?w-ttg|O!>7!Y( z6fKA3x+y7`=w+dV(5vDu1gn{}WY)o7&ytT`1$*_phnaw@3i4Y>$7DMib}}Oh+ONx5 zpW2YTIM|rL>p=y3qW}2%7cPk5>KEr`cPA3R|1@J<3O8~%>o}T-Z08|IA$y;T9L1T7 z#mAViyq}YkQEi99^X(@Gp3d#`$(x79e{O!Vn{W8|L%#MgH4-$-XWca*xU++GR#t%k ze3FE&x)9%x5b{aOw`uC*`_BY;n+BwJH+1ps)H*9ev(Jh*8=W>9Waun84Iys6C$+-E z6FQkM^RxLb0d3QO^k$(@84~KOY$148-@4Xjehc;S<;Ln;589>y>2bbU_!i{IE(GoB zyBzvz5Jr8x&#XRtnr7+yE%Z%uGO(n)*dwlW$u{OZsjmRu>bo8^)9^)tjvGZRh+Q|z zZ-aN^)uFJ9nLr(7^gmYAV6PCBVRbW%`O?9JlXbrNC|@DMSUy~uuzZh$#wBG{h%1La z+QzJ7o^(ai|UN=ozwGLWBjcYf$b1(^JO`BEnIyg5XjFL>ukQ3x9El+ zh6x7GtVmzHzARZ=g*c+ z#HAGEJxD&ISgd%AVlTxC#gU3~osq6e`BN3eUXF0KL+U+Cak1huMY-;fuT`G?DC4u= zCBhUbc%9;%iuWo$p!l%jFBE^N_&Y`RP1N^y#a9&nrTB*8zZGpe$z%N?U4f#s5AdH; zzF1M(3Br3T-%pVy6s8}oSfzN9A}ubIpQ*S=QQ8l}S1NyjBCS4*f0-hddkBB6BF#XQ z-=+8?#h)lXs`!K=4M2?lM@3q9$V)o{@;xMhZqBw3up+nZhtG1xkGCT{P9;2}Xxmd) z<$EZWDwZjhD~?d?qva8Ocy_RVV}5S`HK1fsuYKB8dk=thm2Tg5)vc!6ZeUm4eea>P zsis<1&aG_omcPRv(x$$}*c3wA)OQ#>Vtc{tHuY_GjMyF=IedG;@KLavzM|IDO@1p_ zQ**cGji5F4(6)ZPf83?R>bLEF@PBxII49hZ{#S7HUqZk}__&iui9=aWfuD0C*uYN@ zB9}cG2Kw#<|s=dhAQCZ+d?WpHMpmx+LAnE+H zEK?fAn=%8Ru4Q0kN2LMR*iqL);Mh^G2b(vVk;RU>htkN7IugZk?5J}LYwf7(4QuVF zH-gQBwGejH-{JTuSvESu{*^3k*oLKfBJYTh<#m84+O^5Cfw~(u1<^)Md)>R~fZ9M= zEORTv%*k7tH4c+!Yld4l7zE6m1d1D)IoSumf=MVB@)UwpyElO_5gv9;zmCMo@Q96L z=y+4ZFi5aDOw2NSnjESKoh9yMLOFckEvu;`!3PdXNif;ftdi`g5aBq6E(t1y5!yaS z)sZyHrxN(q3&S9xKYZYwuO7s z>nvH00KVp0_cFcBGQN_#`ncC7pW)QUPY|nb9cY^dq&Efn z7|%K@TY~^sU!kKfA2O@&O3*e9NN*nWO>qJ&c^PD`z6|v7{8&C(uB^W6Kr>A#Jl(^1 z!#pEaf0W+}@5bv4<*X~~D5ICz6E+aI8S$)c1~Xr}`{3R3b#>0S6=b%2zW@!}Vhupt z!${N=o90`H_pD6>WZCG5&gprZQ5j9KX+Dg0dX#7|2dmEs64DJn5H?LTQ^(obGeHN# zrishqv{zo4$Th{LNn0`NgndQ>n}yz<-gMSs7A5ruw^!8OUh_? zvEm1{NuHwVPFI|%I9HJ$ILvpc;#$QGikB!}sz_@C<9|o-HpROXf2jDN;$wtAM~?%U=# z8}|iVmd&x|o-5P6w)%St@en8s`c>BL{M^b(JCiH@&vW)>65;i`{=V|eT^Fw$u`>-x z?#hVI1)t;aIp9+cpIZ6+w*G$a5v3z&nQXqb4zYLd@K^eStd1AKy}qsHftpb$S7`<7 zM2eU+Gaz|09|s?InD5D{n3!jIE|VluGNO^leHC25-H#GOtB?khJa1yize!ijl#tw3 zOc74`gAJj zl2#OBksQy+RFFqwx?e>pZ*kC#S_UIyVAFPWKk$}8R1Plg`Er4!)AP>HC-Nj1?z*{P zU}qyx+|WwMy9RbYMyN3)j-fjX6ik2wn>^bDXp&bEI>Tc^V{IJ?u`gq)U>%7eMl!FC z#5luL*V!_?zZuYEa5AAIJf;s4jFM%(C}HW;3`o+P#zew7@G=dO1W&-3=h&Eej8RdVvhQ77P4PqHef+!Mdj2pFS;l=cWuz|`0~o)nL)EmBH3UL;D7a8 zx~y4mVxeAz> z+18_T@^rpsBeN^r*?N(g)Sb^~3S_7Jnc1A7`R$f!G4+Zg$vJy&^-)lq!VDt;RrXcjV3DX5Cb7> z3zo07)JJ>GBzT(!q{sK?%SouSvN_-_O%eAHFt0-*o77-jQn{WWLPL=35Ke zrUB{w1xA<*33XP+2dk@ZU{T|Cu!|ATrlE=e85NRHXJr?GclC{S^zlBk<@-8ln}#Y5 zf#4J;z>-%$=IWaQeT~_{Zd84xR0ekzE<)UnNS$}U6K%ZP@h!3#ymge(^ZSu#T?U!j zGz{Z;(D8fIE#GwKd|f-(lZb~)P{TBIRnT{=A?0ZELUP6n9e<_i_aPURiShaBXk9VB z@yij|4gnlNXZZ@@SvFVSY_wB;!&_(bwY)_){6N^j_{tZ#q?B`G7+`DD1RM;z80(4k zW84R~i<#F~^Bx+vi`fTd1Jju4!i{YV7l!vk0@s7roG7+2UX%PW@a>d8T;;UqGG0FoAF4dmWZ4Q(MZ)tsGGA*ekdFcIQg6Ug zl@CxnPLW@cOgBMM>J9u<<@s4jxwTR8yMz2n#Z8Kv6|YkKrs55XH!I$$c(3A56n~~D z^$Gp|qx}CW{#kLS;vPkQ53@Y)C`$c;&t-i93l&={9;Rq*RNa*?QIz?WNJrBG)8|kx z`X5`rU?rS)E9GSxkN0*0k!=0<8u-C%HT|%8L{n`wkE30{W!Y-5=5`d;-sWwn+*El4 zW{IVfu-gQuRJI-G52dxHUuElmU>`(;kKgW%$=UAZjNk5$PHp#7!|OBG46kp$X?T67 z>f!aRr~Y+Y!7EP|FiI$mWTW{Hu^oP8akTtl$@QV7RS%Z7Ahg;yi_r%63#Yy@% z0{t=^I4LmhV3(PQ&Kh||choo7D%ay+2I@}}^`?4w)_8Gb3@#~_ZI9UlP9da|8E_HnXDhU|8*Nci!y0`X`6>#vk5ktYFX?KYx2nYa@O8F*QxO5$k4Os^v`#4xkPs8eZ} zd37g&I0N4IrV^?pd~v#t#6rU)v*wUZK_IL$gca~COk`o=$*~k#@a`b7T6a|)36o`Q ztz^lhzGMsn7ZKj1JB`5J9qVTaCKcAtvY=Do)o?^|COnElm<=z6BN8i2IF90Y@=Wc_ zmSYg_h!oz|%8SM3Wn%Dl5XTsO;M0gvv}Vn!j&( ze3qvX!>A!=B2AVUIPg4i>%g%w7{_yPoy*TgJ5PLyR=ILjC|0@l?fv2GTC&Qu1gl(w zmL);{+@LlS6b=rSWyY75mLjOMXK8RoNziY~R4#YTfvGF{rLoAw(b!BdciHM*4J__S zeAuvK2cT%6jN{9^E>k7BKBbRjot0gP09W6` zj=p@ztUi7_+BDQr0e$nF084%iGFRVL=;QgZd03$zLGdJ~&! z3md5MM=Fk0oS?|>7V4X&$OcD#x#9(in-niqyhiamiuWk;K4AKvDL$dNRq<)X7Zu-D z^iesqnWPk(5z(Q@JR<0mwT<9AGaP(ZmCM>!@M4>RT-Lqx1-bmH)EhR~4^R{D$K7igMkM?tbMTQ2e>#FBEBgU^)M&_>$twihC4a zSA177!TLfvnk$HH6gw$q6zx2)W0bcxGmaH8-EhTGisKX~DxR*$eGeF)CJ^EhMcP2f z%XJ3wnM+=-Gf=KC@H-lQui_6CX(eHNS>p_RR(Y;7WH`+x#9fNCE0JesOT=U4eQkt& zG=6KwLkGitg6Z5h>L#rrE$iE48)0>GWP)4GJfFyv~1 zA(QLVPo)s@^X>T~#&0j1{qyZTh9`Hw*E-n!9@dd21Fj?Gu6)1t{8zpbt|KjlMexv8 z(K=G@&xU`vr2jn}{mXFDtk?|094C>&b)<{HVkzgzh+tNZcB4TWOG;%2zC0nvV1^zh z_uvGEW@vwdy2Hu%>0yL)lJ`=OOdd~2C;9e}x{oMrL{P z*kSl5Qp#J?tTdg-yKyAEu@wqSJ4haTCw~&9?EmsgL-snb(n{E_^Takei#jFRW=0d1 zcT3(?A^QSYFTXPmN5Hp`WV4wpPm&19MgJy=u&i{r#_f(D>AF;RZ$9qthZAbBJ0A;g zC#Ov{G;ie4m4kvgk3exl<71&jkY%fEF0k7X_)vhsjlk9~%T`I8X2Nj{-DprS;}L8Q zkwuZQOb+p7tIP$51bKjZ%W6$T&tq60BX)yI zB?V0SatYg1Z z@e!|YwfFyL>s!rL;TskmZ8B;2fDBxjf$(VK^*{(|KCS5(&wZZQr;>SWNfbG3#_>q= z;1b^ID+fm#k#+0%07E=JzxdfheJocMyiEgA_UyZxggPsm3Et8aaZmlD8_D+!$g=W< z38qT(WqvkaejmH~Hla`%gjr{0e4%&s{SFUdo(j(+58moq2im3q>D>Z-r6kl@*&6V! zzL%h{9AVVQd(7&)60}VN()$DS@!QopOJ0TmS6^`(Q?Jwqb3~}`I?zmG%f#Q~TobE5 z%5ROu`!STWuB>Am`X4FU@E)iPtD9jw54!u{-SYK7`E32+(uC!s9RZiL1|V)K^fkqf zc?IGiefeg#S{*w<`a8<^QC-tZziRf0D;}aETnT zUgZI9Lh6ypR){C7=fHDC8}p-Me71O^v;!dTP4XGVV#Q+=t(~+&`H_la6{Q^@y|e?M zwUf?N`CP?Cic1xxJs|!D>UDjw){voh@k<&*XVtkHaG70**#tw=);%l9=!8idGmVI(nb zCzW=E@JCf{?WNMb5dMOOzof|Jht#uMk!B(C(yoBC3z6r(!NeTa8=h^p{eYEl+rIb? zzu8@c_eGZ7wdUR{(*t!K zZCcjR9!@@sJdzWxmT>&+2#If)a2!Lo z3KZ;|ge~ydGba%sH!{k~qR@_pX`Cx%ZLTTG(j`t&uxd9d%F=VBC>xLl$qAbzIc%UL zw!p`1pzLzg21?S@L43`wIZv$F<$1EyY6B%{PJ1F@BfLz#B(Vh^=ZK@YPBVk8x4LVN2n%xUNZ3}jz37hfNx^|YI znX375Si8H=rMe$z4X(TLb|2bn@UO+yunkdgcD zV`UdX=IYBh`go7o@_ik&O#{+f4Z%rHfF-Yh%+*&4eLPQ|uWQ%45j@kB!qf4$J({v! zw>^|CHc8}29rS#ew`HJU6XNwCp^oQ4$M0OXd;^{H1sR?%zk376u6IB59g8sQY+gkO zK)lfHLA>9GTvR5;xAzLgn_x>QM_@b9oa4dr@%pfAuD+*GX|x?!XY;kZMK}CF*!5al z#e!zN?lobUtxXefFzkG+r>On%N=2?IcD{~?&N|uxAGh<_hn}-u*LnBSZ*yE2-VdBB z$7@b(qu7B6;Za0fSGGIK`zj7p9H}@~k$ny0O;MbqSgp8J@j^wuyfgl#iq|UMsCbLw z-HJa_d`R(^iZ3b3H*D&oTd$j8Igo#`BHKCnrrO9()%agfoU3@2qSPPsEmwYx;yT4I zD}Gh+YDKnlmgD=1w=3SKDD?{YQ_62ud{*)QDM~#f-pk7GQM5L)ca=||VKToDY9r&v zH`5JLf`8&p|y6bg^@GJ)*hmtxQ*Z5_vm2v z>e0ZF@UwDuudYn(UX9=6ZM_NM!$;I-@Y}qdrjDp@Klm@03AhO}0rQJ!T}p3F9-A0Z z_?Ca%p*fp}acywD{yy&;tT)L&>E8zQZ$>~@3CKQ3q`>~J#Iay8`EDNKU=m;vxkRqC zO?G~P{auM-2ohh0#-L&W!;>;m5R(93V^}(umdR)m;5We~4oAGCnFRP3N@ZPeg45TM znVCk%D+ovC`OGz)q?H&m|E3bs$({&IU5N-O{ap#BNj0)A_;^H2)cZ0eFyIJ5dQnYp zhTMb%p!-h*mAXK5-f( z&_$32%OCe8F;7xpxiSep6EM#(d%5z-2!uh3V2hbOxzH4|$`%ugl3B>nqU(ZHbtERj zBb+c@$SQ)#yJofIP2KNrV>9_oC9od#=YdT=Sl&$KETr1lNb&?xbOKK;hbyh|%NZcW zv6#|EJ^6X!fnXEf1*?qE)H#(Vyn$hoa_}asJPc!{o3PPgSSLw`gS@j6P3;-V9C^mp zt-}40@cQ!Dl&$t)pfLYq7S5_(HXA<_I%sOml0|3YMVTDw&5`XlTO2yMFW|yh%?~ESOO{&qT*1MFgWQ4+gFua{tX;v?PNcd(Dj0doWYAWYMfSOP4NMvb0+U_hU(4xg$&a^*J`v6+aU@ zXU5Vw-7=>mNiTcb_AHxrY|okax!GCsGE3&1Gk+;6Fw>_`S)YLe@p7M!JHWN|u?Mn_ zJBTot}4(RG1O!&`fXc_*jDI2+GAsIqO0H8v6u-J&=?jcghQ+yMW! z6JW`5gu6DLu`nF)6`T)6e8z}Ama7WhrUB_)i@x?H66&mMCU{Fzw3a6%{W7^ob_QrS z-`8L$XlyO=VkZsLuSKCUB-Giw_=3i=IR>(eJl^_xd7hkyACwdl)}^TcXv6r(K^cL zZ&kGM)0NLy>EWZIAWJI^nY*vhCSkIeY1`4P_4a#u57k+dl1ftOugl^?+j6gFS)Q zezD>?8ooyPuPAZ~3-ycb0r))) zzgzJ^mH$+6tA_tcdD(IV6kk<*Q}Kh^5f9h;m3D!AOO&^3b!k6gc}6Pk%Z@l#HVQrF$&BG3_PrxR*`@t4?$e8C*Y<;p6$vH@*&>p!Oth+uruI>J~`#APlmvxOVT?{pJbN*Pryyu9h(a4)Gz%dQF}jJ*xEXl=%x~NH zzhQhEF7fwB{8nX%HxT|guq|Y|;u4;#6nHar2%AJZKIE#9^$M9}Fyl#*#Z1DJY9UF4 zZHFW+B#E%y!NMJ6Gp!n2#b%qg7n^PKY@02Ow02WS8fmj_wgs+9mW@qJwY1q5HpjVf zEq76wT5(&M5XL$r(jwJ>_6)QWBN5KfpXWEH{W4Qnk4>W*1!`9RSbkt9t%vMRh-BA-kshnH31RL(-GwU#7L z5Je~O)Z*4!Dr8X;D5fnk=oJVO*9ph2@K_p7D1~o^U(706^X^3}I@Xb8HA9M{xD1Xa z!AXQN_-0~{sKe_R)CnGCCS>4aF&I=1UjSt}PD%ucW3nUQowK%@_EMA#Vr!*<5;qvf zSWPrin`I4SF{^~ANXn6ic_C#8mtTfk^3!Jo$6M5aG=e{cd8~z*^Nhti_(qCW@28g^ zA7HP}7MZcV`u4=K_g;Z4cNgn-!fw+U{$6vmnWOm*?A_0?gMYT*J=62d*~@1vncK5Z zrsw#+FlaAa)N^U=lKHc0d(NnyKV#|qg=Zpg?y`kq;dU+EAHedx4?DNCnTFQ!{TZEz ztl(MJ@+EVYE~}R940PT5q$wv2>)jtM;UFx4|2W#v*-?Ge>)^xt@e@8__Tw~P)_nlk z$J7X1YdniWcMYf_^HwZjR#py<_DSpNTfv5oCth0w@ROSQ((qOAHVsJcR_IDO0hXK@ zi+2|ke7=!H& z_b9%u_>LkwYMytlVsk~>DH+~gF>Bukg!k8Q8A}2mA43?c@+!qs6~CYupNkwHL!hCP z`P(_j@i8V^J}H;`26&(HKT>=`@mGp=?BE6E|E~Co;@gUHKS7_|N5CSsFJPnh5yA(k zoOV;jJ3)~qYw{;6(sW8*OyqZ1X=r8opDWU|O8yx|d!M|hyxbp< zzpgxOsf?diq@k4jp^CJWk}pw|ettj3RC@L9JiG}4LEENljb{p6ryA2d01oV=S%3$0R_`CVGDdib2{H_by{==q|AgSQEHgkV(T4Y z7&8-kieakjsB|qnk`u0$@V)Ohuu`HvS&I^i4eaqBuu%`3yRv~G(f6kUEi+E~Inn#ZP0SpMY9Pi`=^+L^Fy*TCVd_jj8C z^V8sGRZb1J85lRSc;=^Vn}IA-qwF*w#!P4GZ!{fO43t?3_F}T!AM2-F(Y}4KRcn}o zO#hWbG}XZ@Q0XX)P;0U7eT(=tt=L_p^f6JB%l<(t5z(u?2F!_ZumEYeQY+L0= zKj)Zzkab%?e3bhO$oIFY$4|Jm^yBsWN4&1q*+)es0_2@T1-}DwHiUJS9EJe>%oNef zFy3(@MO$!qjh06b?Rpd8Z5oh!-CtmKEZ(hnf_=kDXvyh_=jNNi3kP49m@o6=c@USv z+cY4(Q4nNEsI#&~;9Y&YVRz#@4E4G8QuBP*#DFuQkMXRt`uHy5>f__x>f<-KE#K9k zZ5rxW4#6ZRz>=3k=ISeiKAs=T=h{ne0M9g~@N`e&B9xoA0O2X4zg^MB%Y(AT62ly9 zyazO%6|F+N9+m;}Jm~I+cgxq_IbV?B`91*}pH?*haW_L>Q|zTLA|Ai(tz-Gu;t|@bnJ0Lo*!4~+K{nS3h;uciXgCl+pJZ)6G9}>78xa9;f^dU&y?*0PZ zHGF{L5XF&-V--1XgZlXHOq`=wt;jxs;TJ0Mo+f{(;j&;(dxzui&3jeybwKNf__Hb$$@Iaxo215+rNA0 zj$QLs-mz=U%H_MdtZcVybKZMzzWd&y-QMs!UwL8m`0Xz)xoCSLNIw)*V)uc;lVMZZ z-_)IuI%mIAw@2#Key0A>9zPFzC=6cx+6A|d-`=dlxDn$=wBH@1yKH4W{b^^LFZ~4d z^ad%AAEVY{3g3MUiMd&YnAjj0{sl0iX4QA zJM8B<6(a2C*$bjXBGr~$BKKr)0ejqFXcYxX^K(pdpdzT4DIvKdC|=IPskIDAr)23u zI`>Y*injKwVVYkv=&+HDJRgUoF}1OaPaeep{I2^mh=OwDvH%84C^#HUdWDzxtN#L6?7YCE zPdmKlT_Z=ZdGnykpYSfi2Eykp!NH$ckK=5zI}y*H#97ssz?+>HCNuI6;qyO_gMTum ze}-?t$;qd&90f@vV||_l?=R-iR?D``Q3RKRxS4`;IL74&euKcjQE(njppKvrY%#pQ zW_KtkWFD;ObrjT@*q|D<5EgsQn-6Io;1L(Ndom<799>UJ!)2~+PD{k+Mhm$m{s-NN z;YwN%KiEbLk$n+0)aVRfbd7E}>WEIdNByyQzPP{wnIX!qvEKQmL|$lyBRF(DK*2;u zpjj0^ZbV?rhK5NKcLKj?j+eNn&_;ZvAw!KIOvH(V!6KbPuu7x(y7^(;sz~X{ypTpI zn~k_A;;Fp;UEu?7TOzC^45tvH~zdngQ5J;LrPNBYy@PW5tbsY(#oG(P;8Z!;D ztgdr;8J#tIo;Srb*udcS$*~oRX;9u!?LIv+laqF%XnTSNmO^}4WbI~vYl40S_5WK; z-8`fuSWpriGUcA0C)|cPoNp%PV*chA&%d^`7ukOa`xVRX6!vSDeOcJ|R$Uu(C<)Fi z2}odHH>02zsR6Et9pLT zG)W_SOL=1JlGOtLq#quXXMcR4hRx)#g^`yw2C>!kTsboWFU>~vY|u^RcE z_E80;sjB?cgyyM z&^?Q}8Vh3Ajq-co-FPEl)LqO3>L{cCsiFpZ_ak1FWq{0=?m>9BeD%)x;?jiW`!#4> z`Wk?^G%EL4%K(`t9Y2f^FLV`%_rD<*#bbQu^t?1KMim0vBi!bTASs)xZwfMCS7)8g z*YXzK@B?A*M7221?5BEln2D`T6D0`mX3O)6M=r>!an=`GYUBc}rE*;$EhP#GP|IvT ztRLf8W04D_23?+?6OjwNHeSbw6+KWZ2Hz{7K zNEQ!$0}WqR(WNbF8TUzW9IANMA|fhZqF1V2jo z3Cf?W{B-3PDRL4I({W}I)5*M4=)ZzIkkfXEw<-Qyk<*44{s+Yu6kk_-OA)6b@z}x{ zpPzF?wml;6SE7800gILIs>pkla=zaXhbxX!9H%%@akk<-#YKus6;~?C^@BdzGpJXt zAMk4BL>%YwEWjG?)`tQ}d-+&KdL+$?oevkce(;bC2 z)b{87d}%mO*iSq1Z^98oNMjqD_sRFE-G|WBWrImL+d+9d=~ME%aac zh3v@CS#3UtG&dgt;&}Kv zFnPbHo@&Ot4f*9Q1Yy{pg7unL*0Q1E?OMvh zmjvZZsx%p&LU;@wwq61omTXzT^I@rVQYA@lB7t)un7o$w;TEtN$h*QPyv^f@tToW% zh`edi-s|JLy*{qn5q0E-87a4pl+ggDIvMml6F!c}+b2pzPC5_7TmyO?JW~;Q9hevK z8}Lyoa@QK^_}hSYDNTID(Bp`_rJ_{ier=@V-v+*`G_epT&%B7dxuR6$IvVMCL=<;C zj#`Hrx@bHBJB{CDC$QDfc!FmT`K9axwgwtcz)MZb zx^oWpIcGWkk3rDtgmZN-_7j)?;;}~`DL~jjMEZ~0yBo1}qmDka zb(;%h9}```rs2)YX~W+bv+;T$4(S|tI)2i)&ldXx;s=vW!+5j7oM;|WWJB3-(9I;o z9A0bXdHh;x3l^W&q3x13Ay?m>DCo^5i5#tLPAuN3DA4uxq#W4{&~CniG12c1#ACj! z2c8Gfyi9;l_fD?oWh?`<`SMlC)wiR)`TnQAJb0_`VkZqquM;vUB%#jgy9m6i?;S^9 zK4exOZPPXlRrG*9_mkAhu7J$dm*2shAIpbZG1PY>Xr?KJr@Ib`xIWT4%INP*tr0OIa}zGE!|w0RYQ zb}qZO6Y+lENIb@OPS4wjgyjgNZ5H1_k}u1_vbp*mN1={Em~}Q^%Ug8A|5G+>+MkTG zwQ0D6F=v#)f;Ds7b)_+6aX63mSg86UJcsD5Cs`4MG z`~l@3Q~oI;^lnvrUgdvL`OC`xOZj>t;=iNFw{f0NOCs`bt$b(Yi;0NeRk5eaWnDPp z%RUQ8FZ(Qjr(=BHJw$XBf^661(e(<-cNX{_%9kn*P&`iYM8ye;QxvBv&QYANxJ254RRQqKZK+b&lrf05$FiZmQD z{xyoWU2<%k;ddzBqxdsLX`hgDx+vrQMv*2z^8c&&H^uFW@%EY2c9&KxRFrlKJ)M-# zD3&PpQRGg&%x{Qdd_R!*J_fTj-aN$`#ahKxifa@%D%yPwzM=fJiZre=|GN}vT_yjh zA`PnK|Ds5XD)~1QX+$O8T9H;%@?8{ZI3+()k(N{PQxs`1C4Y`0EvDqZs3`ruzBe(P zj%e@Sy^pU981R9{R|b}qn)v(P2Vn>L6SxNBD{JpqmNmkX|2dAY953T5Ntu&=Q`XGu zO3b|G_(~TUU-{Kef8~R3B};=>bAx1kTEEvZp zoKB7gm*PVeyEt5hpcG$%Fa~oS=~fUnI_|<=!#@G3@PQ;pu<7Xx97{Xt2>A4wIQS>l z<2Z*b$EW;p9D{fS-i*6cG4fyGv3UZd6DZ|sdl`3`yaU|b;AGro92gmQVTb3R&6p`v zYTk4ZhHcL}ZeD}K8h9CZk+?OCds-M**aZ^zItcE9e-kS6BmTa8n(_GQXW|K4&3GvIzQ$eL!Iq}XNBF4E~? z+=a*w6pY8TCk``oA(8EZ<20_@&2#pu2oyJEJO%?Ah|RZT8Jr=(I}XgbbtJAe%*r|v zTMctw-D@D2Lu@>TjS*uQ1e<@;#$zUmVvNU-SZA1dbtLXHOtoamml2#FVGz8G$B-~Z zsY2Ayu>mwb9`hSWFdjo-gOl+Xo)1f{<1r)=hvz~_!^bzd$RGwQi^C+uA@CTk7}pIW zG1;z`7mYZqfxivjQEKbD zp;Fd4>lsSjdTyZfF2wnBwo+UD4VCgTu1x>uut zQudNV;2ov*A~jUXi^U7nHv0lKP%58B$ebOFb-V*z=kjIrox|ZWmr}Ts*Sbl9VumtbNz8~%t5{*7#FoT?d--tWtwC~ydtcp+B(A0l)Pi;Fs^+EQ~jz+1nN0A2Tb~4cEeZb+U zgFpI|k6y-IhtbvPb=c`RV^6~h+9$qMP*|ZOP>>Bo_l^PEqj`pI)#-N5l+DzjR+PB8* zBMRRZG|UR}NMpJ9a$(B~(t83YbTbKcRyG^Fr72pB0^Mc{<;bRkcJrN%3^Rzwe3>7U z5SPNc`VK>)48p9lGS0Jg^{wd`jiJ!YY4vRYZPQT4P$ViOq0Y+If_L?8cJ%R{v-++E zZPQT2cqHPNv~`xe909JrEzrmFYrkEgBz# zdO+g=#9f1UgDnGOzI6A)yXCvtIp0>0+44OB8kfEXAnrNnYswf@5l-@Xn+Ry@h3K4~ zcMCErM_@aI)5gGjd3{(mdk=y1c0kyTggUFw@)q6j12G20GDXhp8#5xz#MY*XaWKZ9 z*nU_)#_>u;t|?H!ahk9rKMnAZj6=&D$%$Y(3VM<|X~Pb>dN#TOODDh;_^(L&sDU0X0KOX_MV6QD&=L*dGOaO{~g62D?X(73&me5KCfu^(Eh9P|4^hM zn&oJwNJ}*NPKtdL`zz8IP5Bv$v__L(ta!2FmlbJ{ru=S2TBON8ruYZN7ZhofraY}k zt2FsT6?-f8Q>1a4@-HaTI!(Staf9NQ6#0(L-*_n0`v4&EAr`dlx;1%3YOmq)SvSAB zdKxxaz|W~>_PO_WpVEODar++g`W?yxmo?^9de0T0XZC`h!kFub9G5?;@m=^4v`(g27LWjtQB*o_~DE zlwqXEFi3yU2R!h)-Yk3H?$}1%&7*C0IDbPNY7j5M=gW(*ycBuor-_3!Tq5a#A0HTI zAnHCUm=$#-@bXS(RUL`WhN-UW3W6$QqZF)sSoR5&Hr$Gv_n9+xU`jBV zfR`d9J&9m)sr4ln>e8_Tk|h#tBB2yM@RqEW?Ym83CL%~&V}?{lah=O^KrmrerhY2s z^4qRVcEZ_TE9%3rq84S&>UBb|;M|g+r{sEb&pFKfejMw30`q)H$W5=eU(|uNc0ITOgH+ZtwaqXRa)?3HEp`swYF0tM} zos;YjwtZ9YlTW;H^W$XOY|K_Q9M@UiEA+zG08e%TEXfz7W*Ud^GHg{D2>FD>>t<-v z;`gCV1JZj8%=IMHS=kKmmZoSvp4-ix084%WGB@9JOEbrp`SP`q&r>4HZPS4CYVkgu zA)(I7s=>SZ1{RukVd~>6gw=NuXqyJ4cRBPSYUr$NH9}l{qaA&`zpOsao40AG(FTfXVe`SR7tmhUmpIK>)(xJRImFSgb(U%DcA#0%ZO5$~Chi|UN= zozwF!N9C3xkhV>mFNz{%bM-xfc6wwZ`kWvkZF$HX2-_yh5;qMT6dzaIruekt z3yLo(zM}X~#d^he6my8^4{ZH_mHce|@&0H2VynP&!PZ~&{)J^9O|ezMvT7F3E&k~S*fUROWBEoXOM`F+$heWqwJSI}7Q%NFs9R(E(8hSd9 z$rOLFE}&5$QL#Wma+eUo-9OqQVPv-8bqabSDCoeZ7W5-|SQW`(RFs*?#K~M5B2W&# zCcuJmhXf|2@uicT9-BG=L70cS8IU@K^d&y+yJr87T$!t?)(rbf;-}fD{UN{Ov8vhk z2}5__$a|pKSmflF-vshX_&l~_e;C;xko^hS(J$c0g)97pGwF%)Dw%3LqcJ?6aSiKN z<=@~iBtM3>4ZCwjzVqW`jTt$l*YwWMC$c)@6E}JHz)C@2r!J-p5}hS{5~0|HuaNyK zx=Z*3LaBr=PKbe_zhRPfBnBELhh0SIx`Kl7gTR6`G=8KJs>TnJrer4*_<(}(gJ22? z;|EJcU26Ow=@>uCz>4vMgelIF3&P^C>tKc87sqfE*9k|q4HnEg+x!~iN21Yu>MSB3 zc4vc!VG$|F^f{~7$e{h;ac7GyB>SuR{VgMse>AHsZXPNFzfxMi5woie*BzPbg*9E|5ko{KVQ^a*P9^XGm z^MOLgckh@($jYr$fkmnIF%C$a32>AidwCf-)r3Sy?rB_dKQ+ znddq6@h!#by9l&R1JZjN`uM=N&dOFJz|~jn=*x%9>bnB8O+y`d5R7pGEO{wpuD(^! z$Ma+P-p`IQ2^XQ-ye1%~$%{H!_ry|ox`*&xve=Mvq>P^5L`3UKk*Q6?FrEk9z3^`N z);Z_Pw;+4IkAX&&@v?}U4t>X3259p_@~|ya{B^{8hJ-pBkLaA9SBme`rr1%YqtcGF z%79j%6C|V?{+S)6wX`?Z3Hywg9VNaef$ge4v>kw>=mnvSP_#MT26o0JvGsPzqw<_|xlKNj%d`g^Jd` z&`J3oilvGJ6!|I3bR!f;E3!{#xY)CRQ^Xn^zymR&rSX&Sj|0;-j!3COpM&_%?Xk>+!egGI@p{Z zxjmU0xjjhbZq2U@D*fX|)F)5>KiGEGh;1jiHC@@evgQH&`qx9W>s-Qf7M)3d7-+vY zxQ8Sl`yi3R--e$C7C+j~I~czW&j&ev8(!{DJg?QRgY95t*2;AZsaU|M$z0yk_?h@a znIfJ0Dmb<4Kz0`+c3=eaGx41BX6!l%PUkXq9mJ!(GL=O3oCJhliT^5-B$I6B;3gqz z&aI%a+ITY{rw?gk*~v}vS(ElNII3lbji1h62xZN1cfz{ENDOaw5!s=;aGXPy4aC@Y zZUCECNvYU(9wp0W?vMU6j=bTUmy@N^e19S)>`d(2krvkz5t{NgQg%NN1w0n4<>8As zAf!6fxKPHuHe@rS};y1Evmm8n%W8%se*ZL^X6~pp-BX0he zUhOhW3elN;)aWPizUJY0(&=@W(dZjGJ(MNSZF8*P(y4Q4DTjbf(TZBv{;wj0CQGL z5J{6=72#-jEGZ<=1O;=IFXkueQcDm?lmA3QIlNs$OWKrYA}Db*aIt=13L-GYVR&^b zFHXN#Ufgl9H@f)nSN*E=dmRs7>te^TT+Wmur!0?ih+GFxu)IVpxG2WX`B^^aSIXb zCR~RY8FvPl9TeYhBg|>jqyY05PFpZ%!O}UkX5+>z3r{196lJE3CQwU6P2;wr|MY6T zY(r7DxoxkLR6b<}qxUyEvfX}cOiD5?=+4Vww`d)^n9!#5g*-7T4QpN@cyQ+EESXbX z677X)Zu?LCG@XxZ4WfCv@&RU?ePr6}om7G^VSI_Qt_tsi_{5j_4~#=kz7if!p3toT zb*U3zNj}|NeN&)s9)#@>&azm2e2m&OAiZYjoB38|ot4c-fTbz>HR7G;1Xyx9WNy9> z7n*(Gm@mU^zDq&dG$6e(5M)TGv$93tU42!p%=a4g;k7N)w*jdjM>nwRW0$hDH&}Xk3syx(p18AmUd!TzZ<#}hL4y~h% z{&qzhZy1yITMfV`yK+6Dm9&~(7cFVWIIbXhU+Vgz^v}=dj0ewxeLmdU> z&m*mMEE^rsIX#(AR*t~-2uBelUtS-U4f%$yD=MvP$YoyxCs_1b{y^BFc&#F5YtMun zjNf=-okZ=`ehb+A<2++Wj=%BL1}y7*1U&6fheu+g*Lh>gUZ9hFA1E7@%u#{9M^x`G6@R1n ztm0o3-%$KF5%;2x$|I(TXp}99(APov&dPUHp3^Age3h4VVu;U42~02Z?ZHo0UOpF~ zzedxYqloM!U$!{rFZB&%TOiN-h1f~4SdsS#!`V*|`CK9L`V&Vhj#r$dI7e~5VvS<0 z;(3az71^&+-9#9R+X3~wsc3D9 zIjlE?+jV_K%C}KGT+!O5#D<9YG_^3@P(`sNg6A`l;nj-L?qU14^^fdDZm*BbjY0g@ z3`eJ7uTOY;&F$N#Npq5V_iwTd>wesaaG?#0zsXd1&nB#&!tXH!M^yTQf}P2{U}uoW z^;5yl9MGw}SFzV#vao1(;A8#Nv0HZddH=WV3-!qpYDQJ?Tt#J4rX%@j1h@}3k>P+j zNjn(VPhUewq<$)pD;u#UQ}=@lHIV|()3S|Cb+r0 zSv_R_*n4p70pIKxMD|Zy3GxE?yx))=Pqq%;ER{M*lbW?slOqm`rB04Gtd=@OIp}EA z-V~XbKJc%WH)3eQtAw*YDi0^)uxP0taJdxiIZC~{h6K=ZRixLl5M=? z5SCXm)>^1myXdcItqW*=Shpzt+W+@^?wR{0k1Z;0mHE7R-*aX; zckbM|GxwgEIhRr6F+ycn0fsyuarSYaM{DGo4jz}s<9QHSZj%S3GZ__>Afe90Rf4zW zWo8G@yOf8Aj8NWXpiLf-&Sj8?q@go$%MoJBYir5l{bkC>cLtM(Lau|n#_W;m3VA#~ zmX9~0k#{p_$}51UdkGO8f>B<0#?jxUXwt>;d_PZ81b-&oe``7uwG`>thK%EJ>3#-p zpKqaczI<>p<$D}7PO%Cg?oP;Sj85f6qK#@ z-HCSEKID?}tRNxHamXAFoeIm6bf)%#kgw7nDfSr+*Y*TMb;=$ocGVwSZ^HIPJwi`K zc}53cto&fb;fm)fPE?$sxKL5v-;sZ<^4BO{ulQezn-#yWc)#K!M7-brT2b^UXzV*Q z{%?w}6A@mgJYTxV%j+PHFKb4?(@`F;J`qh;kZprJ$6I1sMX3+)1F!TSfqSPDskCZ=@{(<*9^Y2gpFnMm(Mf=!q>77Ufo1cRJ?ga(Cdi6>q z3VWP_f4W24Z)qD`#|HX`lV0CbT)ykt`1K`MmK;Mpgil*814}l)l^rRo_uIOs`v{{x z;?dv0noHaM^@*)Tesy35ixc8uH=&n+78=zw;x?vl3suD5)5RK0(iSa~_~gB=gN zw&&6^o+s)AEyukQ|6pNcO8!YD9ds1OBO&w%>{_9t_>egxX%*l+_Ija>7aG_1W-_*T z62twp5rla31%}1bI7}zi6*b_zC;1oHc%hCVwDIx`bGY$$32}e5Nb^q;X?|-YjPiEI z+8M?e8!y$Mb?rWOqY;VCCg9uuTRrR;;|-3@Y8S z@=^*0R$c;=FXN!bfZ{@!e<5M!%sJ3p2#frmyV?RRx{0;L2`tqX@l!KS%NWv3n$VDu@*U&2A%fWT1E;up5E>`I=f1>`S0G@M}vzRKTZbCxU#V89Pd1 zClDsUd(KjyJwfP#q@{!kcvtN0Nh}|jg4pqd<0W=1p)Wi>6zt03hk}Vh0|m7O$>4aU zgmID#R$fR{z(ebSe{nnm7SDC4U=zm^L!*IXbp)=$5c}a}apc!WlM(iTpGuRl6`G8! zd~bd}{wrzx<$~i1@TJxT`QEYPCv?f{5}{J#Kri!F5t83*4c>bX$DSr5zQJau|7ev; zd3mUi2$dC7N_-N%#{pC*5ci2z*@OiPH6^yn!&Zejz3PyZ!9q}KB_X75Swy-%uFb@V!anx~C1f=|% zL83o6BbyN$;Ky45hCCDD`q<87P61xHjjjQYoigaKT&X$^&J%5626aZ>MDT`Y)FzBw zoU=2|kf}P3ie|~<@_0NCViml}1Jd~sDkwohor$XiZ=c7y?8fOheg}C-8ag9yd5XN7 zEP1@gO!-oE94|l~=YEYd>{1={a^mi$m zbhDsCm?tTMKa(z1$MHPUnLJEs+DodA<35xRKPjKlHL$#o!{ZdI0OB$c*ccthK%{%t zWCF5$bVTd)oaa%wjnQ#rqSD%ngy7G}vx0=Q!;k1VlKYn`P&=WH!}Q7x7K)g_!>{Au z6E1ZiV-&|LPF3W+%y_;*5ieC-qsV)S;WsMYrpSAO;XhUUh2n#Xe^C505%<*#iZ2pz zbH1waZz=zt@@%Axm$f30FKb1>=P(?+tQ7&z`ERD9qkP_5L^NqZ-cRHcig}7BDt1%s zqsSKurXQ#{L{aJs;S-dftTqHyjt;E#hVpxQBucK-;A*C%>LU|}_Sm@9PE1RZft{FdlQec>`XU|5 zu?}I-g4|2+eK9m0_um8;ZHhm&6Ju<{{2M_o7fU$~--GGg_#F&9eJALy@bPyUcm~-i zWEV5`%-cb(gm3Zy*dez6M&@1L?LLl7Y0d39aF=8-@^+0eTA_ zg|c*84#_j%aRfpUyclR95frr)l(_vVDVW4|HqQk;Un5&AVJG#eloV&WUS?u(mkF@N za`ey<&`KENw8?i|z9s*Ms|Ik2-Fsn2Q0h_(6CRk9G4Jo=b;Lg(k-UKYSo(@#nuow)iLO7qkxhOD{Ha!eAyf4g&*S;K z4j3I9e_dEjLYc=VZHD?E`v9DKss|EkLipvajE)>GD{xsGb1lmU$G4GMi?PTXGp$d z+2xx8c`Og>`C$5rCvl*Gs6*o@kNz&j0*z>%);N8|Dx?dZ!GnxE54u!+MWuDVEf87EU;$iJx`hOa4)?#F$vGTaBiHMhXK=86x0(=*Z zFVuKs7rDH5C?8E*5Vw|KuA)5cBfhKh1&X~D8@qO6il(2TI9E~hK9Ijs`8A4HDN21J z{#NCsKEdCu{Jn|~C_bdPP4P)ZsaNDP`k#)a-_1MB^{AMAKA)KR2i$4F#AcD;Mrx_)lGt6B zn@7&a$)~!=E3A=Y*iU28T*>HzSp<)Znd8=f?k=fufXPGmp0+d*)7%ENq;&PGI3=BiJT?BP$k8 z{u?al{pu(hVVuOaN)j_xNz#%wL^@_RcU!ncvG4T5&1r8IiJ=q?S6xU!aIzS#0v$!K zfX*iJJX3WPkcgHo+dfag>#7exUjq$n!_0i&6#gT#&|bb`k=4Yw8; zy5m7XuRx%nLuxJp(PtCb8^NFmfdf5MDa+*}KS7zr{w>9-5`!d5fP)d(M2&3`kmB~I zykMbhXY)gFu_M8U?7t45)(OVdPi6@Omm$Jx^tNJwMP}ms&L?z+?t&{S_OH7*_zNq` z@E@(+Xz=o$s^Ca!8$MH|Mp%ZVDua6+wG{+bHKc{P?ij`pT}8$g>pl)=3z!>s^Au0xzHZx!V6{8&C)Z*dcN<|%-u z+l~Vj$ygQejHCadqDhwxy}-O6iTs;%_h~v4bs)XPJxE}e?@E*pKPjKBw|ER;IK?U> z@8jq#_+Dci%ST7FPVZysEshfj!Jm<51qo?~9}c|*nyKZ?-4+CW9(zf6EqGl5M=t3a z^Szx`NX|N8pOK=s;A2d3D~TCck&b=MSIGv)f2!W1AFl&mLrWBgD~kRH;pZxUfg;}s znV$Uuak1i3#mf{gSKO$$N%2-iqsQPoB;^?W#Wv-iRQ$N>E#A|7A1cZ^7RYac2Fl}P zE6REn@X`*^&$0b8o{q@7kl4+nCyyI7SHr{SL~fU|zteLdy+&crM(;@}3OdaO>oLrp zly=sBl(PElC*9M_>NDTqUX-%>_)_jmDXY)HPL#xx*pc!Eccfs4O6BXiE2UUgX+*b& zJ5o*ycBD8DQUek6nYu>fy9nqGpX#ti<6lhc#@7%c(ccK9aX$yX+H*gkq1_A`;7G2< zpl%_#8iOl5yuUJwv75oK2t)P;$>cvn@MYTxR$_8EglL?5$ z4isT0f`!=q>O($D;~8kfDf$q57YbWAowR7(X(D&Ca|s)B=yE_o$w6Sa>@*?KE?^ed zlIRdHOKVAVfroWf!r&mhs+I($r>IK;;iDNFJoT}E3EePIP+Aa}cV7)j9HF|lgJd9W zJb^1ru(pG6D!lAT;ZZ0{)gmN=gO(D?;AL$GiJ+*Zpv3WfncJ21W)j4+4uY6g9M3%n zI$J};R7Vgr&IGjup?8!ClEZ}zh)^Wxk!U?%w{;@HUQ?X-C;f^s&2lu&U(@A;v(CaM zmTq1Rcd-@N(anbs+x(0hDQ+kv9i~vak92nV`a&MhFIAs%v&t&~(#^zs z!U@4pFFfVZ-=%2MU5)pQd6FXdGwJvaL^^ahsL8`Ho(J8};O+7au+G=kr#y~yxCB+q zL&xvM-r?8LWdWoKje0U~btTyf&ajoJtiq|Xtm*Qr{?Wx&46QboTo``wjBEe#C@gp5lp$-4y#M_Ej9HI7E@J z7L+qik$o!piHfrn=P2^+l<}7;N_~RAQhC0vGM+Qc#M>2rpeXf;@U6;AJ%aze^3N*% zMe#+&e<;=|{!{V)6kRtsp42Pk$$A@LD-AzdkuS_FS64;8F_S-2k+00;OBMOfOrG!X zM2?xCbbrjkiSvz#kmPrE4xo=YxlduA#;!A|VWYt7WH8SGdXML1Y`>u1Kc-2Gn%sx>x=8in0=G|xl5Qn$?`ZPYzx!mD z99`nH?^hDroAy4w?elNHq-n|Rdt+{sz43p-YQpY8E<^L$csESl?MDBe(SO&#{w*t_ zTVSK)8mE0o;f#1TkH2~)uaQ)R@3Nh_%kcLT1g1I|9Qg;+#-lBf9y@Zl>I8}-8UcfH zN7hb7q6Oq4`t=`(h@3f<|9-STB0TD!BE^d&ByAYLyOs1g1^72hWn}fuvFw_>Q<*1G zNfO@iPGH$^WHGtw#yMpK4H8FC=#%6oj{Cz9810TASTk7%h<=1)`q#R=r_7$7V?n#Y zqS1Fi(z$UyFu5b&06hUdejM3RyffKb#eal9cQj)^gl|&4V7B9q*$J`$;?t)vaT(d0 z$j$>1un&T5GINgOj(rAUuQGBVBgauNO@F0xByrE)iT@kHg8r;EP1he_<&80Lf}1tP zOe>2e&nsMT!;v=*4?2(dd_eah?hNQW;wu5&hba9z(i2(X$jdG^bnJ(rTOxFU$6}kB zS`sAzGer!Nj1QO@wIrqmOl9p#5Ld#(zzN|-317Cfmc&nk@SOl2HAQ=skf70ookE^N z2ojD46}mQ{pvWTZgpWAubXwe}SLX@S=PXFn%$-|V zoq)O~F?IH&sZ*v*oid>?|CB_Jg6=2J>oEc0C(W5VXX;5)Cr+94KE+=&_=zdJM9__lF)VU3@twWxRbmk`5oYq%S%l2D)PO=&<(4+ z&CC0G&pY|vP0RZR#&MvP>Q#sZKFJk4=;KFD8#8ag#Q9UJ?bA5)_nY=r&FxQ(snrWA!_`Xv(Mr(I!I;jxUOjQ;_gSAMmoZdXCUu{( zuq?R`E?g@XCKW;zleS5n*|^lnCiTS_*vUkPWa}vlt!|1vT)(WmRZUjM*Q8w@TN}N? z|EBjXSlQ{9)h9A5Ju9zYMt}K7y5c_g`^;?%H~6-bb|YVT73P=f+fKaZ#`#Kg1?p?G zglumfjO<5&V;Xus*l<+EU=}*QCsLPaoFO?9+wyio-U>ugUJTyI<9oHq1JbzP*}e@P=m8FuWeLlUIZwp^2*iYah3wrQ;MK9goX!bKGjsCJ#tw77CRhq0Yq31#io{ zsdchmG7x9vtpRQFP{cPOkB>vfnYfh*u;p#BusfTi#a4 z<8|WsHiI|i+YFj{_`pX;UE-qP5k`2%(f?S{q`M=1|GLimH61`)E-GWNVSqd?-F@(O z`LFP0BMQZ}m@ zIh)W*TdcI#YW=$XDgtPNw{<*Aw7bN9=1t-DmQlFt5hRn}P=~ z8BNM7r_5Y9d+wA5Ph7~i1)eXr-u3Mw-@n|C21CJfSpvOL~ zF}l%_nr@upd5SX>XDjlJf$}(CL0qr6N%0QFdlY}E_^=||IP+~+{G;NFimWTf?G zP32J>DHmHO%g5&mBCj`*_ZCs!j(~Z}cTy}+EL7~PSft4QgZYOkPEf2+oUVAGVvXWr z#Y+`eD_*U5ts)gLl+U+h;_Zq*Q2eRl&lP{ADAy0^cPKB{4gB-U?^JwMakt`!ivLoK zvL2DotYK@eywSb3RX(9eJrmOxDvGWf{9xtfI)Wds{1n9*iku5%{>6%`6xS-=q$pZF zq@(7F=^s&~?uxuD2?PF9`S%q6Ptiq3%XD!?+U6lIN<-jL%2WBpaPEU6o~(F^Vv*ti z#j_MgDvH_>`6ehoUGYLis`Ds!q2hAI%M`zD6eRcw6)z za1C_gZfCAiY+BN~0i8tJTk*&%C2omdQd%GH>wkFJJO1wW10LD?h+A6k zH{gHumYWqp>Rmh1c0ZZcO6*DX{vdK1)4Hd&9Zof+DdiH{ybvXJDll_dGFTs#wVi!3$s(IH@(90e=S85v|5m)_KhGe*fJVW#U2X~`r_k8_5!?1smn ztbMoO%0xi3h979lPTDe$;0ddFaz`%eG|4co2Tae(x}S z3#3iJL!(Y867mAV0C>+?w!D@E>jyI<1ePl5ETEp9Bs)2r0HFdNwd~fe0}-6U1W=(% zfU;*D$QQxKoKe^Lqp$NRof!;o&d<(+XmPwPgF=nb5LvoA9!v!0Cy0{*dYOqg_nZ-L zhZlmutN>v!e8ic*n8+i5W(yG47XP@9;e7e$A5YYFHopq3HxfK)HBv*rkKX&Mqq0xF zXo)=%ociS1)ibNhr%#@oKZDh_&oW*-!IW3mOu+z(1gKFylFXi1Gb2cjW+rv*J%wew zS*|xfL8J6uM&j0P-Ta96mw3MKdUr0$*Ok4kYx;RhhIaHWNU4O zeFL4m7)`@)Gj)3Tf&*#ksfrZ^x%HIf1P0Y~fvBx?|Fp*Kx#0C+N_(l#^71jmhZPSS z5ES`{_I~P=1fRSeoO)yB34deQOw&ksbygkTBc`S>O$A=1AUMWt959Y=h za!N|Ng%H4ZIpa*a3Iy24U7Ujj2S~@`GTa=u8nnp+(y2$G5+u}_xVhkMdASf|>IILl zp}aMqO&*HK)pvB#bS7>kXj@(Sikx+yrxdCZ`WarE~qYOwPsq%*P^#^ci62XB|J$U0v> z<(u+70UDRS3Lq|y&Z#lF`(mVPjPBlV?lekwKLG8NFVx2IT=(bf@FTkWRt>*x_jzLi0n5Ghwgqb<=|!;saU2sQE`UiY(*ZQ>6a^B zskmNolj0qUcPl=ixJ~hC#hr?;D%L5!tN4+kth2>&#ReEq*3|+}M8&c^vR)Q=oAP%N zp^Mz2cn=XbA8mj#{iDi1q5RXz|4I3mlz&T6bhOAPx>;Zb`U}eAx9KUbjq=onkngN~ zZ^aTtqkE;whUL3J!$tQBc~#0U(D;iKQ4I}ro4D15XZxa@gkqlJiHhA6dnr<##Pt0Y z2Pw+?9>PnNKTnZrF{YoU$aYAcV+L`NBHuO1uT;E3@hU}W7l^+}d1)Wuf2h2)6Y%#c zFYN{VL&|Sgd`9uFihomlMRAuRRb4F4|0$-<6=d_eB0fiv<1G13iqv3{H**2y%1>6D zr8q}%k)q7?ARi6&Ge5Ol#Py0arcZv8;!TR*SNxG8Rc=hTRdKuGGm1MEUsmMv1k=Bx zXyy#0eIi`iC9u7=Ct3IlzMJyY)-iv7MJnycpQk9QT=3JBpQC8z2&6ws3!Vp;X++Jzu(|?F5CXMH&2>XaL-lo((QZd zrY*s$bgyek%QyWcZr_$~dP8Y5pkrOytTAuKhW4(ze94$Mqvz(;`R6XI>oBW#oxdcn zZu6`KpcmEUEjgj?wj~T-1Y89C>kemkG`sm8&ug-M%NytahDNBs1Ns2zp6a0L?u#%e>#tHN8uj zu6SyY>1;wgDpOSPwBI4hEH39qD!jzGL9*9Hc3f7I$Nm43Og`IIv`FG+! z&1Ik9jzSJJYyQEx@zF@^j=l$UANVHJmbj&tGHP^_ZxhBa&Mi$BHTF14x&=Pt1cshX zmO}=t4LI(2a-6))7{$nQC}lobHfpz=vE2HX!FwiPeMDp|Wnzh?aY)dg_44uk8g8_d z$muwrhDu~=rm5BD*E4yi(IFKo>k>g3g`G>{L{=BWiCY6Y4hUT?DCmg^9pGU*u|}*G zoDncnYDo+Ym>Kfn%5ecxSvv*99C&0Wu;O3~a%nAzt?&rPf9QCKm~$h$0GWGZlZZI$ zMiOPban_9>uG8@U2iyv8@_-Cos;o_jfvn*N%F`C{db|-to>auCt}rKuyn}g?JU7ro zh&(;eXUzdF3uqQk98ZE{uCB}`8C2w0LOXb@=q6kM4;vA#RMreI%mIxt$trm0S_whj zRlBw3GC^mKU~wDp&-05r?+)+$?y%0s)RN3BIL?ndiJ;@V-WFMg;E;TNEo$Zin#oCAc^U4&By}a%3^u*KbL7u<;Q6 z$vzrh)Ll};i?=yT!z(w0YIvWfp$6B>$oFRCd%1~=I(HhUOUpKD`i?I6^ zckXx+KS|0J*gdCtqY@`#*>-;62(R-{?|aJ=UUgq|3&Gb(528&C3fo{!wy1PP*%v5x zL#?1J&{fNgqBIO+s4qO!T5O{`<`&E&3#|{Us+J3&ozO@_QlHDq@*ldsI$?D)>~aQX z#aBgEyOH9@9?f#f0;aeRB0lrA)HPEV*W}xc`>SpW;tN|x-4&M$-6qERz!d_vDov0+ z64(!(>5O{^1mD4oGvpZvXkr3^McKi-TWio!c*^5r5C?RV2c#@cxRr!D6ITJ=(2V*J z{rTizJR}>&O#p2lcO!IbE0B)Ikeu`UE}%gfCP-l-^$Pkct+ zO3)?`NaqsB!zqW(#4SUJEw7U$j}I|M-UiSn4~1L>d8@1dL#{)dEw2yc@jO|+EO;aD zCeX}N08htneT++~KgRR@-%d9j!sjuAI>yo8r>McspOCK5FhCxc?jCr%d_^c9>xJcO z0dLCp7-(C^nu*G7jE;36()|&6jbqv9h}P*j&!aMm5J=s#(e1JvEE|p+y0!>BF606^ z78{c0I1KnKbgZnK`@^G|+6)3d58DttKI_aPeswCfiG5mu%hTv5k5|N(WQZ(p*;Hn%2}w$ zdzt(-iq|X3>omeQEB}2(UMHr1goyj}*NVR-qJ8erc+ru8->LkYiar_>)5*G7$dUEW z;E&Vr4n%|(C@;1lz@Mr70FCGNZ^{{?JU1|Di!V+jIg|zW4_v5=JQ^dCZ7XA@+RB*qm9&*{d>dHG z@U~}o-!0nJzep@)jKo^x2lus>@fh@&AMv_Nb@(pt5%*SbTpXY3u>q+j% zUPciQ;>ITu;{MYV;rrtWaeo^EqprWujiY$6h2WeR+y3$x8lkf+R*e5kV$_^3jb&i) zzc|LHo+VBip9K76?la)T+=trRkPq0Xy^Xlf8Hy(E$w;I2Hr@kC=l%mR>3bp89oZEm zhnIBf?E{+|FOcPs;ErZ2#bk&MbxZ;z`-aRnnYfJX<797SVqqycLu_s^TT>*FK2eVV-vIBvd|(`3Jkb!Ew~rD;Vu&7xmbt!6gVv^KqBrHkTzyI&^P;bwhvrHc`6 zeLoCx&B6o7QscfD7BaCi(I$4;nS30>e1v)vDthDS|N>?R~=G=XJzopa17&_wO%+GMuThz?yFP`ctb zIQ8{qCLd0#jJY^eA_*Zl+rw`WgoiX1L`*^Vx6XDm(%l7r5Q`ub^;NY9!UnYm9{Om4 z*7hinp<|=6YleJ3cw^C{1oR|}p9Xr4#V-N9!QyWO%^EfN4_5o~Y>2eMog{>mF`)M4 zuS3uB^-@2ZCzUUYMUd+jp6cDPJm32(OoH5;Y7(Tlba?sj;BR1Q=LaIYZ($h^ZsX0Rl+l30NG{ z)hkW#mF^0(^{H#|fXnw~>NS~$p2y>}fRPPS>|A0%4xNeP^Mft#Cdk{4NXlbbj6B>O z4dvm4b|TC;BX0@<49&Pq2pC{a-ioULZ6CJ^O1>(j<8c{oj#~}dmNzQRaS{kK&csoN zXUp4(O36kTJdd22wMJRqGa$YVO=Ox#KY*z)#R^6-)q%G(IqIe49Zt58DIXQONX-l=@@*kKyffh3H83r>CcG(v$(Db0^Z3kx<9u z(%lDdmoJX;nfl{9lqug6pi!JEfVht!?-auT&9SJvwTkVWj7t0Se$p|$)hwNQWE_P+ zRChQ(z;du`w!Fb8)ENjf&K%e92JP_ALQijwL;Nb+G2vK4J$-lUgjnygP9iz(9@wsl z837uM#{1eh;VW9ZoS<(x9P6cvA&+wbgB3?Aj#Cs}KjLR7KUY2h6`+k>^GJWyM{Jdlcn;4)Gr;A3?)pdeQj<#YP73I1MjUJdFq)sp$HF z{mJ8I;CJ?z|7_(aC_hd43zc7>{3^vOG+f@#AZMfUw`lwp#h+>TgUUau{8P$5O+Q!KM-)@%9H{MM{ELdODZZij zw&MGWR8=#5RFUdA^4#uEJXW#2qO7w=xcTl^Zw)u?rJwR!p`y_%g+B zDqgL4gW`>fKT!OCid0y#oWD_|?vcDKNCi@7Nxr#a>KsCQ4ezL!uW05Lj1863HJnOM z${VF<)NXDc+{|eZ?(`+^59!)VdO>dnW!# z@p;A96yH#+SNupZj=_!jG8JKOJdIDFSOgjF(lox+X6bY+mdeCZOP~bnY7y? zvm$D@g_$#LyDd%CZp%%GaI)^l-`_zsV@K@bbBfyDikO`X+!|dwPM%I=EEV;o&6+&T5muQd#u)LL0nH_sS-z- zl)0>&z($<22PtwM#-F>MC3px_%U38(Sf|akqj$U2Zsu-rQQ+f%^>> z<{La~Bs|pY(1Gm1e7xDAR4Xy*ww0KShE`%SZ7VTNb!om>iODinVwxE%G1=j~P)5g0 zT5&0g!AcA#o|-qDc%m&B%V2!V=rIvRyb>NWGr2@wLrzc;Z_#i-=y>~Lnuw4P@@xXz z)TcE+!y|5jhjaoDeqi%6EGm}Ln-T}}QIx<3Etsew1QOU~g{}=Kotg?Hj3e-24S5I@ z5qy8qQ~;7AEOZG_#!5{fqRgaBwNk_AFVsp6A3lRhm;fqt2~hTY5BVZ^V>V_4Xl5|H zIX^oOqQ&ufo9QvV6a)ln0C{}=?5xzR#j&oIqmD91Z3`kI3||!j$8$Gs8Hg3|E8&^l zc6K^>K>b=7v@wruGQo714B9*yY1_F zaNRo;`(kw@oCnx?cr@Xv$;F#1M8)4xOJ&|>|jO~2MW~egJ z|Jw6Yovi+t-EoQ?o=E@nr*uN9e?~DMs6X>PAPsEtXdiiG9?D!Md4vbk5k3x&hkkL? zv)Rt1la~%e@Ntul={5@${Fyy1p@5j7V-ojlfZCu+-lG! z4@hSqPA)-0or#+ZzJWYE$z~&r@(wl+H5KwYsVst#w-U51Zvf=+8c`nAuBLn&L7O}v zovR>^x;x_xxd8#Tyc)Ub=ArIZ{sF~picc% z#ZHR(iYF@;E1LPIbCfspO*bnq`hUoOgFO1)J&NxTafAO$)5Xyzlb87cq(4e|*;@d< zgYsfa9qCRbkMMztvey9NWy%}-J(HE6O+@^~ir-Ycj)-zmEl9jw!+)%JpW*`=PaPW5 z{f>x^{8=K(v6Be-|4{xdBGN_CIWeA&Jo`5ypQnf%6NtHrZ58trJ1O>2WM9ej{S^l( zj!@*d$atCW1ePm5O>veY$1$c`q{!E8@+%d;rFf0v^@=wr-mG|=;ysG&w<+gP^J0I} zbk8gPT~XRC^1rA2hl;85Vwu{Gr2QiOQOX~qc!FYQMXG68uD*%`6bCEHHzN=~MtLf4 znSQz=wYTKIqiE*8WWE&P-`8+sC+J?~f1&u0;$w>26`xW3tK#1jUsE*q4b{aw{=XGD zSwOy}VyYdXZW`WGkqTy}m-_@L_Xlv2hMV~@V?T&mW~MjuVpKMh=iUwC&5E}v{z#EC z5{x(Z$z#g%+3jHSRB^q|=DtY1AEdv5Tnw}O*ePOH&+UYbu~XEmch4RPafjX;bU&UE z;2P`=ayw6jouX4_75wa~_+?ur?axxtEVWdWZd)qqP!~J5N-Pz{4u_?pbXqD3>=YHH zUtZ_HPSJ`6c8cDu+q&efy6g|Vzi_XQx252LpVYmYeotLdIzyZ6Sox-t&d{VKqeoxe zQa3%_y_Vl9aBrwnyGA*@eo_s-`vK79gM17j2?jeY zfl)WI&}C;5V@q{nFGBcoHag5*U5NinVw@RX8e@NaaqJm{VD9QeN?YdM2`+6k>A)^h z+VEP|(LxJi47MQnjnj;Q%l04GoMOplw0XG@pBLU$iBfKNwrU^_yu@3>A zNtD46^ESj^XgKkyfX*du*Kp#q0WHXO#W^29=-Pn7>IPs z#s^Gg?KBWo@W@W!@GmB#NNfwjS%QBAB>qDe#EvE~MKF_-Ogoxc_Jk22LKoyLwR4u% zCUcgWocIiJWta&B&(GMNB3%eilSsr-0X>4aPQxiux&pOv1vYf4vNj=x)|(ELryb(; zcq52KlD@ivI9TX)!-%Y0*s+>oDj70|u(DatpwFrTt_bK60C9X4%!IdWSFw1QCL<(- zEF)CFi|r~(;}e|Pt|B=f9+NqQ;3C3y726Ff;DENPiqv)$F9pw@iCO!k0pd2`|0Z~Z z@nuFF!#2VM7w}KQQ-&Q6wgE2-o1C8L4I^KZ4vQr02>V#m!f27S zriJ$0chZ8Hl{F{LoO1^25e-!?g-2^znPN?AX1;e+!kd}E|AmLNsWns0Y2n)n&z;C` zE4(>oytm8A2mce{e_yuFyB>R+s{117&aQo7<-m1AWqpI$rofI?dASsD=A80s>=c<6 ztZL<+5n9A*V1erp6G?&jittbkC#0%IF2IhKIrbhDHQ5y$_2V1v3J=s^cIj(s!Yizd zgH0tJ#@VB!F}Co?IuG0gt{-Sy zULNF8=g4^ymc_^`weo;;`r?GR+|oEhPCfYaEYDcOSf6zP>15Ho{mwyu*d%djd3yQw0!rC*<+P+c@%p>=U7JDTWkl!R*JZdoG+6t zGQQfdd~E;3UnxGS_#4ITilSmbI_jgC{&mH@in8wn;T=$^j6aDOb)4>sG9Lte$C(<> zmDRL0HbQwWbtW%1$dF(3>EIV?_{ExTweq58NBl+&7yUZ;JCy&4rW5@-I76{gk>dr^FH&5gxJvOVMVT)|x*L?gQSlDNA1X@wK)QRC zKh!*pvAES(JSX@wlpm-lhPMztN_m<01b@Er6BR2J zMRAV!Mas)ODEL*%uT?bjpx;y8>~k{nJ3rHK*-L`_)GxEVG9L=0f|>k_itj7#Rm{Pl z$9S`^DRnGhO&bPA?F;5*#>+0~7wYQ%o3`&l^XQrM?Z(;L{RtM7kJ zylF|SWPM5Dc77}4)DkD*9Czzm*}i)!XP`E`mfieOd~144ea^6Ld*kktdox|~Z|;cg zPHT;?ReRCxu=(LCTM%)i}IPJU0cdEBG`|VLhyNaEk?%ugPvVHCzr)Yf9kdg;p ztM4znrf`g%m>VkQ^_24X?ma-a1-OS$IjIgaLBC~MH+~kPFcTy*iIKGV;KVGPcjhQY z_)#`BkKbeQiYG}(S_RX5kALUXFeDxwOi}SP_TD-_gbAm6n5Q>l{9^|)@l7NXXOo1- zR;ZcyM>_eIiW`?(A@2W30{t@yasO`QkvXI|gvC~ab7Gr78e4Il5O7J1y9SrW-p2pM zvDFB{9MWrGFo*OExHKL;a+SM|bSA^Em2X(9t+)z?yzII;EH3-C^uVle|*?v`dtQI7j7un}W$t`(2biUmf(FT*5KayBPrUr=Vlc_XvGNDb0)8p-=0Lm3|9D&a-m@lfTCDB2`%Lu0i;T1A3@Yu{l2qcUJ6}lWymR5~L^K(-86y zC?c3RAQea`1r<6T+};U8o_B)TEn~9TX-sCGIfYq!ia20U1hzU6+6A$Mpz83k=^`)# z;Pso-B!|IcmWB}2BxY&MfvrtbJrG|cNhjc6Tr#N41Wf`_2`^_b<~lYAalDkc)!@P) zsSpX$KUR=&^KcV>JlkwgiU+?Tb0$|Vm@?J*ihT>(jL@HCY9pM?;9i;Re6K3uW%u=( zPV=gW6z9O*b3ttPAvq}7@u|nODMd-bb=iG>--t#uv$K+iG^S*%0XtDlI_(ri$i~5 zq;h6exd@&shS0JTJH+XN-R!)Dln?{NS4!&I@d2?9>Ub-k$DKcUh>=snz~XB z#qxv?EQGh6NyqChGyLH5WqFj#+kSZ1lY&T$#KH{ zGYmJ!rC!P80qG1zp%Nt2nYh$>h#EXjW+M&H<6!d;Ga!%Yj5G39BET-+DoY+z>S6gd zf;M?5V=?3{umTLZ0dcmx4Uos{#PS_%9^y^RlW;Adag;}&IuG$rJj^#{9)jPX9$4`6wpfJbqv0OIb1yi*JVH0Qg|JOtAHc|Ylx-fAAsW?YO>2;?&> znxd4C*N0`Zs=;{&2RH*^#+l<9-k=@+ShNN)*Q^j#r$jI7@MnBF~fgu2d9#H26)*iyj*M zJ<9)5@nJ=_f9Bt=_&RH>5Rrud}d9~J+s zNJSmfy`e}=9eLBGOpTT)sd@B7H!N8HkSU(h`x@>V?Z_KvjOPo+V( z9f@x5{Xyh3rf^UFU`Lk{r#<&IY|VgXyXd%*z!F$}QD6zIs$^ct%g|}R#X6EA`0m?4 zcRaYJ@Vwb<2c5R;>vH4NdwG0z^g8#$Kh)cQKzeL+xS3%bNWC-V*7Bo!5aIC=&?}zJ zq<-2pjQ$J%&RNcoz?_&zO|W;KbfEDx>e-W;Zq6=wmoez*-puzclE;oB$sGWGViHMK zqkjTN25&IQ4r}m_?AxeTpVK$4*mD>V2u5*83;1=zj%0K|LYP8zt;UVg4F)k4v=4r{V$qYb4ze$!AfeP z`xlh2d2>b#qOB|Toy~7Sm^=7>kQ}m_a~yJqFqR`vVE^kZ4kGL*#E#c!b`cyN0y|!% zMIe6)-*PRpj-jNd!RBy;VXvKFaQUq`OsfqDDj~t_+?myi-3W=+Cgo9&BSc%`uMyF5 z6aL)Al)4Pm(JW-ZI&G$q<~dnrz1XlnnOU#TV(CU+7 zR{#w?A&_t&t$rY(j4(OKLomWh<#XME1U{;Sjwfwv?8$e6H(Gt3C{N1p6i6|490%dtE36>7w zgg)>(Q9zPq#zi9xfX78!UQ1$d5N=Mxm8*rYWM5*=R01_z&t$PV6P#6*i9Z)a1w2}j z31Vjx5ym$`QfY?a*_OeNgJ*Wzv2u-*hv%=AO)m3DbU1BtJ;8Z~1V1#M-SPGU~_Q~b;eW+eJ&d|~qusK+Do5qgp2sT_1i z_&7XXBE)fMx1C8>fI!kQjbyq?r3q%>S3&bM(w7h3^_oRX3b-&l0k@8`G`NM|265Bl$& zdR&H^<5s80yE)Bq5(qQS95;17!aq7$F9(~CcnI?Bd&|gMi38Z>%Yi&zBi0MmaHf14 zL7O}vo!23cIv?WqL16n~#`?OlO+LgS3=KpE@6LQ)c7lBXUsqzQ}JJ z&x7thc)NVVtolQf2+#Kk&?rt7K-?(EJH;?SbH2?%Tg7&+K)OHgCmqvU&BGZ6-F0K; zBQ~K>e9$(|9M|v$?eHV>5eK%b#WCgJ^AU%ztEEr6!AL4!Tf=bRI78t%A5j539P<%; z7or|~pyDt^>Y*6U_eJ7lMK)CO3lw=@lfPV%_a*sT6z@>HTk!$KZHiAT?o@nLu}<+_ z#g7!f>h`qy~4R-}fM@n+w}gUUamNR=t$pHuuF#g`Oc zSA0`Z=Gl<`L*-pPx!w$wjCjugOSZQYR8HLJnUHA08l$tGGrdej@7rAJhWrQ zQPt%--J z;ni2{9U$-UuAl=s)fL1dc-oI54hZNOM0s98g^dR-&%DmMVZ{8eWM($Z>EGTjF@xR}?WV+yr?YAyX zKALMXNe^YZiC5CN86eobQO+{>mGFG7rz|@i*arM2bRUtgl?f;FB=AZ0IUK-*)9*1G zk(Kb~C-6V3ONSxdPwIYBm%=Uu1>S;uuN^l%4D>R&>ETVW%yeB@Ko9j=j>jH|OND($ zqOOF|ropt~bQcUZHNlpML#UU7o%-PfL4*Agjj-xOm9N%E@Ok=!ZLc^imYc$&Hkive zVyx+N`A&UU`MTBN&>JRZOq}n8x%Rcrbnp!kwne6JwxRmVGsD35XM27jkDa4B_L;?& z4W>&16HM}7+y{}L?>9TlO?qT*L9dTI^@8pQABQ)3)? z$7c^)2fVgLQb)}+^gLb(ypau3zG?it6=2AIh_mIbgS;(>Jk;F6)=1-QF8vuN{$r#y z&K$P_0rqi=avUdtv^*}u&3UBGEv!WaB@l0%k(WBRPys>NNJM!Dn_IXO@_4%#XXNqu z#4cYI1dT!%CCJ#twC*<8^1sIagI<~y65X9?5c?X+YSb;>lQtFQ~Q|A_D z;UwoF+&HG8zhBXWKaX_w`SLvI?t{0>w+#g|^>?tjg&cHJjhR~*j&zNgTgYynoLex* zWjR8kI(uE9BVA;Jh7H#^Guy|9xNfX0?Rtu0)If8OUXylq|GJMAvhRuDUi+bj%bo_L|8Me$ zH@233OCIH;V>tT(BC-myO_9%4Y^#{3*h#TKk>eH9_f;%X9IQA@ae`un;&jCe6>Ah1 zD_*L&TJdVdYZbqzSgUxu;tv#ms`zt7xxOgp!^%?!#&Z8r@p;9ain|o+6sdn?`VSPT zG$Y?kv9)3w#XQAMiro}@DpJeF{DTz7D4wlYt~gooLdCg?ixfG}PdU`n5v5%Kzo&ey z;vI_8J`n#?RRTx{DQ;E6Us#!exCu@Ov6wtH>Ta z5)b-V=BFc?`vprK+*rZegJ=36y)(bV~Bm8g4R;mJLF zoYM1@-ibtk?8ylJyB8Gn>eVZeIJsx{9*y0rQ4tI?;haD&MuC%F-!t-C@o#Opvc$hO zdR-Og2HYDqZry5GI-O#j{M@gGj8&zz9?R(9ru`b6gHz0v6t>T`#! z*z34I%NV(9U7rc{Ihm1fkKA?hDT8-iIymy(ReSw`#k(#qZm~Na8M$l2sgd;~ciqvw z|L!K<&|RyCdf;w5jk(ukKzq6Ah1Vm~2kg3Zz!fd;&2=`o>&uH&NJ&P?FL%T?M!)+4%eULjZo9|J%-%k#-am`S<8dgLM`(fk{gL5JBxfL-aIRn!kMMnP>0>~+ zqnY)6ImRbe^y?l5`A|fxnUet9mjI4 zQztM5ROUs*cYZ9*FT>*!FRvxRawDAZo{(b*T7v^XieqI* zgz|#`{4>kvkpmXVL;q6a6vGBxG3Qug`-CHug&|A{C zgSRBVefJZ)d-LL z^-Y1Vy@j9fqYSt#hw}r|;YX!qa-nfL=js`A=hq}ykdLWib_VtDe`=!Bpb=veWpn3N zRwt&-ou7aPJ27zfq^VP;Or4S#HGl5psnykU=T~=56y~3j-!svpp!>-MC-*od(Fxy4 zo;tC5YUjjx$kJ`9W;v;_{FIX>&7U}D@{Gj%sS9UT&zw6a(W6IUk3N0Q=RJ`LZ|jk} zGEg1+oPJq(tD3BiuSvT+wl;c&|4nR7z1r=UH7Zh_o|OmdIiHU{xn}C(n*4_M#aCRL zd<^QA&pzf+qfqPIKrkLS&T*Q~=(keSQ3f6LU3@e-R61VY)Z^M?iy479I2qX>ovvVJ zS^bdYfrL5}HwnC<8PyplbfKvXEA9f& z_HnmCH@Fq)cw8RO9Cx0T2c)wBg-Vc6XO1-+ye)5SPVinwd3+`?@>YR1c|bb%Kpsvx zbS7>ELTq^(EqT1>jJ)eXn>-+$MwzhmNF6irXd-kEye8C9vY%pjPsLLeixo>0 z`6|hD;}xeW&Qe^YxJ>a%#r2At6z@>HNAZ`64=X;QxLr|nf;jGr%73WnqH?GMiYhiC zqVY8&@;sGqr@ZL?5HGr5#P`;CS~6h1GR1Q=z3BQ7PG{?yq+W4cwsnT*D$2VB_!E@x ztk_-gWJRe@q#LUIXvMLL>~AS|lA_Vc&Q*S~;!?%cidQJEQ{12^x^~FBS@|uBQvV2- z`UgI!;g2i+M)41d&noUzd|B~r#rGBer6~4#Fnq6K1f3@Nm||1K=8B@hLVP>rJ1bIw#e9W|+-pX@SaG1@FvU@dsk&I{ z5751t_KM3Ra@Zq^d@U#Ys|fmZ)1Iw|K(SPFNZn^)kHUnwL))p@vmf2(9>{$6)uCwQX z>XMq0J+EHCy5NaIpST16Zh!m*_CFYybkHYW!L)At2M81mVrYkkcEX`r{0<}9@Xy$x zp%&YtxuMVw&1y#9$3J6-hMIG)f`7&i4R!KKEhA@wyrU4Wc4)YIUhUBEAx!PiK%%ij zlTWh48vH|**%3)lW>LS#eYsP8|8&O1eeNrX_6DtXWTLZ3U*-OUz(%KbWMV#tmzdAF zvb5n8xYc)gvwPn~NPKQpcZS@L0MI=`dgA2Cq?xb@2eo+QVgE{GNMD4HeMKJenK^w? zuRvu zS zg^zW-y6)thbHVbi&l!O~-rhM(MWU5S)taYDci0uFVhUZ%mM1c3?wmSQnnM?jYm$8@{lHp@DIj<#7t9W8dBhQ`>_@zBsvW!s{m%C@C# z>jl+hEWNZcmR?#1mR_W$aP4p}2Fs^;g+a5c2^|{|G>Qbd%V;87&O zmP8*3A4TXZ;Z@6ONlB2~!^a$GRm-mPd1xNS z@J5WC2hrk~m!}Xxna!zyUdmIV9P6vHg@`F^yjVsHZe z^wjC)3!J2$72mh$1$z|wQBARDVjC_ww6ZlYYtgei%vv;foN!bD+bET5sBsiS+(#6! z=Bv1$l>&DE)<+sz#+g((ck+c}W-h_^3%K~Vyj-o!BsH?-<)ICnFTZj&6CIMRn`Pf+ z9Q&-|tem6;5%TP+Kl8P{sk+#&zSWQ~lP=aCi_8c$0GCxC@IX1v3iwIEAVxNfD*~;m z0R}tq=7DW;j){0hlMyct90hO7dkL~SSOJEdl#(uv0)1p6t+)$7+sFMA9s&}O$>Z{P zJP+bLcq_Z(hWa8_e9FWQ(!1>6=;(Oq>~4EOlO>lTY&&uUK~m% zBaio(Dc|*=O&*X=A>_@q0t|UA;%s@jkjL|5`Lf`RyjwssPXRpLt$5$P0rg@WUDMi+ZD9^jut zUgJ!eh}P*jTN_+Q zpsO56IY1tt$Tt@v`vc-+#VW-GiYpZ_SKOe;`-S=V%1pdl@d3qcicc%&FaXcp;Y=^< z9l`s!Dagw@NAN9`&n1FCUilM=IBqw^Q#HK5qUh8hXSBwTRm5pZKHmS#&pwTa+e$E@ zn5TH6VmC#(o=DHvFXp3Kia1Ddlwz6Ud5YzVGZZTosSaWO<%(+*zo{tK8}S>Jm+KAw zhsys_(dd4EtNia3|El;mMe0;|yuFGZ>mPiYqUheiw^W`=7shkUBjzg_+t}2vFuX+3 z=y=B}KS8lVQQ8mE%ex}5M#C2?E?1Owe~7VlYmr{ZghZz#(Bo|bG6s3u8o+Dm^;hhg?Wy4Kz_K5-~rYp?DnW3?&Wp>?e@(C*Rw_j;4__WHftGv9))^-9sT z#Mv=xMSly|ikPkRYb zs$li}w3}Jgybt}Bo$()G8U3UCk)#sTKlVJ5)baX>*&vbSXfU1|XJ_CAU$^vpzdPgN z{tN_0H$i6fGWUB3it^Sr8dlM^1{&6wzY7sDKZ2xbtC1;E@4EL>#z2GwTGe_92(+pJ z?WDz-be$h0tqPN_^O?8F2MCBrU72DdK^BxEB^ih z?=)jwG6ma*JNZ_oIvYW6!Z$bJEhdBGAv8VHwqyD!Pn-1lAex(SNzXDMJud*$9?$eM zTA_t!-+&-ay=1dbDI>8`iRLC{3w9^d5rqzr5}3OKCCrrEjFH?+Ol}g*O)ANK6+-Ct zuU@tdiFkFApmn+jS1+r2S5(O92T&MiSQ=vVbN07A({WiFDvVRV z?P)8Fsh){bI3DibOXPWq?KM@0%y$9kehF+msvTwBV;$+z zS`zs|IN?+wM-htPvCemSEeT3)tOhwq%jdBF&)%27S5;l>pL5Siax)kspnxJ?MnT8` zL_kF(fm~(?LlKb&gb*fy1QG^Qs>mc-tqj(=LLF)4S&G>Dl#0)hI`n~m>$8Iut1T@l zc~B>iw*J3wowe`XxkQPAsMY@$C7pM7G1wTGO%^+c{zOiyjrEylRA z4bdQ#5G+OBdWaIb=djALtY7V4j!1$0a18h3OPYKp(~=r z1G7Hxy#!X3?7ZWSzz|#0H26iT1o~&EhR~BlI)ltZumtWu!Qzh66xnrxs(B$JAzrd) zY?)1(MTawqJMc-EhOTFmCTF#Yv~Ak1)p{n$zUz!8(076bQY5f7LDk>V6e$>V&=@-@ zq0Ll-g0aPjC&d+&yxR=iJ^x zbGu%74#@7|AiHn&a=hD;a=geOOqTKEg@e47gNAp+XGAk1UNk2Z!Xz2O9QTwNmMi90 zbqRQGAvczo*nrQo=GeB~#` zJ_CJ;gS%X-uzz{KV~5~eabm_BlP@yCoSn!yuze;hf$%L{;hJFbEt zb1`m#W8CI&$fgW!e+^&hR)P^r66|)PK^shGSb6^e*{-)OIMvNsFRpN7^^)r{z9BkG zaNixFpuyykE3y5((iE4UNaJ#(A+lfScNwB71JT)__wke&Odc=EY=3WC{>TRzf8V#t zKy)_4-{r=MmA3}6?eAUqV|&=XOhn`Fhmcu350RlG3Vk=B|CqlC(YD)~UO&hEUup-C z&;gA%zL~&!86HNo+xHJ^d3m{J+V?DEta`2%31i`}AsqJ_*u82B0ois2qP2KVhf~l# zB%*q`9%a2;k8GQ@`8s3Ks5VG5!T2+}K|B3;aNKN5Jeb}KQclEpW876qe*`sh&BQ}P z#v5~cW1sL`kjQcK^5ux(#yx^#+@~39d=7k*hec7r-imz{ixn?cm4M*b^Ihc5g!^tV(Oei8ads>|3>*vU5tk=_D32+Or1LKj{ey5X}2 zYQD@#jrwIsBd|=<=O`{BB7LzUk1O=MTJ;+hf1v3+572&-;$xcrgz8T#zNG1#YnArD zSFF+WcNPDsh;Q(SU9#fIM6}~{)mtj^T@|KxRlGp4kLLGN9IEM9ed3pUCEI~Rjv)70 z>Ji1ZiX``#Zg~6ds>>ZZ()+63UvZe?NX1JOc`l=$sfsfdNvJXXJBrH{S1GPlyh-t1 z#UCmDRFTJK`q`%VgyM6GFDSmO$m1;SW%~y1RsHXZ?<e%n4))6m4av@pjiXJSw@W{(JQ8)rZ- zAqL}vrw4MFD91{q6WLj?2?Jt*`v%xr0y#mMI++5G)iQN51zuo4nJ!~o3j<}=dal7S zh$v2&gea3eP+(OFByh1LjUccw!7yUeERd*3iv>2v%vwyDjlc}OgNV^U9!?CFZuKDJ z#*{&pgeLeu2az)!69Ye$lZbNFgqeTCT2Pw16i(|Fw-${ve?9DUVtiB z?G~5Jrh(YzC@Kl*=AU>A$NQO4v zS;tIH8fG``FKAu_?kwNTi@?JVP69zV8^9AZ z4p9>F6%81>&Pbqa&i}OIdNn}~YEb$inljAWh{$(EO)z2~Bm|eHLC$_$WJQq46BsV3 zWBe3PTBZywcR{(Ef(Dbvv!#)lRfPlaAFTui2BI?t z84(H^Ox|qhw!c1&>gOq!!_JhUiv{q9s$;?AEkTOyk8fDfj_u<kMV{?%68v%b=#SU6#@}6#StbvW;V)PT+2|J&n8)~^ipK6#IAdR#VC)`60%a3c z!OoOn8tY~F8KT|3>DKZ>jJ1#V#@I$H01_U7zlQLX2VnQVrV!AyiD)gJvkE*+A0#$K zIypJEFAI@vGy4WaX9qg19R&@>pV1B4>BoboJjFN`^ktrcSZBm~GcY<4yk!$q#r_Eb z*Hk<-gtufrvyXTTN#HGm6I~*4$zwMHk3Zy)xG!)HR`v@Kj~fJ=6OqYvL~f18E#`Mq z6fOvQf$9SkhboR!EK!`UxIj@jOq5@x`VETQA6d^26z@^|k>WPRr-<0MxIGhv>q!f~ zC&co^I~a?u_^3)Mfq&V0+ciQ8Z&<<&8(=_tx}6 z#X*Y06b)B4PIVrm>3^ysZ~CcME3QzyM$vF(H>!TSqM4I+qw1R!4R=ObfqtJ>I-2)%>b`JO$);V$Sov8zMHpzQ2>YwejFFu&H?fwH^S}|r<&C0vGXyf)R(eXva z2b;~>xP5%|{sW=(O@%wQ|2BGWVakDzF4(xeU9|XMlOYdF+QWq#x1WogSGJFd_Kt3X zg`cu+UJbigrxF)q(%l%$vlbye+aWlsr^wT#KKC*p5bVFe#=2G3bJrez1kstm0 zuB=HdCvjfXVbMK%BGC^pzE;+&EQTL^vx__64d~3o0KTgaPDJ3OMj#7wqjH=pCNNk8 z&AWg}W^PnICh!(=eH2V)x}P$Y5KelRY2lQo0CDPTDKw8yBy>X5)+{X(qM~38OSs_- zRu%ST-}C(<@#g0vF=;Sl%!0ZCknBH>{}h*_>Rp~9gQ+QrZY9((hyJ<+&qI$OriQ2% zu4eX#)bA4dGS3~EdIod)v5Y%PR`Qk)WfIA{s!KR_#h&9Gai~_fyZ$W zTm&AvU1w}HV0j?k0$?Ge;$K20{sY6&6%Yf%(KO_d6`lw|8TPaUmf@K^316A&+HO6? zz{MqWQH3ZIcT!;G7;Q+n0+A&!4v}I|(*(NzF{0~SLI`S_04WyengcJn5eJ3Fd=FyK zyfLOcE#eNw#7aXj4%j$01mh zBSs|#%#ETA+e>-C@z1?fntCe@p zmA$-Q;!zC8_RXF#XH3bgE>3{BH_yo(g-;00sH~b%S{YTcs4~|+*OWS?h%f@3kTrfQHNCpna@qu%ulr6$M1fOQKUYt9t2#O!cvDvhj&7Z|SLWPZq zS0!J-XgwaB?f22!nga@u$CrBN3Pt(}elOj0&{v!Z!*~w#ot*fA4EX`X{&Be>p%wmV zXYS(@?U=`KHX^S@j%L>xHi`9aMw$ucEK`UCCLKCyAiS} zLmwNEF~dqQ;%emC{)WIGmygSviD>+7fXp&^hzzO8n7__!OwgIf_<*9Zn+j)hk!FIi zdjtuTO?VAkfmKS2Iea}F~Dy;xW$U>opaA5;s_iIxKXxc=y7SGuY z-lQR8_Oh^@wyMXUl_a96hsyEb!ceUhOz#CrCxZLpy2y&PfLc5>g!>{_#XjLVA;x{_ zQMt~LJ#(an9X3JSswwY<^>Ye!pzvNm;l0w8_rlJ>V-)j+_X3`;dVyk8ag-u&9B5yr zI7_io@hZiYifa__RJ>Pllj1{)k17gZ1OG3p{u?3=Zm%o8NyPS9qxtWt{-Nsft}@CC z?*(jy4itV*v4Dv3QPqo8|CZ_#RiC2z9M$2z4&Q;U6P@dq?TaY3RqUjgtJqyp`WN;E zsuwAaR+RolKJRGhw^VVa;vB{KikB;{QoK&_X2shT?^3)^@h6JX|ENd$ANaVY|5EWK z#a9$xQ+z}5EycepzOVQ%#Sr@sep3}??f~eret^w1J)+oFk$37W*F*6lMKjiHi0ZQb zU?VTW-MUHCX-aFEkZFUZXQd3sB>&EO%%i9?pzTeMu+TFBY0+8GCjwtV*~;i62i$Px0Y7v5mgje+);yoeulh9K`C^TmanY9Z4uuBaU)U4& z5tM&qducQS?ADSk*A-p8<^OhNEpcyaJjs*q`izSHaZk_ad*H8xkCf&6RQ#29F3N;D z7V^Iim4%^OpOwFA-UHseqw`mTS!p=nuZkf1t3Hmu`W12+T(W5vf7K6Zb@;3BcWEX3 z)gnmYfWcy^d!Wi@@JSrjZ((F{SeYniaabd$Uc?H7(&B6fUu_Nxrzi4Oa!tkSDRNlE zCj&W;_^hTAxf)<&E}x(U{1ezIo>W^Sf<9UexGfO30$2#C_>To1+we^u0^M??*U0sz z0%XJtAp}lG5rU?y8BN@Qh}V4yL95n`hA4qYmY~$d*Fp@Maxt62V=LMkujyhWNQjpi z$L8ONs9(dO7`PbEa?c~W&NxD_V7w-e1y)M}YzZ(ZH0nW!EQrRM^0bIM;0Zkzi~}~D z4UzY%?Q+JlK8lPDvV*OcV`KdqQejgBCa)wM0a>=xYZ4yRD%ZOUWZ90-NR~-kg(j1?WdqvGenmFM{m5vhZ^*LpIUJ9c zIR5MelV!55VgtG21KBuSEI#B-*4S|)%P>RX2_G@W>uj4V>ueoqc%bQ5-*?;s;WL4(P=47$A> zeHsV%I`o%@X#6dOY|21%8e<`|C}=QwS3tM@6(! zoLLj$x!5N>H`L|K5@vEVM{3w%6Fer)tS8HZYbsJ4qBu%%tYVqsEX7L2s}xr%eo>qm z-%TPnb{Y}O6H&dL>fCN+IW=9zFu`uL>X&GKsp>q=(te)mSiCx%439J9W_Wxe8cs%T zGN8BB^bU$VX3#EQv7h1q#o>z5@30%E`UJ%?#TkmcRj0qjipvzQR+ROC{O_xNkK#tf zpC~@0_?V(_m?*~^DEjA37xA}>e^C6B;$Ic_E556ESn(r8@&feJNKwZ0K|fRV4vL&f zjdqC~TH+Wq5(~5w?h}~!o~Eonq|Z`29`|W4V~c=Ss=iE-%mnjqQoK{~F2x5Ff1)V+ z-LY_XGMi#UIJ<7$8_L;j;K?+Bvm;-(0$iP&nY<{pZg5L?t+Vd-u(z&gXZe0Ft$cqd zwS2!D?tkVJHEC&2)TE|9Q40&cBS zwCSPH_|%$|(DK<5p9BWcUu_g4;FSqdZ*}vg|BUI9eujF-{aDvmSRaR zuW_`Ej6HjQ%Zt0b+cImGW;(Yu+VA@6&gv>mT{ZR&!Dt1O1 zCU@jSteD)9`yXa>l-Flvd|Sa}Nl7Ungp>BeEoO9l4iKNwaV50SSu_Y{bmWJU^uyeK z${v<*!+hrwvo)?2Z+?66=3jusq^sy_SsfmaZ_~S^je`fOME7#2;Ze-!!<~``knq2d z<`%4m$m2oyTKu_%%>5Zv(ur4=d>zqDXOzMs(yDz9a;_rj>p2XdO+?M!u zAom2s0{1Y`VFc+ZM+Sjyk<ECGMUAad%QLud4XNlUZe2X+%DeCUZMI1w8bW`3)nZ1IGm?07_s)*>9?Z|ljE{}O~q5HcbZG?=`Z&~1NNjf4AI`s0<3@plzuQwE~b z9QRASU@*bteFq7)zlh~819`^ZI>@FBeRPCB-p83>#2b)c`^$qrE+5;MiD>+-hs-j0 zhzu)nb;o&bOkf`4j}?vGAK+}RG15HR{aj^}Rg6aTF$$3NGCYK6x38zQyp51&+V?bM ztkMdAgw-h25Pt5LuzST60gD=j+fZ*Ttj2cAyA>0RKcgG8 z(~k!~$8{ACruTxB6EUU@yNR{EvWMcKA!FK_z?^;ZHey|Vj#ne`mpO%=!+;LC$-uV7 zZJt~b>nEP7$h#@~d)Mb^I*N*2Z^a_TA&R3E$10X7&Qh#Yyh?GU;u=NX4X_>eDsEEb zcFgog6}KzCtoR!u_R)rpXXA4Xa&j_$3Vs`_F5{-4w^sdZBJ{3`{WV?2Ng;iV>X&MM znd&oDuTmY&llF1TVmqbZf!qhEH&c|`3FvKA@1V%z0qyb?`za1k9Ihz+54&-yPf#pV zoT0c#ak1huMZ?jpQ~hSeyA|(O{F$Px57hVHsz0O1yLz_Qte4%YbNgiayNU-DKT`DA zU&v2WG~C>&svB-Dk(2A8`4=b_D$007_#3IZtS{(^oZM{9pR2e;ak=7kimMfGRy6N} zl5=3YA5@h6>k~M*E^5d9w!U$5dqgh@m6QX&V5ex z#J%579fS8ecSP}Zg!Wnc{F(Rgz0Q3eFqFBqcF)YLeWB`N%qljmWmevS+N=);Y~NoS ztsa24H{Y%Ob2U?TAZ2Rx4!ouLZtZiil>SKRjg&uWO8Y47%BneT&OhM$J9cH%q_#M9 zzvndD89sg6-`r}{Cbk2%Cu5`@Uai}{xprFhs>1!X{i|y^!&$Yw^Lh2K=v#Z3^WL6G z>{D4p-~Bew{T&i`(UTbP&S!5J;tkBM$ihH5nW-+6atSp*NhmVD01z^Bob_i$IO!#( zg;VYU#9#CzEAK_%E;h&6(=>C#YzxN2Rf$u-wYcy}-X$gBFJX=|UN5*jxH!&>{6lcL zjfMxo)*Y}FdIT|*#{+j@HUCGX@}TMtVjkY^|b}y*52$#kL?ifm)@c@iBE58T0DG)aU zSSaD^4sxV+Ru5l-ELvjDvEej*GLVN6gSuAp;4Fbx89cWq;X@5|-|$?5)a8htv*^n8 z6xaZ4^n|sDECFVVV$iH&`hOM?gYgJK3yUGeLeRpz^;~g5A$hHn1@V;)Q=YU}+`*Vw zX$Z!_63D9%U1v0bZNda+i`UyOkR~B0L(vZs@Xxl{!Pci@3 z+4Icd!ONZ)&4w2}({j%BNf^c z`s@_h*OdN>br^?>eIBoKehl+<6h<=G+GNn0tYVqJ>{y4dees-F#5$(%kW!c#Ssq@I zvNHMVq*eYk-nF6cxnIP)o!pbYdAC#74KE!S&PEI)ntT0xCR)MRbw(OxUOzL?&OTk3 zlS(1dO&QuznPMdvk@uNj11n}nqb7$NU;6!4FWD7`#BTQ_}c)PW%3Xi&cccw zj=na5d5jMz8oN1gRv!=ch}r=p?1r7aZLwa4t%!E}_`L)63)=@V*1l&TW0h6_Bs4*x z^Na#C%S*n*Y|G3Z3OnBOnqcgR*5WyDgEMFd57q?RX)EIlX#818BHHQ4g9k&kRxrI6 zB%KHzjO&8yB?#2wp&>jN`78Dbj~R7%u;3h6mk8sL8iB`}pIiZc}`Uh=bX4iZ2j#d!*ktRDYWY{ea@X6#3m5rk|!L z^U|X{w^OE{PlPV-3PK;K`Y_FxTV>=kupQiLh&+xExju;z#kPu_6mu23E1s`dpjf0h zT5+u6B*iI;vlO}Wvc5!)>pD$et$4fQdd2$`f2=5+BmDea^~V*TRD4Nsm*Q)RzgK)q zagXBriXSSPcQ}*TkEqAI!+DD8!bKvzh3ah;4fmDEdG*zN;V4l~)(_BdUzckBL`B)| zQ{w9f&60MQ^(UMs$~R#;4h+pSUv3%7N@A0b9c{k+bGtTtoY>9;j;cA1&=@CHa6|Z{ z=;~-U&YJJ`isFT^HX{yZ&C2RB;$Vxvt!+NyV6zwd*8I7$QB7uO#K9)B`qtD!&It9b z`CH}M=FD+>{TW~7P00eohaKK(-h|eP?n{_DZ?<^Tg83{uVC#8gW#AIE__$^Ea z)`vD_w7H~;|KX%xvv4@&en6aQ;;phra_NXE#pF!nwVT1he#(n1?1uLd!u~=@^v@E< z!P}YbAY*nh?gvSHi07|$x$P(Wui!t$~jL=@$wLC+BJ9}8KK;Eg~F%pxB*91*jE&_r@a5(2}qgatt=A#gqx zQY^5!Y0jP8ekD+EjhO6=T<4Ek=br;P$I`n)KHt)NL+)eg{UEafQ=W@A)zaA_Hp8wH zssuKI_2ZMR1iAttMTjDTkh)Sn#L6y3I)VM9#2H0ahMpo!Kt#V^xt_w5Al=jr|45L) zdRiccu!@MhTmW@OpnoJ!0!Xk-t7xkE^ew^4Uu5M^uP1-8l|RemGfj2?+0uek_LLoL zT^?`*(`SBN#+jK@(lL!RBe9m58(_zJnQrRk$=;NK=$x12 zI1vgOOkM?a+h4CH!Tl2br6U@DS3@>sAUc=89~L*yAEnCdry^vWZ50T+{tOU*|Yy$HbH!B*uGvIu#G15HR{X%7v zbsg+X8K$vc82$^DZc^f0o^xyN4vCUTiBy2+=-Zq%PIvKD!WBUg6_h9#13L1}wF6gXpww6f_urMmK1u9}nJ*ZHWiddqIj9J8Br6 zYd9XfIz7zg;g%T>p2ICG9z2IzMm%`vRj!M88>q#DC%LxH9*hSMqsDl7YXbeWM`R!I zJQC;O;^)SIh?_XEqzs=hnmB99j0LmHrv!81su7MCD4T|=c)U2C{9Kg&&?Tc3c|$_I zOmU{-LPg&9GygipHHvpA-mkb-@iE0G6@RI?Q&Gl7!QY#zzpHqdi2c0ISSW0u4IQH< zV~SwU?VNmF5fSwaSABxwY(;rD4R+sE9o5(2e|UYs_Hca?BZ_SmkH+8e9KdosXAt>} zg*a02QpJgiQx&EEVRyOe9J9-E%N18C-k`Wn@h-*t6#rB4r;3j#Zc}_p@j1m;6?r^i zeR~ya6+cw`mtx`=wbR*;DA!W)9K{?(;Zc#_TlGPThNqLE5Xk5A75bU0IA2lL7t)ug zevP7VR7k&3^;;D0RwRo=e-A2dQRILhrf*k#R`Gd7vNOzoUGYzfe^uPC_^u-98`_)i ze{x<1>P-~M=TPsU$nXA8=ZyD65^bm|M0}UYcgAbs|@?|qfVRA2g8fq3r8RHXZc9+KD_!J zujcH&-iIrJ?fd>8c*$Qmr{En^e`nsI(4}s#PW?XIweIkNcN#C*|BK4#fjz<%N;SUA zYd7H_xp5?hI0xAcS#ny7%>}1)3z#>IhO9z906JIhNgzn!j1eU?x}85ubJE2 zJ>5OSZQ-^I;Wd+-%FAb0l}rX!%?oh4kw}9%Is8JalQX%p(n;jS{tYHXI|F^i{^NOr zfyZ<^1PAov&x?`oO03sDIha!j?_uOBK^w(;5I#RQ!H5?jA-EI_a)xB$tcFaU`EY3( z<2i;yHf3nZYnZz!XfSyt(2dNjmFS3eR)P`#19^76*WuQ_7@4d$jL796Rv?-(5S<5b zbr_+b!Q{R5?Z@bD;|+Z+3&7%_q0N}Lc)_$kk2Vn9HKZvk=M!0FID8mMg7ap zWAV7gcJ?A-=P6KquuU7o7B5yXC&wC}}j};$O$wh}0yZUM|HEhPOo>hfn{x3%|5CSi-w#*3Tl7v!8^mF4`c?MxYTA_^0F!bZnUtiY zok{(&4!MIj7Pc{5O2z(Plt%a0;ZknI^12t`Pp;s&^j46AX>2|&PKJevvf9G{^Kmt% z7D|~1joYhoDVUn8Ju*T<+ZD{Fsh={55Kej@U5}}`o&?0F=DLdOgH*dt%|*V=J4?30 zGg*UhDe&M+q zu2gb&?x6daH6nEdK}K`c;Zn%Q;!}#q6E5XZNO3NOgA$QbFPCzBr`y5_-}=@gHsX3d z{TMz!{etv?jYG)g#~%|1YatnDOU!izl%r?@m%=Lv&>;k#3cxoIIv~nN4k_dW>4ft| zEGCdx@tle)*HfV91X6__$(|6KN%km0YY|5i`UR;2071*@QZ3v!m1?0#KX@;Z&_u*B zgrK1d-1Rw7x*{soLa{p{7#TtzM9nePS?@Sgl_k8R>> z_HLh??2mD>D^kX%^hJ$EUdZ1Zw4|BUrc$ z4H}~KHRWGE*O{)4AYbBRVR|%ljMA5$V);alg@={CUj~ll-(XU!FB8XNpDxTvq!8;` zt{(IpvIJNk$HH@}-Uf)}B%Jp8pdjzXa5*a{r7&<9qV4YuD0d^x1d}%j2}Wk#Qk>f^ zuo8?o9(i`X8^EztAd~g7J}w8b9MP14===gV_z?;kOx|VCZGTx7M__X-OJQfq(8cTU z$7^*HOx_hpu>D0We;LR#?UU~s0Jyy)_nzYUOCCJ&Ke zC{_YLMs5Q07#~nHcDLf5W3DmMJlZ{?vdPLorKSwi%=WSsvfaL(*7EYI#VqeLkgho&>yO(#IR$JQf~P7rC#J{0(|C@i_fX_9hUJPBSvU0& ziW3w|6}fRS{~L}4{eb7s8|@M~m-{r`a4)=RrQPF-zf^ol@fF3_6yH#MOYv`t`xOr>ex#U;otXa96puD< zm29t{z`=A?KTYT#J2dYW=|6Ts$oEziz=3rh44z6`Ln7pmmhqL+io!2?~ z#=g_48}IY0-Cm6`Gn9w49<^6jkJ^`vm^8CTZF2R(+OrYwtF8eflavKU#!K3{8FMz0Kq%;ThkTx4hVWtt_gFP)iroZ8VWHnQbmWW`6eaHclzAN-5RPM`Q5-9(o4 zeV(8(hJ|DdRs$T|?A``Q_BY}`#T|rym&7He_var1Xd@WALwMTii5QGq8CuP(5vdmw zhB41@EyeV-5;46cQ%BJ7Wkhf-T^x4|b2)+xD&CtDl>^40;=MUhuMJeZHz(?kr8V_4 zGi{yp^xo+nPEejr(qQ&4NymXSNz;=Cf~iVA8R-;Ka@=|*LO%}74A(oE8RFPL4ihJ9 zI*}a<8#FE+xB-A`AxN(|qX@kaJ*To_J%uPDObA@TplKG%AQQSvplRqP*|}3rnUq^2 za(*Xb*FYXdo*i9n3Dj@{#j>%`W0VRi!3HNlo}bBm)kiv*PEZ?wd8=D zP8g6g_^iR+zzEJ4t{b2D=UAsdw@*D^*Llv5MxO<1w$7`3$8kESkC_GPV_#SM@>4;d z$OZApQIHv49$MjEmiElknNCsq7c$<4(}jHV9$IktmTL-#XCv}NjQeZ}`HBXNU1uav zPSypyrUOrx`!%E->$4y`!<0eI87lE_6#z^yM_g^ZTtQ%ox$}o+~!SFDm-9FAc#eQM? zAjaDFEM#n>6#xlO!{2#E0kTd8@&&Mqg@3~C)tDByqrJ6w&W+#z`XI3>()mc2?PELG zHrwAT=(ILSGr`nrbc1&K@!*2kmU!@`jniWZrZ>p%=5(c%Rb`% zQDU`xJe26z$|a zGPI|$>KJ?~>0K1L{nAd}7vsT)enhtKO+4$)$dZgPw_#;EsBpSKCbw(;;V{p zD*j3FZ;JaBKTtFrkn}U^53?VE($B!As+;%1q~DR=Nz-!`&3j>mst-~m{Xu{7!UB-v zBB{?*oTIovv0Cw3MGkMF{Y{FuDgIdTLB*dbKB}0^6?i+R|eK5_4zsRJ;F`HNA!Z`8i{VAi(#IfwbdjPY4{cNe|3 zeG9$_SbVVAtVgzwkKTVEl)edH@%wG`-olgvA6@Xs_IAE zCRq3>k8JNO-v@koSGXp%SBm;g+cCAoSDz#9`U>K6K z!N8+p{`*O7km1SpQZQLkQh0I$)%7>7%Ww)`^@~$o+(5kF@$al6n0X}8f^P!i?Jtf< zMvd|^U)Yy@(D!B4hW*YkOyUhcMi{LCB>UWVQrv+^ce(lEB}4upxRp@De5KF5=y~W7 z#MBRw=Jr|5>=CIG2nEc;?ByI%{hNxmNd%2{JMq&mI=or;RUp$^> zyv(Aa{+%i|TUEK0qMT>&vL98E(WDdC9_lwnUxV3|gU zNzN4sGndmv6{6=XzH&VUR*rE*gewqP0yCFW3~G|k68>0>E+GUpachVLIip~h6t}*h z(3tN*44NmCn6n@UQpFvNiIs+69I$b0hz#3eaZ?VWgusxZA0*(P4YGr+Ps7&qH5<~T zNAhEuRq06(RVU|kDqQHLVyf~SFRf~Xmo}A?mQM>e@}6?WUV6LNxK}IhhnTPY1t&+| zBAZ>ZXiUkhu1+vdd3=adz+ZjB*rsoWEmdTfmd~l0S5jJaVfoal7#!0(9hO|r`54_O~S@6u=cdY^SY;shI27fedfx9|Cp4*iFHD>Aygd{$*-YWciK z!N{SJqS=$nrc5cD5-FZnURqXJSw63_V4u6bR~%{#a2d65p7qo}N;vaDm| zQWVK8(<0gV6VJ<@Jg;O<>Ga6FvIR3LXOz#0bnTkowP#P#21jsQZLNb0k1_Rr(+}wd zJ@Iz}-z^KagReZ*<(z?TlaoJ?AwPiFKdv$)w8B5_%zb*I9rGBDh3ncJxR8HyrYVGG zd^6*1L|&SiV8q@?usIISVa_>sPeVE`>*dVF>z!eUrVK=90v2!!1q~)|5_BUoD+>!g z$x1Ndc;wmjuFi6t4aj7@tdGkJi1Zik%d56}u}+|H8gN^&-X5iqgNxH{4gLrq5KIqc~sja>Z4O*D2ntc)Q|V ziuWo0L{a)5^-2E&AJ_C>D!!!nisEaEZz#T{_;8hEpf1hNv#<54vpkDe?7z>ZM+@zCLmM6nCFsN}!{UpE|E+eni5g zv@45-L|qpR(ct2Ro4AJKbed$;89xPnsu$)lA3kyK9cjxpI|o9kDXZLdV|J$H?TilJ z?`Jw~@(zV(U9=_dQ1bW(4|x9Lg%9DYcVXv|?T7H`j@wE{7G&gx;|bRv4}&J7+*=84hbLa}qeL zlUY|dc#eXb3 z4#{;!66n@<-f>6DC+`B=kugIEfzwfhpebuc6L%nD3>G11)fyhSB{ac*Q0n4qAqGvk zm`&la6>T+(V$CZaFEftKzY#IXSxlOYV&Gyt%RP_iI^zgIV|h&;3#^tT*b-n+Xw-uc zSrCmiz7!B=_FPLbVn^n) zo;>TazF=EE3te_J8c90BqMc$DlioRwBcW_YNv19Ov_qpv0QEf%{7xi$c4@`@3rmAp ze`fc9UNwFG?8(5XNS|7<;N0xWitH&}x-(@~c}Z0^CO*Azdda*gk?d(x7M9GLn%y;$ zJ-k~ad+MC>Y|H>OqZB5yW|UOUm@^HDQ|HeqtpcHxU0Ehri8Rg(Wb0ECc)w$$%P?of z7e<%yI@_L`yt8$r;en=KX4~bdE5a*Nu1;Q+bd7(l_g&1x)HgFPG%hW(ZQ+R@9~N9n ze#4oW)x?VxhGXH(b_OowpV#vYg^0#Cbv|>y!b&h=Z{+Fi8_k>@;LJGxIJqI*Hpu-P zuS13*nlcdO9l$LVG?=_e(2dNje9#Wttpp<`a%OyYj`N_hUe?FuASQBV?;s`}m0CP}8qSR8hPs?t;&e=Uq=p?f!DHggda^vY zqawv2ilY?ADwZkEQmj4(Qz+RsxRi&uw};cQ-FyaTH?4edA|;J!hHheQ&GSY^&{&K z`YhFX+^2u?8pJCVmno8&VERppcPiec_<-V16lK3V7S1l1cB%oKUBkaSxPd2ATpDm2 z;{-a*z?_q>TLG@l%}ibtS~s|*yVhBEd)Ql7w6lD_msY+%lv=(Y6DghfL`_=S6E&%+ zPt=6NcSN7)>$GWl$nU&hOVdN%wzQg*q%DO_z^&y+w}4yg6m5DaG(NQ^B{aUMJyIuN zG}@-^Euu}3?rsYs{lUU+NbeMVuyEt{*3qY%`#ml#YAKfF@)}3m$oRAOx4gK^yDhV3 zX{K{qBg`G%Y-j2jRs9xhX?e&^Us>1{_Mzxz)R!K;ugE>%x-V~e6tbqtQX_Z> zjiF!R@i2i^5i`O`GU6m(}6%xE1SIw6|f&;9icj@L&`O#-i~666P%S0guPyL3k$Zgvt9E)ewyf zS&nD-R8B=7j7Y=r&4_8Z`_xqKy6L@{BSX-*N2dRh6^OcoDz6*@mE$fynaQ)?#q{FC z(>~*Cne~lGiw`pk#-mw7(CV8o%SVez-4SK?#Sk>&?}PN7#NC11mdKumeNR9va1R3= zMmS$Y83?u|5P9BaAy+=l2O$WX0r+GefmI}<3CV5T^`^RHXUzcWyO9@^9swy9f@($* zf(EVODLNLiAb}?%Xm+v5V_Hyp%$*Q}Mvh@4Uq%F(xEm1EI0ljgmf>Y@l2gecaufp> zqwa&a2~nC4l8+;<|UJ)MSlwBn5GJ27$J2~Rbjo`lxXu8lq7ew9I+&u5HUO1q* zt{KuM93AKB3Me{|V)044DrZcagW*TQ(8Xx8W994qt!XZcXN(Q?>fwB@6LiIR$4|>Q zHi(it8oSDkwPMt~(l3slJ7O$bXX|*v!%4kk*$OgyhA#W!__=?Bsl2{aW7_P~hOg_t z0LaT56Zo8eiIrf)3t=FaQfjyv1VjZggA-_Qvf>rzP()LPrhG5+ZVDPq-bCm|X4VBD zX&$!{jCd*X?0O@(EZdJv*30_19K<<@rVK>q5HcbZG?+YIHroEO8VC2a^v5e5P`wkLpe-X=H2J(!*b&yRN`sfIMypJ=%h&Ld?_Lm2LTt2oh6VdqN zlRlQoLu6QqtGltmb%W^4WBjqAvHJs@%@vE_&)EH3?MzlN8qvonK-SCf5Tf0_p4Rd< zLY`^g(~z-BD*zH!qfkTmxnIKW6;lYv_AwBx#d9X1GaACrt;TkGmUsyMj6W+$L_7U> z@N-;O@nCu{NI4Pw9PeJ@+bh>hJT!!#YXWoj$=ir^`MHFtyyRj`Z!)lLahoTX#QKS+ zDmEutsW(%U+X?7xRqvq4;{omR75ga;P#mr({SUiws!vcXQ=Fl= zNO7^^GDXADtyBGGMV=E_|NV+TQ zPg6A9+^MP?ZZ46NGvnDVP`g4!8IK5mBUP961wE0IlW#U6UFZ_v6188hc%9;E#hVpx zS0v}ac0Z`doA=NsaByAJj{EHq^NwL3zFYg}YNiZ8%GBxscvJJ;+UH^^{gKie zDSy(G_EFlERdd{&f57*5?8>M~ZE@;;&uO+ZeEK%bWro_scE|Q)jMQ_T*S2r2omRc7 za6jfXtKGE}t(EsauO1eCYY%hY+cSxMDvRj5-vhd*_M|D=Pu^P2Je<8otloEQ0r;Bp%c7ovdMe=GC|VrnhY+yT|h9+7$_VIcGH zhUY0X9K|Ri35iX4h>?EbmcmT%RmE3-A3dGF-7P97U=h~7ZHRdK;0-2Var;Mgg2J$ds zP}gc6oF%Xv&+SRh{DikWmmqaHqUS8Say^(AS6$3ntOPe)U;rCVO69_&l@NyzqGnUi%#6rRALKO$xPj!Hrc7 zea34tDA(JdZ+v%kPDJzq&PFm$(<6X@ztWvAg)OjVdVT4y`b4sc(;BoT&D!6TUI0L3~>enLq2}MJyw^BRs2NDwP z=!4;GL|#=K&8{{38Ro=NsCIxLpwJXk8B&bMdsV#!6T4pE7zQBoG-$YFk8vQw zAe%BYoPq`1LP3Mcn*`m+%sLGV!~xkR7;!uj?0T1HInHKevR?KBmxEZ2Xv#ozRv;rn zL4(Ol9IKX(O9{9Xf4qV*{+2>EW$5BwWYEq8lXnFY?DqAu{AD1|_`4CZDMKF*BZCiy zO)%nWB-s8&!ylKA%bSU4{B3~DGI@v$t#Gq6+-ywHnaB8mqOq%hv--HON7N1=;ceL2 z+aT*@*otVkZ@jg<5M%9o1~OJ@1wcYG6lw?;HUf6M?=`{n3(;CU=P%$98p4G&!*<%r zI0G7gR+5Nz`tjhxP^}eA?*&OGf(zri$cnXqT0As_3nPccKH)K=4i^?&#?*bklSgU< zY=XEw3(ha(d5*@1@fbzBZi?qC7AOu-9I7}@u|#pY;sV8QE3Q(!LGdOeeG(&zZ52By<|=kql>UT$f$BwyqZP+0PEwqrI7^W`FY8O>xvtan z)rz+(u2;NI@yCh}DUxrezsD7yRD4Nsm*Q)RzgK)qagXBriXSS5*l+MFZ`1+Jdz`0e zy6}-mZ=t#j9Dr{4FW#H8yy3n2sxCYw(q;Vs4gV!PCG?4EC)<5WeEpzV;?Jx<;XPsB zgy}diG}HXtF6VU*c&Fh1X!GOu$TRjw=czUaJAZ7fSaX~~I9BYLldj)<&2Xe`tt z!fTQaEb%Ws*e+{B%`?RpA8Z|Y`kk(C#m@%|*#?G-U6<4Ciq8;D*B)MHz=vt}E;J>|wX)&68`J7VIr@ox{oR zZ-5RzC4W5mq<)2ai$XO`8`Wfn`qrd-57qqfN^j@ynwIZ(3di+Hz9Z@O4beX}O}V34 zOMeDCuM{KKIa`|ll>!sUGF zuc2$a+cskP%lf&8L%046Jvt!TTrwqiJ++|77Q||BnralhL2fHOYrlpFOwV ze;>}QXE{@4Ig@S;mULvZzBO-F)?Lo2NF z)%XR`bk^k#C8-DE99^@06NoQvaY#d29;|V!tP(BNhTJP5& zXqINpe1}7M!qCDDj6$>q9-b6eTfjK;Ot(wpQ`|=G*z`-J&XbdzF7ipwEIS9+LasZo zF>7no${E-=7iWXU@!^dZW%R;1zDaxJu(uH8)S+V;xnqEAZA&Ee?K$6hO$2Ub%wPc% zT0#H|OJFwNBQEB7ITlWbgwcwG94WtM08xDnh}l8lDFnj^32HjTG96+}dHQ30X}H>- z@APlmqG#Ln)H@@lvwoAv1lE(uMEv@<3yhI0fsSZ{4@MZ%WSaJG7h3{j5_aY zPhW2=PYNvCXma2&xQCgl@!<$)<{yCULmIA2((CY*7Qq0 zYduBYDuT%-XnlRG`ud=N1U7a7BGww=K}6KI=}HQ8lY%xUU*WV6pErun(S%14VYu~5 z3Ur*xs?j&eE!LZQQm|afb5Rz)Bvj*n17aiRy>LfVlKerB4?2b;A9QTnVm;GYX=^TR zGJLi8An${Ya~=M-Ot7ULFZtTmYb))wJo{)N4?CxdH8V1J5QE$I{En^HbIo3dnB}|| z>R9Di1)0iaJsmw{HKvXY^Z69AMO_Usxfpbb{&7V@{l%7AnVqW<)FlUjeGiH@l zMmj9&*}dcVX>;aBs$?EJu;vjnA>DY)TPL&D&FwlK>DhD2=agla;l1PWGXi(xXP1;t zCsTKv-Bw;+>BuLl@bdD+((+1~3b+)zPVn8TlB(%B)7f)JJY4{-F|o303a)KnfKKHz z05XT=b0$`mOvdsC<*@%sx8ga1+ud8l@wQ%C#G4l3yYh1)_!vs}j`^MP&S;0=y@kE-K7MC!0jtUz04JTZbEju78$=_xw6v=&hPwR#lSNIZj32@=DBh$rWDDc96?{sN0tnqh`!uff;kA zlr8G(eEg)CVlb+nxBRQhW>+ZJUgr^j3{KWYbKXdKuYOATe00C_bs0xor$dh8dl=hg7GODFe~znC3VU3K~ov&ZTwyEjc5&f1tl~MC0#T z$fgWLXCVCX2EzoCw-O0<`&L{2K%K_?-2vH@p^r=8kFVmHV8mOHVEfwue_T&&A1Jw) zzm1SthT8+f5F8M0O;~Tte+bdG`%`B9&sCmKJAj0-sH~651hZ<$GT80gXe}>q3Qhl! zE5&N607$q6{u=UJWf$x?uG0k5FGOqcoLibWPB9WmW|(@pe%Lm%4?%SPf(HcMDQGbM zjBe0QKOWCj*rs^!<+)g1YynJf1{PjyZ#FvDcszJ@dYsG0Ej1oIhg(`acnPz1dU(Qt z-PPKD>$c959<<9hiYt&j+{82ovX6MI;d7RbmWAvW2}gLmRTF>qVqI-HbxyI^e&H{K zb;)B0pF!}v#_znyGZ`SC?@(v`A!N2AVsUwVV|q8m0>uG}!xcv>mMBhDtW;d2xI&Tp zJ^kLS$o-c3{fb)@$qO?5c}0090R1)9-%$LsVvXVliZT`%_A=%e$lE1y`-X$>P94XH zK1AdXQhm7U@@gUSC#XJM^JQ!+>=&vo?<7NCsrq--{`;!mt@u+#&cnibUsC+5Vl5GV zgf~UL%k_r#^4@{igoyN(s`D0)>DiiIL_~Q8rgIM<%K8R!8=}trnJBk|z;>#0dt*9} zA;b$6`zgwLNBTI`$$rqTOmT+dT*di{D-^F$T&;McqO5=T*`WGn#jT1@EACMIjUta> ztpAYWKNU#}FrCx@(LC#ksGhhTkT9j)2*t6A;}uI4rzut_RwQ<40()Tc;VoBH{Ra$Lpf z#Oz<#3?(1gf@b@|A=nAQ$n1Z)UAvrH?=wF<3Cxp>;NOf*@7|?*kPtcgGryj}aiGpK zzc=<3R!3^jPOI4ZaP1Rm|EzsN#)JF6Zd$wgeD{JB{2#;^@%8)8uRed!=GyQ%Z|pm7 zTwd+8v`B4A+CN}TyQkg>dmf$?hH922vjm);>3LVeS3rRMqw!)UDQ^*{#+)y{h(})2G(nJF_dswYRTrH* zpN=txpB;QqZ2%Hz+ZvJOi0u(G9F$r+TuAE{>w6-lms$WM48Z?bL`-Etn1#r({=`Ly z;^2e4)WdC4562(&m_lKvQlILWvZ>D6;hJPzG-ex&i^QiutV6C4oYhfc&>5@yBU!>? z{BJ}=n+6aA+bW+Jbm9UY*d@^RHAJ?bNSh?*z5X4~T5q|IiY@+Veg`5>O?9Ij!5oYUP~+yPCBEB=o{RmkeorBmsY`5FbHA+CU=fN^`1M z*L%^9Eu@L8CM~ER&5l3NVOh4Xne*Q8j%aO*cRR{%*YdrA9r0`3LR!BW7N^rf7T`!5 z=0A;y77Qh_k2=R&0H2Q2r%y{(F}!2zx=vcWHx$osSmO7H+4Yn{H?z(46=RXzh@)j? z)U}9pKul=e0^3W=m>O$V{S~xcPtW@i@nETc$Dm`jwL~YiUeDBnh-2#Hz)!=Pz|Q@c zO4-8Jv8@UY)GPPjzq+$ouZu!9yT)Dz(ICJkrJ3b2!~-m zi{W9;1RlC$-M-nQArw z;6~7`VIXgAXv0W-5TbqdBcEO0GXY+s+5R@e-z~7Ezhp$?FY(z+Uz{HPfP527UDJ_Z zWahPkgM+X&!Q@Rrf?e+bkg=K)mZ_M z5J6{umvOIgqFbfmw&0s;lO3z++ ztU2nlm*6~kc1$6*nnzzhe5MirW=m zR!rpJ-())WQS%JuJ=H%{`xN#A{7HWRTT+L8XT>g>e}U?KR5#CLgp-H;RL!qaY;J|AeMLujy~9j^@?jYH?T)o%=jFUhMvYa$5zxv+6u{Fu$i_FU4ZT z(TY}6_+S3SCsVwd!Aca&O8&j zU-hkuk0{D|gWc1rlNe+6zZ63_=(C>jijx!4>N4&HZtj0;|2HAf*c`LMZmtTf+dmshG4YR-FxRaq_dKtGT1-IBa z$!F=KGuZa45}1J~J-v6jhi2D(Yof86p3XNT$W^DD6wuFjO`<1`nqjD7&=*DEJzEFbKCn-_web8$u0z z9q1g=UtAM2=AiTDlhA!U#Bx0&g6V)rWtWCT+rd^foD*L`~YJAa%h0o3XyiW^pKEf$2^9HayPs- zPOR5HlAC+%0cuCz3_Qp4`q2a<_CtbwFFqX`#%`oFLByp{>|T5{WK#yB^IuSSeQbis zn~DS@Gj9$$B0@of$(sz_u6F?L*?FnJdU?|4au6>^G-V(<--AEenPBqfBf<7J*7Ao_ zW6a-oA)7MvaVPxo`r8B}UX29X-*ot6d)PkiJEna%LuQ#gM25GpqC3N<3Cv@>OVQY! zj17llxJ)p1KS2Uz6PCa(VicfRzYjpR+gD*NFZ;)|ZyRJZsRAHj1N=3FL-`HtUNnV( zrcFd^@tkJ3K#3snRHT!KVZE%MZ8O_EM5iY@Et`S{-nwlJ_1%^XU2^)8hnKJqS2N;7=F8L);Ss=)Zi*ay%nj(TaaBz8 zsX8JmZes=AD?nn#6KB?7$xm|Xx*g7lMDlNpNaUB2OC_y;pUUTOK(^~P6kPl&{_Hu3 z={YD6-+O|k&%X@}_Q)Kf-*%`86Rd*Z*vds`2DaR{v3-wj9YlF85>Mt0Kw|6B{UVPu zf_#r|bKcL5vxNqN#Pg;X>y)xS+zV1IvOe64;)<;g_ma4hpb_oy?p$ycO$Eu`$V=jv zdA|hLIOO62>cd%WKp$>7bgd6Z!uoJ_Zx5S=U5c7Fju-7!bZB0)usSS8HHu}wp%eda z>BI3jqan(dG4xd8yl5GDK!Y|#65|7E9_U(9w_}}Z>p)_{;E&bPh zJGRAe6Sp=F!1|QYJG^hbj+7pC7=~dxg$WfrNqMx7a26^G-%+q_#HJJNrLaxL=F@-- z9s=`25(++UE_hEfYB?UjX%Y%PZWj3Hepf~MCfuLjZ*Jf2QrL?gueY}>$KJY#z0d30 z-2{8P)3>`0_L#3-_3hq4hlXqH_`v*e+bAqmL~pb%cBgO0zF1mm2rL(d+`io{k>h3g z`0~r`+dT+-yVJM(2zpQ1p4^WwXJX{=g2B7lx0{N3wO<4FA|fOGe#m^4`*u8s4fXAE zzDgYF+wrOLKkwUdh>v}$;le86MB!1wIl_g)rNYyMYlZ8D_8t{>ZxnyK@CU+sg!XPcl&&|GgCYE z`F8rgZak04k|aWOOM{R%;%6bu4e0;fPu(zOhaXE`KrWVlDj=h!F7<^uNX%KrS??RgB z1g=jIdskc{4{zpTTg9dFpJehnONBRcd3ZAy`?Dfj=i$v<>^*U9^YCUawoP0*NYVOU zNZn{LcM~M+efIl#tVRW46(Vxp%u&>sZ{{p+LQt4s>RrE?%f5{B>zUcgWXb5uxV-u= zp^?E70)n{;pxMPPeTWIxc`mTX{=fhb`nP}@|*pFAr z^dG2~IRV-Ji8>?MxyLRlW0760=t3^88~cUVsEO_lcC{eQe^kGQgH!)&{TiO7ulqG$ z$~!Bz34HM6FbJaki-l;XZiZ}E{TdE=-r|h`y}h{+n$cr$S4@*o@OrbrNB7G`B-xhZ zem}2Yb1dvp&j)WWw_n4xPrSX)>(`tFdz??>gSVIa&gux*+ns*Rhp_eWm2SLnittF`vBD)njze%itAxCc$e%B~NNDqNA?N&M#&;K%5>fa13wPCDIga+A z&-+IGcU1cia{Z6p>#qzb9kAQ)s79hLBV^uDwMOZdZu;5$Gv=@U_>A`x3)XzR`u*69 zH6O3};Eaz?|KRY7H8Y0Jn0e>UXCRi|S2JP_E-H6jC9D?_^8M85*!a>d8qlY)^)AAc zwfJMnwoDnzKLSc|mO|XmLEMKCiTu%!WxF>&g30WQEWX-_cZNd3&p~`067+OhF>NYA zmut*H9A+jGd}EYs4?5}RASSbO5R>)hASUb0K}=@nAhN%ftTzWSS#J(vvfdoTZc+B`D%nrh?~R>!=D! zGSgc{S=&X;H4Sk3f`g4eB}FWAG=5#+jSjYOHmV6_*kVBqo8}f6&16_#I-9yCb8}!4 zK3tF*zZO`bT#Ct&6loV3sgT(etV^Gh!q*zCgW!!&_PyoSKR7!?*-CUshgDEQ>IlXdMgeb^jOb_5b(G$&I`?n;)5h zJNvk$^OsIPX7=oVVkO`PhBFQcu~P4QjnY_i_p;?_&~J(E)gXQ4^3m}Y>G;BQyj8l> zFED9646}WD>sdEAvDd$coIZVG`LJO-9Fg3;cN{NhpzEIL$J?O5SK)Q>4g()t(>7BK zEc7otc(G%NV+dy1!rH(_VkYriRxX@*OmUL9Jlv)!zBRuNM^WV;_o6B~;FU;K^KKT#*(4e2E$J;tXe+QXg_el71 z=Kq#u_L_YNjerbKluW1vb(YT*XdgEebaYJPXgrZOBa%-^bWt*Way~wN8j!)Kuth&9 zA3Qk+0#7q;6rO$TANk_G)3T6f)XlE5+Np0<=#9GI$8~&Wi{k`ETm8vJv{^Dei?p( zEti7cUMjpsc!Tge!Z(FBw;1UUMx|iB<_S5XK>idWuHVyyXAn{G zu2j6ul12RY$>TU5Q2gVN|8zz-zCoo$!yscZKf>d9$K^LdX~3`f|)IKR=h9_mFzu zCG6MdpBwkO+#I8S55JulI&?-Kj{ikwu^+iTF{Wlj@Y6R~f6QJYJR2DP9tCt3w%mYmKdXbz z_c+e?{Bb{*-3A0>`7@D5Lx6{a#0-aVFdd&u)$-#^l5h1XGuh!jL}f<{BKp3l}02}d+SR0;2WJs~PN5yTu2&Amd4^^lwk2_67U z$Y&5+G2w^`pYU3+mhce}&Aoyp{C|)@#!F)#Yd%AICO=={-)$u=|3w z-7zI^Na5J;``t}oE|^aeW||5unNJQ%+UO)DX-j5@##?@CCJC#X`zXub)sQjlnc!L3 z^&FEg!*k$E8d{8gRxdiV=td5+gNxbKP`Q|DOFyF6s{V*#Ya5(IrP=w=;t&)th8Yt? zR#Xl-`T)yTB^w1b#TUoQI+yLU!B;?x7xH>zib!lUVHym^?+DT=k_|{K(12Ci`Xh!MKWpja5n^zAqL2w6G!{@ApG=4i`OW437DJF=FQKrG} zIxoBwcCE#%(cb452sM}yX!-oO+(Bl6W@1KV4#SSi#kyY}rw=P}`FvH!Grc#;zid3S zD+Vs#$Qz9T%_~miAm$r+y&^ORIyan%&zX(x6mM6HRZ(_t05dxV#{n)(G5sI9xlEs4 zUOl1@7C->>4ZaGanA4|czOD7|_kYnSCdNk14Q97SEv+K%Y}|AD^y=Z0aJo2r-DhC- z17!0SFR4v)2sU$YnSo9l0NvSWXSP21#T@=OoMCYPDa5w3F;L#3%8L?f!XvSOCF#NV z`Eu7ia2@J@#x>^aF;Jc=Jeyo_PgXY`K}mmXWh4~*1FE4h(0AN3%rw2dq2SO>&V(8a zY_PA*2RpihnXxa9Q}{Ggo{j;j-5CSD9T~bmlF*YgVI#UW8R zTVU*lb;t+qmmzlybVlTO+3xfC`#ETw`WmKTD1*J-83R2Ldat-7_RG965F>{dv?$)a zG0nug5@JxH%>$89oad7z1s<4JUKUu0K}|V}>{dHg<@rVz{d@ zP(E%r);L^PC7dWcN;q4{N=E$?gr^F>C0sAOT6nW?lki^Q&xB73Hw#}9{!YkABHZ5* zLO(`&q4?{BHxqGltT!f#o5drFw=qz}zbw5siHP4O{Hx?23+a){H`xE(6;UU7I!qLKU z!a2hELaR4O&u0hioGY|3bMV)S-zfZ!@VmlCgii=LZbLi27QQX46MiWCNXX$E>NgR# z67D7Bcn;(Jcf#nxM1FrEhjPeI7IHL({B)s>*@L%kCa~U^J$R1eP~Yk+Ft@(q5%sxa zxjP@L?e|ZO)%F`Ou)mwlx$AXAiuo`^lY{LUzLn%UBI~xMR&L&!w{qRq`~}MPnXW|=7kF9(V-&|US??Qdvd`*tqE@7FN?L@d57_u@ggfKT?+&0a6 z8>Ws!6c!!{$;E7ak@{;!HfBU3zdhAb$!EEPR6ff*J3`Ad7H2ijtQq+j)xy+krk&sz zALeV?1&~U#fI(Z%1YcUZ5;0ga@~!Nek?&}EN4I9=yW-rMkz2)S&B(fXYexQAk#5b% z_r$q1Be#i5@3>|p2euRM=kaFRIOMWUA>SQgH5zPOGjcIFt~YWBiEu&_&QuM{Rw6c> z7!>^n%}&huY|_pakgPx9uqZPru%W>pmO(T`dA5pUfnDRfIhpOhXYSh0o$aiZ;AXqy z_`m3Kk`D&q9`pO)qx1M6eUCoAUzzD>nIrz!&pew` z+rX4F8$zi+sYZv`5=$3y0W*ZUp>qx#OcTx&&J!*dTCV|mXNk9dEqGod zOmB0+fH#Q$j_^&P%>_gJ&eoaaBJi|>OX73;iG!$zn-{Ous4pKM=d7WYo? zYVDCe0|yRv9mQSu6R+-!okjYI?J%OX-&^mE7@JB|wyX@^DbF9h`GLxHmE9}HzZVov z-JZBAKJTKBdw%en?Lqp&k9)rV!p9{aU-WUu56ZSD4($F(!TX~=Y4g$EW5WF#y&aDa zeY<4nILQC-T=&X!W#7tJr_cWOkIx3fR;*Ls%EUX5CdsEOuW#G$qu9x*($bIe7N+`@ zew3*CW>ET3tmpFJ=%CZ~f|IL*^!B`k>FtTC^!8ZKTPogo?*2F5JCjztJ=%tB1o)o@ zSQ_TD&%Wp}jKVQ={|`BaaNn9AHmOWhwyzA&>b&{R4_AG&`R3HG(%t)P9{zG!_a>WH zb?>?P{GZg^kC?@In>)RH=ZC@KPSl(J!E@azXUz+(e1cwEH+QT2_SqZf-T!7y8B2(k z+HYiO{><`8Vjs|D<+<3bKL83d)*^lu*P~3eiC9&jZ zl+dFy-ebB+@_SHHgmm#k_&~yJFFteQzv55%=_bkF6FL}6m_ja^+g@PB2Pg^Etzm4JoD)H<>VTr|mAm@5v`m zg9vlL?j&#)6y|_E4mvNv+hktiKG6Ba$pcdhz@{im9+aXG6T(tGkgMdu78UE1NUfud zLsHA2gc)He4h$sAq+AGFH4xx?k~Dh~Nt#J^;7@s~vxzz4+GrJi3ckx-+!YU>2gd0P z+Soir?}}3Z8lIw#F0`+)Z!&pMa3+(zqGU-Nj!X7RB$=aKvR9R?hRLo=xV>?B)g`+w zk=>i4U9ycP4+>63zG81H+0sn1wm^%7mPE{T(Ls z3N84S;Xap;R{#^0G2wk(XuD_d-pI*$pBO?W4VT1-RSHY_hxr5+SdF9~p~lz_GtK7Rruof@c3-yb2sUm@F=X zypYvx?4O8=CNZAo=GnQ9FqmT!D zFphsOyBrFPUk1LNzaCn%eA|TONMkkaeneVLdk%!nHMLsyM{rm~rQQY6Eo z;!M@QBGQl`WxXq6@9>9A$xDLKc1iSO%6gXsi$VMJH9qVR{@L%dk|}vje1j>yhUIo4 zBuL4-w6F5vK4Eueay?|{GUXW{u4PKE(c&6N?sO@6qxN+^>>AEy$|oRWMJ%}w#Q$ST zuhHT~NO%%-RlI@7vyjAB*#@r)D&4VzQl?sGt_tcsnbnJ26^!w_`24G)J+F#yps3up zDc?pyyQcO=1)TOR$UCALvNvz$hqJ=m39jfgra9s!B>8~sM##e>$)1khPSdI&oX)GK zc_EIu5(G=8Mj7hEs~Q(?dMYBq0wiB+F%yu>i9xI7kn)*yr4v%K)mq9>ir>r1I&f$H z7`@4$V_3nA^$0^obz*iqF(X+DDnEiC>=W9qvk_S;=p1gP%Ahdp)SedDMCrt~421uZ zwbcEah5YDRe7Rr3+9%-0tgzxFvT8VeAAH%bbz{eqHXcO;o zbei~xnZs4Px`-%mnwinvON*Gzw6TRs?=DJUpdd3$xZNhOzP9*T)y*BCHx5=EGiY*o_ zJ(ak|(aVXn6b6Uk*8){nV8c=#G2%InUP*MSQ$SgWs3xfTEo?}3GSR8BLuMhOnn%@j z*r0mqg+QlTZF=}=kF7H{L>pRTFS~#Tqxc|<;ed#I%tWT+^GW9nP6K6u2FtL8!8eS@ z4--wrmc%(K%NBhZL@segvjCzt*su$Ni=9efg@N>+sW&vn(nH11TG;h9kgaZqF%L(Y zg`;TU9wQGUxC%SL*Qx@mRo3#$)GQVRQ?X70EKoKW8%x^<7I6cmo|}|vF6pU0WkY9# zCn?7oPf`QtEk}!N1vWS(5GG(_?E+Zfu9>CKMhi2dG81LapFh))Dne0CLW*({Lh|)Z z550*@P07~6uWx#&8>ot3-}J&@*AL6DZ+g6yxX}*YXCikZ-Ut7qZ+erFLA3gciF{tN z1xUP4azG~VaexOKp_`GD2?skVfkx2I^R`?&kJk9)K}y03r$bm}afUg201t5u~oeh7<%Ihl?QP@{?&4L1K*|JPV`wnPmB?K%^d$ zK0lKzKj=F$g1}tR`lJn{&TtU~pPxw^NNscx1fQQt8?yPC1i1wkt1F+0-9Qevt`O=`}dNwams>!k(1&j zVHj`TD}G!$-l$i+pcme^#PhKBnqmCBydfCmgDCzX{TGcoH_w#f-D-`U3Xeu3R;~0J zb@)g*)BHT}albmjNoJ=lqMgAgqmS+tKPWxV$VS%^4$A!WB-M#OMs*<7owT&F!oL=z*|DA{T8fG1~OCQuR-ZC9;emf5S#(3e>-Usa$pV}*4bo-bt@uDGP z;zy=${6@Sm9bY&E%V30|bAKE>U31cGK3ct*beWgnnf2}IW}1;MnR)d575!(O*w?&I zF}KYe8_i5+l3R3D`{~msjXkt{Sat@Sb6AB3n=e~5FaTnEjni`lbSDJPz z{!f2V!aRWc^~KdNd-0sPbFA8U5&ko)7PeqT)4)GvaGucV59WX0rkV?_biq(j{{i_R6elXphtE3F7Iq8Kyf^ zh@Qa)6f^0Mo-=FNF}N|!T^#gs^vqeaaQ}(UU;PjD48}M%&IR8W_nasmHJ!Th!jWu-6ST=8yUE_SS=D{(M-0g6+Z% zw}Ov54}8>K3lzW|$QbQW-P^kcv`+&vxCR&chY^7%xfYkFsdpi+=_8@*gO9rng6Mu9 z>5HM?CT_og%zhsL?bFc4pV7kSx%9!uaiBA5Z*o}>q#@&RG{xqR<2lei4ai_`C`5aQ zKJID6MeWs=x!x%4HN)oZ{Q)Wy6xxAbi70urb(7POIec*90#Gw?;-=}3R56oXHZ2ovT9|qZ} zfyly;PP;dkcNz3LM>66`qQB;8uyc2}K3-eUEFbQ-7#s5zDTW|{dVdpSK6rbc_ZXG` zD}0=pmuyJbxqC1p@TKVlaopwV>*wX@^A3;=aa_Um^?5~SL)@;&C?C17AdUyTaghziSoGdtV94<02mkw0vcnK6oD1Ta&VZ$L&s=Q5hrI$8+@Q+hDp}1>ak?##&Af zz|B)Gz+~qI$T#s;A@5V|!A~QPi_7AH77w&|V1@KKVpPz^jT05%g4n2Z9I|TP&OJvt zznC>4hLguLOx#0=T?H`+yAVtCf(-F}6o0UAsBnVtP~j}$F~VBmi9(()?(aO|#X{zj z@|%Ts3HcU^@+X8Z2)78|5Y`Dl6n-j1$J^4I|1j+I5`U1eN@#w;h(AsI#t4-Ve^y@9t${*v$yLi%!W-glkweIgz}oN7mVdANy@Z%hQg zhxj()JB#llJVZEFXfrvHe!lnx;$IhjAo-`l5XZpdND47s#PYwV_;$jck`E9bAo;<<5t5G+ zzf^dYaFg&4M4Yd;iMajO3EwB8+&)!2C)im%BC;NdZzH~o_J( z&Ut`5{&|uw6fTo|mH0KnizUBCxKZ+(gx{C^9`O$dpOO6k315|bi|{SU{~~_7klyCZ zUo&A#BDOZdPLlT$-&a^6`555@$tMesl>BJ%XAAEX{#^JG5$B5yC;HhWgefBO)kfG& zxE~SvgTxOJ&)I_1pCp`0guUa1X9}+peqZ<)5%%5^78W=jIdbb;dRy zk?lWXPhqKWknliZg|Jd+&o89o^O5Nf7fu(>74o^u_>+aJgl7uR6<#8|LU^6<2I1X8 zKDTM_A>pIKr-Yk@uLyr5{G;$K;d{cr2tN^iCgjv|?q?5STVYz*RY;Et>h%{67M2Nz z3AuzV^~MXQ2&V}-d7bf`MoTIY<=uq#ya(T3JSW{V z-me!kUi>7XtrvrMTT2_rdHK{|BD6KM!JjIgQ}r3o`Lje@HwMT_v*bB{op^_k)Az|g zEad!s^1l>v5;^&;LTgumXXl9We4({3z?X<`DQqX~AnYdWDeNa4B&1IO?OOW-I9dEu zA=f%%{A}R@;UeKGp|ww-cdqyggqI4h6n3=|ei;x}&C<0>)n{q(1@q z?+WQnK>k4?{RhauAfy`s`9BFcGoR0qkA&7f0dMUSU=!#vzL~Itu#3>zDTpr>KS+3> zaJX=kaDs5M@NnUDA>9DDzh%Ocg{y?;2+tQ@BINfqn2v4(#P1957TzO#NcgDmS>X%9 zSA@S2{!#dr@IB#Qgw}4t{tDPG0X7p_`w4to@o8aq;eNsa!u^G1!ePQO!tp|SK5#$B z2p0*L2u~EABIKHT)IU#nvG8)?2I2KWx>8X8Ug5*S$A!-dUl7vQg8F|F)(PJiek}Zl zkj@y?ZzkMR*iP6**j-3(4eAdO4ikl82kosDo-e#mNM{Ge z-zeN9{IQTeAB_KnknRTLe=nrd2l)?$p9(pcN_oDpv9Ltw+jH&2cMx_H_7u{Igmx-~ zql9CHzFjv}{B$8*Czy^-C&UwltAuNW=L#WJ5Kj=EB&5#?!V)1pJ{Z4`a6e%m z;b7qq;ZWfS;W!~bj7U322xkb75gsdCB3v#!MR=Ol>s`$OS< z!Uu(q3x6SeUieGl7UAncI=Rr^--Q1VQpT-NSS)NM+)LO+*j-pE>@Pf6SRouG94kCb zc(`zuaIUaMSSzF#4)b-U@O2kgvvV5#)_3kOR+L|8_|eufFl)sA=0*buTEhxitZ$DpR~ zADTY+k(6UUwTfRsgnnj(7jqDHYn_F@gZ3YoX4v&Q3s3Q2(d6PW@$H+|Sr|Vib>1C$ zm6ujFTAzPm>Z0Jii&p&_1FwxQ&3h+aSa8wI%BSB7&YrS;Kq*#V7=6U{0cl|4tBUil zzOeW=+Y>dDw+~oVv@KP1b?d9zq)JnLDz^_Pd*YM$Z4R+7HRF_Pg1u%y}j^`*WL+Y8$k z51hO`)pKev8In;!bx^szMd9JWFvJXld>Ev+W9^3~cVMN53))uhsr4TkUDcs7|4L`u z;>L501FZjGWxG04vge^>^DBcc7h_e6c;kYL8m~L5a+)jIvcplbh1*hv`Bz+3d|`2F z(8TQnwxk9gu|3f?Tz>`1cJ%fE#fO1w%iQ)H|2CeG9WE?>=973BUmtrX75~{gsQ_hJ z5p>AAD7-4Reih0u==9(xMV*ot5);;&?q0#15Iu-$e2=>fFVUw7*`5GA(kL8<`^=z zkOHGFA~$~~mQ^7461f$%k);y~PxRab?7qq6_;KqhoI-Xy(l~Y<*g|@vU&-UT-Z=R1 z8uu8uqPL;i3lF`s!8E0dep9&Up8%3x#7*I(yBta%OKHX74O`1&J$KOj33&t+H6 z&(fuLBFfa2^JW&&2C`Pp&#|0;2bSgh0^>R%CCk|uzJ;-JevwfeyRdRLj&Dw^oL^#T z!NoSPayD)pI9JZbolwa$X4~ z)($H1O;bZkuAEo0oH@uzRla9v^?g0qLVA6(VEf@_R8$Fqr~DOVvJWfNGK|zs<$h}s z^Pa^xukRvMwSZSs!g6n#MQb5jk3HgBN;poFHNOcme}vv-&?4lxD!slLwFj%n9?VFV zf=U;ZKE1xV>uf}pf=YL!q1X3?RIwl4XZGMt1NQ=2{8#&bJ0I^<)D65*6RZ(*K;r}9 z0?l3){J(Qnug$xx!rYbV22RDs&UKoO;1Sp7CiPvqi@fJE-JqLB+_8%zF48#P_5G(y zB9Tnk+*?6QHJUHyKfQ9?tLo~dw2+rL4$;9C%oqq7-3p#Ef!vu}sg91^-pdI?*c=aXYh$N=!N0s{FoCw<=Gf7dBRTVx^BDFSWvl%popPr3S3vPKQ)XM#0<+7T72MMZ)!1Ue$ylM#C5{K{ zZ)c<20&h9o2?~e6t28fIS?{tyoKz-Kg;$9#3z9B7JH0F>!#*m~*Y1=k2j}X@`+XTU zoN&TaY%YQnPdy?CD>4zJR=WtoS(yk@*I`2n!Y$aGDN^i6MJg3I8@s}Z?hLXUHtPN# zb*DT6HIreSkcANqpBHa4#)2+L8QVSg$p0R1$Q>Lx>klWId*l~g#vlHW1LG^w>1uiw zKE$8?{K2~Zx%6HXbm321{_Mw}3H;fcKjy~Rk5mu-9Lb;V{Mm;;GG{K0ohdLASP(K1 zH<>v+npdQm9m9w$WuBAf^;pUXQ?4QvU*sGSiw(?8GJf2UcVyWZf&XUX(`J zezV?|Mn&8!kM9*P=@nlvx+>mcE*%MD5g*IvRA$4tgB{9jIHgujgEAQ?CuQYiyS2lx za7!_K__G1>mL5Mi>hg>>;<(%3R zYvwq=*ol;qb#*+_hRs0A0WuiVb;BJ|{G@|FX0YzRpCjQzl z6X#hC$^VgGrf+q!{&38Ip(i#>(a41RIt4)*++NtI!!3o4JuK!S4;#ZeFcW;HzkQF~iryXTkrDeSTH!2B^^-rjoI16a5kgRh(m=Y!8G{b{24>)bgA zWX7F(wo{HK#x=#?KA)~#f*u1^xK>IWxgFFnXrb#IHxTnEK?X7`5 z&M~09X4t&FKY;dWKnDB3-m@q_AAH7iRXr0XcL;(9A#4i?M~%4OVr(qCsJ#}Q{xkeCk*!Q<$PY6U3F7~f-zD#z zpXYbUXL$+kj&mXf!1K5k8=`DDWEXyy*3`;=|0UP&5|6_Mn@N05?xI=NV7lnzHMjFxJt<91mzbCnNRXJ3-1z|-zDTvh<`!2MfirWPWYklQ(=hmpCz;_nuJulPsB|6Kfw;(sTs6MiZzh&g-a?*Y5} zi0?tf{s)LZK>RTA)xsG{C!U7`p%Q+{E=hETi zJBi;!1us4Zv;Bq0Vos~C|8QOJ*INqyx9{7wV@_9t;BJ3{gBOD;K>kWDp;_Z3^KTbT~ z3ee6h;e6q7!dl@9;VR)8;km*KgqI4h6y7epL--@%y~2luj|-m>J}=~bi~0MF(5_SP z?~DIP_;+EF*9GDm3Hc6!JlhGxw!*ZqRLJ`wFBUu=^2!-Slv!*s_AR|roQ z+I;}=mx-@;AAtN;$-gK3q3|cdhlF-tfIescaDOig?Y;p1kK#EgiSh3VbN$2;x}Hm)yi|33Z?r*X%*H3JLnqNA2^A`h} ze>%_>Ndz7wy>cOEA~F4;!Xtz;gvSVv6)qK;KReQ$Dt@)_Y~guAPHm$7>xH)pzbCv~ zX!k?tJtY27p}#LaC!TYoXz!20cZKFp2KjdJp9;;d407`;12*OT4QPJxKu)hB-&JV- zW#IdXKR{^yW{_8kA1&mJET%t7c&u=-kaM&cZ+`K>_2MrPUL&;oG~#a&f4gv#@W(>) zkB6T5#{*xK{8z%?3jZK{SID_a%*Wq^p9ncmjPj2;UICBQ$?B=>JtbW;R&*gpkwhXs?y9y|AOOr?6BwNNDQ{Al-2BqlD&{ z2D$mA0gsY=mTU^HSp`iUo7N2K}OBg&zt3E;K(j*fBpgp!u-@&5sS3##j*Z$B8*aPE{lh5}F?y_zLmn z#|GZ~*nsB81~fl5p!u-@&5sSZKk>?rJ?l4tzg%{D_Zu)M9SOVoKIi@eOG};l zuKh+$yrf_w9)#A-9U;Y8U)_BzB0l-y@yKDxxxa7I-{8^{c`=;JiGh%R;-c`M! z+dD^h{9k@Ir$<#!#PrOG!M?uvTkPf4W&2chMSRzs_|h(&syaj7IY-{2OS-B9_jRPqPpQu${9vVH(;QO67T)5ba791cMCYFbB}&Y9b?XkH|;loR-=_53yKp*rr3IK+y+01=_v}~572lr z6V0$F_yaU%2O=>u^|8gK8V?~mOUi{X%Z`2{+QvnQsM#s@GzwZL?oC}m<1D7c{i!LS zX?#14KcM8rjX%RtBz~Iu3zTA=S_Jv*B_tk9%>opLAK*7Ew*sK)qrozS{{YbhbFV8% zybDPYk02b%17J6xDfbx;XN#V(O^?Jr!x1dUCfFUa%#5WH%u+Ek-Uf=zc&_%wm-+z7 zer)82VI!U&(-`744hc#+AX&2iD5ufWYaHb@z8RFf3OYG}z8$bJ&TFjl8lMFv-=fAq zE(HON8n3}7esksn-$O0wg-j<0-QiR&^eSxSJC%4)@(!5f;1`?<$0aPUToA&k%b+BV8)*_)}VXF3UwsRW~BL2?os@<_!)DB+?a$;oFp33FW1pQ#SL%t@HRlAqJ^ zlJubBjSuv|#N8Om-(8fDMx+ zQ$*gMI3t)?B{^||6X!`zT;=E#akZljuXA*YxY5yuKbD+$kL1M7k`ryb2Kga! zjG6f)zUyd*sIHX9fV|5w|IsiQ4CX5ncvzf&IAH@R-mMTp;BmPKQb)T80uRhZkUG^x z5O{4rnD8fwi99@r3IC9o$U}n|l!dnVjTx120{l`X8lt?7`VFfZ8J+pD?6%hxmeYyp@yeXR3Qr zcvL#x$q758pB&c<(>2odp=~iF^`qUTpDec?8{`A2~oURs4hYvWwc!hl-Vbr3d z=d7^rM$k}s_1NiS%O{VVKIzb*Lx)eA6q&bHZ}M9M$@>l%7}4e~qjSqLlh300=v&%< za6>uS)dwv!b24fQB~vehw!eCksJ0cH6;uQBGFk4?s<^av=AzkiSRKF6^ubJ#P98pK z^7P8`QB{Xl4{zwGVLx}*?kZ^bLl-+74^P03LKbl*3su9%jljtrUR^!DdPiMkz|CyU z=ua9oZp5Kg<@I&@^o>{?S3YjkxXNtV+l0pK=P@#t%Bx2lI(GQD$qnp#VE=kqVKw|p zeLW*nMw3QO8$NyPs7bg0hmOpAH>0|;a&kk}#j3BJFPmu^J@c#y4P2op=*+}ZRO;Gg zOY0T9yC`sSSql~4fEAwpoljMbUO1V1crmDS3W8lj}c!b953{8k3N2kC1>Ms=A4`;8qG+E}lZNv7lj$zPi>50eT zaR;nj;&7g)_%#lEM`LE~%%In-rTBEEzc*ee->zO&jzIoOak`y*{t1X}!)(c** z6jIW8iltt(P3K#FJt4=?Z6=hpbB%3G-?6p|^|-%@*t~6!!R25c_C_LcV?jsl@e6TN z(cGau=Ed7%=RIoga76wcG9P^0VhB9VxTzQld)*&=B<@(y(fv+MJKuipmvX<~Q$a`V z4MBGps+r*9RzecBH?j+cARwbXB+1xY589^z861H~>iOW~&VwLoZ)(IIMhPtd;NRgXg}uxqe1=&gJPP4bP=~ zT>1bDe}UdY&j5Xuco=jve>IWg#qdbxcwYpK(^&(sFaweMdj{ys0@GD8b)L~zK<{-D z3SN&GDXw5%Yt&~50GTyA*&(7hm$>BHU@Q>v1ujKICa`-S(hq=F5|iS9UuwUjuJ1`?v<7)_YN zT0+;$YN+oUO_|%Nwxm`74eb>L7){Iqjq;Y5$M5bju@-n{p#E^Jzd~Y5TmwWrL~QOF zZknyh@2NR#xLKvi<6haBh=HVTMBFrb67j6(o4DBCS_?hxmRgB*&>XjpfvsnPmsPU9o+kwiQjs)+kwERBdp&SYXYJnxC!weAQ8FK3YN;o1^>7tJiyoXqT!A9Y8 zM5O<<_$}h!7XN4QHs=rN_QL&#`Zi||I9Gl@doHy`8#oOFA z@HUqXc%tOz3T=)qcg;w7XKUw@#;SAx?!iB;b;R@l&!Zkvxhp@L!{Kdkn zh1Ush5#BD`B(!>o^bd-EMEI0&v+!5KSB38i-xK~#_=%8jtXU2_n;UEO81d*hnjTlY zqrTN^;2`k_3M+(Mt%iDbzX00(0(iLO(}nYe#|dkNd>hX6tA%TY=Ly#fuM%z$-X!#M zXg7)fu@EmN&F;g(+_|%M{b0YZEB;;Kd%{nIp9%ALeL$b@iisscwpGb@5Oxvr4Kn4W z!ofnmW~Y3FaE!28$W_!B&zJ4QS;FIl#|u{oPZq8bo+Z3Uc$v_?;RJgd#osFQb8LSi z{(j*j!Y72Ag)a(!EBu4d?jNvUC!X))ng5T4c3%PCjQ0f~U&a&L32m+|c$;erES0>! z@Ic`q!V$tT!fK)U6d?Uk;%5ox3y%{n6WaX?`m4mR5q?X!PRQ5y%xDN9Z4NHt z?-FlwaKZDXKGWG8T;P-9Z4NH@m&CJ2!8Lu0b-e;CT|ziX^{@qbD7BWncfY~?B2%~0 zyPCVzXW*d0{Vl<+=WeCDU?&)I>Tl2u{(-H7noZAb4OZS=7c5x6HC!2PD^8wJck{}; zvj)}WuN*qRru`jtm7`>1N=R;<(q)SWpx zZ(AyFZe7>WC)CZEwh#8(AMyLtB^I!>PpIpH(mwYTAD`BV7jtHwApT;`# z*Sg>Umi@f;%jUE6A42~Aw6bemC)A7UGbO*}2dVv$=UDN8!eKa;@ZznpmEquOj6BH+PdWEF39D8x?$6n*FC&opSsS- zT@rQX2IxPAy7fofEB9WGT!vc{s3)bB<&`XF^NwbonSYB+Kc(qf<5~9y(HUAAjvy+JU!ppSPcd{x4V5R;il{*ehFcc&J~z1 zho(GMv3${f*>=d^h##z`zl$0GuzE zWD5!N<>uE$y5bj6)!kZawWRqiqu=jVtHmNFgGK{&wepwBE%at+vl zCgiHAqWWeiyw5cmN{eOElxZ+ztj3sd=2=;lJ-3Q`r5|4u5 zl*?wD@xwB0_G|nsBJn5uu;J8#6JOK=>f1_}OA*a+9vmLUG#4r&2&{6SN5I+LZjGu=Zh(~%eP7s_zVj&1R z_cf!355Ef3jIKSKNU(iTM}m{K55m*G*|$N=CviK7OGx|(#1BdQ3|gCq;%yKolK23`oglE1U_Q<^?p*lA(s20Y2mQkBNZ%Z%XSiKNakM#_~pACczrKo&;;~lO$M!KP15# z+@TNzYw%bStie~1U=4nj1Z(hzBv^y@!kyY`a5)GZ2~YX+AlNAhCxrK)r0n#bglIeA zeL>VE3ay2{uoH?%%4euXZ~gqJoAr};F*7m1kZf0rXYCcuOz`U|2zqv`G1h$ znQxC)o}Kx=BzWeJAi*nx*6qrq|tHb05)l)}3~+n_?ugv&JKn5al#^o|o1`wi_tbC93l&8{3=}{lCGBN&cTLs5jKM z7g#IUo$YU}OE-?FbS;>MA&qSyHs*)O@-4)1{58?temZVg0*OxLD3BJ?_#J``sm2kN zs+Otv)6uHqrA}ikk^3zSj&G6GfWQJvZ#A}5@Zp&5ACBtYegiq}afGShhgvKzXpMGS z!~4q1Nss6fH7wt=(S`$*Y2*jTv!u?!AQjtiXm9n+Z2zvz45I7I+=4 z#)hIBL)>U|P3F>=3;q@t&kR^#NzksF#N5IkRwJ9;-6F43DpS1y0|}R}+U$)XCnc|zJY3aFvG6--8b~=FyCYYPEgrx&31=>HXJ`u{bHF36fZTGV{_LFuSRk@U74%V+sj@rw0a>n9wCu?D30!--u1%t zJa(6!dm(o|Hl!a<J&`~wVKABSrjZi~DYIY;niqn^ z)mpQGgg00Js%I5Oi-F+GO(i7EMm53ZZE7}e6Qg;n&YWhXvf)rXi(AVWGe2nq?X5C< zlL$T=lQJn&Q1~|$7_X9n*zn~60xNnvSdp*?^DM`tHjr3{tua>gt_|Aa>P3@?f{W`3 zaT}xHiF(3FgNXZbMK~Fh1&YeB;oK6eWO@I|96B>K&lC~_*jG8R!O_EMSBXg1t#W>P+bWwzBXI-Xtu4eGIvF=G<%P2AZ02z z0qre3aO~98z#dwjsSPAt@|tXGi&=F?SR1gQ&ccQx98Fwj^wJeXceL4NXe3>N>25IH zb>oQA&6G?;*Y?4ZWGNDzF1v~@M0CyWbr3^$3{ko*Kw6+~6*k0=C-OLOj}35-wV#d~ zxQ9*BAkso1I;PNA$_7`qxlUVCoaQ*9Y$a%mKOL=dvxZ`CBLNmJ#_!eGaCfZg{^5As z9mz>6^DLki%LQ6vofbK1jRR?cTDN0!wnoAhIcf3mEKutXY|a+7$f+YXprzkq!`+Oq9hx^VJK2DcEo>tB6aC&h{k+fUoF9y`6#heqp?IdceLT;!AtQi_`IWy}HE@PRFNA9dlss{rLTWFuo^0uMoytI+&j( z$L}wMb)|&d)Z~_8MC?5Z|2W-4{Ot z_QP@P*Bb{G-#cB;*yFLVwEe+-;*E#I>rNTcr!P$GPzZ-HY3p9`R`?i1dQ8^-xc=Sy z_UPTm+3pwL5~kyKo!Sc-i?2+_o1~d1@$iDse+qWO~T+rzZRL16#>`?ru5rxEcYcpkwC9HxBbCzsO?x$IV$1HBs-g z3N_;~n1uP2JM+HFxbvBN7!_xm$0)M0qr2ZO9sB6dCr3iJgugzvVBV6hkiOF2S;&+& zT{$y_UC$TQN`1$o_g_YcICAaQcM!79Y*`1w-TaJ!|02gRi{>1iw(9YvyNTgpTHjBs zZRAPA2TgfV;hOjvv9)1r+GBJPi^lT-RPOx9Vv`w((2YL|d~j71wO*5VMsjW9%=lUO zvO(;@XP$W63_+)SFn<2+eq(ebgMV4Qn?NrU=3Lf0^DyHz_h0`Z0XKxeW}^%Jg&tfZ z1n(vxV0#0v=`7^x`L;+`#HO(AO0Oq$m?pYk-++M_LpUy!1EPBGf@l5m!Rt+fAgXsc zm}mpZ>#-Nt$R`F)=)v(Zytl%}yikw%UyhCTd`RPfdgXgA8@B|asJ$7mcR7sE9_@I0 zt3gNYjVr)fQ4xVBFV4|>x-puQoS3fQ_11xp?st1{2%yLPB1vYy*Ms(HKnB0Xg<48N z!N;+8QO{mk5TqfaJ-%S}$8k4kp9W;m6!Z4eBoutyUErhkT9>>1(jMLtXY4%z+NS{- z^oBjo*jJ79&F2AR zFr$-OiGwr)_sj4mwrKulAb-pQ^GAOIpTCblqbk(^EW8SP`+ElH_r+s^UMB3(8TNf7 zq@E;34lkJ6JqWIYunpubv2nk}*qFDdz3uzDHT592;O%+dV^sdH@Ks}3WP>j~Cy8T# zt$sYFV?+Xd*XqanyN6HDD=r)281aaPFXGEqKYeqnb1Y96>gR^OYtax7T0~ite=7~y zy0IDhw&66`x#T^q1jo<1z%u8(i|hW60qukBw|Dd$ zTvwkX)?8PgCHqCz%kRf@sJwiH6Nd|{gcF4}x`_BW;ui={5S}VLLwJ$!a^dyD?+Nb} z{!I9!aI^3w;U~fZ94GU~$%4dg!lA;c!efLS8KK@cHNV<2c3%R|sRcG-G()m(z7i1^{cal*rdGlcVne%<<$#B*6U z?uSdT5jjnb$W_&dwk|Tzd~JaDNd6EJ$MGZ)H@l~W&nf|h&itj;$-QGf5=NRcmDxTkKryb6nquw;(Y{_k%W5h2Lf2#0I;X0wMa}2$W;%^gj z;vMbZFMLe+tngPtTi+OZZ;Stsi2QscY=jG&c1nbM3DZRAbr$X?`9R?z!jVE-#~5~| ziMREO!7miQOn9o$)+x3T)KN8w~3wlMo-vC<*IeJT;BgVvigdBV&-&a^6O7WNY!C_F?sLg;;)4i|4eh_G{v_+y1jg`5b^{d`k+x{%Y8DZfm( zL3q9JHsSY$KN8+6WLuc&pB38uAN;Sy|3UbM@Xx{zgq#e`^!Y;jUI6&!;=2gD3pr<+ z`UeSz3r7hL7fu(NFD3Mk70;>GOnT#kr@eSdJ z!jFWUzs>k2!o7rh3vE4r#P<--+0cBhjTIg$T(+0EN@&k1@b-KH za(z(7e_ME?kh7~PzgPG(;bX#Qg)azS6>br}CEO}R6VdD?g!Y_*{k_C<5;ymEfUsOR zTxicH#M|=;I7{-mLQeT+`jtY?{3h?$pYzCR z|9zo7r@;SRygjeLH{o*tXwNI)-r~CndkQ%noqFZMQ9@gPAM!)Re?vH5c%0ClThKdE z{At27gqH~I`2{^&Umtj*KQQ=F%mxXT$w+cTLek8PY^I_lC%?EbD#^dWQ zhNt`~0*Zx*+Tv@)Rn2gF~BkBLu-&xx;yuZeGq?~3n>AB(hFp#E>g zAi|W}h#kcf#O`8GkyZ}OKU_RR93_^E6U1}H8R9%~p}1766)zSq6KOcX`WnS1@iy^p z@n_=0;xEPL#h1nR#DgO3F{uA9BF!==cM!XZCy6xDV0xigES@gXc7y3t#q-5kVwJd9 ztQS{_Ys9r8O+ct`i@069Q@me%Nc@%fg!r8JqDV^;>iakGL-COKh4?4Y!^=PBPZ4Q= zLb;pROYA4+iACaR;z*HpD=dGuc!4-aTqf3umx^mdn!B+4jpD81PsE>!KNo)?{;NnU z8J6dJQ1T7&ZSfD{2O^DWnD0MD7ylqo4vKBX_9AU=nBGUs5%a}U#nVKZ<}m+c@jUSY zahX^rULvj*Y0<;-w~BX(KNWu^J|WWZhxvai{z3deq&*PR|5HrC|5%ja2;7inLX=My zbHsd+)M4A&Z|7!7SalP0m-Yjkx?-YM7J|I3NJ}15{zAMsdiS>OW z(hmpaWU;N-Ud$G|i!^p({vz=Q;u&H@EEgw>(?yy_vHXQ%t+-O8#T3)86C1^wMH*5u z{b%As;=hQruVVU(;_Kpmk!Dv+ZxO!~TgAVK9$u<5U%Hqnb`?(&X}!gK1>&jVX=0f; zMw}*|D=rYL#Z}^^;#K0cB8|jY-)-U!ai{p8_=xzpxJRUI8Oy&Zz9$|O4~bEcCTPr0 zKLcc{m?6?KjqyE28mLhoCY~;qinLo}`fQPN5-D?f5=kpIa-DdS*d)@pjp_G^kBPg* zz2ZwEZQz*yGx1xI?>-oh$HIT=Iy}B_l=u1nG@j9Db;x@7=9=s7`0rDSBo8N%Z<=KD zz6AM)6y;gh48}i0`1^f1oKjd|vwpuXhfmQaY%yOB?eOdLxNh#CEl(JK1K!4NTSE`D z2G%^#nzSKxU4CoQOKZxmC`&3^TlRLVQ?tL-nccbSomQvhd4%>N=A~9=Qm5H(w+4_F zm^~e70i*?x7C>5H(zMy3eD?=$yb4=-ujb6ZU6XSdD<~a4uZ?pUUQiCtNdH?kQtQ7- z>t^$MH9N;(y<_Y~}p9 zD;CaLylCnCzyH_%Ikj_^E}ReNv~Y)E-p#jo0692DI68 z^xfa(zw|SRW{4o%4?F&ai2Vlm*Yf2dk6#8shxxWJpv_Mk3>lYwY`Y!}rG9)(J3Kqw zDVJdP%OL1n58)~XwE1ZxASdeE41Hn5Q6Kxj*Eb$vzYKy-dvru62DJHU{C&v}GpRrF zg&EMswsGUUfy8?G{u#GiQ!nHFdY2%KS57s6*~UO$A723dy7-D3`C{7=S$dwa%t`N7YRI$L4U&akGBAx#oB5 z24DP+zGNpCX?O(Hme`}z@AtM%_KbEvFVm0BpJvwG_H$&SzA^~ail9u_lgHeBX2ErM z-ghD~?JdvgUHP4O{N{OVd3ac~mIF}FF~{#g9us}pu`h6gwBL(8XyUFgxd$W=@T$I&5(z7h>@H4@*!%qh$ zWu+b7ljN2K3epbmcG3<%=?3zO zaNrwA>41DI;bEseeB`W%UXu;~N9DEfb2JpbZdOL0t;mO`oq}lPKzQJRFPp2&>Br_2 zc-|S`;+8LuKArtE^e%{ATm2?{;q;5PseYryE#B1Pln;&e&4&M-@)gkq)kC9C7sGo{ zYF+gGhHc2d582rhg0W8+kmqx3ZrX^>!ZC> z=SQ!tsE<~b7e;qOXP@E~@CbB@DYvkp03MzSqR&>>MZ*INqqB?A{?wORoPo8-zZUJO zkIosGAMI8AT#J*MADx%I8|_*dy$iC7e)yoeTiJ@}nHAg0hDK8=PA)qIM_3f?fg`=T zVGWKltL*9)r`T@rP!Vr8KY0>T(O>51m_<+T6Y@yDV)hQhs+{S)1mHvbK##`CX_PF)sv~ah6|5 zM%aBc$nc{n4DU>3cxRht7vIP`7i+)(VFnVpn28@Iop&KK$d?U_qe)O3Nw0?a-^rQ8) z(Yq^N!^o+PR&kU!TojEAJSCc(N`F`d(f-x7(GQ!7qIVChjqboz60WX~epG%+baq4U zXq)mH67`B-!4)?=x^De#Ws9S|*5^k@Bi9|p7}x7hjjl;8jLt#WMckFCFSoeG zx3+i{Inm_x@3tfrFOJ^Xv=&DX-)H7p>J{CQ-3va_-bKDXXi4|7oapVT-O8$?f$W;- zJ*m0TYl<(7_FF$Vnlx|;d}J+--c?Z@?Kv<9*ZUy&3|k8SSas1o#lxfS`eC?cPeqGY z;3$$>-1T|U9;vvV(1UXa;yOdS`r~?Y(F@Ntq@aDce#=iP!r)CaAkJI zr`wQ)tMB9cIyAL8;0606eBem3C%GQCo-nhqDe*?hUdbxS~SZ@bB%EYEYk%#uy3p8EL7JP@j>wFmu|xWyrdf z1z)lv@*44g6_MG9Us@5ZGhztOpD2sw8L^uc(LN*QSrH91Vj0D{MW|>SE8+sl5K)m4 z7h4e(8F7sjQIQchTM-o*@g6IpA|vuQA*ez{M&wUE>7$0DD{ker6W~`BMtys?Pe#Wy zFXP0F>G&UbikpcJgO}^Hw9^rZi&HL#(#GQLOhEC_6#Sd6h+@8X(h__C;W~@E8KMWE z)I>)^X>oyR>2a|e?i#v-F436L>c~5iQr&dUIo})XGS^7^CxixABm|t4<*dT ziguaQbK|LegJ!mLd@={jVF}g?3w)y71g8-Ee-#-Bwi5@q|8j)Q#$%vfG|7*;8UZuq z$k|Xv?!gXA#fjt#*t48VFQv^St)qKh#LpTN?Ago-MP{;)v*FCyIJkA#Q8Gd<#)(IG z)bGGUHe3c}X1fiauV807`JN4r?-|!OhI-9}BeaC9#@@|YNsH=QR^M#}gUd~@+aIUE zM)FeBYTVhPHRL_EHRYU+INP>>y<@hW_O6ai+ugJ$7)-Y!^F=ZA{QSo|?@B zM%3b;Am%}Kvr+Sh*bz5|6RS?g&RR$w1043m8s5{i`7zs0euJBh=Oe?GDrYZTX~U&# zMc5uksj@n(?OE)oVFGE7Vps9}4}>);x}R)mNsD?Kbb2g#H=t*TE6SHlf93T+VniczYVB0A>jH?D6z@!tp|)Uba2mNw|8=xGcB2#*u&P`tE72?|AFu z-DYe28nvR;WBeL<-A%B%jWxMFl8boE=D_WdthYJNq~2~;!vxYERs1x?`;U69uEZ8F zhNeVl!MJ!E<2@WNUj*$luwxv}7+{?2P`VO3%1&nA@lJ`cE?~Y-VIR;bkQ*urK_<+S9wAk&ON#foP5sf z8M$WpH9iuLo9V~xiN{^w$GsAd<39yvdnX3&>#JZ_pFmyNjY*m1lQN$SBj={=YG8TgH^$a`av$Nl*M zB@;J(C;Qur$*f^8N6+8)6VJTj88x-b7S_&L5?-(fOTC8suNppVz>I}USA^@AEn8d{ z#tX~v{3UbeS60rioKci}YPcXTf9Udp8HmqWx@_tE9ImxDW6{!ii&s?6pRr`lyej@` z@lRG;cQJm~$Q@$;#@f2=_HZ+Fb99TyJD< z*z1@(#Mr-k>7n;&5$_GP#`NRDlnP8#fsLAAqKw_Wv70xx^o7h}#DNUu#XgK^${TZg zSfn$_M3@hw2PW=}^%ff#HC`thb)iArULP$rS!*oXThtkty1dRdYMDi*#S#Nk*-%sd zViRGSV3fyO3{!cN!`AG#!z!@HAf3zODoklF)fQY~V6>_+rfZM)0h@f*WsW%Bna8*& z@G`94qYwFSNT*R}{KKP`T4H5e8G7u7B2MKjPNcB zpEk@}6&`Y$*?OEjiHPawrRP;6x_Gr#CVSC2yXfa`P z8WToK*s7|qP#Z2Vl2L3L;+<@h7h0TXV5^yD!tuf3^*tuSw!j{$$>v!tM!V5rbJ%j; z`L+rxnLOSs8>NGm)XhYi^6?L4H43fPm9}hK19M(%v+ckgW=?c3Gn72rn_e$lVupb^ zW444&Ru2LYLd7n~0HYfElLVMK-q`HMUA!BlB&FJyWJq z(~t3xXD?;XX0&DP8M9$^+3|W9E;~#g$oYuwI+ARf(GhQGJaoqCp%1F6@V3!)<8BP% zo)YLy!Frc4%l0NXnlSD-%r9*ELckB;_48{NEWX&RJ#Aea7)8_(ca~tHDwnOmQs>96 z!@MZ&4T~c_eOlF=+RAXw!pe*0)Go*=2J4CgFZ zx-18a-7cDkEQ=S-sav#kAtD#7SURsB73S2^V(7r{-G7u4j;Teh^mcFw%|)0Qn* zV3uv;(&}d|t6a2T(fnGw61C~OqdG|4E&m~ZeWu5Ezu#k?FlwgO&ijX4sQk}+w%|W2 zNBg!|!v_v+e1I#>=)JbhRiUd>u1Q`Oyf(1jyAB>I#$;3mCv^=@&I(RBAvm>5a9Zc! z^iILEI|k3`5Inbi@Vv}mMZ4hn8NnHCgBPR+XQl;brH;xt;CjDF%BU<&o|!x=c}DUD z$rZ`xC!d>qUh>(==Oj-{o}N4Wxv)t$j5q_-LLmjg#9uII(OqubeI8ce%dO?iTd(}*!dFFhbF}I{TN}t z41&&c(3i=8Hb3n;$cg$&67=z!_S^Rpg#9v9@fP&`#y>d;X}2PrsBaSV@i^JO4D7zX zpCe3tdDyw_$i~YQe=tF28uwp{e!f5BKSutz*e+&_Qdv` zn{d1xkmk4VHH0xnYXGway8nGXB~C-WgMJ~Ic8$Cf5YN~9te5A9ZS$`U z1f9Iz*4HV++B60I*Xq>Qp zckU8LZhZ61w@ISRkrUrM^c03m!g%JHi*FvhJS1+O@n#Z_p$`cR57U>tr_g7Fd93>G zm$CH%@mKHen$v{l^IA!2XZ@y-^jbl7CEMD0ZJcM%`x@g5#bR-!7!jw6e6Pd&e1}9X z7VE?Yah>=haf^7Dc(3@7_^9}V_^$Xqi9Y#Q{FH><$LC7_vt-V!WqZ;{q-RRbmVB~g zvu-5P=>voL4vJiXi1L4lX}CBjcNP1IT;PiFqr}Ogu^mP{=K?bQ67gEm*ajp1F3Asx zPm0F&7wPXxJ}myHXl#3t-Wg+@`g@6H{Zq&#k|&C0eL=)8k<6a}SnfKpN&Kn!OYu4J zP4NTqOVO;83O(F-UU;RE=_2nLl(R(hLJe{s$pgd!ahQ09I7&3*4dwVQkosndb4A{B z8NWj0_Z8(e;wJGXk>3MM|B3jZ_=xyx@k#MT@i*d|;_t*y#1`>b8-8BQtS=y%aS7S1 z%L^WB)89k+`iPua!1BYzGeqON1o7slHPF292QN_i9I;AVEY^t^iIk4wK z42bwV$-~7FVwuRFP+0z4kw4f_t`w_8{?y0#deQti19^?)4dP~To48%vB|a=ZChivZ ziZ6-$p@#LnC-M=6va$IGOC?9d3E~vd*!CklQ?jw`N4Q$D@il|+X33oNK>ZJjkBX0r z#&#d!*CoFr9uSS~KEhu~=JX%xOBK6`VbR#^Bi-2SgA)`#MXVI7L{1>0zDvcm;ySTO zyiMF8?i3#s9}zhPiTYj_KNJs%pNn6KoTSA3oy4AEUy*(RnO-1r8WZL5Vud(U3@)n(_-f4 z`_B^)O?g}{hNtR#g#WA1Zq9$+;G?m5Y^K+=WkbH#My(+4l)T|#Zr?vge|$b$5uc-f z5}x|G7H&>U@^!mfodYS6(yEDvW~RG`ZwSpg^j^lqL)UxGXZNqkEX*vxYQ4!=FE;p6 z)~K@SErIICkGL6Uw*<h(CGH2NK2?`Ip+Q5NAKPlX-U~x8|{g?zaLZ#jgG8HZb?R5uxVJdtU6%weUx3+ zl7jiea~lFJ$?NN)^9BZ5f~g%^LgiCXSMTWB;(o9UsEqC?$12AN2e5MO+6u08+$S2q zZ2L-B1l)zTC6yOqesr)Ur6Gv29@;hv<)^eH!mRZE+36@9?E;*>MtwqZ>T!?>+8P^MUr~;h+s|J zzm!CJL>j7+dj0y-WX{1g>*Ugog6Al(?#H`0XFD}g8QO@M!0yI7oWRD)(8#Lv4ShI! z9xM3rJSA^_J!@xo_efUoKo(|`m%omg#XBOfi>Q7s3l<3t+ap-ZnX|sjlQst;DK`cq zm?=Imb%VPF>qDcZ{a{Jq;tbwC@Uh56(S;4cn}$W_HF!67h;C@Y9CKJCJY8}6$tA6! ztt+GdUX5Ak122Nz!$p{FzOBVA9~SLd?QS?FI=UgSWd(ZTz9WH@VVI>}7#)q7>+i$P z;m!)oW3KKL&1|{|b`oQt=LXc*IlAFcS!?KU7cjJWaO5hq)Vp;&VrX+PJ%qXbpXFT< z*b@4|&mwnX*1v<1yxZDodtq5-(QK?R{Bmp2ZmuZ(t0Qh2MrK9okx(kv zN9MZ4E6{rM!@y3^xFY(YS%LX>*ay@_?=I)e_+dDM=-FzHyf#NN+tfzyG;31VML#Oe zIFgldN_1iI9atxOG_C;jQ^TvsyE57*8@-B=(i1(?7d9XfjLK&be`odb=$`DM(b9_1 zEgojXCl7>83g(0#EWWwL$;Qn1fty+a>z88=d1FgpXBV_-IePn?7S3QV&&DkF>fg3_ zO?lC4Qa6FCqI)Zfqsi5IXxk~#=gYf9GhfJyjzt|Q>HqmSlQoDkjcLIC|3z}+H(_QTesdS**{L-&?6SP}HA zz|~aUGnz7RF02RUL{qB6(Q6uJNAFIZ1D!)LFTXar2R1DSQn@xc`vT+f#gZ0x;8SSV zQ!O5@u0P+`=9b`=7oB%8BHY6xVf*T~-%_@%EV$9VrE8hHF&Ur98$nR*&1)auew9J?8Ck9if~T; zzAChub?O^R(;>M;^HLLDM>S$j7gyL^o8lqL=>^bsC<-*mZK=+lRH} zU8h(37OZbx2rHU~Q2wo@xa(tGa;!<;5-{tM{|7CdukbZL@zGrmxJU4xOwXw-RS+sX zf-!qz=_us>djpSY(TvOe~`QD_O*@V@?-vTE~1glfsLrDUi~ia6{(5%}~JnlNSo~LXO}; zq{OTzUWbqzV0%+;$47h}^Pe(Td>wPXjYwF>oG&*L)-fML@%ZbQ^WRCWW1i~rF~$82 z8ewOElJ3Je04{p{8wSb{W9H}o<^V!9*we>5?yEmX;A!k_-#{MswF3wqq)0z>R?L9X zwuq9*c~5Qmq-In3E+U;1{eOD^acd~mU*x#2)Bgb9FQn5v;f+V3jc*guX`W!D2x8Lf zG5g*~$vBksdQ84IQk9XoMEV=-#Qu2xgHo)YZN%9Wm%yC-O(t$J66!G0XGTIDMk>Oy zW%?4-VWd@*7CY`+JY>#S&)9$#EytnIXJ0!kNLda8ml;eV&nBlt zwr903phyS)F5o#G-Je2m&v20je-LN^|BrHO@X-mKe}*{?r$S37T1TAW9zd=I5Idv$ zN4jjxN07Rh{x3DDC3v3iVordSmr?!$E3xw3ls}5ghbZ3xMM}@X^K=)!T$Ie``YwE# zC7I9bUEYby^kvn#{vveSD3|B0#meY7E7M*U={P-B&Zo?CUS^s*+la_L+K9h3A~Hve zNQXz{V}Blbwv~l_BRi z88$EjM>#d{jQ|H@qJ~|_kjY^e8>&nVUiR?n%}E%_fy*`{14ikMY|`mTW|T(Jw~KKE zE(f9+rAZ83k0>)rOOg&C#~&bO;S6A$Cfy7S>j0TA!`xCMUjn%+MsZmZN3lDdy<@|> zk9A0SMi0=Lbi;31M~d z&dgHax_qj34IPC{!0q!ogb7Qf;?iC`AjImgdQJEBR=iFu14z)pu4kKJ=t)-*G4rxj*5 zGjOjJD$SaH_FH0QRWk#7ZOY=9&U8d%VTX+p@nci}41~Wc4^s7=gan{S|o`=0RvhUaaW{!E9lC+MKJ*+P(3dMo!4d8f|}^Yf9pS zQT?%F*+GJ-Nyg{`0c<7Md2q=vhiD8mrZc?G$SY@4W|$qA>QLTr7UDvFhi1m&HjF}A zS!00RydQgpWApm)jQbLMy5ena#{3z3veTH((g>Q(*Pr36U>gD(CSo6LweLlaRHrfI z$5E#COw;}i6XLlUd*J94wi0?6i~dL~!xYrQSUhjr_EVSQ88;rgsabK9`MXVstwG$; z?ca?m(57+FQHuRc>|+`OjQtF|>7Rsn#s#3u^pD~j1B_7(MoVJ|+04csdKx=w7zxeg z*dy4-HwGBH4||45iN`bUeeCH8@r?n-d~9>GrP9+FU|c$C*AXxt{YL$a?S$PNK|(y^ z=*i#okn&QF^$_CXJ;dV;BNb)=W61s{Tsxb;v(2#aXOT5Fz6#mR#u1aLbW-IiM<6`S z#!nzsZn27)vDXR#<{D!Mm{mC`4YnmBEM0;fsiOv9iBK4ZK$>k+$CA{S%GBB_Sii)V z81zRlN=~pPIi97rjC#wkBX!~cWa!>ZsUACzJF#sXUseZK45gH1b4{R*@irAY*fvU) zHg#g64#(!g@i7-AwPP%GjIpUWKDL9B+A+@8QG~zVfxv7_Aes~Om1g)OTYC@_bE6b5K1g{4EWYB~bHvqDXC7gWmnQmB9nu=|y# zIG5Q7=rLO-e1@@OMNxt+PQyQNo0C%i@|W!VK4vNPCPcR7AtcA5*$y4q!-+@saO}v| zA;(e2pzK=`vu`;n`#}`J7YuR81ZNT|w;{1y+&-7p@PQNUC;n`L(}{uT48#&ru`5x< zuA{2v@!+eO0P#12NH)Rggj8%!RIxdxg5~-q85P6?>{whn)XV@&LNzsW+k>4g#qz0_ zHv3J+8N9UFZ?s8avw41T2JsAD6#oWg`GZi4g|3MYvEw=6(q;zuTP)&{!)$x-$y*DS zi#A`j{%s~?Wef{tWGR1GZI2yPLgY3x)*6t@b1trFW?+Y@_~O~e({ZQCzTRZNysDXj z&rSBr3ZK>3@i<0&XoAxSosfVzAzvZ_CnV6!z*jaC!8Xv~YjrM^Pck*F z3^X%PVTDjL1FRNj?Ve+=I~xH#X5+ZsgI$B}YZIJ7APUu78Zh@gd-yX5_8?kL48##* z5#m5I1E-tApTysz8%#S;l!4V&h#x*@SoB2cR2V1QZ_~yQ<$>7o9jiF=>=a;JHFkV! zCdBi5pRs&9Wxh4}O^s(Q#xt%KyZPQ%d}Dwy4`Me@7JMoT96)nZ(KNJzPZEp^QSN{p zxfH{G;Px8Y96@>I#b36E~jX#Tg&x9|Y9R)j}MjAwt9E?fM z<&*piF$oJs^HLds9eE~@46avSo# zZ}rBWX!y>#$>yCvy>o5e2|JL_%!EPz`bWW@n~B{%1D4`+P;| zpiLdaUi`|Ymf7{?Ddnm)?7t%H(2UjR`Se9eJvxq@X;aH>Dkb&tS&6M<>!BlJ>!)-% zcJ#vpw(dcj3LRW3o03{LmaY5RrjE8XP~s~(o<+9KUXgzsKL8KM)+pM{*Fh>I-U*yu$JtdvlQEc6#HWg=<^;1&coypdH zYg2J%SwAJ6*)q0nxUC;&mVHOb%z1+A1h$U%4b+R{X5Ud-iXFXD?w?tHaq&?pi0d9t zjtpjFcb(}(u?e0}6rf8y=aQqJ$CIIkkI^K*juFm^X+|IqJHGyiF(!C6ajuOecG*~h zb1{*Zc+|!c)QVVq#OBw8th8eCV(V{^JKqATG99B~ufXOf^b&BMY3-5WbSB&2c4D5pT9D@p(OVdY~aU zVMjS)Cw9-NTiwinJ;JGe`0GeB3{StIkl^s8Q5>*{R){KF=k_p)P^w;yW0I$ z;3n{jKyL;pdJd$4r|2f5`sct_X>4n^ie~!JHL~>u1$pTrRT48&%zqLn3<6j#xhwmS# znrCc}ZQZ5;rbn!?y=M*RJ!=B)SsP%FX3Bn)X`#`2ypYjH8)bV`3CCxwm2I2i?Ua6_ zDIxaft8=}#oDnO>jZI2|EwArn;fW-7+{s=z?9CbB^$2@ybG_-|Zr%yu?%suA0EW^- za=h}eSB#jkxn9q34)ZJtdkb>CZeg!I!$Z9bi~xB7RD`{=bG?CKuQoiS0KGKKTO5Y( z1aDc`o001c2%~-Z-lAOZr0}2ugp2aWo>iPT$LS{z zF-IO+#N#(7$ef2sruQ1m=rS41$ueDIPj|XWQeVW&sn>0yEk1^-rtrfg8uk95GtLtH zGv=Rh+w10ZnPH>MCLC{zpWE1=dm4)VWnl+wyjfl5DL;zsYFx7~^fv zglXpPS=SY|qx=@=Qnc#gb($WFk9#AU@gg0jDwA${)QGlk)i8T6@W;4uDB(#mCqjBO z>}^!SB|6Tu*XlBQ&0*OZ?A4@>wNdt3R+K$ft4viMb>5D?b*R1eN=-b3W2%iez?@vu zVpCIGG$EbE?`ZODAAIM)yhdDmUpS%LyrE%lTzD4lqC*Gd4B>@z5$>*oyc2W1eAm6aJzKN9oNfC3w!O}tUkl5F2C5z zC_k+t?<$^}ir6L5i=k8b(UTwMxZ{`FAaB`-ao*A}lgy3YTt=p&OvscOJQU_du3K}~ zqRM=Sp9Rh$Ser){&sk``g%Xw!fD>;gW>p@Wuxrhg=U!Z3oChHLl=&;i&tJN*zUr^I zABa0Es3|qMr_C`Q1@PrJe3tbbeq0min$b(qL|MXHCj~XrE?QJs33mi>rvr3ZU?c`u zq|kg8CHOJ0t`Jz)_t?|h@9UcUIW>iFRBp8XbKM{OzvlJ8c4fYGc0i91#`nW_y&lwG z1iuK@3A{fk93B%8S9Gj><=l&l62{&9+Pe8>Rvi;zR_BfUuRCeW&S_pMPbp>mE)cNaaRiIcoP2$HrGkIG$XyO`Jvl? zIOl_TX-3xCL2d?qf!Gl6+MqY4IdT?@Da7t=$YMbD+P;h!m(hEoVLC7k7W$$y( zKJ#=2_3*v2zwsY{=YH7wQZ(LHwh|;5!_bz?q z#TTBB>+j|(2l0|LZ;(;A|wfe*UWZ+}Q9q`fg{uG8{jH9hS$*z!ly9 zw|jHIln!)1|Nl$I&aKEI_G$lF{O9{~$U_as*6aVH$;$nIPx%ikCb7k~0LDuuB(|G* zxQDRwl|rJv{Sasq=5KzG|7s`d>jZsa#8Dsnz}HucaH2liL4AfefAjS%MMR>$q6B?x zm#^$?$QzYKy-KCb5L5+eNI-N)p6 z3=`?-OTyp$e0LxsvEFSX(0`orgZQ@C{dylk*e`>iGq0C@*TgV4KkY$;6ZMUsSp^+!0xv%9m>$08bq1xOXxe*7eK!*_EAE!og66Z<|iiP zW0Zf*Bj~(76ypGqypMOm&U!Pkvu%m`)}C_wHF%Kis4byN=sLpgh;7HNkaN5>bYhti z;2JkpnM=H8uJJ=n( z6z!(GPNe-W<((kYhoKDR3KE^c<4Mi7ub)$KLGz3!;k5D0(N2-q0ohqJ{y1>j`cTG+ z;P(yF3q{<1jXYW$FHRPXUj*czFPZhT{6*sB;#Fd!xJA4}yifd6L3xX~P2}?iVX?PJ`#I(xF8Y2+xEKoKr-)~Zm131hi#z7KR9r9K zAl@W4iT8;2iZs$=`Q74k;)^2f?0A1aAbu=^ABpCB0O`gL3V4U&?-qB74~xGR zpA=saUlTtP4~xbh3iKL(C}0Y9wl7WWF7^}$i9^H^u}nNmoGcpuCC?M?^slQHa z5HA<660a3Ei8qO~dt~{aiN;?F!p2_;_-n;KDee`G9~Fe(ko>ktyGiPcihmUUQ{+n? zrU%3{v7JamBc>ZaD`1Y~d~vuqLL4oQ70(rozZI09FL{wzE3On*i$4^%h}*s(e{rxlR6JFTh~*+pX{mpnSS>CUSBMvjSBh7QKN2^JTf}YRUE)v0UE;&yuf-=t z+VZkJZ;Bs^hs1A1{77i>Wr?)^W4S!BNQ{W(;<@4saj{q<(s-D9){9NzZQ_ICBjQWq zKJk6=WASV8TQMCE+|-{bhQ;0@t(BR6x>znw5NC>W#Z}^^;s$ZEc&B)e_^|j(@o90d zxLjIii#Ldy#3u1Jafi55d{lf~d`a9V?ib$?4~bFn zEAeYFgm+eKZ@Sn?%o6*G1H}Sym{=x`5ovEveKW*rajCdcY!KIp*NdCQE#eMwr}&`w zi1@U)SKKGQE*=y=6zKqf?fY5`;U8~v{9-3DOYAES6br;*VwpHboFq;Y=ZXu&rDCnP zMqDe>BLUm9Mcg6o6dx2H5uX2ds<{u`G z6i18W#Yy5h;`t&y6!00OMqDLcD$-p6(>I7Wi(AFp#U0|$#RtS+ijRp;iO-3zh_8wC zhrs$i5I+?^6aOTBBPMmQ`IE)AVtX-5>?ZaS`-$|o!1{{Ck>Y4^qR1)8%vT}K6syF= zBK>dYPbHE>0Gwi!;T!;)UWeag}(fc$IjqxJkT8#J^R>-!d*2 z^M9*(KZo%jri^xQVrRTbN1gurze?tZ zTqQkEOWrFzLyC${p|?YS%P%S#T3B#u;i<#I;XD&*KlAhQh7Chpeqm8wk%|9)|A?DU zMkNXU5l=*`=zH(RUF|oH4P|cVuqnN<-A3oLldcGyH1W_=ZJfhTdK)5rA{{qxiv%Lm zTLU8|e&(c3Yt0XzpSi!)nLP!c0q5n`%7M z(`$5V;M12sN$oYaYIvBTC- zW76Rly!6IUQ`(V$a~{?QFFMelqxm+gO)b8cAv#7kL_z-`1CL1W8-p zMc#3<-~Ghtwdus*ZT_*0Y%QKWr;JBL&yyw4IlJu9S3_IVj)c-un>v<-8q>FK9sTkr zN!Q-}YR1;rBkh{bccz54KA1GH-KLDj_4_9tst9z%aZWshU%UEFJXD?$IGh@Mx3z5d z)Yd@y%Cae~MVSwehKIN|Pabwcqgn&ornVM2ldIgrPMe<`cHBL!FpFy~S~CjyrnDA2 zQ(A{+`ngM6i#JSdEzX?UiZzy%e-z?MTZgVGE*piMKPY=~f9G9XQ@#Dx^%4A!JLpgQ zGPec_J2w8}qo&9%_z>ebYuxq2NQfhCQ<@oP{jUh*{oYAC{AB8^$kma}@TS&&Lz~8z zTl;T+xixRsIju!`=;M-^t%1Q{>Uo)Mwob`>2jlLY*1)7~WmB`JWIH`L`p(aM_M0U4 zy2u2ajf<;hqTE z)bwThGPb_lI(XObopi+D8p_Drn#xh<9f`DUbb7UEOl=BneGR@yUuzAlY17nLI`-|f zt(_umo3b#zGI!mY6=>$Tn$$WX567SRO4jq)POp`juYBWTOeJqcduDgT7%Q!E8ZWGR zGdt<9m&*K3FJ4C;YO40G{wA~#qw8m*X20AT+WzR_ZY`&d86AjCc%qj+NNfV zJ&wGWTeEh@N8cKZz8Qh`TPq?H52c&YHy)!e9iuP2CO-OharC8P^tHk0yEiuaQZ@Rv zWAtsXqi=*i`b_T9))CvMwvO;epUFQ8aTt9Y;-jyl8GWIx*K727C$(>URvLeGAT`x5!jh* z0$qH^nI9xgT*3z&-L=8}-ZNhgC;b2^@HO`%A}RPU(BOT*@StfXCgn-MJDuS(7Vt9= z{4Mjm&To#9t4vJF{mk=whR<8i&rt9h4Z?vRxsL(C8bky( zxvwFdY`mZ(2OdB;B{T49%FSp-=yhiPZ3-ikdO4wgLtNnXlpRJ)3e92hHzax?I<^YD znPPlc^a_O7w!m8{-Pr}bLZLAf_e)iJh`((F-jq@nNk( zNtcT@q|zMDtzr!k#HF%%?xN@Lc`3zHm|D%$trS_Kdm-EYD)zKRj=QuO0eT2btCldI z!i5qprU2hrCL51GZHWZ_;+?h>4$78M!*7fP|71ow5e-XQG)K}6lvdR{ZjFOnv?@%y z*q8dCed%;^XA^IvxCZ*H$X`p^*1#v)a+YjMCv_%-{@@Qi?nj8VR>wh%VfPVaxBc-k zkC?yh+Wz>2{lT9sY=0bL>I)Q2e;j6iIC%JBe?)mS{PlqSVT6C7fc`K7e@A717{SF; zmFa^2U?IMWPg{yEFw(`8*ab%Vj1s%xGag7cJS>?mFj5U9+XY7ah~gUPvv~)E)CEUk zU0_1!g7cV(6B_Vy8}=p0>4tGs8B-m1G6Q!Z#`eb)9`QR6+wsAS{+IZqmkFn3EASgb ze~9iNM0Bx{9+tRwIt)fEM;NXH{)*m_XTOunVdM^X-Okk5nf=#@+$uE*NM zTz|p$R(rRDTatWpX*#`wrOJJmoQtK&eV4>^`TCMbPh@lqX6nO_PQH+YcDGA(OO~17 zmaKh(TQcL146@VSrAx4mec_r6{gl``I)mvPH1X^s`-}}+RdlMIkKjd z3-nqaXcXX6;Z1c}$4NS;h6c|4>2%_^Oe zpmb7P>68Sell&577(0wZ33GRZ$?8;N?)eG^1zJ!-9aBuhrV`Xc^VO-%2^vdK+H4pO z4jVw@(3ha#piz?7O!A8WE=uyCfWIUo=r=FXl=MB64ycq-i4Qi6@i=(DQUv`}Uw5)o z5AP;Dc{!V{6SUl9>YPb5VL!?h5ZlVWRF|>>9PfDYa}zy-6M$?}EBvM=G=Z6s&uqS~ zASOz}0GevmVB#S5Anxf%VUWMmyG{kc8sKq;UBwz;D@$;q5Go>gyof!{VJCJqEAczc zSCH7Lt%b~SfGs9NrWTHRz6r8@o-gQpT zJP5};GyCqN8S6|cQX%?z!?j`9Tcvk=O}Hr%+7Jejc7!<$en5dmB06v8%j zGo@l%R18@|%s<2^+w%%G1yv zJ5Jfds~H%N9Yen!xX%W8rMF^dcJf;jeRc$O%r;e??H@tn;6H#0LMlb>#%?NMU@vwY z53-nzM{)o=>h;@;ph?1q->PI>%k{X^_-#1$&cnk>=>7u`QQ@xD3~+J|gnL%Mhk$MM z48PSlU4E@5KeC(6*QdJ+Rok;?+!q{xh(;10Vz&;6aI2y4jyb#;1nV;uvlm$-$`Ff9 za5BMhl5n_*XNTJTPV`G9cJkRsza2Xq2hh)hJz#?nafpVK8iKnM|CHJ$7@6K$w8t zzqv4MtBrl1j7OCROtoicq8>X!X8L0fT{tP3omG#WcNG7Op=l^&HeN9Yu*3faN43>( zuCGBimjoSwxQ^*Yfj&?Js<;fhCgC}kW%fq6zv4+gJt9vg5Zid-aAzQx9jDYUW$zw- zxrB4gvUtWr-pK@JAyWfkHB2Y^*;s-qsBCgGLxXGr!S>*|@oBcf_+;~$+ut~TxN*2~ zW0Az|Z>8UlXZR%R6Y&2bCk!N!-_+d=Ey#^Cu!p4Z#B*~E8*Jw?@SF%tq zew-K6aUw&#`C)1?Aq@9`*M}b_)r7bly5}vs*Py*=v$w3=%L<=0E0lLyAJ{sxUe{~G zB$usmy#^DeMYd}lQMe~F+?OA;-FB^Ew#y1!w%s*4XoZZz^#5RErOiapnAznqxTo`j z4RqOPm(91K>lrdSX{K*OKVZmcAIp$g+&xikDPohn`Ssq(=Xw`}PxAVPY0s@sW7`b} z3BOvs0NFfmAHI6P>HIJq7B{XoXTbE;F>xlroK0hHeoX4|;&^=UpD}`N8)l3sO9~}; zfxyd0j3Q%&j?awSOjf)VKnd#-K(_v}q)!-7#u$7gGxA*6ac72vMhs7mXBrFB^jO%8 z9CN6~?LhpXhck;2O&O!}7<+Sey|<7b?0QcFsoXnZ#G+ZD)BBt_#P}@u3DZpF_RM>x zON>4f8y|_baVt#Y;!X0>Ohi1J37MuCHvz^v-o(XSBp5FaW^~6-hY6WB&S#5O@B{up zyo>9-6YuqAhP|F)Z%%j+K_Qo)7$zllWW4zQ%g9Jc7#XiQZqM!o-Fp`ID;Sr9bD9J* zC>JKx!-`K~*=VtU9E*5a{F}xl9Go#7mkIZo6Q+kpg^O}e%`FTUJ4CgFZx-6%zzIM?(WLdmu4mxHbA{VS!IKulcJ|AM6(Z6fH8JN9aV0#bF)s~f9L!r*$01@BMR1VIYIW9` zH|7+80W%bhE+!rKFkxNK#+bu3IW;2c7A;&lzcL&fd2uVW0t|AQ__L3U^*`JK%wORA zj~nUZL5%-jB--io8P4DMY<66``jIf9@8zau^e#cQt$fOiq2pSofD=>fHa3eSOSy{RZ8UZI`f3rz^oZE@X&?LYrYmCD2h7LzZ^rH)6N1hd=;QAg{^qA`Kt!Ux zKws30gQq^~@%3#-*e`>i(}+Sn5+eNIgU96KyxO9K3jBQcAzwnYQ#1f`oRF9G^7``Y zeexK6A9p;uUwnOB=Q>f}(}j)`MjZ8Fs$)#w>j?X05OlIS*?bIh^V9YroT%@8=*vSK z^!siIl*Hr%M%6yve0h+=<@zu%P-F>F1~%&PM%jreEUc2Z>HYkJSgKmLfjnwJ6~n|lKS39 zo8xFb?gO2dgFX zcYMaL6Ss(WiT9Ei_PfM~N!)-RS32K6Qhr(TTax)!n0h~yd{{E4E10?c7++*Nk-yYX z9v}`A%fu<-Y;mc`?_QR>f<%4SN!}p2N%AiwKSriF&Ti4ziK6@~N;meRkl&TeCF`jF zQ^{XR=E7jCFNm8M(>sVKi-W~e#WTg};ylsVyQBPS$!5KK=)FO5BMJFd$-k8R1c{sI zQ{r<6Cemll&!#>?ZaR2Z;INP%$E! z>jvc}OP(%XAkGo1#Kj^fsj$8^;x*!RBBvWLoxjMEJH(x$xvmiZh-7npL4H#5tKu8t zJK_QHkZ7(ql>18Z*P^-J5Fg}t2HS}pMb4aIJijB!A!4EU1Mv(oB9@Dj#pxm^-%t-1 z{3OkF3tlF9t!S=e#B)*x^BKPs;Qf*x5+4=Kb&T}iNdB$(JCVQaP>;Ee!9$Xdh~|1m z{GTQB%b)pE#59pJe;9wVI8e+Lhl;0)=DJ7zF_I^WQ^g8#rZ`_*B-V)LmlWu^M6&UR z0r>{Wn?!S;K>TfzcZfU1N5#j*XT;~leWLNF0X^ov0UlQTpG0%tKs?@Fnf~zY&&~Y< z@y6>s$oWs~uK^;T;VBo1KM>Cl$B7fgv&9N=p?INqk$8!CrRdwObHWwtyG7hC-YNb} zyk9i;CFD2$I6&W?eV@|b5`Qlq6n#7QBa;6pa^4p2({04|VrTIrv4=QN%oT@;#UlS# zqP~gZ*$-cdOj^rY7xHwWAElv=pi06qHh?QcM$Z3D9|1yz&@+e;~Hi|ckw~4ol z_lpmSkBX0r&xtRJzWw~0lHV2oAadd%>;F>xvxr}_O?*g97dbVN`NLvA(YLQJkUUH* z6(i!YcJ>!2evZh=j?`Z-ULvj*uNK#fTf}YRJ>tFML*l=PPm8{N{p*tVi=17_`VWhr zi(iTVCA#>Rj`>o>46%!tEpmD$^ZEAmMUs8{`ZFYt5+{gL#0qhy$Vr@hZd)#1EM6vF zC0;9T6mJwc<&))qDjGX`$i~hd{FUOL5T6%c7CA?hR&dV*lFQ6{G-Z6Ga{_|~_@`p z*lyovmsBvcuxPl+`u%oE^kIoDh*ve(`oo8zwM$wbxn|ecP;i5{$!!e4F6qNH&fzOU zPQR|Ol?ZL8h0@x{vyl;zq{COFT^Xrp?d_b~+B9CdzcN@nL#zMhv_12H|5%9DyFmZcvFrKgtAVx$xr zX_XRyWyO8_U09B=-J{Y@{`$Hvk{ScXPHF9$?vWLtQTt%W(IyC+k!REI?>g~NBx7&H zZS=P889lWXziMv1rEJjK?$)wMcGc9@KD%D~`otrfz8>^>_U!OC?l&dhv_Fzxo?23R z=)}@dt$o5%Tl?*r+S)hl=Ng5upRZqeeOYSB?W1kpe&Km#Z=hYFBW@^Ac+Y6J@tIeX zw&q3xG3%nhrliLE_b(0wZ&}clmR-+exQDMwxjy0^UK_~5=heweoEfcN_z&m4_I3N# zO<%YFd_1JGR&UMM=N^g0^)LH+QUq~zWmk^=Xn%^a)o2TAk*2_-N1S&1UbQhNMPB%b zzmm{a=vs5`J=D%K|BgBHS4NzE?IZhPebQ;e>pJs4OuIJXZt&0j!oPCv3rC%I)H&n1 zABl6{1LwZt|Kqv$^^C!}celjPeM(v4+5h=|Sbm}1N1y%Lx4UC3ciOJ=pPG37_nGtm zB+fs6q2Jo{SI&P4&VLx^zyJ4~e?MP$bN+ww-#q_l`SxX@tbM76uYn7>2S%@ZqA-&2 zc13Hi@TAsWnK<)b^30b*E@|ymGN|m9(Vy*ihdo~UN$kx28|-R$ZvVTsIG1GL{$uV7 zm>+_Gy8%KaZfeJFu*DgNI6OwYa#k z-Wkgo69_&=72oh<&?7UHbB;B6^vI<0W{?@h2dWrq=yLVQ~l+%C}z4Pxp~Vpce>BUkWt zqlZ>Fd_@zyL#on4=dkRZ5;IUS>j?6FVDK(uxzpxFgp+>f85<#w|3IfMgJlY0UPA)H zn4e+8Y4uQ@^p1&l+8klA2UV;+4$T&OFrk`9*v^DT+OREluNt|V#SW^rmRPZa z3ANdw}z0_ox_MvDrr6lTgftZLyuUSi1WKs*^DkUr2Cs`J~gfHxrC86i0ho zjuLkfJ8C;c{!?v@p?EIZ^2ECr^7QiUO$LmAjPcTi6kz;g1YSQGF#a(DopNTt_{Rw2 zDA4|?hVQ2Mo-u>QKSt^X%^8be{9~l`Mq28)#&+pRO4A&-HXZeRMgitJMxf8Nj42Yn zh0u;~2i!Vl+J%xG!~~YU_ehu`aRL`v3i&^P77oHz0O-`)~U)pG>~zdCqgzId|^NopYXP z5*jq+54n}lAR&h^6HR5ppWVuYoRv%$VU0gUfcG>_LW8DpwDeY&kb`(863u183wR6L zxC>Mpn6Mau_n9y>Xu2OXbmxTa?uptr=7Wh`T!=O1FFw2rX%ZSVT?kDV zXw=4Q5x9W~*Br`(Y~w&CWE&?lVQ64&JkKR$8=2@9CcJY66S9rGjj%R8#e|`OwXxPE zWE*csBL2|m-~A*LvW>+UZPvyC2s8-|tc_!#Q5%_vzfAhSj-lb!##v0rHu6foNoZhg zq|Yq1aZl8(2)qBzeoV+V-pzz;BQM#Tga+2ew_QTEk%`)3_czusA=~&l6Y@9)xUOvy z8dw{5g9atCjqPF3i3vZrjS1PtUWm0e4rRj7z}h&`CFF5rqOMH%`#*$jq?0Ub4mM&9aDvXOUUzndxB_*py-Y~@2t$yWZ3DMJfuWvxre^EFf5$CPb--b6OO3c3~z z5Lk&oKLnbD7EN!4rV<+5=CI7iu|LI>-F)6YTA4GMl4YLBl%a){xyn-R!ZMj^158KZjKZ3J@%GII(ur4GqRI@O$n!DCw)c<=VT`pDPbVw;{_x|0ky8pr;d;x+mzq&>$thz-J;b7rXzKe+J9sFV{yPy73bTR54{} z(R3p;r?`~-4ri+QO!>A?w`z?W;7DK0l;0!rW~K}+n(l_EwJs$`;I&9~15?)eTbYvW ze4Z&e0zYHQ(85MwOH2+?JDKVhru?(tlY@`#EJ3ujb2tKZPtr?WO1ATMq`H$S|LQMb zO1ATQrer(sVam|L+WE9g$#yc8ou$9`Z)Qri^BtySJGU@pXkqP)H-o)9p5e*V-#hj` zQ?i{!h_-h2L?C^-<@fDSmy*Ym=jeT~`|V(- ze*YLhsn*VBh_-gNLm++1WjhacDcR29*eh7(z*rVOsn*UTnUd{1nkhpIYv)BSCEFRE zQT_7RflSGE-piD1=QB(hT39>Zbt&1-@yL22%N!D0!jx?17fi`^Vx_UyB($)0Hit&X za}846#gs?Ie#MkLo*fZw?L2@fLkkx`!zj#O%zuh^cs{K9i}!SUYpx zYN@<@zXrud)^9%qy+0PGs1{tm&A>O%xJz1Fzg>cP4=tM`5wDbcAikAbzr9C$W;6+k zVNPl5xA*J>Eia033o`-wz4)jw>9?jW)^E3N4zcx%kXrK!xHa#p5c98Gza11{;dNHK z{Gm;g4Z?-nT#Idsz`1PO;<=nUKf0W{&SG!)Q8zO!=PpPu=jIhxqq>W|3-`bpZ6+Vz z;4mw(ahBJuDGi%6K+C!IvuO`$nni50Si4=K3Ov9|RS7MqQ>EQhB{YLsH&>M;?w)QJ zV_Vc+a^5n!0^#yoIhJHnScExXmFHMkq&9p>AljCt zySye4A7JNtP?DLr#bW8~CWP6!2w0^ymy4}TRW*jE(~Sw!A@kv>BnY@vm0{V;wsI9q zUxCtDlXM=Hkvt9x^S}X3twm)ftFdE&9C07^0E-Uob;X;Vo&$~_Lo7}t`dM%+!P8eZ zR-$u-D8uty6svJ7cCMNv*PFUx1HhW0gTo5aBCKI#i5?5ih9#rPrIu?jy(%U1dC!BJkJUk z#{xdG;Anz{D66nMb|vg>iw+OwS^r2J7G@Y-7dru_GqLBRyGq+E_KGfyb!%%~e>=1} z-ma* zYmYtVRofV?KsX0oQOcF}9EJ~Kr*8s?>k)j>#A7KUL)%!VD(qO*xf-|@dkpm^*%45O zh2&sFWMquhGhPwPVCFb9=`xOC42xs8=^%e?!EwmdHeNWNj2)ki8vs{YMG=g;x-`7D z8SjF;p>jEm4-X%bSvL5`Hq6J4a#jO(yI=v*xKB|<`02#*-r?EdaELk#n2RL*9W)Eo z?!Wh{I}v;;Ep|dq{jq0x$1!#+g7eZM>}+EVPREW~um)@hf@}*Lf*{+%njn~N#Ar*4 ze~|+bRZWHPBgRXZB+{u-m5y*!^*3frbM_MILM+41W!I%`Fm@5PjRX2*?2$u5l@5)W z;9uC+k%jqGWhA63BVnY2!@RCVU^8|MQ+8>_2xIIm7W+dVA{f{f8HDM>lNw{`*lm@> z*dJdKEjh%{1H?M)F?_hm=Un)Bz_#1*-!(9G+K==uV>Q~Hxy$z{2$9}p8Qaf;u^D+# zbP2XKQ1?Vf^Aq8Fhr`Y`s>1V7sEd4%qpFOQw8~7$`>RqbU<|?UB%a{HjpjN-L{*R{a{8FlK zQRl0Xb<>wlXqm3=_VP+w)XD3)R9>liG0!-5`hXy#SN}A(Yk3A(d0zdKZ-o&|9d1bk zaEysBEI5I<*pjUrOEM|1uPRoBnZQL6Y*JeuLO5_lR|_6SFdJMZjU~e@MyIl13?fon zDMILX;w=jvMzF@P+}_pvA7J9H<{5g%86OnZ5()q2OL$fm7uLHXt5(?Q*a+xv!Lh_- z?4eT^hO1oEYTzad9zwXGTp89Ra;eS&@?gO$L2{WT8qa=a9#oTTOT=vmn|Gc?ue9qC znxnS}wYnl*RwayW;|;)S>^r)yXPqKf=wXY)>-zpEWis~2b$wV^0-rnFFyLkYS=g41 z|2rNJCtLjw3G0t<;4sJNxCryw_GLV44eJW>OYFLgXK;mOKaM!xl|;Bs8%JD zjOXFhiJpUUttqPOUUsn>Y=XNU!(B+^QgSu)ybKDj>Dd7|RAE7>Yx=sGSGjBVmr)vw zk;JyhwdD;^@W&~fb@*-F!wg3c2PV4UU4Z)prA`s7=6p*tdNrVHjwUd4AE4A%&0NGT z#vZvCeSCPVOZ)&!gq>|H=ydEjr?DVb5<%9Jl|+#BTs*0rs3XQU);;5rnYnO~M$S7_WhA63BO%2v zEaB*FjKlOrbn0@As_-0vbhbr4gHaVfDv@heT4ko(2fAKnHiqbrJ$kK8bA7nOjH%)W zE^<*Bek3DhQI(O9s*Hq@&tsVVL9pUyI+7Pv6{Z?PjK!WhDTc|0L#b0wRF#nvt#*_X z^roU+goCZ6I1_x zDBfNm=-KkJALqoZq@;`c8#;g5yhYPzc+>WsShaA$tc6pKO3s`!Z$@>p{o+2oI!v53 ze^Ih#!Gd|!Ni5DyhTdf+!U>JJpgFp9BJ`c-FPJ~0^9(qNnK;K~H}R+`(`L_^|4+}h zdI|2y>n#)R*3&sLn|4(7oa#xlrcEoE&A~Bg`iz-V7R{@fRI{XNMm2PJP&TQ$W;)!g zK)~$}GdgNY&1`3m?{khUFMv<8pz*L^K{9A;zQ__SFfTGNKTGuG74+x7wBslXSu7kY zF{(ZPnJcHDCW#4Bkb-x!lg9BSao+-OEGbdcMF~q4JmrOPYn+3tAm62_aVWIPpjwu` zfhEeQl)0}momDD0#@QBxMXkxK#doP%e36q`i zciN=2d$;Ur9;wRIoaNcBo~f4JvNSCI(Hxgkx}_&Awo=WLR?r}{`+b&`6r{3vES1I0 z^{RQL%OV)=itS-VnA@vhL_hdx3m*1n!qpj^pgn>2yxwzSGQtv*pMn14WiI)R{(Wl4 zeOXRZ5gwIVbKxduV!2^mZ_9H1mNGl-I7?S#-88FTu+lFHK3q1e7XtmTw!rtpVRl!L z8fKP7!p2R;5w+u(b_*6cwu@a~=7$wIJMI*zPP_K_FzUQ)SI6?ODfhXi{PPFcM?pp< z9!*u^Q*~6T5^t#z4{Cg^cjL?alm!oAd_9iwbyU6ab#LH~ORAk)QbjzJkeV`Y($U>|(vg+96-y_fB}lBCJmo6 zbzUyTKY&`mR=?s1mxpt?UGh$q2S*F7==VlH^#hRC@ zcFNCJefJtTF0Mg5lyJ6z4o&$M)4>_UroEtQb$$H(G za=3-=WcSe*TsS5Nu|+;+{DGQ)&>V zzb}@-{P@V@LhNCi5cK*X;=}@m+!n^IfEdm11LW5pA3o;Ce8T)zBOInd(7V5h`zeZH zZeiS=kudc?YldG8F^@0YLc80ch?bj=j+zWRmW!FCsd67iI81|}w+lYd(S8Zz=m#a5 z-@K`wmxPY_VP<10zn2jX(;(;#Mt(^Kw1sgSAV>2%7x}SV=J!K>)n*_+zT-aJ!u;NY zBAVY?d#)u31`3r=ZCT!yorJhIMIpM}Q?tc+OyWjQ1^wQ8sakS&l@?^M;?S&s` zLjh#D+_GU5t>4R$_U?lCuzt204!@&VBK-Rj`SlG2Ff5C0id5U{-22D*RXevIem6uW zEs&o5!*UC;vu@G+hGU$b2wk{^<%V*|sQ!P$uNv!Fn<^yiO;`H1{H)Rb^^|>Npg{lM zUhp7Z`bzial>#}D~k!|ZycQ8H4MD=I39WUu(tvCZ0XLe zF`PefYV`PiPmXVrpAC}dg&353lQ=ixG+_E}B8IEUgTxAPoQRK`#m^FJ#3kbC;!j1M z-&yXp;*BEDzto#wDDVl%FNqt)55>*mSK@afZsIMUhGKiMw^%NY6Q_&SBA;Wj9+!&O ziG1=-{clD7AVs-}*iRfPR*TC;^IHV_UrYX-xLItDlLYf?D|ROFG3zGwByj>a|3a`E zDtROcdA#H!B%6OB*w2%EjN(rbSBU1v40g9jHorlTAD8^HX#Rnq|D)vZMDqs(eF07( ztVeSaviSpo+)i>Q#hV`>#2-i*?HeSHk=^0qWa+1i=Klxj7E3-}G`~O4Uq~6eO!}+D z8>GKOvibc%xsOW!toWkhUlre#{u9ZY#lJ|OjXYSM`T0TE{QQ9QD@%PbiM^fJOZo%F zGU>Tqly;+~pD1~8p`n;#8?Z<78F@ovT6Cz}5rq~nTI zmj9yoI}-XL>^C-FP!b8ykdbPdE7B+?a&?WOM|_LRQAFZF*XFlm0pJCFx%iH%h-r@*l;&N}rSC>T7;@ zP);Fb(B7+z`m~YUUhFOV{^DTihl*pQH~%}x$NcYr=6?tIEm8b3*`F+)BmKpaFBfl- z-u&$#{XNpJ6(3Xl2Fd1k2jzVr{b!>2+kxKv?SS7)Z+>b4 zfmkE`V(}#D&y`Fc)U3~H>2DTqm;O%ie(4{V{FL~n^zVxwN&l(%mGrzBvv!NkNVIzo zu}J#1Vi)Q6m3)9WQu;&1iPBFN=SW{8d9ldlyDV>|c(L@Ci$9nCcFA19%lfXD{%LW8 z^jz4>__wA1Nb;xRchYC!LXYL&O^KjE_?H2bWQU7*g zC+WM2eWfpxe2_R^`YGZ}>F0{o(l3*IvUtAqSBR^nzfQbO`gdH zIkAT2-6yUW9~U=>{GEk%zZKsVw}^JXfq1*$0QtiK?Gs|Y*i_{24veSg60)OMDsq|) z_5H;%k#ke1=lm1$Q1Nh)&QGXcARa3oC)#}s;!l_SGw}lPa`9^MdhuqFGfbF2Cxeju zZG(JNd|C|s)V?O!?vG&ip5#A>pNXNL+HWQQMWp{0=3gi_7wMFUdb)HW>FIXh?#p0zvgFgn(C_TUlCKx(vVr-o6CV|y7M~Yi72g!!6aOH7E`BL) z6}i-z`DgQf3d|GfnTB#w>?n2-dx`YwK)Zorxj0%h|JI0~D0#A&>3`Pl4`H`d@$`km ze9iAQc(LTm#cRbI#M{I>M0(F*`p3jff3tL`!}u@7t>X7$OWkknCGySIv^T%9-~h>k z#S!9Y@knv1X!nmuceG^s@L_&uism;K@&%Hw5LbzIABlMLBMbgo`uoMlMe`$z_!lIb zA6dv7C4V4p68|XDjS%Y-?zswM-L&bNiFSX9@LrO``^Cc73n>R?Jz&GU{Z1$v7^{UwEIrj9V(ell$d_5n0dc>s`Tb37IyTkMEf=3 zuf_XC`c`86%i{auhaw#;G5*gYT`Ey-D4Ks)$VtictHk*3B0VWlHh-?5`EvzFOFvnh zF8)MZAky6u)1NP1CSE0)-&Vx0k!*fjA>S{Vewdj4Iq?BIZSpG&?`q!%Z~ z+x;U*XHJx#73s=}^6x}CZ=(FANFPp=?S2uY2Peuc#Uin-NFPp&-&dq7C(0v4I&z{s zS)}VG%GDx0I8i=br2i($mx=V)MEO?ne(@pkanbHCVMjMkw0~c;`%1`POU~kb7UW#9 zP;4gBn-k+Zi#^0XBAw$fo@Ma8PMxSfR-_jv%4dso=0y1_k*=I5uMz3HiSi@j zbK;94T{N2Et5%6p0(#LgleJu$w&NHFtU4MKRqkW!@j|Dt!yF zSZpVD5xa|-_lcvVuM{VUM~XAWxnhmDSfryV*3a%6!Sf}D_m5XezDB%RyiNSIc)v*Z zH_Y#O@m29n@pt0yMLM#g{kI|?zEX~h1!5Dig=qJeu%qiM+Lwy^iU){;#i8OD@euI{ z(e5{q&uq!_M7!UF{#ePUh-ZlBiFW@9yUQeBC5HE(H%X>*F4p&c@e%Pi;&bAQVt60= zj%2#?V)`xOx8h&KIPWVFpAZYhW@53}PNbV0+V>HMh<2X}Jw4+v{z!4IIA1(LJV~TS zG1^}tUMt=p-X`85-YY&JJ}N#TJ}{zde0FV1@8iVel)Vk@y&Y$uk8 zrD9)kfAJu3xL7G3D$-{f%bhDO6ps;?i6@J6sz&>Z#2dw5h;*~Y_(#R3#plIM;vdDY z#XpOU@k0XB?;`FYwiZjoQjw0_Xn(LcUYsaS6K9DF#A_*?N^k*?;L-xuPy;$Or#p1CqUA<`8c<(6VwaUZd#*jFqQ4-)CR zj_D_fGsU^$(c&WUcyYOShIo!hZ+Fb^YLQOwDBmI8Bd!%UiXVvdc}M$iM7qACoF_IG zcM<6bkMaA9W#U01J>fBaib#ielxsw~!=rqLNdI?~FBj1#IwYe;zc4o z=+XXWk&g5zuNCP=kMi>({pL}APo(=i%3q0eo<}($HWHhP^q$A~wj!PAQSK|!g&yS* zB7Npjo-8g9tHo2qGsN@6^F?~jWBMCJI?$thuSoZKl%EmlFOTxOBHiXu{z9bFJjz)j zz2s4DF49>Z<&I*h*h{4AJjRa_=_`-&RFN+8C@&I^7nh54pvU;j#MR<;B0cCa{sEDW z^eAr-=|+$8`y&13QT|%Y+SSRqBAw?kzLiLCd6c_|beczbpg2?NV6WKKZ2eC!I8T{GCVC#t*IB#K(qi&PG zs98N-yr{6A?)zfafBco)za0uJN2J zC?&G&=j}w!BqWT-v$$dbaeFeGWBAX#Nr1my2Q7v&t6wp=7gr<0?tTb(XTWcXM0|Ia z8;{pm#_@(ICd-c>koWFXXI(n74%nFS*7PdwIJcyZFmFE1-=P$MTj@ zd_`iA_aentbJ)AF;&|RHrhP4^t%-@eJ``V9R{447QG7#UftN$C!tpnAI>EYu&mZ6Y zk=8VrnFk}%Z;BG~;Ushv196x(WCi^SRyrH1hOD4Jn)Ty*DI2na{uqka;yh5m9`?tv z!`gC4B;ssiBPQnC`U>wr06&*E#xE9LRtX=7_%NpmqO947X&O!C;DM`o`4t{?;?mJQxOc!brA#`>{2ka%ta7v zv5R2nQWrs7or+-SP8UJklZs&IaTh_b(Jm{7-gFVfM(i$vq0QLQ4uZ{g5e$9jA_%tM zML#nU9<_i&1^P8`2lv6 zMQp}S8yK_Jv+v9Qas*k#2rcG_@fMXPlW44#V}Rs_41d68FRmlcCIV22f<4vvK#EUSAEb)T~$ z)Wxx|i)Hl;qMmbBggQAEcCxHCBI-S7MW~x&VK>Vv-O*!Ul-f!Vg5MBA9Uau|Xsohz z*K@F{K#(1bW(VYv*j@GkgHy4?icm)fbvrs>M<3&?h-KKB7n$zpfWZ~mkr%-ZrWJWL zc9qEBE!bg2sH20r9Ua_*s0W=Dp^gsfc67jwe$iPG>gb?uM+X}b^#^A~sH20r9UZWv zzjju{ci35bk^^0}hm_jb`E(FPvbWJ9;t;9HBb}OCwOk+RJoyC8S_lkOsH|njYo-=<=%_J=0#S&?BQ9UOX=$f<>3tZ1}@rImO zpmS|0$AY7dS}=c7&6KI|;@o(%3gaafyRax!SeRO^-M39qDUa5Kza zv1AQgUd8>|1jCa-S6Y@NgL%V>f;F&t&TN__gF~ShoDBN1q;|=m3>hDi4BFDXPjc|y zvE6YgnO@_L#tocPGiJsyW7#w;tqxcCa*givc{2uKq3@&~UHkT8_tjsxTU|4yW>K{_ zV9ba~BL<8;Xj0|S34u1- zJZ~fao~8O}F9>zA3YUMo;|=EtGs@>pnUx+qBL|EeIVGOm4jDImz!>k}U|svz$QJ~^9|jb}PxU9};j!6(1{DqmISh3eUI$Xv#UQ5cgN&!p zVUg$a+c#^_f`v6R7Iz-e+skg4Ga@&ZmuP}p|6Tmug6972eha^)-^$-JR^)pn)k}`T zi509_=r}tJA%hyPWcrkvDPGCc>gpd@Sss4;|I?S3<6X7<_Qx$cc5Xc!Qvcm|zUQ@u zhIaV6vMtk&aopNrPhj7XU02v-mK(i(2(L0a!46YNQd=whC{+OoKbPWu&Fw6Y7b;;L z5Hxpblf%kK;zl7H&2Jv^+kk}3kA1*AnIGpJNAp{Y2JsRp+`_n{p$Nl_TZ0Um<%Cx0 zxTBzomfMdV4+YDmJ}h@R!qNO5#c!`k=)x_GGz4(zRRlipeMs=zH z+r~EeaqGc<3On9vgj?8WWTd;iiRh5YP&S7?ESJZJb&GU^w-yE*li?QT7s?@{`hUiH za9;PPx45?#g;XJ7Z#oOE?~ZPP9r3g#sMF(YA4h6>3(S*2ROU!YZ}<(<%4h$$jXjp$ z0_(x3jDrx_0<2~(g3RjkT*LL-`$giJZ$*auL)Z3gYP>enw`*Wmuk|izGcJIwGO=bD zZ>SHSza&Ik9{{;fGJmRNd~>mtm=xQHJOVKco_rFYB@BNfk{azdeMIg}86Rw(UuoA( zJU|>Q4igU*CyH~#D)CrxnRu?aQoK^UQM^mMUtBLfDQ*zo5kC+=5kD7stIGO+C&t(h zkaNXdL|Z=r{b0#s#cAR~@g#ADxLUkTyobzkely8+l=GaQbJEr~pq$@HZ|fQ$e=hke z67u(w;ZDrt0ut$M{Q}}gN{?n)dHkfYJUgynp=6#nsORUD#A(dfUhFFJ`>o%pEujJQF3U3^RY zK>SGjT>MhB&l&Q!&l%W=#{mr2;p`!~waD`XihRTMIKP+vW6{Pf z;=h#4$5CuYp2%0tQsxsXau2b!$R|+L+Y7?Mo|5~D1H{3ijeFRQk$jkVgg8T-BQ6yA z*pcO&Af6EAd+~ zhA(;6D_qyZ=bw}ti+pBFc@MFzxR1!^fsEf@EE5kBE5xzlB$4lCWxBcId@*x<&uP-1 zC7M47q`Oe^mEvmg7oyEKfZg4a?-SRHkBcveuZVAn8^w>rPsMMF-88p)ymiRF?{6*Jcl z@c}N6L%43}Hp!tMihCtLAU+{JBfccQCYnDAzJYlD`$rKLzZvu(SMd9np@~ z4|SA1AD}YbzTyGmU~#Bu{wfe2Cwa0sUHpl-Ks;7FPCQ)<*AcCh9Qv^c*AZPKeYlQj zjpWSrMCQ)|alcV~=+EL+$>F*p^KSv&$I^c$()ShHZT>C502f@8bHqksQ?aeMk60@9 z689Geh(pB@;#hIKI9Z%7{zP0L9xEOvo-Cd&o+q9!UM5~8UN7D(hU=E@lDt-2C;mo! zTFms5@s9NGiJyp@#jnI~MIZOh?9VI_>h!!O=(#Z-!`Nv4c_25VT$rBE)TL)>w`647 zIbZ4DbiUFRIB>iu$lNerX%x=&_``vX&R25Nk~)l_K9Q=QU`uf z#B=O=F_C49Ske;vfH6$-P2mepZ{w4m0^OY_^_y^`I)gV>;OrKrh<||>Q(v>-vp=oZW($zUP zur$n6+6x)QSLN7MHD)TENpZErAnzlJ*VLVW@!mH6f|-th8f788JoBeA=AJ`Bxu5kyrgf+7Bl zffU54sR)KHbrHnXsR)MdbP>cosR)K1cM$|nMy_y%I7b0xgi{q<#6~DLy9k1}tuBJ0 z?_31I&!UTfklH#Sg!wo`FYK7Tuyei=`eEmMB@T-*_n|8|3^6Qr&R618w4L*ncFtGA z=Yd-;zBvDn&sPfH!Shd^ue2d!zS6oj!JK5!loN!W$IPP}F<+?%<|{pbNktFaq@vJg=ShVzxKhuIt9d?n`9re9GoA{lh!e5CHl;3t@# zbQ^45Fq@{ypfWOFsbex21aVw4=s@%Re%yQ|o4Heez7pK@)_c)F{h1ltov-9xq2XpN zrKYji>mKUNSNdCKC)okD=_aWRImKq@e5EO!t7lBBnX_Pib+Yr!nN^*qEtp@kaLTlr z{TIxf8JWA2n%47gI&%pJ)5c<|o^@t0)tzS)eRD}_D$)*SF>QO&5ypA_Nlo=l!^ul9 z&z$8{|5LGZzS6&Bz7mebfB5S#cFtGYIbX@H*LKcVO3(KS=M5#$Gdt%i+3?W6o%5A2 z!JadPGhQ+geMwSiu#Ndj_`dj0nXfbmN1XF&D#UT(RPjG;zEW5GzQ^_)D2^155N-Yl z;?0jMc((Mb#hvq&(0_O?IFH94!#4Cb|4Qx5ztTbQuhee%sLyAPc0QI)o$OCZds*6N!|w31lnpOS zJ>X?&PuNwB{^Y|wz=dO+f2C6=$5QsOqTLWPd-NM07ItW5ewCU*K4$a_AJUsrQ+QKq z40+z@CqG-qTytX`X4^abSX zLP%aVR|uS#&G!l{%jPtM6SC<~>GW<8!>S)q6<0a ziq4Vt1G7r__F8y8Y63K3Ez46TdwGrDrpbPl&cvpy`HlU(3z{|v3R)J7%WmwC@e8xj zvNmvQbO4k%#&UOLUXJ3@<5!xj|03r|{n0C!coZiGy0EcIdUB!kutTnqa%BCa-pC zLhX-{H#s$-_Q%LOotjYlW9jyffi|_3A_UJRL_h2(&RpK4+aEAE)mag0Xi&GI!9ql> zbymcB?97Y&6#F*(zOYC-N+AbgM=c1>BcqyRrcj4@Q_akoA=LP9TPysJSt#xl_)nAQ z7L{!o&;Mz+Dl@y6{;#-I;WUND$>7+M;^N@gWO0z2e7H?fFuf%Bh%*OT2XKdS8KxIJ z?9~*t9@HB14oZU8T@2Ot}j{i>uU6x5%gkU2BLTQGmd)FtwW zvU4^9W*tOlAJExERL-1@kUAv)rgIQd^{X@Y;755)vAHhYODEMt#@#>YKjq(NW$h6wGtLcwshB4`)=0uR6DJ3)_S`l)S2vmfWzB#F$Ux2|EiqcZZ_i2R;FB>io$ zE-aVz=OURf4T9bhH0VnPw1sg;Lk`1?;`&CuLp1Ilm>C%6mpM=1qey-~}qYED%Xz9A65S#qu7 zxfYZ8bNwUpX+uIDBBB{q9zR_yH(%s=filk(q}>#QZ6voByNW%;eqw*|AaS@jQJgH! z5`Q8t5|@a}#Z$%e#Ph|=#H&R9`pEj)@doX9gAYpoxcHR#lK7hVj`*JViMUz(O8i#z z*}up?OSB)LA={6yU~}osHxT4v$>BSNZQMZLUHW}R8%NNWOCBbU7Q;2xHunT}Q>33Q z+FTUqYa}lg`ExAmdyaU%c(Hi3c&%u2R$w2F%X_3>D?Tdnx`z2aFTNy(K1^(!BK{NU zZJa_j-#g&9()%2jkh4Voz)X32?-u3{#*A+#b`iUa`-%sM{Pmdj!^F{|J&%As^l36h z`q|<Bn~Fm1=r(mvYDs*!q@))Hr}&L4k1YGmTHHL(@J`QGQ}FaOHht=!uZFNl?Uo3irT z?=k9=M-tP^3(NNW%%7VmE&R-1TCgQiFy=FVSfcBNpZODx**s)!ugy8bUi-{j+GF!$ zOD}<4kIkn|7*aNK^NkYQtz{1 zX&Lf-{)NN6Sjk?0K4t6ZH~fo7eR4=5wrbQTPv^Z|o4;<6z?UHR-2CCvMJV~0%`=y_+Z>jhiXUwOa$F!xunE3l4dOCr|fv)J5N*O&0Wu=E1ta1!beumqMr zH`r1b^xoVKCCyqo@U!d*gJ2hY7R((4%iq18wdR43KL6SOul~OQ{r~v?$NryzUOD6M z?Ej$|{m-5+Eag#f{m*_6k3sLvXITHw*t~o~+s(@{4wf&Sx!Ie`;}LuoTgqcG2*>0N z9gnL2Ic0IYykU8w-0#@>%&D_~epc3o@4xx$_wO(EJLYVtdf>v(;(4L`%?s_zTc7#f zSwElsz(-a6p?%1E$b8}0$1LviIV0cN;q8u-PUeQ!##{&;9^3vEv3!*-Tty5tP2w6N zmUR~+Y8mdx+YI=Jc$SD~(J@o-A-@R*)R-pcej<@|DkAU%cLb1rg3GUlU^@Rb>kYGj zr^uj11%n$IOwMt690vgpbFUy0@qpPU;$J|@;;S|A6t)A99e>&WUyJ`adxar+z$z-Dt7##2GYhkgyBL;zZ&@iuuYaKXD_C z8%iul@UjI@VOa-0h0U5wxlw{wow@#lu=SUtKAz|PL;N*#d3@o#f6_+i`(SUtfPeCB z{69J`n~6@LikDJ(EZ#r$TKwk~Q9eBMod&B&nNH`Hf!+8?&=Xdk`GnwEy z+RQJN^gBv(rbyy&$cMLH|17p+Fr_7-bPA+`)%fQk`L$MXIjo%cC)!qZ_58D$vMHLC zUxgA)I@BbTXwnrXb(i!mr71{v4$~FmODKN|(wTG?zmgjH2eOd%yiCJu5b&QbZ})e{ zze4N14*o_&@J;NE8SwY9mo@pL3$6b;S}gq{6-?#8&igf)4F! zNk2qn6ZEK)4$g*zE_D)LP~H@M>ZB&@)NYpOLYlExop>WfcB>QLrO19Qwc;A&KxD@{ zaT3I4*0WB2jIwpDlYdWh_HB1dorO`{gq`cet4u`6PV9-#Ym+K;uM?l8$o}nNX=mUD zq6s_LiF^+;hG!!j1UzR)*k*kU!cRi}iRj>6FhQV_fd$aGu{w4mjIMyVEAK0KFEkDD zyZIF{T=zF`4;{z#?gt>?pY39TKl!8i@jMM;3w|hD`d{F`-`DqBZG>Gb9ufEN4+tUV z@0|b;eGgK0_#UL3=zEY7b>D-O8+{K_W50=?dJ9q>-hvc)&rySjh(625OO6uhw;(l4 zi}+BaUw{D($2pW0X;A2r_% zuEp+qM-uBTIQA{TrMKGHeIJa;GRwAt7>hmds+O%{fS(&Q83}E>6#s9*&N4`s+mRNh ze;6QmWPY^QZSPeKx}G?Mt+)`o?;S$0B{6U1@N|nRnU(9{LttPVE!$WHQYz{*N?@Ik zEy3)3Z#C6KzCTDjP%_ZagM4vB$g>BVGnSa^aB&A=`=A6W&+DJA5^wL#tJk z*h930k!?)93_Elq+2LQf@F?zo(Bk}j9@8yuA+1ycBD9%HQb2Z)!`t-Qc@nn5VS2U z!&wc76-!he!?P8EmGP>M=O`HOj+%{vqE(c1)atZ$yvuKBhp&bqKT4|UFxE6W7K-eZJF4l3 zvB+<_E5XJ^(JD$RVK|bew(Xtj&V@ZsbtErD{-INy%ite4)hPpZd}=!zAYbvm`r|x84L^eg)LNf7J$3x` zvoO+IE{0kTD4spSfxr(y4R&{a`rFQ;tQWr>P%oTgM|N8az9EOdJ7 zWS4?k)vL}o7W>=P>u)KmEI@gMmH;U_S99Z_W05gaibEo9~=u&B-_@SpI#;>M7D zuc&o(zE@&sA-*%Pr@RRk?u+mN(gUe24;{ndb$gL3#5L!Sb@Ie##GU5x%AtLpMo#dnDh7kfA7t8 zc)t60&8~D0QE=aIs_zGdB|%j(3E+3OAZYk1aV-BG!hfAjyU0ZrI8;Za18C5l|2pyC ze*9O;e;xQQnCEO;B`H~E2b&&KHCrc(_vqH`!fpqTgvM{je}R?Y2McKK2Tg_@bmiotXeT%Sv`%~P9|AIW0>v!S5j{L`JI`P2PtU)X|j25w=Ju{C5`{&#)*Hq&JEz7^Gr5qOOtVc{M0`$AXuT{HWAZVBEf`0vo~9bCU3>iRvDN`lVg zgQ>3W$#lP4NB3phZIGEbgrfDkb?>%98OOp*EQ4TSNw6{FSiJ1{MSFJNqqr|76PE_Z z3=8sx9XO(6EQZ512lHX=ZFK3Gy+3YJu={{=^2Wj`)8{NMoiue(P0fsjGv_UVr-x(s zk~^EpTYq+k{4sF?M|$FARrF#{ck%#4T|wc(Is`om&rw)PHy7>3OZ8p&g!2 z*p_L>IBvYMO<>=V9j|IL%jFmhH~#X&jW?H3ySpHSSG9}}?T*Q?<9lNI(?DBjw-7QO z#H6<~JVs@trixkNJf8twuPSUkM^t zMigQ2&J4SUkolh)K&dUXyB%`0+?zU}TztS;F3rPoA4WJ#gP?aO<|}q(KwB910OV+X zwLLvA2_5rmh&{~jWrV{t2zu`!za#_N!nh5Pqxm)O<;rD#jj)IL{Q==H4T4^5SIkpn zq_!~bJ;>4g4nls-p<{lW!yD$uUsahVY~!pJcp@1NM#VAyFBx`c@3HN9$$2mi>wqNQ zcd$E`0c~Mbvtbmi-{eSp(M75H?FKtkrz%W;=AJ)pUh>1R<2<);3xj0%8D(6ujpwa~ z63zC|l~!&c$ht+k!CSXCR#`(AZef0*95Sl^XUt3H{cw5?eBRXV>&hauc`Gb`_pYavgwWQUyN>ny|pE+2~c|s9~)20(XpJz zjA3Fj&uLB2{zE16d$S4J`x7wStlZ2iUwjAEnbKVEvYB5}+x!ZQe#dPiS4)(6MQ1I_ z!@$BY^YU;o`18e{_z?0)#Blz>pBKXilAlSEJwozx8p8)4!_MZib&|fj*hd^J4i`s@ zM~XAVx#F?nGVwI=0`XGu=OWLWtdC8G0oO}@QrsZEB7QB}oK)C1!*ODIn|lhDN**9q zh?B$xB7gB>x>Lw3x0Ii>xuZD2UZnU{B;@NP+gwqkyI=Zs(my5H-fsu{4A5)4%TakPb%K# zU?Se;ULyVbvbUGdK>wZWZ0;rGe4Mmcp1m&)vc2{Oa&PGei${t_iN}lQh?k42NaS;i zWP6VrWP5)b@_kbJ*ToOTuf;5!vRI#HVoMU~i%6Vg+lu=rzMnXNgx$fCD@fQ+7w!FO zkk6GJhFzVxp!T`Kc;PvKJh{&0COnIX91bJ70mfNxnn8SA0NxT6|vQY(A!cU)&;oCH_V9dA@;NBeAK-`G3^6 z6Z?w$i*_DE{3ywXiieAwi^lY`#6{u~kuwSz|5Nb_ag}(Z_zUq~F?>(tW0Ic~!}mk} zRx+n1^84qH;y2<}F+kaj&k-AmO-0UPWPCfZL@X8iiu;T9UP##6dm+IJ>BoxpK1k?i zOE&*%kgFvx6_<(jUP#2-dm%x4FC=L1g#aJ|k`rId7Ed-xoKDe-ytFw~CxtO8Z9QZemNZ zSZpWu6#I$;#K9tGrZT^2;!nf{;<4g!;#uNP#Vf>B;*H`jM9y?&{!fZ8h_8s8`O5f@ z#Vz7jBB#PKK3CjLY$+Ct?Zlp9UvYpqSUglbTwEYli)V>H6*>2o|#xVOm3zKriH4iOI)E5$>_8R8uAXmOEvhIo#+O8mKa zulRt-*~KjX1@T?+eQ}fcNAWMBk6UD>%M}}ndx^zjZ*f0yv^Y-WbY|u=M?6kEQT(a6 zQoKyOO1xgYS^Twlzxasw8Er(KZ)On--`i$45M9RaTjq9v9;Jm>@ITVHLuTy zh@-?x@o;gH$a&ecuNIez%f!>fvqVnZru{1M2Jsg04)K4)wce@9K*>>a?vUi_evfuGqw)`e21W)eWZ`JMb+s$samTf53vf;j` zjla_0;^znFpS@@6^4R%B<^ENEw^)yT%AWMDyYoeFaPxRKZ&R!wURvI~!|Zoz;q0rd z%jEc`{H*6{xrE^}@5Neg^{cg*-?u5J0AHMmc+bb7iT5twJ-BK;^sUQVoY}D~c2!Q< zs881C-a0UUQ!K0F>$qdtl$&?$z}zkIT%>A{wI!Z)QrWsU-og5`tg_4T|2*tZVSlaG z+xP}@{0;Ue5q=$Y_$~MZ_NNiWzxp9?4f~3)k#3rGIUYH5Ik_keaQT3n?E` zpX58W&DT9w+dSF7w$HkEYFn*4`LO3|TS3ZRSJ<;)OJPBN+3mAqy+?iWXg+fqHJCZy zG8uVIMqd3l&-O3>6jJ`=R%bRvFFcwb-;|eF`$iD1Ya22&;k6z0$-um^`gx&gXhv} zd8;!k%W#wu@4SJvb7$Cfz72!8|2XJ#ap|kL>B-!%$ja^^{6qz!aCMCF*|FBf zC%9nSf2@H2Ri(#S$|6L%D*c94;!kI;ubyC)xJsvi_3~4$F;>>oEbA3US#6(**47Eu ziO*91Cz!FeChTED_n*9QC%PP^&dQlY-PJg`5iuJ>pzZ>k1`!dToy?^>+bjgl<7Qt= z+gS7R7UDP&oZRTbZGhBSkcV--PJ=P2sdrFB{T$LD;@hwQ zVslfCCN^T{k`KVPCive9J6B%t+ioLvOdiDl)K))wOc=+{7j02_f*&Z~JM3y;4R+2P zCf8xd5*Xr53m%I9scn0mW@j?*gsvn%Q<<~pBb~+%j zg%Fe2*()S_#`g}r9B`I(T0o1smSfYFsjj3Ik2)5~q`U2KM$a|v#2Ucmeh5OTE!scR zp+!F=Q;`Tn`hn5)`(aOL(GNsuP`4i@m_a2$gGfKLg?NCe4m$`q(t_jh-!_gN=E}B{ z1F@rZjCc9eX-9p_v1!XxFLko~@DB|Mw~Y$0bGR|{=(bV9w&G{=7bJU6bL{`dJkrRs zFg$U?nfq^ik!WfTXtflNFEMfn_XrcHFd`H=`*Hx?lGxv=cx;)%%3(pi8+OHs^M2OSz6ko zv`?QSlAVv5R<&sVX$ux&R#xYudPA<6z38Z^;7sUeRvpu`b9Ghc>D_u!GjG9^n$ABQRgq{TwSwp&NP_Jn==KILuc`osf*^@>rNg zv2wwph0|tC95QH-I~w&5N&4t};YbN*C~jvyq#gP6Oxf+sgseZ|ar@JFBZCa*$L-CB z#DJ)rvvh{_0e)T?G-%&sdk&1T3l_|)PR?AgFo|K19IRoGtXQ~U+KlSz1q-V?{1ZkF zE;{jzw!Jx!{I=WfyvDh8=RoosaXYqMV-cr93PvVo1Xp{jltQ(+fK}X!RuB3zrA0z6UG288SI)8uz8jn8PFD9la)h`+VPe! zy!xVPXg4{-ZXN8RS8t)+GT8yPaUKYtd4?Oy;D1oVx=EwVuc4OMEsOZlT?!P(;f;w*}^R!j9$grYtP?7YK)G5cEor zs4D~7!nhkDNAqiii{m78%r75%nBRj4hiMS>jzpp)1KPs4`yfa2>xcYUF7x9JV3^+q zgu^rlddrY#-Zt9HzKZ5I5BV`K?uFRH{N6&C`Gsx#1eJe1T*ch4u51DVkTsG~Cu9zrHSL|5+wCOnIp@@9xC0-)({Kxb>ACY&84~S2RFNm*;?}~pA zH;Lbf0Xm)ewHLdP7+#^z%ife5Vts|;M~dU6Hy@WsKTERBQ-XYqA#kqA9~g|i$r`Q$;~A5=T_=_Nk2%m`9(;_ zAGaAliNwcbnm9{#M=9RsFT(Cr>Cck>0?C(3zE(1QiZR~@B(InJy!e6iTSOe5I?vB= zx;B}gF&-bD-^o^D8?n9EN9-pK5{HQVft~4(5c#>HJX_@VH|1sGX`+ow=r5IQ;}Y`E zCENIf{A8{*sI2jWK}A0p7+=G}n-#|@Yx7Klwm8~2E}d3PY6715q=@FIJQ z`-ua^a*+=t_<1-?oFdK;`AmZGeDFjr7wz)_+2;3xmrH+*c)iG{7EE`)XrB+rk4xsG z3&y`8ZWQfv13jNvFrL?xh^`cJA4mfw{AU3 zyC%8q_<46HTsvb+J?{>Ew_dhp)F=L)#aHgSVxza)%AhP()?`Jq3!e6xp1;cl2k+VN z0`K!Hm+x}L?OXB-cD)QaX-#KLSk_h{@3_PuYqY^yfD! zZ+2OB`CGMx$$Nk5)#{GDC*Yajtys`mXysWD z*Ya7L{G7M&47qTN*MGIyh{?7Jo|Bh|Mth({<9w!7JDt< z{y0`VWmA^V6mNfAFc`V|OCi*Klg&SKh7&|(qh^sES-n` z?T-^a;~w9du(XeC@nTGy`*EJv@QU0miQMN^f|6>)F$051ibf?C`>1^6ud??@=q)Tvk5nlZO-e zE4>ch=VvZ&dBsgz;)!Q#`>gQLo4@szm#r*sctMLR;5|0p@Cx+lz&C2+g7M)6}?bBZUGvo{{z znl;P6iv6+c7Oy<#0`z^3e?@S~d0T^G^!2Q}Tg=)N=(WnkkU5PuOk2{YoE}!+n_WDoYx#Av2b5z0#f8+wnD(R_X0M-}C@-Ef zp!}yFP4=i~iVo#POBgPm?RETQ!#;a?t;f{H5A?eo?lqlUJo}u1-@NWp+gwijD8>DW z_`Lg7_^_AY1fIEJ2%ZUDU|;It`!ql0nLd`)5(xvlN(tu-@T)Eu!1G2pXW&96eiHvu za|X6jQ%TKXXY+p|%f8qXIlL}NPapW0W_$pn7jFKNvYS4@FCI-F=*BA8^nu_a+V0H- zUzka-h&A*R!x4?S1NWFRZWGKCabE9bbwmti53EH@mfd`v@4tv}cAVep+3_~`pK}Kk ziNg5s!~#gU??H->Oi+m*%X258xcDfG!b>!BuVrjS!sgr;Cvsmyiuh<5=OaT_D2I9D zf&o!u5}b{nXdXW!@ht+mS24G<62DRA57FlA#0@6KbFY9&{2Yl{xpYz#B5^vxc|KRu`0SeW;!`}s z!Nd8lq4CdQ?tKwz@E*l;S<&$n8$$2@l(ENB?28osc@%jymVXug`9HIot@QGbrnJJ^ zxH8@l6A{j5_+IPj3Z6=dygn(QiGMM(;%t?IT~cBZ#fvFk!q_J%R;9!QYJg68tVTGO{ME6%TWO*e5fL^OR2 z+j=OX;g$;fI9z@BdmyS2+_sKq;Cg6WKODwfKBQ<(n?SL54lY#YBB4K#1KvNB$Nvbn zavWkB4~I+HBPsdgn-l@UTKNlpFHv19PRB8K4wFQv!?2j*?XEVdZL$4-dHY6y>> zVVewx9mj4qa$yc;N6)ZkX!d5|Q_)MbxgyfxpPB18$@y=z?2CFl#Ph4~09K zkW#5ab;s_j3WgvHJR$*A3CcPNgrjh4!mU1A;NYmrpSYO}FOeWgl|Ke_-`C-w_)CIc zmQ5SNeYiCQ8{1Gejl~Xt=W*Ok6n`jhBh>Gk7eH0U(XI&OFZ$w?E8d|%-BH|_p#}VW zaHGNk_4xvaAnOz&pZ5jbdDFoS>BL9Yo$3aMPV{!>R z9B^w2k_5<^Do-Tkq6HNzb>>Gj)mbE%tEfD+BoGEEK|Pi>q|K+BJll-#zC~MHiQz~_=s(&BaoYzrzW5NOUiCd zv;JC*NYOXD6Og4g;-AjRqeJRkseaP9ZPaU*f&V4?%I( zDda^pZyG!5%NdyukV*%^(Apv(rVh_TK#!&(NKQlq{(6pIMa=F5lrQx;Ld9EX?A9bL zQ@lU^EhK;x31+FLP&E`$N&dxO6!q`l$2x@2`yf1k8(m$Qp1k41U-9@|j9Vz^NpOsJ z_9jr&e`60g`HNywWt;q4YI=A@g&H><#PCwoo&OSTK%xoGOd-cG1u>U@)l?cnzO-_B z6k4*2v5hj5AA5*$Y2qVJA&PR>!mduBQz9RW=t;Omf|=qJa!{>67^IMcUNwk+ZuV3x zTDJuujfHSa2qTz3A$3pkCnS!B;sY8l>d z&x;Sj4?iXlDkeBW>gjY*lBO3;fOP#`IB&r!a7K*(kLblUinE5}1N@hj;x-6{&D}+s zqz(oxFFRjrM;kYhf!N2xDPA<)CvG#;$V8e^Hu0X0HeE%tBrd+KdOEfiX+=Sm4Dk^~ zq#GrI#*|h&>o^x8wInu(7XY;}AM1ct0UmrT#2w}7IK|%+@enCU)EnpLMTxrmhvyJ$Py4!(9VU+JJd6$+!ANNr7|KT2eKQZ!8B8HDo%MGii2#yX;$AR8MB zo{f|6e5~U<0!Y(stdGb%3db`Bh;)4b!6x-D*lc@7;j_a0xdXyFK3alq~m7MxTq~-u%H+9qaXg5KK{5xFOfkMpOl1+ z{CQPlC$Z!4NV{W7NFemZ6#7bGa5ah~zlz1{@BCHKh}S<031Z3k%qh?AgIly})k83G z@`$mc#*UoYL`{kGos!0WIS-A`l2?LCNcu)=tx?%%#N=tiCX5s)4-xFfD$A?ACH9yx zb_D)CV|=%fIKWMzUiL+wjn9})T>ERy6Px!KO1UO>o|YUSP#pI5l~&e&MIDO{xNGh& z;2}Ve*cShHq*33BKm9IVFnL;X+pn~t5X+yPJV)ml(lLqMC{{Pc!G-+yNJ^Z5|5-kj z-T+C8`2yno`MN99b{IKnbn+Nd_u}76A3UCOuAoPSI7g;|cu48I(9m)HV+0u+L8 z+IXy;@?gVm9hF~{&$fwv-~X$X`4Zz5ZRLx$CI2y-f9WgqQIs#4e{Iy0{#iG!$ryz4|`i#*t+j5i!~(|EtCe9g5f;|)eUY{NBP z10(_g{&;;Bbs)tf9&$GBCdCLy*xnX`FXg2Sn+}hr`OTGJ@q|n);ZOM}^IHzLG7X%9 zvk3HW;-PeI|0Z4oGEasOP=Njv`8gp!TDMSsP*H2lFBfiQ z8aM?o4nlE(bX;ifcH7G3@(SmNQ^DK846`z}LeybANb z*PHv5#RKqH2NX)*NO{rsrRyo~ruCc9lg2|B)u#mpagw{c`;$=l{_+p?6AS9qG-v zGn(d5I{z=4(KCT`{vV0BlowxaBexC?F*)JYORh*)%QB$~5xtytSDY+L#{- zqx1dR5TZ}?AcQ}?>HmtJoj;{RV~$}+<2ljvT!g(DlAx66u?$J9L9|lOZXu)BGNkd3 z!VfT{agOM3_3UWeApc^9bqpUee9rJK!%qx__#Tvw`WzvzUk8k5bXSH$7|vlx-<9I? z`f|Y2jK0n=mtiHtCk)lli76eg{{yrn8qHsM{uZwfgn^j0W+`4UA!yp}Bszi7Z5iF2 z(MtWeVT|VW;t-$L{{hliOZjYI>3Dq~&?$`mfrX!D^kqi#dT~gf!RTBTUdHH3M&D;N z|G$+H{|%$xvv6MD2j$ToBLDn^p!svR5TDog0qw%V{aAP?qhkm$@5M80#lqIJ(3xxm7=<5vA z8D=vqV|a(*U55Plf%LyI`U69L+<-r{o%r(g7}Aap)rYq133>S-ka$_5{TPNZjAEF; zunj}nKBM@97>;B}8~fxxg(0uw0eUH;S1{bj@Oy?Q8J=Nync+2tMGQ+B-ebt?H6njr zuMzl>`76&4pt*;LqzF0(redAV2N^`Ey2r&8Qy&?HKwpRQ?b5C`QLIY|F4CL;f66 zj7P(W299IMk2j#FGkP||B@Fp-2jQe4LFxGM26%wcM;P+s4g9Y$TF#Ikci_*T{|78) z{`@(Bpzku8bSx-;{ybCQXGZhq0D|Vv{{xy+e+Sw!bYSSt(3@c}Lw@{0eA3dObo{x1 zK>l1nV1MR6iQ!a+%NX+K0U{nLa!~qX41Z*Jp5YaSHyDzp2gSd|u!13JL6HA_hL0JN zDhT<1V)*SjfcRIie7Fh2|I_CHk~Rv}cN0TWM`OUIF#W?h7%c1VaT87hxqdt zy^P^Xh8r1v&yW;rDE}WAo?&=_;Z=q=8D=reV_3qloFQrEP=5URe!y3Z{*B>hhC;j} zipQVx2jtKB1DY{^D~9$Aof(p<52cG_7|*a3LsIym@V*R(G91Ye#s9aS;}yWh?Gi$i z!SjtMAIs*i^qLbG&Ckn-m&oX3Ld5^FwD1r9kMx>DV9YI{>)-1&$2p-8OsPRUxIt!R z!Jp$b`PaCFCD3h_;uI>~J;Dvb@Xk+`X?K3IRM0P>e}Z6xU!eeJYzcSkY$uK61FiNa zK)+VJJOO&MI{n_McJ2m^*MyIPw|(EKPVD|pC(-4jM$c9s&3|+HXfOmDzsSurp(=rc zMzY&G6&<&CsvSo#6dh)e!M+^@O8> zUhh-~7URsbmLD}gb$O?{+GLE|N7Y>CkCtyI#wUEV=s|DOx@G4lP6?3-X-`xWA`&{i zQ*D2@2->=*9*QlRSp0h zdHk#po+W63lxk~*8E`A~Z8Z$kBE=&RP5h9;qs7+%Dvkp2Uere|h7W?0t#}WG#xk8- zu~>!jiDQvT$#xvF(4>b{=-X;iHfq82)124L)v!>T#B0Keb1CCQF{%7gIVAE^o1)aW z71Ih3b!KJQlMHae3Z{)#i6)OIxI^MBB zNaqymkv6(Qe>n^;J!*f#b@UBLYNN+1vGMxL%ZQ|vwr~S!+#CU^zXm_TjYO(!6zJ13 zPPmD0Q5#hapxwHK+|g4XWYiLYMFxD zL>a-9`L#4*TLQjlG^D&YNvOJ;I**%7L4y@P5mPdL39a6j6(Lt=iw!xZ+R3yf#leQpP}Sf zkDp|6EWyur4I4BZwT&;Al;b_izyVY^sKz zUF0yt&lB9X)TW0Z!x6ZJ1B6R7P!ct2F*&GFH-p1O8G~=s5%57uYSa_pAihpGMwm_s zs8x3)2es-UlFws;4FK%3I) zWC}S#;MmN^5ZE~(%5?OAMW7|T;=4rHMFa&|fn5lKXz=`j1x-VQF3^mZD0Jrm0@AU! z-^;R~h}gKrS0;lmn)3mhJla*XgcrKAQSrIgelO2|PCf{tD` zQAXt(ggWg&DjEbO_n|B%3Joa%H3&-t^9{la4ijYzzCpBCq@)Jnhg3n7GD+BjQc{DM zKq;v~tR)9Eh<%iWGAiF7Zt_{!kRRV5=wxKRLEI+?H3$tIgh2wg5$V-hzj`b|i@N3vd^9GR&DSuaqYj5M+l`WsVjeYE@X6);v4`13Xq zCfax(G&7h6F(0$0anYC?D}?$hYHz`c=4)@s3g!tbvIoc6F-@ytP5E^b_EcAvZKDkW z?WjpPYV=adMmYs??ec+tXvX~rsozvvTF95X(+D?uD?*h>gg$U$-cs?;ihFO*sd zlo7tx40qrobSF?o_@V+H2VZ_B5OgJ&kDD(K$X^}s%g^J2o&;lXs|ltF;+#{+xdL|+ zo!tQ-hwxs#2!`=a8szv(g5NmYs4T%a-0HBufI@krjy%DP4UzEQSZZTOm%!9=PpPXt4Rr0whyqr4?v721{Xv|HSt1CiHyUojqe$#w6_4wUv2O^1UH%m0X?~z;^n}_Uld~u zZoF@Tskl}6*$@s~O+J*uqX`50<@6ikG*{q;Vt&(Dig(tFK#}h(WhnnXXrmRX@Jc`B zyJ?aMdHst_C`eIkFJ&g=H3auRKQP7k7Y|H{hbc0^Z{wv37y2Qu)Ifbv*(bvk?l8hA z=1)i~SHuY;B%YAs0~)U;eU+l)gjE81Ueug`62TY0jh7=_&`Bo<;hlX5D4nAFe#xP$ zGKatRYcZdaS5~J92QQo87;ceZhDr)KsAx*~rN3LjM}iw2h(J-1E(BC2OdNU;w!@7W z1XR9?Adz25C?5aIShN>mR17J_D~m(tg%5vGS&GN&`Q?Ec8;LS=l*8il#s24y@+E^o zO*2ru`2m0R`kRvf;q6k+b8(|d6KudO5=;{|cIOfBNaVx26D-871|uVkdF0%JyU9Zl zCp(?@>Pj#hw<_!~>{7_Jln-cpV^r`S-s`LSFXz1mt!fPYn+N6}Wegv&4*?Ym3y!%d zipT9sK+nhf1Nn=xQ@r)w1Qae5 z^yh={GX%H7t4C9>WDw{A1RHR}08bgpPdAG48e7H$1pbW|y+SlNf;G5R_^$>BE=r*& zwhK?=hcZ}*yUE8PFGZ{#aPb#;QLX-=aun3$b5df(=Y)g5lo1rZ6qVv2H$|`_bA?x9 z%_z;kc$U9uDbyAenKU*YinS2;KQ~2XJ~VN}xuj6zqkNilSx|T!dXtI)l4=OIHTf$q z6F4xm5l}FVFJBw6DI#=j8lh`r-=SO-5xO;v@MVPh5`i}pRTlAuBhf;P5ZrjB1l0Pz z;z%U$@W3q;3?PWWt%iny-bqfH2AfP(w5;$`co78QRt5WFmqM->KA;DF`HKpU!;SWn z0HB&RX-X98#Cvripo~R=#JRj>r6MZ*@)t$b!>x`cIUW6v+(x*`h6^2p)aLC=P1g@B%k_XqM9eJ{m>_GLc&nNd_HJUc-<+$wxSRz#2h6gg6F z=Pwuh{*4#C7_b-wt#GUG3;`UtD21X}8VC4GSv`D=zj`%Rj$-|b%25z~9n_tGKBM9z z!NFh32nt_ioNqq!H#MU)|KeFF=$r3PA6=125582E!M|=`%6!x?sG!eLmXuEurq~Ol z3T{Qu;~hL7PA(d_>1u2`aL3`MEZX7Tf?Ihlgkvdgnk`o0R$f#;DmD%`rE7X!W5nN; za}$+P5d>k4^&i@x!E!?dV<-K$XPY!D z>6@)b-Ue;>#H6uFgGUb^?gR6vzcEP@!7nL!1S~NSK~<5%#G%P!6wxu}AQ8IdCZSMd zfP=|l!6hL>uSAK+(npje3GlFY6lqEXFuD>MltJo4j^pBXszTmXKf{OlJ=37$#zmqC zI{I5A>g2;>q|8)!bXDZx!$Wh5<3T@k5V@!`{j{YYq!UF-QXH-A?Ht?Ni6RuXUCK(5 zSr}}>9BrMImSH}zWEm!^6Z(ku&G!*K6h?^*lX0l|Dh`9J)Yw?D&Jn^=^F?M6g6^EfWF?~~3 zkD18*Zk=)D+gkN&nV|goo>RQ`0^UAOqD%lJ4j^97da1@T_2p{csjd*Mq|@J_qZ@{wp)^kl zgv8RQwNU&=gN~sBbzO~)nkrgiBUKZjsnA?xA+!`)37ZM6g|;dVLV-`xtcl4(hXIqP zDsYU_g@1_vLqz&-1p=R8Nl8u4a{qRKz&~F2V(-@2>%Mq>JLd8xa3e+zn>HH%jbhYf z6vDfQ4jYDl(9qNpZo=f@P067chDMJ>O{hRcn!ox?Ant&L;!y-X!zWLiI1&SLlT@R? zjUW>KKY-8BWc<^HVbhY4?SFnXLsWY2>MRNIcTF#T)`y2ZZi)vsfxo_uM`3ii;uhon zckzfz{I*;r_l6+iK=`XIew)Vo6*R|(D1MajT7txOOyiXZ9-NjHmbkGI#OFu#BDTG0 zex&0|ZBcnC^P3G1ir0AIMQqb*q#DC$LEN<56)2a(79EvKMc?+VV3#uN66mJ+tw4So;79rWD_gg2XpnMcqeEO} zewp9oXA%45`x+ul`Ml*UjUSLMQ(J+cM%fraQ+{;cWvGnz+8(>3@KavOc)!Af+{$Z& z!`G`6WqWyw2u+{Y5A~zG>3L0YE9>_eZd4}`z+dl>U$~M0D$Am0YEo^1za#DEe~GAc z5;l2Vf|+iD|H#(O0`0U>B;KUlFC{2k%5sSMKX2=%(ZtS-YJ`r~LgX+lZdGkuL%74Q}2RI7(Qh9oZ(xBpBM`9vMHU? z#?6h0KbEUA7nJy2UC9M82uBYrHoEzbRnZl8GV=Gd*=TK zqs15isT|&h3;FW46rioiAG8Y#=WVz^^EMO+k6_^mEW9nFl{Q?%n7`6yYc|n%uK5ht zvT)K}qVjh!{}hJ2O$GdUTMDH6iTS6q_yr8h8S*w1h*!_zJz@TD8U3E27;&gPLxwob zkgt~&L*9l0;XaHGU>HpZ|5gk;Gwi{_`!FOGDvCFb5btXy!=(&2Fx<`X7(?DR0`apM zUBdOyP-8D1tt{?`aG?&L6k-ev*$S2Own!xs$SG30F(kWL+WP_yD=Qb{Kqq-a|bA#&M6?AM~Hk^FnSHc-OQg9!YKSS!}Bcs zCx*mRQg{xd3mDci|3?g;G5?ngKQMnav7#QD3`u*8@^fJ5$CmB1JF43PP0okm0Wk-!r5*6yA)X6GLx?(F|KL?96a5A@1P} zlbHWphKrd0GKTAz{|-j)VR(x9Ut)NZVJZvHWLU)fs~BC!kTlMy{_h$7!TeRQcA)xc z6C&J<(N+vSn13L{D2B~hcuR(zn14?~e2+nl9?dY3;Y>pGOS))0#IVF8KaYbZ-h%vT zjYMe8(21cN!!U+X3|la4&5(FVN>BTvgu@t)VmO&0tw||-8N-zfH!$Sqb%Y;b^l^q~ z8D3W>u8+s*^$GI}9H(hsNb zEesDbJj#$1!zugorP6Z{~{FUeY zE}VTUSP;@Nw1di&7E^>n(uSxG?NVr10pH0z3d4X42Rjsk8r-u;Xz$Zb;J9c={Lnt< z{H`Uoj&lzzw60j_u7&W03tARQ>|MVOw|DxAR_PU(tU$`d#aDF0r-XCjYqq`A;08aw?Nw$3_VSoLbF;Sny_? zX2(0RR@wqi|5{$`bz=c%<|&OWw-s=9J1@kJ^Ad1gn#W?3qXb;k%w4f>I|;Zh57)&$ zA1>g=^jaJ{c#eQumNqT6_4fkqSkTzmqh|$N;lTm1^9u#sA4Xkb^Irx0njK z#Frtl#gRhp!Vr(xl_P|lu+S#<(t07+E7mY}z;z*a@w95}%x6N*#`ax|u0(}fzxJ0H z%bqHn&gYt#-D_01Efa3VY)e<++^W)Iv_v8p^US z{2!`u+9x7o(qq)QF3o&ninptCM^`(<^m?n#8GbU2>DEJoTRTBBCiS8QXH)$t`n08( z<2wEtt-nyr&Af3p`q3jX*V6ZPbXX5f&UIgQ^q*2q&erfobaa3g=e783^y@=fT-Vo! zq9s<^+}aV_qf<9(bM>XGqwBPFxQ?wCL{D9z!`-?(HF~awE|=&rD*E#ZUCwQH-{`kG zdfa>6j?p7F>v0bj#6`EW*5{tR42(W@RG%{#;Tk0X26|jqZhrZk0IxD zRTwRQX2@OjejAm%%!r%3?@`n)J7X^1xGF0AnlTr&ydbJme-p0dds)<-PbS=q374X( z_nC5;wLe7lZf(XzcHa}#`d2fqAbmsB>0RdBvWTToYuZ|HgHF$gs()|6^>r8@b@HSo zH*@QtsOLkixGP%SqK;ZNj1&4s)0^!rE^HCJxh@RgDF_guN*cjiW3N^|4p zbxn+v{@~7~W)6>x-{8T8$Mud3pXJF_{?sn=$Otd)q;E{*%5L7=$)o;}4e>r)m7R0s z*u%lUDx94&#i^Knz+JXCZTYC8Z;~lxKW>>;5-|NKvy5&@OOZzTdp7H+hmP5L7Pd04{ zzq-F0*V1T3_~HBAx%!QB!bM&^xod`#!^@I;aTObfh1+nwxlp5C;pMu0x!arChHDJ! z$6Yp#4nJ|GKUclQFI=uRkZWn?6y9mzAe3hw-sz{oT%DzMxXgGcXS(~3u;WvQaqDbf zg{hSc=Q{4cA661NlI!MF5oWP>6u0+iZdkth7|!353wu9hET{A1`LJ!Z<2awdqhZH7 zPvCa^v@^^{Hj(QXwJyvhbTZdox+rYZ=|pZ*t7&0V+@^9)xnsiQhmts9w*g@*9j9^b z<(|(=sEQzoWq{l&^LRQa=l%OLw^We&Q<-G9$HxZ9d|zbO6a($ zE4fPfsnF@htGS+?_J_W`w1#u2*b;hwz&b8|#EQ^1Y8$wVFXn{WoY~0Dn=?6d#K6tm z4vpcVHoD()T3dRBwz;{LE0nYgy_d9|dv+>1^tH!MZb+nmXwto1oJW>Z=*WG0xc0p* zLNf=YaH;pTL-*M2=e8#Q8FIJb0LO`5hwM6bh)dY~AS5;M2xsqjCuC6MF|P0VypVC? zJZUg^M)<0r0gy~cJ8vDtWyTmLyBL^$gP=e8*6h zvFsw_=3KK2=@^^Jg?2LzdF7YR^?0NnqVAl@mCXMTysB9?_mk=K-~}eR+~bQj`Mh4#)-N1Ra?i>8eyn9^i-44Oaw?5#mFNh1? zaP|>**g7a!v)~E$`_HbyFP}f2R%RcJ9lGhb z?I}T>pQ}ngL~ITk?5QEGuU;NhJx)^^zG!w(=1Fa-s`I2E$xB^nT-MN_2cZVi7ZZC1 zSuQe?8XC6^`Z?D`dh~KsP`Z`5^voc?pxE)2QeQQvAeS4>qz)&|gJv1qN>_K+4hkPH zk&gTLN8qS52kFg&uLA$Hcb2Z{@E}lik*l=eZAIYp26yS|l)S+1t-Pc++e!oXob-`S zcyl4JyQ#l)Q_8WxX$u3T0qu7Osyq*tcKm&P;KzYs(uRXe0*4evNMCiC5$M-4S~~xa zae))A#Y&f-9296A5--*6-!0JjT!K_rt5x7Zzt+;VKZggdKHFBhYOHr)ZBPfPhLwHb zo-3WCDmf;B>G55q^X7^J`{i|)&hYsZ(5GK7>8rXI0n*2Pq%St#4cIcLzjQ+D+W|%T zgQVj>W(UkXGDQ09#~T5wVuwp#jW`#eRyk5S+v-TbFEhtTmlf^^h_Dk@EPcaC&SMT>x^H|9wX zZVnAtHg%zNR431X6>dwUXEp5tUe_&?E=w~CNZ++WdUug}fT-_kX->=s|DzV`q|u+A z`CquRK^k$T-rqfCvs5;-)L(tnR%uyimVXD|9nu-UU-N(eVVCsKPiOpfv-U~{%{=74 zYR7)*k?`&QlO`OJ&ilC9|L5jMr482?_)oArE-hP_~~c<%GSewOZ*LK*ZVg9^S!0gf|G{+`BtgY zx@0x~rCJ%%<E^ySVHzdrT1q)$d>`sq}cN@x3D z^K-5&m+t%gqu;^GO6kDtgMQ!D)JV^5+vZnzw_chua<$+5U+zhrf)@B~eEU!uFG}*$ zRQW~v;npa>`v%XY9S-*Mb9Hzr4NLCimmB;>%C(I5D{KF|w81>YujPmj()~}|{md79 zmVUf$+=U03%0VV!SCHv^gY zW{IzCp0VuW)=b~CC(LA`$=7^ERhF_>twV`#FxXWo4^< z-7dPwKAc_PJNl)&%xGPbucn{3EPvc+U)?EwGVeD1eUmN(%KTh9`$m2Uk(H~q@EsW+ zA#=GG;`?$@L^SjFC8aDWhtmq+A{jJpJeMlc!aAlUy^R4}52GZ+3E#423Z9RI{=iR_zvh;O_ zee}{s%Jxs+;j_eNtjvAzTAw~UC&&i0S>&@$oG6P5nC9a!D@m4RJ=VwU>2#T@c%aX? zp|fSrUU%`au9zoVT9@GC(|wUFCojw=rC_N{dezHkQl}NN(Z?k|y9-v!uJ17Maqqrf zmby~xV^Xn6Hh1QAqkXB%X()vvuSPkbO7RrAoRyVnz0 zyShrRw$Gl)o-`DA?KtyN*5-lSD`EOu+3+Vnd9{mqFN=P0!s`d|XIa^s6tCf>0=dt} z&0aGOsmfcbtnj)&O)R(3n(K9{t&aSnQKDDAoq=4>dW2V-cgAvemp)$B#pZH#{|;Vl z&oq-Cj*9atSZ^m6w+-?-J;hP(-OJ7Eeot4q`3P&TX;Gf?)TstugPeWkp^H_$_8J7r zCvSS^8Tv-mZ6BtK<&*z^63ZgM-n9iAO;_LBE+z1H)0X+Qap!HYcKr4N$(&Yb4iC4ZPad*fKo z&$ma(eNPVb6y6&rACl44v;V6}@_~0-dTNQ1s{`)axT`YR8QpV!O%>mGP4uG%b56jgfos%)1p za4qog_1G;R(n0RAw8uWV(bS(jycQjjZ{2>v!|lv5`LmlT9y9At%FQ2b_Go5$R&HXr z!o#rrMfv@RxgPzN{48HJGSTC=>(}LK8%KED{~(q3xZcOZB_dru>q!TXD|52t$rjB$ z_T9{vw`v{iQLa`je=*(NV_2u#^2DPy9x*#A<(cJ%9upqa%HM0LdprrgCl|$haKHN9 zBl&|V&)uskpUMv&X>jip@KPRGRpxH6`mOwwQI5OQgZJ_eZEw1-Xz_>Kaq)TgsDmo0 zZdZ@G$Ej(gYQEj&zGbX-YKHFy_s~N9)Zycox_gG3q*foD=|1t0MQZT<3GROy+N4f! z9O_=T$Ub%Pu%7M)Z=6$S9%$>nevC(Ir@PVa18RLz)tm#|XY>h7-96gHy}md!)$D|o z`;M+rsZ(C)x$iBCOZ_oOFA%hZC|zq@TJZ<|^y{l#tJ;7+MmH0#{1J?fUayjzJ| zLUQla(A}ACmMQ~M^B!Dti`+CMwN1cTw;!BFrv5Phu-ovT$ELo_+2J;}%cN9^)jGFp zkEf=Fj9u*3Z`q90pr5C^B{P2fZtq7fOWl9EyIZQ(s?-)LZQLr) zu1hWG73CJye{*WflYVXw)wib}RdIH!zOXy>Oyi6Yz0c{o9Wg(W+D%)XXd;VNHOn)>4BwXT!<-AV0hv)FZ*TW#v4Mblk(zq^~N z`f!}9ZO)_AmK_JXK1_L*I_pAr*WahVO5JbW#6WhJbG6d02I{%mpVd#>zhA}GX1ht+e1qRz1~0Nq>$dP0mj@GU(`;VW zx}59hm{vcm#6{lDEp2ycri(?icUsrB*Imy02c-RZ{jAGIx6rgBfk#{}*hi(cIlj}S znN9Pw`}XTy(ydyh&E2`g<$_iFGy{{FF88gwq@}Ez;L^{&XPSrBP!}V&ere~I_jJ+q zADkAZ+Rmk2)QGfei(_1}+m20(Q3-Te(|1zZjm54m8^$N4MXOr7lr5N`#);0YZ=|K!A0FYn;kWFx($K!n7XF24>vK9fS5GWW>pCRfx&Gvxv}V7B zI6FMAO?$q^(|N!D{j@A6iSwWtPts0ZH*xNB^F`XO-kQ$qHQ%OfdG*;z)aygq)^)F( z&L8?S?U3g~r+sf#)30Y$I%T!dN^clb=;X6kKixz#&8gt6NqV>AKRcc5Y?Z#J!)d3~ z6L#spy*S`xq2-)DaLYEQBjY^Mi^JDAP0sU8?_IahDJdX0{g>~iIi1}Rk-pw+Y0M)h@l-uZ`2Q4qehytD~Gc-0YctW3|82y}4xK|bgSL^PQsM&=|eiHI?b`3l72<_-qC0G^mMmN&m1jm=cb<=-{2T=U{QKY zhue-@+`dbHQ<3B7baqYp&zm^Mr;(e|zwdC-@t4eP=_@pjJ4*WON#88r>$v*yf%HoY zH#>UIJC^<`W`(1w@#*x|f6R3>I&nVz;*BYeJzD;p9<^|kV_yA@^xF9TjjfRh zS0+!>OBV96 zPmNE_xT`tJetnDV3H^` zMkllV^Loh-?~O90ugfI0W|o=bKIBNEL+mnJt4JmC-p-kQv@b~#=XhrBH9a9|vEM(_ z%6^|DCMz^E$NPK9;MdWa=OR~0j@Tt+7PMO+G3nGU)2V;5He) zAW6)F0hyCGcbCN549`4ttc_$`ud$hiH=`v#ZJeBWxhz29RxmAd#|u}Nsl}0GDi>oWH-~{`^?1oFYRtl*p+!&DyZ78%G*5`EQOZ9ZSfD;!oy}Yj4ISQ_39`1I=E~K|KbKva5cH_@vWcE0?(~i^5 z&s?3i-Y#TpNv6vCrFMClcQUUy&$e6YQJ;Cf`((TR>mFu4TRg(9+nZ;ZW6$@s8#CZd zrtAGqc6-x5WV%@-*u4r6W{vL^K6bww>Sf)y>}YpvsYzD;uNHRG-&

  • -|I;_X*@${zNTklP8>3#G*bVN_q`_bEae?67n)d%Z? z=_5T&Pot0ZbUmGp>%;Zo^ogFKXV9m5rk+Wk=~;RfozS!O@$|VqQJ+Ys^<4cz`bwXq ze~-@SWqKLY^m4tN+4Q;kTqg8Ny^`rzHP$h^Ua!|Pr#??_WQHEpTbbJ#<&0vn&U>A^ zSuX?2UzTjx3>)if=!VYv84kn2QjBOLn)NsEVFL`e;bsGkSR4Pm<>15j5IdVNH@}1rZL5UShg|A$Y&QBlZ_%a*(f%O+2uxwQNoIi*~V-(%P2KUS&88@eC!IN%qU~C zjdG)$U1`iU=CV?w(x_x!quQuuKBLy~vpGhC(ZI@$Mx&8kWi%O0Y%VcAkuU98Ki6PA zT2o1^4(sR|tch!yKyO0Y1}p}aSy%zAw6KP#HXZ5Bzy@G5>R|0%vklk|>;gK0$AG7R zXMw*0e+S+G-T^*9ox72K3Vf-~vAUh=JgdXHz2+?1umRCPERcwNtmA7_fK;M}TA&dK z5^Gq9bSZER^`nVYNJY3al27j}q~)}d*3m}XtL~(S=_z`FUZHpBIGtuT=4MGOm5pVE z@_Az4t~sf`&N=D6$L3(>_FeCL&9~ln1k^I$8@@HZcR(%hJ?&fWdmdDy?-}1h-wU8B zeY<>q-?N}feY<_-zNbOW@NM#y__l&7@NM=@_2F*Cm+QO1SLj;{D$94HFVD9QRGM#t zFT=M6RElqjFV%Mgs5oD(FUi+P@(&9AKDVz4RHCogXY-YUGJGZ8(>@<4?wjO2?kgbf z{nD53eaBY_>LcH9?<>A6P)B?j-WPn?pdQ27r+g`(cKhTSoTv`>ly$hD zti%0e9quFRj!=d--J1!F1#;`$-a_v*Z=yHFo9cbqTkXyFHh7D@rQR0r0&lr@3F776 zYY}enuJzvP-H4nm-n$TXcz1(-*t@T8YF$y?Y)Q$d$e@4pke}e66X##R7B*!IUD?8} zY+=9_Ik3ou-4^Kui(F1g`YhNbMcJjl?$doV5O%qXJkGmeogvPzoM&jLGXxtA|9{vL zqkL*pw$3ESKerR+3rA^N>EhC5r7KETmaZwixmG@%;^3e0&p@2yCy9w%kxN`J){9Al z?|I3l&w&RD=O3JZAl-S^d6w+|Rvi}iQM`QK-(U|D<{Up{^}B%tpfB-d@HM{&NCV)r z{%q@bA}|Rku#Tr%D6-1T2Fkj@{B6Xqwh_m?$ghr8Dfufw$AW$`0(+2`2&9;hd2msF zb*fokA>BfzRemgho?e{~6n2;IkqL9ZzX`y+?_aEVNSRd~t6lQrI^bWS%JHkGS$Qk} z4dD9Wzc~W9hWIxteelX<#IIV>4f1a@^D1TA+y4)F-vZRuawXWh#zNv30tE9gCbEoq zgy--GWi%KoJPO@7aPMx`#A-o>e@j5Iaj+b?@tcNfzhPYV9 zMOcSX91rWIC=cN|UY2pZjKi=L!?;{5OSu@z+0(6i#g!g@elIgSwN+DHr~BM_nDNfA=UBUUj!-7p3ywMOW7h6??0v#EI-WosT>lxgo${`-9>AXy zZkuck^s>rU0=^A3pFzzU$0~=6!}c4Tlnq#txCBB;VY?mAy+iC($0nD-_BrMt@3*u< zK4@`r*~V$dHkZQ=Tc30JY`+t6h3qKQ$!5oGEu4y-gj~%A31!;8&Q-9pPAON(&N~x; zvH*F8aoU*zt@@oAoPmAn%;r?aWoHgo!!A4Xxq6_dK+QF0A=k*hfVM4wrvSd@RB`8w z3r;n6f!%Uea0v2BkRR;E+1VYZ!8>80oHgG27MZi&`wZ|#(6P@sinS2sqt0=HLvE=i z6s%o8&?iB!kK`7kGsx9j&N!z*-xlXAHwgK>cgDEoT;Q@TP0pvl=QTMSbS`tlB*!%& zX9r0>3T<;NNzN9|!`3^`fwZm8HEz^$9_Zt&-5qy!%97^1z#&Vf(+;`J>47><=N30> z;ha0%yoH6Dlg5CH@~(c+=nOy|1+hS=Rj$*(1$fFaXE)bvDT4f}rNns^@-k;1*Jq&# zPjSvT`@wpQbCBd1zi8h8e;c(0xdnET9p;`|F1uu0f~Cim#5G#3K`-N=(ImG_{B4Zr z6@;-E=2AiuvIgf1@H$MNw%l-~d7l`!T$$XOrO2fK8+JRUxEIC+u>Y3jrYo1*G0wY= zf%R@-+;SV^#(Bq-k79RRMc|)!>=rC{TqQo4<*rlZOS0Sp$;T`Yz|V)s+?lXEbd~wi zEO%Wr+#MJ>r;T`4Zd9Cj?2j{TV6RPe8;RY zF3wkEje}7b0{o({#F~tGTGL&ZxttKr23 zIctIImUk8VgD=;59BX7P1r8%1RTJRluG?Y!ln=z;>UsdU-;u?2TQ9jDdS@&p zu1DS(>m}zb!50Y*v%`AD(sOnSVnV=IZS8d}`Ha@j3a?Vn>bRzEpmLh^(sWId1s-Iw#Yz|XV&9nENC9z;4-WumLy-3bZoI3_| ze++d7U`#j8Ua}bNXDb=PbC> z!E+kjBcRcO>lT+|o3{o1L$(FSrhnvvM!X8xo^}NMW7g;HA^!x9vHmHG!ad}juq}6V z!#EP$xP@b{ZLQ;~|Gw=-M;}*V+p-1xGhjWBe-1}}|6_=*3H~P*8t`Y(wx0{yb{x%o!Acg>byZ}QIAQrvDX!P?;V;}y!92a@;L zq`n)r4EH6d+332c?1VWsPH55SzNbo;?8M%+WbTWkQY zs;~y-aE-Qnh+PS`Ldyzxatzz=yA7WF1ftL|+vvN4ao=6&T?f{<>R9#Nv#H!;z6X{j z_lWNySYyKX2>7Ucix4>{d`l29AQG}cET_%mQ3NtUUldT-FMDzWx%M8~}rYfokKl`#G0mzvnRqjP?i4wZIve z*Ee8?0P8jAV)mQ?d=SrfdlHP@g#DqXsk5G~w~hK3>_5JjFutum29Gb`_dMqVO>EG^ zLVTF^I0LQrM;;EOS_G-i+m}Ep*1qCN6Jm&Q)N_&B!7D<*32igE07O(+ZK1Er;8#6> z2f?oZ$9}~Hp-vAM2>FloF~Q0DXj_BTYS4Pglf-okxHIU#Z=JxtXKnCY!_ffa>?q(l zz~_c{)4uMx8Q?4mjI+a@o1Dt3^V|~r6WWGx_JXG;aM2oL-40x42W>%Lt9_#*JJ4g# zb=?kJv%mD*1|JxO2$N=i1v{T{+c2zyIe6>>H}Kd6ZsOSy(!#f5eeRg(yozTov0i9) zJmqp6F`hf%GdrMZzb)H!%eTVzyC;0>HZ_dJI$H@ls2p1bc)|w6AC-@?!EVs^66TH@ z`@DOK&`Do7_ouVt>>5OmMw=&`x3HD|tWeHQT6+9S@cd`Ko3?ZARev7I3rK#P%$HUo ze{0CophpBfUT|-EpV;i~Z5*GmXWBd+$X{*?um;FIww$wB?9&dZ{}joUIOkNhZj;Ps z1kY4qO~F1+cC919uLDVH{HJYK*~TWdtq*22%&Cr)v)i_Q+f~1rUAA34yA76n%w?No z9T{Lxu!hfRtLexF4lg=#xE5O_%yg%92;_9)@#3~{?r&iGUAO$rI1c-pZC9a=(b|AV z7UZl4N#>#Vw$QE&xaITmwA%(d3PDrYo%*e|VPhZk4)n8^Y=#b%-)-D-yM44RU>x=t zElsdW=GaC%)PBDusiVSw$u{0m>Azx=b`<)0Y?B=ZuwJmE#@`Ehz5hB}-_ZzBqOYUH zy9p7}&n?@g-G2W7StGWMvyRP9WKV+K`!+<0IhfaJ7N>v6p6QtDl)_5q>`cHr@XnME z@Dss+wE^x9;Qf4O2F5$H37%tV!Z={!zIW#eFb9UO)+kL3^vTQ8?h%_2SDaN`PE z+c_`77YP0o<9;Q`T-vz|URvl+CwL9UaZDEQ&NaM0fjy+MBf+-_>zW((0BlD>=L_o$ zeiDQ|%u}w#IBvhuxdrp+Y3B~?2cF>i77oTJ5-0lv3&-_?pG@IBkA)*E+EjqDQx+~D z!+7T`!IO+zHYx0CiaM49X?ADF8rNdyI$l6jeA=<)Td`m4*x^)N)-HFK-{JNqa}^G& zH@T}EW|kkk5h4=!41S7yfg?6oZ<~eL#DsE3oab)fmLu77FL2wD?z|AV06%F49^$9Sz#~V2=Mn4*LQlBl*_MB*6+N-?&#L4p)p6Xj82PLk zdKz_m-=M|UXX!gbgUgCZO zuSmazxZkcA{%IONI~U?-=dL&`NmnwFq;OY~uJn)=p$Lhel)JL)yOBGyl$k*o}XyK%U;y{BGFfe6#42fMphv+ zqy6Md!z}Wp;bHQnVUElybE9`9sh;+LR1sK7Qc?pkS`zKC*L`K z6Z$AZIq1s>AsT%HWuhkJL&wn{L8?Jl(GO598bJRMna~iVIy8cAqk8l+G>P6v)9Bae zELuW;gT9CU7g|R)w1s|$IwX`NAN^}dx8yRqE$Nf|8vSRK*xq@Iss7UE0W-(ro;_mZlG& zA7Bt*7-eeuHG`UA&8TKvGpPvzHm#Y}%xe}jPc_S$HO&hsw=_F6Ma$?UI*rbx6?88C z_K%D$l4)cbM9CN#L%xwrp^j0<5TZ(`5+tEYsZvBy?@{leeN+XdK{4d_TvAF;=}|0I zOVuJ7WuoeloO+*nA0<*v)HhKQ`8`)M^&RRv=(CiCvH(vT~k`YY+L z@cVwWfSwY~Qt%g%nr76bY1Xu9+BH^YOZSrG((yZ&6s9FGo`t&nbFK? z9&4Uxo@rL0e6HElY}1IA(g}15ok3^QIdncA}N)h791}zeZm}Ymlmmjs7t9 zNbFH`I`-|@w^42EJF)K|W9%1W3y>+cFt!lY#j0Xes6MtdwiJCmRvoKGXJWq^TZz6A z`}No}=>6D+*any{64Vbf30ql-_7k5$no)ppfJuNLQfrnpE1Gr9hUTT_6&<5_NypL2 zbUK|yD>WN*9$i2mr%UN_`V_5${4{`>ZlIg#Ho6^>m3Gs9`VxJG?uGn1JwOiuZ3Jjz z^aSnJENULoQ<{g69svFb@`sw+nmd}intS+LMA`Rb7V@=eT!gh8kdC9jgj9@v3rPjD z{%_D9pjAjEvDLBF=tOL7Y%MB{ZH{e5Cy^v!Gm-qq9F&h@5voZ7NJA3i3n()I6o795 z?CdM5kr|f>BpKHTU_8zEq9)V0MXnXbotj(|Md-&&vYH}O5~1V!m?qQ{+6j1xDJ{$! z({Wo2n3sTK-U41`$|QjA;}Z8H+!KH{Dad`H9ma8gxD{!j0_`XnIDDgekR1&tWz#ErNUIvVFrZQ4qG|^$Z3#HIE zzQ*Gzl!A=dURWor!(|imk@kXaLfK=guDND1*4!|iiI7vQOSG&^lpTaJQzRSKN3dVC zFEoj8vCqnQ9R&Mfn!w|xsVSllp-g&>{(`CS8IvRCQ+g!kW6@6+_t#M@V}b7s_deO&3>y*4I<^nP6#wo8<)jVU2J zy{Qb3JF`bA)8Fmr1|a?}d2%$kbD_ zXu1}*nQYfLNV#OX5!MmcUoqXRS%*3srd#28&bO(JG2N|=Gu^HqW$Fn`L@LY?yDJFczApj4JbequM-!5HDf9-(zH1YfT-9Ex&-e`V?bqL$~O}^I@HMgUEDmq?8$0goISSDkO zc~yuZ#&hQ9#tY_6qusn6ww2IlbUYUPX0P=rie9TUEfPCpC@`(m9yhIv*Qwf4(?)H% z>1FLH)2j$x!a563t24*co;Jr3+-y!JYpwtSp9XU}DVxn%wQXi)ZM!*-=>Hn1wVDes z2!2=VHXkRY-&`tQOKUHg%WJQgPl?x_+FrAcl-Gd=*pZB{cx}%O`9bZF*^KoiI*ynd zYRAmYq}_zMO>D2)DRX=6eY3T8#_X=0Gy7{Fn=jQqF<+^DX6~(BHD9lNZXT%JG!NBo zn@2tp3-?<4gf&GRhhJAl`&TqSfsWU)CXv7G75ANc@E2mDus;yyi7@A7B45JwurFrw z>vP#|Y0L?Yw@`-RO?tj2)<*cUxD@71Qq(+(UjIa~l;|TW!|Q%jOo}L9CvSC>J)`;y zua(j3YIJ#C6z{~PFeXC0J{Gd~ciHbch52Um)FC_%jDb3-vAZt8h|FUIuGXbs2=BuM zegbbSUte8Dcn;%!#QS4m{t0_yzCDTGuud5J>$1c19@Amo;rS=#XB@1{*>msB^ED3F znaI;tjPoN}dP76?NxGo$0y@_$glYec8W7DE>?2KUe)-{NEw`Ut4qk zY2UBx--muj-lM!v-lLqA2Bp80^pZCy*T@@`LGlJ=p1eW%Yw`x=w{mY>8dX8wi!6}$ zBL9QD7x^plUgWRIdy&7z??v`y;`bu^^6-0+eP6)uMfMfq_aghg1W&X#(XHLL2Pz6x zs>)QficwXojH)xLW2z=qtLnUph1>}^rQ%c_f!v54^@v;Nyq)FMb(mOMYXOx2>MKwfyN9ffp)Jm;38U!i$;l6?f}%aZ>lnL%YSb1@&Ha{Rsu zT1t=^HHh?8ASEwB5%d?*yolFb(A+7~`7&sX^}P*x-hy-oYBj0u5*hKEzXRlpLhs3n?3P{}6p%k|aq&hsm!)J-fPAJ=|AR z^-%qy>QU8V)l%7&s+Fqs;+gk?RqIt7RWGYvRXt*2sy3K7Cb`(mB&(O1bSA5;jZp$E zuS}=PQLm|Ym;&Z_@c>hbbCpzu%5+RQbEWw`v3AOU8186pQcmm9;^uD~!Ktg(-mA*O`H;M`bz;#jC()gBfB*suoo_ zRg26RGf}mqUc(&1@JfXUKz$|-IL9$lg!_GFrr4~WW|Bc`4A2`7bIfDRSLlUs6aZwv zz&wF+9k>E8y^IwnYzgKWv-)0;DLn}?GRL9bb7m7H+}0w28xyCM;{GH02GAyGQmj97@jmgtym$@O&0k3ouu8UQVwE4xW+Cr_WtX-?FTG3W$E47B=nW}Z- zr$}2<^-5b0wHmc8Wxb4Fdyb6Zw)TS7jxDM6XanFo$H8-947J_btKc1GZ68yvZ`WJ( zZoOZBNqhwX0tgw-aBz&a~qe*f#1lRZej^B(v_8 z?zVuFRIa-NzEc3@U4VO_KPv9U>AlhSMs*K#4|R`pi@GIMj&23)Q?6UrZRlRUH~rqU z?iJ%_o)r&#`Mi!Q)9GVQ=IP_~$+}j3x;~5a(5}kSD`9p{>GQzXp$~n*m#MOH?FBNQ zplAJYeW~^;*slJ|=hd_Na{Vd2j@j0qu6m_6<5AK#Fvqbb>K8DA)7n|>ymo;xgH|vD zwNC+-wF_F%jJbZ&AGX(Z?F;Reb_Z);c167-*u839M}zG0h_8ncd&PaTS z$B7p$Kma?VYtmlOwQ4JL=XI>kspE7P1@DH4s)M?hLo-v?1JTuu0gq-VcIYVGHQf!} zP4#ru3V8oUaqs(cINItT!#F(FKhZbq+w{+vQ#c-ij2kfa$Fvn?*O@$s&O4wJV#^{p5)V9ZNF-6acxAaz^M9Eo-zLqRZ$$qsKxF zVxJXs5bU?S%cJzz$Mm(A{?Rf-mrq6GAoMTLqD#I`X%RpP00(gKW9;((ODWh_C|@^T zZz#ihzoCq_v0$e+l@aqRx}4ubeu014iSXPhr2!ZoXGHZxzFb-@s$&fCCw|Yz>(Vm- zO(L6#eFKkw>xqbYSb83S1#pV&F8Io2fSwcKxfq_4*LYcOoQRAylPAKluJks*%@BU_ z3P3Nwb%22rB(9$v;%OrQV|?E@CT{I9hJp^!bm;43UPw1_AHw~U6CoWUV&I#6Ejr$Q zT)f&VE=`AIIytpVKY1Tu24GHPtJlRLLD#+3rzm>qE#A%;?f~395wT8{-UE05@Gy$k z@-CD<0$AknrO?=fLEy8(m+Jr<055s{UjwDDLLm6v$r!$jI}x##o=gTvKM@h9PiFC@ zlDA`?NOu9iRwoNW`eGeV9tSAp+m%P!>*Of_9l&V-Ge84CGe8?aJAf6y4dDL-{vlpd zJ}xeQQhyUlVQ#%{?Ri}(j*a5E9$gA!{;IIPMqA_m4VE?^w9hh^Efo@hQa zkJSmg`l(Yye!~^?I`1R_q=_I?R7U}j3vdjeh;Ls4 zP{z~g-vbzcY7rO#&hTRZnIzPDJM@~?_gzkt2f zlRub0{MKdu{vg2UTh;mF`QvZr;2f7cHW|8tnuDYsZX3)W&Y#Yoh8nY?gwJ3|`RFfw z$;l!yTp1w!ICk~QdawBqbOz6y* z{p6S2apafWiR8?f4029P7C9m25IGx0LC%0tlG9&u$%!v{&g|DW-dpiwlw z`!}FNy-0s_@z4ZLN0$znkFFeDKe};rom{`fC4pCmCURqP(=xyhK0Q*Jt@&OkL0gHoCH3H%!ET6)EUCS)urTB4K^1`d zV8y{o!s8nL1updy>L<|mpHhDcl%G;RMHDqgjiG(ipHY7XlKmHuWLq*9jRAdKT?>Pebi^R&|CSEqupUWJx{ss~ zz5JlBfL}V2LB%0Pwc}I$p|@I2o;n~10 zKi`s_b>I%9>cbNXTG4d)65N@|p22mX)^-Kc;?+;^cMmI`Du7c>{RBH|5_14``F0M@jPU z$-jqE$*E^)@tg6R=s^5d{1(a}=bF9ssbZWNpc>#jiE>KvjY&QEErXhmeB}IG?b-LCGzy~a*vR{j}V%lNG(A@5$z!_x47OUky?VJni=xr8kZH>*Vf36C$}ov`KVRtvG1=>H>7=Dsb z_=k-0Ubc{+J7|{d3NrD3A5S|S27MX>DKo7)&6suu@+P=CLujoe58({lWzx<=YD#0t zHO3h}agdm_i##wQjxtCL0fC>uNzCUwDe)aA>Ay8}jdhWqm7fKj+vVV8a*G^$z$adt z&=?s({x6%U4FE$(pE?Msg5<;Daxk2RQ%A%2I3&nZ#!{}NwBsbI8B7@?AY6wyjgoSg z!)TaOh>tZjAw)?r1Kdw(PPv~tnL3H{l>6Ar<=>LG{=OQfJO|iB`ji(bTPZuKRH`gB zDK!mpTxO;!QgaD@EVT%7DzzlF3}}i}I+X#uI@L&06V%L1ZG}|AC)`FB=6F7pC3$A5 z6Y5}YGM*F1^Jz-if_s=EBdsye33&dN`Yptq$@oc#IX{P8`R8C){^#HucyIp$ zl7FA%KmG{*0}1o!?Vf+mwB!PSEZ z8n&+t0QQ0#JAKDv?f8aYZC1OGr${(fAx$@gl4$Z~KTOSl*Ek0Y{+q$1K0V9g^)55RgkL_D}Y`JDFx_;#2To9(>cD(A??H|8|tM% zTWR72;9-Xn*Gb^-ssTKS_2gctHHLbU3KJV4Z%k|v?HfMn^GuSYhG=*J^hPOh0LdbN z=Z}>C%ig&_Sy5bjzfMswuxNz7XORi2a@CRgs+z0V)^YXzoq_j?tF7e z)~wn)YhNa~ulAwZpVj_Keh$^H%nP$-=}%r(?Mgl7_Nu)zFSqu-yxhD~^KwP|GyTcS z%4?R_482_cR$11P$x(mLm)~B=v2RkQdIOT*E5x7EvkRmjv$NZ0mt=R% z?jb+DvoFh`Qi|0HMq&Eoj)+f!SKrSI&N zWEY5Lf!fNNnpKfikv%+nj2x$DRs1*iC;zR;&5^m8EBQHBA~RPaG*==wS0Xo8A~#ne zH&-Gzw>Z)3Bfqj5%pD}ZvP#O8yqP;rekUenQ{-2oHn%kSmCx;`n@iFga|&wB7c9&v zk)N*eQ(BU{F*#!>ALxIQv;N*fd$kqSHd*XX50Nw9Il@m|y{qE;KxMHY& ziqX>?yrHV(yPRxiMHRyLMLM?o(zC%qDo?L7sc^d6E}8joq*t*McC$&j?UC$~!}=<( z(bn!asdU4zk4Sb$w@Qo*aYoOr(kt9PMbVJ_pX$w3U|;1#<%)KeO6;tY@2QSrI9(;d zIy6rxN*#jXNaTkV(`A)QL_W1juI9F%VydueoURn21B&ToU{fRmzzR^?zdh1-FONn) zQA}?_^A^2AMLPxON4k@1pUxmJLq~BjXq@g(jh2f3PmpjQ!L31}=bCUgycY89=r01X zkkqvmRBxZ)tP|QJb3%I|e6yBTb_I(;cE6P}ZdG;Ea^?HjuMs{?jcdg-E7Cm#mxA*m z8R_6z@G$tE%54MX_8BCb;ID(NkhBh;6YK$A7Hy7v34ldf63*a#asMQ64^x{CY)qW%!`*O693(incGMze93~`-?2w^3Y6y z*I;2iHV1(nNssV{H%U?Ju!QwC~`(R-)Z*ajVrcDhc|zjl%barwcx= zl2l=+>(Db5ZAW;4>PLBrg@**6Q+aS>*hu(4SZPn{^YAR;Pjc2=MK=jP3S0<2q8JUq z&bNxuPHG&l@-RYv0L^~zdeoHbjuXdB49Oa(>CgGKOL zY%h%m_+fB|N`j@}CY7WbA^%EIvWor%(+TBv6xfQ=O<{fQueYN-SOy;rzK7;U_)>5X z*g7TIGU!WtT7#WwZ3x%@DJDG%S1H1Gd5N|`YFC|Z;2`8jIrlh{9g0;)!}j9UK5o3= zDxLfGYDVNbT006p7rsPMbjB0&q8YxX7%b(iR!Hh=sojsx zFG2qj9IjleeMe_I z*OZCM9kqzQYR=O9EPH7gcbN%X-4w$n@aw>7XpRYgCz@C4RUkDm=%hU8Cti9im;pWp z?!_Cs1oskGH3P{)L5kVb4_rXhT^t_N>wUOKB=@Lgn~(iL@coLZ<4D#anFaP!4C^B= zK(ZEm9lTo6wM6GP@Vf9-@Tu5bkE9R!3&4qr=0vD>H8+5_DW>Yd7b{Aul`9JgLA;~id945Bfu_d z#};Fm@k-rCU7P6XX8h38TdU#JqP9Ef7P*ITfSyuD>u99y$6O3(xi9tiI4?t#I5 za3{FCYtXI`aE(L_gqNedVo(o(drL7IIX zaKxYe^JTQS&jrQOt!hRa`Q(D0)z(>QtslxR2wZ*=2(4F<9|{Ord%ILPRAa9ty7$`Z ziy@G7A{g-E7FC{YD%u21z*ndQyufd*yg7=i{>rIE6D|0&C|LllAFz#>kc@d{3gZ!& zaPwhR`&#kOk5(6?Hr1(W*lAHxS2d5vnq46Wk7VvjS&-g}+)zF3-{V6JDVr=Me=o~P$gpub|^h*lZ$x?5iJvTFG(5H&(tb4HUl>%CQaNV_bdw`lRo#NqCl)&#AH za(>(`Ox;33JI(n7Kf3VCiS`)rR7TM_VKUZ|CrDr;1JgaRPhQrjcKdv zBv!|Y9?~s8D5r6yt*D@xsac_2t6lRDAJAal53?9D)&0Gu`&_%-@!lm9iXP)+u@ui3 zwE@isQy2LJ+{=1)9I6+p&pKjDdsDW*Zt~ejii$(1E9wosT99njpIum+hL?u5^4GvDS^a&&M{FG(m^VPUb3g1peH8hGeI|aU z-_{AZ#41194VqsIG5l~CoVJeMk2uKj&N*&6LO;Yi=RSF3Aflu{MXf#vsl(Aw=ZsZJ zql_s=5uWofbx?6_ENF5X-&)W4f?g&>qxE>p%FiiHKZ8CRFdvvjBNHtAzEy6CEA+AX zoxwNm3DJt2Q$VCV&v8}Xnm^SGT1S@H3+of-+3hbgx~`M4;2Hx#C0D8Aw5F*G+NEHz zFAo?p#Pse3rT~Q#dH0#b!&)7RC75uT4)V1)L*Bv?{+x#ix*4<+*bD3S&+R8`^1A-G zL1TkzhKBi?XW~5$(MD6!tWaVw3ZgH+j2=*XupZvUBJ=G_;GNX}^8Yz8)Ugf1X(+@ih+$=MJ{gYXnPA9>gn1IZ|t+2`Uek%?DH{grF@ZugR?hx;MsO%+-!vuCg!TH&2bZ2x&;y|n!oc_M33Am}Gw87GV-V)GHkbfHn z^bd355aPU8jsUF_^%TY#L4_`TMy4k9S7P=3ZiM&@6%M$ACi8h$1rZ^i(NW5@+hU|g zL-Vp83>q5ODz_MSF9kE+bTLZlgIA8v>>LngB!Gxnp)V$tu{gbkLU~!)_r@M5e{@cBeujSh`WdbX92