Superminaren/MMDVM
1
0
Fork 0
mirror of https://github.com/g4klx/MMDVM.git synced 2026-10-14 15:54:11 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add submodules for F4/F7 libs

Browse Source
This commit is contained in:
Luca Marchesano
2018-06-29 09:31:01 +02:00
committed by GitHub
parent 047229d6d3
commit 0833dba9bd
72 changed files with 116688 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
STM32F7XX_Lib/Device/startup/startup_stm32f7xx.c
+519
View File
@@ -0,0 +1,519 @@
/**
******************************************************************************
* @file startup_stm32f4xx.s
* @author Coocox
* @version V1.0
* @date 03/05/2012
* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM324xG-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*/
/* Some modifications by Andy Uribe CA6JAU :
- Added C++ global constructors support
- Changed initial stack pointer
- Changed support for STM32F767
*/
/*----------Macro definition--------------------------------------------------*/
#define WEAK __attribute__ ((weak))
/*----------Declaration of the default fault handlers-------------------------*/
/* System exception vector handler */
__attribute__ ((used))
void WEAK Reset_Handler(void);
void WEAK NMI_Handler(void);
void WEAK HardFault_Handler(void);
void WEAK MemManage_Handler(void);
void WEAK BusFault_Handler(void);
void WEAK UsageFault_Handler(void);
void WEAK SVC_Handler(void);
void WEAK DebugMon_Handler(void);
void WEAK PendSV_Handler(void);
void WEAK SysTick_Handler(void);
/* External Interrupts */
void WEAK WWDG_IRQHandler(void); /* Window WatchDog */
void WEAK PVD_IRQHandler(void); /* PVD through EXTI Line detection */
void WEAK TAMP_STAMP_IRQHandler(void); /* Tamper and TimeStamps through the EXTI line */
void WEAK RTC_WKUP_IRQHandler(void); /* RTC Wakeup through the EXTI line */
void WEAK FLASH_IRQHandler(void); /* FLASH */
void WEAK RCC_IRQHandler(void); /* RCC */
void WEAK EXTI0_IRQHandler(void); /* EXTI Line0 */
void WEAK EXTI1_IRQHandler(void); /* EXTI Line1 */
void WEAK EXTI2_IRQHandler(void); /* EXTI Line2 */
void WEAK EXTI3_IRQHandler(void); /* EXTI Line3 */
void WEAK EXTI4_IRQHandler(void); /* EXTI Line4 */
void WEAK DMA1_Stream0_IRQHandler(void); /* DMA1 Stream 0 */
void WEAK DMA1_Stream1_IRQHandler(void); /* DMA1 Stream 1 */
void WEAK DMA1_Stream2_IRQHandler(void); /* DMA1 Stream 2 */
void WEAK DMA1_Stream3_IRQHandler(void); /* DMA1 Stream 3 */
void WEAK DMA1_Stream4_IRQHandler(void); /* DMA1 Stream 4 */
void WEAK DMA1_Stream5_IRQHandler(void); /* DMA1 Stream 5 */
void WEAK DMA1_Stream6_IRQHandler(void); /* DMA1 Stream 6 */
void WEAK ADC_IRQHandler(void); /* ADC1, ADC2 and ADC3s */
void WEAK CAN1_TX_IRQHandler(void); /* CAN1 TX */
void WEAK CAN1_RX0_IRQHandler(void); /* CAN1 RX0 */
void WEAK CAN1_RX1_IRQHandler(void); /* CAN1 RX1 */
void WEAK CAN1_SCE_IRQHandler(void); /* CAN1 SCE */
void WEAK EXTI9_5_IRQHandler(void); /* External Line[9:5]s */
void WEAK TIM1_BRK_TIM9_IRQHandler(void); /* TIM1 Break and TIM9 */
void WEAK TIM1_UP_TIM10_IRQHandler(void); /* TIM1 Update and TIM10 */
void WEAK TIM1_TRG_COM_TIM11_IRQHandler(void); /* TIM1 Trigger and Commutation and TIM11 */
void WEAK TIM1_CC_IRQHandler(void); /* TIM1 Capture Compare */
void WEAK TIM2_IRQHandler(void); /* TIM2 */
void WEAK TIM3_IRQHandler(void); /* TIM3 */
void WEAK TIM4_IRQHandler(void); /* TIM4 */
void WEAK I2C1_EV_IRQHandler(void); /* I2C1 Event */
void WEAK I2C1_ER_IRQHandler(void); /* I2C1 Error */
void WEAK I2C2_EV_IRQHandler(void); /* I2C2 Event */
void WEAK I2C2_ER_IRQHandler(void); /* I2C2 Error */
void WEAK SPI1_IRQHandler(void); /* SPI1 */
void WEAK SPI2_IRQHandler(void); /* SPI2 */
void WEAK USART1_IRQHandler(void); /* USART1 */
void WEAK USART2_IRQHandler(void); /* USART2 */
void WEAK USART3_IRQHandler(void); /* USART3 */
void WEAK EXTI15_10_IRQHandler(void); /* External Line[15:10]s */
void WEAK RTC_Alarm_IRQHandler(void); /* RTC Alarm (A and B) through EXTI Line */
void WEAK OTG_FS_WKUP_IRQHandler(void); /* USB OTG FS Wakeup through EXTI line */
void WEAK TIM8_BRK_TIM12_IRQHandler(void); /* TIM8 Break and TIM12 */
void WEAK TIM8_UP_TIM13_IRQHandler(void); /* TIM8 Update and TIM13 */
void WEAK TIM8_TRG_COM_TIM14_IRQHandler(void); /* TIM8 Trigger and Commutation and TIM14 */
void WEAK TIM8_CC_IRQHandler(void); /* TIM8 Capture Compare */
void WEAK DMA1_Stream7_IRQHandler(void); /* DMA1 Stream7 */
void WEAK FMC_IRQHandler(void); /* FMC */
void WEAK SDMMC1_IRQHandler(void); /* SDMMC1 */
void WEAK TIM5_IRQHandler(void); /* TIM5 */
void WEAK SPI3_IRQHandler(void); /* SPI3 */
void WEAK UART4_IRQHandler(void); /* UART4 */
void WEAK UART5_IRQHandler(void); /* UART5 */
void WEAK TIM6_DAC_IRQHandler(void); /* TIM6 and DAC1&2 underrun errors */
void WEAK TIM7_IRQHandler(void); /* TIM7 */
void WEAK DMA2_Stream0_IRQHandler(void); /* DMA2 Stream 0 */
void WEAK DMA2_Stream1_IRQHandler(void); /* DMA2 Stream 1 */
void WEAK DMA2_Stream2_IRQHandler(void); /* DMA2 Stream 2 */
void WEAK DMA2_Stream3_IRQHandler(void); /* DMA2 Stream 3 */
void WEAK DMA2_Stream4_IRQHandler(void); /* DMA2 Stream 4 */
void WEAK ETH_IRQHandler(void); /* Ethernet */
void WEAK ETH_WKUP_IRQHandler(void); /* Ethernet Wakeup through EXTI line */
void WEAK CAN2_TX_IRQHandler(void); /* CAN2 TX */
void WEAK CAN2_RX0_IRQHandler(void); /* CAN2 RX0 */
void WEAK CAN2_RX1_IRQHandler(void); /* CAN2 RX1 */
void WEAK CAN2_SCE_IRQHandler(void); /* CAN2 SCE */
void WEAK OTG_FS_IRQHandler(void); /* USB OTG FS */
void WEAK DMA2_Stream5_IRQHandler(void); /* DMA2 Stream 5 */
void WEAK DMA2_Stream6_IRQHandler(void); /* DMA2 Stream 6 */
void WEAK DMA2_Stream7_IRQHandler(void); /* DMA2 Stream 7 */
void WEAK USART6_IRQHandler(void); /* USART6 */
void WEAK I2C3_EV_IRQHandler(void); /* I2C3 event */
void WEAK I2C3_ER_IRQHandler(void); /* I2C3 error */
void WEAK OTG_HS_EP1_OUT_IRQHandler(void); /* USB OTG HS End Point 1 Out */
void WEAK OTG_HS_EP1_IN_IRQHandler(void); /* USB OTG HS End Point 1 In */
void WEAK OTG_HS_WKUP_IRQHandler(void); /* USB OTG HS Wakeup through EXTI */
void WEAK OTG_HS_IRQHandler(void); /* USB OTG HS */
void WEAK DCMI_IRQHandler(void); /* DCMI */
void WEAK RNG_IRQHandler(void); /* RNG */
void WEAK FPU_IRQHandler(void); /* FPU */
void WEAK UART7_IRQHandler(void); /* UART7 */
void WEAK UART8_IRQHandler(void); /* UART8 */
void WEAK SPI4_IRQHandler(void); /* SPI4 */
void WEAK SPI5_IRQHandler(void); /* SPI5 */
void WEAK SPI6_IRQHandler(void); /* SPI6 */
void WEAK SAI1_IRQHandler(void); /* SAI1 */
void WEAK LTDC_IRQHandler(void); /* LTDC */
void WEAK LTDC_ER_IRQHandler(void); /* LTDC error */
void WEAK DMA2D_IRQHandler(void); /* DMA2D */
void WEAK SAI2_IRQHandler(void); /* SAI2 */
void WEAK QUADSPI_IRQHandler(void); /* QUADSPI */
void WEAK LPTIM1_IRQHandler(void); /* LPTIM1 */
void WEAK CEC_IRQHandler(void); /* HDMI_CEC */
void WEAK I2C4_EV_IRQHandler(void); /* I2C4 Event */
void WEAK I2C4_ER_IRQHandler(void); /* I2C4 Error */
void WEAK SPDIF_RX_IRQHandler(void); /* SPDIF_RX */
void WEAK DFSDM1_FLT0_IRQHandler(void); /* DFSDM1 Filter 0 global Interrupt */
void WEAK DFSDM1_FLT1_IRQHandler(void); /* DFSDM1 Filter 1 global Interrupt */
void WEAK DFSDM1_FLT2_IRQHandler(void); /* DFSDM1 Filter 2 global Interrupt */
void WEAK DFSDM1_FLT3_IRQHandler(void); /* DFSDM1 Filter 3 global Interrupt */
void WEAK SDMMC2_IRQHandler(void); /* SDMMC2 */
void WEAK CAN3_TX_IRQHandler(void); /* CAN3 TX */
void WEAK CAN3_RX0_IRQHandler(void); /* CAN3 RX0 */
void WEAK CAN3_RX1_IRQHandler(void); /* CAN3 RX1 */
void WEAK CAN3_SCE_IRQHandler(void); /* CAN3 SCE */
void WEAK JPEG_IRQHandler(void); /* JPEG */
void WEAK MDIOS_IRQHandler(void); /* MDIOS */
/*----------Symbols defined in linker script----------------------------------*/
extern unsigned long _estack; /*!< The initial stack pointer */
extern unsigned long _sidata; /*!< Start address for the initialization
values of the .data section. */
extern unsigned long _sdata; /*!< Start address for the .data section */
extern unsigned long _edata; /*!< End address for the .data section */
extern unsigned long _sbss; /*!< Start address for the .bss section */
extern unsigned long _ebss; /*!< End address for the .bss section */
/* C++ global constructors support */
extern unsigned long __preinit_array_start;
extern unsigned long __preinit_array_end;
extern unsigned long __init_array_start;
extern unsigned long __init_array_end;
/*----------Function prototypes-----------------------------------------------*/
extern int main(void); /*!< The entry point for the application. */
//extern void SystemInit(void); /*!< Setup the microcontroller system(CMSIS) */
void Default_Reset_Handler(void); /*!< Default reset handler */
static void Default_Handler(void); /*!< Default exception handler */
static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline));
/**
*@brief The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x00000000.
*/
__attribute__ ((used,section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
/*----------Core Exceptions------------------------------------------------ */
(void *) &_estack, /*!< The initial stack pointer */
Reset_Handler, /*!< Reset Handler */
NMI_Handler, /*!< NMI Handler */
HardFault_Handler, /*!< Hard Fault Handler */
MemManage_Handler, /*!< MPU Fault Handler */
BusFault_Handler, /*!< Bus Fault Handler */
UsageFault_Handler, /*!< Usage Fault Handler */
0,0,0,0, /*!< Reserved */
SVC_Handler, /*!< SVCall Handler */
DebugMon_Handler, /*!< Debug Monitor Handler */
0, /*!< Reserved */
PendSV_Handler, /*!< PendSV Handler */
SysTick_Handler, /*!< SysTick Handler */
/*----------External Exceptions---------------------------------------------*/
WWDG_IRQHandler, /*!< 0: Window WatchDog */
PVD_IRQHandler, /*!< 1: PVD through EXTI Line detection */
TAMP_STAMP_IRQHandler, /*!< 2: Tamper and TimeStamps through the EXTI line*/
RTC_WKUP_IRQHandler, /*!< 3: RTC Wakeup through the EXTI line */
FLASH_IRQHandler, /*!< 4: FLASH */
RCC_IRQHandler , /*!< 5: RCC */
EXTI0_IRQHandler, /*!< 6: EXTI Line0 */
EXTI1_IRQHandler, /*!< 7: EXTI Line1 */
EXTI2_IRQHandler, /*!< 8: EXTI Line2 */
EXTI3_IRQHandler, /*!< 9: EXTI Line3 */
EXTI4_IRQHandler, /*!< 10: EXTI Line4 */
DMA1_Stream0_IRQHandler, /*!< 11: DMA1 Stream 0 */
DMA1_Stream1_IRQHandler, /*!< 12: DMA1 Stream 1 */
DMA1_Stream2_IRQHandler, /*!< 13: DMA1 Stream 2 */
DMA1_Stream3_IRQHandler, /*!< 14: DMA1 Stream 3 */
DMA1_Stream4_IRQHandler, /*!< 15: DMA1 Stream 4 */
DMA1_Stream5_IRQHandler, /*!< 16: DMA1 Stream 5 */
DMA1_Stream6_IRQHandler, /*!< 17: DMA1 Stream 6 */
ADC_IRQHandler, /*!< 18: ADC1, ADC2 and ADC3s */
CAN1_TX_IRQHandler, /*!< 19: CAN1 TX */
CAN1_RX0_IRQHandler, /*!< 20: CAN1 RX0 */
CAN1_RX1_IRQHandler, /*!< 21: CAN1 RX1 */
CAN1_SCE_IRQHandler, /*!< 22: CAN1 SCE */
EXTI9_5_IRQHandler, /*!< 23: External Line[9:5]s */
TIM1_BRK_TIM9_IRQHandler, /*!< 24: TIM1 Break and TIM9 */
TIM1_UP_TIM10_IRQHandler, /*!< 25: TIM1 Update and TIM10 */
TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/
TIM1_CC_IRQHandler, /*!< 27: TIM1 Capture Compare */
TIM2_IRQHandler, /*!< 28: TIM2 */
TIM3_IRQHandler, /*!< 29: TIM3 */
TIM4_IRQHandler, /*!< 30: TIM4 */
I2C1_EV_IRQHandler, /*!< 31: I2C1 Event */
I2C1_ER_IRQHandler, /*!< 32: I2C1 Error */
I2C2_EV_IRQHandler, /*!< 33: I2C2 Event */
I2C2_ER_IRQHandler, /*!< 34: I2C2 Error */
SPI1_IRQHandler, /*!< 35: SPI1 */
SPI2_IRQHandler, /*!< 36: SPI2 */
USART1_IRQHandler, /*!< 37: USART1 */
USART2_IRQHandler, /*!< 38: USART2 */
USART3_IRQHandler, /*!< 39: USART3 */
EXTI15_10_IRQHandler, /*!< 40: External Line[15:10]s */
RTC_Alarm_IRQHandler, /*!< 41: RTC Alarm (A and B) through EXTI Line */
OTG_FS_WKUP_IRQHandler, /*!< 42: USB OTG FS Wakeup through EXTI line */
TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12 */
TIM8_UP_TIM13_IRQHandler, /*!< 44: TIM8 Update and TIM13 */
TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/
TIM8_CC_IRQHandler, /*!< 46: TIM8 Capture Compare */
DMA1_Stream7_IRQHandler, /*!< 47: DMA1 Stream7 */
FMC_IRQHandler, /*!< 48: FSMC */
SDMMC1_IRQHandler, /*!< 49: SDIO */
TIM5_IRQHandler, /*!< 50: TIM5 */
SPI3_IRQHandler, /*!< 51: SPI3 */
UART4_IRQHandler, /*!< 52: UART4 */
UART5_IRQHandler, /*!< 53: UART5 */
TIM6_DAC_IRQHandler, /*!< 54: TIM6 and DAC1&2 underrun errors */
TIM7_IRQHandler, /*!< 55: TIM7 */
DMA2_Stream0_IRQHandler, /*!< 56: DMA2 Stream 0 */
DMA2_Stream1_IRQHandler, /*!< 57: DMA2 Stream 1 */
DMA2_Stream2_IRQHandler, /*!< 58: DMA2 Stream 2 */
DMA2_Stream3_IRQHandler, /*!< 59: DMA2 Stream 3 */
DMA2_Stream4_IRQHandler, /*!< 60: DMA2 Stream 4 */
ETH_IRQHandler, /*!< 61: Ethernet */
ETH_WKUP_IRQHandler, /*!< 62: Ethernet Wakeup through EXTI line */
CAN2_TX_IRQHandler, /*!< 63: CAN2 TX */
CAN2_RX0_IRQHandler, /*!< 64: CAN2 RX0 */
CAN2_RX1_IRQHandler, /*!< 65: CAN2 RX1 */
CAN2_SCE_IRQHandler, /*!< 66: CAN2 SCE */
OTG_FS_IRQHandler, /*!< 67: USB OTG FS */
DMA2_Stream5_IRQHandler, /*!< 68: DMA2 Stream 5 */
DMA2_Stream6_IRQHandler, /*!< 69: DMA2 Stream 6 */
DMA2_Stream7_IRQHandler, /*!< 70: DMA2 Stream 7 */
USART6_IRQHandler, /*!< 71: USART6 */
I2C3_EV_IRQHandler, /*!< 72: I2C3 event */
I2C3_ER_IRQHandler, /*!< 73: I2C3 error */
OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out */
OTG_HS_EP1_IN_IRQHandler, /*!< 75: USB OTG HS End Point 1 In */
OTG_HS_WKUP_IRQHandler, /*!< 76: USB OTG HS Wakeup through EXTI */
OTG_HS_IRQHandler, /*!< 77: USB OTG HS */
DCMI_IRQHandler, /*!< 53: DCMI */
0, /*!< Reserved */
RNG_IRQHandler, /*!< 53: Rng */
FPU_IRQHandler, /*!< 53: FPU */
UART7_IRQHandler, /* UART7 */
UART8_IRQHandler, /* UART8 */
SPI4_IRQHandler, /* SPI4 */
SPI5_IRQHandler, /* SPI5 */
SPI6_IRQHandler, /* SPI6 */
SAI1_IRQHandler, /* SAI1 */
LTDC_IRQHandler, /* LTDC */
LTDC_ER_IRQHandler, /* LTDC error */
DMA2D_IRQHandler, /* DMA2D */
SAI2_IRQHandler, /* SAI2 */
QUADSPI_IRQHandler, /* QUADSPI */
LPTIM1_IRQHandler, /* LPTIM1 */
CEC_IRQHandler, /* HDMI_CEC */
I2C4_EV_IRQHandler, /* I2C4 Event */
I2C4_ER_IRQHandler, /* I2C4 Error */
SPDIF_RX_IRQHandler, /* SPDIF_RX */
0, /* Reserved */
DFSDM1_FLT0_IRQHandler, /* DFSDM1 Filter 0 global Interrupt */
DFSDM1_FLT1_IRQHandler, /* DFSDM1 Filter 1 global Interrupt */
DFSDM1_FLT2_IRQHandler, /* DFSDM1 Filter 2 global Interrupt */
DFSDM1_FLT3_IRQHandler, /* DFSDM1 Filter 3 global Interrupt */
SDMMC2_IRQHandler, /* SDMMC2 */
CAN3_TX_IRQHandler, /* CAN3 TX */
CAN3_RX0_IRQHandler, /* CAN3 RX0 */
CAN3_RX1_IRQHandler, /* CAN3 RX1 */
CAN3_SCE_IRQHandler, /* CAN3 SCE */
JPEG_IRQHandler, /* JPEG */
MDIOS_IRQHandler /* MDIOS */
};
/* C++ global constructors support */
static void call_constructors(unsigned long *start, unsigned long *end)
{
unsigned long *i;
void (*funcptr)();
for ( i = start; i < end; i++)
{
funcptr=(void (*)())(*i);
funcptr();
}
}
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
void Default_Reset_Handler(void)
{
/* Initialize data and bss */
unsigned long *pulSrc, *pulDest;
/* Copy the data segment initializers from flash to SRAM */
pulSrc = &_sidata;
for(pulDest = &_sdata; pulDest < &_edata; )
{
*(pulDest++) = *(pulSrc++);
}
/* Zero fill the bss segment. This is done with inline assembly since this
will clear the value of pulDest if it is not kept in a register. */
__asm(" ldr r0, =_sbss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
" .thumb_func\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
#ifdef __FPU_USED
/* Enable FPU.*/
__asm(" LDR.W R0, =0xE000ED88\n"
" LDR R1, [R0]\n"
" ORR R1, R1, #(0xF << 20)\n"
" STR R1, [R0]");
#endif
SystemInit();
//Call C++ global constructors
call_constructors(&__preinit_array_start, &__preinit_array_end);
call_constructors(&__init_array_start, &__init_array_end);
/* Call the application's entry point.*/
main();
}
/**
*@brief Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*/
#pragma weak Reset_Handler = Default_Reset_Handler
#pragma weak NMI_Handler = Default_Reset_Handler
#pragma weak HardFault_Handler = Default_Reset_Handler
#pragma weak MemManage_Handler = Default_Reset_Handler
#pragma weak BusFault_Handler = Default_Reset_Handler
#pragma weak UsageFault_Handler = Default_Reset_Handler
#pragma weak SVC_Handler = Default_Reset_Handler
#pragma weak DebugMon_Handler = Default_Reset_Handler
#pragma weak PendSV_Handler = Default_Reset_Handler
#pragma weak SysTick_Handler = Default_Reset_Handler
/* External Interrupts */
#pragma weak WWDG_IRQHandler = Default_Reset_Handler /* Window WatchDog */
#pragma weak PVD_IRQHandler = Default_Reset_Handler /* PVD through EXTI Line detection */
#pragma weak TAMP_STAMP_IRQHandler = Default_Reset_Handler /* Tamper and TimeStamps through the EXTI line */
#pragma weak RTC_WKUP_IRQHandler = Default_Reset_Handler /* RTC Wakeup through the EXTI line */
#pragma weak FLASH_IRQHandler = Default_Reset_Handler /* FLASH */
#pragma weak RCC_IRQHandler = Default_Reset_Handler /* RCC */
#pragma weak EXTI0_IRQHandler = Default_Reset_Handler /* EXTI Line0 */
#pragma weak EXTI1_IRQHandler = Default_Reset_Handler /* EXTI Line1 */
#pragma weak EXTI2_IRQHandler = Default_Reset_Handler /* EXTI Line2 */
#pragma weak EXTI3_IRQHandler = Default_Reset_Handler /* EXTI Line3 */
#pragma weak EXTI4_IRQHandler = Default_Reset_Handler /* EXTI Line4 */
#pragma weak DMA1_Stream0_IRQHandler = Default_Reset_Handler /* DMA1 Stream 0 */
#pragma weak DMA1_Stream1_IRQHandler = Default_Reset_Handler /* DMA1 Stream 1 */
#pragma weak DMA1_Stream2_IRQHandler = Default_Reset_Handler /* DMA1 Stream 2 */
#pragma weak DMA1_Stream3_IRQHandler = Default_Reset_Handler /* DMA1 Stream 3 */
#pragma weak DMA1_Stream4_IRQHandler = Default_Reset_Handler /* DMA1 Stream 4 */
#pragma weak DMA1_Stream5_IRQHandler = Default_Reset_Handler /* DMA1 Stream 5 */
#pragma weak DMA1_Stream6_IRQHandler = Default_Reset_Handler /* DMA1 Stream 6 */
#pragma weak ADC_IRQHandler = Default_Reset_Handler /* ADC1, ADC2 and ADC3s */
#pragma weak CAN1_TX_IRQHandler = Default_Reset_Handler /* CAN1 TX */
#pragma weak CAN1_RX0_IRQHandler = Default_Reset_Handler /* CAN1 RX0 */
#pragma weak CAN1_RX1_IRQHandler = Default_Reset_Handler /* CAN1 RX1 */
#pragma weak CAN1_SCE_IRQHandler = Default_Reset_Handler /* CAN1 SCE */
#pragma weak EXTI9_5_IRQHandler = Default_Reset_Handler /* External Line[9:5]s */
#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Reset_Handler /* TIM1 Break and TIM9 */
#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Reset_Handler /* TIM1 Update and TIM10 */
#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Reset_Handler /* TIM1 Trigger and Commutation and TIM11 */
#pragma weak TIM1_CC_IRQHandler = Default_Reset_Handler /* TIM1 Capture Compare */
#pragma weak TIM2_IRQHandler = Default_Reset_Handler /* TIM2 */
#pragma weak TIM3_IRQHandler = Default_Reset_Handler /* TIM3 */
#pragma weak TIM4_IRQHandler = Default_Reset_Handler /* TIM4 */
#pragma weak I2C1_EV_IRQHandler = Default_Reset_Handler /* I2C1 Event */
#pragma weak I2C1_ER_IRQHandler = Default_Reset_Handler /* I2C1 Error */
#pragma weak I2C2_EV_IRQHandler = Default_Reset_Handler /* I2C2 Event */
#pragma weak I2C2_ER_IRQHandler = Default_Reset_Handler /* I2C2 Error */
#pragma weak SPI1_IRQHandler = Default_Reset_Handler /* SPI1 */
#pragma weak SPI2_IRQHandler = Default_Reset_Handler /* SPI2 */
#pragma weak USART1_IRQHandler = Default_Reset_Handler /* USART1 */
#pragma weak USART2_IRQHandler = Default_Reset_Handler /* USART2 */
#pragma weak USART3_IRQHandler = Default_Reset_Handler /* USART3 */
#pragma weak EXTI15_10_IRQHandler = Default_Reset_Handler /* External Line[15:10]s */
#pragma weak RTC_Alarm_IRQHandler = Default_Reset_Handler /* RTC Alarm (A and B) through EXTI Line */
#pragma weak OTG_FS_WKUP_IRQHandler = Default_Reset_Handler /* USB OTG FS Wakeup through EXTI line */
#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Reset_Handler /* TIM8 Break and TIM12 */
#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Reset_Handler /* TIM8 Update and TIM13 */
#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Reset_Handler /* TIM8 Trigger and Commutation and TIM14 */
#pragma weak TIM8_CC_IRQHandler = Default_Reset_Handler /* TIM8 Capture Compare */
#pragma weak DMA1_Stream7_IRQHandler = Default_Reset_Handler /* DMA1 Stream7 */
#pragma weak FMC_IRQHandler = Default_Reset_Handler /* FMC */
#pragma weak SDMMC1_IRQHandler = Default_Reset_Handler /* SDMMC1 */
#pragma weak TIM5_IRQHandler = Default_Reset_Handler /* TIM5 */
#pragma weak SPI3_IRQHandler = Default_Reset_Handler /* SPI3 */
#pragma weak UART4_IRQHandler = Default_Reset_Handler /* UART4 */
#pragma weak UART5_IRQHandler = Default_Reset_Handler /* UART5 */
#pragma weak TIM6_DAC_IRQHandler = Default_Reset_Handler /* TIM6 and DAC1&2 underrun errors */
#pragma weak TIM7_IRQHandler = Default_Reset_Handler /* TIM7 */
#pragma weak DMA2_Stream0_IRQHandler = Default_Reset_Handler /* DMA2 Stream 0 */
#pragma weak DMA2_Stream1_IRQHandler = Default_Reset_Handler /* DMA2 Stream 1 */
#pragma weak DMA2_Stream2_IRQHandler = Default_Reset_Handler /* DMA2 Stream 2 */
#pragma weak DMA2_Stream3_IRQHandler = Default_Reset_Handler /* DMA2 Stream 3 */
#pragma weak DMA2_Stream4_IRQHandler = Default_Reset_Handler /* DMA2 Stream 4 */
#pragma weak ETH_IRQHandler = Default_Reset_Handler /* Ethernet */
#pragma weak ETH_WKUP_IRQHandler = Default_Reset_Handler /* Ethernet Wakeup through EXTI line */
#pragma weak CAN2_TX_IRQHandler = Default_Reset_Handler /* CAN2 TX */
#pragma weak CAN2_RX0_IRQHandler = Default_Reset_Handler /* CAN2 RX0 */
#pragma weak CAN2_RX1_IRQHandler = Default_Reset_Handler /* CAN2 RX1 */
#pragma weak CAN2_SCE_IRQHandler = Default_Reset_Handler /* CAN2 SCE */
#pragma weak OTG_FS_IRQHandler = Default_Reset_Handler /* USB OTG FS */
#pragma weak DMA2_Stream5_IRQHandler = Default_Reset_Handler /* DMA2 Stream 5 */
#pragma weak DMA2_Stream6_IRQHandler = Default_Reset_Handler /* DMA2 Stream 6 */
#pragma weak DMA2_Stream7_IRQHandler = Default_Reset_Handler /* DMA2 Stream 7 */
#pragma weak USART6_IRQHandler = Default_Reset_Handler /* USART6 */
#pragma weak I2C3_EV_IRQHandler = Default_Reset_Handler /* I2C3 event */
#pragma weak I2C3_ER_IRQHandler = Default_Reset_Handler /* I2C3 error */
#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Reset_Handler /* USB OTG HS End Point 1 Out */
#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Reset_Handler /* USB OTG HS End Point 1 In */
#pragma weak OTG_HS_WKUP_IRQHandler = Default_Reset_Handler /* USB OTG HS Wakeup through EXTI */
#pragma weak OTG_HS_IRQHandler = Default_Reset_Handler /* USB OTG HS */
#pragma weak DCMI_IRQHandler = Default_Reset_Handler /* DCMI */
#pragma weak RNG_IRQHandler = Default_Reset_Handler /* RNG */
#pragma weak FPU_IRQHandler = Default_Reset_Handler /* FPU */
#pragma weak UART7_IRQHandler = Default_Reset_Handler /* UART7 */
#pragma weak UART8_IRQHandler = Default_Reset_Handler /* UART8 */
#pragma weak SPI4_IRQHandler = Default_Reset_Handler /* SPI4 */
#pragma weak SPI5_IRQHandler = Default_Reset_Handler /* SPI5 */
#pragma weak SPI6_IRQHandler = Default_Reset_Handler /* SPI6 */
#pragma weak SAI1_IRQHandler = Default_Reset_Handler /* SAI1 */
#pragma weak LTDC_IRQHandler = Default_Reset_Handler /* LTDC */
#pragma weak LTDC_ER_IRQHandler = Default_Reset_Handler /* LTDC error */
#pragma weak DMA2D_IRQHandler = Default_Reset_Handler /* DMA2D */
#pragma weak SAI2_IRQHandler = Default_Reset_Handler /* SAI2 */
#pragma weak QUADSPI_IRQHandler = Default_Reset_Handler /* QUADSPI */
#pragma weak LPTIM1_IRQHandler = Default_Reset_Handler /* LPTIM1 */
#pragma weak CEC_IRQHandler = Default_Reset_Handler /* HDMI_CEC */
#pragma weak I2C4_EV_IRQHandler = Default_Reset_Handler /* I2C4 Event */
#pragma weak I2C4_ER_IRQHandler = Default_Reset_Handler /* I2C4 Error */
#pragma weak SPDIF_RX_IRQHandler = Default_Reset_Handler /* SPDIF_RX */
#pragma weak DFSDM1_FLT0_IRQHandler = Default_Reset_Handler /* DFSDM1 Filter 0 global Interrupt */
#pragma weak DFSDM1_FLT1_IRQHandler = Default_Reset_Handler /* DFSDM1 Filter 1 global Interrupt */
#pragma weak DFSDM1_FLT2_IRQHandler = Default_Reset_Handler /* DFSDM1 Filter 2 global Interrupt */
#pragma weak DFSDM1_FLT3_IRQHandler = Default_Reset_Handler /* DFSDM1 Filter 3 global Interrupt */
#pragma weak SDMMC2_IRQHandler = Default_Reset_Handler /* SDMMC2 */
#pragma weak CAN3_TX_IRQHandler = Default_Reset_Handler /* CAN3 TX */
#pragma weak CAN3_RX0_IRQHandler = Default_Reset_Handler /* CAN3 RX0 */
#pragma weak CAN3_RX1_IRQHandler = Default_Reset_Handler /* CAN3 RX1 */
#pragma weak CAN3_SCE_IRQHandler = Default_Reset_Handler /* CAN3 SCE */
#pragma weak JPEG_IRQHandler = Default_Reset_Handler /* JPEG */
#pragma weak MDIOS_IRQHandler = Default_Reset_Handler /* MDIOS */
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop,
* preserving the system state for examination by a debugger.
* @param None
* @retval None
*/
static void Default_Handler(void)
{
/* Go into an infinite loop. */
while (1)
{
}
}
/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/
STM32F7XX_Lib/Device/stm32f722xx.h
+15173
View File
File diff suppressed because it is too large Load Diff
STM32F7XX_Lib/Device/stm32f767xx.h
+18607
View File
File diff suppressed because it is too large Load Diff
STM32F7XX_Lib/Device/stm32f7xx.h
+230
View File
@@ -0,0 +1,230 @@
/**
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx
* @{
*/
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F7)
#define STM32F7
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
/* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
STM32F769NG, STM32F769NI, STM32F768AI Devices */
/* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
/* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
/* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
STM32F722VC, STM32F722RC Devices */
/* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
/* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
/* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
//#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F7_CMSIS_VERSION))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F722xx)
#include "stm32f722xx.h"
#elif defined(STM32F723xx)
#include "stm32f723xx.h"
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
#include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
#elif defined(STM32F745xx)
#include "stm32f745xx.h"
#elif defined(STM32F765xx)
#include "stm32f765xx.h"
#elif defined(STM32F767xx)
#include "stm32f767xx.h"
#elif defined(STM32F769xx)
#include "stm32f769xx.h"
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
#include "stm32f779xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#ifdef USE_HAL_DRIVER
#include "stm32f7xx_hal_conf.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F7xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
STM32F7XX_Lib/Device/stm32f7xx_hal_conf.h
+228
View File
@@ -0,0 +1,228 @@
/**
******************************************************************************
* @file stm32f7xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.0
* @date 25-June-2015
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_CONF_H
#define __STM32F7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#ifndef NULL
#define NULL 0
#endif
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
#define USE_FULL_ASSERT 1
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* LAN8742A PHY Address*/
#define LAN8742A_PHY_ADDRESS 0x00
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x00000FFF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
/* Uncomment the line below to enable peripheral header file inclusion */
#include "misc.h"
#include "stm32f7xx_adc.h"
#include "stm32f7xx_dac.h"
#include "stm32f7xx_flash.h"
#include "stm32f7xx_gpio.h"
#include "stm32f7xx_pwr.h"
#include "stm32f7xx_rcc.h"
#include "stm32f7xx_tim.h"
#include "stm32f7xx_usart.h"
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
STM32F7XX_Lib/Device/system_stm32f7xx.c
+405
View File
@@ -0,0 +1,405 @@
/**
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx_system
* @{
*/
/** @addtogroup STM32F7xx_System_Private_Includes
* @{
*/
#include "stm32f7xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M (HSE_VALUE/1000000)
static void CPU_CACHE_Enable(void);
static void MPU_Config(void);
static void SetSysClock(void);
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 216000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
MPU_Config();
CPU_CACHE_Enable();
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 216000000
* HCLK(Hz) = 216000000
* AHB Prescaler = 1
* APB1 Prescaler = 4
* APB2 Prescaler = 2
* HSE Frequency(Hz) = 8000000
* PLL_M = 8
* PLL_N = 432
* PLL_P = 2
* PLL_Q = 9
* VDD(V) = 3.3
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 7
* @param None
* @retval None
*/
void SetSysClock(void)
{
RCC_HSEConfig(RCC_HSE_ON);
if ( RCC_WaitForHSEStartUp() != SUCCESS )
{
while(1);
}
RCC_PLLConfig(RCC_PLLSource_HSE, PLL_M, 432, 2, 9);
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
/* Activate the OverDrive to reach the 216 MHz Frequency */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
PWR_OverDriveCmd(ENABLE);
while(PWR_GetFlagStatus(PWR_FLAG_ODRDY) == RESET );
while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
PWR_OverDriveSWCmd(ENABLE);
while(PWR_GetFlagStatus(PWR_FLAG_ODSWRDY) == RESET );
FLASH_SetLatency(FLASH_Latency_7);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
RCC_HCLKConfig(RCC_SYSCLK_Div1);
RCC_PCLK1Config(RCC_HCLK_Div4);
RCC_PCLK2Config(RCC_HCLK_Div2);
SystemCoreClockUpdate();
}
/**
* @brief Configure the MPU attributes as Write Through for SRAM1/2.
* @note The Base Address is 0x20020000 since this memory interface is the AXI.
* The Region Size is 384KB, it is related to SRAM1 and SRAM2 memory size.
* @param None
* @retval None
*/
static void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct;
/* Disable the MPU */
MPU_Disable();
/* Configure the MPU attributes as WT for SRAM */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x20020000;
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_ConfigRegion(&MPU_InitStruct);
/* Enable the MPU */
MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief CPU L1-Cache enable.
* @param None
* @retval None
*/
static void CPU_CACHE_Enable(void)
{
/* Enable branch prediction */
SCB->CCR |= (1 <<18);
__DSB();
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
}
void assert_failed(uint8_t* file, uint32_t line)
{
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
STM32F7XX_Lib/Device/system_stm32f7xx.h
+125
View File
@@ -0,0 +1,125 @@
/**
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F7XX_H
#define __SYSTEM_STM32F7XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F7xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F7XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/