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Add submodules for F4/F7 libs
This commit is contained in:
Luca Marchesano
@@ -0,0 +1,436 @@
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/**
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******************************************************************************
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* @file startup_stm32f4xx.s
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* @author Coocox
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* @version V1.0
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* @date 03/05/2012
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* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the clock system and the external SRAM mounted on
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* STM324xG-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*/
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/* Some modifications by Andy Uribe CA6JAU :
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- Added C++ global constructors support
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- Changed initial stack pointer
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*/
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/*----------Macro definition--------------------------------------------------*/
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#define WEAK __attribute__ ((weak))
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/*----------Declaration of the default fault handlers-------------------------*/
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/* System exception vector handler */
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__attribute__ ((used))
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void WEAK Reset_Handler(void);
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void WEAK NMI_Handler(void);
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void WEAK HardFault_Handler(void);
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void WEAK MemManage_Handler(void);
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void WEAK BusFault_Handler(void);
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void WEAK UsageFault_Handler(void);
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void WEAK SVC_Handler(void);
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void WEAK DebugMon_Handler(void);
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void WEAK PendSV_Handler(void);
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void WEAK SysTick_Handler(void);
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void WEAK WWDG_IRQHandler(void);
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void WEAK PVD_IRQHandler(void);
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void WEAK TAMP_STAMP_IRQHandler(void);
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void WEAK RTC_WKUP_IRQHandler(void);
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void WEAK FLASH_IRQHandler(void);
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void WEAK RCC_IRQHandler(void);
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void WEAK EXTI0_IRQHandler(void);
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void WEAK EXTI1_IRQHandler(void);
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void WEAK EXTI2_IRQHandler(void);
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void WEAK EXTI3_IRQHandler(void);
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void WEAK EXTI4_IRQHandler(void);
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void WEAK DMA1_Stream0_IRQHandler(void);
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void WEAK DMA1_Stream1_IRQHandler(void);
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void WEAK DMA1_Stream2_IRQHandler(void);
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void WEAK DMA1_Stream3_IRQHandler(void);
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void WEAK DMA1_Stream4_IRQHandler(void);
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void WEAK DMA1_Stream5_IRQHandler(void);
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void WEAK DMA1_Stream6_IRQHandler(void);
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void WEAK ADC_IRQHandler(void);
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void WEAK CAN1_TX_IRQHandler(void);
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void WEAK CAN1_RX0_IRQHandler(void);
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void WEAK CAN1_RX1_IRQHandler(void);
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void WEAK CAN1_SCE_IRQHandler(void);
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void WEAK EXTI9_5_IRQHandler(void);
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void WEAK TIM1_BRK_TIM9_IRQHandler(void);
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void WEAK TIM1_UP_TIM10_IRQHandler(void);
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void WEAK TIM1_TRG_COM_TIM11_IRQHandler(void);
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void WEAK TIM1_CC_IRQHandler(void);
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void WEAK TIM2_IRQHandler(void);
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void WEAK TIM3_IRQHandler(void);
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void WEAK TIM4_IRQHandler(void);
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void WEAK I2C1_EV_IRQHandler(void);
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void WEAK I2C1_ER_IRQHandler(void);
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void WEAK I2C2_EV_IRQHandler(void);
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void WEAK I2C2_ER_IRQHandler(void);
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void WEAK SPI1_IRQHandler(void);
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void WEAK SPI2_IRQHandler(void);
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void WEAK USART1_IRQHandler(void);
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void WEAK USART2_IRQHandler(void);
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void WEAK USART3_IRQHandler(void);
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void WEAK EXTI15_10_IRQHandler(void);
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void WEAK RTC_Alarm_IRQHandler(void);
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void WEAK OTG_FS_WKUP_IRQHandler(void);
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void WEAK TIM8_BRK_TIM12_IRQHandler(void);
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void WEAK TIM8_UP_TIM13_IRQHandler(void);
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void WEAK TIM8_TRG_COM_TIM14_IRQHandler(void);
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void WEAK TIM8_CC_IRQHandler(void);
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void WEAK DMA1_Stream7_IRQHandler(void);
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void WEAK FSMC_IRQHandler(void);
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void WEAK SDIO_IRQHandler(void);
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void WEAK TIM5_IRQHandler(void);
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void WEAK SPI3_IRQHandler(void);
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void WEAK UART4_IRQHandler(void);
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void WEAK UART5_IRQHandler(void);
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void WEAK TIM6_DAC_IRQHandler(void);
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void WEAK TIM7_IRQHandler(void);
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void WEAK DMA2_Stream0_IRQHandler(void);
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void WEAK DMA2_Stream1_IRQHandler(void);
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void WEAK DMA2_Stream2_IRQHandler(void);
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void WEAK DMA2_Stream3_IRQHandler(void);
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void WEAK DMA2_Stream4_IRQHandler(void);
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void WEAK ETH_IRQHandler(void);
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void WEAK ETH_WKUP_IRQHandler(void);
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void WEAK CAN2_TX_IRQHandler(void);
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void WEAK CAN2_RX0_IRQHandler(void);
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void WEAK CAN2_RX1_IRQHandler(void);
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void WEAK CAN2_SCE_IRQHandler(void);
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void WEAK OTG_FS_IRQHandler(void);
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void WEAK DMA2_Stream5_IRQHandler(void);
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void WEAK DMA2_Stream6_IRQHandler(void);
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void WEAK DMA2_Stream7_IRQHandler(void);
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void WEAK USART6_IRQHandler(void);
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void WEAK I2C3_EV_IRQHandler(void);
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void WEAK I2C3_ER_IRQHandler(void);
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void WEAK OTG_HS_EP1_OUT_IRQHandler(void);
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void WEAK OTG_HS_EP1_IN_IRQHandler(void);
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void WEAK OTG_HS_WKUP_IRQHandler(void);
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void WEAK OTG_HS_IRQHandler(void);
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void WEAK DCMI_IRQHandler(void);
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void WEAK CRYP_IRQHandler(void);
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void WEAK HASH_RNG_IRQHandler(void);
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void WEAK FPU_IRQHandler(void);
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/*----------Symbols defined in linker script----------------------------------*/
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extern unsigned long _estack; /*!< The initial stack pointer */
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extern unsigned long _sidata; /*!< Start address for the initialization
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values of the .data section. */
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extern unsigned long _sdata; /*!< Start address for the .data section */
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extern unsigned long _edata; /*!< End address for the .data section */
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extern unsigned long _sbss; /*!< Start address for the .bss section */
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extern unsigned long _ebss; /*!< End address for the .bss section */
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/* C++ global constructors support */
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extern unsigned long __preinit_array_start;
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extern unsigned long __preinit_array_end;
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extern unsigned long __init_array_start;
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extern unsigned long __init_array_end;
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/*----------Function prototypes-----------------------------------------------*/
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extern int main(void); /*!< The entry point for the application. */
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//extern void SystemInit(void); /*!< Setup the microcontroller system(CMSIS) */
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void Default_Reset_Handler(void); /*!< Default reset handler */
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static void Default_Handler(void); /*!< Default exception handler */
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static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline));
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/**
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*@brief The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x00000000.
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*/
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__attribute__ ((used,section(".isr_vector")))
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void (* const g_pfnVectors[])(void) =
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{
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/*----------Core Exceptions------------------------------------------------ */
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(void *) &_estack, /*!< The initial stack pointer */
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Reset_Handler, /*!< Reset Handler */
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NMI_Handler, /*!< NMI Handler */
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HardFault_Handler, /*!< Hard Fault Handler */
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MemManage_Handler, /*!< MPU Fault Handler */
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BusFault_Handler, /*!< Bus Fault Handler */
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UsageFault_Handler, /*!< Usage Fault Handler */
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0,0,0,0, /*!< Reserved */
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SVC_Handler, /*!< SVCall Handler */
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DebugMon_Handler, /*!< Debug Monitor Handler */
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0, /*!< Reserved */
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PendSV_Handler, /*!< PendSV Handler */
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SysTick_Handler, /*!< SysTick Handler */
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/*----------External Exceptions---------------------------------------------*/
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WWDG_IRQHandler, /*!< 0: Window WatchDog */
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PVD_IRQHandler, /*!< 1: PVD through EXTI Line detection */
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TAMP_STAMP_IRQHandler, /*!< 2: Tamper and TimeStamps through the EXTI line*/
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RTC_WKUP_IRQHandler, /*!< 3: RTC Wakeup through the EXTI line */
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FLASH_IRQHandler, /*!< 4: FLASH */
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RCC_IRQHandler , /*!< 5: RCC */
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EXTI0_IRQHandler, /*!< 6: EXTI Line0 */
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EXTI1_IRQHandler, /*!< 7: EXTI Line1 */
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EXTI2_IRQHandler, /*!< 8: EXTI Line2 */
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EXTI3_IRQHandler, /*!< 9: EXTI Line3 */
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EXTI4_IRQHandler, /*!< 10: EXTI Line4 */
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DMA1_Stream0_IRQHandler, /*!< 11: DMA1 Stream 0 */
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DMA1_Stream1_IRQHandler, /*!< 12: DMA1 Stream 1 */
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DMA1_Stream2_IRQHandler, /*!< 13: DMA1 Stream 2 */
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DMA1_Stream3_IRQHandler, /*!< 14: DMA1 Stream 3 */
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DMA1_Stream4_IRQHandler, /*!< 15: DMA1 Stream 4 */
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DMA1_Stream5_IRQHandler, /*!< 16: DMA1 Stream 5 */
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DMA1_Stream6_IRQHandler, /*!< 17: DMA1 Stream 6 */
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ADC_IRQHandler, /*!< 18: ADC1, ADC2 and ADC3s */
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CAN1_TX_IRQHandler, /*!< 19: CAN1 TX */
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CAN1_RX0_IRQHandler, /*!< 20: CAN1 RX0 */
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CAN1_RX1_IRQHandler, /*!< 21: CAN1 RX1 */
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CAN1_SCE_IRQHandler, /*!< 22: CAN1 SCE */
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EXTI9_5_IRQHandler, /*!< 23: External Line[9:5]s */
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TIM1_BRK_TIM9_IRQHandler, /*!< 24: TIM1 Break and TIM9 */
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TIM1_UP_TIM10_IRQHandler, /*!< 25: TIM1 Update and TIM10 */
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TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/
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TIM1_CC_IRQHandler, /*!< 27: TIM1 Capture Compare */
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TIM2_IRQHandler, /*!< 28: TIM2 */
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TIM3_IRQHandler, /*!< 29: TIM3 */
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TIM4_IRQHandler, /*!< 30: TIM4 */
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I2C1_EV_IRQHandler, /*!< 31: I2C1 Event */
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I2C1_ER_IRQHandler, /*!< 32: I2C1 Error */
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I2C2_EV_IRQHandler, /*!< 33: I2C2 Event */
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I2C2_ER_IRQHandler, /*!< 34: I2C2 Error */
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SPI1_IRQHandler, /*!< 35: SPI1 */
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SPI2_IRQHandler, /*!< 36: SPI2 */
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USART1_IRQHandler, /*!< 37: USART1 */
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USART2_IRQHandler, /*!< 38: USART2 */
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USART3_IRQHandler, /*!< 39: USART3 */
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EXTI15_10_IRQHandler, /*!< 40: External Line[15:10]s */
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RTC_Alarm_IRQHandler, /*!< 41: RTC Alarm (A and B) through EXTI Line */
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OTG_FS_WKUP_IRQHandler, /*!< 42: USB OTG FS Wakeup through EXTI line */
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TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12 */
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TIM8_UP_TIM13_IRQHandler, /*!< 44: TIM8 Update and TIM13 */
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TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/
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TIM8_CC_IRQHandler, /*!< 46: TIM8 Capture Compare */
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DMA1_Stream7_IRQHandler, /*!< 47: DMA1 Stream7 */
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FSMC_IRQHandler, /*!< 48: FSMC */
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SDIO_IRQHandler, /*!< 49: SDIO */
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TIM5_IRQHandler, /*!< 50: TIM5 */
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SPI3_IRQHandler, /*!< 51: SPI3 */
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UART4_IRQHandler, /*!< 52: UART4 */
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UART5_IRQHandler, /*!< 53: UART5 */
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TIM6_DAC_IRQHandler, /*!< 54: TIM6 and DAC1&2 underrun errors */
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TIM7_IRQHandler, /*!< 55: TIM7 */
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DMA2_Stream0_IRQHandler, /*!< 56: DMA2 Stream 0 */
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DMA2_Stream1_IRQHandler, /*!< 57: DMA2 Stream 1 */
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DMA2_Stream2_IRQHandler, /*!< 58: DMA2 Stream 2 */
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DMA2_Stream3_IRQHandler, /*!< 59: DMA2 Stream 3 */
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DMA2_Stream4_IRQHandler, /*!< 60: DMA2 Stream 4 */
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ETH_IRQHandler, /*!< 61: Ethernet */
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ETH_WKUP_IRQHandler, /*!< 62: Ethernet Wakeup through EXTI line */
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CAN2_TX_IRQHandler, /*!< 63: CAN2 TX */
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CAN2_RX0_IRQHandler, /*!< 64: CAN2 RX0 */
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CAN2_RX1_IRQHandler, /*!< 65: CAN2 RX1 */
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CAN2_SCE_IRQHandler, /*!< 66: CAN2 SCE */
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OTG_FS_IRQHandler, /*!< 67: USB OTG FS */
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DMA2_Stream5_IRQHandler, /*!< 68: DMA2 Stream 5 */
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DMA2_Stream6_IRQHandler, /*!< 69: DMA2 Stream 6 */
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DMA2_Stream7_IRQHandler, /*!< 70: DMA2 Stream 7 */
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USART6_IRQHandler, /*!< 71: USART6 */
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I2C3_EV_IRQHandler, /*!< 72: I2C3 event */
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I2C3_ER_IRQHandler, /*!< 73: I2C3 error */
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OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out */
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OTG_HS_EP1_IN_IRQHandler, /*!< 75: USB OTG HS End Point 1 In */
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OTG_HS_WKUP_IRQHandler, /*!< 76: USB OTG HS Wakeup through EXTI */
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OTG_HS_IRQHandler, /*!< 77: USB OTG HS */
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DCMI_IRQHandler, /*!< 53: DCMI */
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CRYP_IRQHandler, /*!< 53: CRYP crypto */
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HASH_RNG_IRQHandler, /*!< 53: Hash and Rng */
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FPU_IRQHandler /*!< 53: FPU */
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};
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/* C++ global constructors support */
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static void call_constructors(unsigned long *start, unsigned long *end)
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{
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unsigned long *i;
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void (*funcptr)();
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for ( i = start; i < end; i++)
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{
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funcptr=(void (*)())(*i);
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funcptr();
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}
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}
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval None
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*/
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void Default_Reset_Handler(void)
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{
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/* Initialize data and bss */
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unsigned long *pulSrc, *pulDest;
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/* Copy the data segment initializers from flash to SRAM */
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pulSrc = &_sidata;
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for(pulDest = &_sdata; pulDest < &_edata; )
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{
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*(pulDest++) = *(pulSrc++);
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}
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/* Zero fill the bss segment. This is done with inline assembly since this
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will clear the value of pulDest if it is not kept in a register. */
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__asm(" ldr r0, =_sbss\n"
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" ldr r1, =_ebss\n"
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" mov r2, #0\n"
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" .thumb_func\n"
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"zero_loop:\n"
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" cmp r0, r1\n"
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" it lt\n"
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" strlt r2, [r0], #4\n"
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" blt zero_loop");
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#ifdef __FPU_USED
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/* Enable FPU.*/
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__asm(" LDR.W R0, =0xE000ED88\n"
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" LDR R1, [R0]\n"
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" ORR R1, R1, #(0xF << 20)\n"
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" STR R1, [R0]");
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#endif
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SystemInit();
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//Call C++ global constructors
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call_constructors(&__preinit_array_start, &__preinit_array_end);
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call_constructors(&__init_array_start, &__init_array_end);
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/* Call the application's entry point.*/
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main();
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}
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/**
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*@brief Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*/
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#pragma weak Reset_Handler = Default_Reset_Handler
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#pragma weak NMI_Handler = Default_Handler
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#pragma weak HardFault_Handler = Default_Handler
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#pragma weak MemManage_Handler = Default_Handler
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#pragma weak BusFault_Handler = Default_Handler
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#pragma weak UsageFault_Handler = Default_Handler
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#pragma weak SVC_Handler = Default_Handler
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#pragma weak DebugMon_Handler = Default_Handler
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#pragma weak PendSV_Handler = Default_Handler
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#pragma weak SysTick_Handler = Default_Handler
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#pragma weak WWDG_IRQHandler = Default_Handler
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#pragma weak PVD_IRQHandler = Default_Handler
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#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
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#pragma weak RTC_WKUP_IRQHandler = Default_Handler
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#pragma weak FLASH_IRQHandler = Default_Handler
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#pragma weak RCC_IRQHandler = Default_Handler
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#pragma weak EXTI0_IRQHandler = Default_Handler
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#pragma weak EXTI1_IRQHandler = Default_Handler
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#pragma weak EXTI2_IRQHandler = Default_Handler
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#pragma weak EXTI3_IRQHandler = Default_Handler
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#pragma weak EXTI4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
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#pragma weak ADC_IRQHandler = Default_Handler
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#pragma weak CAN1_TX_IRQHandler = Default_Handler
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#pragma weak CAN1_RX0_IRQHandler = Default_Handler
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#pragma weak CAN1_RX1_IRQHandler = Default_Handler
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#pragma weak CAN1_SCE_IRQHandler = Default_Handler
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#pragma weak EXTI9_5_IRQHandler = Default_Handler
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#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
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#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
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#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
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#pragma weak TIM1_CC_IRQHandler = Default_Handler
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#pragma weak TIM2_IRQHandler = Default_Handler
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#pragma weak TIM3_IRQHandler = Default_Handler
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#pragma weak TIM4_IRQHandler = Default_Handler
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#pragma weak I2C1_EV_IRQHandler = Default_Handler
|
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#pragma weak I2C1_ER_IRQHandler = Default_Handler
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#pragma weak I2C2_EV_IRQHandler = Default_Handler
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#pragma weak I2C2_ER_IRQHandler = Default_Handler
|
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#pragma weak SPI1_IRQHandler = Default_Handler
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#pragma weak SPI2_IRQHandler = Default_Handler
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#pragma weak USART1_IRQHandler = Default_Handler
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#pragma weak USART2_IRQHandler = Default_Handler
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#pragma weak USART3_IRQHandler = Default_Handler
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#pragma weak EXTI15_10_IRQHandler = Default_Handler
|
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#pragma weak RTC_Alarm_IRQHandler = Default_Handler
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#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
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||||
#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
|
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#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_CC_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
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||||
#pragma weak FSMC_IRQHandler = Default_Handler
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||||
#pragma weak SDIO_IRQHandler = Default_Handler
|
||||
#pragma weak TIM5_IRQHandler = Default_Handler
|
||||
#pragma weak SPI3_IRQHandler = Default_Handler
|
||||
#pragma weak UART4_IRQHandler = Default_Handler
|
||||
#pragma weak UART5_IRQHandler = Default_Handler
|
||||
#pragma weak TIM6_DAC_IRQHandler = Default_Handler
|
||||
#pragma weak TIM7_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
|
||||
#pragma weak ETH_IRQHandler = Default_Handler
|
||||
#pragma weak ETH_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_TX_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_RX0_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_RX1_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_SCE_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_FS_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
|
||||
#pragma weak USART6_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_EV_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_ER_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_IRQHandler = Default_Handler
|
||||
#pragma weak DCMI_IRQHandler = Default_Handler
|
||||
#pragma weak CRYP_IRQHandler = Default_Handler
|
||||
#pragma weak HASH_RNG_IRQHandler = Default_Handler
|
||||
#pragma weak FPU_IRQHandler = Default_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop,
|
||||
* preserving the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void Default_Handler(void)
|
||||
{
|
||||
/* Go into an infinite loop. */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CONF_H
|
||||
#define __STM32F4xx_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment the line below to enable peripheral header file inclusion */
|
||||
#include "stm32f4xx_adc.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm32f4xx_tim.h"
|
||||
#include "stm32f4xx_usart.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
/* If an external clock source is used, then the value of the following define
|
||||
should be set to the value of the external clock source, else, if no external
|
||||
clock is used, keep this define commented */
|
||||
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
|
||||
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F4xx_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,105 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.0
|
||||
* @date 22-April-2016
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user