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Add submodules for F4/F7 libs
This commit is contained in:
Luca Marchesano
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/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V4.10
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* @date 18. March 2015
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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|
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All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
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||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __CORE_CMFUNC_H
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#define __CORE_CMFUNC_H
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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#if (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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|
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/** \brief Get IPSR Register
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This function returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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|
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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|
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\return PSP Register value
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*/
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__STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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|
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|
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/** \brief Set Priority Mask
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||||
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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||||
*/
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__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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||||
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|
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#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
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|
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/** \brief Enable FIQ
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||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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||||
Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__STATIC_INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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/** \brief Set Base Priority
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This function assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xff);
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}
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/** \brief Set Base Priority with condition
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This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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or the new value increases the BASEPRI priority level.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
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{
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register uint32_t __regBasePriMax __ASM("basepri_max");
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__regBasePriMax = (basePri & 0xff);
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}
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|
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|
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/** \brief Get Fault Mask
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This function returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__STATIC_INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
|
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/** \brief Set Fault Mask
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This function assigns the given value to the Fault Mask register.
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||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
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__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & (uint32_t)1);
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}
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#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
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#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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||||
*/
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__STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPSCR
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This function assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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}
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|
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#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
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|
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|
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#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
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|
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/** \brief Enable IRQ Interrupts
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This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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{
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__ASM volatile ("cpsie i" : : : "memory");
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}
|
||||
|
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|
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/** \brief Disable IRQ Interrupts
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|
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This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
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__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
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/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority with condition
|
||||
|
||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
@@ -0,0 +1,916 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
#else
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
#endif
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __builtin_clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
@@ -0,0 +1,697 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32) ) >> 32))
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/* not yet supported */
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
Binary file not shown.
@@ -0,0 +1,436 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f4xx.s
|
||||
* @author Coocox
|
||||
* @version V1.0
|
||||
* @date 03/05/2012
|
||||
* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system and the external SRAM mounted on
|
||||
* STM324xG-EVAL board to be used as data memory (optional,
|
||||
* to be enabled by user)
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Some modifications by Andy Uribe CA6JAU :
|
||||
- Added C++ global constructors support
|
||||
- Changed initial stack pointer
|
||||
*/
|
||||
|
||||
/*----------Macro definition--------------------------------------------------*/
|
||||
#define WEAK __attribute__ ((weak))
|
||||
|
||||
/*----------Declaration of the default fault handlers-------------------------*/
|
||||
/* System exception vector handler */
|
||||
__attribute__ ((used))
|
||||
void WEAK Reset_Handler(void);
|
||||
void WEAK NMI_Handler(void);
|
||||
void WEAK HardFault_Handler(void);
|
||||
void WEAK MemManage_Handler(void);
|
||||
void WEAK BusFault_Handler(void);
|
||||
void WEAK UsageFault_Handler(void);
|
||||
void WEAK SVC_Handler(void);
|
||||
void WEAK DebugMon_Handler(void);
|
||||
void WEAK PendSV_Handler(void);
|
||||
void WEAK SysTick_Handler(void);
|
||||
|
||||
void WEAK WWDG_IRQHandler(void);
|
||||
void WEAK PVD_IRQHandler(void);
|
||||
void WEAK TAMP_STAMP_IRQHandler(void);
|
||||
void WEAK RTC_WKUP_IRQHandler(void);
|
||||
void WEAK FLASH_IRQHandler(void);
|
||||
void WEAK RCC_IRQHandler(void);
|
||||
void WEAK EXTI0_IRQHandler(void);
|
||||
void WEAK EXTI1_IRQHandler(void);
|
||||
void WEAK EXTI2_IRQHandler(void);
|
||||
void WEAK EXTI3_IRQHandler(void);
|
||||
void WEAK EXTI4_IRQHandler(void);
|
||||
void WEAK DMA1_Stream0_IRQHandler(void);
|
||||
void WEAK DMA1_Stream1_IRQHandler(void);
|
||||
void WEAK DMA1_Stream2_IRQHandler(void);
|
||||
void WEAK DMA1_Stream3_IRQHandler(void);
|
||||
void WEAK DMA1_Stream4_IRQHandler(void);
|
||||
void WEAK DMA1_Stream5_IRQHandler(void);
|
||||
void WEAK DMA1_Stream6_IRQHandler(void);
|
||||
void WEAK ADC_IRQHandler(void);
|
||||
void WEAK CAN1_TX_IRQHandler(void);
|
||||
void WEAK CAN1_RX0_IRQHandler(void);
|
||||
void WEAK CAN1_RX1_IRQHandler(void);
|
||||
void WEAK CAN1_SCE_IRQHandler(void);
|
||||
void WEAK EXTI9_5_IRQHandler(void);
|
||||
void WEAK TIM1_BRK_TIM9_IRQHandler(void);
|
||||
void WEAK TIM1_UP_TIM10_IRQHandler(void);
|
||||
void WEAK TIM1_TRG_COM_TIM11_IRQHandler(void);
|
||||
void WEAK TIM1_CC_IRQHandler(void);
|
||||
void WEAK TIM2_IRQHandler(void);
|
||||
void WEAK TIM3_IRQHandler(void);
|
||||
void WEAK TIM4_IRQHandler(void);
|
||||
void WEAK I2C1_EV_IRQHandler(void);
|
||||
void WEAK I2C1_ER_IRQHandler(void);
|
||||
void WEAK I2C2_EV_IRQHandler(void);
|
||||
void WEAK I2C2_ER_IRQHandler(void);
|
||||
void WEAK SPI1_IRQHandler(void);
|
||||
void WEAK SPI2_IRQHandler(void);
|
||||
void WEAK USART1_IRQHandler(void);
|
||||
void WEAK USART2_IRQHandler(void);
|
||||
void WEAK USART3_IRQHandler(void);
|
||||
void WEAK EXTI15_10_IRQHandler(void);
|
||||
void WEAK RTC_Alarm_IRQHandler(void);
|
||||
void WEAK OTG_FS_WKUP_IRQHandler(void);
|
||||
void WEAK TIM8_BRK_TIM12_IRQHandler(void);
|
||||
void WEAK TIM8_UP_TIM13_IRQHandler(void);
|
||||
void WEAK TIM8_TRG_COM_TIM14_IRQHandler(void);
|
||||
void WEAK TIM8_CC_IRQHandler(void);
|
||||
void WEAK DMA1_Stream7_IRQHandler(void);
|
||||
void WEAK FSMC_IRQHandler(void);
|
||||
void WEAK SDIO_IRQHandler(void);
|
||||
void WEAK TIM5_IRQHandler(void);
|
||||
void WEAK SPI3_IRQHandler(void);
|
||||
void WEAK UART4_IRQHandler(void);
|
||||
void WEAK UART5_IRQHandler(void);
|
||||
void WEAK TIM6_DAC_IRQHandler(void);
|
||||
void WEAK TIM7_IRQHandler(void);
|
||||
void WEAK DMA2_Stream0_IRQHandler(void);
|
||||
void WEAK DMA2_Stream1_IRQHandler(void);
|
||||
void WEAK DMA2_Stream2_IRQHandler(void);
|
||||
void WEAK DMA2_Stream3_IRQHandler(void);
|
||||
void WEAK DMA2_Stream4_IRQHandler(void);
|
||||
void WEAK ETH_IRQHandler(void);
|
||||
void WEAK ETH_WKUP_IRQHandler(void);
|
||||
void WEAK CAN2_TX_IRQHandler(void);
|
||||
void WEAK CAN2_RX0_IRQHandler(void);
|
||||
void WEAK CAN2_RX1_IRQHandler(void);
|
||||
void WEAK CAN2_SCE_IRQHandler(void);
|
||||
void WEAK OTG_FS_IRQHandler(void);
|
||||
void WEAK DMA2_Stream5_IRQHandler(void);
|
||||
void WEAK DMA2_Stream6_IRQHandler(void);
|
||||
void WEAK DMA2_Stream7_IRQHandler(void);
|
||||
void WEAK USART6_IRQHandler(void);
|
||||
void WEAK I2C3_EV_IRQHandler(void);
|
||||
void WEAK I2C3_ER_IRQHandler(void);
|
||||
void WEAK OTG_HS_EP1_OUT_IRQHandler(void);
|
||||
void WEAK OTG_HS_EP1_IN_IRQHandler(void);
|
||||
void WEAK OTG_HS_WKUP_IRQHandler(void);
|
||||
void WEAK OTG_HS_IRQHandler(void);
|
||||
void WEAK DCMI_IRQHandler(void);
|
||||
void WEAK CRYP_IRQHandler(void);
|
||||
void WEAK HASH_RNG_IRQHandler(void);
|
||||
void WEAK FPU_IRQHandler(void);
|
||||
|
||||
/*----------Symbols defined in linker script----------------------------------*/
|
||||
extern unsigned long _estack; /*!< The initial stack pointer */
|
||||
extern unsigned long _sidata; /*!< Start address for the initialization
|
||||
values of the .data section. */
|
||||
extern unsigned long _sdata; /*!< Start address for the .data section */
|
||||
extern unsigned long _edata; /*!< End address for the .data section */
|
||||
extern unsigned long _sbss; /*!< Start address for the .bss section */
|
||||
extern unsigned long _ebss; /*!< End address for the .bss section */
|
||||
|
||||
/* C++ global constructors support */
|
||||
extern unsigned long __preinit_array_start;
|
||||
extern unsigned long __preinit_array_end;
|
||||
extern unsigned long __init_array_start;
|
||||
extern unsigned long __init_array_end;
|
||||
|
||||
/*----------Function prototypes-----------------------------------------------*/
|
||||
extern int main(void); /*!< The entry point for the application. */
|
||||
//extern void SystemInit(void); /*!< Setup the microcontroller system(CMSIS) */
|
||||
void Default_Reset_Handler(void); /*!< Default reset handler */
|
||||
static void Default_Handler(void); /*!< Default exception handler */
|
||||
static void call_constructors(unsigned long *start, unsigned long *end) __attribute((noinline));
|
||||
|
||||
/**
|
||||
*@brief The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x00000000.
|
||||
*/
|
||||
__attribute__ ((used,section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) =
|
||||
{
|
||||
/*----------Core Exceptions------------------------------------------------ */
|
||||
(void *) &_estack, /*!< The initial stack pointer */
|
||||
Reset_Handler, /*!< Reset Handler */
|
||||
NMI_Handler, /*!< NMI Handler */
|
||||
HardFault_Handler, /*!< Hard Fault Handler */
|
||||
MemManage_Handler, /*!< MPU Fault Handler */
|
||||
BusFault_Handler, /*!< Bus Fault Handler */
|
||||
UsageFault_Handler, /*!< Usage Fault Handler */
|
||||
0,0,0,0, /*!< Reserved */
|
||||
SVC_Handler, /*!< SVCall Handler */
|
||||
DebugMon_Handler, /*!< Debug Monitor Handler */
|
||||
0, /*!< Reserved */
|
||||
PendSV_Handler, /*!< PendSV Handler */
|
||||
SysTick_Handler, /*!< SysTick Handler */
|
||||
|
||||
/*----------External Exceptions---------------------------------------------*/
|
||||
WWDG_IRQHandler, /*!< 0: Window WatchDog */
|
||||
PVD_IRQHandler, /*!< 1: PVD through EXTI Line detection */
|
||||
TAMP_STAMP_IRQHandler, /*!< 2: Tamper and TimeStamps through the EXTI line*/
|
||||
RTC_WKUP_IRQHandler, /*!< 3: RTC Wakeup through the EXTI line */
|
||||
FLASH_IRQHandler, /*!< 4: FLASH */
|
||||
RCC_IRQHandler , /*!< 5: RCC */
|
||||
EXTI0_IRQHandler, /*!< 6: EXTI Line0 */
|
||||
EXTI1_IRQHandler, /*!< 7: EXTI Line1 */
|
||||
EXTI2_IRQHandler, /*!< 8: EXTI Line2 */
|
||||
EXTI3_IRQHandler, /*!< 9: EXTI Line3 */
|
||||
EXTI4_IRQHandler, /*!< 10: EXTI Line4 */
|
||||
DMA1_Stream0_IRQHandler, /*!< 11: DMA1 Stream 0 */
|
||||
DMA1_Stream1_IRQHandler, /*!< 12: DMA1 Stream 1 */
|
||||
DMA1_Stream2_IRQHandler, /*!< 13: DMA1 Stream 2 */
|
||||
DMA1_Stream3_IRQHandler, /*!< 14: DMA1 Stream 3 */
|
||||
DMA1_Stream4_IRQHandler, /*!< 15: DMA1 Stream 4 */
|
||||
DMA1_Stream5_IRQHandler, /*!< 16: DMA1 Stream 5 */
|
||||
DMA1_Stream6_IRQHandler, /*!< 17: DMA1 Stream 6 */
|
||||
ADC_IRQHandler, /*!< 18: ADC1, ADC2 and ADC3s */
|
||||
CAN1_TX_IRQHandler, /*!< 19: CAN1 TX */
|
||||
CAN1_RX0_IRQHandler, /*!< 20: CAN1 RX0 */
|
||||
CAN1_RX1_IRQHandler, /*!< 21: CAN1 RX1 */
|
||||
CAN1_SCE_IRQHandler, /*!< 22: CAN1 SCE */
|
||||
EXTI9_5_IRQHandler, /*!< 23: External Line[9:5]s */
|
||||
TIM1_BRK_TIM9_IRQHandler, /*!< 24: TIM1 Break and TIM9 */
|
||||
TIM1_UP_TIM10_IRQHandler, /*!< 25: TIM1 Update and TIM10 */
|
||||
TIM1_TRG_COM_TIM11_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM11*/
|
||||
TIM1_CC_IRQHandler, /*!< 27: TIM1 Capture Compare */
|
||||
TIM2_IRQHandler, /*!< 28: TIM2 */
|
||||
TIM3_IRQHandler, /*!< 29: TIM3 */
|
||||
TIM4_IRQHandler, /*!< 30: TIM4 */
|
||||
I2C1_EV_IRQHandler, /*!< 31: I2C1 Event */
|
||||
I2C1_ER_IRQHandler, /*!< 32: I2C1 Error */
|
||||
I2C2_EV_IRQHandler, /*!< 33: I2C2 Event */
|
||||
I2C2_ER_IRQHandler, /*!< 34: I2C2 Error */
|
||||
SPI1_IRQHandler, /*!< 35: SPI1 */
|
||||
SPI2_IRQHandler, /*!< 36: SPI2 */
|
||||
USART1_IRQHandler, /*!< 37: USART1 */
|
||||
USART2_IRQHandler, /*!< 38: USART2 */
|
||||
USART3_IRQHandler, /*!< 39: USART3 */
|
||||
EXTI15_10_IRQHandler, /*!< 40: External Line[15:10]s */
|
||||
RTC_Alarm_IRQHandler, /*!< 41: RTC Alarm (A and B) through EXTI Line */
|
||||
OTG_FS_WKUP_IRQHandler, /*!< 42: USB OTG FS Wakeup through EXTI line */
|
||||
TIM8_BRK_TIM12_IRQHandler, /*!< 43: TIM8 Break and TIM12 */
|
||||
TIM8_UP_TIM13_IRQHandler, /*!< 44: TIM8 Update and TIM13 */
|
||||
TIM8_TRG_COM_TIM14_IRQHandler,/*!< 45:TIM8 Trigger and Commutation and TIM14*/
|
||||
TIM8_CC_IRQHandler, /*!< 46: TIM8 Capture Compare */
|
||||
DMA1_Stream7_IRQHandler, /*!< 47: DMA1 Stream7 */
|
||||
FSMC_IRQHandler, /*!< 48: FSMC */
|
||||
SDIO_IRQHandler, /*!< 49: SDIO */
|
||||
TIM5_IRQHandler, /*!< 50: TIM5 */
|
||||
SPI3_IRQHandler, /*!< 51: SPI3 */
|
||||
UART4_IRQHandler, /*!< 52: UART4 */
|
||||
UART5_IRQHandler, /*!< 53: UART5 */
|
||||
TIM6_DAC_IRQHandler, /*!< 54: TIM6 and DAC1&2 underrun errors */
|
||||
TIM7_IRQHandler, /*!< 55: TIM7 */
|
||||
DMA2_Stream0_IRQHandler, /*!< 56: DMA2 Stream 0 */
|
||||
DMA2_Stream1_IRQHandler, /*!< 57: DMA2 Stream 1 */
|
||||
DMA2_Stream2_IRQHandler, /*!< 58: DMA2 Stream 2 */
|
||||
DMA2_Stream3_IRQHandler, /*!< 59: DMA2 Stream 3 */
|
||||
DMA2_Stream4_IRQHandler, /*!< 60: DMA2 Stream 4 */
|
||||
ETH_IRQHandler, /*!< 61: Ethernet */
|
||||
ETH_WKUP_IRQHandler, /*!< 62: Ethernet Wakeup through EXTI line */
|
||||
CAN2_TX_IRQHandler, /*!< 63: CAN2 TX */
|
||||
CAN2_RX0_IRQHandler, /*!< 64: CAN2 RX0 */
|
||||
CAN2_RX1_IRQHandler, /*!< 65: CAN2 RX1 */
|
||||
CAN2_SCE_IRQHandler, /*!< 66: CAN2 SCE */
|
||||
OTG_FS_IRQHandler, /*!< 67: USB OTG FS */
|
||||
DMA2_Stream5_IRQHandler, /*!< 68: DMA2 Stream 5 */
|
||||
DMA2_Stream6_IRQHandler, /*!< 69: DMA2 Stream 6 */
|
||||
DMA2_Stream7_IRQHandler, /*!< 70: DMA2 Stream 7 */
|
||||
USART6_IRQHandler, /*!< 71: USART6 */
|
||||
I2C3_EV_IRQHandler, /*!< 72: I2C3 event */
|
||||
I2C3_ER_IRQHandler, /*!< 73: I2C3 error */
|
||||
OTG_HS_EP1_OUT_IRQHandler, /*!< 74: USB OTG HS End Point 1 Out */
|
||||
OTG_HS_EP1_IN_IRQHandler, /*!< 75: USB OTG HS End Point 1 In */
|
||||
OTG_HS_WKUP_IRQHandler, /*!< 76: USB OTG HS Wakeup through EXTI */
|
||||
OTG_HS_IRQHandler, /*!< 77: USB OTG HS */
|
||||
DCMI_IRQHandler, /*!< 53: DCMI */
|
||||
CRYP_IRQHandler, /*!< 53: CRYP crypto */
|
||||
HASH_RNG_IRQHandler, /*!< 53: Hash and Rng */
|
||||
FPU_IRQHandler /*!< 53: FPU */
|
||||
|
||||
};
|
||||
|
||||
/* C++ global constructors support */
|
||||
static void call_constructors(unsigned long *start, unsigned long *end)
|
||||
{
|
||||
unsigned long *i;
|
||||
void (*funcptr)();
|
||||
for ( i = start; i < end; i++)
|
||||
{
|
||||
funcptr=(void (*)())(*i);
|
||||
funcptr();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Default_Reset_Handler(void)
|
||||
{
|
||||
/* Initialize data and bss */
|
||||
unsigned long *pulSrc, *pulDest;
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
pulSrc = &_sidata;
|
||||
|
||||
for(pulDest = &_sdata; pulDest < &_edata; )
|
||||
{
|
||||
*(pulDest++) = *(pulSrc++);
|
||||
}
|
||||
|
||||
/* Zero fill the bss segment. This is done with inline assembly since this
|
||||
will clear the value of pulDest if it is not kept in a register. */
|
||||
__asm(" ldr r0, =_sbss\n"
|
||||
" ldr r1, =_ebss\n"
|
||||
" mov r2, #0\n"
|
||||
" .thumb_func\n"
|
||||
"zero_loop:\n"
|
||||
" cmp r0, r1\n"
|
||||
" it lt\n"
|
||||
" strlt r2, [r0], #4\n"
|
||||
" blt zero_loop");
|
||||
#ifdef __FPU_USED
|
||||
/* Enable FPU.*/
|
||||
__asm(" LDR.W R0, =0xE000ED88\n"
|
||||
" LDR R1, [R0]\n"
|
||||
" ORR R1, R1, #(0xF << 20)\n"
|
||||
" STR R1, [R0]");
|
||||
#endif
|
||||
|
||||
SystemInit();
|
||||
|
||||
//Call C++ global constructors
|
||||
call_constructors(&__preinit_array_start, &__preinit_array_end);
|
||||
call_constructors(&__init_array_start, &__init_array_end);
|
||||
|
||||
/* Call the application's entry point.*/
|
||||
main();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*@brief Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*/
|
||||
#pragma weak Reset_Handler = Default_Reset_Handler
|
||||
#pragma weak NMI_Handler = Default_Handler
|
||||
#pragma weak HardFault_Handler = Default_Handler
|
||||
#pragma weak MemManage_Handler = Default_Handler
|
||||
#pragma weak BusFault_Handler = Default_Handler
|
||||
#pragma weak UsageFault_Handler = Default_Handler
|
||||
#pragma weak SVC_Handler = Default_Handler
|
||||
#pragma weak DebugMon_Handler = Default_Handler
|
||||
#pragma weak PendSV_Handler = Default_Handler
|
||||
#pragma weak SysTick_Handler = Default_Handler
|
||||
|
||||
#pragma weak WWDG_IRQHandler = Default_Handler
|
||||
#pragma weak PVD_IRQHandler = Default_Handler
|
||||
#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
|
||||
#pragma weak RTC_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak FLASH_IRQHandler = Default_Handler
|
||||
#pragma weak RCC_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI0_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI1_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI2_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI3_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI4_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
|
||||
#pragma weak ADC_IRQHandler = Default_Handler
|
||||
#pragma weak CAN1_TX_IRQHandler = Default_Handler
|
||||
#pragma weak CAN1_RX0_IRQHandler = Default_Handler
|
||||
#pragma weak CAN1_RX1_IRQHandler = Default_Handler
|
||||
#pragma weak CAN1_SCE_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI9_5_IRQHandler = Default_Handler
|
||||
#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
|
||||
#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
|
||||
#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
|
||||
#pragma weak TIM1_CC_IRQHandler = Default_Handler
|
||||
#pragma weak TIM2_IRQHandler = Default_Handler
|
||||
#pragma weak TIM3_IRQHandler = Default_Handler
|
||||
#pragma weak TIM4_IRQHandler = Default_Handler
|
||||
#pragma weak I2C1_EV_IRQHandler = Default_Handler
|
||||
#pragma weak I2C1_ER_IRQHandler = Default_Handler
|
||||
#pragma weak I2C2_EV_IRQHandler = Default_Handler
|
||||
#pragma weak I2C2_ER_IRQHandler = Default_Handler
|
||||
#pragma weak SPI1_IRQHandler = Default_Handler
|
||||
#pragma weak SPI2_IRQHandler = Default_Handler
|
||||
#pragma weak USART1_IRQHandler = Default_Handler
|
||||
#pragma weak USART2_IRQHandler = Default_Handler
|
||||
#pragma weak USART3_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI15_10_IRQHandler = Default_Handler
|
||||
#pragma weak RTC_Alarm_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
|
||||
#pragma weak TIM8_CC_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
|
||||
#pragma weak FSMC_IRQHandler = Default_Handler
|
||||
#pragma weak SDIO_IRQHandler = Default_Handler
|
||||
#pragma weak TIM5_IRQHandler = Default_Handler
|
||||
#pragma weak SPI3_IRQHandler = Default_Handler
|
||||
#pragma weak UART4_IRQHandler = Default_Handler
|
||||
#pragma weak UART5_IRQHandler = Default_Handler
|
||||
#pragma weak TIM6_DAC_IRQHandler = Default_Handler
|
||||
#pragma weak TIM7_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
|
||||
#pragma weak ETH_IRQHandler = Default_Handler
|
||||
#pragma weak ETH_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_TX_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_RX0_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_RX1_IRQHandler = Default_Handler
|
||||
#pragma weak CAN2_SCE_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_FS_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
|
||||
#pragma weak USART6_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_EV_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_ER_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_HS_IRQHandler = Default_Handler
|
||||
#pragma weak DCMI_IRQHandler = Default_Handler
|
||||
#pragma weak CRYP_IRQHandler = Default_Handler
|
||||
#pragma weak HASH_RNG_IRQHandler = Default_Handler
|
||||
#pragma weak FPU_IRQHandler = Default_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop,
|
||||
* preserving the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void Default_Handler(void)
|
||||
{
|
||||
/* Go into an infinite loop. */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CONF_H
|
||||
#define __STM32F4xx_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment the line below to enable peripheral header file inclusion */
|
||||
#include "stm32f4xx_adc.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm32f4xx_tim.h"
|
||||
#include "stm32f4xx_usart.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
/* If an external clock source is used, then the value of the following define
|
||||
should be set to the value of the external clock source, else, if no external
|
||||
clock is used, keep this define commented */
|
||||
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
|
||||
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F4xx_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,105 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.0
|
||||
* @date 22-April-2016
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Binary file not shown.
@@ -0,0 +1,21 @@
|
||||
STM32F4XX library for MMDVM project
|
||||
|
||||
This is the STM32F4XX_Lib directory structure with just the needed code for MMDVM.
|
||||
Copy this STM32F4XX_Lib directory inside the MMDVM source code project. You have to
|
||||
conserve the STM32F4XX_Lib folder name: MMDVM/STM32F4XX_Lib
|
||||
|
||||
The source of this package can be found here:
|
||||
http://www.st.com/en/embedded-software/stsw-stm32065.html
|
||||
|
||||
In order to run the MMDVM firmware correctly, there are the following modifications
|
||||
already done in this package:
|
||||
|
||||
1) STM32F4XX_Lib/Device/startup/startup_stm32f4xx.c :
|
||||
- Added C++ global constructors support
|
||||
- Changed initial stack pointer
|
||||
|
||||
2) STM32F4XX_Lib/Device/system_stm32f4xx.c :
|
||||
- Changed PLL_M definition (support "integer" only crystal frequencies: 8, 12, 16 MHz, etc)
|
||||
|
||||
3) STM32F4XX_Lib/Device/stm32f4xx_conf.h :
|
||||
- Peripheral header file inclusions
|
||||
@@ -0,0 +1,178 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be an enumerator of @ref IRQn_Type
|
||||
enumeration (For the complete STM32 Devices IRQ Channels
|
||||
list, please refer to stm32f4xx.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,656 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_ADC_H
|
||||
#define __STM32F4xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
|
||||
This parameter can be a value of @ref ADC_resolution */
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
|
||||
is performed in Scan (multichannels)
|
||||
or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
|
||||
is performed in Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
|
||||
enable the trigger of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
|
||||
the start of conversion of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
|
||||
is left or right. This parameter can be
|
||||
a value of @ref ADC_data_align */
|
||||
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
|
||||
that will be done using the sequencer for
|
||||
regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Common Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
|
||||
independent or multi mode.
|
||||
This parameter can be a value of @ref ADC_Common_mode */
|
||||
uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
|
||||
to the ADC. The clock is common for all the ADCs.
|
||||
This parameter can be a value of @ref ADC_Prescaler */
|
||||
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
|
||||
mode for multi ADC mode.
|
||||
This parameter can be a value of
|
||||
@ref ADC_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of
|
||||
@ref ADC_delay_between_2_sampling_phases */
|
||||
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
/** @defgroup ADC_Common_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
|
||||
#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
|
||||
#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
|
||||
#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
|
||||
#define ADC_DualMode_Interl ((uint32_t)0x00000007)
|
||||
#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
|
||||
#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
|
||||
#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
|
||||
#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
|
||||
#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
|
||||
#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
|
||||
#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
|
||||
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_DualMode_InjecSimult) || \
|
||||
((MODE) == ADC_DualMode_RegSimult) || \
|
||||
((MODE) == ADC_DualMode_Interl) || \
|
||||
((MODE) == ADC_DualMode_AlterTrig) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_TripleMode_InjecSimult) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult) || \
|
||||
((MODE) == ADC_TripleMode_Interl) || \
|
||||
((MODE) == ADC_TripleMode_AlterTrig))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
|
||||
#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
|
||||
#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
|
||||
#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
|
||||
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div4) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div6) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
|
||||
#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
|
||||
#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
|
||||
#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
|
||||
((MODE) == ADC_DMAAccessMode_1) || \
|
||||
((MODE) == ADC_DMAAccessMode_2) || \
|
||||
((MODE) == ADC_DMAAccessMode_3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_delay_between_2_sampling_phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
|
||||
#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
|
||||
#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
|
||||
#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
|
||||
#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
|
||||
#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
|
||||
#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
|
||||
#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
|
||||
#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
|
||||
#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
|
||||
#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
|
||||
#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
|
||||
#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
|
||||
#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
|
||||
#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
|
||||
#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
|
||||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000)
|
||||
#define ADC_Resolution_10b ((uint32_t)0x01000000)
|
||||
#define ADC_Resolution_8b ((uint32_t)0x02000000)
|
||||
#define ADC_Resolution_6b ((uint32_t)0x03000000)
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
|
||||
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
|
||||
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
|
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
|
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
|
||||
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
#define ADC_Channel_18 ((uint8_t)0x12)
|
||||
|
||||
#if defined (STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
|
||||
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
|
||||
((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || \
|
||||
((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || \
|
||||
((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_sampling_times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
|
||||
((TIME) == ADC_SampleTime_15Cycles) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles) || \
|
||||
((TIME) == ADC_SampleTime_56Cycles) || \
|
||||
((TIME) == ADC_SampleTime_84Cycles) || \
|
||||
((TIME) == ADC_SampleTime_112Cycles) || \
|
||||
((TIME) == ADC_SampleTime_144Cycles) || \
|
||||
((TIME) == ADC_SampleTime_480Cycles))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
|
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
|
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_EOC ((uint16_t)0x0205)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0106)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0407)
|
||||
#define ADC_IT_OVR ((uint16_t)0x201A)
|
||||
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
#define ADC_FLAG_OVR ((uint8_t)0x20)
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || \
|
||||
((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT) || \
|
||||
((FLAG)== ADC_FLAG_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor, Vrefint and VBAT management functions ******************/
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
void ADC_VBATCmd(FunctionalState NewState);
|
||||
|
||||
/* Regular Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetMultiModeConversionValue(void);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
|
||||
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,304 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DAC_H
|
||||
#define __STM32F4xx_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,564 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_GPIO_H
|
||||
#define __STM32F4xx_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH) || \
|
||||
((PERIPH) == GPIOI) || \
|
||||
((PERIPH) == GPIOJ) || \
|
||||
((PERIPH) == GPIOK))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration Mode enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Output type enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Output Maximum frequency enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Low_Speed = 0x00, /*!< Low speed */
|
||||
GPIO_Medium_Speed = 0x01, /*!< Medium speed */
|
||||
GPIO_Fast_Speed = 0x02, /*!< Fast speed */
|
||||
GPIO_High_Speed = 0x03 /*!< High speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
/* Add legacy definition */
|
||||
#define GPIO_Speed_2MHz GPIO_Low_Speed
|
||||
#define GPIO_Speed_25MHz GPIO_Medium_Speed
|
||||
#define GPIO_Speed_50MHz GPIO_Fast_Speed
|
||||
#define GPIO_Speed_100MHz GPIO_High_Speed
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
|
||||
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration PullUp PullDown enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternat_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#if defined(STM32F410xx)
|
||||
#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */
|
||||
#endif /* STM32F410xx */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
|
||||
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
|
||||
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG Devices) */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection Legacy
|
||||
*/
|
||||
#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF10_DFSDM ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
#if defined(STM32F469_479xx)
|
||||
#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
|
||||
#endif /* STM32F469_479xx */
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#if defined(STM32F40_41xxx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
|
||||
#endif /* STM32F40_41xxx */
|
||||
|
||||
#if defined(STM32F401xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
|
||||
#endif /* STM32F401xx */
|
||||
|
||||
#if defined(STM32F411xE)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
|
||||
#endif /* STM32F411xE */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15))
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
|
||||
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
|
||||
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
|
||||
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
|
||||
((AF) == GPIO_AF_LTDC))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F469_479xx)
|
||||
#define IS_GPIO_AF(AF) ((AF) < 16)
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Mode_AIN GPIO_Mode_AN
|
||||
|
||||
#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
|
||||
#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
|
||||
#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the GPIO configuration to the default reset state ****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration function ****************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,982 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RCC_H
|
||||
#define __STM32F4xx_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Dual_Mode_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
|
||||
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
|
||||
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
|
||||
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLSAIDivR_Factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
|
||||
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
|
||||
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
|
||||
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE))
|
||||
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#elif defined(STM32F412xG)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#else
|
||||
#endif /* STM32F446xx */
|
||||
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
|
||||
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
|
||||
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
|
||||
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
|
||||
/* Add legacy definition */
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
|
||||
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
|
||||
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
|
||||
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
|
||||
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
|
||||
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
|
||||
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
|
||||
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
|
||||
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
|
||||
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
|
||||
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
|
||||
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
|
||||
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
|
||||
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
|
||||
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
|
||||
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
|
||||
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
|
||||
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
|
||||
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
|
||||
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
|
||||
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
|
||||
#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
|
||||
#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
/* Legacy Defines */
|
||||
#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
|
||||
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
|
||||
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
|
||||
#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
|
||||
#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
|
||||
#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
|
||||
((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_APBBus
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SBus_APB1 ((uint8_t)0x00)
|
||||
#define RCC_I2SBus_APB2 ((uint8_t)0x01)
|
||||
#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SAI_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
|
||||
#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
|
||||
#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
|
||||
#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
|
||||
|
||||
#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
|
||||
((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_Instance
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
|
||||
#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
|
||||
#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_BlockA_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
|
||||
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
|
||||
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
|
||||
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
|
||||
((SOURCE) == RCC_SAIACLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_BlockB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
|
||||
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
|
||||
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
|
||||
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
|
||||
((SOURCE) == RCC_SAIBCLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
|
||||
|
||||
/** @defgroup RCC_TIM_PRescaler_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
|
||||
#define RCC_TIMPrescActivated ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_DSI_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DSICLKSource_PHY ((uint8_t)0x00)
|
||||
#define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
|
||||
#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
|
||||
((CLKSOURCE) == RCC_DSICLKSource_PLLR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_SDIO_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
|
||||
#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
|
||||
#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
|
||||
((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RCC_48MHZ_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
|
||||
#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
|
||||
((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
|
||||
((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
|
||||
#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
|
||||
#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
|
||||
((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_CEC_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
|
||||
#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
|
||||
#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
|
||||
((CLKSOURCE) == RCC_CECCLKSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_ClockGating
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_FMPI2C1_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
|
||||
#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
|
||||
#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
|
||||
|
||||
#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/** @defgroup RCC_DFSDM_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00)
|
||||
#define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01)
|
||||
#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
|
||||
#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
|
||||
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
|
||||
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
|
||||
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
|
||||
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
|
||||
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
|
||||
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
|
||||
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
|
||||
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
|
||||
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
|
||||
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
|
||||
#if defined(STM32F410xx)
|
||||
#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
|
||||
#endif /* STM32F410xx */
|
||||
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F40_41xxx)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F40_41xxx */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#if defined(STM32F410xx)
|
||||
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
|
||||
#endif /* STM32F410xx */
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#if defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
|
||||
#endif /* STM32F446xx */
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#if defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
|
||||
#endif /* STM32F446xx */
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
|
||||
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
|
||||
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
|
||||
#if defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000)
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
|
||||
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
|
||||
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
|
||||
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
|
||||
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
|
||||
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
|
||||
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
|
||||
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
|
||||
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
|
||||
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
|
||||
((DIV) == RCC_MCO1Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
|
||||
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
|
||||
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
|
||||
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
|
||||
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
|
||||
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
|
||||
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
|
||||
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
|
||||
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
|
||||
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
|
||||
((DIV) == RCC_MCO2Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_BORRST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
|
||||
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
|
||||
void RCC_PLLI2SCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F401xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
|
||||
#endif /* STM32F40_41xxx || STM32F401xx */
|
||||
#if defined(STM32F411xE)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
|
||||
#endif /* STM32F411xE */
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
void RCC_PLLSAICmd(FunctionalState NewState);
|
||||
#if defined(STM32F469_479xx)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
|
||||
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
|
||||
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
|
||||
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
|
||||
|
||||
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
|
||||
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
|
||||
|
||||
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
|
||||
void RCC_LSEModeConfig(uint8_t RCC_Mode);
|
||||
|
||||
/* Features available only for STM32F469_479xx devices */
|
||||
#if defined(STM32F469_479xx)
|
||||
void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx devices */
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
|
||||
void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx devices */
|
||||
#if defined(STM32F410xx)
|
||||
void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
|
||||
void RCC_MCO1Cmd(FunctionalState NewState);
|
||||
void RCC_MCO2Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
|
||||
void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
|
||||
#endif /* STM32F412xG */
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,431 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_USART_H
|
||||
#define __STM32F4xx_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
|
||||
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
|
||||
|
||||
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5) || \
|
||||
((PERIPH) == USART6) || \
|
||||
((PERIPH) == UART7) || \
|
||||
((PERIPH) == UART8))
|
||||
|
||||
#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == USART6))
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_0_5) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
|
||||
/** @defgroup USART_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define USART_IT_ORE USART_IT_ORE_ER
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the USART configuration to the default reset state ***/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,249 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to configure Interrupts using driver
|
||||
* ===================================================================
|
||||
*
|
||||
* This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
* The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
*
|
||||
* 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
||||
* function according to the following table.
|
||||
|
||||
* The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
* to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
* | | | 4 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
* | | | 3 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
* | | | 2 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
* | | | 1 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
* | | | 0 bits for subpriority
|
||||
* ==========================================================================================================================
|
||||
*
|
||||
* 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
|
||||
*
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
*
|
||||
* @note IRQ priority order (sorted by highest to lowest priority):
|
||||
* - Lowest pre-emption priority
|
||||
* - Lowest subpriority
|
||||
* - Lowest hardware priority (IRQ number)
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
|
||||
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
|
||||
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,714 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
===============================================================================
|
||||
[..]
|
||||
*** DAC Channels ***
|
||||
====================
|
||||
[..]
|
||||
The device integrates two 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC channel1 with DAC_OUT1 (PA4) as output
|
||||
(#) DAC channel2 with DAC_OUT2 (PA5) as output
|
||||
|
||||
*** DAC Triggers ***
|
||||
====================
|
||||
[..]
|
||||
Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register
|
||||
using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
|
||||
[..]
|
||||
Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
|
||||
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
|
||||
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
[..]
|
||||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC wave generation feature ***
|
||||
===================================
|
||||
[..]
|
||||
Both DAC channels can be used to generate
|
||||
(#) Noise wave using DAC_WaveGeneration_Noise
|
||||
(#) Triangle wave using DAC_WaveGeneration_Triangle
|
||||
|
||||
-@- Wave generation can be disabled using DAC_WaveGeneration_None
|
||||
|
||||
*** DAC data format ***
|
||||
=======================
|
||||
[..]
|
||||
The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_Align_8b_R
|
||||
(#) 12-bit left alignment using DAC_Align_12b_L
|
||||
(#) 12-bit right alignment using DAC_Align_12b_R
|
||||
|
||||
*** DAC data value to voltage correspondence ***
|
||||
================================================
|
||||
[..]
|
||||
The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
||||
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
*** DMA requests ***
|
||||
=====================
|
||||
[..]
|
||||
A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
DAC_DMACmd()
|
||||
[..]
|
||||
DMA1 requests are mapped as following:
|
||||
(#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
|
||||
already configured
|
||||
(#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
|
||||
already configured
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC
|
||||
registers using
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using DAC_Init() function
|
||||
(+) Enable the DAC channel using DAC_Cmd() function
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 DAC channels configuration
|
||||
* @brief DAC channels configuration: trigger, output buffer, data format
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DAC channels configuration: trigger, output buffer, data format #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||
* in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger,
|
||||
wave generation, mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
|
||||
DAC_InitStruct->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the DAC channel is enabled the trigger source can no more be modified.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data: Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data: Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 DMA management functions
|
||||
* @brief DMA management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* @note When enabled DMA1 is generated when an external trigger (EXTI Line9,
|
||||
* TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
|
||||
* already configured.
|
||||
* @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
|
||||
* already configured.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before the
|
||||
* acknowledgement for the first external trigger is received (first request).
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before the
|
||||
* acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's pending flags.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before the
|
||||
* acknowledgement for the first external trigger is received (first request).
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before the
|
||||
* acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's interrupt pending bits.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before the
|
||||
* acknowledgement for the first external trigger is received (first request).
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,611 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + GPIO Read and Write
|
||||
* + GPIO Alternate functions configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
|
||||
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
|
||||
is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
|
||||
Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel or DAC
|
||||
output.
|
||||
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC and DAC, configure the desired pin in analog mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
|
||||
(+++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members
|
||||
(+++) Call GPIO_Init() function
|
||||
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
|
||||
}
|
||||
|
||||
else if (GPIOx == GPIOI)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOJ)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOK)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRH = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins..
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
|
||||
* @brief GPIO Alternate functions configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
|
||||
* @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
|
||||
* @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
|
||||
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
|
||||
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
|
||||
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
|
||||
* @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
|
||||
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
|
||||
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
|
||||
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
|
||||
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
|
||||
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
|
||||
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
|
||||
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
|
||||
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
|
||||
* @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
|
||||
* @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
|
||||
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
|
||||
* @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
|
||||
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
|
||||
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
|
||||
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
|
||||
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
|
||||
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
|
||||
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
|
||||
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
|
||||
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8
|
||||
* @arg GPIO_AF_UART7: Connect UART7 pins to AF8
|
||||
* @arg GPIO_AF_UART8: Connect UART8 pins to AF8
|
||||
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
|
||||
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
|
||||
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
|
||||
* @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
|
||||
* @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
|
||||
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
|
||||
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
|
||||
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
|
||||
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
|
||||
* @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
|
||||
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
|
||||
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
|
||||
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
|
||||
* @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
|
||||
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue
Block a user