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MMDVM
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Change the hardware sample rate and ring buffer sizes.

This commit is contained in:
Jonathan Naylor 2017-10-12 13:22:41 +01:00
parent 4a8d2d5cd1
commit e469294348
6 changed files with 19 additions and 19 deletions
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4
Globals.h
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@ -82,8 +82,8 @@ const uint8_t MARK_NONE = 0x00U;
const uint16_t RX_BLOCK_SIZE = 2U; const uint16_t RX_BLOCK_SIZE = 2U;
const uint16_t TX_RINGBUFFER_SIZE = 500U; const uint16_t TX_RINGBUFFER_SIZE = 1000U;
const uint16_t RX_RINGBUFFER_SIZE = 600U; const uint16_t RX_RINGBUFFER_SIZE = 1200U;
extern MMDVM_STATE m_modemState; extern MMDVM_STATE m_modemState;

8
IODue.cpp
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@ -140,11 +140,11 @@ void CIO::startInt()
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR |
TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_CLEAR; TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_CLEAR;
#if defined(EXTERNAL_OSC) #if defined(EXTERNAL_OSC)
t->TC_RC = EXTERNAL_OSC / 24000; // Counter resets on RC, so sets period in terms of the external clock t->TC_RC = EXTERNAL_OSC / 48000; // Counter resets on RC, so sets period in terms of the external clock
t->TC_RA = EXTERNAL_OSC / 48000; // Roughly square wave t->TC_RA = EXTERNAL_OSC / 96000; // Roughly square wave
#else #else
t->TC_RC = 1750; // Counter resets on RC, so sets period in terms of 42MHz internal clock t->TC_RC = 875; // Counter resets on RC, so sets period in terms of 42MHz internal clock
t->TC_RA = 880; // Roughly square wave t->TC_RA = 438; // Roughly square wave
#endif #endif
t->TC_CMR = (t->TC_CMR & 0xFFF0FFFF) | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET; // Set clear and set from RA and RC compares t->TC_CMR = (t->TC_CMR & 0xFFF0FFFF) | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET; // Set clear and set from RA and RC compares
t->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; // re-enable local clocking and switch to hardware trigger source. t->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; // re-enable local clocking and switch to hardware trigger source.

2
IOSTM.cpp
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@ -433,7 +433,7 @@ EXT_CLK PA15 input CN11 Pin17
const uint16_t DC_OFFSET = 2048U; const uint16_t DC_OFFSET = 2048U;
// Sampling frequency // Sampling frequency
#define SAMP_FREQ 24000 #define SAMP_FREQ 48000
extern "C" { extern "C" {
void TIM2_IRQHandler() { void TIM2_IRQHandler() {

2
IOSTM_CMSIS.cpp
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@ -103,7 +103,7 @@ USART1_RXD PA10 input (AF)
const uint16_t DC_OFFSET = 2048U; const uint16_t DC_OFFSET = 2048U;
// Sampling frequency // Sampling frequency
#define SAMP_FREQ 24000 #define SAMP_FREQ 48000
extern "C" { extern "C" {
void TIM2_IRQHandler() { void TIM2_IRQHandler() {

8
IOTeensy.cpp
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@ -112,7 +112,7 @@ void CIO::startInt()
#endif #endif
#if defined(EXTERNAL_OSC) #if defined(EXTERNAL_OSC)
// Set ADC0 to trigger from the LPTMR at 24 kHz // Set ADC0 to trigger from the LPTMR at 48 kHz
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger
SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0 SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0
@ -121,14 +121,14 @@ void CIO::startInt()
SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access
LPTMR0_CSR = 0; // Disable LPTMR0_CSR = 0; // Disable
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = (EXTERNAL_OSC / 24000) - 1; // Frequency divided by CMR + 1 LPTMR0_CMR = (EXTERNAL_OSC / 48000) - 1; // Frequency divided by CMR + 1
LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13 LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13
LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter
LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable
#else #else
// Setup PDB for ADC0 at 24 kHz // Setup PDB for ADC0 at 48 kHz
SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock
PDB0_MOD = (F_BUS / 24000) - 1; // Timer period - 1 PDB0_MOD = (F_BUS / 48000) - 1; // Timer period - 1
PDB0_IDLY = 0; // Interrupt delay PDB0_IDLY = 0; // Interrupt delay
PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0 PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0
PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode

14
TODO.txt
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@ -19,15 +19,8 @@ Jobs To Do
DMR DMR
YSF YSF
P25 P25
7. Sample ring buffer sizing
RX
TX
8. TX symbols. 8. TX symbols.
9. DC Offset workspace and clearing. 9. DC Offset workspace and clearing.
10. Hardware sample rates:
Due
STM32
Teensy
Jobs Done Jobs Done
--------- ---------
@ -38,3 +31,10 @@ Jobs Done
DMR DMR
YSF YSF
P25 P25
3. Sample ring buffer sizing
RX
TX
4. Hardware sample rates:
Due
STM32
Teensy