Merge branch 'FM' into boxcar_fm

FM.cpp

@@ -235,6 +235,7 @@ void CFM::stateMachine(bool validSignal)
   }
 
   if (m_state == FS_LISTENING && m_modemState == STATE_FM) {
+    if (!m_callsign.isWanted() && !m_rfAck.isWanted()) {
       DEBUG1("Change to STATE_IDLE");
       m_modemState = STATE_IDLE;
       m_callsignTimer.stop();
@@ -245,6 +246,7 @@ void CFM::stateMachine(bool validSignal)
       m_hangTimer.stop();
     }
   }
+}
 
 void CFM::clock(uint8_t length)
 {
@@ -279,6 +281,9 @@ void CFM::listeningState(bool validSignal)
 
     m_callsignTimer.start();
 
+    io.setDecode(true);
+    io.setADCDetection(true);
+
     DEBUG1("Change to STATE_FM");
     m_modemState = STATE_FM;
   }
@@ -297,6 +302,9 @@ void CFM::kerchunkState(bool validSignal)
       }
     }
   } else {
+    io.setDecode(false);
+    io.setADCDetection(false);
+
     DEBUG1("State to LISTENING");
     m_state = FS_LISTENING;
     m_kerchunkTimer.stop();
@@ -317,6 +325,9 @@ void CFM::relayingState(bool validSignal)
       m_timeoutTone.start();
     }
   } else {
+    io.setDecode(false);
+    io.setADCDetection(false);
+
     DEBUG1("State to RELAYING_WAIT");
     m_state = FS_RELAYING_WAIT;
     m_ackDelayTimer.start();
@@ -331,6 +342,9 @@ void CFM::relayingState(bool validSignal)
 void CFM::relayingWaitState(bool validSignal)
 {
   if (validSignal) {
+    io.setDecode(true);
+    io.setADCDetection(true);
+
     DEBUG1("State to RELAYING");
     m_state = FS_RELAYING;
     m_ackDelayTimer.stop();
@@ -366,6 +380,9 @@ void CFM::relayingWaitState(bool validSignal)
 void CFM::hangState(bool validSignal)
 {
   if (validSignal) {
+    io.setDecode(true);
+    io.setADCDetection(true);
+
     DEBUG1("State to RELAYING");
     m_state = FS_RELAYING;
     DEBUG1("Stop ack");
@@ -393,6 +410,9 @@ void CFM::hangState(bool validSignal)
 void CFM::timeoutState(bool validSignal)
 {
   if (!validSignal) {
+    io.setDecode(false);
+    io.setADCDetection(false);
+
     DEBUG1("State to TIMEOUT_WAIT");
     m_state = FS_TIMEOUT_WAIT;
     m_ackDelayTimer.start();
@@ -407,6 +427,9 @@ void CFM::timeoutState(bool validSignal)
 void CFM::timeoutWaitState(bool validSignal)
 {
   if (validSignal) {
+    io.setDecode(true);
+    io.setADCDetection(true);
+
     DEBUG1("State to TIMEOUT");
     m_state = FS_TIMEOUT;
     m_ackDelayTimer.stop();

FMKeyer.cpp

@@ -205,6 +205,11 @@ void CFMKeyer::stop()
   m_audioPos = 0U;
 }
 
+bool CFMKeyer::isWanted() const
+{
+  return m_wanted;
+}
+
 bool CFMKeyer::isRunning() const
 {
   return m_poPos > 0U || m_dotPos > 0U || m_audioPos > 0U;

FMKeyer.h

@@ -35,6 +35,8 @@ public:
 
   bool isRunning() const;
 
+  bool isWanted() const;
+
 private:
   bool     m_wanted;
   uint8_t  m_poBuffer[1000U];

Makefile

@@ -155,7 +155,7 @@ LDFLAGS_F722 =-T stm32f722_link.ld $(MCFLAGS_F7) --specs=nosys.specs $(INCLUDES_
 # Common flags
 CFLAGS=-Os -ffunction-sections -fdata-sections -fno-builtin -Wno-implicit -DCUSTOM_NEW -DNO_EXCEPTIONS
 CXXFLAGS=-Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -DCUSTOM_NEW -DNO_EXCEPTIONS
-LDFLAGS=-Os --specs=nano.specs
+LDFLAGS=-Os --specs=nano.specs -Wl,-Map=bin/mmdvm.map
 
 # Build Rules
 .PHONY: all release dis pi pi-f722 f4m nucleo f767 dvm drcc_nqf clean

NXDNTX.cpp

@@ -54,7 +54,7 @@ m_poBuffer(),
 m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(240U),     // 200ms
-m_txHang(6000U),     // 5s
+m_txHang(3000U),     // 5s
 m_txCount(0U)
 {
   ::memset(m_modState, 0x00U, 16U * sizeof(q15_t));
@@ -72,10 +72,7 @@ m_txCount(0U)
 
 void CNXDNTX::process()
 {
-  if (m_buffer.getData() == 0U && m_poLen == 0U && m_txCount == 0U)
+  if (m_poLen == 0U && m_buffer.getData() > 0U) {
-    return;
-
-  if (m_poLen == 0U) {
     if (!m_tx) {
       for (uint16_t i = 0U; i < m_txDelay; i++)
         m_poBuffer[m_poLen++] = NXDN_SYNC;
@@ -200,5 +197,5 @@ uint8_t CNXDNTX::getSpace() const
 
 void CNXDNTX::setParams(uint8_t txHang)
 {
-  m_txHang = txHang * 1200U;
+  m_txHang = txHang * 600U;
 }

P25TX.cpp

@@ -70,10 +70,7 @@ m_txCount(0U)
 
 void CP25TX::process()
 {
-  if (m_buffer.getData() == 0U && m_poLen == 0U && m_txCount == 0U)
+  if (m_poLen == 0U && m_buffer.getData() > 0U) {
-    return;
-
-  if (m_poLen == 0U) {
     if (!m_tx) {
       for (uint16_t i = 0U; i < m_txDelay; i++)
         m_poBuffer[m_poLen++] = P25_START_SYNC;

SerialPort.cpp

@@ -103,7 +103,7 @@ const uint8_t MMDVM_DEBUG5       = 0xF5U;
 #define	HW_TYPE	"MMDVM"
 #endif
 
-#define DESCRIPTION "20200512 (D-Star/DMR/System Fusion/P25/NXDN/POCSAG/FM)"
+#define DESCRIPTION "20200520 (D-Star/DMR/System Fusion/P25/NXDN/POCSAG/FM)"
 
 #if defined(GITVERSION)
 #define concat(h, a, b, c) h " " a " " b " GitID #" c ""

SerialSTM.cpp

@@ -906,7 +906,7 @@ int CSerialPort::availableForWriteInt(uint8_t n)
          #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
          return AvailForWriteUSART1();
          #elif defined(DRCC_DVM)
-         AvailForWriteUSART2();
+         return AvailForWriteUSART2();
          #else
          return AvailForWriteUART5();
          #endif

YSFTX.cpp

@@ -66,9 +66,6 @@ m_txCount(0U)
 
 void CYSFTX::process()
 {
-  if (m_buffer.getData() == 0U && m_poLen == 0U && m_txCount == 0U)
-    return;
-
   // If we have YSF data to transmit, do so.
   if (m_poLen == 0U && m_buffer.getData() > 0U) {
     if (!m_tx) {
@@ -191,4 +188,3 @@ void CYSFTX::setParams(bool on, uint8_t txHang)
   m_loDev  = on;
   m_txHang = txHang * 1200U;
 }
-

pins/pins_f4_drcc_nqf.h

@@ -22,11 +22,11 @@
 /*
 Pin definitions for DRCC_DVM BG7NQF  board rev1
 
-PTT      PB12   output
+TX/PTT_LED  PB12   output
-LED_PTT  PB4    output
+RX/COS_LED  PB5    output
-LED_COS  PB5    output
+STATUS_LED  PB10   output
-LED_SRV  PB10   output
+
-COS      PB13   input
+COS_IN      PB13   input
 
 DSTAR       N/A
 DMR         N/A
@@ -35,23 +35,27 @@ P25      N/A
 NXDN        N/A
 POCSAG      N/A
 
-MDSTAR   PB14   output
+MDMR/BIT0   PB8    output
-MDMR     PB8    output
+MYSF/BIT1   PB9    output
-MYSF     PB9    output
+MDSTAR/BIT2 PB14   output
-MP25     PB15   output
+MP25/BIT3   PB15   output          Generic Mode Pins
 MNXDN       N/A
 MPOCSAG     N/A
 
-RX       PB0    analog input
+RX          PA0    analog input
-RSSI     PB1    analog input
+RSSI        PA1    analog input
 TX          PA4    analog output
 
 EXT_CLK     PA15   input
 
 UART1_TX    PA9    output
-UART1_RX PA10   output
+UART1_RX    PA10   output          Host Data Communication
+
 UART2_TX    PA2    output
-UART2_RX PA3    output
+UART2_RX    PA3    output          Nextion Data Communication
+
+I2C1_SCL    PB6    output
+I2C1_SDA    PB7    output          OLED Data Communication as master
 
 */
 
@@ -124,13 +128,13 @@ UART2_RX PA3    output
 
 #define PIN_RX            GPIO_Pin_0
 #define PIN_RX_CH         ADC_Channel_0
-#define PORT_RX           GPIOB
+#define PORT_RX           GPIOA
-#define RCC_Per_RX        RCC_AHB1Periph_GPIOB
+#define RCC_Per_RX        RCC_AHB1Periph_GPIOA
 
 #define PIN_RSSI          GPIO_Pin_1
 #define PIN_RSSI_CH       ADC_Channel_1
-#define PORT_RSSI         GPIOB
+#define PORT_RSSI         GPIOA
-#define RCC_Per_RSSI      RCC_AHB1Periph_GPIOB
+#define RCC_Per_RSSI      RCC_AHB1Periph_GPIOA
 
 #define PIN_TX            GPIO_Pin_4
 #define PIN_TX_CH         DAC_Channel_1