mirror of https://github.com/g4klx/MMDVM.git
Follow the ETSI standard for DMO operation.
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61
DMRDMOTX.cpp
61
DMRDMOTX.cpp
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@ -41,6 +41,21 @@ const q15_t DMR_LEVELB[] = { 213, 213, 213, 213, 213};
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const q15_t DMR_LEVELC[] = {-213, -213, -213, -213, -213};
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const q15_t DMR_LEVELC[] = {-213, -213, -213, -213, -213};
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const q15_t DMR_LEVELD[] = {-640, -640, -640, -640, -640};
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const q15_t DMR_LEVELD[] = {-640, -640, -640, -640, -640};
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const uint8_t CACH_INTERLEAVE[] =
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{1U, 2U, 3U, 5U, 6U, 7U, 9U, 10U, 11U, 13U, 15U, 16U, 17U, 19U, 20U, 21U, 23U,
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25U, 26U, 27U, 29U, 30U, 31U, 33U, 34U, 35U, 37U, 39U, 40U, 41U, 43U, 44U, 45U, 47U,
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49U, 50U, 51U, 53U, 54U, 55U, 57U, 58U, 59U, 61U, 63U, 64U, 65U, 67U, 68U, 69U, 71U,
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73U, 74U, 75U, 77U, 78U, 79U, 81U, 82U, 83U, 85U, 87U, 88U, 89U, 91U, 92U, 93U, 95U};
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const uint8_t EMPTY_SHORT_LC[] =
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{0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U};
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const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02U, 0x01U};
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#define WRITE_BIT1(p,i,b) p[(i)>>3] = (b) ? (p[(i)>>3] | BIT_MASK_TABLE[(i)&7]) : (p[(i)>>3] & ~BIT_MASK_TABLE[(i)&7])
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#define READ_BIT1(p,i) (p[(i)>>3] & BIT_MASK_TABLE[(i)&7])
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const uint8_t DMR_SYNC = 0x77U;
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CDMRDMOTX::CDMRDMOTX() :
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CDMRDMOTX::CDMRDMOTX() :
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m_fifo(),
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m_fifo(),
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@ -49,7 +64,8 @@ m_modState(),
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m_poBuffer(),
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m_poBuffer(),
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m_poLen(0U),
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m_poLen(0U),
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m_poPtr(0U),
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m_poPtr(0U),
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m_txDelay(240U) // 200ms
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m_txDelay(240U), // 200ms
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m_cachPtr(0U)
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{
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{
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::memset(m_modState, 0x00U, 70U * sizeof(q15_t));
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::memset(m_modState, 0x00U, 70U * sizeof(q15_t));
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@ -63,13 +79,17 @@ void CDMRDMOTX::process()
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if (m_poLen == 0U && m_fifo.getData() > 0U) {
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if (m_poLen == 0U && m_fifo.getData() > 0U) {
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if (!m_tx) {
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if (!m_tx) {
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for (uint16_t i = 0U; i < m_txDelay; i++)
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for (uint16_t i = 0U; i < m_txDelay; i++)
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m_poBuffer[m_poLen++] = 0x00U;
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m_poBuffer[i] = DMR_SYNC;
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m_poLen = m_txDelay;
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} else {
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} else {
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for (unsigned int i = 0U; i < 72U; i++)
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createCACH(m_poBuffer + 0U, 0U);
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m_poBuffer[m_poLen++] = 0x00U;
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createCACH(m_poBuffer + 36U, 1U);
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for (unsigned int i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++)
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for (unsigned int i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++)
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m_poBuffer[i] = m_fifo.get();
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m_poBuffer[i + 3U] = m_poBuffer[i + 39U] = m_fifo.get();
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m_poLen = 72U;
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}
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}
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m_poPtr = 0U;
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m_poPtr = 0U;
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@ -149,3 +169,34 @@ void CDMRDMOTX::setTXDelay(uint8_t delay)
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m_txDelay = 240U + uint16_t(delay) * 12U; // 200ms + tx delay
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m_txDelay = 240U + uint16_t(delay) * 12U; // 200ms + tx delay
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}
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}
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void CDMRDMOTX::createCACH(uint8_t* buffer, uint8_t slotIndex)
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{
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if (m_cachPtr >= 12U)
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m_cachPtr = 0U;
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::memcpy(buffer, EMPTY_SHORT_LC + m_cachPtr, 3U);
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bool at = true;
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bool tc = slotIndex == 1U;
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bool ls0 = true; // For 1 and 2
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bool ls1 = true;
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if (m_cachPtr == 0U) // For 0
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ls1 = false;
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else if (m_cachPtr == 9U) // For 3
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ls0 = false;
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bool h0 = at ^ tc ^ ls1;
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bool h1 = tc ^ ls1 ^ ls0;
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bool h2 = at ^ tc ^ ls0;
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buffer[0U] |= at ? 0x80U : 0x00U;
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buffer[0U] |= tc ? 0x08U : 0x00U;
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buffer[1U] |= ls1 ? 0x80U : 0x00U;
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buffer[1U] |= ls0 ? 0x08U : 0x00U;
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buffer[1U] |= h0 ? 0x02U : 0x00U;
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buffer[2U] |= h1 ? 0x20U : 0x00U;
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buffer[2U] |= h2 ? 0x02U : 0x00U;
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m_cachPtr += 3U;
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}
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@ -41,11 +41,13 @@ private:
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CSerialRB m_fifo;
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CSerialRB m_fifo;
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arm_fir_instance_q15 m_modFilter;
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arm_fir_instance_q15 m_modFilter;
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q15_t m_modState[70U]; // NoTaps + BlockSize - 1, 42 + 20 - 1 plus some spare
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q15_t m_modState[70U]; // NoTaps + BlockSize - 1, 42 + 20 - 1 plus some spare
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uint8_t m_poBuffer[1200U];
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uint8_t m_poBuffer[800U];
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uint16_t m_poLen;
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uint16_t m_poLen;
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uint16_t m_poPtr;
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uint16_t m_poPtr;
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uint32_t m_txDelay;
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uint32_t m_txDelay;
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uint8_t m_cachPtr;
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void createCACH(uint8_t* buffer, uint8_t slotIndex);
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void writeByte(uint8_t c);
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void writeByte(uint8_t c);
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};
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};
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