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MMDVM
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Disable ADC clocks.

This commit is contained in:
Jonathan Naylor 2016-11-28 16:20:51 +00:00 committed by GitHub
parent 4584b20c45
commit 91b4dddd8b
1 changed files with 2 additions and 2 deletions
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4
IOTeensy.cpp
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@ -76,7 +76,7 @@ void CIO::initInt()
void CIO::startInt() void CIO::startInt()
{ {
// Initialise ADC0 // Initialise ADC0
SIM_SCGC6 |= SIM_SCGC6_ADC0; // SIM_SCGC6 |= SIM_SCGC6_ADC0;
ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
@ -97,7 +97,7 @@ void CIO::startInt()
#if defined(SEND_RSSI_DATA) #if defined(SEND_RSSI_DATA)
// Initialise ADC1 // Initialise ADC1
SIM_SCGC3 |= SIM_SCGC3_ADC1; // SIM_SCGC3 |= SIM_SCGC3_ADC1;
ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb