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Merge pull request #278 from shawnchain/drcc_serial_bugfix 

Drcc serial bugfix
This commit is contained in:
Jonathan Naylor 2020-05-18 06:34:09 +01:00 committed by GitHub
parent ff375abb0e 6397c720e8
commit 89b8641955
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 35 additions and 31 deletions
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2
Makefile
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@ -155,7 +155,7 @@ LDFLAGS_F722 =-T stm32f722_link.ld $(MCFLAGS_F7) --specs=nosys.specs $(INCLUDES_
# Common flags # Common flags
CFLAGS=-Os -ffunction-sections -fdata-sections -fno-builtin -Wno-implicit -DCUSTOM_NEW -DNO_EXCEPTIONS CFLAGS=-Os -ffunction-sections -fdata-sections -fno-builtin -Wno-implicit -DCUSTOM_NEW -DNO_EXCEPTIONS
CXXFLAGS=-Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -DCUSTOM_NEW -DNO_EXCEPTIONS CXXFLAGS=-Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -DCUSTOM_NEW -DNO_EXCEPTIONS
LDFLAGS=-Os --specs=nano.specs LDFLAGS=-Os --specs=nano.specs -Wl,-Map=bin/mmdvm.map
# Build Rules # Build Rules
.PHONY: all release dis pi pi-f722 f4m nucleo f767 dvm drcc_nqf clean .PHONY: all release dis pi pi-f722 f4m nucleo f767 dvm drcc_nqf clean

2
SerialSTM.cpp
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@ -906,7 +906,7 @@ int CSerialPort::availableForWriteInt(uint8_t n)
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
return AvailForWriteUSART1(); return AvailForWriteUSART1();
#elif defined(DRCC_DVM) #elif defined(DRCC_DVM)
AvailForWriteUSART2(); return AvailForWriteUSART2();
#else #else
return AvailForWriteUART5(); return AvailForWriteUART5();
#endif #endif

38
pins/pins_f4_drcc_nqf.h
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@ -22,11 +22,11 @@
/* /*
Pin definitions for DRCC_DVM BG7NQF board rev1 Pin definitions for DRCC_DVM BG7NQF board rev1
PTT PB12 output TX/PTT_LED PB12 output
LED_PTT PB4 output RX/COS_LED PB5 output
LED_COS PB5 output STATUS_LED PB10 output
LED_SRV PB10 output
COS PB13 input COS_IN PB13 input
DSTAR N/A DSTAR N/A
DMR N/A DMR N/A
@ -35,23 +35,27 @@ P25 N/A
NXDN N/A NXDN N/A
POCSAG N/A POCSAG N/A
MDSTAR PB14 output MDMR/BIT0 PB8 output
MDMR PB8 output MYSF/BIT1 PB9 output
MYSF PB9 output MDSTAR/BIT2 PB14 output
MP25 PB15 output MP25/BIT3 PB15 output Generic Mode Pins
MNXDN N/A MNXDN N/A
MPOCSAG N/A MPOCSAG N/A
RX PB0 analog input RX PA0 analog input
RSSI PB1 analog input RSSI PA1 analog input
TX PA4 analog output TX PA4 analog output
EXT_CLK PA15 input EXT_CLK PA15 input
UART1_TX PA9 output UART1_TX PA9 output
UART1_RX PA10 output UART1_RX PA10 output Host Data Communication
UART2_TX PA2 output UART2_TX PA2 output
UART2_RX PA3 output UART2_RX PA3 output Nextion Data Communication
I2C1_SCL PB6 output
I2C1_SDA PB7 output OLED Data Communication as master
*/ */
@ -124,13 +128,13 @@ UART2_RX PA3 output
#define PIN_RX GPIO_Pin_0 #define PIN_RX GPIO_Pin_0
#define PIN_RX_CH ADC_Channel_0 #define PIN_RX_CH ADC_Channel_0
#define PORT_RX GPIOB #define PORT_RX GPIOA
#define RCC_Per_RX RCC_AHB1Periph_GPIOB #define RCC_Per_RX RCC_AHB1Periph_GPIOA
#define PIN_RSSI GPIO_Pin_1 #define PIN_RSSI GPIO_Pin_1
#define PIN_RSSI_CH ADC_Channel_1 #define PIN_RSSI_CH ADC_Channel_1
#define PORT_RSSI GPIOB #define PORT_RSSI GPIOA
#define RCC_Per_RSSI RCC_AHB1Periph_GPIOB #define RCC_Per_RSSI RCC_AHB1Periph_GPIOA
#define PIN_TX GPIO_Pin_4 #define PIN_TX GPIO_Pin_4
#define PIN_TX_CH DAC_Channel_1 #define PIN_TX_CH DAC_Channel_1