Superminaren
/
MMDVM
mirror of https://github.com/g4klx/MMDVM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #96 from N4IRS/master 

Fix USART2 to USART1 after PR 94
This commit is contained in:
Jonathan Naylor 2017-06-04 14:40:41 +01:00 committed by GitHub
parent 8a5d5bc286 00a7f15011
commit 61b05dd5af
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
IOSTM_CMSIS.cpp
View File

@ -151,17 +151,17 @@ void FancyLEDEffect()
for(int i=0; i<7; i++){ for(int i=0; i<7; i++){
*foo[i] = 0x01; *foo[i] = 0x01;
} }
GPIOConfigPin(PORT_USART2_TXD, PIN_USART2_TXD, GPIO_CRL_MODE0_1); GPIOConfigPin(PORT_USART1_TXD, PIN_USART1_TXD, GPIO_CRL_MODE0_1);
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x00; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x00;
delay(SystemCoreClock/1000*100); delay(SystemCoreClock/1000*100);
for(int i=0; i<7; i++){ for(int i=0; i<7; i++){
*foo[i] = 0x00; *foo[i] = 0x00;
} }
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x01; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x01;
delay(SystemCoreClock/1000*20); delay(SystemCoreClock/1000*20);
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x00; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x00;
delay(SystemCoreClock/1000*10); delay(SystemCoreClock/1000*10);
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x01; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x01;
*foo[0] = 0x01; *foo[0] = 0x01;
for(int i=1; i<7; i++){ for(int i=1; i<7; i++){
@ -176,10 +176,10 @@ void FancyLEDEffect()
} }
delay(SystemCoreClock/1000*10); delay(SystemCoreClock/1000*10);
*foo[5+1-6] = 0x00; *foo[5+1-6] = 0x00;
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x00; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x00;
delay(SystemCoreClock/1000*10); delay(SystemCoreClock/1000*10);
*((bitband_t)BITBAND_PERIPH(&PORT_USART2_TXD->ODR, PIN_USART2_TXD)) = 0x01; *((bitband_t)BITBAND_PERIPH(&PORT_USART1_TXD->ODR, PIN_USART1_TXD)) = 0x01;
GPIOConfigPin(PORT_USART2_TXD, PIN_USART2_TXD, GPIO_CRL_MODE0_1|GPIO_CRL_CNF0_1); GPIOConfigPin(PORT_USART1_TXD, PIN_USART1_TXD, GPIO_CRL_MODE0_1|GPIO_CRL_CNF0_1);
delay(SystemCoreClock/1000*50); delay(SystemCoreClock/1000*50);
} }
#endif #endif