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MMDVM
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phl0 2016-11-30 13:17:36 +01:00
parent d022276c94
commit 51faaed880
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1 changed files with 10 additions and 8 deletions
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16
IOTeensy.cpp
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@ -34,8 +34,8 @@
#define PIN_DMR 10 #define PIN_DMR 10
#define PIN_YSF 11 #define PIN_YSF 11
#define PIN_P25 12 #define PIN_P25 12
#define PIN_ADC 5 // A0 #define PIN_ADC 5 // A0, Pin 14
#define PIN_RSSI 8 // A2 #define PIN_RSSI 8 // A2, Pin 16
#define PDB_CHnC1_TOS 0x0100 #define PDB_CHnC1_TOS 0x0100
#define PDB_CHnC1_EN 0x0001 #define PDB_CHnC1_EN 0x0001
@ -123,16 +123,18 @@ void CIO::startInt()
#if defined(EXTERNAL_OSC) #if defined(EXTERNAL_OSC)
// Set ADC0 to trigger from the LPTMR at 24 kHz // Set ADC0 to trigger from the LPTMR at 24 kHz
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger
SIM_SOPT7_ADC0TRGSEL(14); SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0
CORE_PIN13_CONFIG = PORT_PCR_MUX(3); CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
SIM_SCGC5 |= SIM_SCGC5_LPTIMER; SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = EXTERNAL_OSC / 24000; LPTMR0_CMR = EXTERNAL_OSC / 24000;
LPTMR0_CSR = LPTMR_CSR_TIE | LPTMR_CSR_TPS(2) | // Interrupt, counter, input=Alt2, free running mode LPTMR0_CSR = LPTMR_CSR_TIE | // Interrupt Enable
LPTMR_CSR_TFC | LPTMR_CSR_TMS; LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13
LPTMR_CSR_TFC | // Free-Running Counter
LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter
LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable
#else #else
// Setup PDB for ADC0 at 24 kHz // Setup PDB for ADC0 at 24 kHz