mirror of https://github.com/g4klx/MMDVM.git
Use information from STM32Cube to update the I2C driver.
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115
I2CPort.cpp
115
I2CPort.cpp
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@ -24,6 +24,7 @@
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#include "Globals.h"
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const uint16_t MAX_NBYTES_SIZE = 255U;
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CI2CPort::CI2CPort(uint8_t n) :
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m_port(NULL),
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@ -97,11 +98,11 @@ bool CI2CPort::init()
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// Configure and Initialize the I2C
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I2C_InitTypeDef I2C_InitStructure;
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I2C_InitStructure.I2C_Timing = 50000U; //400kHz (Fast Mode)
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I2C_InitStructure.I2C_Timing = 0x0010061AU; // 400kHz (Fast Mode)
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I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
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I2C_InitStructure.I2C_DigitalFilter = 7U;
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I2C_InitStructure.I2C_DigitalFilter = 0U; // No digital filter
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I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
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I2C_InitStructure.I2C_OwnAddress1 = 0x00U; //We are the master. We don't need this
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I2C_InitStructure.I2C_OwnAddress1 = 0x00U; // We are the master. We don't need this
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I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
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I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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@ -121,68 +122,49 @@ uint8_t CI2CPort::write(uint8_t addr, const uint8_t* data, uint16_t length)
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if (!m_ok)
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return 6U;
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// Generate a start condition. (As soon as the line becomes idle, a Start condition will be generated)
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m_port->CR2 |= I2C_CR2_START;
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// Wait for the I2C transmitter to become free
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if (waitISRFlagsSet(I2C_ISR_BUSY))
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return 6U;
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// Set I2C device address if needed
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if (addr != m_addr) {
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bool ret = setAddr(addr, I2C_Direction_Transmitter);
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if (!ret)
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return 7U;
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m_addr = addr;
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}
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// Unstretch the clock by just reading ISR (Physically the clock is continued to be strectehed because we have not written anything to the TXDR yet.)
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(void)m_port->ISR;
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// Configure the data transfer
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uint16_t size;
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if (length > MAX_NBYTES_SIZE)
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size = MAX_NBYTES_SIZE;
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else
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size = length;
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configureDataTransfer(size);
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// Start Writing Data
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while (length--) {
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bool ret = write(*data++);
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if (!ret)
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return 7U;
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while (length > 0U) {
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// Wait for the TXIS flag to be set
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if (waitISRFlagsSet(I2C_ISR_TXIS))
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return 6U;
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// Write the byte to the TXDR
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m_port->TXDR = *data++;
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length--;
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size--;
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// Configure the data transfer
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if (size == 0U && length > 0U) {
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if (length > MAX_NBYTES_SIZE)
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size = MAX_NBYTES_SIZE;
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else
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size = length;
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configureDataTransfer(size);
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}
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}
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// Wait for the data on the shift register to be transmitted completely
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bool ret = waitISRFlagsSet(I2C_ISR_TC);
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if (!ret)
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return 7U;
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if (waitISRFlagsSet(I2C_ISR_STOPF))
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return 6U;
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// Here TXE=BTF=1. Therefore the clock stretches again.
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m_port->ISR &= ~I2C_ISR_STOPF;
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// Order a stop condition at the end of the current tranmission (or if the clock is being streched, generate stop immediatelly)
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m_port->CR2 |= I2C_CR2_STOP;
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// Stop condition resets the TXE and BTF automatically.
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// Wait to be sure that line is iddle
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ret = waitLineIdle();
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if (!ret)
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return 7U;
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m_port->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));
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return 0U;
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}
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bool CI2CPort::write(uint8_t c)
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{
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// Write the byte to the TXDR
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m_port->TXDR = c;
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// Wait till the content of TXDR is transferred to the shift Register.
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return waitISRFlagsSet(I2C_ISR_TXE);
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}
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bool CI2CPort::setAddr(uint8_t addr, uint8_t dir)
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{
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// Write address to the TXDR (to the bus)
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m_port->TXDR = (addr << 1) | dir;
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// Wait till ADDR is set (ADDR is set when the slave sends ACK to the address).
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// Clock streches till ADDR is Reset. To reset the hardware i)Read the SR1 ii)Wait till ADDR is Set iii)Read SR2
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// Note1:Spec_p602 recommends the waiting operation
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return waitISRFlagsSet(I2C_ISR_ADDR);
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}
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bool CI2CPort::waitISRFlagsSet(uint32_t flags)
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{
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// Wait till the specified ISR Bits are set
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@ -197,20 +179,19 @@ bool CI2CPort::waitISRFlagsSet(uint32_t flags)
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return true;
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}
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bool CI2CPort::waitLineIdle()
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void CI2CPort::configureDataTransfer(uint8_t size)
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{
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// Wait till the Line becomes idle.
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uint32_t timeOut = HSI_VALUE;
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// Check to see if the Line is busy
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// This bit is set automatically when a start condition is broadcast on the line (even from another master)
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// and is reset when stop condition is detected.
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while (m_port->ISR & I2C_ISR_BUSY) {
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if (!(timeOut--))
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return false;
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}
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return true;
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m_port->CR2 &= ~(I2C_CR2_SADD |
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I2C_CR2_NBYTES |
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I2C_CR2_RELOAD |
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I2C_CR2_AUTOEND |
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(I2C_CR2_RD_WRN & (uint32_t)(I2C_Generate_Start_Write >> (31U - I2C_CR2_RD_WRN_Pos))) |
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I2C_CR2_START |
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I2C_CR2_STOP);
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m_port->CR2 |= (uint32_t)(((uint32_t)m_addr & I2C_CR2_SADD) |
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(((uint32_t)size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) |
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(uint32_t)I2C_CR2_RELOAD |
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(uint32_t)I2C_Generate_Start_Write);
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}
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#endif
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@ -52,10 +52,8 @@ private:
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bool m_ok;
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uint8_t m_addr;
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bool setAddr(uint8_t addr, uint8_t dir);
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bool write(uint8_t c);
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bool waitISRFlagsSet(uint32_t flags);
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bool waitLineIdle();
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void configureDataTransfer(uint8_t size);
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};
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#endif
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@ -1 +1 @@
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Subproject commit 6241f7c05eeb6cf1ecd16ca0274bf310efee853f
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Subproject commit a06aca356cbfb4db847c66512e0a6ee52e58b116
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