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Reorder LPTMR initialisation in accordance with the chip specification.

This commit is contained in:
Jonathan Naylor 2016-12-01 10:10:12 +00:00 committed by GitHub
parent e39624bb9d
commit 1e4b5e6b89
1 changed files with 2 additions and 2 deletions
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4
IOTeensy.cpp
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@ -129,12 +129,12 @@ void CIO::startInt()
CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = EXTERNAL_OSC / 24000;
LPTMR0_CSR = LPTMR_CSR_TIE | // Interrupt Enable
LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13
LPTMR_CSR_TFC | // Free-Running Counter
LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter
LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
LPTMR0_CMR = EXTERNAL_OSC / 24000;
LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable
#else
// Setup PDB for ADC0 at 24 kHz