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Add the LL library files and clean up some indentation.
This commit is contained in:
Jonathan Naylor
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/**
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******************************************************************************
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* @file stm32f4xx_ll_cortex.h
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* @author MCD Application Team
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* @brief Header file of CORTEX LL module.
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL CORTEX driver contains a set of generic APIs that can be
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used by user:
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(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
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functions
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(+) Low power mode configuration (SCB register of Cortex-MCU)
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(+) MPU API to configure and enable regions
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(MPU services provided only on some devices)
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(+) API to access to MCU info (CPUID register)
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(+) API to enable fault handler (SHCSR accesses)
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_LL_CORTEX_H
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#define __STM32F4xx_LL_CORTEX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/** @addtogroup STM32F4xx_LL_Driver
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* @{
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*/
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/** @defgroup CORTEX_LL CORTEX
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
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* @{
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*/
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/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
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* @{
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*/
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#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
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#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
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* @{
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*/
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#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
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#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
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#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
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/**
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* @}
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*/
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#if __MPU_PRESENT
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/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
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* @{
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*/
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#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
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#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
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#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
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#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
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* @{
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*/
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#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
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#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
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#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
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#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
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#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
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#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
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#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
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#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
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* @{
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*/
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#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
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* @{
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*/
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#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
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#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
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#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
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#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
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#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
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#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
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* @{
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*/
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#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
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#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
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#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
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#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
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* @{
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*/
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#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
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#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
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* @{
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*/
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#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
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#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
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* @{
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*/
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#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
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#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
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* @{
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*/
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#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
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#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
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/**
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* @}
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*/
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
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* @{
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*/
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/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
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* @{
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*/
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/**
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* @brief This function checks if the Systick counter flag is active or not.
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* @note It can be used in timeout function on application side.
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* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
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{
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return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
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}
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/**
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* @brief Configures the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
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* @param Source This parameter can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
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{
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if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
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{
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SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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else
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{
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CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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}
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/**
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* @brief Get the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
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{
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return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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/**
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* @brief Enable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
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{
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SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Disable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
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{
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CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Checks if the SYSTICK interrupt is enabled or disabled.
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
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* @retval State of bit (1 or 0).
|
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
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{
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return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
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}
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
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* @{
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*/
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/**
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* @brief Processor uses sleep as its low power mode
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* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
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* @retval None
|
||||
*/
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__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
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{
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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}
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/**
|
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* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
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* @retval None
|
||||
*/
|
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__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
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||||
|
||||
/**
|
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* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
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||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||
* @retval None
|
||||
*/
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||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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||||
|
||||
/**
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||||
* @brief Do not sleep when returning to Thread mode.
|
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* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
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* @retval None
|
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*/
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__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||
{
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/* Clear SLEEPONEXIT bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
|
||||
|
||||
/**
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||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||
{
|
||||
/* Enable the system handler fault */
|
||||
SET_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||
{
|
||||
/* Disable the system handler fault */
|
||||
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Constant number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||
* @retval Value should be equal to 0xF for Cortex-M4 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC24 for Cortex-M4
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable MPU with input options
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||
* @param Options This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||
{
|
||||
/* Enable the MPU*/
|
||||
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||
/* Ensure MPU settings take effects */
|
||||
__DSB();
|
||||
/* Sequence instruction fetches using update settings */
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable MPU
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
/* Disable MPU*/
|
||||
WRITE_REG(MPU->CTRL, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if MPU is enabled or not
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||
{
|
||||
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a MPU region
|
||||
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Enable the MPU region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and enable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @param Address Value of region base address
|
||||
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||
* @param Attributes This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Disable the MPU region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_CORTEX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,204 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_LL_CRC_H
|
||||
#define STM32F4xx_LL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC)
|
||||
|
||||
/** @defgroup CRC_LL CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the CRC calculation unit.
|
||||
* @note If Programmable Initial CRC value feature
|
||||
* is available, also set the Data Register to the value stored in the
|
||||
* CRC_INIT register, otherwise, reset Data Register to its default value.
|
||||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||
* @param CRCx CRC Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write given 32-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData32
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
WRITE_REG(CRCx->DR, InData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||
* @rmtoll DR DR LL_CRC_ReadData32
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return data stored in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_LL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,956 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_LL_EXTI_H
|
||||
#define __STM32F4xx_LL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private Macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
|
||||
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
|
||||
|
||||
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
|
||||
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
|
||||
|
||||
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
|
||||
} LL_EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_LINE LINE
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
|
||||
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
|
||||
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
|
||||
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
|
||||
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
|
||||
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
|
||||
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
|
||||
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
|
||||
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
|
||||
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
|
||||
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
|
||||
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
|
||||
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
|
||||
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
|
||||
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
|
||||
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
|
||||
#if defined(EXTI_IMR_IM16)
|
||||
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
|
||||
#if defined(EXTI_IMR_IM18)
|
||||
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
|
||||
#if defined(EXTI_IMR_IM20)
|
||||
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM21)
|
||||
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM22)
|
||||
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM23)
|
||||
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM24)
|
||||
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM25)
|
||||
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM26)
|
||||
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM27)
|
||||
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM28)
|
||||
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM29)
|
||||
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM30)
|
||||
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM31)
|
||||
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
|
||||
|
||||
|
||||
#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/** @defgroup EXTI_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
|
||||
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
|
||||
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
|
||||
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in EXTI register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in EXTI register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->EMR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->EMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a Falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for the same interrupt line.
|
||||
* In this case, both generate a trigger condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
|
||||
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
||||
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
||||
* resulting in an interrupt request generation.
|
||||
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
||||
* register (by writing a 1 into the bit)
|
||||
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->SWIER, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear ExtLine Flags for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19(*)
|
||||
* @arg @ref LL_EXTI_LINE_20(*)
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
WRITE_REG(EXTI->PR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
uint32_t LL_EXTI_DeInit(void);
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* EXTI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,982 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_LL_GPIO_H
|
||||
#define __STM32F4xx_LL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
|
||||
|
||||
/** @defgroup GPIO_LL GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LL GPIO Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_LL_EC_PIN */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_MODE.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
|
||||
|
||||
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
|
||||
|
||||
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_PULL.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
|
||||
|
||||
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_AF.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
|
||||
} LL_GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PIN PIN
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
|
||||
#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
|
||||
#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
|
||||
#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
|
||||
#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
|
||||
#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
|
||||
#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
|
||||
#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
|
||||
#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
|
||||
#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
|
||||
#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
|
||||
#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
|
||||
#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
|
||||
#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
|
||||
#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
|
||||
#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
|
||||
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
|
||||
GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
|
||||
GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
|
||||
GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
|
||||
GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
|
||||
GPIO_BSRR_BS_15) /*!< Select all pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
|
||||
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
|
||||
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
|
||||
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
|
||||
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_SPEED Output Speed
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
|
||||
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
|
||||
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_AF Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
|
||||
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
|
||||
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
|
||||
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
|
||||
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
|
||||
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
|
||||
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
|
||||
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
|
||||
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
|
||||
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
|
||||
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
|
||||
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
|
||||
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
|
||||
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
|
||||
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
|
||||
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Mode This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
||||
{
|
||||
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->MODER,
|
||||
(GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @param OutputType This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Speed This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
|
||||
(Speed << (POSITION_VAL(Pin) * 2U)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
|
||||
(GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Pull This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
|
||||
{
|
||||
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->PUPDR,
|
||||
(GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
|
||||
(Alternate << (POSITION_VAL(Pin) * 4U)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
|
||||
(GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
|
||||
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
|
||||
(GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Lock configuration of several pins for a dedicated port.
|
||||
* @note When the lock sequence has been applied on a port bit, the
|
||||
* value of this port bit can no longer be modified until the
|
||||
* next reset.
|
||||
* @note Each lock bit freezes a specific configuration register
|
||||
* (control and alternate function registers).
|
||||
* @rmtoll LCKR LCKK LL_GPIO_LockPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
__IO uint32_t temp;
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
temp = READ_REG(GPIOx->LCKR);
|
||||
(void) temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
|
||||
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
|
||||
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Data_Access Data Access
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return full input data register value for a dedicated port.
|
||||
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Input data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write output data register for the port.
|
||||
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PortValue Level value for each pin of the port
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, PortValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return full output data register value for a dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Output data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->ODR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to high level on dedicated gpio port.
|
||||
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to low level on dedicated gpio port.
|
||||
* @rmtoll BSRR BRy LL_GPIO_ResetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, (PinMask << 16));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle data value for several pin of dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_TogglePin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,307 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_LL_IWDG_H
|
||||
#define STM32F4xx_LL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(IWDG)
|
||||
|
||||
/** @defgroup IWDG_LL IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
|
||||
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
|
||||
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
|
||||
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
|
||||
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
|
||||
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
|
||||
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the Independent Watchdog
|
||||
* @note Except if the hardware watchdog option is selected
|
||||
* @rmtoll KR KEY LL_IWDG_Enable
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* @rmtoll KR KEY LL_IWDG_ReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_SetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
|
||||
{
|
||||
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the selected prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_GetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->PR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
|
||||
{
|
||||
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the specified IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if flag Prescaler Value Update is set or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Reload Value Update is set or not
|
||||
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flags Prescaler & Reload Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* IWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_LL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,989 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_LL_PWR_H
|
||||
#define __STM32F4xx_LL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR)
|
||||
|
||||
/** @defgroup PWR_LL PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_WriteReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
|
||||
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
|
||||
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
|
||||
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
|
||||
#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
|
||||
#if defined(PWR_CSR_EWUP)
|
||||
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
|
||||
#elif defined(PWR_CSR_EWUP1)
|
||||
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
|
||||
#endif /* PWR_CSR_EWUP */
|
||||
#if defined(PWR_CSR_EWUP2)
|
||||
#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
|
||||
#endif /* PWR_CSR_EWUP2 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR_VOS_0)
|
||||
#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
|
||||
#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
|
||||
#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
|
||||
#else
|
||||
#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
|
||||
#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
|
||||
#endif /* PWR_CR_VOS_0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
|
||||
#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
|
||||
#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
|
||||
#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
|
||||
#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
|
||||
#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
|
||||
#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
|
||||
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
|
||||
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
|
||||
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
|
||||
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
|
||||
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
|
||||
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
|
||||
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
|
||||
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
|
||||
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CSR_EWUP)
|
||||
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
|
||||
#endif /* PWR_CSR_EWUP */
|
||||
#if defined(PWR_CSR_EWUP1)
|
||||
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
|
||||
#endif /* PWR_CSR_EWUP1 */
|
||||
#if defined(PWR_CSR_EWUP2)
|
||||
#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
|
||||
#endif /* PWR_CSR_EWUP2 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in PWR register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in PWR register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR_FISSR)
|
||||
/**
|
||||
* @brief Enable FLASH interface STOP while system Run is ON
|
||||
* @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_FISSR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable FLASH Interface STOP while system Run is ON
|
||||
* @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if FLASH Interface STOP while system Run feature is enabled
|
||||
* @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
|
||||
}
|
||||
#endif /* PWR_CR_FISSR */
|
||||
|
||||
#if defined(PWR_CR_FMSSR)
|
||||
/**
|
||||
* @brief Enable FLASH Memory STOP while system Run is ON
|
||||
* @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_FMSSR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable FLASH Memory STOP while system Run is ON
|
||||
* @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if FLASH Memory STOP while system Run feature is enabled
|
||||
* @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
|
||||
}
|
||||
#endif /* PWR_CR_FMSSR */
|
||||
#if defined(PWR_CR_UDEN)
|
||||
/**
|
||||
* @brief Enable Under Drive Mode
|
||||
* @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
||||
* mode is only available when the main Regulator or the low power Regulator
|
||||
* is in low voltage mode.
|
||||
* @note If the Under-drive mode was enabled, it is automatically disabled after
|
||||
* exiting Stop mode.
|
||||
* When the voltage Regulator operates in Under-drive mode, an additional
|
||||
* startup delay is induced when waking up from Stop mode.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_UDEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Under Drive Mode
|
||||
* @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Under Drive Mode is enabled
|
||||
* @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
|
||||
}
|
||||
#endif /* PWR_CR_UDEN */
|
||||
|
||||
#if defined(PWR_CR_ODSWEN)
|
||||
/**
|
||||
* @brief Enable Over drive switching
|
||||
* @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_ODSWEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Over drive switching
|
||||
* @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Over drive switching is enabled
|
||||
* @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
|
||||
}
|
||||
#endif /* PWR_CR_ODSWEN */
|
||||
#if defined(PWR_CR_ODEN)
|
||||
/**
|
||||
* @brief Enable Over drive Mode
|
||||
* @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_ODEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Over drive Mode
|
||||
* @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Over drive switching is enabled
|
||||
* @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
|
||||
}
|
||||
#endif /* PWR_CR_ODEN */
|
||||
#if defined(PWR_CR_MRUDS)
|
||||
/**
|
||||
* @brief Enable Main Regulator in deepsleep under-drive Mode
|
||||
* @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_MRUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Main Regulator in deepsleep under-drive Mode
|
||||
* @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
|
||||
* @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
|
||||
}
|
||||
#endif /* PWR_CR_MRUDS */
|
||||
|
||||
#if defined(PWR_CR_LPUDS)
|
||||
/**
|
||||
* @brief Enable Low Power Regulator in deepsleep under-drive Mode
|
||||
* @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_LPUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Low Power Regulator in deepsleep under-drive Mode
|
||||
* @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
|
||||
* @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
|
||||
}
|
||||
#endif /* PWR_CR_LPUDS */
|
||||
|
||||
#if defined(PWR_CR_MRLVDS)
|
||||
/**
|
||||
* @brief Enable Main Regulator low voltage Mode
|
||||
* @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_MRLVDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Main Regulator low voltage Mode
|
||||
* @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Main Regulator low voltage Mode is enabled
|
||||
* @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
|
||||
}
|
||||
#endif /* PWR_CR_MRLVDS */
|
||||
|
||||
#if defined(PWR_CR_LPLVDS)
|
||||
/**
|
||||
* @brief Enable Low Power Regulator low voltage Mode
|
||||
* @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_LPLVDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Low Power Regulator low voltage Mode
|
||||
* @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Low Power Regulator low voltage Mode is enabled
|
||||
* @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
|
||||
}
|
||||
#endif /* PWR_CR_LPLVDS */
|
||||
/**
|
||||
* @brief Set the main internal Regulator output voltage
|
||||
* @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
|
||||
* @param VoltageScaling This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
|
||||
* (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the main internal Regulator output voltage
|
||||
* @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
|
||||
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
|
||||
* (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
|
||||
}
|
||||
/**
|
||||
* @brief Enable the Flash Power Down in Stop Mode
|
||||
* @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_FPDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Flash Power Down in Stop Mode
|
||||
* @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the Flash Power Down in Stop Mode is enabled
|
||||
* @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the backup domain is enabled
|
||||
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
|
||||
}
|
||||
/**
|
||||
* @brief Enable the backup Regulator
|
||||
* @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
|
||||
* @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
|
||||
* The LL_PWR_EnableBkUpAccess() must be called before using this API.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
|
||||
{
|
||||
SET_BIT(PWR->CSR, PWR_CSR_BRE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the backup Regulator
|
||||
* @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
|
||||
* @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
|
||||
* The LL_PWR_EnableBkUpAccess() must be called before using this API.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the backup Regulator is enabled
|
||||
* @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
|
||||
* @param RegulMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR FPDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR FPDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_SetPowerMode
|
||||
* @param PDMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
|
||||
{
|
||||
#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
|
||||
#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
|
||||
#else
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
|
||||
#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR FPDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR FPDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_GetPowerMode
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
|
||||
{
|
||||
#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
|
||||
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
|
||||
#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
|
||||
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
|
||||
#else
|
||||
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
|
||||
#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the voltage threshold detected by the Power Voltage Detector
|
||||
* @rmtoll CR PLS LL_PWR_SetPVDLevel
|
||||
* @param PVDLevel This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the voltage threshold detection
|
||||
* @rmtoll CR PLS LL_PWR_GetPVDLevel
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_EnablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnablePVD(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_DisablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisablePVD(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Power Voltage Detector is enabled
|
||||
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
SET_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the WakeUp PINx functionality is enabled
|
||||
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Wake-up Flag
|
||||
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Standby Flag
|
||||
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Backup Regulator ready Flag
|
||||
* @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
|
||||
}
|
||||
/**
|
||||
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
||||
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
|
||||
* @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
|
||||
}
|
||||
#if defined(PWR_CR_ODEN)
|
||||
/**
|
||||
* @brief Indicate whether the Over-Drive mode is ready or not
|
||||
* @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
|
||||
}
|
||||
#endif /* PWR_CR_ODEN */
|
||||
|
||||
#if defined(PWR_CR_ODSWEN)
|
||||
/**
|
||||
* @brief Indicate whether the Over-Drive mode switching is ready or not
|
||||
* @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
|
||||
}
|
||||
#endif /* PWR_CR_ODSWEN */
|
||||
|
||||
#if defined(PWR_CR_UDEN)
|
||||
/**
|
||||
* @brief Indicate whether the Under-Drive mode is ready or not
|
||||
* @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
|
||||
}
|
||||
#endif /* PWR_CR_UDEN */
|
||||
/**
|
||||
* @brief Clear Standby Flag
|
||||
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Wake-up Flags
|
||||
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
||||
}
|
||||
#if defined(PWR_CSR_UDRDY)
|
||||
/**
|
||||
* @brief Clear Under-Drive ready Flag
|
||||
* @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
|
||||
{
|
||||
WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
|
||||
}
|
||||
#endif /* PWR_CSR_UDRDY */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup PWR_LL_EF_Init De-initialization function
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_PWR_DeInit(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(PWR) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,337 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_rng.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RNG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_LL_RNG_H
|
||||
#define STM32F4xx_LL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (RNG)
|
||||
|
||||
/** @defgroup RNG_LL RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_RNG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
|
||||
#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
|
||||
#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Enable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Disable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator is enabled
|
||||
* @rmtoll CR RNGEN LL_RNG_IsEnabled
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Indicate if the RNG Data ready Flag is set or not
|
||||
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Current Status Flag is set or not
|
||||
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Current Status Flag is set or not
|
||||
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Clock Error interrupt Status (CEIS) Flag
|
||||
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Seed Error interrupt Status (SEIS) Flag
|
||||
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_IT_Management IT Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_EnableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_DisableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator Interrupt is enabled
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_IsEnabledIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_Data_Management Data Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return32-bit Random Number value
|
||||
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Generated 32-bit random value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(RNGx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* RNG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,499 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_usb.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USB Low Layer HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_LL_USB_H
|
||||
#define STM32F4xx_LL_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USB Mode definition
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_DEVICE_MODE = 0,
|
||||
USB_HOST_MODE = 1,
|
||||
USB_DRD_MODE = 2
|
||||
} USB_OTG_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief URB States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
URB_IDLE = 0,
|
||||
URB_DONE,
|
||||
URB_NOTREADY,
|
||||
URB_NYET,
|
||||
URB_ERROR,
|
||||
URB_STALL
|
||||
} USB_OTG_URBStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Host channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HC_IDLE = 0,
|
||||
HC_XFRC,
|
||||
HC_HALTED,
|
||||
HC_NAK,
|
||||
HC_NYET,
|
||||
HC_STALL,
|
||||
HC_XACTERR,
|
||||
HC_BBLERR,
|
||||
HC_DATATGLERR
|
||||
} USB_OTG_HCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USB OTG Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t Host_channels; /*!< Host Channels number.
|
||||
This parameter Depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
|
||||
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref USB_Core_PHY_ */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
|
||||
|
||||
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
|
||||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
} USB_OTG_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t num; /*!< Endpoint number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t is_stall; /*!< Endpoint stall condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t type; /*!< Endpoint type
|
||||
This parameter can be any value of @ref USB_EP_Type_ */
|
||||
|
||||
uint8_t data_pid_start; /*!< Initial data PID
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t even_odd_frame; /*!< IFrame parity
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
} USB_OTG_EPTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_addr ; /*!< USB device address.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||
|
||||
uint8_t ch_num; /*!< Host channel number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_num; /*!< Endpoint number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t speed; /*!< USB Host speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
|
||||
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||
|
||||
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
||||
|
||||
uint8_t ep_type; /*!< Endpoint Type.
|
||||
This parameter can be any value of @ref USB_EP_Type_ */
|
||||
|
||||
uint16_t max_packet; /*!< Endpoint Max packet size.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t data_pid; /*!< Initial data PID.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||
|
||||
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||
|
||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||
|
||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
} USB_OTG_HCTypeDef;
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
/** @defgroup USB_OTG_CORE VERSION ID
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_CORE_ID_300A 0x4F54300AU
|
||||
#define USB_OTG_CORE_ID_310A 0x4F54310AU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Mode_ USB Core Mode
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_MODE_DEVICE 0U
|
||||
#define USB_OTG_MODE_HOST 1U
|
||||
#define USB_OTG_MODE_DRD 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_SPEED_HIGH 0U
|
||||
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
|
||||
#define USB_OTG_SPEED_FULL 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_ULPI_PHY 1U
|
||||
#define USB_OTG_EMBEDDED_PHY 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
|
||||
* @{
|
||||
*/
|
||||
#ifndef USBD_HS_TRDT_VALUE
|
||||
#define USBD_HS_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
#ifndef USBD_FS_TRDT_VALUE
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#define USBD_DEFAULT_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
|
||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
|
||||
* @{
|
||||
*/
|
||||
#define DCFG_FRAME_INTERVAL_80 0U
|
||||
#define DCFG_FRAME_INTERVAL_85 1U
|
||||
#define DCFG_FRAME_INTERVAL_90 2U
|
||||
#define DCFG_FRAME_INTERVAL_95 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0U
|
||||
#define DEP0CTL_MPS_32 1U
|
||||
#define DEP0CTL_MPS_16 2U
|
||||
#define DEP0CTL_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
|
||||
* @{
|
||||
*/
|
||||
#define EP_SPEED_LOW 0U
|
||||
#define EP_SPEED_FULL 1U
|
||||
#define EP_SPEED_HIGH 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||
* @{
|
||||
*/
|
||||
#define EP_TYPE_CTRL 0U
|
||||
#define EP_TYPE_ISOC 1U
|
||||
#define EP_TYPE_BULK 2U
|
||||
#define EP_TYPE_INTR 3U
|
||||
#define EP_TYPE_MSK 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
|
||||
* @{
|
||||
*/
|
||||
#define STS_GOUT_NAK 1U
|
||||
#define STS_DATA_UPDT 2U
|
||||
#define STS_XFER_COMP 3U
|
||||
#define STS_SETUP_COMP 4U
|
||||
#define STS_SETUP_UPDT 6U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HCFG_30_60_MHZ 0U
|
||||
#define HCFG_48_MHZ 1U
|
||||
#define HCFG_6_MHZ 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define HCCHAR_CTRL 0U
|
||||
#define HCCHAR_ISOC 1U
|
||||
#define HCCHAR_BULK 2U
|
||||
#define HCCHAR_INTR 3U
|
||||
|
||||
#define HC_PID_DATA0 0U
|
||||
#define HC_PID_DATA2 1U
|
||||
#define HC_PID_DATA1 2U
|
||||
#define HC_PID_SETUP 3U
|
||||
|
||||
#define GRXSTS_PKTSTS_IN 2U
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
||||
|
||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
|
||||
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
|
||||
|
||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
|
||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
|
||||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
|
||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#define EP_ADDR_MSK 0xFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||
|
||||
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F4xx_LL_USB_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,309 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UTILS LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_LL_UTILS_H
|
||||
#define __STM32F4xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @brief Package data register base address
|
||||
*/
|
||||
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
|
||||
This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
|
||||
and Max_Data = @ref RCC_PLLN_MIN_VALUE
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLP; /*!< Division for the main system clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Package type
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_UTILS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,319 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_ll_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of WWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_LL_WWDG_H
|
||||
#define STM32F4xx_LL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Write a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||
* then it cannot be disabled again except by a reset.
|
||||
* This bit is set by software and only cleared by hardware after a reset.
|
||||
* When WDGA = 1, the watchdog can generate a reset.
|
||||
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if Window Watchdog is enabled
|
||||
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||
* @rmtoll CR T LL_WWDG_SetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Counter 0..0x7F (7 bit counter value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||
* @rmtoll CR T LL_WWDG_GetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time base of the prescaler (WDGTB).
|
||||
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Prescaler Value
|
||||
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||
* @note This window value defines when write in the WWDG_CR register
|
||||
* to program Watchdog counter is allowed.
|
||||
* Watchdog counter value update must occur only when the counter value
|
||||
* is lower than the Watchdog window register value.
|
||||
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||
* (in the control register) is refreshed before the downcounter has reached
|
||||
* the watchdog window register value.
|
||||
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Window 0x00..0x7F (7 bit Window value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Window Value (7 bits value)
|
||||
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Window value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||
* It must be cleared by software by writing 0.
|
||||
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the Early Wakeup Interrupt.
|
||||
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||
* This interrupt is only cleared by hardware after a reset
|
||||
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Early Wakeup Interrupt is enabled
|
||||
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* WWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_WWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user