From 2c76d67098af58c7687d3ec1e4bc53d19358669b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Gomu=C5=82ka?= Date: Tue, 20 Dec 2016 20:32:54 +0100 Subject: [PATCH 1/8] RSSI readout support for NTH board @Arduino Due --- IODue.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/IODue.cpp b/IODue.cpp index 17d4fa4..93faf35 100644 --- a/IODue.cpp +++ b/IODue.cpp @@ -64,6 +64,8 @@ #define ADC_CDR_Chan 7 #define DACC_MR_USER_SEL_Chan DACC_MR_USER_SEL_CHANNEL0 // DAC on Due DAC0 #define DACC_CHER_Chan DACC_CHER_CH0 +#define RSSI_CHER_Chan (1<<1) // ADC on Due pin A6 - Due AD1 - (1 << 1) +#define RSSI_CDR_Chan 1 #else #error "Either ARDUINO_DUE_PAPA, ARDUINO_DUE_ZUM_V10, or ARDUINO_DUE_NTH need to be defined" #endif @@ -104,7 +106,8 @@ void CIO::startInt() ADC->ADC_IDR = 0xFFFFFFFF; // Disable interrupts ADC->ADC_IER = ADC_CHER_Chan; // Enable End-Of-Conv interrupt ADC->ADC_CHDR = 0xFFFF; // Disable all channels - ADC->ADC_CHER = ADC_CHER_Chan; // Enable just one channel + ADC->ADC_CHER = ADC_CHER_Chan | // Enable rx input channel + RSSI_CHER_Chan; // and RSSI input ADC->ADC_CGR = 0x15555555; // All gains set to x1 ADC->ADC_COR = 0x00000000; // All offsets off ADC->ADC_MR = (ADC->ADC_MR & 0xFFFFFFF0) | (1 << 1) | ADC_MR_TRGEN; // 1 = trig source TIO from TC0 @@ -169,7 +172,7 @@ void CIO::interrupt(uint8_t source) sample = ADC->ADC_CDR[ADC_CDR_Chan]; m_rxBuffer.put(sample, control); - m_rssiBuffer.put(0U); + m_rssiBuffer.put(ADC->ADC_CDR[RSSI_CDR_Chan]); m_watchdog++; } From 75eccb751e7de71e1d941fa6505af6345a1aee65 Mon Sep 17 00:00:00 2001 From: g4eml Date: Tue, 20 Dec 2016 20:48:15 +0000 Subject: [PATCH 2/8] Update IOTeensy.cpp Switch ADCs to External Reference. (3v3 on Teensy) --- IOTeensy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 7bb40f0..7ff7801 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -84,7 +84,7 @@ void CIO::startInt() ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb - ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger + ADC0_SC2 = ADC_SC2_REFSEL(0) | ADC_SC2_ADTRG; // Voltage ref external, hardware trigger ADC0_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples ADC0_SC3 |= ADC_SC3_CAL; @@ -105,7 +105,7 @@ void CIO::startInt() ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb - ADC1_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger + ADC1_SC2 = ADC_SC2_REFSEL(0); // Voltage ref external, software trigger ADC1_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples ADC1_SC3 |= ADC_SC3_CAL; From bef0d9cfd650354dc223235f2ab5e285b796141d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Gomu=C5=82ka?= Date: Wed, 21 Dec 2016 01:55:35 +0100 Subject: [PATCH 3/8] Added missing conditions for preprocessor --- Config.h | 1 - IODue.cpp | 15 ++++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/Config.h b/Config.h index 3eb0ed4..c68fba1 100644 --- a/Config.h +++ b/Config.h @@ -62,4 +62,3 @@ // #define SERIAL_REPEATER #endif - diff --git a/IODue.cpp b/IODue.cpp index 93faf35..4c41752 100644 --- a/IODue.cpp +++ b/IODue.cpp @@ -106,8 +106,10 @@ void CIO::startInt() ADC->ADC_IDR = 0xFFFFFFFF; // Disable interrupts ADC->ADC_IER = ADC_CHER_Chan; // Enable End-Of-Conv interrupt ADC->ADC_CHDR = 0xFFFF; // Disable all channels - ADC->ADC_CHER = ADC_CHER_Chan | // Enable rx input channel - RSSI_CHER_Chan; // and RSSI input + ADC->ADC_CHER = ADC_CHER_Chan; // Enable rx input channel +#if defined(RSSI_CHER_Chan) + ADC->ADC_CHER |= RSSI_CHER_Chan; // and RSSI input +#endif ADC->ADC_CGR = 0x15555555; // All gains set to x1 ADC->ADC_COR = 0x00000000; // All offsets off ADC->ADC_MR = (ADC->ADC_MR & 0xFFFFFFF0) | (1 << 1) | ADC_MR_TRGEN; // 1 = trig source TIO from TC0 @@ -172,7 +174,11 @@ void CIO::interrupt(uint8_t source) sample = ADC->ADC_CDR[ADC_CDR_Chan]; m_rxBuffer.put(sample, control); +#if defined(RSSI_CHER_Chan) && defined(SEND_RSSI_DATA) m_rssiBuffer.put(ADC->ADC_CDR[RSSI_CDR_Chan]); +#else + m_rssiBuffer.put(0U); +#endif m_watchdog++; } @@ -203,7 +209,7 @@ void CIO::setDStarInt(bool on) digitalWrite(PIN_DSTAR, on ? HIGH : LOW); } -void CIO::setDMRInt(bool on) +void CIO::setDMRInt(bool on) { digitalWrite(PIN_DMR, on ? HIGH : LOW); } @@ -213,10 +219,9 @@ void CIO::setYSFInt(bool on) digitalWrite(PIN_YSF, on ? HIGH : LOW); } -void CIO::setP25Int(bool on) +void CIO::setP25Int(bool on) { digitalWrite(PIN_P25, on ? HIGH : LOW); } #endif - From 414f3eb19387da0fe1dcb3c1a81a2e9cb40c9fbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Gomu=C5=82ka?= Date: Wed, 21 Dec 2016 01:57:58 +0100 Subject: [PATCH 4/8] typo :/ --- IODue.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/IODue.cpp b/IODue.cpp index 4c41752..34913ec 100644 --- a/IODue.cpp +++ b/IODue.cpp @@ -174,7 +174,7 @@ void CIO::interrupt(uint8_t source) sample = ADC->ADC_CDR[ADC_CDR_Chan]; m_rxBuffer.put(sample, control); -#if defined(RSSI_CHER_Chan) && defined(SEND_RSSI_DATA) +#if defined(RSSI_CDR_Chan) && defined(SEND_RSSI_DATA) m_rssiBuffer.put(ADC->ADC_CDR[RSSI_CDR_Chan]); #else m_rssiBuffer.put(0U); From 461e7c942e49325b0371036b7f3e355cf774074d Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 21 Dec 2016 08:46:17 +0000 Subject: [PATCH 5/8] Add RSSI input for the ZUM board also. --- IODue.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/IODue.cpp b/IODue.cpp index 34913ec..ab71d46 100644 --- a/IODue.cpp +++ b/IODue.cpp @@ -51,6 +51,8 @@ #define ADC_CDR_Chan 13 #define DACC_MR_USER_SEL_Chan DACC_MR_USER_SEL_CHANNEL1 // DAC on Due DAC1 #define DACC_CHER_Chan DACC_CHER_CH1 +#define RSSI_CHER_Chan (1<<1) // ADC on Due pin A6 - Due AD1 - (1 << 1) +#define RSSI_CDR_Chan 1 #elif defined(ARDUINO_DUE_NTH) #define PIN_COS A7 #define PIN_PTT A8 @@ -107,7 +109,7 @@ void CIO::startInt() ADC->ADC_IER = ADC_CHER_Chan; // Enable End-Of-Conv interrupt ADC->ADC_CHDR = 0xFFFF; // Disable all channels ADC->ADC_CHER = ADC_CHER_Chan; // Enable rx input channel -#if defined(RSSI_CHER_Chan) +#if defined(SEND_RSSI_DATA) ADC->ADC_CHER |= RSSI_CHER_Chan; // and RSSI input #endif ADC->ADC_CGR = 0x15555555; // All gains set to x1 @@ -174,7 +176,7 @@ void CIO::interrupt(uint8_t source) sample = ADC->ADC_CDR[ADC_CDR_Chan]; m_rxBuffer.put(sample, control); -#if defined(RSSI_CDR_Chan) && defined(SEND_RSSI_DATA) +#if defined(SEND_RSSI_DATA) m_rssiBuffer.put(ADC->ADC_CDR[RSSI_CDR_Chan]); #else m_rssiBuffer.put(0U); From 38f6d7d9d8d25c4d40996412b2ba8bd871b782c5 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 21 Dec 2016 14:01:18 +0000 Subject: [PATCH 6/8] Update DAC reference comment. --- IOTeensy.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 7ff7801..ad2e49b 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -77,7 +77,7 @@ void CIO::startInt() { // Initialise the DAC SIM_SCGC2 |= SIM_SCGC2_DAC0; - DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 1.2V VDDA is DACREF_2 + DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2 // Initialise ADC0 SIM_SCGC6 |= SIM_SCGC6_ADC0; From cb30a8d357edd88fd3b2c4d24e1ab3f7d7d16b21 Mon Sep 17 00:00:00 2001 From: g4eml Date: Thu, 22 Dec 2016 16:35:35 +0000 Subject: [PATCH 7/8] Adjust ADC pre-trigger setting for external TCXO External TCXO was not working with Pre-Trigger set to B. This change sets it to A which appears to work. --- IOTeensy.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index ad2e49b..ab75282 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -123,7 +123,6 @@ void CIO::startInt() #if defined(EXTERNAL_OSC) // Set ADC0 to trigger from the LPTMR at 24 kHz SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger - SIM_SOPT7_ADC0PRETRGSEL | // Enable ADC0 pre-trigger SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0 CORE_PIN13_CONFIG = PORT_PCR_MUX(3); From 957d0d8d3413106d1d584766af2ef0fc3664fb30 Mon Sep 17 00:00:00 2001 From: g4eml Date: Thu, 22 Dec 2016 22:27:10 +0000 Subject: [PATCH 8/8] Change ADC1 to reduce number of interrupts. Disable interrupts for ADC1. Every time ADC0 interrupts (24Khz) read the current conversion from ADC1 and software trigger a new one. This way there will always be an ADC1 conversion available whenever ADC0 interrupts. --- IOTeensy.cpp | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index ab75282..8c22c77 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -117,7 +117,6 @@ void CIO::startInt() sum1 = (sum1 / 2U) | 0x8000U; ADC1_PG = sum1; - NVIC_ENABLE_IRQ(IRQ_ADC1); #endif #if defined(EXTERNAL_OSC) @@ -162,25 +161,30 @@ void CIO::interrupt(uint8_t source) if ((ADC0_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) { sample = ADC0_RA; m_rxBuffer.put(sample, control); - -#if defined(SEND_RSSI_DATA) - ADC1_SC1A = ADC_SC1_AIEN | PIN_RSSI; -#else - m_rssiBuffer.put(0U); -#endif } - - m_watchdog++; - } - + #if defined(SEND_RSSI_DATA) - if (source == 1U) { // ADC1 + if ((ADC1_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) { uint16_t rssi = ADC1_RA; m_rssiBuffer.put(rssi); } - } + else { + m_rssiBuffer.put(0U); + } + ADC1_SC1A = ADC_SC1_AIEN | PIN_RSSI; //start the next RSSI conversion + +#else + m_rssiBuffer.put(0U); #endif + + + m_watchdog++; + } + + + + } bool CIO::getCOSInt() @@ -223,4 +227,4 @@ void CIO::setP25Int(bool on) digitalWrite(PIN_P25, on ? HIGH : LOW); } -#endif +#endif