diff --git a/Config.h b/Config.h
index 3eb0ed4..c68fba1 100644
--- a/Config.h
+++ b/Config.h
@@ -62,4 +62,3 @@
 // #define SERIAL_REPEATER
 
 #endif
-
diff --git a/IODue.cpp b/IODue.cpp
index 17d4fa4..ab71d46 100644
--- a/IODue.cpp
+++ b/IODue.cpp
@@ -51,6 +51,8 @@
 #define ADC_CDR_Chan           13
 #define DACC_MR_USER_SEL_Chan  DACC_MR_USER_SEL_CHANNEL1 // DAC on Due DAC1
 #define DACC_CHER_Chan         DACC_CHER_CH1
+#define RSSI_CHER_Chan         (1<<1)                 // ADC on Due pin A6  - Due AD1 - (1 << 1)
+#define RSSI_CDR_Chan          1
 #elif defined(ARDUINO_DUE_NTH)
 #define PIN_COS                A7
 #define PIN_PTT                A8
@@ -64,6 +66,8 @@
 #define ADC_CDR_Chan           7
 #define DACC_MR_USER_SEL_Chan  DACC_MR_USER_SEL_CHANNEL0 // DAC on Due DAC0
 #define DACC_CHER_Chan         DACC_CHER_CH0
+#define RSSI_CHER_Chan         (1<<1)                 // ADC on Due pin A6  - Due AD1 - (1 << 1)
+#define RSSI_CDR_Chan          1
 #else
 #error "Either ARDUINO_DUE_PAPA, ARDUINO_DUE_ZUM_V10, or ARDUINO_DUE_NTH need to be defined"
 #endif
@@ -104,7 +108,10 @@ void CIO::startInt()
   ADC->ADC_IDR  = 0xFFFFFFFF;                 // Disable interrupts
   ADC->ADC_IER  = ADC_CHER_Chan;              // Enable End-Of-Conv interrupt
   ADC->ADC_CHDR = 0xFFFF;                     // Disable all channels
-  ADC->ADC_CHER = ADC_CHER_Chan;              // Enable just one channel
+  ADC->ADC_CHER = ADC_CHER_Chan;              // Enable rx input channel
+#if defined(SEND_RSSI_DATA)
+  ADC->ADC_CHER |= RSSI_CHER_Chan;            // and RSSI input
+#endif
   ADC->ADC_CGR  = 0x15555555;                 // All gains set to x1
   ADC->ADC_COR  = 0x00000000;                 // All offsets off
   ADC->ADC_MR   = (ADC->ADC_MR & 0xFFFFFFF0) | (1 << 1) | ADC_MR_TRGEN;  // 1 = trig source TIO from TC0
@@ -169,7 +176,11 @@ void CIO::interrupt(uint8_t source)
     sample = ADC->ADC_CDR[ADC_CDR_Chan];
     m_rxBuffer.put(sample, control);
 
+#if defined(SEND_RSSI_DATA)
+    m_rssiBuffer.put(ADC->ADC_CDR[RSSI_CDR_Chan]);
+#else
     m_rssiBuffer.put(0U);
+#endif
 
     m_watchdog++;
   }
@@ -200,7 +211,7 @@ void CIO::setDStarInt(bool on)
   digitalWrite(PIN_DSTAR, on ? HIGH : LOW);
 }
 
-void CIO::setDMRInt(bool on) 
+void CIO::setDMRInt(bool on)
 {
   digitalWrite(PIN_DMR, on ? HIGH : LOW);
 }
@@ -210,10 +221,9 @@ void CIO::setYSFInt(bool on)
   digitalWrite(PIN_YSF, on ? HIGH : LOW);
 }
 
-void CIO::setP25Int(bool on) 
+void CIO::setP25Int(bool on)
 {
   digitalWrite(PIN_P25, on ? HIGH : LOW);
 }
 
 #endif
-
diff --git a/IOTeensy.cpp b/IOTeensy.cpp
index 7bb40f0..8c22c77 100644
--- a/IOTeensy.cpp
+++ b/IOTeensy.cpp
@@ -77,14 +77,14 @@ void CIO::startInt()
 {
   // Initialise the DAC
   SIM_SCGC2 |= SIM_SCGC2_DAC0;
-  DAC0_C0    = DAC_C0_DACEN | DAC_C0_DACRFS;                          // 1.2V VDDA is DACREF_2
+  DAC0_C0    = DAC_C0_DACEN | DAC_C0_DACRFS;                          // 3.3V VDDA is DACREF_2
 
   // Initialise ADC0
   SIM_SCGC6 |= SIM_SCGC6_ADC0;
   ADC0_CFG1  = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) |                // Single-ended 12 bits, long sample time
                ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
   ADC0_CFG2  = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2);                  // Select channels ADxxxb
-  ADC0_SC2   = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG;                     // Voltage ref internal, hardware trigger
+  ADC0_SC2   = ADC_SC2_REFSEL(0) | ADC_SC2_ADTRG;                     // Voltage ref external, hardware trigger
   ADC0_SC3   = ADC_SC3_AVGE | ADC_SC3_AVGS(0);                        // Enable averaging, 4 samples
 
   ADC0_SC3  |= ADC_SC3_CAL;
@@ -105,7 +105,7 @@ void CIO::startInt()
   ADC1_CFG1  = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) |                // Single-ended 12 bits, long sample time
                ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
   ADC1_CFG2  = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2);                  // Select channels ADxxxb
-  ADC1_SC2   = ADC_SC2_REFSEL(1);                                     // Voltage ref internal, software trigger
+  ADC1_SC2   = ADC_SC2_REFSEL(0);                                     // Voltage ref external, software trigger
   ADC1_SC3   = ADC_SC3_AVGE | ADC_SC3_AVGS(0);                        // Enable averaging, 4 samples
 
   ADC1_SC3  |= ADC_SC3_CAL;
@@ -117,13 +117,11 @@ void CIO::startInt()
   sum1 = (sum1 / 2U) | 0x8000U;
   ADC1_PG    = sum1;
 
-  NVIC_ENABLE_IRQ(IRQ_ADC1);
 #endif
 
 #if defined(EXTERNAL_OSC)
   // Set ADC0 to trigger from the LPTMR at 24 kHz
   SIM_SOPT7   = SIM_SOPT7_ADC0ALTTRGEN |                              // Enable ADC0 alternate trigger
-                SIM_SOPT7_ADC0PRETRGSEL |                             // Enable ADC0 pre-trigger
                 SIM_SOPT7_ADC0TRGSEL(14);                             // Trigger ADC0 by LPTMR0
 
   CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
@@ -163,25 +161,30 @@ void CIO::interrupt(uint8_t source)
     if ((ADC0_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) {
       sample = ADC0_RA;
       m_rxBuffer.put(sample, control);
-
-#if defined(SEND_RSSI_DATA)
-      ADC1_SC1A  = ADC_SC1_AIEN | PIN_RSSI;
-#else
-      m_rssiBuffer.put(0U);
-#endif
     }
-
-    m_watchdog++;
-  }
-
+    
 #if defined(SEND_RSSI_DATA)
-  if (source == 1U) {  // ADC1
+ 
     if ((ADC1_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) {
       uint16_t rssi = ADC1_RA;
       m_rssiBuffer.put(rssi);
     }
-  }
+    else {
+      m_rssiBuffer.put(0U);
+    }
+    ADC1_SC1A  = ADC_SC1_AIEN | PIN_RSSI;             //start the next RSSI conversion
+
+#else
+      m_rssiBuffer.put(0U);
 #endif
+  
+
+    m_watchdog++;
+  }
+
+
+
+
 }
 
 bool CIO::getCOSInt()
@@ -224,4 +227,4 @@ void CIO::setP25Int(bool on)
   digitalWrite(PIN_P25, on ? HIGH : LOW);
 }
 
-#endif
+#endif