From 33f4d35e2b8acf4edcb40ae3b4bb77e8f323eea3 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Tue, 10 Jan 2017 00:47:45 -0300 Subject: [PATCH 1/3] Adding new pin definitions for Nucleo-64 STM32F446RE board --- Config.h | 4 ++++ IOSTM.cpp | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/Config.h b/Config.h index c68fba1..50acea0 100644 --- a/Config.h +++ b/Config.h @@ -50,6 +50,10 @@ // For the SP8NTH board // #define ARDUINO_DUE_NTH +// For ST Nucleo-64 STM32F446RE board +// #define STM32F4_NUCLEO_MORPHO_HEADER +// #define STM32F4_NUCLEO_ARDUINO_HEADER + // To use wider C4FSK filters for DMR, System Fusion and P25 on transmit // #define WIDE_C4FSK_FILTERS_TX // To use wider C4FSK filters for DMR, System Fusion and P25 on receive diff --git a/IOSTM.cpp b/IOSTM.cpp index b1bfad4..30167d2 100644 --- a/IOSTM.cpp +++ b/IOSTM.cpp @@ -143,8 +143,10 @@ EXT_CLK PA15 input #define PIN_RSSI_CH ADC_Channel_7 #elif defined(STM32F4_NUCLEO) + +#if defined(STM32F4_NUCLEO_MORPHO_HEADER) /* -Pin definitions for STM32F4 Nucleo boards: +Pin definitions for STM32F4 Nucleo boards (ST Morpho header): PTT PB13 output COSLED PB14 output @@ -201,6 +203,69 @@ EXT_CLK PA15 input #define PIN_RSSI GPIO_Pin_1 #define PIN_RSSI_CH ADC_Channel_1 +#elif defined(STM32F4_NUCLEO_ARDUINO_HEADER) +/* +Pin definitions for STM32F4 Nucleo boards (Arduino header): + +PTT PB10 output +COSLED PB3 output +LED PB5 output +COS PB4 input + +DSTAR PA1 output +DMR PA4 output +YSF PB0 output +P25 PC1 output + +RX PA0 analog input +RSSI PC0 analog input +TX PA5 analog output + +EXT_CLK PB8 input +*/ + +#define PIN_COS GPIO_Pin_4 +#define PORT_COS GPIOB +#define RCC_Per_COS RCC_AHB1Periph_GPIOB + +#define PIN_PTT GPIO_Pin_10 +#define PORT_PTT GPIOB +#define RCC_Per_PTT RCC_AHB1Periph_GPIOB + +#define PIN_COSLED GPIO_Pin_3 +#define PORT_COSLED GPIOB +#define RCC_Per_COSLED RCC_AHB1Periph_GPIOB + +#define PIN_LED GPIO_Pin_5 +#define PORT_LED GPIOB +#define RCC_Per_LED RCC_AHB1Periph_GPIOB + +#define PIN_P25 GPIO_Pin_1 +#define PORT_P25 GPIOC +#define RCC_Per_P25 RCC_AHB1Periph_GPIOC + +#define PIN_DSTAR GPIO_Pin_1 +#define PORT_DSTAR GPIOA +#define RCC_Per_DSTAR RCC_AHB1Periph_GPIOA + +#define PIN_DMR GPIO_Pin_4 +#define PORT_DMR GPIOA +#define RCC_Per_DMR RCC_AHB1Periph_GPIOA + +#define PIN_YSF GPIO_Pin_0 +#define PORT_YSF GPIOB +#define RCC_Per_YSF RCC_AHB1Periph_GPIOB + +#define PIN_RX GPIO_Pin_0 +#define PIN_RX_CH ADC_Channel_0 + +#define PIN_RSSI GPIO_Pin_1 +#define PIN_RSSI_CH ADC_Channel_1 + +#else +#error "Either STM32F4_NUCLEO_MORPHO_HEADER or STM32F4_NUCLEO_ARDUINO_HEADER need to be defined in Config.h" +#endif + #else #error "Either STM32F4_DISCOVERY, STM32F4_PI or STM32F4_NUCLEO need to be defined" #endif From a59da0ebd27b2de41b8055a2a7a97aa4118652c7 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Tue, 10 Jan 2017 01:38:56 -0300 Subject: [PATCH 2/3] Adding more flexibility for STM32F4 pin definitions --- IOSTM.cpp | 95 +++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 71 insertions(+), 24 deletions(-) diff --git a/IOSTM.cpp b/IOSTM.cpp index 30167d2..6995ebe 100644 --- a/IOSTM.cpp +++ b/IOSTM.cpp @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 by Jim McLaughlin KI6ZUM - * Copyright (C) 2016 by Andy Uribe CA6JAU + * Copyright (C) 2016, 2017 by Andy Uribe CA6JAU * Copyright (C) 2017 by Jonathan Naylor G4KLX * * This program is free software; you can redistribute it and/or modify @@ -77,11 +77,22 @@ EXT_CLK PA15 input #define PORT_YSF GPIOD #define RCC_Per_YSF RCC_AHB1Periph_GPIOD +#define PIN_EXT_CLK GPIO_Pin_15 +#define SRC_EXT_CLK GPIO_PinSource15 +#define PORT_EXT_CLK GPIOA + #define PIN_RX GPIO_Pin_0 #define PIN_RX_CH ADC_Channel_0 +#define PORT_RX GPIOA +#define RCC_Per_RX RCC_AHB1Periph_GPIOA #define PIN_RSSI GPIO_Pin_1 #define PIN_RSSI_CH ADC_Channel_1 +#define PORT_RSSI GPIOA +#define RCC_Per_RSSI RCC_AHB1Periph_GPIOA + +#define PIN_TX GPIO_Pin_4 +#define PIN_TX_CH DAC_Channel_1 #elif defined(STM32F4_PI) /* @@ -136,11 +147,22 @@ EXT_CLK PA15 input #define PORT_YSF GPIOA #define RCC_Per_YSF RCC_AHB1Periph_GPIOA +#define PIN_EXT_CLK GPIO_Pin_15 +#define SRC_EXT_CLK GPIO_PinSource15 +#define PORT_EXT_CLK GPIOA + #define PIN_RX GPIO_Pin_0 #define PIN_RX_CH ADC_Channel_0 +#define PORT_RX GPIOA +#define RCC_Per_RX RCC_AHB1Periph_GPIOA #define PIN_RSSI GPIO_Pin_7 #define PIN_RSSI_CH ADC_Channel_7 +#define PORT_RSSI GPIOA +#define RCC_Per_RSSI RCC_AHB1Periph_GPIOA + +#define PIN_TX GPIO_Pin_4 +#define PIN_TX_CH DAC_Channel_1 #elif defined(STM32F4_NUCLEO) @@ -197,11 +219,22 @@ EXT_CLK PA15 input #define PORT_YSF GPIOB #define RCC_Per_YSF RCC_AHB1Periph_GPIOB +#define PIN_EXT_CLK GPIO_Pin_15 +#define SRC_EXT_CLK GPIO_PinSource15 +#define PORT_EXT_CLK GPIOA + #define PIN_RX GPIO_Pin_0 #define PIN_RX_CH ADC_Channel_0 +#define PORT_RX GPIOA +#define RCC_Per_RX RCC_AHB1Periph_GPIOA #define PIN_RSSI GPIO_Pin_1 #define PIN_RSSI_CH ADC_Channel_1 +#define PORT_RSSI GPIOA +#define RCC_Per_RSSI RCC_AHB1Periph_GPIOA + +#define PIN_TX GPIO_Pin_4 +#define PIN_TX_CH DAC_Channel_1 #elif defined(STM32F4_NUCLEO_ARDUINO_HEADER) /* @@ -256,11 +289,22 @@ EXT_CLK PB8 input #define PORT_YSF GPIOB #define RCC_Per_YSF RCC_AHB1Periph_GPIOB +#define PIN_EXT_CLK GPIO_Pin_8 +#define SRC_EXT_CLK GPIO_PinSource8 +#define PORT_EXT_CLK GPIOB + #define PIN_RX GPIO_Pin_0 #define PIN_RX_CH ADC_Channel_0 +#define PORT_RX GPIOA +#define RCC_Per_RX RCC_AHB1Periph_GPIOA -#define PIN_RSSI GPIO_Pin_1 -#define PIN_RSSI_CH ADC_Channel_1 +#define PIN_RSSI GPIO_Pin_0 +#define PIN_RSSI_CH ADC_Channel_10 +#define PORT_RSSI GPIOC +#define RCC_Per_RSSI RCC_AHB1Periph_GPIOC + +#define PIN_TX GPIO_Pin_5 +#define PIN_TX_CH DAC_Channel_2 #else #error "Either STM32F4_NUCLEO_MORPHO_HEADER or STM32F4_NUCLEO_ARDUINO_HEADER need to be defined in Config.h" @@ -357,22 +401,25 @@ void CIO::startInt() ADC_CommonStructInit(&ADC_CommonInitStructure); ADC_StructInit(&ADC_InitStructure); - // Enable ADC clock - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); -#if defined(SEND_RSSI_DATA) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2, ENABLE); -#else + // Enable ADC1 clock + RCC_AHB1PeriphClockCmd(RCC_Per_RX, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); -#endif - -#if defined(SEND_RSSI_DATA) - GPIO_InitStruct.GPIO_Pin = PIN_RX | PIN_RSSI; -#else + // Enable ADC1 GPIO GPIO_InitStruct.GPIO_Pin = PIN_RX; -#endif GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AN; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStruct); + GPIO_Init(PORT_RX, &GPIO_InitStruct); + +#if defined(SEND_RSSI_DATA) + // Enable ADC2 clock + RCC_AHB1PeriphClockCmd(RCC_Per_RSSI, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE); + // Enable ADC2 GPIO + GPIO_InitStruct.GPIO_Pin = PIN_RSSI; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(PORT_RSSI, &GPIO_InitStruct); +#endif // Init ADCs in dual mode (RSSI), div clock by two #if defined(SEND_RSSI_DATA) @@ -424,8 +471,8 @@ void CIO::startInt() // DAC Periph clock enable RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - // GPIO CONFIGURATION of DAC Pins (PA4) - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_4; + // GPIO CONFIGURATION of DAC Pin + GPIO_InitStruct.GPIO_Pin = PIN_TX; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AN; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -433,18 +480,18 @@ void CIO::startInt() DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(DAC_Channel_1, &DAC_InitStructure); - DAC_Cmd(DAC_Channel_1, ENABLE); + DAC_Init(PIN_TX_CH, &DAC_InitStructure); + DAC_Cmd(PIN_TX_CH, ENABLE); // Init the timer RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); #if defined(EXTERNAL_OSC) - // Configure GPIO PA15 as external TIM2 clock source - GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_TIM2); - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; + // Configure a GPIO as external TIM2 clock source + GPIO_PinAFConfig(PORT_EXT_CLK, SRC_EXT_CLK, GPIO_AF_TIM2); + GPIO_InitStruct.GPIO_Pin = PIN_EXT_CLK; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOA, &GPIO_InitStruct); + GPIO_Init(PORT_EXT_CLK, &GPIO_InitStruct); #endif TIM_TimeBaseInitTypeDef timerInitStructure; @@ -464,7 +511,7 @@ void CIO::startInt() TIM_TimeBaseInit(TIM2, &timerInitStructure); #if defined(EXTERNAL_OSC) - // Enable external clock (PA15) + // Enable external clock TIM_ETRClockMode2Config(TIM2, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_NonInverted, 0x00); #else // Enable internal clock From 1ce71bcd62ac4c64ef9b004494397689d2f127d8 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Wed, 11 Jan 2017 00:27:27 -0300 Subject: [PATCH 3/3] New pin definitions for serial port Nucleo-64 STM32F446RE board, Arduino header --- IOSTM.cpp | 4 ++++ SerialSTM.cpp | 39 ++++++++++++++++++++++++++++++--------- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/IOSTM.cpp b/IOSTM.cpp index 6995ebe..2a98c68 100644 --- a/IOSTM.cpp +++ b/IOSTM.cpp @@ -543,7 +543,11 @@ void CIO::interrupt() m_txBuffer.get(sample, control); // Send the value to the DAC +#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) + DAC_SetChannel2Data(DAC_Align_12b_R, sample); +#else DAC_SetChannel1Data(DAC_Align_12b_R, sample); +#endif // Read value from ADC1 and ADC2 if ((ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET)) { diff --git a/SerialSTM.cpp b/SerialSTM.cpp index 904ec10..e4ee3ab 100644 --- a/SerialSTM.cpp +++ b/SerialSTM.cpp @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 by Jim McLaughlin KI6ZUM - * Copyright (C) 2016 by Andy Uribe CA6JAU + * Copyright (C) 2016, 2017 by Andy Uribe CA6JAU * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +31,8 @@ USART2 - TXD PA2 - RXD PA3 (Nucleo board) USART3 - TXD PC10 - RXD PC11 (Discovery board) - Serial repeater: -UART5 - TXD PC12 - RXD PD2 +USART1 - TXD PA9 - RXD PA10 (Nucleo with Arduino header) +UART5 - TXD PC12 - RXD PD2 (Discovery, Pi and Nucleo with Morpho header) */ @@ -48,7 +49,7 @@ extern "C" { } /* ************* USART1 ***************** */ -#if defined(STM32F4_PI) +#if defined(STM32F4_PI) || (defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)) volatile uint32_t intcount1; volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE]; @@ -612,6 +613,7 @@ void WriteUSART3(const uint8_t* data, uint16_t length) #endif /* ************* UART5 ***************** */ +#if !(defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)) volatile uint32_t intcount5; volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE]; @@ -800,6 +802,7 @@ void WriteUART5(const uint8_t* data, uint16_t length) USART_ITConfig(UART5, USART_IT_TXE, ENABLE); } +#endif ///////////////////////////////////////////////////////////////// void CSerialPort::beginInt(uint8_t n, int speed) @@ -815,7 +818,11 @@ void CSerialPort::beginInt(uint8_t n, int speed) #endif break; case 3U: - InitUART5(speed); + #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) + InitUSART1(speed); + #else + InitUART5(speed); + #endif break; default: break; @@ -834,7 +841,11 @@ int CSerialPort::availableInt(uint8_t n) return AvailUSART2(); #endif case 3U: - return AvailUART5(); + #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) + return AvailUSART1(); + #else + return AvailUART5(); + #endif default: return false; } @@ -852,7 +863,11 @@ uint8_t CSerialPort::readInt(uint8_t n) return ReadUSART2(); #endif case 3U: - return ReadUART5(); + #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) + return ReadUSART1(); + #else + return ReadUART5(); + #endif default: return 0U; } @@ -877,9 +892,15 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool #endif break; case 3U: - WriteUART5(data, length); - if (flush) - TXSerialFlush5(); + #if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER) + WriteUSART1(data, length); + if (flush) + TXSerialFlush1(); + #else + WriteUART5(data, length); + if (flush) + TXSerialFlush5(); + #endif break; default: break;