From 9144ed41ec47e686c3ed9295e9bd2087ff29eac1 Mon Sep 17 00:00:00 2001 From: phl0 Date: Mon, 28 Nov 2016 12:44:45 +0100 Subject: [PATCH 1/3] Correct calibration --- IOTeensy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index eb0bbbb..2485f32 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -91,7 +91,7 @@ void CIO::startInt() ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger ADC0_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples - while ((ADC0_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration + while ((ADC0_SC3 & ADC_SC3_CAL) != ADC_SC3_CAL) // Wait for calibration ; uint16_t sum0 = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + // Plus side gain @@ -111,7 +111,7 @@ void CIO::startInt() ADC1_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger ADC1_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples - while ((ADC1_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration + while ((ADC1_SC3 & ADC_SC3_CAL) != ADC_SC3_CAL) // Wait for calibration ; uint16_t sum1 = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + // Plus side gain From 4584b20c451a0609f243f4c30f326fecf7438463 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Mon, 28 Nov 2016 14:02:21 +0000 Subject: [PATCH 2/3] Make calibration into a seperate step. --- IOTeensy.cpp | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 2485f32..49e8a03 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -75,22 +75,15 @@ void CIO::initInt() void CIO::startInt() { - if ((ADC0_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) - io.interrupt(0U); - -#if defined(SEND_RSSI_DATA) - if ((ADC1_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) - io.interrupt(1U); -#endif - // Initialise ADC0 SIM_SCGC6 |= SIM_SCGC6_ADC0; ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger - ADC0_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples + ADC0_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples + ADC0_SC3 = ADC_SC3_CAL; while ((ADC0_SC3 & ADC_SC3_CAL) != ADC_SC3_CAL) // Wait for calibration ; @@ -109,8 +102,9 @@ void CIO::startInt() ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb ADC1_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger - ADC1_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples + ADC1_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples + ADC1_SC3 = ADC_SC3_CAL; while ((ADC1_SC3 & ADC_SC3_CAL) != ADC_SC3_CAL) // Wait for calibration ; From 91b4dddd8b873d5b2ea996f8bc421d94c3ff18a7 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Mon, 28 Nov 2016 16:20:51 +0000 Subject: [PATCH 3/3] Disable ADC clocks. --- IOTeensy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 49e8a03..f99b1dd 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -76,7 +76,7 @@ void CIO::initInt() void CIO::startInt() { // Initialise ADC0 - SIM_SCGC6 |= SIM_SCGC6_ADC0; + // SIM_SCGC6 |= SIM_SCGC6_ADC0; ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb @@ -97,7 +97,7 @@ void CIO::startInt() #if defined(SEND_RSSI_DATA) // Initialise ADC1 - SIM_SCGC3 |= SIM_SCGC3_ADC1; + // SIM_SCGC3 |= SIM_SCGC3_ADC1; ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP; ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb