From 88409dccd2fbd6f0b012a69f748cbf0fd327ebac Mon Sep 17 00:00:00 2001 From: Andy Date: Thu, 12 Jul 2018 00:59:08 -0400 Subject: [PATCH 1/3] Add temporary POCSAG pin definitions for F446 and F722 --- IOSTM.cpp | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/IOSTM.cpp b/IOSTM.cpp index 6557496..b8aae13 100644 --- a/IOSTM.cpp +++ b/IOSTM.cpp @@ -113,6 +113,7 @@ DMR PC8 output YSF PA8 output P25 PC9 output NXDN PB1 output +POCSAG PB12 output RX PA0 analog input RSSI PA7 analog input @@ -145,6 +146,10 @@ EXT_CLK PA15 input #define PORT_NXDN GPIOB #define RCC_Per_NXDN RCC_AHB1Periph_GPIOB +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_7 #define PORT_DSTAR GPIOC #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOC @@ -188,6 +193,7 @@ DMR PC8 output YSF PA8 output P25 PC9 output NXDN PB1 output +POCSAG PB12 output RX PA0 analog input RSSI PA7 analog input @@ -220,6 +226,10 @@ EXT_CLK PA15 input #define PORT_NXDN GPIOB #define RCC_Per_NXDN RCC_AHB1Periph_GPIOB +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_7 #define PORT_DSTAR GPIOC #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOC @@ -263,6 +273,7 @@ DMR PC8 output YSF PA8 output P25 PC9 output NXDN PB1 output +POCSAG PB12 output RX PA0 analog input RSSI PA7 analog input @@ -295,6 +306,10 @@ EXT_CLK PA15 input #define PORT_NXDN GPIOB #define RCC_Per_NXDN RCC_AHB1Periph_GPIOB +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_7 #define PORT_DSTAR GPIOC #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOC @@ -372,7 +387,7 @@ EXT_CLK PA15 input #define RCC_Per_NXDN RCC_AHB1Periph_GPIOB #define PIN_POCSAG GPIO_Pin_12 -#define PORT_NXDN GPIOB +#define PORT_POCSAG GPIOB #define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB #define PIN_DSTAR GPIO_Pin_7 @@ -420,6 +435,7 @@ DMR PB4 output CN10 Pin27 YSF PB5 output CN10 Pin29 P25 PB3 output CN10 Pin31 NXDN PA10 output CN10 Pin33 +POCSAG PB12 output MDSTAR PC4 output CN10 Pin34 MDMR PC5 output CN10 Pin6 @@ -458,6 +474,10 @@ EXT_CLK PA15 input CN7 Pin17 #define PORT_NXDN GPIOA #define RCC_Per_NXDN RCC_AHB1Periph_GPIOA +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_10 #define PORT_DSTAR GPIOB #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOB @@ -523,6 +543,7 @@ DMR PA4 output CN8 Pin3 YSF PB0 output CN8 Pin4 P25 PC1 output CN8 Pin5 NXDN PA3 output CN9 Pin1 +POCSAG PB12 output RX PA0 analog input CN8 Pin1 RSSI PC0 analog input CN8 Pin6 @@ -555,6 +576,10 @@ EXT_CLK PB8 input CN5 Pin10 #define PORT_NXDN GPIOA #define RCC_Per_NXDN RCC_AHB1Periph_GPIOA +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_1 #define PORT_DSTAR GPIOA #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOA From 0aea9aef38d71b476ba031506a5b67c838991d11 Mon Sep 17 00:00:00 2001 From: phl0 Date: Thu, 12 Jul 2018 07:16:40 +0200 Subject: [PATCH 2/3] Correct typo in Makefile --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index bb8e3b5..2c5e005 100644 --- a/Makefile +++ b/Makefile @@ -148,7 +148,7 @@ CXXFLAGS=-Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -f LDFLAGS=-Os --specs=nano.specs # Build Rules -.PHONY: all release dis pi pi_f722 f4m nucleo f767 dvm clean +.PHONY: all release dis pi pi-f722 f4m nucleo f767 dvm clean # Default target: Nucleo-64 F446RE board all: nucleo From d62c945887b1faddce2a3f2f80067da2a4eb4d51 Mon Sep 17 00:00:00 2001 From: phl0 Date: Thu, 12 Jul 2018 07:36:44 +0200 Subject: [PATCH 3/3] Add POCSAG pin defs for f767 target --- IOSTM.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/IOSTM.cpp b/IOSTM.cpp index b8aae13..701ebfa 100644 --- a/IOSTM.cpp +++ b/IOSTM.cpp @@ -627,6 +627,7 @@ DMR PB4 output CN12 Pin27 YSF PB5 output CN12 Pin29 P25 PB3 output CN12 Pin31 NXDN PA10 output CN12 Pin33 +POCSAG PB12 output CN12 Pin16 MDSTAR PC4 output CN12 Pin34 MDMR PC5 output CN12 Pin6 @@ -665,6 +666,10 @@ EXT_CLK PA15 input CN11 Pin17 #define PORT_NXDN GPIOA #define RCC_Per_NXDN RCC_AHB1Periph_GPIOA +#define PIN_POCSAG GPIO_Pin_12 +#define PORT_POCSAG GPIOB +#define RCC_Per_POCSAG RCC_AHB1Periph_GPIOB + #define PIN_DSTAR GPIO_Pin_10 #define PORT_DSTAR GPIOB #define RCC_Per_DSTAR RCC_AHB1Periph_GPIOB