From 3ec929ff5272d2df6f1356ffcf6e4e6b59cec6f5 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Mon, 12 Dec 2016 15:29:41 +0000 Subject: [PATCH 1/7] Remove RSSI ADC startup software interrupt. --- IOTeensy.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 632dccf..bfd419c 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -117,7 +117,6 @@ void CIO::startInt() sum1 = (sum1 / 2U) | 0x8000U; ADC1_PG = sum1; - ADC1_SC1A = ADC_SC1_AIEN | PIN_RSSI; // Enable ADC interrupt, use A2 NVIC_ENABLE_IRQ(IRQ_ADC1); #endif From f831b64518a6da1a45c320ee935e3e57440d3a1c Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Tue, 13 Dec 2016 09:45:10 +0000 Subject: [PATCH 2/7] LPTMR changes based on PJRC Teensy forum feedback from manitou. --- IOTeensy.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index bfd419c..7572ccd 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -131,9 +131,7 @@ void CIO::startInt() LPTMR0_CSR = 0; // Disable LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter LPTMR0_CMR = EXTERNAL_OSC / 24000; - LPTMR0_CSR = LPTMR_CSR_TIE | // Interrupt Enable - LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13 - LPTMR_CSR_TFC | // Free-Running Counter + LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13 LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable #else From 2747e2979d47f687bedaed3a6b62a1da1e49e44c Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 14 Dec 2016 09:12:59 +0000 Subject: [PATCH 3/7] Enable ADC0 pre-trigger via the LPTMR to match the PDB. --- IOTeensy.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 7572ccd..4afe045 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -123,6 +123,7 @@ void CIO::startInt() #if defined(EXTERNAL_OSC) // Set ADC0 to trigger from the LPTMR at 24 kHz SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger + SIM_SOPT7_ADC0PRETRGSEL | // Enable ADC0 pre-trigger SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0 CORE_PIN13_CONFIG = PORT_PCR_MUX(3); From dca6dd35dc27d48f593d1cfdff5d35e2dfb95968 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 14 Dec 2016 13:24:08 +0000 Subject: [PATCH 4/7] Reduce the value of the LPTMR CMR by one. --- IOTeensy.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 4afe045..5e3d24e 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -131,7 +131,7 @@ void CIO::startInt() SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access LPTMR0_CSR = 0; // Disable LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter - LPTMR0_CMR = EXTERNAL_OSC / 24000; + LPTMR0_CMR = (EXTERNAL_OSC / 24000) - 1; // Frequency divided by CMR + 1 LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13 LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable From 2fad06093f7df9f35d922d4f743c6299b888b49e Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Thu, 15 Dec 2016 10:22:07 +0000 Subject: [PATCH 5/7] Tweak the PDB timer period. --- IOTeensy.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 5e3d24e..18d9d4d 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -138,7 +138,7 @@ void CIO::startInt() #else // Setup PDB for ADC0 at 24 kHz SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock - PDB0_MOD = F_BUS / 24000; // Timer period + PDB0_MOD = (F_BUS / 24000) - 1; // Timer period - 1 PDB0_IDLY = 0; // Interrupt delay PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0 PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode From 5d0d2d0bd951125cfe00725866f161707675b519 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Tue, 20 Dec 2016 08:42:56 +0000 Subject: [PATCH 6/7] Fix calibration setting. --- IOTeensy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 18d9d4d..8f8ac27 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -87,7 +87,7 @@ void CIO::startInt() ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger ADC0_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples - ADC0_SC3 = ADC_SC3_CAL; + ADC0_SC3 |= ADC_SC3_CAL; while (ADC0_SC3 & ADC_SC3_CAL) // Wait for calibration ; @@ -108,7 +108,7 @@ void CIO::startInt() ADC1_SC2 = ADC_SC2_REFSEL(1); // Voltage ref internal, software trigger ADC1_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples - ADC1_SC3 = ADC_SC3_CAL; + ADC1_SC3 |= ADC_SC3_CAL; while (ADC1_SC3 & ADC_SC3_CAL) // Wait for calibration ; From 0585d817cb631e6ce3bd7f8307e78050da026883 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Tue, 20 Dec 2016 14:21:36 +0000 Subject: [PATCH 7/7] Change Teensy RSSI input pins. --- IOTeensy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IOTeensy.cpp b/IOTeensy.cpp index 8f8ac27..7bb40f0 100644 --- a/IOTeensy.cpp +++ b/IOTeensy.cpp @@ -34,8 +34,8 @@ #define PIN_DMR 10 #define PIN_YSF 11 #define PIN_P25 12 -#define PIN_ADC 5 // A0, Pin 14 -#define PIN_RSSI 8 // A2, Pin 16 +#define PIN_ADC 5 // A0, Pin 14 +#define PIN_RSSI 4 // Teensy 3.5/3.6, A16, Pin 35. Teensy 3.1/3.2, A17, Pin 28 #define PDB_CHnC1_TOS 0x0100 #define PDB_CHnC1_EN 0x0001